NEMAllNativeTemplate-win.cpp.h

Last change on this file was 108545, checked in by vboxsync, 3 weeks ago
VMM/NEM/win: Workaround for SMP TSC drift introduced in NEMHCResumeCpuTickOnAll on startup and resume (unpause). bugref:10876 ticketref:22334
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 144.6 KB

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1	/* $Id: NEMAllNativeTemplate-win.cpp.h 108545 2025-03-13 08:43:30Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, Windows code template ring-0/3.
4	*/
5
6	/*
7	* Copyright (C) 2018-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef IN_RING3
29	# error "This is ring-3 only now"
30	#endif
31
32
33	/*********************************************************************************************************************************
34	* Defined Constants And Macros *
35	*********************************************************************************************************************************/
36	/** Copy back a segment from hyper-V. */
37	#define NEM_WIN_COPY_BACK_SEG(a_Dst, a_Src) \
38	do { \
39	(a_Dst).u64Base = (a_Src).Base; \
40	(a_Dst).u32Limit = (a_Src).Limit; \
41	(a_Dst).ValidSel = (a_Dst).Sel = (a_Src).Selector; \
42	(a_Dst).Attr.u = (a_Src).Attributes; \
43	(a_Dst).fFlags = CPUMSELREG_FLAGS_VALID; \
44	} while (0)
45
46	/** @def NEMWIN_ASSERT_MSG_REG_VAL
47	* Asserts the correctness of a register value in a message/context.
48	*/
49	#if 0
50	# define NEMWIN_NEED_GET_REGISTER
51	# define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, a_Expr, a_Msg) \
52	do { \
53	WHV_REGISTER_VALUE TmpVal; \
54	nemR3WinGetRegister(a_pVCpu, a_enmReg, &TmpVal); \
55	AssertMsg(a_Expr, a_Msg); \
56	} while (0)
57	#else
58	# define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, a_Expr, a_Msg) do { } while (0)
59	#endif
60
61	/** @def NEMWIN_ASSERT_MSG_REG_VAL
62	* Asserts the correctness of a 64-bit register value in a message/context.
63	*/
64	#define NEMWIN_ASSERT_MSG_REG_VAL64(a_pVCpu, a_enmReg, a_u64Val) \
65	NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, (a_u64Val) == TmpVal.Reg64, \
66	(#a_u64Val "=%#RX64, expected %#RX64\n", (a_u64Val), TmpVal.Reg64))
67	/** @def NEMWIN_ASSERT_MSG_REG_VAL
68	* Asserts the correctness of a segment register value in a message/context.
69	*/
70	#define NEMWIN_ASSERT_MSG_REG_SEG(a_pVCpu, a_enmReg, a_SReg) \
71	NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, \
72	(a_SReg).Base == TmpVal.Segment.Base \
73	&& (a_SReg).Limit == TmpVal.Segment.Limit \
74	&& (a_SReg).Selector == TmpVal.Segment.Selector \
75	&& (a_SReg).Attributes == TmpVal.Segment.Attributes, \
76	( #a_SReg "=%#RX16 {%#RX64 LB %#RX32,%#RX16} expected %#RX16 {%#RX64 LB %#RX32,%#RX16}\n", \
77	(a_SReg).Selector, (a_SReg).Base, (a_SReg).Limit, (a_SReg).Attributes, \
78	TmpVal.Segment.Selector, TmpVal.Segment.Base, TmpVal.Segment.Limit, TmpVal.Segment.Attributes))
79
80
81	#ifndef NTDDI_WIN10_19H1
82	# define NTDDI_WIN10_19H1 0x0a000007
83	#endif
84
85	/** WHvRegisterPendingEvent0 was renamed to WHvRegisterPendingEvent between
86	* SDK 17134 and 18362. */
87	#if WDK_NTDDI_VERSION < NTDDI_WIN10_19H1
88	# define WHvRegisterPendingEvent WHvRegisterPendingEvent0
89	#endif
90
91
92	/*********************************************************************************************************************************
93	* Global Variables *
94	*********************************************************************************************************************************/
95	/** NEM_WIN_PAGE_STATE_XXX names. */
96	NEM_TMPL_STATIC const char * const g_apszPageStates[4] = { "not-set", "unmapped", "readable", "writable" };
97
98	/** HV_INTERCEPT_ACCESS_TYPE names. */
99	static const char * const g_apszHvInterceptAccessTypes[4] = { "read", "write", "exec", "!undefined!" };
100
101
102	/*********************************************************************************************************************************
103	* Internal Functions *
104	*********************************************************************************************************************************/
105	NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
106	uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged);
107
108
109
110	NEM_TMPL_STATIC int nemHCWinCopyStateToHyperV(PVMCC pVM, PVMCPUCC pVCpu)
111	{
112	/*
113	* The following is very similar to what nemR0WinExportState() does.
114	*/
115	WHV_REGISTER_NAME aenmNames[128];
116	WHV_REGISTER_VALUE aValues[128];
117
118	uint64_t const fWhat = ~pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK);
119	if ( !fWhat
120	&& pVCpu->nem.s.fCurrentInterruptWindows == pVCpu->nem.s.fDesiredInterruptWindows)
121	return VINF_SUCCESS;
122	uintptr_t iReg = 0;
123
124	#define ADD_REG64(a_enmName, a_uValue) do { \
125	aenmNames[iReg] = (a_enmName); \
126	aValues[iReg].Reg128.High64 = 0; \
127	aValues[iReg].Reg64 = (a_uValue); \
128	iReg++; \
129	} while (0)
130	#define ADD_REG128(a_enmName, a_uValueLo, a_uValueHi) do { \
131	aenmNames[iReg] = (a_enmName); \
132	aValues[iReg].Reg128.Low64 = (a_uValueLo); \
133	aValues[iReg].Reg128.High64 = (a_uValueHi); \
134	iReg++; \
135	} while (0)
136
137	/* GPRs */
138	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
139	{
140	if (fWhat & CPUMCTX_EXTRN_RAX)
141	ADD_REG64(WHvX64RegisterRax, pVCpu->cpum.GstCtx.rax);
142	if (fWhat & CPUMCTX_EXTRN_RCX)
143	ADD_REG64(WHvX64RegisterRcx, pVCpu->cpum.GstCtx.rcx);
144	if (fWhat & CPUMCTX_EXTRN_RDX)
145	ADD_REG64(WHvX64RegisterRdx, pVCpu->cpum.GstCtx.rdx);
146	if (fWhat & CPUMCTX_EXTRN_RBX)
147	ADD_REG64(WHvX64RegisterRbx, pVCpu->cpum.GstCtx.rbx);
148	if (fWhat & CPUMCTX_EXTRN_RSP)
149	ADD_REG64(WHvX64RegisterRsp, pVCpu->cpum.GstCtx.rsp);
150	if (fWhat & CPUMCTX_EXTRN_RBP)
151	ADD_REG64(WHvX64RegisterRbp, pVCpu->cpum.GstCtx.rbp);
152	if (fWhat & CPUMCTX_EXTRN_RSI)
153	ADD_REG64(WHvX64RegisterRsi, pVCpu->cpum.GstCtx.rsi);
154	if (fWhat & CPUMCTX_EXTRN_RDI)
155	ADD_REG64(WHvX64RegisterRdi, pVCpu->cpum.GstCtx.rdi);
156	if (fWhat & CPUMCTX_EXTRN_R8_R15)
157	{
158	ADD_REG64(WHvX64RegisterR8, pVCpu->cpum.GstCtx.r8);
159	ADD_REG64(WHvX64RegisterR9, pVCpu->cpum.GstCtx.r9);
160	ADD_REG64(WHvX64RegisterR10, pVCpu->cpum.GstCtx.r10);
161	ADD_REG64(WHvX64RegisterR11, pVCpu->cpum.GstCtx.r11);
162	ADD_REG64(WHvX64RegisterR12, pVCpu->cpum.GstCtx.r12);
163	ADD_REG64(WHvX64RegisterR13, pVCpu->cpum.GstCtx.r13);
164	ADD_REG64(WHvX64RegisterR14, pVCpu->cpum.GstCtx.r14);
165	ADD_REG64(WHvX64RegisterR15, pVCpu->cpum.GstCtx.r15);
166	}
167	}
168
169	/* RIP & Flags */
170	if (fWhat & CPUMCTX_EXTRN_RIP)
171	ADD_REG64(WHvX64RegisterRip, pVCpu->cpum.GstCtx.rip);
172	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
173	ADD_REG64(WHvX64RegisterRflags, pVCpu->cpum.GstCtx.rflags.u);
174
175	/* Segments */
176	#define ADD_SEG(a_enmName, a_SReg) \
177	do { \
178	aenmNames[iReg] = a_enmName; \
179	aValues[iReg].Segment.Base = (a_SReg).u64Base; \
180	aValues[iReg].Segment.Limit = (a_SReg).u32Limit; \
181	aValues[iReg].Segment.Selector = (a_SReg).Sel; \
182	aValues[iReg].Segment.Attributes = (a_SReg).Attr.u; \
183	iReg++; \
184	} while (0)
185	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
186	{
187	if (fWhat & CPUMCTX_EXTRN_ES)
188	ADD_SEG(WHvX64RegisterEs, pVCpu->cpum.GstCtx.es);
189	if (fWhat & CPUMCTX_EXTRN_CS)
190	ADD_SEG(WHvX64RegisterCs, pVCpu->cpum.GstCtx.cs);
191	if (fWhat & CPUMCTX_EXTRN_SS)
192	ADD_SEG(WHvX64RegisterSs, pVCpu->cpum.GstCtx.ss);
193	if (fWhat & CPUMCTX_EXTRN_DS)
194	ADD_SEG(WHvX64RegisterDs, pVCpu->cpum.GstCtx.ds);
195	if (fWhat & CPUMCTX_EXTRN_FS)
196	ADD_SEG(WHvX64RegisterFs, pVCpu->cpum.GstCtx.fs);
197	if (fWhat & CPUMCTX_EXTRN_GS)
198	ADD_SEG(WHvX64RegisterGs, pVCpu->cpum.GstCtx.gs);
199	}
200
201	/* Descriptor tables & task segment. */
202	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
203	{
204	if (fWhat & CPUMCTX_EXTRN_LDTR)
205	ADD_SEG(WHvX64RegisterLdtr, pVCpu->cpum.GstCtx.ldtr);
206	if (fWhat & CPUMCTX_EXTRN_TR)
207	ADD_SEG(WHvX64RegisterTr, pVCpu->cpum.GstCtx.tr);
208	if (fWhat & CPUMCTX_EXTRN_IDTR)
209	{
210	aenmNames[iReg] = WHvX64RegisterIdtr;
211	aValues[iReg].Table.Limit = pVCpu->cpum.GstCtx.idtr.cbIdt;
212	aValues[iReg].Table.Base = pVCpu->cpum.GstCtx.idtr.pIdt;
213	iReg++;
214	}
215	if (fWhat & CPUMCTX_EXTRN_GDTR)
216	{
217	aenmNames[iReg] = WHvX64RegisterGdtr;
218	aValues[iReg].Table.Limit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
219	aValues[iReg].Table.Base = pVCpu->cpum.GstCtx.gdtr.pGdt;
220	iReg++;
221	}
222	}
223
224	/* Control registers. */
225	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
226	{
227	if (fWhat & CPUMCTX_EXTRN_CR0)
228	ADD_REG64(WHvX64RegisterCr0, pVCpu->cpum.GstCtx.cr0);
229	if (fWhat & CPUMCTX_EXTRN_CR2)
230	ADD_REG64(WHvX64RegisterCr2, pVCpu->cpum.GstCtx.cr2);
231	if (fWhat & CPUMCTX_EXTRN_CR3)
232	ADD_REG64(WHvX64RegisterCr3, pVCpu->cpum.GstCtx.cr3);
233	if (fWhat & CPUMCTX_EXTRN_CR4)
234	ADD_REG64(WHvX64RegisterCr4, pVCpu->cpum.GstCtx.cr4);
235	}
236	if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
237	ADD_REG64(WHvX64RegisterCr8, CPUMGetGuestCR8(pVCpu));
238
239	/* Debug registers. */
240	/** @todo fixme. Figure out what the hyper-v version of KVM_SET_GUEST_DEBUG would be. */
241	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
242	{
243	ADD_REG64(WHvX64RegisterDr0, pVCpu->cpum.GstCtx.dr[0]); // CPUMGetHyperDR0(pVCpu));
244	ADD_REG64(WHvX64RegisterDr1, pVCpu->cpum.GstCtx.dr[1]); // CPUMGetHyperDR1(pVCpu));
245	ADD_REG64(WHvX64RegisterDr2, pVCpu->cpum.GstCtx.dr[2]); // CPUMGetHyperDR2(pVCpu));
246	ADD_REG64(WHvX64RegisterDr3, pVCpu->cpum.GstCtx.dr[3]); // CPUMGetHyperDR3(pVCpu));
247	}
248	if (fWhat & CPUMCTX_EXTRN_DR6)
249	ADD_REG64(WHvX64RegisterDr6, pVCpu->cpum.GstCtx.dr[6]); // CPUMGetHyperDR6(pVCpu));
250	if (fWhat & CPUMCTX_EXTRN_DR7)
251	ADD_REG64(WHvX64RegisterDr7, pVCpu->cpum.GstCtx.dr[7]); // CPUMGetHyperDR7(pVCpu));
252
253	/* Floating point state. */
254	if (fWhat & CPUMCTX_EXTRN_X87)
255	{
256	ADD_REG128(WHvX64RegisterFpMmx0, pVCpu->cpum.GstCtx.XState.x87.aRegs[0].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[0].au64[1]);
257	ADD_REG128(WHvX64RegisterFpMmx1, pVCpu->cpum.GstCtx.XState.x87.aRegs[1].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[1].au64[1]);
258	ADD_REG128(WHvX64RegisterFpMmx2, pVCpu->cpum.GstCtx.XState.x87.aRegs[2].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[2].au64[1]);
259	ADD_REG128(WHvX64RegisterFpMmx3, pVCpu->cpum.GstCtx.XState.x87.aRegs[3].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[3].au64[1]);
260	ADD_REG128(WHvX64RegisterFpMmx4, pVCpu->cpum.GstCtx.XState.x87.aRegs[4].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[4].au64[1]);
261	ADD_REG128(WHvX64RegisterFpMmx5, pVCpu->cpum.GstCtx.XState.x87.aRegs[5].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[5].au64[1]);
262	ADD_REG128(WHvX64RegisterFpMmx6, pVCpu->cpum.GstCtx.XState.x87.aRegs[6].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[6].au64[1]);
263	ADD_REG128(WHvX64RegisterFpMmx7, pVCpu->cpum.GstCtx.XState.x87.aRegs[7].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[7].au64[1]);
264
265	aenmNames[iReg] = WHvX64RegisterFpControlStatus;
266	aValues[iReg].FpControlStatus.FpControl = pVCpu->cpum.GstCtx.XState.x87.FCW;
267	aValues[iReg].FpControlStatus.FpStatus = pVCpu->cpum.GstCtx.XState.x87.FSW;
268	aValues[iReg].FpControlStatus.FpTag = pVCpu->cpum.GstCtx.XState.x87.FTW;
269	aValues[iReg].FpControlStatus.Reserved = pVCpu->cpum.GstCtx.XState.x87.FTW >> 8;
270	aValues[iReg].FpControlStatus.LastFpOp = pVCpu->cpum.GstCtx.XState.x87.FOP;
271	aValues[iReg].FpControlStatus.LastFpRip = (pVCpu->cpum.GstCtx.XState.x87.FPUIP)
272	\| ((uint64_t)pVCpu->cpum.GstCtx.XState.x87.CS << 32)
273	\| ((uint64_t)pVCpu->cpum.GstCtx.XState.x87.Rsrvd1 << 48);
274	iReg++;
275
276	aenmNames[iReg] = WHvX64RegisterXmmControlStatus;
277	aValues[iReg].XmmControlStatus.LastFpRdp = (pVCpu->cpum.GstCtx.XState.x87.FPUDP)
278	\| ((uint64_t)pVCpu->cpum.GstCtx.XState.x87.DS << 32)
279	\| ((uint64_t)pVCpu->cpum.GstCtx.XState.x87.Rsrvd2 << 48);
280	aValues[iReg].XmmControlStatus.XmmStatusControl = pVCpu->cpum.GstCtx.XState.x87.MXCSR;
281	aValues[iReg].XmmControlStatus.XmmStatusControlMask = pVCpu->cpum.GstCtx.XState.x87.MXCSR_MASK; /** @todo ??? (Isn't this an output field?) */
282	iReg++;
283	}
284
285	/* Vector state. */
286	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
287	{
288	ADD_REG128(WHvX64RegisterXmm0, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 0].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 0].uXmm.s.Hi);
289	ADD_REG128(WHvX64RegisterXmm1, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 1].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 1].uXmm.s.Hi);
290	ADD_REG128(WHvX64RegisterXmm2, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 2].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 2].uXmm.s.Hi);
291	ADD_REG128(WHvX64RegisterXmm3, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 3].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 3].uXmm.s.Hi);
292	ADD_REG128(WHvX64RegisterXmm4, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 4].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 4].uXmm.s.Hi);
293	ADD_REG128(WHvX64RegisterXmm5, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 5].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 5].uXmm.s.Hi);
294	ADD_REG128(WHvX64RegisterXmm6, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 6].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 6].uXmm.s.Hi);
295	ADD_REG128(WHvX64RegisterXmm7, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 7].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 7].uXmm.s.Hi);
296	ADD_REG128(WHvX64RegisterXmm8, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 8].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 8].uXmm.s.Hi);
297	ADD_REG128(WHvX64RegisterXmm9, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 9].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 9].uXmm.s.Hi);
298	ADD_REG128(WHvX64RegisterXmm10, pVCpu->cpum.GstCtx.XState.x87.aXMM[10].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[10].uXmm.s.Hi);
299	ADD_REG128(WHvX64RegisterXmm11, pVCpu->cpum.GstCtx.XState.x87.aXMM[11].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[11].uXmm.s.Hi);
300	ADD_REG128(WHvX64RegisterXmm12, pVCpu->cpum.GstCtx.XState.x87.aXMM[12].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[12].uXmm.s.Hi);
301	ADD_REG128(WHvX64RegisterXmm13, pVCpu->cpum.GstCtx.XState.x87.aXMM[13].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[13].uXmm.s.Hi);
302	ADD_REG128(WHvX64RegisterXmm14, pVCpu->cpum.GstCtx.XState.x87.aXMM[14].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[14].uXmm.s.Hi);
303	ADD_REG128(WHvX64RegisterXmm15, pVCpu->cpum.GstCtx.XState.x87.aXMM[15].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[15].uXmm.s.Hi);
304	}
305
306	/* MSRs */
307	// WHvX64RegisterTsc - don't touch
308	if (fWhat & CPUMCTX_EXTRN_EFER)
309	ADD_REG64(WHvX64RegisterEfer, pVCpu->cpum.GstCtx.msrEFER);
310	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
311	ADD_REG64(WHvX64RegisterKernelGsBase, pVCpu->cpum.GstCtx.msrKERNELGSBASE);
312	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
313	{
314	ADD_REG64(WHvX64RegisterSysenterCs, pVCpu->cpum.GstCtx.SysEnter.cs);
315	ADD_REG64(WHvX64RegisterSysenterEip, pVCpu->cpum.GstCtx.SysEnter.eip);
316	ADD_REG64(WHvX64RegisterSysenterEsp, pVCpu->cpum.GstCtx.SysEnter.esp);
317	}
318	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
319	{
320	ADD_REG64(WHvX64RegisterStar, pVCpu->cpum.GstCtx.msrSTAR);
321	ADD_REG64(WHvX64RegisterLstar, pVCpu->cpum.GstCtx.msrLSTAR);
322	ADD_REG64(WHvX64RegisterCstar, pVCpu->cpum.GstCtx.msrCSTAR);
323	ADD_REG64(WHvX64RegisterSfmask, pVCpu->cpum.GstCtx.msrSFMASK);
324	}
325	if (fWhat & (CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
326	{
327	PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
328	if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
329	ADD_REG64(WHvX64RegisterTscAux, pCtxMsrs->msr.TscAux);
330	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
331	{
332	ADD_REG64(WHvX64RegisterApicBase, PDMApicGetBaseMsrNoCheck(pVCpu));
333	ADD_REG64(WHvX64RegisterPat, pVCpu->cpum.GstCtx.msrPAT);
334	#if 0 /** @todo check if WHvX64RegisterMsrMtrrCap works here... */
335	ADD_REG64(WHvX64RegisterMsrMtrrCap, CPUMGetGuestIa32MtrrCap(pVCpu));
336	#endif
337	ADD_REG64(WHvX64RegisterMsrMtrrDefType, pCtxMsrs->msr.MtrrDefType);
338	ADD_REG64(WHvX64RegisterMsrMtrrFix64k00000, pCtxMsrs->msr.MtrrFix64K_00000);
339	ADD_REG64(WHvX64RegisterMsrMtrrFix16k80000, pCtxMsrs->msr.MtrrFix16K_80000);
340	ADD_REG64(WHvX64RegisterMsrMtrrFix16kA0000, pCtxMsrs->msr.MtrrFix16K_A0000);
341	ADD_REG64(WHvX64RegisterMsrMtrrFix4kC0000, pCtxMsrs->msr.MtrrFix4K_C0000);
342	ADD_REG64(WHvX64RegisterMsrMtrrFix4kC8000, pCtxMsrs->msr.MtrrFix4K_C8000);
343	ADD_REG64(WHvX64RegisterMsrMtrrFix4kD0000, pCtxMsrs->msr.MtrrFix4K_D0000);
344	ADD_REG64(WHvX64RegisterMsrMtrrFix4kD8000, pCtxMsrs->msr.MtrrFix4K_D8000);
345	ADD_REG64(WHvX64RegisterMsrMtrrFix4kE0000, pCtxMsrs->msr.MtrrFix4K_E0000);
346	ADD_REG64(WHvX64RegisterMsrMtrrFix4kE8000, pCtxMsrs->msr.MtrrFix4K_E8000);
347	ADD_REG64(WHvX64RegisterMsrMtrrFix4kF0000, pCtxMsrs->msr.MtrrFix4K_F0000);
348	ADD_REG64(WHvX64RegisterMsrMtrrFix4kF8000, pCtxMsrs->msr.MtrrFix4K_F8000);
349	if (pVM->nem.s.fDoIa32SpecCtrl)
350	ADD_REG64(WHvX64RegisterSpecCtrl, pCtxMsrs->msr.SpecCtrl);
351
352	#if 0 /** @todo these registers aren't available? Might explain something.. .*/
353	const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pVM);
354	if (enmCpuVendor != CPUMCPUVENDOR_AMD)
355	{
356	ADD_REG64(HvX64RegisterIa32MiscEnable, pCtxMsrs->msr.MiscEnable);
357	ADD_REG64(HvX64RegisterIa32FeatureControl, CPUMGetGuestIa32FeatureControl(pVCpu));
358	}
359	#endif
360	}
361	}
362
363	/* event injection (clear it). */
364	if (fWhat & CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)
365	ADD_REG64(WHvRegisterPendingInterruption, 0);
366
367	if (!pVM->nem.s.fLocalApicEmulation)
368	{
369	/* Interruptibility state. This can get a little complicated since we get
370	half of the state via HV_X64_VP_EXECUTION_STATE. */
371	if ( (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
372	== (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI) )
373	{
374	ADD_REG64(WHvRegisterInterruptState, 0);
375	if (CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
376	aValues[iReg - 1].InterruptState.InterruptShadow = 1;
377	aValues[iReg - 1].InterruptState.NmiMasked = CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx);
378	}
379	else if (fWhat & CPUMCTX_EXTRN_INHIBIT_INT)
380	{
381	if ( pVCpu->nem.s.fLastInterruptShadow
382	\|\| CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
383	{
384	ADD_REG64(WHvRegisterInterruptState, 0);
385	if (CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
386	aValues[iReg - 1].InterruptState.InterruptShadow = 1;
387	/** @todo Retrieve NMI state, currently assuming it's zero. (yes this may happen on I/O) */
388	//if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
389	// aValues[iReg - 1].InterruptState.NmiMasked = 1;
390	}
391	}
392	else
393	Assert(!(fWhat & CPUMCTX_EXTRN_INHIBIT_NMI));
394
395	/* Interrupt windows. Always set if active as Hyper-V seems to be forgetful. */
396	uint8_t const fDesiredIntWin = pVCpu->nem.s.fDesiredInterruptWindows;
397	if ( fDesiredIntWin
398	\|\| pVCpu->nem.s.fCurrentInterruptWindows != fDesiredIntWin)
399	{
400	pVCpu->nem.s.fCurrentInterruptWindows = pVCpu->nem.s.fDesiredInterruptWindows;
401	Log8(("Setting WHvX64RegisterDeliverabilityNotifications, fDesiredIntWin=%X\n", fDesiredIntWin));
402	ADD_REG64(WHvX64RegisterDeliverabilityNotifications, fDesiredIntWin);
403	Assert(aValues[iReg - 1].DeliverabilityNotifications.NmiNotification == RT_BOOL(fDesiredIntWin & NEM_WIN_INTW_F_NMI));
404	Assert(aValues[iReg - 1].DeliverabilityNotifications.InterruptNotification == RT_BOOL(fDesiredIntWin & NEM_WIN_INTW_F_REGULAR));
405	Assert(aValues[iReg - 1].DeliverabilityNotifications.InterruptPriority == (unsigned)((fDesiredIntWin & NEM_WIN_INTW_F_PRIO_MASK) >> NEM_WIN_INTW_F_PRIO_SHIFT));
406	}
407	}
408	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
409	{
410	Log8(("Setting WHvX64RegisterDeliverabilityNotifications, fDesiredIntWin=%X fPicReadyForInterrupt=%RTbool\n",
411	pVCpu->nem.s.fDesiredInterruptWindows, pVCpu->nem.s.fPicReadyForInterrupt));
412
413	if ( pVCpu->nem.s.fDesiredInterruptWindows
414	&& pVCpu->nem.s.fPicReadyForInterrupt)
415	{
416	ADD_REG64(WHvRegisterPendingEvent, 0);
417
418	uint8_t bInterrupt;
419	int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
420	AssertRC(rc);
421
422	aValues[iReg - 1].Reg64 = 0;
423	aValues[iReg - 1].ExtIntEvent.EventPending = 1;
424	aValues[iReg - 1].ExtIntEvent.EventType = WHvX64PendingEventExtInt;
425	aValues[iReg - 1].ExtIntEvent.Vector = bInterrupt;
426	}
427
428	if (!pVCpu->nem.s.fIrqWindowRegistered)
429	{
430	ADD_REG64(WHvX64RegisterDeliverabilityNotifications, 0);
431	aValues[iReg - 1].DeliverabilityNotifications.InterruptNotification = 1;
432	pVCpu->nem.s.fIrqWindowRegistered = true;
433	}
434	}
435
436	#undef ADD_REG64
437	#undef ADD_REG128
438	#undef ADD_SEG
439
440	/*
441	* Set the registers.
442	*/
443	Assert(iReg < RT_ELEMENTS(aValues));
444	Assert(iReg < RT_ELEMENTS(aenmNames));
445	#ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
446	Log12(("Calling WHvSetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
447	pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues));
448	#endif
449
450	pVCpu->nem.s.fPicReadyForInterrupt = false;
451
452	if (!iReg)
453	return VINF_SUCCESS;
454
455	HRESULT hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues);
456	if (SUCCEEDED(hrc))
457	{
458	pVCpu->cpum.GstCtx.fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK \| CPUMCTX_EXTRN_KEEPER_NEM;
459	return VINF_SUCCESS;
460	}
461	AssertLogRelMsgFailed(("WHvSetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
462	pVM->nem.s.hPartition, pVCpu->idCpu, iReg,
463	hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
464	return VERR_INTERNAL_ERROR;
465	}
466
467
468	NEM_TMPL_STATIC int nemHCWinCopyStateFromHyperV(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
469	{
470	WHV_REGISTER_NAME aenmNames[128];
471
472	fWhat &= pVCpu->cpum.GstCtx.fExtrn;
473	uintptr_t iReg = 0;
474
475	/* GPRs */
476	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
477	{
478	if (fWhat & CPUMCTX_EXTRN_RAX)
479	aenmNames[iReg++] = WHvX64RegisterRax;
480	if (fWhat & CPUMCTX_EXTRN_RCX)
481	aenmNames[iReg++] = WHvX64RegisterRcx;
482	if (fWhat & CPUMCTX_EXTRN_RDX)
483	aenmNames[iReg++] = WHvX64RegisterRdx;
484	if (fWhat & CPUMCTX_EXTRN_RBX)
485	aenmNames[iReg++] = WHvX64RegisterRbx;
486	if (fWhat & CPUMCTX_EXTRN_RSP)
487	aenmNames[iReg++] = WHvX64RegisterRsp;
488	if (fWhat & CPUMCTX_EXTRN_RBP)
489	aenmNames[iReg++] = WHvX64RegisterRbp;
490	if (fWhat & CPUMCTX_EXTRN_RSI)
491	aenmNames[iReg++] = WHvX64RegisterRsi;
492	if (fWhat & CPUMCTX_EXTRN_RDI)
493	aenmNames[iReg++] = WHvX64RegisterRdi;
494	if (fWhat & CPUMCTX_EXTRN_R8_R15)
495	{
496	aenmNames[iReg++] = WHvX64RegisterR8;
497	aenmNames[iReg++] = WHvX64RegisterR9;
498	aenmNames[iReg++] = WHvX64RegisterR10;
499	aenmNames[iReg++] = WHvX64RegisterR11;
500	aenmNames[iReg++] = WHvX64RegisterR12;
501	aenmNames[iReg++] = WHvX64RegisterR13;
502	aenmNames[iReg++] = WHvX64RegisterR14;
503	aenmNames[iReg++] = WHvX64RegisterR15;
504	}
505	}
506
507	/* RIP & Flags */
508	if (fWhat & CPUMCTX_EXTRN_RIP)
509	aenmNames[iReg++] = WHvX64RegisterRip;
510	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
511	aenmNames[iReg++] = WHvX64RegisterRflags;
512
513	/* Segments */
514	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
515	{
516	if (fWhat & CPUMCTX_EXTRN_ES)
517	aenmNames[iReg++] = WHvX64RegisterEs;
518	if (fWhat & CPUMCTX_EXTRN_CS)
519	aenmNames[iReg++] = WHvX64RegisterCs;
520	if (fWhat & CPUMCTX_EXTRN_SS)
521	aenmNames[iReg++] = WHvX64RegisterSs;
522	if (fWhat & CPUMCTX_EXTRN_DS)
523	aenmNames[iReg++] = WHvX64RegisterDs;
524	if (fWhat & CPUMCTX_EXTRN_FS)
525	aenmNames[iReg++] = WHvX64RegisterFs;
526	if (fWhat & CPUMCTX_EXTRN_GS)
527	aenmNames[iReg++] = WHvX64RegisterGs;
528	}
529
530	/* Descriptor tables. */
531	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
532	{
533	if (fWhat & CPUMCTX_EXTRN_LDTR)
534	aenmNames[iReg++] = WHvX64RegisterLdtr;
535	if (fWhat & CPUMCTX_EXTRN_TR)
536	aenmNames[iReg++] = WHvX64RegisterTr;
537	if (fWhat & CPUMCTX_EXTRN_IDTR)
538	aenmNames[iReg++] = WHvX64RegisterIdtr;
539	if (fWhat & CPUMCTX_EXTRN_GDTR)
540	aenmNames[iReg++] = WHvX64RegisterGdtr;
541	}
542
543	/* Control registers. */
544	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
545	{
546	if (fWhat & CPUMCTX_EXTRN_CR0)
547	aenmNames[iReg++] = WHvX64RegisterCr0;
548	if (fWhat & CPUMCTX_EXTRN_CR2)
549	aenmNames[iReg++] = WHvX64RegisterCr2;
550	if (fWhat & CPUMCTX_EXTRN_CR3)
551	aenmNames[iReg++] = WHvX64RegisterCr3;
552	if (fWhat & CPUMCTX_EXTRN_CR4)
553	aenmNames[iReg++] = WHvX64RegisterCr4;
554	}
555	if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
556	aenmNames[iReg++] = WHvX64RegisterCr8;
557
558	/* Debug registers. */
559	if (fWhat & CPUMCTX_EXTRN_DR7)
560	aenmNames[iReg++] = WHvX64RegisterDr7;
561	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
562	{
563	if (!(fWhat & CPUMCTX_EXTRN_DR7) && (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_DR7))
564	{
565	fWhat \|= CPUMCTX_EXTRN_DR7;
566	aenmNames[iReg++] = WHvX64RegisterDr7;
567	}
568	aenmNames[iReg++] = WHvX64RegisterDr0;
569	aenmNames[iReg++] = WHvX64RegisterDr1;
570	aenmNames[iReg++] = WHvX64RegisterDr2;
571	aenmNames[iReg++] = WHvX64RegisterDr3;
572	}
573	if (fWhat & CPUMCTX_EXTRN_DR6)
574	aenmNames[iReg++] = WHvX64RegisterDr6;
575
576	/* Floating point state. */
577	if (fWhat & CPUMCTX_EXTRN_X87)
578	{
579	aenmNames[iReg++] = WHvX64RegisterFpMmx0;
580	aenmNames[iReg++] = WHvX64RegisterFpMmx1;
581	aenmNames[iReg++] = WHvX64RegisterFpMmx2;
582	aenmNames[iReg++] = WHvX64RegisterFpMmx3;
583	aenmNames[iReg++] = WHvX64RegisterFpMmx4;
584	aenmNames[iReg++] = WHvX64RegisterFpMmx5;
585	aenmNames[iReg++] = WHvX64RegisterFpMmx6;
586	aenmNames[iReg++] = WHvX64RegisterFpMmx7;
587	aenmNames[iReg++] = WHvX64RegisterFpControlStatus;
588	}
589	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX))
590	aenmNames[iReg++] = WHvX64RegisterXmmControlStatus;
591
592	/* Vector state. */
593	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
594	{
595	aenmNames[iReg++] = WHvX64RegisterXmm0;
596	aenmNames[iReg++] = WHvX64RegisterXmm1;
597	aenmNames[iReg++] = WHvX64RegisterXmm2;
598	aenmNames[iReg++] = WHvX64RegisterXmm3;
599	aenmNames[iReg++] = WHvX64RegisterXmm4;
600	aenmNames[iReg++] = WHvX64RegisterXmm5;
601	aenmNames[iReg++] = WHvX64RegisterXmm6;
602	aenmNames[iReg++] = WHvX64RegisterXmm7;
603	aenmNames[iReg++] = WHvX64RegisterXmm8;
604	aenmNames[iReg++] = WHvX64RegisterXmm9;
605	aenmNames[iReg++] = WHvX64RegisterXmm10;
606	aenmNames[iReg++] = WHvX64RegisterXmm11;
607	aenmNames[iReg++] = WHvX64RegisterXmm12;
608	aenmNames[iReg++] = WHvX64RegisterXmm13;
609	aenmNames[iReg++] = WHvX64RegisterXmm14;
610	aenmNames[iReg++] = WHvX64RegisterXmm15;
611	}
612
613	/* MSRs */
614	// WHvX64RegisterTsc - don't touch
615	if (fWhat & CPUMCTX_EXTRN_EFER)
616	aenmNames[iReg++] = WHvX64RegisterEfer;
617	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
618	aenmNames[iReg++] = WHvX64RegisterKernelGsBase;
619	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
620	{
621	aenmNames[iReg++] = WHvX64RegisterSysenterCs;
622	aenmNames[iReg++] = WHvX64RegisterSysenterEip;
623	aenmNames[iReg++] = WHvX64RegisterSysenterEsp;
624	}
625	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
626	{
627	aenmNames[iReg++] = WHvX64RegisterStar;
628	aenmNames[iReg++] = WHvX64RegisterLstar;
629	aenmNames[iReg++] = WHvX64RegisterCstar;
630	aenmNames[iReg++] = WHvX64RegisterSfmask;
631	}
632
633	//#ifdef LOG_ENABLED
634	// const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pVM);
635	//#endif
636	if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
637	aenmNames[iReg++] = WHvX64RegisterTscAux;
638	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
639	{
640	aenmNames[iReg++] = WHvX64RegisterApicBase; /// @todo APIC BASE
641	aenmNames[iReg++] = WHvX64RegisterPat;
642	#if 0 /def LOG_ENABLED/ /** @todo Check if WHvX64RegisterMsrMtrrCap works... */
643	aenmNames[iReg++] = WHvX64RegisterMsrMtrrCap;
644	#endif
645	aenmNames[iReg++] = WHvX64RegisterMsrMtrrDefType;
646	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix64k00000;
647	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix16k80000;
648	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix16kA0000;
649	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kC0000;
650	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kC8000;
651	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kD0000;
652	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kD8000;
653	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kE0000;
654	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kE8000;
655	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kF0000;
656	aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kF8000;
657	if (pVM->nem.s.fDoIa32SpecCtrl)
658	aenmNames[iReg++] = WHvX64RegisterSpecCtrl;
659	/** @todo look for HvX64RegisterIa32MiscEnable and HvX64RegisterIa32FeatureControl? */
660	//#ifdef LOG_ENABLED
661	// if (enmCpuVendor != CPUMCPUVENDOR_AMD)
662	// aenmNames[iReg++] = HvX64RegisterIa32FeatureControl;
663	//#endif
664	}
665
666	/* Interruptibility. */
667	if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
668	{
669	aenmNames[iReg++] = WHvRegisterInterruptState;
670	aenmNames[iReg++] = WHvX64RegisterRip;
671	}
672
673	/* event injection */
674	aenmNames[iReg++] = WHvRegisterPendingInterruption;
675	aenmNames[iReg++] = WHvRegisterPendingEvent;
676
677	size_t const cRegs = iReg;
678	Assert(cRegs < RT_ELEMENTS(aenmNames));
679
680	/*
681	* Get the registers.
682	*/
683	WHV_REGISTER_VALUE aValues[128];
684	RT_ZERO(aValues);
685	Assert(RT_ELEMENTS(aValues) >= cRegs);
686	Assert(RT_ELEMENTS(aenmNames) >= cRegs);
687	#ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
688	Log12(("Calling WHvGetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
689	pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, cRegs, aValues));
690	#endif
691	HRESULT hrc = WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, (uint32_t)cRegs, aValues);
692	AssertLogRelMsgReturn(SUCCEEDED(hrc),
693	("WHvGetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
694	pVM->nem.s.hPartition, pVCpu->idCpu, cRegs, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
695	, VERR_NEM_GET_REGISTERS_FAILED);
696
697	iReg = 0;
698	#define GET_REG64(a_DstVar, a_enmName) do { \
699	Assert(aenmNames[iReg] == (a_enmName)); \
700	(a_DstVar) = aValues[iReg].Reg64; \
701	iReg++; \
702	} while (0)
703	#define GET_REG64_LOG7(a_DstVar, a_enmName, a_szLogName) do { \
704	Assert(aenmNames[iReg] == (a_enmName)); \
705	if ((a_DstVar) != aValues[iReg].Reg64) \
706	Log7(("NEM/%u: " a_szLogName " changed %RX64 -> %RX64\n", pVCpu->idCpu, (a_DstVar), aValues[iReg].Reg64)); \
707	(a_DstVar) = aValues[iReg].Reg64; \
708	iReg++; \
709	} while (0)
710	#define GET_REG128(a_DstVarLo, a_DstVarHi, a_enmName) do { \
711	Assert(aenmNames[iReg] == a_enmName); \
712	(a_DstVarLo) = aValues[iReg].Reg128.Low64; \
713	(a_DstVarHi) = aValues[iReg].Reg128.High64; \
714	iReg++; \
715	} while (0)
716	#define GET_SEG(a_SReg, a_enmName) do { \
717	Assert(aenmNames[iReg] == (a_enmName)); \
718	NEM_WIN_COPY_BACK_SEG(a_SReg, aValues[iReg].Segment); \
719	iReg++; \
720	} while (0)
721
722	/* GPRs */
723	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
724	{
725	if (fWhat & CPUMCTX_EXTRN_RAX)
726	GET_REG64(pVCpu->cpum.GstCtx.rax, WHvX64RegisterRax);
727	if (fWhat & CPUMCTX_EXTRN_RCX)
728	GET_REG64(pVCpu->cpum.GstCtx.rcx, WHvX64RegisterRcx);
729	if (fWhat & CPUMCTX_EXTRN_RDX)
730	GET_REG64(pVCpu->cpum.GstCtx.rdx, WHvX64RegisterRdx);
731	if (fWhat & CPUMCTX_EXTRN_RBX)
732	GET_REG64(pVCpu->cpum.GstCtx.rbx, WHvX64RegisterRbx);
733	if (fWhat & CPUMCTX_EXTRN_RSP)
734	GET_REG64(pVCpu->cpum.GstCtx.rsp, WHvX64RegisterRsp);
735	if (fWhat & CPUMCTX_EXTRN_RBP)
736	GET_REG64(pVCpu->cpum.GstCtx.rbp, WHvX64RegisterRbp);
737	if (fWhat & CPUMCTX_EXTRN_RSI)
738	GET_REG64(pVCpu->cpum.GstCtx.rsi, WHvX64RegisterRsi);
739	if (fWhat & CPUMCTX_EXTRN_RDI)
740	GET_REG64(pVCpu->cpum.GstCtx.rdi, WHvX64RegisterRdi);
741	if (fWhat & CPUMCTX_EXTRN_R8_R15)
742	{
743	GET_REG64(pVCpu->cpum.GstCtx.r8, WHvX64RegisterR8);
744	GET_REG64(pVCpu->cpum.GstCtx.r9, WHvX64RegisterR9);
745	GET_REG64(pVCpu->cpum.GstCtx.r10, WHvX64RegisterR10);
746	GET_REG64(pVCpu->cpum.GstCtx.r11, WHvX64RegisterR11);
747	GET_REG64(pVCpu->cpum.GstCtx.r12, WHvX64RegisterR12);
748	GET_REG64(pVCpu->cpum.GstCtx.r13, WHvX64RegisterR13);
749	GET_REG64(pVCpu->cpum.GstCtx.r14, WHvX64RegisterR14);
750	GET_REG64(pVCpu->cpum.GstCtx.r15, WHvX64RegisterR15);
751	}
752	}
753
754	/* RIP & Flags */
755	if (fWhat & CPUMCTX_EXTRN_RIP)
756	GET_REG64(pVCpu->cpum.GstCtx.rip, WHvX64RegisterRip);
757	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
758	GET_REG64(pVCpu->cpum.GstCtx.rflags.u, WHvX64RegisterRflags);
759
760	/* Segments */
761	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
762	{
763	if (fWhat & CPUMCTX_EXTRN_ES)
764	GET_SEG(pVCpu->cpum.GstCtx.es, WHvX64RegisterEs);
765	if (fWhat & CPUMCTX_EXTRN_CS)
766	GET_SEG(pVCpu->cpum.GstCtx.cs, WHvX64RegisterCs);
767	if (fWhat & CPUMCTX_EXTRN_SS)
768	GET_SEG(pVCpu->cpum.GstCtx.ss, WHvX64RegisterSs);
769	if (fWhat & CPUMCTX_EXTRN_DS)
770	GET_SEG(pVCpu->cpum.GstCtx.ds, WHvX64RegisterDs);
771	if (fWhat & CPUMCTX_EXTRN_FS)
772	GET_SEG(pVCpu->cpum.GstCtx.fs, WHvX64RegisterFs);
773	if (fWhat & CPUMCTX_EXTRN_GS)
774	GET_SEG(pVCpu->cpum.GstCtx.gs, WHvX64RegisterGs);
775	}
776
777	/* Descriptor tables and the task segment. */
778	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
779	{
780	if (fWhat & CPUMCTX_EXTRN_LDTR)
781	GET_SEG(pVCpu->cpum.GstCtx.ldtr, WHvX64RegisterLdtr);
782
783	if (fWhat & CPUMCTX_EXTRN_TR)
784	{
785	/* AMD-V likes loading TR with in AVAIL state, whereas intel insists on BUSY. So,
786	avoid to trigger sanity assertions around the code, always fix this. */
787	GET_SEG(pVCpu->cpum.GstCtx.tr, WHvX64RegisterTr);
788	switch (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type)
789	{
790	case X86_SEL_TYPE_SYS_386_TSS_BUSY:
791	case X86_SEL_TYPE_SYS_286_TSS_BUSY:
792	break;
793	case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
794	pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
795	break;
796	case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
797	pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
798	break;
799	}
800	}
801	if (fWhat & CPUMCTX_EXTRN_IDTR)
802	{
803	Assert(aenmNames[iReg] == WHvX64RegisterIdtr);
804	pVCpu->cpum.GstCtx.idtr.cbIdt = aValues[iReg].Table.Limit;
805	pVCpu->cpum.GstCtx.idtr.pIdt = aValues[iReg].Table.Base;
806	iReg++;
807	}
808	if (fWhat & CPUMCTX_EXTRN_GDTR)
809	{
810	Assert(aenmNames[iReg] == WHvX64RegisterGdtr);
811	pVCpu->cpum.GstCtx.gdtr.cbGdt = aValues[iReg].Table.Limit;
812	pVCpu->cpum.GstCtx.gdtr.pGdt = aValues[iReg].Table.Base;
813	iReg++;
814	}
815	}
816
817	/* Control registers. */
818	bool fMaybeChangedMode = false;
819	bool fUpdateCr3 = false;
820	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
821	{
822	if (fWhat & CPUMCTX_EXTRN_CR0)
823	{
824	Assert(aenmNames[iReg] == WHvX64RegisterCr0);
825	if (pVCpu->cpum.GstCtx.cr0 != aValues[iReg].Reg64)
826	{
827	CPUMSetGuestCR0(pVCpu, aValues[iReg].Reg64);
828	fMaybeChangedMode = true;
829	}
830	iReg++;
831	}
832	if (fWhat & CPUMCTX_EXTRN_CR2)
833	GET_REG64(pVCpu->cpum.GstCtx.cr2, WHvX64RegisterCr2);
834	if (fWhat & CPUMCTX_EXTRN_CR3)
835	{
836	if (pVCpu->cpum.GstCtx.cr3 != aValues[iReg].Reg64)
837	{
838	CPUMSetGuestCR3(pVCpu, aValues[iReg].Reg64);
839	fUpdateCr3 = true;
840	}
841	iReg++;
842	}
843	if (fWhat & CPUMCTX_EXTRN_CR4)
844	{
845	if (pVCpu->cpum.GstCtx.cr4 != aValues[iReg].Reg64)
846	{
847	CPUMSetGuestCR4(pVCpu, aValues[iReg].Reg64);
848	fMaybeChangedMode = true;
849	}
850	iReg++;
851	}
852	}
853	if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
854	{
855	Assert(aenmNames[iReg] == WHvX64RegisterCr8);
856	PDMApicSetTpr(pVCpu, (uint8_t)aValues[iReg].Reg64 << 4);
857	iReg++;
858	}
859
860	/* Debug registers. */
861	if (fWhat & CPUMCTX_EXTRN_DR7)
862	{
863	Assert(aenmNames[iReg] == WHvX64RegisterDr7);
864	if (pVCpu->cpum.GstCtx.dr[7] != aValues[iReg].Reg64)
865	CPUMSetGuestDR7(pVCpu, aValues[iReg].Reg64);
866	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_DR7; /* Hack alert! Avoids asserting when processing CPUMCTX_EXTRN_DR0_DR3. */
867	iReg++;
868	}
869	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
870	{
871	Assert(aenmNames[iReg] == WHvX64RegisterDr0);
872	Assert(aenmNames[iReg+3] == WHvX64RegisterDr3);
873	if (pVCpu->cpum.GstCtx.dr[0] != aValues[iReg].Reg64)
874	CPUMSetGuestDR0(pVCpu, aValues[iReg].Reg64);
875	iReg++;
876	if (pVCpu->cpum.GstCtx.dr[1] != aValues[iReg].Reg64)
877	CPUMSetGuestDR1(pVCpu, aValues[iReg].Reg64);
878	iReg++;
879	if (pVCpu->cpum.GstCtx.dr[2] != aValues[iReg].Reg64)
880	CPUMSetGuestDR2(pVCpu, aValues[iReg].Reg64);
881	iReg++;
882	if (pVCpu->cpum.GstCtx.dr[3] != aValues[iReg].Reg64)
883	CPUMSetGuestDR3(pVCpu, aValues[iReg].Reg64);
884	iReg++;
885	}
886	if (fWhat & CPUMCTX_EXTRN_DR6)
887	{
888	Assert(aenmNames[iReg] == WHvX64RegisterDr6);
889	if (pVCpu->cpum.GstCtx.dr[6] != aValues[iReg].Reg64)
890	CPUMSetGuestDR6(pVCpu, aValues[iReg].Reg64);
891	iReg++;
892	}
893
894	/* Floating point state. */
895	if (fWhat & CPUMCTX_EXTRN_X87)
896	{
897	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[0].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[0].au64[1], WHvX64RegisterFpMmx0);
898	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[1].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[1].au64[1], WHvX64RegisterFpMmx1);
899	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[2].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[2].au64[1], WHvX64RegisterFpMmx2);
900	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[3].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[3].au64[1], WHvX64RegisterFpMmx3);
901	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[4].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[4].au64[1], WHvX64RegisterFpMmx4);
902	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[5].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[5].au64[1], WHvX64RegisterFpMmx5);
903	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[6].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[6].au64[1], WHvX64RegisterFpMmx6);
904	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[7].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[7].au64[1], WHvX64RegisterFpMmx7);
905
906	Assert(aenmNames[iReg] == WHvX64RegisterFpControlStatus);
907	pVCpu->cpum.GstCtx.XState.x87.FCW = aValues[iReg].FpControlStatus.FpControl;
908	pVCpu->cpum.GstCtx.XState.x87.FSW = aValues[iReg].FpControlStatus.FpStatus;
909	pVCpu->cpum.GstCtx.XState.x87.FTW = aValues[iReg].FpControlStatus.FpTag
910	/\| (aValues[iReg].FpControlStatus.Reserved << 8)/;
911	pVCpu->cpum.GstCtx.XState.x87.FOP = aValues[iReg].FpControlStatus.LastFpOp;
912	pVCpu->cpum.GstCtx.XState.x87.FPUIP = (uint32_t)aValues[iReg].FpControlStatus.LastFpRip;
913	pVCpu->cpum.GstCtx.XState.x87.CS = (uint16_t)(aValues[iReg].FpControlStatus.LastFpRip >> 32);
914	pVCpu->cpum.GstCtx.XState.x87.Rsrvd1 = (uint16_t)(aValues[iReg].FpControlStatus.LastFpRip >> 48);
915	iReg++;
916	}
917
918	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX))
919	{
920	Assert(aenmNames[iReg] == WHvX64RegisterXmmControlStatus);
921	if (fWhat & CPUMCTX_EXTRN_X87)
922	{
923	pVCpu->cpum.GstCtx.XState.x87.FPUDP = (uint32_t)aValues[iReg].XmmControlStatus.LastFpRdp;
924	pVCpu->cpum.GstCtx.XState.x87.DS = (uint16_t)(aValues[iReg].XmmControlStatus.LastFpRdp >> 32);
925	pVCpu->cpum.GstCtx.XState.x87.Rsrvd2 = (uint16_t)(aValues[iReg].XmmControlStatus.LastFpRdp >> 48);
926	}
927	pVCpu->cpum.GstCtx.XState.x87.MXCSR = aValues[iReg].XmmControlStatus.XmmStatusControl;
928	pVCpu->cpum.GstCtx.XState.x87.MXCSR_MASK = aValues[iReg].XmmControlStatus.XmmStatusControlMask; /** @todo ??? (Isn't this an output field?) */
929	iReg++;
930	}
931
932	/* Vector state. */
933	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
934	{
935	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 0].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 0].uXmm.s.Hi, WHvX64RegisterXmm0);
936	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 1].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 1].uXmm.s.Hi, WHvX64RegisterXmm1);
937	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 2].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 2].uXmm.s.Hi, WHvX64RegisterXmm2);
938	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 3].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 3].uXmm.s.Hi, WHvX64RegisterXmm3);
939	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 4].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 4].uXmm.s.Hi, WHvX64RegisterXmm4);
940	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 5].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 5].uXmm.s.Hi, WHvX64RegisterXmm5);
941	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 6].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 6].uXmm.s.Hi, WHvX64RegisterXmm6);
942	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 7].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 7].uXmm.s.Hi, WHvX64RegisterXmm7);
943	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 8].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 8].uXmm.s.Hi, WHvX64RegisterXmm8);
944	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 9].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 9].uXmm.s.Hi, WHvX64RegisterXmm9);
945	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[10].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[10].uXmm.s.Hi, WHvX64RegisterXmm10);
946	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[11].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[11].uXmm.s.Hi, WHvX64RegisterXmm11);
947	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[12].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[12].uXmm.s.Hi, WHvX64RegisterXmm12);
948	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[13].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[13].uXmm.s.Hi, WHvX64RegisterXmm13);
949	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[14].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[14].uXmm.s.Hi, WHvX64RegisterXmm14);
950	GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[15].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[15].uXmm.s.Hi, WHvX64RegisterXmm15);
951	}
952
953	/* MSRs */
954	// WHvX64RegisterTsc - don't touch
955	if (fWhat & CPUMCTX_EXTRN_EFER)
956	{
957	Assert(aenmNames[iReg] == WHvX64RegisterEfer);
958	if (aValues[iReg].Reg64 != pVCpu->cpum.GstCtx.msrEFER)
959	{
960	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, aValues[iReg].Reg64));
961	if ((aValues[iReg].Reg64 ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
962	PGMNotifyNxeChanged(pVCpu, RT_BOOL(aValues[iReg].Reg64 & MSR_K6_EFER_NXE));
963	pVCpu->cpum.GstCtx.msrEFER = aValues[iReg].Reg64;
964	fMaybeChangedMode = true;
965	}
966	iReg++;
967	}
968	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
969	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrKERNELGSBASE, WHvX64RegisterKernelGsBase, "MSR KERNEL_GS_BASE");
970	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
971	{
972	GET_REG64_LOG7(pVCpu->cpum.GstCtx.SysEnter.cs, WHvX64RegisterSysenterCs, "MSR SYSENTER.CS");
973	GET_REG64_LOG7(pVCpu->cpum.GstCtx.SysEnter.eip, WHvX64RegisterSysenterEip, "MSR SYSENTER.EIP");
974	GET_REG64_LOG7(pVCpu->cpum.GstCtx.SysEnter.esp, WHvX64RegisterSysenterEsp, "MSR SYSENTER.ESP");
975	}
976	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
977	{
978	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrSTAR, WHvX64RegisterStar, "MSR STAR");
979	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrLSTAR, WHvX64RegisterLstar, "MSR LSTAR");
980	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrCSTAR, WHvX64RegisterCstar, "MSR CSTAR");
981	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrSFMASK, WHvX64RegisterSfmask, "MSR SFMASK");
982	}
983	if (fWhat & (CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
984	{
985	PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
986	if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
987	GET_REG64_LOG7(pCtxMsrs->msr.TscAux, WHvX64RegisterTscAux, "MSR TSC_AUX");
988	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
989	{
990	Assert(aenmNames[iReg] == WHvX64RegisterApicBase);
991	const uint64_t uOldBase = PDMApicGetBaseMsrNoCheck(pVCpu);
992	if (aValues[iReg].Reg64 != uOldBase)
993	{
994	Log7(("NEM/%u: MSR APICBase changed %RX64 -> %RX64 (%RX64)\n",
995	pVCpu->idCpu, uOldBase, aValues[iReg].Reg64, aValues[iReg].Reg64 ^ uOldBase));
996	int rc2 = PDMApicSetBaseMsr(pVCpu, aValues[iReg].Reg64);
997	AssertLogRelMsg(rc2 == VINF_SUCCESS, ("%Rrc %RX64\n", rc2, aValues[iReg].Reg64));
998	}
999	iReg++;
1000
1001	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrPAT, WHvX64RegisterPat, "MSR PAT");
1002	#if 0 /def LOG_ENABLED/ /** @todo something's wrong with HvX64RegisterMtrrCap? (AMD) */
1003	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrPAT, WHvX64RegisterMsrMtrrCap);
1004	#endif
1005	GET_REG64_LOG7(pCtxMsrs->msr.MtrrDefType, WHvX64RegisterMsrMtrrDefType, "MSR MTRR_DEF_TYPE");
1006	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix64K_00000, WHvX64RegisterMsrMtrrFix64k00000, "MSR MTRR_FIX_64K_00000");
1007	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix16K_80000, WHvX64RegisterMsrMtrrFix16k80000, "MSR MTRR_FIX_16K_80000");
1008	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix16K_A0000, WHvX64RegisterMsrMtrrFix16kA0000, "MSR MTRR_FIX_16K_A0000");
1009	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_C0000, WHvX64RegisterMsrMtrrFix4kC0000, "MSR MTRR_FIX_4K_C0000");
1010	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_C8000, WHvX64RegisterMsrMtrrFix4kC8000, "MSR MTRR_FIX_4K_C8000");
1011	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_D0000, WHvX64RegisterMsrMtrrFix4kD0000, "MSR MTRR_FIX_4K_D0000");
1012	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_D8000, WHvX64RegisterMsrMtrrFix4kD8000, "MSR MTRR_FIX_4K_D8000");
1013	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_E0000, WHvX64RegisterMsrMtrrFix4kE0000, "MSR MTRR_FIX_4K_E0000");
1014	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_E8000, WHvX64RegisterMsrMtrrFix4kE8000, "MSR MTRR_FIX_4K_E8000");
1015	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_F0000, WHvX64RegisterMsrMtrrFix4kF0000, "MSR MTRR_FIX_4K_F0000");
1016	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_F8000, WHvX64RegisterMsrMtrrFix4kF8000, "MSR MTRR_FIX_4K_F8000");
1017	if (pVM->nem.s.fDoIa32SpecCtrl)
1018	GET_REG64_LOG7(pCtxMsrs->msr.SpecCtrl, WHvX64RegisterSpecCtrl, "MSR IA32_SPEC_CTRL");
1019	/** @todo look for HvX64RegisterIa32MiscEnable and HvX64RegisterIa32FeatureControl? */
1020	}
1021	}
1022
1023	/* Interruptibility. */
1024	if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1025	{
1026	Assert(aenmNames[iReg] == WHvRegisterInterruptState);
1027	Assert(aenmNames[iReg + 1] == WHvX64RegisterRip);
1028
1029	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_INT))
1030	pVCpu->nem.s.fLastInterruptShadow = CPUMUpdateInterruptShadowEx(&pVCpu->cpum.GstCtx,
1031	aValues[iReg].InterruptState.InterruptShadow,
1032	aValues[iReg + 1].Reg64);
1033
1034	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_NMI))
1035	CPUMUpdateInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx, aValues[iReg].InterruptState.NmiMasked);
1036
1037	fWhat \|= CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI;
1038	iReg += 2;
1039	}
1040
1041	/* Event injection. */
1042	/// @todo WHvRegisterPendingInterruption
1043	Assert(aenmNames[iReg] == WHvRegisterPendingInterruption);
1044	if (aValues[iReg].PendingInterruption.InterruptionPending)
1045	{
1046	Log7(("PendingInterruption: type=%u vector=%#x errcd=%RTbool/%#x instr-len=%u nested=%u\n",
1047	aValues[iReg].PendingInterruption.InterruptionType, aValues[iReg].PendingInterruption.InterruptionVector,
1048	aValues[iReg].PendingInterruption.DeliverErrorCode, aValues[iReg].PendingInterruption.ErrorCode,
1049	aValues[iReg].PendingInterruption.InstructionLength, aValues[iReg].PendingInterruption.NestedEvent));
1050	AssertMsg((aValues[iReg].PendingInterruption.AsUINT64 & UINT64_C(0xfc00)) == 0,
1051	("%#RX64\n", aValues[iReg].PendingInterruption.AsUINT64));
1052	}
1053
1054	/// @todo WHvRegisterPendingEvent
1055
1056	/* Almost done, just update extrn flags and maybe change PGM mode. */
1057	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1058	if (!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL \| (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT))))
1059	pVCpu->cpum.GstCtx.fExtrn = 0;
1060
1061	/* Typical. */
1062	if (!fMaybeChangedMode && !fUpdateCr3)
1063	return VINF_SUCCESS;
1064
1065	/*
1066	* Slow.
1067	*/
1068	if (fMaybeChangedMode)
1069	{
1070	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1071	false /* fForce */);
1072	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);
1073	}
1074
1075	if (fUpdateCr3)
1076	{
1077	int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3);
1078	if (rc == VINF_SUCCESS)
1079	{ /* likely */ }
1080	else
1081	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);
1082	}
1083
1084	return VINF_SUCCESS;
1085	}
1086
1087
1088	/**
1089	* Interface for importing state on demand (used by IEM).
1090	*
1091	* @returns VBox status code.
1092	* @param pVCpu The cross context CPU structure.
1093	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1094	*/
1095	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1096	{
1097	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
1098	return nemHCWinCopyStateFromHyperV(pVCpu->pVMR3, pVCpu, fWhat);
1099	}
1100
1101
1102	/**
1103	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
1104	*
1105	* @returns VBox status code.
1106	* @param pVCpu The cross context CPU structure.
1107	* @param pcTicks Where to return the CPU tick count.
1108	* @param puAux Where to return the TSC_AUX register value.
1109	*/
1110	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
1111	{
1112	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
1113
1114	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1115	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
1116	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
1117
1118	/* Call the offical API. */
1119	WHV_REGISTER_NAME aenmNames[2] = { WHvX64RegisterTsc, WHvX64RegisterTscAux };
1120	WHV_REGISTER_VALUE aValues[2] = { { { { 0, 0 } } }, { { { 0, 0 } } } };
1121	Assert(RT_ELEMENTS(aenmNames) == RT_ELEMENTS(aValues));
1122	HRESULT hrc = WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, 2, aValues);
1123	AssertLogRelMsgReturn(SUCCEEDED(hrc),
1124	("WHvGetVirtualProcessorRegisters(%p, %u,{tsc,tsc_aux},2,) -> %Rhrc (Last=%#x/%u)\n",
1125	pVM->nem.s.hPartition, pVCpu->idCpu, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
1126	, VERR_NEM_GET_REGISTERS_FAILED);
1127	*pcTicks = aValues[0].Reg64;
1128	if (puAux)
1129	*puAux = pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_TSC_AUX ? aValues[1].Reg64 : CPUMGetGuestTscAux(pVCpu);
1130	return VINF_SUCCESS;
1131	}
1132
1133
1134	/**
1135	* Resumes CPU clock (TSC) on all virtual CPUs.
1136	*
1137	* This is called by TM when the VM is started, restored, resumed or similar.
1138	*
1139	* @returns VBox status code.
1140	* @param pVM The cross context VM structure.
1141	* @param pVCpu The cross context CPU structure of the calling EMT.
1142	* @param uPausedTscValue The TSC value at the time of pausing.
1143	*/
1144	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
1145	{
1146	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
1147	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
1148
1149	/** @todo Do this WHvSuspendPartitionTime call to when the VM is suspended. */
1150	HRESULT hrcSuspend = E_FAIL;
1151	if (WHvSuspendPartitionTime && WHvResumePartitionTime)
1152	{
1153	hrcSuspend = WHvSuspendPartitionTime(pVM->nem.s.hPartition);
1154	AssertLogRelMsg(SUCCEEDED(hrcSuspend),
1155	("WHvSuspendPartitionTime(%p) -> %Rhrc (Last=%#x/%u)\n",
1156	pVM->nem.s.hPartition, hrcSuspend, RTNtLastStatusValue(), RTNtLastErrorValue()));
1157	}
1158
1159	/*
1160	* Call the offical API to do the job.
1161	*/
1162	if (pVM->cCpus > 1)
1163	RTThreadYield(); /* Try decrease the chance that we get rescheduled in the middle. */
1164
1165	/* Start with the first CPU. */
1166	WHV_REGISTER_NAME enmName = WHvX64RegisterTsc;
1167	WHV_REGISTER_VALUE Value = { { { 0, 0 } } };
1168	Value.Reg64 = uPausedTscValue;
1169	uint64_t const uFirstTsc = ASMReadTSC();
1170	HRESULT hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, 0 /iCpu/, &enmName, 1, &Value);
1171	AssertLogRelMsgReturn(SUCCEEDED(hrc),
1172	("WHvSetVirtualProcessorRegisters(%p, 0,{tsc},2,%#RX64) -> %Rhrc (Last=%#x/%u)\n",
1173	pVM->nem.s.hPartition, uPausedTscValue, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
1174	, VERR_NEM_SET_TSC);
1175
1176	/* Do the other CPUs, adjusting for elapsed TSC and keeping finger crossed
1177	that we don't introduce too much drift here. */
1178	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
1179	{
1180	Assert(enmName == WHvX64RegisterTsc);
1181	const uint64_t offDelta = SUCCEEDED(hrcSuspend) ? 0 : ASMReadTSC() - uFirstTsc;
1182	Value.Reg64 = uPausedTscValue + offDelta;
1183	hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, iCpu, &enmName, 1, &Value);
1184	AssertLogRelMsgReturn(SUCCEEDED(hrc),
1185	("WHvSetVirtualProcessorRegisters(%p, 0,{tsc},2,%#RX64 + %#RX64) -> %Rhrc (Last=%#x/%u)\n",
1186	pVM->nem.s.hPartition, iCpu, uPausedTscValue, offDelta, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
1187	, VERR_NEM_SET_TSC);
1188	}
1189
1190	if (SUCCEEDED(hrcSuspend))
1191	{
1192	hrc = WHvResumePartitionTime(pVM->nem.s.hPartition);
1193	AssertLogRelMsgReturn(SUCCEEDED(hrc),
1194	("WHvResumePartitionTime(%p) -> %Rhrc (Last=%#x/%u)\n",
1195	pVM->nem.s.hPartition, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
1196	, VERR_NEM_SET_TSC);
1197	}
1198
1199	return VINF_SUCCESS;
1200	}
1201
1202	#ifdef LOG_ENABLED
1203
1204	/**
1205	* Get the virtual processor running status.
1206	*/
1207	DECLINLINE(VID_PROCESSOR_STATUS) nemHCWinCpuGetRunningStatus(PVMCPUCC pVCpu)
1208	{
1209	RTERRVARS Saved;
1210	RTErrVarsSave(&Saved);
1211
1212	/*
1213	* This API is disabled in release builds, it seems. On build 17101 it requires
1214	* the following patch to be enabled (windbg): eb vid+12180 0f 84 98 00 00 00
1215	*/
1216	VID_PROCESSOR_STATUS enmCpuStatus = VidProcessorStatusUndefined;
1217	NTSTATUS rcNt = g_pfnVidGetVirtualProcessorRunningStatus(pVCpu->pVMR3->nem.s.hPartitionDevice, pVCpu->idCpu, &enmCpuStatus);
1218	AssertMsg(NT_SUCCESS(rcNt), ("rcNt=%#x\n", rcNt));
1219
1220	RTErrVarsRestore(&Saved);
1221	return enmCpuStatus;
1222	}
1223
1224
1225	/**
1226	* Logs the current CPU state.
1227	*/
1228	NEM_TMPL_STATIC void nemHCWinLogState(PVMCC pVM, PVMCPUCC pVCpu)
1229	{
1230	if (LogIs3Enabled())
1231	{
1232	# if 0 // def IN_RING3 - causes lazy state import assertions all over CPUM.
1233	char szRegs[4096];
1234	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
1235	"rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
1236	"rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
1237	"r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
1238	"r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
1239	"rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
1240	"cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
1241	"ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
1242	"es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
1243	"fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
1244	"gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
1245	"ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
1246	"dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
1247	"dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
1248	"gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
1249	"ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
1250	"tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
1251	" sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
1252	" efer=%016VR{efer}\n"
1253	" pat=%016VR{pat}\n"
1254	" sf_mask=%016VR{sf_mask}\n"
1255	"krnl_gs_base=%016VR{krnl_gs_base}\n"
1256	" lstar=%016VR{lstar}\n"
1257	" star=%016VR{star} cstar=%016VR{cstar}\n"
1258	"fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
1259	);
1260
1261	char szInstr[256];
1262	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
1263	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
1264	szInstr, sizeof(szInstr), NULL);
1265	Log3(("%s%s\n", szRegs, szInstr));
1266	# else
1267	/** @todo stat logging in ring-0 */
1268	RT_NOREF(pVM, pVCpu);
1269	# endif
1270	}
1271	}
1272
1273	#endif /* LOG_ENABLED */
1274
1275	/**
1276	* Translates the execution stat bitfield into a short log string, WinHv version.
1277	*
1278	* @returns Read-only log string.
1279	* @param pExitCtx The exit context which state to summarize.
1280	*/
1281	static const char nemR3WinExecStateToLogStr(WHV_VP_EXIT_CONTEXT const pExitCtx)
1282	{
1283	unsigned u = (unsigned)pExitCtx->ExecutionState.InterruptionPending
1284	\| ((unsigned)pExitCtx->ExecutionState.DebugActive << 1)
1285	\| ((unsigned)pExitCtx->ExecutionState.InterruptShadow << 2);
1286	#define SWITCH_IT(a_szPrefix) \
1287	do \
1288	switch (u)\
1289	{ \
1290	case 0x00: return a_szPrefix ""; \
1291	case 0x01: return a_szPrefix ",Pnd"; \
1292	case 0x02: return a_szPrefix ",Dbg"; \
1293	case 0x03: return a_szPrefix ",Pnd,Dbg"; \
1294	case 0x04: return a_szPrefix ",Shw"; \
1295	case 0x05: return a_szPrefix ",Pnd,Shw"; \
1296	case 0x06: return a_szPrefix ",Shw,Dbg"; \
1297	case 0x07: return a_szPrefix ",Pnd,Shw,Dbg"; \
1298	default: AssertFailedReturn("WTF?"); \
1299	} \
1300	while (0)
1301	if (pExitCtx->ExecutionState.EferLma)
1302	SWITCH_IT("LM");
1303	else if (pExitCtx->ExecutionState.Cr0Pe)
1304	SWITCH_IT("PM");
1305	else
1306	SWITCH_IT("RM");
1307	#undef SWITCH_IT
1308	}
1309
1310
1311	/**
1312	* Advances the guest RIP and clear EFLAGS.RF, WinHv version.
1313	*
1314	* This may clear VMCPU_FF_INHIBIT_INTERRUPTS.
1315	*
1316	* @param pVCpu The cross context virtual CPU structure.
1317	* @param pExitCtx The exit context.
1318	* @param cbMinInstr The minimum instruction length, or 1 if not unknown.
1319	*/
1320	DECLINLINE(void) nemR3WinAdvanceGuestRipAndClearRF(PVMCPUCC pVCpu, WHV_VP_EXIT_CONTEXT const *pExitCtx, uint8_t cbMinInstr)
1321	{
1322	Assert(!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS)));
1323
1324	/* Advance the RIP. */
1325	Assert(pExitCtx->InstructionLength >= cbMinInstr); RT_NOREF_PV(cbMinInstr);
1326	pVCpu->cpum.GstCtx.rip += pExitCtx->InstructionLength;
1327	pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
1328	CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
1329	}
1330
1331
1332	/**
1333	* State to pass between nemHCWinHandleMemoryAccess / nemR3WinWHvHandleMemoryAccess
1334	* and nemHCWinHandleMemoryAccessPageCheckerCallback.
1335	*/
1336	typedef struct NEMHCWINHMACPCCSTATE
1337	{
1338	/** Input: Write access. */
1339	bool fWriteAccess;
1340	/** Output: Set if we did something. */
1341	bool fDidSomething;
1342	/** Output: Set it we should resume. */
1343	bool fCanResume;
1344	} NEMHCWINHMACPCCSTATE;
1345
1346	/**
1347	* @callback_method_impl{FNPGMPHYSNEMCHECKPAGE,
1348	* Worker for nemR3WinHandleMemoryAccess; pvUser points to a
1349	* NEMHCWINHMACPCCSTATE structure. }
1350	*/
1351	NEM_TMPL_STATIC DECLCALLBACK(int)
1352	nemHCWinHandleMemoryAccessPageCheckerCallback(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1353	{
1354	NEMHCWINHMACPCCSTATE pState = (NEMHCWINHMACPCCSTATE )pvUser;
1355	pState->fDidSomething = false;
1356	pState->fCanResume = false;
1357
1358	/* If A20 is disabled, we may need to make another query on the masked
1359	page to get the correct protection information. */
1360	uint8_t u2State = pInfo->u2NemState;
1361	RTGCPHYS GCPhysSrc;
1362	#ifdef NEM_WIN_WITH_A20
1363	if ( pVM->nem.s.fA20Enabled
1364	\|\| !NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
1365	#endif
1366	GCPhysSrc = GCPhys;
1367	#ifdef NEM_WIN_WITH_A20
1368	else
1369	{
1370	GCPhysSrc = GCPhys & ~(RTGCPHYS)RT_BIT_32(20);
1371	PGMPHYSNEMPAGEINFO Info2;
1372	int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhysSrc, pState->fWriteAccess, &Info2, NULL, NULL);
1373	AssertRCReturn(rc, rc);
1374
1375	*pInfo = Info2;
1376	pInfo->u2NemState = u2State;
1377	}
1378	#endif
1379
1380	/*
1381	* Consolidate current page state with actual page protection and access type.
1382	* We don't really consider downgrades here, as they shouldn't happen.
1383	*/
1384	/** @todo Someone at microsoft please explain:
1385	* I'm not sure WTF was going on, but I ended up in a loop if I remapped a
1386	* readonly page as writable (unmap, then map again). Specifically, this was an
1387	* issue with the big VRAM mapping at 0xe0000000 when booing DSL 4.4.1. So, in
1388	* a hope to work around that we no longer pre-map anything, just unmap stuff
1389	* and do it lazily here. And here we will first unmap, restart, and then remap
1390	* with new protection or backing.
1391	*/
1392	int rc;
1393	switch (u2State)
1394	{
1395	case NEM_WIN_PAGE_STATE_UNMAPPED:
1396	case NEM_WIN_PAGE_STATE_NOT_SET:
1397	if (pInfo->fNemProt == NEM_PAGE_PROT_NONE)
1398	{
1399	Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1\n", GCPhys));
1400	return VINF_SUCCESS;
1401	}
1402
1403	/* Don't bother remapping it if it's a write request to a non-writable page. */
1404	if ( pState->fWriteAccess
1405	&& !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE))
1406	{
1407	Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1w\n", GCPhys));
1408	return VINF_SUCCESS;
1409	}
1410
1411	/* Map the page. */
1412	rc = nemHCNativeSetPhysPage(pVM,
1413	pVCpu,
1414	GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1415	GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1416	pInfo->fNemProt,
1417	&u2State,
1418	true /fBackingState/);
1419	pInfo->u2NemState = u2State;
1420	Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - synced => %s + %Rrc\n",
1421	GCPhys, g_apszPageStates[u2State], rc));
1422	pState->fDidSomething = true;
1423	pState->fCanResume = true;
1424	return rc;
1425
1426	case NEM_WIN_PAGE_STATE_READABLE:
1427	if ( !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1428	&& (pInfo->fNemProt & (NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE)))
1429	{
1430	Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #2\n", GCPhys));
1431	return VINF_SUCCESS;
1432	}
1433
1434	break;
1435
1436	case NEM_WIN_PAGE_STATE_WRITABLE:
1437	if (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1438	{
1439	if (pInfo->u2OldNemState == NEM_WIN_PAGE_STATE_WRITABLE)
1440	Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #3a\n", GCPhys));
1441	else
1442	{
1443	pState->fCanResume = true;
1444	Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #3b (%s -> %s)\n",
1445	GCPhys, g_apszPageStates[pInfo->u2OldNemState], g_apszPageStates[u2State]));
1446	}
1447	return VINF_SUCCESS;
1448	}
1449	break;
1450
1451	default:
1452	AssertLogRelMsgFailedReturn(("u2State=%#x\n", u2State), VERR_NEM_IPE_4);
1453	}
1454
1455	/*
1456	* Unmap and restart the instruction.
1457	* If this fails, which it does every so often, just unmap everything for now.
1458	*/
1459	/** @todo figure out whether we mess up the state or if it's WHv. */
1460	STAM_REL_PROFILE_START(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
1461	HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
1462	STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
1463	if (SUCCEEDED(hrc))
1464	{
1465	pState->fDidSomething = true;
1466	pState->fCanResume = true;
1467	pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1468	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
1469	uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1470	Log5(("NEM GPA unmapped/exit: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[u2State], cMappedPages));
1471	return VINF_SUCCESS;
1472	}
1473	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
1474	LogRel(("nemHCWinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp %s hrc=%Rhrc (%#x)\n",
1475	GCPhys, g_apszPageStates[u2State], hrc, hrc));
1476	return VERR_NEM_UNMAP_PAGES_FAILED;
1477	}
1478
1479
1480	/**
1481	* Wrapper around nemHCWinCopyStateFromHyperV.
1482	*
1483	* Unlike the wrapped APIs, this checks whether it's necessary.
1484	*
1485	* @returns VBox strict status code.
1486	* @param pVCpu The cross context per CPU structure.
1487	* @param fWhat What to import.
1488	* @param pszCaller Who is doing the importing.
1489	*/
1490	DECLINLINE(VBOXSTRICTRC) nemHCWinImportStateIfNeededStrict(PVMCPUCC pVCpu, uint64_t fWhat, const char *pszCaller)
1491	{
1492	if (pVCpu->cpum.GstCtx.fExtrn & fWhat)
1493	{
1494	RT_NOREF(pszCaller);
1495	int rc = nemHCWinCopyStateFromHyperV(pVCpu->pVMR3, pVCpu, fWhat);
1496	AssertRCReturn(rc, rc);
1497	}
1498	return VINF_SUCCESS;
1499	}
1500
1501
1502	/**
1503	* Copies register state from the (common) exit context.
1504	*
1505	* ASSUMES no state copied yet.
1506	*
1507	* @param pVCpu The cross context per CPU structure.
1508	* @param pExitCtx The common exit context.
1509	* @sa nemHCWinCopyStateFromX64Header
1510	*/
1511	DECLINLINE(void) nemR3WinCopyStateFromX64Header(PVMCPUCC pVCpu, WHV_VP_EXIT_CONTEXT const *pExitCtx)
1512	{
1513	Assert( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_INHIBIT_INT))
1514	== (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_INHIBIT_INT));
1515
1516	NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.cs, pExitCtx->Cs);
1517	pVCpu->cpum.GstCtx.rip = pExitCtx->Rip;
1518	pVCpu->cpum.GstCtx.rflags.u = pExitCtx->Rflags;
1519	pVCpu->nem.s.fLastInterruptShadow = CPUMUpdateInterruptShadowEx(&pVCpu->cpum.GstCtx,
1520	pExitCtx->ExecutionState.InterruptShadow,
1521	pExitCtx->Rip);
1522	PDMApicSetTpr(pVCpu, pExitCtx->Cr8 << 4);
1523
1524	pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_APIC_TPR);
1525	}
1526
1527
1528	/**
1529	* Deals with memory access exits (WHvRunVpExitReasonMemoryAccess).
1530	*
1531	* @returns Strict VBox status code.
1532	* @param pVM The cross context VM structure.
1533	* @param pVCpu The cross context per CPU structure.
1534	* @param pExit The VM exit information to handle.
1535	* @sa nemHCWinHandleMessageMemory
1536	*/
1537	NEM_TMPL_STATIC VBOXSTRICTRC
1538	nemR3WinHandleExitMemory(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1539	{
1540	uint64_t const uHostTsc = ASMReadTSC();
1541	Assert(pExit->MemoryAccess.AccessInfo.AccessType != 3);
1542
1543	/*
1544	* Whatever we do, we must clear pending event injection upon resume.
1545	*/
1546	if (pExit->VpContext.ExecutionState.InterruptionPending)
1547	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
1548
1549	/*
1550	* Ask PGM for information about the given GCPhys. We need to check if we're
1551	* out of sync first.
1552	*/
1553	NEMHCWINHMACPCCSTATE State = { pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite, false, false };
1554	PGMPHYSNEMPAGEINFO Info;
1555	int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, pExit->MemoryAccess.Gpa, State.fWriteAccess, &Info,
1556	nemHCWinHandleMemoryAccessPageCheckerCallback, &State);
1557	if (RT_SUCCESS(rc))
1558	{
1559	if (Info.fNemProt & ( pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite
1560	? NEM_PAGE_PROT_WRITE : NEM_PAGE_PROT_READ))
1561	{
1562	if (State.fCanResume)
1563	{
1564	Log4(("MemExit/%u: %04x:%08RX64/%s: %RGp (=>%RHp) %s fProt=%u%s%s%s; restarting (%s)\n",
1565	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1566	pExit->MemoryAccess.Gpa, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1567	Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1568	State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pExit->MemoryAccess.AccessInfo.AccessType]));
1569	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_MEMORY_ACCESS),
1570	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, uHostTsc);
1571	return VINF_SUCCESS;
1572	}
1573	}
1574	Log4(("MemExit/%u: %04x:%08RX64/%s: %RGp (=>%RHp) %s fProt=%u%s%s%s; emulating (%s)\n",
1575	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1576	pExit->MemoryAccess.Gpa, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1577	Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1578	State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pExit->MemoryAccess.AccessInfo.AccessType]));
1579	}
1580	else
1581	Log4(("MemExit/%u: %04x:%08RX64/%s: %RGp rc=%Rrc%s; emulating (%s)\n",
1582	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1583	pExit->MemoryAccess.Gpa, rc, State.fDidSomething ? " modified-backing" : "",
1584	g_apszHvInterceptAccessTypes[pExit->MemoryAccess.AccessInfo.AccessType]));
1585
1586	/*
1587	* Emulate the memory access, either access handler or special memory.
1588	*/
1589	PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu,
1590	pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite
1591	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1592	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1593	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, uHostTsc);
1594	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1595	rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM \| CPUMCTX_EXTRN_DS \| CPUMCTX_EXTRN_ES);
1596	AssertRCReturn(rc, rc);
1597	if (pExit->VpContext.ExecutionState.Reserved0 \|\| pExit->VpContext.ExecutionState.Reserved1)
1598	Log(("MemExit/Hdr/State: Reserved0=%#x Reserved1=%#x\n", pExit->VpContext.ExecutionState.Reserved0, pExit->VpContext.ExecutionState.Reserved1));
1599
1600	VBOXSTRICTRC rcStrict;
1601	if (!pExitRec)
1602	{
1603	//if (pMsg->InstructionByteCount > 0)
1604	// Log4(("InstructionByteCount=%#x %.16Rhxs\n", pMsg->InstructionByteCount, pMsg->InstructionBytes));
1605	if (pExit->MemoryAccess.InstructionByteCount > 0)
1606	rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, pExit->VpContext.Rip, pExit->MemoryAccess.InstructionBytes, pExit->MemoryAccess.InstructionByteCount);
1607	else
1608	rcStrict = IEMExecOne(pVCpu);
1609	/** @todo do we need to do anything wrt debugging here? */
1610	}
1611	else
1612	{
1613	/* Frequent access or probing. */
1614	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
1615	Log4(("MemExit/%u: %04x:%08RX64/%s: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
1616	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1617	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1618	}
1619	return rcStrict;
1620	}
1621
1622
1623	/**
1624	* Deals with I/O port access exits (WHvRunVpExitReasonX64IoPortAccess).
1625	*
1626	* @returns Strict VBox status code.
1627	* @param pVM The cross context VM structure.
1628	* @param pVCpu The cross context per CPU structure.
1629	* @param pExit The VM exit information to handle.
1630	* @sa nemHCWinHandleMessageIoPort
1631	*/
1632	NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitIoPort(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1633	{
1634	Assert( pExit->IoPortAccess.AccessInfo.AccessSize == 1
1635	\|\| pExit->IoPortAccess.AccessInfo.AccessSize == 2
1636	\|\| pExit->IoPortAccess.AccessInfo.AccessSize == 4);
1637
1638	/*
1639	* Whatever we do, we must clear pending event injection upon resume.
1640	*/
1641	if (pExit->VpContext.ExecutionState.InterruptionPending)
1642	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
1643
1644	/*
1645	* Add history first to avoid two paths doing EMHistoryExec calls.
1646	*/
1647	PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu,
1648	!pExit->IoPortAccess.AccessInfo.StringOp
1649	? ( pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite
1650	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE)
1651	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ))
1652	: ( pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite
1653	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)
1654	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)),
1655	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
1656	if (!pExitRec)
1657	{
1658	VBOXSTRICTRC rcStrict;
1659	if (!pExit->IoPortAccess.AccessInfo.StringOp)
1660	{
1661	/*
1662	* Simple port I/O.
1663	*/
1664	static uint32_t const s_fAndMask[8] =
1665	{ UINT32_MAX, UINT32_C(0xff), UINT32_C(0xffff), UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX };
1666	uint32_t const fAndMask = s_fAndMask[pExit->IoPortAccess.AccessInfo.AccessSize];
1667	if (pExit->IoPortAccess.AccessInfo.IsWrite)
1668	{
1669	rcStrict = IOMIOPortWrite(pVM, pVCpu, pExit->IoPortAccess.PortNumber,
1670	(uint32_t)pExit->IoPortAccess.Rax & fAndMask,
1671	pExit->IoPortAccess.AccessInfo.AccessSize);
1672	Log4(("IOExit/%u: %04x:%08RX64/%s: OUT %#x, %#x LB %u rcStrict=%Rrc\n",
1673	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1674	pExit->IoPortAccess.PortNumber, (uint32_t)pExit->IoPortAccess.Rax & fAndMask,
1675	pExit->IoPortAccess.AccessInfo.AccessSize, VBOXSTRICTRC_VAL(rcStrict) ));
1676	if (IOM_SUCCESS(rcStrict))
1677	{
1678	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1679	nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pExit->VpContext, 1);
1680	}
1681	}
1682	else
1683	{
1684	uint32_t uValue = 0;
1685	rcStrict = IOMIOPortRead(pVM, pVCpu, pExit->IoPortAccess.PortNumber, &uValue,
1686	pExit->IoPortAccess.AccessInfo.AccessSize);
1687	Log4(("IOExit/%u: %04x:%08RX64/%s: IN %#x LB %u -> %#x, rcStrict=%Rrc\n",
1688	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1689	pExit->IoPortAccess.PortNumber, pExit->IoPortAccess.AccessInfo.AccessSize, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1690	if (IOM_SUCCESS(rcStrict))
1691	{
1692	if (pExit->IoPortAccess.AccessInfo.AccessSize != 4)
1693	pVCpu->cpum.GstCtx.rax = (pExit->IoPortAccess.Rax & ~(uint64_t)fAndMask) \| (uValue & fAndMask);
1694	else
1695	pVCpu->cpum.GstCtx.rax = uValue;
1696	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_RAX;
1697	Log4(("IOExit/%u: RAX %#RX64 -> %#RX64\n", pVCpu->idCpu, pExit->IoPortAccess.Rax, pVCpu->cpum.GstCtx.rax));
1698	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1699	nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pExit->VpContext, 1);
1700	}
1701	}
1702	}
1703	else
1704	{
1705	/*
1706	* String port I/O.
1707	*/
1708	/** @todo Someone at Microsoft please explain how we can get the address mode
1709	* from the IoPortAccess.VpContext. CS.Attributes is only sufficient for
1710	* getting the default mode, it can always be overridden by a prefix. This
1711	* forces us to interpret the instruction from opcodes, which is suboptimal.
1712	* Both AMD-V and VT-x includes the address size in the exit info, at least on
1713	* CPUs that are reasonably new.
1714	*
1715	* Of course, it's possible this is an undocumented and we just need to do some
1716	* experiments to figure out how it's communicated. Alternatively, we can scan
1717	* the opcode bytes for possible evil prefixes.
1718	*/
1719	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1720	pVCpu->cpum.GstCtx.fExtrn &= ~( CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX \| CPUMCTX_EXTRN_RDI \| CPUMCTX_EXTRN_RSI
1721	\| CPUMCTX_EXTRN_DS \| CPUMCTX_EXTRN_ES);
1722	NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.ds, pExit->IoPortAccess.Ds);
1723	NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.es, pExit->IoPortAccess.Es);
1724	pVCpu->cpum.GstCtx.rax = pExit->IoPortAccess.Rax;
1725	pVCpu->cpum.GstCtx.rcx = pExit->IoPortAccess.Rcx;
1726	pVCpu->cpum.GstCtx.rdi = pExit->IoPortAccess.Rdi;
1727	pVCpu->cpum.GstCtx.rsi = pExit->IoPortAccess.Rsi;
1728	int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1729	AssertRCReturn(rc, rc);
1730
1731	Log4(("IOExit/%u: %04x:%08RX64/%s: %s%s %#x LB %u (emulating)\n",
1732	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1733	pExit->IoPortAccess.AccessInfo.RepPrefix ? "REP " : "",
1734	pExit->IoPortAccess.AccessInfo.IsWrite ? "OUTS" : "INS",
1735	pExit->IoPortAccess.PortNumber, pExit->IoPortAccess.AccessInfo.AccessSize ));
1736	rcStrict = IEMExecOne(pVCpu);
1737	}
1738	if (IOM_SUCCESS(rcStrict))
1739	{
1740	/*
1741	* Do debug checks.
1742	*/
1743	if ( pExit->VpContext.ExecutionState.DebugActive /** @todo Microsoft: Does DebugActive this only reflect DR7? */
1744	\|\| (pExit->VpContext.Rflags & X86_EFL_TF)
1745	\|\| DBGFBpIsHwIoArmed(pVM) )
1746	{
1747	/** @todo Debugging. */
1748	}
1749	}
1750	return rcStrict;
1751	}
1752
1753	/*
1754	* Frequent exit or something needing probing.
1755	* Get state and call EMHistoryExec.
1756	*/
1757	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1758	if (!pExit->IoPortAccess.AccessInfo.StringOp)
1759	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_RAX;
1760	else
1761	{
1762	pVCpu->cpum.GstCtx.fExtrn &= ~( CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX \| CPUMCTX_EXTRN_RDI \| CPUMCTX_EXTRN_RSI
1763	\| CPUMCTX_EXTRN_DS \| CPUMCTX_EXTRN_ES);
1764	NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.ds, pExit->IoPortAccess.Ds);
1765	NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.es, pExit->IoPortAccess.Es);
1766	pVCpu->cpum.GstCtx.rcx = pExit->IoPortAccess.Rcx;
1767	pVCpu->cpum.GstCtx.rdi = pExit->IoPortAccess.Rdi;
1768	pVCpu->cpum.GstCtx.rsi = pExit->IoPortAccess.Rsi;
1769	}
1770	pVCpu->cpum.GstCtx.rax = pExit->IoPortAccess.Rax;
1771	int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1772	AssertRCReturn(rc, rc);
1773	Log4(("IOExit/%u: %04x:%08RX64/%s: %s%s%s %#x LB %u -> EMHistoryExec\n",
1774	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1775	pExit->IoPortAccess.AccessInfo.RepPrefix ? "REP " : "",
1776	pExit->IoPortAccess.AccessInfo.IsWrite ? "OUT" : "IN",
1777	pExit->IoPortAccess.AccessInfo.StringOp ? "S" : "",
1778	pExit->IoPortAccess.PortNumber, pExit->IoPortAccess.AccessInfo.AccessSize));
1779	VBOXSTRICTRC rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
1780	Log4(("IOExit/%u: %04x:%08RX64/%s: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
1781	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1782	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1783	return rcStrict;
1784	}
1785
1786
1787	/**
1788	* Deals with interrupt window exits (WHvRunVpExitReasonX64InterruptWindow).
1789	*
1790	* @returns Strict VBox status code.
1791	* @param pVM The cross context VM structure.
1792	* @param pVCpu The cross context per CPU structure.
1793	* @param pExit The VM exit information to handle.
1794	* @sa nemHCWinHandleMessageInterruptWindow
1795	*/
1796	NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitInterruptWindow(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1797	{
1798	/*
1799	* Assert message sanity.
1800	*/
1801	AssertMsg( pExit->InterruptWindow.DeliverableType == WHvX64PendingInterrupt
1802	\|\| pExit->InterruptWindow.DeliverableType == WHvX64PendingNmi,
1803	("%#x\n", pExit->InterruptWindow.DeliverableType));
1804
1805	/*
1806	* Just copy the state we've got and handle it in the loop for now.
1807	*/
1808	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW),
1809	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
1810
1811	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1812	Log4(("IntWinExit/%u: %04x:%08RX64/%s: %u IF=%d InterruptShadow=%d CR8=%#x\n",
1813	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1814	pExit->InterruptWindow.DeliverableType, RT_BOOL(pExit->VpContext.Rflags & X86_EFL_IF),
1815	pExit->VpContext.ExecutionState.InterruptShadow, pExit->VpContext.Cr8));
1816
1817	pVCpu->nem.s.fIrqWindowRegistered = false;
1818	pVCpu->nem.s.fPicReadyForInterrupt = true;
1819
1820	/** @todo call nemHCWinHandleInterruptFF */
1821	RT_NOREF(pVM);
1822	return VINF_SUCCESS;
1823	}
1824
1825
1826	/**
1827	* Deals with CPUID exits (WHvRunVpExitReasonX64Cpuid).
1828	*
1829	* @returns Strict VBox status code.
1830	* @param pVM The cross context VM structure.
1831	* @param pVCpu The cross context per CPU structure.
1832	* @param pExit The VM exit information to handle.
1833	* @sa nemHCWinHandleMessageCpuId
1834	*/
1835	NEM_TMPL_STATIC VBOXSTRICTRC
1836	nemR3WinHandleExitCpuId(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1837	{
1838	PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CPUID),
1839	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
1840	if (!pExitRec)
1841	{
1842	/*
1843	* Soak up state and execute the instruction.
1844	*/
1845	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1846	VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu,
1847	IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK
1848	\| CPUMCTX_EXTRN_CR3, /* May call PGMChangeMode() requiring cr3 (due to cr0 being imported). */
1849	"CPUID");
1850	if (rcStrict == VINF_SUCCESS)
1851	{
1852	/* Copy in the low register values (top is always cleared). */
1853	pVCpu->cpum.GstCtx.rax = (uint32_t)pExit->CpuidAccess.Rax;
1854	pVCpu->cpum.GstCtx.rcx = (uint32_t)pExit->CpuidAccess.Rcx;
1855	pVCpu->cpum.GstCtx.rdx = (uint32_t)pExit->CpuidAccess.Rdx;
1856	pVCpu->cpum.GstCtx.rbx = (uint32_t)pExit->CpuidAccess.Rbx;
1857	pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX \| CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RBX);
1858
1859	/* Execute the decoded instruction. */
1860	rcStrict = IEMExecDecodedCpuid(pVCpu, pExit->VpContext.InstructionLength);
1861
1862	Log4(("CpuIdExit/%u: %04x:%08RX64/%s: rax=%08RX64 / rcx=%08RX64 / rdx=%08RX64 / rbx=%08RX64 -> %08RX32 / %08RX32 / %08RX32 / %08RX32 (hv: %08RX64 / %08RX64 / %08RX64 / %08RX64)\n",
1863	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1864	pExit->CpuidAccess.Rax, pExit->CpuidAccess.Rcx, pExit->CpuidAccess.Rdx, pExit->CpuidAccess.Rbx,
1865	pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.edx, pVCpu->cpum.GstCtx.ebx,
1866	pExit->CpuidAccess.DefaultResultRax, pExit->CpuidAccess.DefaultResultRcx, pExit->CpuidAccess.DefaultResultRdx, pExit->CpuidAccess.DefaultResultRbx));
1867	}
1868
1869	RT_NOREF_PV(pVM);
1870	return rcStrict;
1871	}
1872
1873	/*
1874	* Frequent exit or something needing probing.
1875	* Get state and call EMHistoryExec.
1876	*/
1877	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1878	pVCpu->cpum.GstCtx.rax = pExit->CpuidAccess.Rax;
1879	pVCpu->cpum.GstCtx.rcx = pExit->CpuidAccess.Rcx;
1880	pVCpu->cpum.GstCtx.rdx = pExit->CpuidAccess.Rdx;
1881	pVCpu->cpum.GstCtx.rbx = pExit->CpuidAccess.Rbx;
1882	pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX \| CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RBX);
1883	Log4(("CpuIdExit/%u: %04x:%08RX64/%s: rax=%08RX64 / rcx=%08RX64 / rdx=%08RX64 / rbx=%08RX64 (hv: %08RX64 / %08RX64 / %08RX64 / %08RX64) ==> EMHistoryExec\n",
1884	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1885	pExit->CpuidAccess.Rax, pExit->CpuidAccess.Rcx, pExit->CpuidAccess.Rdx, pExit->CpuidAccess.Rbx,
1886	pExit->CpuidAccess.DefaultResultRax, pExit->CpuidAccess.DefaultResultRcx, pExit->CpuidAccess.DefaultResultRdx, pExit->CpuidAccess.DefaultResultRbx));
1887	int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1888	AssertRCReturn(rc, rc);
1889	VBOXSTRICTRC rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
1890	Log4(("CpuIdExit/%u: %04x:%08RX64/%s: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
1891	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1892	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1893	return rcStrict;
1894	}
1895
1896
1897	/**
1898	* Deals with MSR access exits (WHvRunVpExitReasonX64MsrAccess).
1899	*
1900	* @returns Strict VBox status code.
1901	* @param pVM The cross context VM structure.
1902	* @param pVCpu The cross context per CPU structure.
1903	* @param pExit The VM exit information to handle.
1904	* @sa nemHCWinHandleMessageMsr
1905	*/
1906	NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitMsr(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1907	{
1908	/*
1909	* Check CPL as that's common to both RDMSR and WRMSR.
1910	*/
1911	VBOXSTRICTRC rcStrict;
1912	if (pExit->VpContext.ExecutionState.Cpl == 0)
1913	{
1914	/*
1915	* Get all the MSR state. Since we're getting EFER, we also need to
1916	* get CR0, CR4 and CR3.
1917	*/
1918	PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu,
1919	pExit->MsrAccess.AccessInfo.IsWrite
1920	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE)
1921	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ),
1922	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
1923	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1924	rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu,
1925	(!pExitRec ? 0 : IEM_CPUMCTX_EXTRN_MUST_MASK)
1926	\| CPUMCTX_EXTRN_ALL_MSRS \| CPUMCTX_EXTRN_CR0
1927	\| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4,
1928	"MSRs");
1929	if (rcStrict == VINF_SUCCESS)
1930	{
1931	if (!pExitRec)
1932	{
1933	/*
1934	* Handle writes.
1935	*/
1936	if (pExit->MsrAccess.AccessInfo.IsWrite)
1937	{
1938	rcStrict = CPUMSetGuestMsr(pVCpu, pExit->MsrAccess.MsrNumber,
1939	RT_MAKE_U64((uint32_t)pExit->MsrAccess.Rax, (uint32_t)pExit->MsrAccess.Rdx));
1940	Log4(("MsrExit/%u: %04x:%08RX64/%s: WRMSR %08x, %08x:%08x -> %Rrc\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
1941	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->MsrAccess.MsrNumber,
1942	(uint32_t)pExit->MsrAccess.Rax, (uint32_t)pExit->MsrAccess.Rdx, VBOXSTRICTRC_VAL(rcStrict) ));
1943	if (rcStrict == VINF_SUCCESS)
1944	{
1945	nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pExit->VpContext, 2);
1946	return VINF_SUCCESS;
1947	}
1948	LogRel(("MsrExit/%u: %04x:%08RX64/%s: WRMSR %08x, %08x:%08x -> %Rrc!\n", pVCpu->idCpu,
1949	pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1950	pExit->MsrAccess.MsrNumber, (uint32_t)pExit->MsrAccess.Rax, (uint32_t)pExit->MsrAccess.Rdx,
1951	VBOXSTRICTRC_VAL(rcStrict) ));
1952	}
1953	/*
1954	* Handle reads.
1955	*/
1956	else
1957	{
1958	uint64_t uValue = 0;
1959	rcStrict = CPUMQueryGuestMsr(pVCpu, pExit->MsrAccess.MsrNumber, &uValue);
1960	Log4(("MsrExit/%u: %04x:%08RX64/%s: RDMSR %08x -> %08RX64 / %Rrc\n", pVCpu->idCpu,
1961	pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1962	pExit->MsrAccess.MsrNumber, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1963	if (rcStrict == VINF_SUCCESS)
1964	{
1965	pVCpu->cpum.GstCtx.rax = (uint32_t)uValue;
1966	pVCpu->cpum.GstCtx.rdx = uValue >> 32;
1967	pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RDX);
1968	nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pExit->VpContext, 2);
1969	return VINF_SUCCESS;
1970	}
1971	LogRel(("MsrExit/%u: %04x:%08RX64/%s: RDMSR %08x -> %08RX64 / %Rrc\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
1972	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->MsrAccess.MsrNumber,
1973	uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1974	}
1975	}
1976	else
1977	{
1978	/*
1979	* Handle frequent exit or something needing probing.
1980	*/
1981	Log4(("MsrExit/%u: %04x:%08RX64/%s: %sMSR %#08x\n",
1982	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1983	pExit->MsrAccess.AccessInfo.IsWrite ? "WR" : "RD", pExit->MsrAccess.MsrNumber));
1984	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
1985	Log4(("MsrExit/%u: %04x:%08RX64/%s: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
1986	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1987	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1988	return rcStrict;
1989	}
1990	}
1991	else
1992	{
1993	LogRel(("MsrExit/%u: %04x:%08RX64/%s: %sMSR %08x -> %Rrc - msr state import\n",
1994	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1995	pExit->MsrAccess.AccessInfo.IsWrite ? "WR" : "RD", pExit->MsrAccess.MsrNumber, VBOXSTRICTRC_VAL(rcStrict) ));
1996	return rcStrict;
1997	}
1998	}
1999	else if (pExit->MsrAccess.AccessInfo.IsWrite)
2000	Log4(("MsrExit/%u: %04x:%08RX64/%s: CPL %u -> #GP(0); WRMSR %08x, %08x:%08x\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2001	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.ExecutionState.Cpl,
2002	pExit->MsrAccess.MsrNumber, (uint32_t)pExit->MsrAccess.Rax, (uint32_t)pExit->MsrAccess.Rdx ));
2003	else
2004	Log4(("MsrExit/%u: %04x:%08RX64/%s: CPL %u -> #GP(0); RDMSR %08x\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2005	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.ExecutionState.Cpl,
2006	pExit->MsrAccess.MsrNumber));
2007
2008	/*
2009	* If we get down here, we're supposed to #GP(0).
2010	*/
2011	rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM \| CPUMCTX_EXTRN_ALL_MSRS, "MSR");
2012	if (rcStrict == VINF_SUCCESS)
2013	{
2014	rcStrict = IEMInjectTrap(pVCpu, X86_XCPT_GP, TRPM_TRAP, 0, 0, 0);
2015	if (rcStrict == VINF_IEM_RAISED_XCPT)
2016	rcStrict = VINF_SUCCESS;
2017	else if (rcStrict != VINF_SUCCESS)
2018	Log4(("MsrExit/%u: Injecting #GP(0) failed: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict) ));
2019	}
2020
2021	RT_NOREF_PV(pVM);
2022	return rcStrict;
2023	}
2024
2025
2026	/**
2027	* Worker for nemHCWinHandleMessageException & nemR3WinHandleExitException that
2028	* checks if the given opcodes are of interest at all.
2029	*
2030	* @returns true if interesting, false if not.
2031	* @param cbOpcodes Number of opcode bytes available.
2032	* @param pbOpcodes The opcode bytes.
2033	* @param f64BitMode Whether we're in 64-bit mode.
2034	*/
2035	DECLINLINE(bool) nemHcWinIsInterestingUndefinedOpcode(uint8_t cbOpcodes, uint8_t const *pbOpcodes, bool f64BitMode)
2036	{
2037	/*
2038	* Currently only interested in VMCALL and VMMCALL.
2039	*/
2040	while (cbOpcodes >= 3)
2041	{
2042	switch (pbOpcodes[0])
2043	{
2044	case 0x0f:
2045	switch (pbOpcodes[1])
2046	{
2047	case 0x01:
2048	switch (pbOpcodes[2])
2049	{
2050	case 0xc1: /* 0f 01 c1 VMCALL */
2051	return true;
2052	case 0xd9: /* 0f 01 d9 VMMCALL */
2053	return true;
2054	default:
2055	break;
2056	}
2057	break;
2058	}
2059	break;
2060
2061	default:
2062	return false;
2063
2064	/* prefixes */
2065	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
2066	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2067	if (!f64BitMode)
2068	return false;
2069	RT_FALL_THRU();
2070	case X86_OP_PRF_CS:
2071	case X86_OP_PRF_SS:
2072	case X86_OP_PRF_DS:
2073	case X86_OP_PRF_ES:
2074	case X86_OP_PRF_FS:
2075	case X86_OP_PRF_GS:
2076	case X86_OP_PRF_SIZE_OP:
2077	case X86_OP_PRF_SIZE_ADDR:
2078	case X86_OP_PRF_LOCK:
2079	case X86_OP_PRF_REPZ:
2080	case X86_OP_PRF_REPNZ:
2081	cbOpcodes--;
2082	pbOpcodes++;
2083	continue;
2084	}
2085	break;
2086	}
2087	return false;
2088	}
2089
2090
2091	/**
2092	* Copies state included in a exception intercept exit.
2093	*
2094	* @param pVCpu The cross context per CPU structure.
2095	* @param pExit The VM exit information.
2096	* @param fClearXcpt Clear pending exception.
2097	*/
2098	DECLINLINE(void) nemR3WinCopyStateFromExceptionMessage(PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit, bool fClearXcpt)
2099	{
2100	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
2101	if (fClearXcpt)
2102	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
2103	}
2104
2105
2106	/**
2107	* Advances the guest RIP by the number of bytes specified in @a cb.
2108	*
2109	* @param pVCpu The cross context virtual CPU structure.
2110	* @param cb RIP increment value in bytes.
2111	*/
2112	DECLINLINE(void) nemHcWinAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
2113	{
2114	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2115	pCtx->rip += cb;
2116	/** @todo Why not clear RF too? */
2117	CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
2118	}
2119
2120
2121	/**
2122	* Hacks its way around the lovely mesa driver's backdoor accesses.
2123	*
2124	* @sa hmR0VmxHandleMesaDrvGp
2125	* @sa hmR0SvmHandleMesaDrvGp
2126	*/
2127	static int nemHcWinHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx)
2128	{
2129	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK)));
2130	RT_NOREF(pCtx);
2131
2132	/* For now we'll just skip the instruction. */
2133	nemHcWinAdvanceRip(pVCpu, 1);
2134	return VINF_SUCCESS;
2135	}
2136
2137
2138	/**
2139	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
2140	* backdoor logging w/o checking what it is running inside.
2141	*
2142	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
2143	* backdoor port and magic numbers loaded in registers.
2144	*
2145	* @returns true if it is, false if it isn't.
2146	* @sa hmR0VmxIsMesaDrvGp
2147	* @sa hmR0SvmIsMesaDrvGp
2148	*/
2149	DECLINLINE(bool) nemHcWinIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, const uint8_t *pbInsn, uint32_t cbInsn)
2150	{
2151	/* #GP(0) is already checked by caller. */
2152
2153	/* Check magic and port. */
2154	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RAX)));
2155	if (pCtx->dx != UINT32_C(0x5658))
2156	return false;
2157	if (pCtx->rax != UINT32_C(0x564d5868))
2158	return false;
2159
2160	/* Flat ring-3 CS. */
2161	if (CPUMGetGuestCPL(pVCpu) != 3)
2162	return false;
2163	if (pCtx->cs.u64Base != 0)
2164	return false;
2165
2166	/* 0xed: IN eAX,dx */
2167	if (cbInsn < 1) /* Play safe (shouldn't happen). */
2168	{
2169	uint8_t abInstr[1];
2170	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
2171	if (RT_FAILURE(rc))
2172	return false;
2173	if (abInstr[0] != 0xed)
2174	return false;
2175	}
2176	else
2177	{
2178	if (pbInsn[0] != 0xed)
2179	return false;
2180	}
2181
2182	return true;
2183	}
2184
2185
2186	/**
2187	* Deals with MSR access exits (WHvRunVpExitReasonException).
2188	*
2189	* @returns Strict VBox status code.
2190	* @param pVM The cross context VM structure.
2191	* @param pVCpu The cross context per CPU structure.
2192	* @param pExit The VM exit information to handle.
2193	* @sa nemR3WinHandleExitException
2194	*/
2195	NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitException(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
2196	{
2197	/*
2198	* Get most of the register state since we'll end up making IEM inject the
2199	* event. The exception isn't normally flaged as a pending event, so duh.
2200	*
2201	* Note! We can optimize this later with event injection.
2202	*/
2203	Log4(("XcptExit/%u: %04x:%08RX64/%s: %x errcd=%#x parm=%RX64\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2204	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpException.ExceptionType,
2205	pExit->VpException.ErrorCode, pExit->VpException.ExceptionParameter ));
2206	nemR3WinCopyStateFromExceptionMessage(pVCpu, pExit, true /fClearXcpt/);
2207	uint64_t fWhat = NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
2208	if (pExit->VpException.ExceptionType == X86_XCPT_DB)
2209	fWhat \|= CPUMCTX_EXTRN_DR0_DR3 \| CPUMCTX_EXTRN_DR7 \| CPUMCTX_EXTRN_DR6;
2210	VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, fWhat, "Xcpt");
2211	if (rcStrict != VINF_SUCCESS)
2212	return rcStrict;
2213
2214	/*
2215	* Handle the intercept.
2216	*/
2217	TRPMEVENT enmEvtType = TRPM_TRAP;
2218	switch (pExit->VpException.ExceptionType)
2219	{
2220	/*
2221	* We get undefined opcodes on VMMCALL(AMD) & VMCALL(Intel) instructions
2222	* and need to turn them over to GIM.
2223	*
2224	* Note! We do not check fGIMTrapXcptUD here ASSUMING that GIM only wants
2225	* #UD for handling non-native hypercall instructions. (IEM will
2226	* decode both and let the GIM provider decide whether to accept it.)
2227	*/
2228	case X86_XCPT_UD:
2229	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionUd);
2230	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_UD),
2231	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2232	if (nemHcWinIsInterestingUndefinedOpcode(pExit->VpException.InstructionByteCount, pExit->VpException.InstructionBytes,
2233	pExit->VpContext.ExecutionState.EferLma && pExit->VpContext.Cs.Long ))
2234	{
2235	rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, pExit->VpContext.Rip,
2236	pExit->VpException.InstructionBytes,
2237	pExit->VpException.InstructionByteCount);
2238	Log4(("XcptExit/%u: %04x:%08RX64/%s: #UD -> emulated -> %Rrc\n",
2239	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip,
2240	nemR3WinExecStateToLogStr(&pExit->VpContext), VBOXSTRICTRC_VAL(rcStrict) ));
2241	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionUdHandled);
2242	return rcStrict;
2243	}
2244
2245	Log4(("XcptExit/%u: %04x:%08RX64/%s: #UD [%.*Rhxs] -> re-injected\n", pVCpu->idCpu,
2246	pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
2247	pExit->VpException.InstructionByteCount, pExit->VpException.InstructionBytes ));
2248	break;
2249
2250	/*
2251	* Workaround the lovely mesa driver assuming that vmsvga means vmware
2252	* hypervisor and tries to log stuff to the host.
2253	*/
2254	case X86_XCPT_GP:
2255	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionGp);
2256	/** @todo r=bird: Need workaround in IEM for this, right?
2257	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_GP),
2258	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); */
2259	if ( !pVCpu->nem.s.fTrapXcptGpForLovelyMesaDrv
2260	\|\| !nemHcWinIsMesaDrvGp(pVCpu, &pVCpu->cpum.GstCtx, pExit->VpException.InstructionBytes,
2261	pExit->VpException.InstructionByteCount))
2262	{
2263	#if 1 /** @todo Need to emulate instruction or we get a triple fault when trying to inject the \#GP... */
2264	rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, pExit->VpContext.Rip,
2265	pExit->VpException.InstructionBytes,
2266	pExit->VpException.InstructionByteCount);
2267	Log4(("XcptExit/%u: %04x:%08RX64/%s: #GP -> emulated -> %Rrc\n",
2268	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip,
2269	nemR3WinExecStateToLogStr(&pExit->VpContext), VBOXSTRICTRC_VAL(rcStrict) ));
2270	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionUdHandled);
2271	return rcStrict;
2272	#else
2273	break;
2274	#endif
2275	}
2276	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionGpMesa);
2277	return nemHcWinHandleMesaDrvGp(pVCpu, &pVCpu->cpum.GstCtx);
2278
2279	/*
2280	* Filter debug exceptions.
2281	*/
2282	case X86_XCPT_DB:
2283	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionDb);
2284	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_DB),
2285	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2286	Log4(("XcptExit/%u: %04x:%08RX64/%s: #DB - TODO\n",
2287	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext) ));
2288	break;
2289
2290	case X86_XCPT_BP:
2291	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionBp);
2292	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_BP),
2293	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2294	Log4(("XcptExit/%u: %04x:%08RX64/%s: #BP - TODO - %u\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2295	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.InstructionLength));
2296	enmEvtType = TRPM_SOFTWARE_INT; /* We're at the INT3 instruction, not after it. */
2297	break;
2298
2299	/* This shouldn't happen. */
2300	default:
2301	AssertLogRelMsgFailedReturn(("ExceptionType=%#x\n", pExit->VpException.ExceptionType), VERR_IEM_IPE_6);
2302	}
2303
2304	/*
2305	* Inject it.
2306	*/
2307	rcStrict = IEMInjectTrap(pVCpu, pExit->VpException.ExceptionType, enmEvtType, pExit->VpException.ErrorCode,
2308	pExit->VpException.ExceptionParameter /??/, pExit->VpContext.InstructionLength);
2309	Log4(("XcptExit/%u: %04x:%08RX64/%s: %#u -> injected -> %Rrc\n",
2310	pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip,
2311	nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpException.ExceptionType, VBOXSTRICTRC_VAL(rcStrict) ));
2312
2313	RT_NOREF_PV(pVM);
2314	return rcStrict;
2315	}
2316
2317
2318	/**
2319	* Deals with MSR access exits (WHvRunVpExitReasonUnrecoverableException).
2320	*
2321	* @returns Strict VBox status code.
2322	* @param pVM The cross context VM structure.
2323	* @param pVCpu The cross context per CPU structure.
2324	* @param pExit The VM exit information to handle.
2325	* @sa nemHCWinHandleMessageUnrecoverableException
2326	*/
2327	NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitUnrecoverableException(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
2328	{
2329	#if 0
2330	/*
2331	* Just copy the state we've got and handle it in the loop for now.
2332	*/
2333	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
2334	Log(("TripleExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> VINF_EM_TRIPLE_FAULT\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2335	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags));
2336	RT_NOREF_PV(pVM);
2337	return VINF_EM_TRIPLE_FAULT;
2338	#else
2339	/*
2340	* Let IEM decide whether this is really it.
2341	*/
2342	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_UNRECOVERABLE_EXCEPTION),
2343	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2344	nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
2345	VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM \| CPUMCTX_EXTRN_ALL, "TripleExit");
2346	if (rcStrict == VINF_SUCCESS)
2347	{
2348	rcStrict = IEMExecOne(pVCpu);
2349	if (rcStrict == VINF_SUCCESS)
2350	{
2351	Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> VINF_SUCCESS\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2352	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags));
2353	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT; /* Make sure to reset pending #DB(0). */
2354	return VINF_SUCCESS;
2355	}
2356	if (rcStrict == VINF_EM_TRIPLE_FAULT)
2357	Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> VINF_EM_TRIPLE_FAULT!\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2358	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2359	else
2360	Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> %Rrc (IEMExecOne)\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2361	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2362	}
2363	else
2364	Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> %Rrc (state import)\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2365	pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2366	RT_NOREF_PV(pVM);
2367	return rcStrict;
2368	#endif
2369	}
2370
2371
2372	/**
2373	* Handles VM exits.
2374	*
2375	* @returns Strict VBox status code.
2376	* @param pVM The cross context VM structure.
2377	* @param pVCpu The cross context per CPU structure.
2378	* @param pExit The VM exit information to handle.
2379	* @sa nemHCWinHandleMessage
2380	*/
2381	NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExit(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
2382	{
2383	switch (pExit->ExitReason)
2384	{
2385	case WHvRunVpExitReasonMemoryAccess:
2386	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMemUnmapped);
2387	return nemR3WinHandleExitMemory(pVM, pVCpu, pExit);
2388
2389	case WHvRunVpExitReasonX64IoPortAccess:
2390	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitPortIo);
2391	return nemR3WinHandleExitIoPort(pVM, pVCpu, pExit);
2392
2393	case WHvRunVpExitReasonX64Halt:
2394	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);
2395	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT),
2396	pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2397	Log4(("HaltExit/%u\n", pVCpu->idCpu));
2398	return VINF_EM_HALT;
2399
2400	case WHvRunVpExitReasonCanceled:
2401	Log4(("CanceledExit/%u\n", pVCpu->idCpu));
2402	return VINF_SUCCESS;
2403
2404	case WHvRunVpExitReasonX64InterruptWindow:
2405	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInterruptWindow);
2406	return nemR3WinHandleExitInterruptWindow(pVM, pVCpu, pExit);
2407
2408	case WHvRunVpExitReasonX64Cpuid:
2409	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitCpuId);
2410	return nemR3WinHandleExitCpuId(pVM, pVCpu, pExit);
2411
2412	case WHvRunVpExitReasonX64MsrAccess:
2413	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMsr);
2414	return nemR3WinHandleExitMsr(pVM, pVCpu, pExit);
2415
2416	case WHvRunVpExitReasonException:
2417	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitException);
2418	return nemR3WinHandleExitException(pVM, pVCpu, pExit);
2419
2420	case WHvRunVpExitReasonUnrecoverableException:
2421	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitUnrecoverable);
2422	return nemR3WinHandleExitUnrecoverableException(pVM, pVCpu, pExit);
2423
2424	case WHvRunVpExitReasonX64ApicEoi:
2425	Assert(pVM->nem.s.fLocalApicEmulation);
2426	PDMIoApicBroadcastEoi(pVCpu->CTX_SUFF(pVM), pExit->ApicEoi.InterruptVector);
2427	return VINF_SUCCESS;
2428
2429	case WHvRunVpExitReasonUnsupportedFeature:
2430	case WHvRunVpExitReasonInvalidVpRegisterValue:
2431	LogRel(("Unimplemented exit:\n%.Rhxd\n", (int)sizeof(pExit), pExit));
2432	AssertLogRelMsgFailedReturn(("Unexpected exit on CPU #%u: %#x\n%.32Rhxd\n",
2433	pVCpu->idCpu, pExit->ExitReason, pExit), VERR_NEM_IPE_3);
2434
2435	/* Undesired exits: */
2436	case WHvRunVpExitReasonNone:
2437	default:
2438	LogRel(("Unknown exit:\n%.Rhxd\n", (int)sizeof(pExit), pExit));
2439	AssertLogRelMsgFailedReturn(("Unknown exit on CPU #%u: %#x!\n", pVCpu->idCpu, pExit->ExitReason), VERR_NEM_IPE_3);
2440	}
2441	}
2442
2443
2444	/**
2445	* Deals with pending interrupt related force flags, may inject interrupt.
2446	*
2447	* @returns VBox strict status code.
2448	* @param pVM The cross context VM structure.
2449	* @param pVCpu The cross context per CPU structure.
2450	* @param pfInterruptWindows Where to return interrupt window flags.
2451	*/
2452	NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleInterruptFF(PVMCC pVM, PVMCPUCC pVCpu, uint8_t *pfInterruptWindows)
2453	{
2454	Assert(!TRPMHasTrap(pVCpu) && !pVM->nem.s.fLocalApicEmulation);
2455	RT_NOREF_PV(pVM);
2456
2457	/*
2458	* First update APIC. We ASSUME this won't need TPR/CR8.
2459	*/
2460	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2461	{
2462	PDMApicUpdatePendingInterrupts(pVCpu);
2463	if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
2464	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2465	return VINF_SUCCESS;
2466	}
2467
2468	/*
2469	* We don't currently implement SMIs.
2470	*/
2471	AssertReturn(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI), VERR_NEM_IPE_0);
2472
2473	/*
2474	* Check if we've got the minimum of state required for deciding whether we
2475	* can inject interrupts and NMIs. If we don't have it, get all we might require
2476	* for injection via IEM.
2477	*/
2478	bool const fPendingNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2479	uint64_t fNeedExtrn = CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS
2480	\| (fPendingNmi ? CPUMCTX_EXTRN_INHIBIT_NMI : 0);
2481	if (pVCpu->cpum.GstCtx.fExtrn & fNeedExtrn)
2482	{
2483	VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "IntFF");
2484	if (rcStrict != VINF_SUCCESS)
2485	return rcStrict;
2486	}
2487
2488	/*
2489	* NMI? Try deliver it first.
2490	*/
2491	if (fPendingNmi)
2492	{
2493	if ( !CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx)
2494	&& !CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
2495	{
2496	VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "NMI");
2497	if (rcStrict == VINF_SUCCESS)
2498	{
2499	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2500	rcStrict = IEMInjectTrap(pVCpu, X86_XCPT_NMI, TRPM_HARDWARE_INT, 0, 0, 0);
2501	Log8(("Injected NMI on %u (%d)\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2502	}
2503	return rcStrict;
2504	}
2505	*pfInterruptWindows \|= NEM_WIN_INTW_F_NMI;
2506	Log8(("NMI window pending on %u\n", pVCpu->idCpu));
2507	}
2508
2509	/*
2510	* APIC or PIC interrupt?
2511	*/
2512	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
2513	{
2514	/** @todo check NMI inhibiting here too! */
2515	if ( !CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx)
2516	&& pVCpu->cpum.GstCtx.rflags.Bits.u1IF)
2517	{
2518	AssertCompile(NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT & CPUMCTX_EXTRN_APIC_TPR);
2519	VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "NMI");
2520	if (rcStrict == VINF_SUCCESS)
2521	{
2522	uint8_t bInterrupt;
2523	int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
2524	if (RT_SUCCESS(rc))
2525	{
2526	Log8(("Injecting interrupt %#x on %u: %04x:%08RX64 efl=%#x\n", bInterrupt, pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eflags.u));
2527	rcStrict = IEMInjectTrap(pVCpu, bInterrupt, TRPM_HARDWARE_INT, 0, 0, 0);
2528	Log8(("Injected interrupt %#x on %u (%d)\n", bInterrupt, pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2529	}
2530	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
2531	{
2532	*pfInterruptWindows \|= ((bInterrupt >> 4) << NEM_WIN_INTW_F_PRIO_SHIFT) \| NEM_WIN_INTW_F_REGULAR;
2533	Log8(("VERR_APIC_INTR_MASKED_BY_TPR: pfInterruptWindows=%#x\n", pfInterruptWindows));
2534	}
2535	else
2536	Log8(("PDMGetInterrupt failed -> %Rrc\n", rc));
2537	}
2538	return rcStrict;
2539	}
2540
2541	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC) && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
2542	{
2543	/* If only an APIC interrupt is pending, we need to know its priority. Otherwise we'll
2544	* likely get pointless deliverability notifications with IF=1 but TPR still too high.
2545	*/
2546	bool fPendingIntr = false;
2547	uint8_t bTpr = 0;
2548	uint8_t bPendingIntr = 0;
2549	int rc = PDMApicGetTpr(pVCpu, &bTpr, &fPendingIntr, &bPendingIntr);
2550	AssertRC(rc);
2551	*pfInterruptWindows \|= ((bPendingIntr >> 4) << NEM_WIN_INTW_F_PRIO_SHIFT) \| NEM_WIN_INTW_F_REGULAR;
2552	Log8(("Interrupt window pending on %u: %#x (bTpr=%#x fPendingIntr=%d bPendingIntr=%#x)\n",
2553	pVCpu->idCpu, *pfInterruptWindows, bTpr, fPendingIntr, bPendingIntr));
2554	}
2555	else
2556	{
2557	*pfInterruptWindows \|= NEM_WIN_INTW_F_REGULAR;
2558	Log8(("Interrupt window pending on %u: %#x\n", pVCpu->idCpu, *pfInterruptWindows));
2559	}
2560	}
2561
2562	return VINF_SUCCESS;
2563	}
2564
2565
2566	/**
2567	* Inner NEM runloop for windows.
2568	*
2569	* @returns Strict VBox status code.
2570	* @param pVM The cross context VM structure.
2571	* @param pVCpu The cross context per CPU structure.
2572	*/
2573	NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinRunGC(PVMCC pVM, PVMCPUCC pVCpu)
2574	{
2575	LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 <=\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u));
2576	#ifdef LOG_ENABLED
2577	if (LogIs3Enabled())
2578	nemHCWinLogState(pVM, pVCpu);
2579	#endif
2580
2581	/*
2582	* Try switch to NEM runloop state.
2583	*/
2584	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2585	{ /* likely */ }
2586	else
2587	{
2588	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2589	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2590	return VINF_SUCCESS;
2591	}
2592
2593	/*
2594	* The run loop.
2595	*
2596	* Current approach to state updating to use the sledgehammer and sync
2597	* everything every time. This will be optimized later.
2598	*/
2599	const bool fSingleStepping = DBGFIsStepping(pVCpu);
2600	// const uint32_t fCheckVmFFs = !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK
2601	// : VM_FF_HP_R0_PRE_HM_STEP_MASK;
2602	// const uint32_t fCheckCpuFFs = !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK;
2603	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2604	for (unsigned iLoop = 0;; iLoop++)
2605	{
2606	/*
2607	* Pending interrupts or such? Need to check and deal with this prior
2608	* to the state syncing.
2609	*/
2610	pVCpu->nem.s.fDesiredInterruptWindows = 0;
2611	if (!pVM->nem.s.fLocalApicEmulation)
2612	{
2613	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC
2614	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2615	{
2616	/* Try inject interrupt. */
2617	rcStrict = nemHCWinHandleInterruptFF(pVM, pVCpu, &pVCpu->nem.s.fDesiredInterruptWindows);
2618	if (rcStrict == VINF_SUCCESS)
2619	{ /* likely */ }
2620	else
2621	{
2622	LogFlow(("NEM/%u: breaking: nemHCWinHandleInterruptFF -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2623	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2624	break;
2625	}
2626	}
2627	}
2628	else
2629	{
2630	/* We only need to handle the PIC usign ExtInt here, the APIC is handled through the NEM APIC backend. */
2631	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC));
2632
2633	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
2634	pVCpu->nem.s.fDesiredInterruptWindows \|= NEM_WIN_INTW_F_REGULAR;
2635	}
2636
2637	#ifndef NEM_WIN_WITH_A20
2638	/*
2639	* Do not execute in hyper-V if the A20 isn't enabled.
2640	*/
2641	if (PGMPhysIsA20Enabled(pVCpu))
2642	{ /* likely */ }
2643	else
2644	{
2645	rcStrict = VINF_EM_RESCHEDULE_REM;
2646	LogFlow(("NEM/%u: breaking: A20 disabled\n", pVCpu->idCpu));
2647	break;
2648	}
2649	#endif
2650
2651	/*
2652	* Ensure that hyper-V has the whole state.
2653	* (We always update the interrupt windows settings when active as hyper-V seems
2654	* to forget about it after an exit.)
2655	*/
2656	if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK))
2657	!= (CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK)
2658	\|\| ( ( pVCpu->nem.s.fDesiredInterruptWindows
2659	\|\| pVCpu->nem.s.fCurrentInterruptWindows != pVCpu->nem.s.fDesiredInterruptWindows) ) )
2660	{
2661	int rc2 = nemHCWinCopyStateToHyperV(pVM, pVCpu);
2662	AssertRCReturn(rc2, rc2);
2663	}
2664
2665	/*
2666	* Poll timers and run for a bit.
2667	*
2668	* With the VID approach (ring-0 or ring-3) we can specify a timeout here,
2669	* so we take the time of the next timer event and uses that as a deadline.
2670	* The rounding heuristics are "tuned" so that rhel5 (1K timer) will boot fine.
2671	*/
2672	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2673	* the whole polling job when timers have changed... */
2674	uint64_t offDeltaIgnored;
2675	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2676	if ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2677	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2678	{
2679	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
2680	{
2681	#ifdef LOG_ENABLED
2682	if (LogIsFlowEnabled())
2683	{
2684	static const WHV_REGISTER_NAME s_aNames[6] = { WHvX64RegisterCs, WHvX64RegisterRip, WHvX64RegisterRflags,
2685	WHvX64RegisterSs, WHvX64RegisterRsp, WHvX64RegisterCr0 };
2686	WHV_REGISTER_VALUE aRegs[RT_ELEMENTS(s_aNames)] = { { { {0, 0} } } };
2687	WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, s_aNames, RT_ELEMENTS(s_aNames), aRegs);
2688	LogFlow(("NEM/%u: Entry @ %04x:%08RX64 IF=%d EFL=%#RX64 SS:RSP=%04x:%08RX64 cr0=%RX64\n",
2689	pVCpu->idCpu, aRegs[0].Segment.Selector, aRegs[1].Reg64, RT_BOOL(aRegs[2].Reg64 & X86_EFL_IF),
2690	aRegs[2].Reg64, aRegs[3].Segment.Selector, aRegs[4].Reg64, aRegs[5].Reg64));
2691	}
2692	#endif
2693	WHV_RUN_VP_EXIT_CONTEXT ExitReason = {0};
2694	TMNotifyStartOfExecution(pVM, pVCpu);
2695
2696	HRESULT hrc = WHvRunVirtualProcessor(pVM->nem.s.hPartition, pVCpu->idCpu, &ExitReason, sizeof(ExitReason));
2697
2698	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2699	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2700	#ifdef LOG_ENABLED
2701	LogFlow(("NEM/%u: Exit @ %04X:%08RX64 IF=%d CR8=%#x Reason=%#x\n", pVCpu->idCpu, ExitReason.VpContext.Cs.Selector,
2702	ExitReason.VpContext.Rip, RT_BOOL(ExitReason.VpContext.Rflags & X86_EFL_IF), ExitReason.VpContext.Cr8,
2703	ExitReason.ExitReason));
2704	#endif
2705	if (SUCCEEDED(hrc))
2706	{
2707	/*
2708	* Deal with the message.
2709	*/
2710	rcStrict = nemR3WinHandleExit(pVM, pVCpu, &ExitReason);
2711	if (rcStrict == VINF_SUCCESS)
2712	{ /* hopefully likely */ }
2713	else
2714	{
2715	LogFlow(("NEM/%u: breaking: nemHCWinHandleMessage -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2716	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2717	break;
2718	}
2719	}
2720	else
2721	AssertLogRelMsgFailedReturn(("WHvRunVirtualProcessor failed for CPU #%u: %#x (%u)\n",
2722	pVCpu->idCpu, hrc, GetLastError()),
2723	VERR_NEM_IPE_0);
2724
2725	/*
2726	* If no relevant FFs are pending, loop.
2727	*/
2728	if ( !VM_FF_IS_ANY_SET( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2729	&& !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2730	continue;
2731
2732	/** @todo Try handle pending flags, not just return to EM loops. Take care
2733	* not to set important RCs here unless we've handled a message. */
2734	LogFlow(("NEM/%u: breaking: pending FF (%#x / %#RX64)\n",
2735	pVCpu->idCpu, pVM->fGlobalForcedActions, (uint64_t)pVCpu->fLocalForcedActions));
2736	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
2737	}
2738	else
2739	{
2740	LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
2741	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
2742	}
2743	}
2744	else
2745	{
2746	LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
2747	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
2748	}
2749	break;
2750	} /* the run loop */
2751
2752
2753	/*
2754	* If the CPU is running, make sure to stop it before we try sync back the
2755	* state and return to EM. We don't sync back the whole state if we can help it.
2756	*/
2757	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2758	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2759
2760	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL \| (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)))
2761	{
2762	/* Try anticipate what we might need. */
2763	uint64_t fImport = IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI;
2764	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2765	\|\| RT_FAILURE(rcStrict))
2766	fImport = CPUMCTX_EXTRN_ALL \| (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT);
2767	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_INTERRUPT_APIC
2768	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2769	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2770
2771	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2772	{
2773	int rc2 = nemHCWinCopyStateFromHyperV(pVM, pVCpu, fImport \| CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT);
2774	if (RT_SUCCESS(rc2))
2775	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2776	else if (RT_SUCCESS(rcStrict))
2777	rcStrict = rc2;
2778	if (!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL \| (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT))))
2779	pVCpu->cpum.GstCtx.fExtrn = 0;
2780	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2781	}
2782	else
2783	{
2784	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2785	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
2786	}
2787	}
2788	else
2789	{
2790	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2791	pVCpu->cpum.GstCtx.fExtrn = 0;
2792	}
2793
2794	LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel,
2795	pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, VBOXSTRICTRC_VAL(rcStrict) ));
2796	return rcStrict;
2797	}
2798
2799
2800	/**
2801	* @callback_method_impl{FNPGMPHYSNEMCHECKPAGE}
2802	*/
2803	NEM_TMPL_STATIC DECLCALLBACK(int) nemHCWinUnsetForA20CheckerCallback(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
2804	PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
2805	{
2806	/* We'll just unmap the memory. */
2807	if (pInfo->u2NemState > NEM_WIN_PAGE_STATE_UNMAPPED)
2808	{
2809	HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
2810	if (SUCCEEDED(hrc))
2811	{
2812	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
2813	uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2814	Log5(("NEM GPA unmapped/A20: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[pInfo->u2NemState], cMappedPages));
2815	pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
2816	}
2817	else
2818	{
2819	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
2820	LogRel(("nemHCWinUnsetForA20CheckerCallback/unmap: GCPhys=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2821	GCPhys, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2822	return VERR_NEM_IPE_2;
2823	}
2824	}
2825	RT_NOREF(pVCpu, pvUser);
2826	return VINF_SUCCESS;
2827	}
2828
2829
2830	/**
2831	* Unmaps a page from Hyper-V for the purpose of emulating A20 gate behavior.
2832	*
2833	* @returns The PGMPhysNemQueryPageInfo result.
2834	* @param pVM The cross context VM structure.
2835	* @param pVCpu The cross context virtual CPU structure.
2836	* @param GCPhys The page to unmap.
2837	*/
2838	NEM_TMPL_STATIC int nemHCWinUnmapPageForA20Gate(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys)
2839	{
2840	PGMPHYSNEMPAGEINFO Info;
2841	return PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhys, false /fMakeWritable/, &Info,
2842	nemHCWinUnsetForA20CheckerCallback, NULL);
2843	}
2844
2845
2846	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2847	{
2848	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2849	NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2850	}
2851
2852
2853	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2854	RTR3PTR pvMemR3, uint8_t *pu2State)
2855	{
2856	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2857	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2858
2859	*pu2State = UINT8_MAX;
2860	if (pvMemR3)
2861	{
2862	STAM_REL_PROFILE_START(&pVM->nem.s.StatProfMapGpaRange, a);
2863	HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, pvMemR3, GCPhys, cb,
2864	WHvMapGpaRangeFlagRead \| WHvMapGpaRangeFlagExecute \| WHvMapGpaRangeFlagWrite);
2865	STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfMapGpaRange, a);
2866	if (SUCCEEDED(hrc))
2867	*pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2868	else
2869	AssertLogRelMsgFailed(("NEMHCNotifyHandlerPhysicalDeregister: WHvMapGpaRange(,%p,%RGp,%RGp,) -> %Rhrc\n",
2870	pvMemR3, GCPhys, cb, hrc));
2871	}
2872	RT_NOREF(enmKind);
2873	}
2874
2875
2876	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2877	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2878	{
2879	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2880	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2881	NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2882	}
2883
2884
2885	/**
2886	* Worker that maps pages into Hyper-V.
2887	*
2888	* This is used by the PGM physical page notifications as well as the memory
2889	* access VMEXIT handlers.
2890	*
2891	* @returns VBox status code.
2892	* @param pVM The cross context VM structure.
2893	* @param pVCpu The cross context virtual CPU structure of the
2894	* calling EMT.
2895	* @param GCPhysSrc The source page address.
2896	* @param GCPhysDst The hyper-V destination page. This may differ from
2897	* GCPhysSrc when A20 is disabled.
2898	* @param fPageProt NEM_PAGE_PROT_XXX.
2899	* @param pu2State Our page state (input/output).
2900	* @param fBackingChanged Set if the page backing is being changed.
2901	* @thread EMT(pVCpu)
2902	*/
2903	NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
2904	uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged)
2905	{
2906	/*
2907	* Looks like we need to unmap a page before we can change the backing
2908	* or even modify the protection. This is going to be REALLY efficient.
2909	* PGM lends us two bits to keep track of the state here.
2910	*/
2911	RT_NOREF(pVCpu);
2912	uint8_t const u2OldState = *pu2State;
2913	uint8_t const u2NewState = fPageProt & NEM_PAGE_PROT_WRITE ? NEM_WIN_PAGE_STATE_WRITABLE
2914	: fPageProt & NEM_PAGE_PROT_READ ? NEM_WIN_PAGE_STATE_READABLE : NEM_WIN_PAGE_STATE_UNMAPPED;
2915	if ( fBackingChanged
2916	\|\| u2NewState != u2OldState)
2917	{
2918	if (u2OldState > NEM_WIN_PAGE_STATE_UNMAPPED)
2919	{
2920	STAM_REL_PROFILE_START(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
2921	HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst, X86_PAGE_SIZE);
2922	STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
2923	if (SUCCEEDED(hrc))
2924	{
2925	*pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2926	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
2927	uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2928	if (u2NewState == NEM_WIN_PAGE_STATE_UNMAPPED)
2929	{
2930	Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n",
2931	GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2932	return VINF_SUCCESS;
2933	}
2934	}
2935	else
2936	{
2937	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
2938	LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2939	GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2940	return VERR_NEM_INIT_FAILED;
2941	}
2942	}
2943	}
2944
2945	/*
2946	* Writeable mapping?
2947	*/
2948	if (fPageProt & NEM_PAGE_PROT_WRITE)
2949	{
2950	void *pvPage;
2951	int rc = nemR3NativeGCPhys2R3PtrWriteable(pVM, GCPhysSrc, &pvPage);
2952	if (RT_SUCCESS(rc))
2953	{
2954	HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, pvPage, GCPhysDst, X86_PAGE_SIZE,
2955	WHvMapGpaRangeFlagRead \| WHvMapGpaRangeFlagExecute \| WHvMapGpaRangeFlagWrite);
2956	if (SUCCEEDED(hrc))
2957	{
2958	*pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2959	STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPage);
2960	uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2961	Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2962	GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2963	return VINF_SUCCESS;
2964	}
2965	STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPageFailed);
2966	LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2967	GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2968	return VERR_NEM_INIT_FAILED;
2969	}
2970	LogRel(("nemHCNativeSetPhysPage/writable: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
2971	return rc;
2972	}
2973
2974	if (fPageProt & NEM_PAGE_PROT_READ)
2975	{
2976	const void *pvPage;
2977	int rc = nemR3NativeGCPhys2R3PtrReadOnly(pVM, GCPhysSrc, &pvPage);
2978	if (RT_SUCCESS(rc))
2979	{
2980	STAM_REL_PROFILE_START(&pVM->nem.s.StatProfMapGpaRangePage, a);
2981	HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, (void *)pvPage, GCPhysDst, X86_PAGE_SIZE,
2982	WHvMapGpaRangeFlagRead \| WHvMapGpaRangeFlagExecute);
2983	STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfMapGpaRangePage, a);
2984	if (SUCCEEDED(hrc))
2985	{
2986	*pu2State = NEM_WIN_PAGE_STATE_READABLE;
2987	STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPage);
2988	uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2989	Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2990	GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2991	return VINF_SUCCESS;
2992	}
2993	STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPageFailed);
2994	LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2995	GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2996	return VERR_NEM_INIT_FAILED;
2997	}
2998	LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
2999	return rc;
3000	}
3001
3002	/* We already unmapped it above. */
3003	*pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
3004	return VINF_SUCCESS;
3005	}
3006
3007
3008	NEM_TMPL_STATIC int nemHCJustUnmapPageFromHyperV(PVMCC pVM, RTGCPHYS GCPhysDst, uint8_t *pu2State)
3009	{
3010	if (*pu2State <= NEM_WIN_PAGE_STATE_UNMAPPED)
3011	{
3012	Log5(("nemHCJustUnmapPageFromHyperV: %RGp == unmapped\n", GCPhysDst));
3013	*pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
3014	return VINF_SUCCESS;
3015	}
3016
3017	STAM_REL_PROFILE_START(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
3018	HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, X86_PAGE_SIZE);
3019	STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
3020	if (SUCCEEDED(hrc))
3021	{
3022	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
3023	uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
3024	*pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
3025	Log5(("nemHCJustUnmapPageFromHyperV: %RGp => unmapped (total %u)\n", GCPhysDst, cMappedPages));
3026	return VINF_SUCCESS;
3027	}
3028	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
3029	LogRel(("nemHCJustUnmapPageFromHyperV(%RGp): failed! hrc=%Rhrc (%#x) Last=%#x/%u\n",
3030	GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
3031	return VERR_NEM_IPE_6;
3032	}
3033
3034
3035	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
3036	PGMPAGETYPE enmType, uint8_t *pu2State)
3037	{
3038	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3039	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3040	RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
3041
3042	int rc;
3043	RT_NOREF_PV(fPageProt);
3044	#ifdef NEM_WIN_WITH_A20
3045	if ( pVM->nem.s.fA20Enabled
3046	\|\| !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
3047	#endif
3048	rc = nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3049	#ifdef NEM_WIN_WITH_A20
3050	else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
3051	rc = nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3052	else
3053	rc = VINF_SUCCESS; /* ignore since we've got the alias page at this address. */
3054	#endif
3055	return rc;
3056	}
3057
3058
3059	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
3060	PGMPAGETYPE enmType, uint8_t *pu2State)
3061	{
3062	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3063	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3064	Assert(VM_IS_NEM_ENABLED(pVM));
3065	RT_NOREF(HCPhys, enmType, pvR3);
3066
3067	RT_NOREF_PV(fPageProt);
3068	#ifdef NEM_WIN_WITH_A20
3069	if ( pVM->nem.s.fA20Enabled
3070	\|\| !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
3071	#endif
3072	nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3073	#ifdef NEM_WIN_WITH_A20
3074	else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
3075	nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3076	/* else: ignore since we've got the alias page at this address. */
3077	#endif
3078	}
3079
3080
3081	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
3082	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
3083	{
3084	Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp pvNewR3=%p fPageProt=%#x enmType=%d *pu2State=%d\n",
3085	GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, *pu2State));
3086	Assert(VM_IS_NEM_ENABLED(pVM));
3087	RT_NOREF(HCPhysPrev, HCPhysNew, pvNewR3, enmType);
3088
3089	RT_NOREF_PV(fPageProt);
3090	#ifdef NEM_WIN_WITH_A20
3091	if ( pVM->nem.s.fA20Enabled
3092	\|\| !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
3093	#endif
3094	nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3095	#ifdef NEM_WIN_WITH_A20
3096	else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
3097	nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3098	/* else: ignore since we've got the alias page at this address. */
3099	#endif
3100	}
3101
3102
3103	/**
3104	* Returns features supported by the NEM backend.
3105	*
3106	* @returns Flags of features supported by the native NEM backend.
3107	* @param pVM The cross context VM structure.
3108	*/
3109	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
3110	{
3111	RT_NOREF(pVM);
3112	/** @todo Make use of the WHvGetVirtualProcessorXsaveState/WHvSetVirtualProcessorXsaveState
3113	* interface added in 2019 to enable passthrough of xsave/xrstor (and depending) features to the guest. */
3114	/** @todo Is NEM_FEAT_F_FULL_GST_EXEC always true? */
3115	return NEM_FEAT_F_NESTED_PAGING \| NEM_FEAT_F_FULL_GST_EXEC;
3116	}
3117

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source: vbox/trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h

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