IEMThreadedFunctions.cpp@ 99298

Last change on this file since 99298 was 99298, checked in by vboxsync, 2 years ago
VMM/IEM: More work on processing MC blocks and generating threaded functions from them. bugref:10369
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1	/* $Id: IEMThreadedFunctions.cpp 99298 2023-04-05 22:27:15Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, Threaded Functions.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
33	# define LOG_GROUP LOG_GROUP_IEM
34	#endif
35	#define VMCPU_INCL_CPUM_GST_CTX
36	#define IEM_WITH_OPAQUE_DECODER_STATE
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/apic.h>
40	#include <VBox/vmm/pdm.h>
41	#include <VBox/vmm/pgm.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/hm.h>
45	#include <VBox/vmm/nem.h>
46	#include <VBox/vmm/gim.h>
47	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
48	# include <VBox/vmm/em.h>
49	# include <VBox/vmm/hm_svm.h>
50	#endif
51	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
52	# include <VBox/vmm/hmvmxinline.h>
53	#endif
54	#include <VBox/vmm/tm.h>
55	#include <VBox/vmm/dbgf.h>
56	#include <VBox/vmm/dbgftrace.h>
57	#include "IEMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/log.h>
60	#include <VBox/err.h>
61	#include <VBox/param.h>
62	#include <VBox/dis.h>
63	#include <VBox/disopcode-x86-amd64.h>
64	#include <iprt/asm-math.h>
65	#include <iprt/assert.h>
66	#include <iprt/string.h>
67	#include <iprt/x86.h>
68
69	#include "IEMInline.h"
70	#include "IEMMc.h"
71
72	#include "IEMThreadedFunctions.h"
73
74
75	/*********************************************************************************************************************************
76	* Defined Constants And Macros *
77	*********************************************************************************************************************************/
78
79	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param. */
80	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED(a_cbInstr) \
81	return iemRegAddToRipAndFinishingClearingRF(pVCpu, a_cbInstr)
82	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
83
84	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as param. */
85	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED(a_i8, a_cbInstr, a_enmEffOpSize) \
86	return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
87	#undef IEM_MC_REL_JMP_S8_AND_FINISH
88
89	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as param. */
90	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED(a_i16, a_cbInstr) \
91	return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
92	#undef IEM_MC_REL_JMP_S16_AND_FINISH
93
94	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as param. */
95	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED(a_i32, a_cbInstr, a_enmEffOpSize) \
96	return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32), a_enmEffOpSize)
97	#undef IEM_MC_REL_JMP_S32_AND_FINISH
98
99	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
100	# define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16(a_GCPtrEff, a_bRm, a_u16Disp) \
101	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
102
103	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
104	# define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
105	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
106
107	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
108	# define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
109	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
110
111	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
112	# define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64(a_GCPtrEff, a_bRmEx, a_bSib, a_u32Disp, a_cbImm) \
113	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_bSib, a_u32Disp, a_cbImm)
114
115	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
116	# define IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR6432(a_GCPtrEff, a_bRmEx, a_bSib, a_u32Disp, a_cbImm) \
117	(a_GCPtrEff) = (uint32_t)iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_bSib, a_u32Disp, a_cbImm)
118
119	/** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */
120	# define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_pfnCImpl, a0) \
121	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
122
123	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
124	# define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_pfnCImpl, a0, a1) \
125	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
126
127	/** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */
128	# define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_pfnCImpl, a0, a1, a2) \
129	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
130
131	/** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */
132	# define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_pfnCImpl, a0, a1, a2, a3) \
133	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
134
135	/** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */
136	# define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_pfnCImpl, a0, a1, a2, a3, a4) \
137	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
138
139	/** Variant of IEM_MC_FETCH_GREG_U8 with extended (20) register index. */
140	#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
141	(a_u8Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
142
143	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U16 with extended (20) register index. */
144	#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
145	(a_u16Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
146
147	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U32 with extended (20) register index. */
148	#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
149	(a_u32Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
150
151	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U64 with extended (20) register index. */
152	#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
153	(a_u64Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
154
155	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U16 with extended (20) register index. */
156	#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
157	(a_u16Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
158
159	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U32 with extended (20) register index. */
160	#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
161	(a_u32Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
162
163	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U64 with extended (20) register index. */
164	#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
165	(a_u64Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
166
167	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
168	#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
169	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
170
171	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
172	#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
173	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
174
175	/** Variant of IEM_MC_REF_GREG_U8 with extended (20) register index. */
176	#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
177	(a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
178
179	/** Variant of IEM_MC_ADD_GREG_U8 with extended (20) register index. */
180	#define IEM_MC_ADD_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
181	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) += (a_u8Value)
182
183	/** Variant of IEM_MC_SUB_GREG_U8 with extended (20) register index. */
184	#define IEM_MC_SUB_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
185	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) -= (a_u8Value)
186
187	/** Variant of IEM_MC_ADD_GREG_U8_TO_LOCAL with extended (20) register index. */
188	#define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) \
189	do { (a_u8Value) += iemGRegFetchU8Ex(pVCpu, (a_iGRegEx)); } while (0)
190
191	/** Variant of IEM_MC_AND_GREG_U8 with extended (20) register index. */
192	#define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
193	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) &= (a_u8Value)
194
195	/** Variant of IEM_MC_OR_GREG_U8 with extended (20) register index. */
196	#define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
197	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) \|= (a_u8Value)
198
199	/**
200	* Calculates the effective address of a ModR/M memory operand, 16-bit
201	* addressing variant.
202	*
203	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16.
204	*
205	* @returns The effective address.
206	* @param pVCpu The cross context virtual CPU structure of the calling thread.
207	* @param bRm The ModRM byte.
208	* @param u16Disp The displacement byte/word, if any.
209	* RIP relative addressing.
210	*/
211	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
212	{
213	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x\n", bRm));
214	Assert(pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT);
215
216	/* Handle the disp16 form with no registers first. */
217	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
218	{
219	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16Disp));
220	return u16Disp;
221	}
222
223	/* Get the displacment. */
224	/** @todo we can eliminate this step by making u16Disp have this value
225	* already! */
226	uint16_t u16EffAddr;
227	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
228	{
229	case 0: u16EffAddr = 0; break;
230	case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
231	case 2: u16EffAddr = u16Disp; break;
232	default: AssertFailedStmt(u16EffAddr = 0);
233	}
234
235	/* Add the base and index registers to the disp. */
236	switch (bRm & X86_MODRM_RM_MASK)
237	{
238	case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
239	case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
240	case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; break;
241	case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; break;
242	case 4: u16EffAddr += pVCpu->cpum.GstCtx.si; break;
243	case 5: u16EffAddr += pVCpu->cpum.GstCtx.di; break;
244	case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp; break;
245	case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx; break;
246	}
247
248	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16EffAddr));
249	return u16EffAddr;
250	}
251
252
253	/**
254	* Calculates the effective address of a ModR/M memory operand, 32-bit
255	* addressing variant.
256	*
257	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32 and
258	* IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT.
259	*
260	* @returns The effective address.
261	* @param pVCpu The cross context virtual CPU structure of the calling thread.
262	* @param bRm The ModRM byte.
263	* @param bSib The SIB byte, if any.
264	* @param u32Disp The displacement byte/dword, if any.
265	*/
266	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint8_t bSib, uint32_t u32Disp) RT_NOEXCEPT
267	{
268	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x\n", bRm));
269	Assert(pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT);
270
271	/* Handle the disp32 form with no registers first. */
272	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
273	{
274	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32Disp));
275	return u32Disp;
276	}
277
278	/* Get the register (or SIB) value. */
279	uint32_t u32EffAddr;
280	switch (bRm & X86_MODRM_RM_MASK)
281	{
282	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
283	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
284	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
285	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
286	case 4: /* SIB */
287	{
288	/* Get the index and scale it. */
289	switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
290	{
291	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
292	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
293	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
294	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
295	case 4: u32EffAddr = 0; /none / break;
296	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
297	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
298	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
299	}
300	u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
301
302	/* add base */
303	switch (bSib & X86_SIB_BASE_MASK)
304	{
305	case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
306	case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
307	case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
308	case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
309	case 4: u32EffAddr += pVCpu->cpum.GstCtx.esp; break;
310	case 5:
311	if ((bRm & X86_MODRM_MOD_MASK) != 0)
312	u32EffAddr += pVCpu->cpum.GstCtx.ebp;
313	else
314	u32EffAddr += u32Disp;
315	break;
316	case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
317	case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
318	}
319	break;
320	}
321	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
322	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
323	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
324	}
325
326	/* Get and add the displacement. */
327	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
328	{
329	case 0: break;
330	case 1: u32EffAddr += (int8_t)u32Disp; break;
331	case 2: u32EffAddr += u32Disp; break;
332	default: AssertFailed();
333	}
334
335	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32EffAddr));
336	return u32EffAddr;
337	}
338
339
340	/**
341	* Calculates the effective address of a ModR/M memory operand.
342	*
343	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64.
344	*
345	* @returns The effective address.
346	* @param pVCpu The cross context virtual CPU structure of the calling thread.
347	* @param bRmEx The ModRM byte but with bit 3 set to REX.B and
348	* bit 4 to REX.X. The two bits are part of the
349	* REG sub-field, which isn't needed in this
350	* function.
351	* @param bSib The SIB byte, if any.
352	* @param u32Disp The displacement byte/word/dword, if any.
353	* @param cbInstr The size of the fully decoded instruction. Used
354	* for RIP relative addressing.
355	* @todo combine cbInstr and cbImm!
356	*/
357	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr64(PVMCPUCC pVCpu, uint8_t bRmEx, uint8_t bSib,
358	uint32_t u32Disp, uint8_t cbInstr) RT_NOEXCEPT
359	{
360	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: bRmEx=%#x\n", bRmEx));
361	Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
362
363	uint64_t u64EffAddr;
364
365	/* Handle the rip+disp32 form with no registers first. */
366	if ((bRmEx & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
367	{
368	u64EffAddr = (int32_t)u32Disp;
369	u64EffAddr += pVCpu->cpum.GstCtx.rip + cbInstr;
370	}
371	else
372	{
373	/* Get the register (or SIB) value. */
374	switch (bRmEx & (X86_MODRM_RM_MASK \| 0x8)) /* bRmEx[bit 3] = REX.B */
375	{
376	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
377	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
378	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
379	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
380	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
381	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
382	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
383	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
384	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
385	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
386	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
387	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
388	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
389	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
390	/* SIB */
391	case 4:
392	case 12:
393	{
394	/* Get the index and scale it. */
395	switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) \| ((bRmEx & 0x10) >> 1)) /* bRmEx[bit 4] = REX.X */
396	{
397	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
398	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
399	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
400	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
401	case 4: u64EffAddr = 0; /none / break;
402	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
403	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
404	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
405	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
406	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
407	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
408	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
409	case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
410	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
411	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
412	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
413	}
414	u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
415
416	/* add base */
417	switch ((bSib & X86_SIB_BASE_MASK) \| (bRmEx & 0x8)) /* bRmEx[bit 3] = REX.B */
418	{
419	case 0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
420	case 1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
421	case 2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
422	case 3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
423	case 4: u64EffAddr += pVCpu->cpum.GstCtx.rsp; break;
424	case 6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
425	case 7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
426	case 8: u64EffAddr += pVCpu->cpum.GstCtx.r8; break;
427	case 9: u64EffAddr += pVCpu->cpum.GstCtx.r9; break;
428	case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
429	case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
430	case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
431	case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
432	case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
433	/* complicated encodings */
434	case 5:
435	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
436	u64EffAddr += pVCpu->cpum.GstCtx.rbp;
437	else
438	u64EffAddr += (int32_t)u32Disp;
439	break;
440	case 13:
441	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
442	u64EffAddr += pVCpu->cpum.GstCtx.r13;
443	else
444	u64EffAddr += (int32_t)u32Disp;
445	break;
446	}
447	break;
448	}
449	}
450
451	/* Get and add the displacement. */
452	switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
453	{
454	case 0: break;
455	case 1: u64EffAddr += (int8_t)u32Disp; break;
456	case 2: u64EffAddr += (int32_t)u32Disp; break;
457	default: AssertFailed();
458	}
459	}
460
461	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: EffAddr=%#010RGv\n", u64EffAddr));
462	return u64EffAddr;
463	}
464
465
466
467	/*
468	* The threaded functions.
469	*/
470	#include "IEMThreadedFunctions.cpp.h"
471

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMThreadedFunctions.cpp@ 99298

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