IEMAllThreadedFunctions.cpp@ 100111

Last change on this file since 100111 was 100096, checked in by vboxsync, 18 months ago
VMM/IEM: Adjusted/reworked the relative jump MCs in the threaded function file. bugref:10369
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1	/* $Id: IEMAllThreadedFunctions.cpp 100096 2023-06-07 15:14:56Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, Threaded Functions.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
33	# define LOG_GROUP LOG_GROUP_IEM
34	#endif
35	#define VMCPU_INCL_CPUM_GST_CTX
36	#define IEM_WITH_OPAQUE_DECODER_STATE
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/apic.h>
40	#include <VBox/vmm/pdm.h>
41	#include <VBox/vmm/pgm.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/hm.h>
45	#include <VBox/vmm/nem.h>
46	#include <VBox/vmm/gim.h>
47	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
48	# include <VBox/vmm/em.h>
49	# include <VBox/vmm/hm_svm.h>
50	#endif
51	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
52	# include <VBox/vmm/hmvmxinline.h>
53	#endif
54	#include <VBox/vmm/tm.h>
55	#include <VBox/vmm/dbgf.h>
56	#include <VBox/vmm/dbgftrace.h>
57	#include "IEMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/log.h>
60	#include <VBox/err.h>
61	#include <VBox/param.h>
62	#include <VBox/dis.h>
63	#include <VBox/disopcode-x86-amd64.h>
64	#include <iprt/asm-math.h>
65	#include <iprt/assert.h>
66	#include <iprt/string.h>
67	#include <iprt/x86.h>
68
69	#include "IEMInline.h"
70	#include "IEMMc.h"
71
72	#include "IEMThreadedFunctions.h"
73
74
75	/*********************************************************************************************************************************
76	* Defined Constants And Macros *
77	*********************************************************************************************************************************/
78
79	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
80	* and only used when we're in 16-bit code on a pre-386 CPU. */
81	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr) \
82	return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr)
83
84	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
85	* and used for 16-bit and 32-bit code on 386 and later CPUs. */
86	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr) \
87	return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr)
88
89	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
90	* and only used when we're in 64-bit code. */
91	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr) \
92	return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr)
93
94	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
95
96
97	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
98	* parameter, for use in 16-bit code on a pre-386 CPU. */
99	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16(a_i8, a_cbInstr) \
100	return iemRegIp16RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8))
101
102	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
103	* size as extra parameters, for use in 16-bit and 32-bit code on 386 and
104	* later CPUs. */
105	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32(a_i8, a_cbInstr, a_enmEffOpSize) \
106	return iemRegEip32RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
107
108	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
109	* size as extra parameters, for use in 64-bit code. */
110	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64(a_i8, a_cbInstr, a_enmEffOpSize) \
111	return iemRegRip64RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
112
113	#undef IEM_MC_REL_JMP_S8_AND_FINISH
114
115
116	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
117	* param, for use in 16-bit code on a pre-386 CPU. */
118	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16(a_i16, a_cbInstr) \
119	return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
120
121	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
122	* param, for use in 16-bit and 32-bit code on 386 and later CPUs. */
123	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32(a_i16, a_cbInstr) \
124	return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
125
126	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
127	* param, for use in 64-bit code. */
128	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64(a_i16, a_cbInstr) \
129	return iemRegRip64RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
130
131	#undef IEM_MC_REL_JMP_S16_AND_FINISH
132
133
134	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
135	* an extra parameter - dummy for pre-386 variations not eliminated by the
136	* python script. */
137	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16(a_i32, a_cbInstr) \
138	do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
139
140	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
141	* an extra parameter, for use in 16-bit and 32-bit code on 386+. */
142	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32(a_i32, a_cbInstr) \
143	return iemRegEip32RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
144
145	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
146	* an extra parameter, for use in 64-bit code. */
147	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64(a_i32, a_cbInstr) \
148	return iemRegRip64RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
149
150	#undef IEM_MC_REL_JMP_S32_AND_FINISH
151
152
153	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit. */
154	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp) \
155	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
156
157	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, pre-386 16-bit. */
158	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_PRE386(a_GCPtrEff, a_bRm, a_u16Disp) \
159	IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp)
160
161	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit with address prefix. */
162	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_ADDR16(a_GCPtrEff, a_bRm, a_u16Disp) \
163	IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp)
164
165
166	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit. */
167	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
168	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
169
170	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit flat. */
171	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_FLAT(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
172	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
173
174	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit with address prefix. */
175	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_ADDR32(a_GCPtrEff, a_bRm, a_bSib, a_u32Disp) \
176	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_bSib, a_u32Disp)
177
178
179	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
180	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64(a_GCPtrEff, a_bRmEx, a_bSib, a_u32Disp, a_cbImm) \
181	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_bSib, a_u32Disp, a_cbImm)
182
183	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters.
184	* @todo How did that address prefix thing work for 64-bit code again? */
185	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32(a_GCPtrEff, a_bRmEx, a_bSib, a_u32Disp, a_cbImm) \
186	(a_GCPtrEff) = (uint32_t)iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_bSib, a_u32Disp, a_cbImm)
187
188	#undef IEM_MC_CALC_RM_EFF_ADDR
189
190
191	/** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */
192	#define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0) \
193	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
194	#undef IEM_MC_CALL_CIMPL_1
195
196	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
197	#define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1) \
198	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
199	#undef IEM_MC_CALL_CIMPL_2
200
201	/** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */
202	#define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2) \
203	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
204	#undef IEM_MC_CALL_CIMPL_3
205
206	/** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */
207	#define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \
208	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
209	#undef IEM_MC_CALL_CIMPL_4
210
211	/** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */
212	#define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \
213	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
214	#undef IEM_MC_CALL_CIMPL_5
215
216	/** Variant of IEM_MC_FETCH_GREG_U8 with extended (20) register index. */
217	#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
218	(a_u8Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
219
220	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U16 with extended (20) register index. */
221	#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
222	(a_u16Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
223
224	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U32 with extended (20) register index. */
225	#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
226	(a_u32Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
227
228	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U64 with extended (20) register index. */
229	#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
230	(a_u64Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
231
232	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U16 with extended (20) register index. */
233	#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
234	(a_u16Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
235
236	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U32 with extended (20) register index. */
237	#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
238	(a_u32Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
239	#undef IEM_MC_FETCH_GREG_U8_SX_U32
240
241	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U64 with extended (20) register index. */
242	#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
243	(a_u64Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
244	#undef IEM_MC_FETCH_GREG_U8_SX_U64
245
246	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
247	#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
248	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
249	#undef IEM_MC_STORE_GREG_U8
250
251	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
252	#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
253	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
254	#undef IEM_MC_STORE_GREG_U8
255
256	/** Variant of IEM_MC_REF_GREG_U8 with extended (20) register index. */
257	#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
258	(a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
259	#undef IEM_MC_REF_GREG_U8
260
261	/** Variant of IEM_MC_ADD_GREG_U8 with extended (20) register index. */
262	#define IEM_MC_ADD_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
263	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) += (a_u8Value)
264	#undef IEM_MC_ADD_GREG_U8
265
266	/** Variant of IEM_MC_SUB_GREG_U8 with extended (20) register index. */
267	#define IEM_MC_SUB_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
268	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) -= (a_u8Value)
269	#undef IEM_MC_SUB_GREG_U8
270
271	/** Variant of IEM_MC_ADD_GREG_U8_TO_LOCAL with extended (20) register index. */
272	#define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) \
273	do { (a_u8Value) += iemGRegFetchU8Ex(pVCpu, (a_iGRegEx)); } while (0)
274	#undef IEM_MC_ADD_GREG_U8_TO_LOCAL
275
276	/** Variant of IEM_MC_AND_GREG_U8 with extended (20) register index. */
277	#define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
278	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) &= (a_u8Value)
279	#undef IEM_MC_AND_GREG_U8
280
281	/** Variant of IEM_MC_OR_GREG_U8 with extended (20) register index. */
282	#define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
283	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) \|= (a_u8Value)
284	#undef IEM_MC_OR_GREG_U8
285
286	/**
287	* Calculates the effective address of a ModR/M memory operand, 16-bit
288	* addressing variant.
289	*
290	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16.
291	*
292	* @returns The effective address.
293	* @param pVCpu The cross context virtual CPU structure of the calling thread.
294	* @param bRm The ModRM byte.
295	* @param u16Disp The displacement byte/word, if any.
296	* RIP relative addressing.
297	*/
298	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
299	{
300	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x\n", bRm));
301	Assert(!IEM_IS_64BIT_CODE(pVCpu));
302
303	/* Handle the disp16 form with no registers first. */
304	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
305	{
306	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16Disp));
307	return u16Disp;
308	}
309
310	/* Get the displacment. */
311	/** @todo we can eliminate this step by making u16Disp have this value
312	* already! */
313	uint16_t u16EffAddr;
314	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
315	{
316	case 0: u16EffAddr = 0; break;
317	case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
318	case 2: u16EffAddr = u16Disp; break;
319	default: AssertFailedStmt(u16EffAddr = 0);
320	}
321
322	/* Add the base and index registers to the disp. */
323	switch (bRm & X86_MODRM_RM_MASK)
324	{
325	case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
326	case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
327	case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; break;
328	case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; break;
329	case 4: u16EffAddr += pVCpu->cpum.GstCtx.si; break;
330	case 5: u16EffAddr += pVCpu->cpum.GstCtx.di; break;
331	case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp; break;
332	case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx; break;
333	}
334
335	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16EffAddr));
336	return u16EffAddr;
337	}
338
339
340	/**
341	* Calculates the effective address of a ModR/M memory operand, 32-bit
342	* addressing variant.
343	*
344	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32 and
345	* IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT.
346	*
347	* @returns The effective address.
348	* @param pVCpu The cross context virtual CPU structure of the calling thread.
349	* @param bRm The ModRM byte.
350	* @param bSib The SIB byte, if any.
351	* @param u32Disp The displacement byte/dword, if any.
352	*/
353	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint8_t bSib, uint32_t u32Disp) RT_NOEXCEPT
354	{
355	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x\n", bRm));
356
357	/* Handle the disp32 form with no registers first. */
358	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
359	{
360	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32Disp));
361	return u32Disp;
362	}
363
364	/* Get the register (or SIB) value. */
365	uint32_t u32EffAddr;
366	#ifdef _MSC_VER
367	u32EffAddr = 0;/* MSC uninitialized variable analysis is too simple, it seems. */
368	#endif
369	switch (bRm & X86_MODRM_RM_MASK)
370	{
371	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
372	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
373	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
374	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
375	case 4: /* SIB */
376	{
377	/* Get the index and scale it. */
378	switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
379	{
380	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
381	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
382	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
383	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
384	case 4: u32EffAddr = 0; /none / break;
385	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
386	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
387	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
388	}
389	u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
390
391	/* add base */
392	switch (bSib & X86_SIB_BASE_MASK)
393	{
394	case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
395	case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
396	case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
397	case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
398	case 4: u32EffAddr += pVCpu->cpum.GstCtx.esp; break;
399	case 5:
400	if ((bRm & X86_MODRM_MOD_MASK) != 0)
401	u32EffAddr += pVCpu->cpum.GstCtx.ebp;
402	else
403	u32EffAddr += u32Disp;
404	break;
405	case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
406	case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
407	}
408	break;
409	}
410	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
411	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
412	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
413	}
414
415	/* Get and add the displacement. */
416	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
417	{
418	case 0: break;
419	case 1: u32EffAddr += (int8_t)u32Disp; break;
420	case 2: u32EffAddr += u32Disp; break;
421	default: AssertFailed();
422	}
423
424	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32EffAddr));
425	return u32EffAddr;
426	}
427
428
429	/**
430	* Calculates the effective address of a ModR/M memory operand.
431	*
432	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64.
433	*
434	* @returns The effective address.
435	* @param pVCpu The cross context virtual CPU structure of the calling thread.
436	* @param bRmEx The ModRM byte but with bit 3 set to REX.B and
437	* bit 4 to REX.X. The two bits are part of the
438	* REG sub-field, which isn't needed in this
439	* function.
440	* @param bSib The SIB byte, if any.
441	* @param u32Disp The displacement byte/word/dword, if any.
442	* @param cbInstr The size of the fully decoded instruction. Used
443	* for RIP relative addressing.
444	* @todo combine cbInstr and cbImm!
445	*/
446	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr64(PVMCPUCC pVCpu, uint8_t bRmEx, uint8_t bSib,
447	uint32_t u32Disp, uint8_t cbInstr) RT_NOEXCEPT
448	{
449	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: bRmEx=%#x\n", bRmEx));
450	Assert(IEM_IS_64BIT_CODE(pVCpu));
451
452	uint64_t u64EffAddr;
453
454	/* Handle the rip+disp32 form with no registers first. */
455	if ((bRmEx & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
456	{
457	u64EffAddr = (int32_t)u32Disp;
458	u64EffAddr += pVCpu->cpum.GstCtx.rip + cbInstr;
459	}
460	else
461	{
462	/* Get the register (or SIB) value. */
463	#ifdef _MSC_VER
464	u64EffAddr = 0; /* MSC uninitialized variable analysis is too simple, it seems. */
465	#endif
466	switch (bRmEx & (X86_MODRM_RM_MASK \| 0x8)) /* bRmEx[bit 3] = REX.B */
467	{
468	default:
469	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
470	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
471	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
472	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
473	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
474	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
475	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
476	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
477	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
478	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
479	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
480	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
481	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
482	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
483	/* SIB */
484	case 4:
485	case 12:
486	{
487	/* Get the index and scale it. */
488	switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) \| ((bRmEx & 0x10) >> 1)) /* bRmEx[bit 4] = REX.X */
489	{
490	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
491	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
492	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
493	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
494	case 4: u64EffAddr = 0; /none / break;
495	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
496	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
497	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
498	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
499	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
500	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
501	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
502	case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
503	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
504	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
505	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
506	}
507	u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
508
509	/* add base */
510	switch ((bSib & X86_SIB_BASE_MASK) \| (bRmEx & 0x8)) /* bRmEx[bit 3] = REX.B */
511	{
512	case 0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
513	case 1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
514	case 2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
515	case 3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
516	case 4: u64EffAddr += pVCpu->cpum.GstCtx.rsp; break;
517	case 6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
518	case 7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
519	case 8: u64EffAddr += pVCpu->cpum.GstCtx.r8; break;
520	case 9: u64EffAddr += pVCpu->cpum.GstCtx.r9; break;
521	case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
522	case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
523	case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
524	case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
525	case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
526	/* complicated encodings */
527	case 5:
528	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
529	u64EffAddr += pVCpu->cpum.GstCtx.rbp;
530	else
531	u64EffAddr += (int32_t)u32Disp;
532	break;
533	case 13:
534	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
535	u64EffAddr += pVCpu->cpum.GstCtx.r13;
536	else
537	u64EffAddr += (int32_t)u32Disp;
538	break;
539	}
540	break;
541	}
542	}
543
544	/* Get and add the displacement. */
545	switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
546	{
547	case 0: break;
548	case 1: u64EffAddr += (int8_t)u32Disp; break;
549	case 2: u64EffAddr += (int32_t)u32Disp; break;
550	default: AssertFailed();
551	}
552	}
553
554	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: EffAddr=%#010RGv\n", u64EffAddr));
555	return u64EffAddr;
556	}
557
558
559
560	/*
561	* The threaded functions.
562	*/
563	#include "IEMThreadedFunctions.cpp.h"
564

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllThreadedFunctions.cpp@ 100111

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