VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp@ 105856

Last change on this file since 105856 was 105856, checked in by vboxsync, 3 months ago

VMM/IEM: Don't flush PC prior to indirect jumps, flush it when in the #GP(0) code path. bugref:10720 bugref:10373
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1/* $Id: IEMAllN8veRecompiler.cpp 105856 2024-08-24 01:54:27Z vboxsync $ */
2/** @file
3 * IEM - Native Recompiler
4 *
5 * Logging group IEM_RE_NATIVE assignments:
6 * - Level 1 (Log) : ...
7 * - Flow (LogFlow) : ...
8 * - Level 2 (Log2) : Details calls as they're recompiled.
9 * - Level 3 (Log3) : Disassemble native code after recompiling.
10 * - Level 4 (Log4) : Delayed PC updating.
11 * - Level 5 (Log5) : ...
12 * - Level 6 (Log6) : ...
13 * - Level 7 (Log7) : ...
14 * - Level 8 (Log8) : ...
15 * - Level 9 (Log9) : ...
16 * - Level 10 (Log10): ...
17 * - Level 11 (Log11): Variable allocator.
18 * - Level 12 (Log12): Register allocator.
19 */
20
21/*
22 * Copyright (C) 2023 Oracle and/or its affiliates.
23 *
24 * This file is part of VirtualBox base platform packages, as
25 * available from https://www.virtualbox.org.
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License
29 * as published by the Free Software Foundation, in version 3 of the
30 * License.
31 *
32 * This program is distributed in the hope that it will be useful, but
33 * WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35 * General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, see <https://www.gnu.org/licenses>.
39 *
40 * SPDX-License-Identifier: GPL-3.0-only
41 */
42
43
44/*********************************************************************************************************************************
45* Header Files *
46*********************************************************************************************************************************/
47#define LOG_GROUP LOG_GROUP_IEM_RE_NATIVE
48#define IEM_WITH_OPAQUE_DECODER_STATE
49#define VMCPU_INCL_CPUM_GST_CTX
50#define VMM_INCLUDED_SRC_include_IEMMc_h /* block IEMMc.h inclusion. */
51#include <VBox/vmm/iem.h>
52#include <VBox/vmm/cpum.h>
53#include <VBox/vmm/dbgf.h>
54#include <VBox/vmm/tm.h>
55#include "IEMInternal.h"
56#include <VBox/vmm/vmcc.h>
57#include <VBox/log.h>
58#include <VBox/err.h>
59#include <VBox/dis.h>
60#include <VBox/param.h>
61#include <iprt/assert.h>
62#include <iprt/mem.h>
63#include <iprt/string.h>
64#if defined(RT_ARCH_AMD64)
65# include <iprt/x86.h>
66#elif defined(RT_ARCH_ARM64)
67# include <iprt/armv8.h>
68#endif
69
70#ifdef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
71# include "/opt/local/include/capstone/capstone.h"
72#endif
73
74#include "IEMInline.h"
75#include "IEMThreadedFunctions.h"
76#include "IEMN8veRecompiler.h"
77#include "IEMN8veRecompilerEmit.h"
78#include "IEMN8veRecompilerTlbLookup.h"
79#include "IEMNativeFunctions.h"
80
81
82/*
83 * Narrow down configs here to avoid wasting time on unused configs here.
84 * Note! Same checks in IEMAllThrdRecompiler.cpp.
85 */
86
87#ifndef IEM_WITH_CODE_TLB
88# error The code TLB must be enabled for the recompiler.
89#endif
90
91#ifndef IEM_WITH_DATA_TLB
92# error The data TLB must be enabled for the recompiler.
93#endif
94
95#ifndef IEM_WITH_SETJMP
96# error The setjmp approach must be enabled for the recompiler.
97#endif
98
99/** @todo eliminate this clang build hack. */
100#if RT_CLANG_PREREQ(4, 0)
101# pragma GCC diagnostic ignored "-Wunused-function"
102#endif
103
104
105/*********************************************************************************************************************************
106* Internal Functions *
107*********************************************************************************************************************************/
108#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
109static void iemNativeDbgInfoAddLabel(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType, uint16_t uData);
110#endif
111DECL_FORCE_INLINE(void) iemNativeRegClearGstRegShadowing(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, uint32_t off);
112DECL_FORCE_INLINE(void) iemNativeRegClearGstRegShadowingOne(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg,
113 IEMNATIVEGSTREG enmGstReg, uint32_t off);
114DECL_INLINE_THROW(void) iemNativeVarRegisterRelease(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
115static const char *iemNativeGetLabelName(IEMNATIVELABELTYPE enmLabel, bool fCommonCode = false);
116
117
118
119/*********************************************************************************************************************************
120* Native Recompilation *
121*********************************************************************************************************************************/
122
123
124/**
125 * Used by TB code when encountering a non-zero status or rcPassUp after a call.
126 */
127IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecStatusCodeFiddling,(PVMCPUCC pVCpu, int rc, uint8_t idxInstr))
128{
129 pVCpu->iem.s.cInstructions += idxInstr;
130 return VBOXSTRICTRC_VAL(iemExecStatusCodeFiddling(pVCpu, rc == VINF_IEM_REEXEC_BREAK ? VINF_SUCCESS : rc));
131}
132
133
134/**
135 * Helping iemNativeHlpReturnBreakViaLookup and iemNativeHlpReturnBreakViaLookupWithTlb.
136 */
137DECL_FORCE_INLINE(bool) iemNativeHlpReturnBreakViaLookupIsIrqOrForceFlagPending(PVMCPU pVCpu)
138{
139 uint64_t fCpu = pVCpu->fLocalForcedActions;
140 fCpu &= VMCPU_FF_ALL_MASK & ~( VMCPU_FF_PGM_SYNC_CR3
141 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
142 | VMCPU_FF_TLB_FLUSH
143 | VMCPU_FF_UNHALT );
144 /** @todo this isn't even close to the NMI/IRQ conditions in EM. */
145 if (RT_LIKELY( ( !fCpu
146 || ( !(fCpu & ~(VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
147 && ( !pVCpu->cpum.GstCtx.rflags.Bits.u1IF
148 || CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx) )) )
149 && !VM_FF_IS_ANY_SET(pVCpu->CTX_SUFF(pVM), VM_FF_ALL_MASK) ))
150 return false;
151 return true;
152}
153
154
155/**
156 * Used by TB code when encountering a non-zero status or rcPassUp after a call.
157 */
158template <bool const a_fWithIrqCheck>
159IEM_DECL_NATIVE_HLP_DEF(uintptr_t, iemNativeHlpReturnBreakViaLookup,(PVMCPUCC pVCpu, uint8_t idxTbLookup,
160 uint32_t fFlags, RTGCPHYS GCPhysPc))
161{
162 PIEMTB const pTb = pVCpu->iem.s.pCurTbR3;
163 Assert(idxTbLookup < pTb->cTbLookupEntries);
164 PIEMTB * const ppNewTb = IEMTB_GET_TB_LOOKUP_TAB_ENTRY(pTb, idxTbLookup);
165#if 1
166 PIEMTB const pNewTb = *ppNewTb;
167 if (pNewTb)
168 {
169# ifdef VBOX_STRICT
170 uint64_t const uFlatPcAssert = pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base;
171 AssertMsg( (uFlatPcAssert & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK) == pVCpu->iem.s.uInstrBufPc
172 && (GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK) == pVCpu->iem.s.GCPhysInstrBuf
173 && (GCPhysPc & GUEST_PAGE_OFFSET_MASK) == (uFlatPcAssert & GUEST_PAGE_OFFSET_MASK),
174 ("GCPhysPc=%RGp uFlatPcAssert=%#RX64 uInstrBufPc=%#RX64 GCPhysInstrBuf=%RGp\n",
175 GCPhysPc, uFlatPcAssert, pVCpu->iem.s.uInstrBufPc, pVCpu->iem.s.GCPhysInstrBuf));
176# endif
177 if (pNewTb->GCPhysPc == GCPhysPc)
178 {
179# ifdef VBOX_STRICT
180 uint32_t fAssertFlags = (pVCpu->iem.s.fExec & IEMTB_F_IEM_F_MASK & IEMTB_F_KEY_MASK) | IEMTB_F_TYPE_NATIVE;
181 if (pVCpu->cpum.GstCtx.rflags.uBoth & CPUMCTX_INHIBIT_SHADOW)
182 fAssertFlags |= IEMTB_F_INHIBIT_SHADOW;
183 if (pVCpu->cpum.GstCtx.rflags.uBoth & CPUMCTX_INHIBIT_NMI)
184 fAssertFlags |= IEMTB_F_INHIBIT_NMI;
185# if 1 /** @todo breaks on IP/EIP/RIP wraparound tests in bs3-cpu-weird-1. */
186 Assert(IEM_F_MODE_X86_IS_FLAT(fFlags));
187# else
188 if (!IEM_F_MODE_X86_IS_FLAT(fFlags))
189 {
190 int64_t const offFromLim = (int64_t)pVCpu->cpum.GstCtx.cs.u32Limit - (int64_t)pVCpu->cpum.GstCtx.eip;
191 if (offFromLim < X86_PAGE_SIZE + 16 - (int32_t)(pVCpu->cpum.GstCtx.cs.u64Base & GUEST_PAGE_OFFSET_MASK))
192 fAssertFlags |= IEMTB_F_CS_LIM_CHECKS;
193 }
194# endif
195 Assert(!(fFlags & ~(IEMTB_F_KEY_MASK | IEMTB_F_TYPE_MASK)));
196 AssertMsg(fFlags == fAssertFlags, ("fFlags=%#RX32 fAssertFlags=%#RX32 cs:rip=%04x:%#010RX64\n",
197 fFlags, fAssertFlags, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
198#endif
199
200 /*
201 * Check them + type.
202 */
203 if ((pNewTb->fFlags & (IEMTB_F_KEY_MASK | IEMTB_F_TYPE_MASK)) == fFlags)
204 {
205 /*
206 * Check for interrupts and stuff.
207 */
208 /** @todo We duplicate code here that's also in iemNativeHlpReturnBreakViaLookupWithTlb.
209 * The main problem are the statistics and to some degree the logging. :/ */
210 if (!a_fWithIrqCheck || !iemNativeHlpReturnBreakViaLookupIsIrqOrForceFlagPending(pVCpu) )
211 {
212 /* Do polling. */
213 if ( RT_LIKELY((int32_t)--pVCpu->iem.s.cTbsTillNextTimerPoll > 0)
214 || iemPollTimers(pVCpu->CTX_SUFF(pVM), pVCpu) == VINF_SUCCESS)
215 {
216 /*
217 * Success. Update statistics and switch to the next TB.
218 */
219 if (a_fWithIrqCheck)
220 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking1Irq);
221 else
222 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking1NoIrq);
223
224 pNewTb->cUsed += 1;
225 pNewTb->msLastUsed = pVCpu->iem.s.msRecompilerPollNow;
226 pVCpu->iem.s.pCurTbR3 = pNewTb;
227 pVCpu->iem.s.ppTbLookupEntryR3 = IEMTB_GET_TB_LOOKUP_TAB_ENTRY(pNewTb, 0);
228 pVCpu->iem.s.cTbExecNative += 1;
229 Log10(("iemNativeHlpReturnBreakViaLookupWithPc: match at %04x:%08RX64 (%RGp): pTb=%p[%#x]-> %p\n",
230 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysPc, pTb, idxTbLookup, pNewTb));
231 return (uintptr_t)pNewTb->Native.paInstructions;
232 }
233 }
234 Log10(("iemNativeHlpReturnBreakViaLookupWithPc: IRQ or FF pending\n"));
235 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking1PendingIrq);
236 }
237 else
238 {
239 Log10(("iemNativeHlpReturnBreakViaLookupWithPc: fFlags mismatch at %04x:%08RX64: %#x vs %#x (pTb=%p[%#x]-> %p)\n",
240 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fFlags, pNewTb->fFlags, pTb, idxTbLookup, pNewTb));
241 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking1MismatchFlags);
242 }
243 }
244 else
245 {
246 Log10(("iemNativeHlpReturnBreakViaLookupWithPc: GCPhysPc mismatch at %04x:%08RX64: %RGp vs %RGp (pTb=%p[%#x]-> %p)\n",
247 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysPc, pNewTb->GCPhysPc, pTb, idxTbLookup, pNewTb));
248 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking1MismatchGCPhysPc);
249 }
250 }
251 else
252 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking1NoTb);
253#else
254 NOREF(GCPhysPc);
255#endif
256
257 pVCpu->iem.s.ppTbLookupEntryR3 = ppNewTb;
258 return 0;
259}
260
261
262/**
263 * Used by TB code when encountering a non-zero status or rcPassUp after a call.
264 */
265template <bool const a_fWithIrqCheck>
266IEM_DECL_NATIVE_HLP_DEF(uintptr_t, iemNativeHlpReturnBreakViaLookupWithTlb,(PVMCPUCC pVCpu, uint8_t idxTbLookup))
267{
268 PIEMTB const pTb = pVCpu->iem.s.pCurTbR3;
269 Assert(idxTbLookup < pTb->cTbLookupEntries);
270 PIEMTB * const ppNewTb = IEMTB_GET_TB_LOOKUP_TAB_ENTRY(pTb, idxTbLookup);
271#if 1
272 PIEMTB const pNewTb = *ppNewTb;
273 if (pNewTb)
274 {
275 /*
276 * Calculate the flags for the next TB and check if they match.
277 */
278 uint32_t fFlags = (pVCpu->iem.s.fExec & IEMTB_F_IEM_F_MASK & IEMTB_F_KEY_MASK) | IEMTB_F_TYPE_NATIVE;
279 if (!(pVCpu->cpum.GstCtx.rflags.uBoth & (CPUMCTX_INHIBIT_SHADOW | CPUMCTX_INHIBIT_NMI)))
280 { /* likely */ }
281 else
282 {
283 if (pVCpu->cpum.GstCtx.rflags.uBoth & CPUMCTX_INHIBIT_SHADOW)
284 fFlags |= IEMTB_F_INHIBIT_SHADOW;
285 if (pVCpu->cpum.GstCtx.rflags.uBoth & CPUMCTX_INHIBIT_NMI)
286 fFlags |= IEMTB_F_INHIBIT_NMI;
287 }
288 if (!IEM_F_MODE_X86_IS_FLAT(fFlags))
289 {
290 int64_t const offFromLim = (int64_t)pVCpu->cpum.GstCtx.cs.u32Limit - (int64_t)pVCpu->cpum.GstCtx.eip;
291 if (offFromLim >= X86_PAGE_SIZE + 16 - (int32_t)(pVCpu->cpum.GstCtx.cs.u64Base & GUEST_PAGE_OFFSET_MASK))
292 { /* likely */ }
293 else
294 fFlags |= IEMTB_F_CS_LIM_CHECKS;
295 }
296 Assert(!(fFlags & ~(IEMTB_F_KEY_MASK | IEMTB_F_TYPE_MASK)));
297
298 if ((pNewTb->fFlags & (IEMTB_F_KEY_MASK | IEMTB_F_TYPE_MASK)) == fFlags)
299 {
300 /*
301 * Do the TLB lookup for flat RIP and compare the result with the next TB.
302 *
303 * Note! This replicates iemGetPcWithPhysAndCode and iemGetPcWithPhysAndCodeMissed.
304 */
305 /* Calc the effective PC. */
306 uint64_t uPc = pVCpu->cpum.GstCtx.rip;
307 Assert(pVCpu->cpum.GstCtx.cs.u64Base == 0 || !IEM_IS_64BIT_CODE(pVCpu));
308 uPc += pVCpu->cpum.GstCtx.cs.u64Base;
309
310 /* Advance within the current buffer (PAGE) when possible. */
311 RTGCPHYS GCPhysPc;
312 uint64_t off;
313 if ( pVCpu->iem.s.pbInstrBuf
314 && (off = uPc - pVCpu->iem.s.uInstrBufPc) < pVCpu->iem.s.cbInstrBufTotal) /*ugly*/
315 {
316 pVCpu->iem.s.offInstrNextByte = (uint32_t)off;
317 pVCpu->iem.s.offCurInstrStart = (uint16_t)off;
318 if ((uint16_t)off + 15 <= pVCpu->iem.s.cbInstrBufTotal)
319 pVCpu->iem.s.cbInstrBuf = (uint16_t)off + 15;
320 else
321 pVCpu->iem.s.cbInstrBuf = pVCpu->iem.s.cbInstrBufTotal;
322 GCPhysPc = pVCpu->iem.s.GCPhysInstrBuf + off;
323 }
324 else
325 {
326 pVCpu->iem.s.pbInstrBuf = NULL;
327 pVCpu->iem.s.offCurInstrStart = 0;
328 pVCpu->iem.s.offInstrNextByte = 0;
329 iemOpcodeFetchBytesJmp(pVCpu, 0, NULL);
330 GCPhysPc = pVCpu->iem.s.pbInstrBuf ? pVCpu->iem.s.GCPhysInstrBuf + pVCpu->iem.s.offCurInstrStart : NIL_RTGCPHYS;
331 }
332
333 if (pNewTb->GCPhysPc == GCPhysPc)
334 {
335 /*
336 * Check for interrupts and stuff.
337 */
338 /** @todo We duplicate code here that's also in iemNativeHlpReturnBreakViaLookupWithPc.
339 * The main problem are the statistics and to some degree the logging. :/ */
340 if (!a_fWithIrqCheck || !iemNativeHlpReturnBreakViaLookupIsIrqOrForceFlagPending(pVCpu) )
341 {
342 /* Do polling. */
343 if ( RT_LIKELY((int32_t)--pVCpu->iem.s.cTbsTillNextTimerPoll > 0)
344 || iemPollTimers(pVCpu->CTX_SUFF(pVM), pVCpu) == VINF_SUCCESS)
345 {
346 /*
347 * Success. Update statistics and switch to the next TB.
348 */
349 if (a_fWithIrqCheck)
350 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking2Irq);
351 else
352 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking2NoIrq);
353
354 pNewTb->cUsed += 1;
355 pNewTb->msLastUsed = pVCpu->iem.s.msRecompilerPollNow;
356 pVCpu->iem.s.pCurTbR3 = pNewTb;
357 pVCpu->iem.s.ppTbLookupEntryR3 = IEMTB_GET_TB_LOOKUP_TAB_ENTRY(pNewTb, 0);
358 pVCpu->iem.s.cTbExecNative += 1;
359 Log10(("iemNativeHlpReturnBreakViaLookupWithTlb: match at %04x:%08RX64 (%RGp): pTb=%p[%#x]-> %p\n",
360 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysPc, pTb, idxTbLookup, pNewTb));
361 return (uintptr_t)pNewTb->Native.paInstructions;
362 }
363 }
364 Log10(("iemNativeHlpReturnBreakViaLookupWithTlb: IRQ or FF pending\n"));
365 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking2PendingIrq);
366 }
367 else
368 {
369 Log10(("iemNativeHlpReturnBreakViaLookupWithTlb: GCPhysPc mismatch at %04x:%08RX64: %RGp vs %RGp (pTb=%p[%#x]-> %p)\n",
370 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysPc, pNewTb->GCPhysPc, pTb, idxTbLookup, pNewTb));
371 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking2MismatchGCPhysPc);
372 }
373 }
374 else
375 {
376 Log10(("iemNativeHlpReturnBreakViaLookupWithTlb: fFlags mismatch at %04x:%08RX64: %#x vs %#x (pTb=%p[%#x]-> %p)\n",
377 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fFlags, pNewTb->fFlags, pTb, idxTbLookup, pNewTb));
378 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking2MismatchFlags);
379 }
380 }
381 else
382 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking2NoTb);
383#else
384 NOREF(fFlags);
385 STAM_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitDirectLinking2NoTb); /* just for some stats, even if misleading */
386#endif
387
388 pVCpu->iem.s.ppTbLookupEntryR3 = ppNewTb;
389 return 0;
390}
391
392
393/**
394 * Used by TB code when it wants to raise a \#DE.
395 */
396IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseDe,(PVMCPUCC pVCpu))
397{
398 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseDe);
399 iemRaiseDivideErrorJmp(pVCpu);
400#ifndef _MSC_VER
401 return VINF_IEM_RAISED_XCPT; /* not reached */
402#endif
403}
404
405
406/**
407 * Used by TB code when it wants to raise a \#UD.
408 */
409IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseUd,(PVMCPUCC pVCpu))
410{
411 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseUd);
412 iemRaiseUndefinedOpcodeJmp(pVCpu);
413#ifndef _MSC_VER
414 return VINF_IEM_RAISED_XCPT; /* not reached */
415#endif
416}
417
418
419/**
420 * Used by TB code when it wants to raise an SSE related \#UD or \#NM.
421 *
422 * See IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT.
423 */
424IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseSseRelated,(PVMCPUCC pVCpu))
425{
426 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseSseRelated);
427 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
428 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
429 iemRaiseUndefinedOpcodeJmp(pVCpu);
430 else
431 iemRaiseDeviceNotAvailableJmp(pVCpu);
432#ifndef _MSC_VER
433 return VINF_IEM_RAISED_XCPT; /* not reached */
434#endif
435}
436
437
438/**
439 * Used by TB code when it wants to raise an AVX related \#UD or \#NM.
440 *
441 * See IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT.
442 */
443IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseAvxRelated,(PVMCPUCC pVCpu))
444{
445 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseAvxRelated);
446 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE)
447 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
448 iemRaiseUndefinedOpcodeJmp(pVCpu);
449 else
450 iemRaiseDeviceNotAvailableJmp(pVCpu);
451#ifndef _MSC_VER
452 return VINF_IEM_RAISED_XCPT; /* not reached */
453#endif
454}
455
456
457/**
458 * Used by TB code when it wants to raise an SSE/AVX floating point exception related \#UD or \#XF.
459 *
460 * See IEM_MC_CALL_AVX_XXX/IEM_MC_CALL_SSE_XXX.
461 */
462IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseSseAvxFpRelated,(PVMCPUCC pVCpu))
463{
464 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseSseAvxFpRelated);
465 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)
466 iemRaiseSimdFpExceptionJmp(pVCpu);
467 else
468 iemRaiseUndefinedOpcodeJmp(pVCpu);
469#ifndef _MSC_VER
470 return VINF_IEM_RAISED_XCPT; /* not reached */
471#endif
472}
473
474
475/**
476 * Used by TB code when it wants to raise a \#NM.
477 */
478IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseNm,(PVMCPUCC pVCpu))
479{
480 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseNm);
481 iemRaiseDeviceNotAvailableJmp(pVCpu);
482#ifndef _MSC_VER
483 return VINF_IEM_RAISED_XCPT; /* not reached */
484#endif
485}
486
487
488/**
489 * Used by TB code when it wants to raise a \#GP(0).
490 */
491IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseGp0,(PVMCPUCC pVCpu))
492{
493 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseGp0);
494 iemRaiseGeneralProtectionFault0Jmp(pVCpu);
495#ifndef _MSC_VER
496 return VINF_IEM_RAISED_XCPT; /* not reached */
497#endif
498}
499
500
501/**
502 * Used by TB code when it wants to raise a \#MF.
503 */
504IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseMf,(PVMCPUCC pVCpu))
505{
506 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseMf);
507 iemRaiseMathFaultJmp(pVCpu);
508#ifndef _MSC_VER
509 return VINF_IEM_RAISED_XCPT; /* not reached */
510#endif
511}
512
513
514/**
515 * Used by TB code when it wants to raise a \#XF.
516 */
517IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseXf,(PVMCPUCC pVCpu))
518{
519 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitRaiseXf);
520 iemRaiseSimdFpExceptionJmp(pVCpu);
521#ifndef _MSC_VER
522 return VINF_IEM_RAISED_XCPT; /* not reached */
523#endif
524}
525
526
527/**
528 * Used by TB code when detecting opcode changes.
529 * @see iemThreadeFuncWorkerObsoleteTb
530 */
531IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpObsoleteTb,(PVMCPUCC pVCpu))
532{
533 /* We set fSafeToFree to false where as we're being called in the context
534 of a TB callback function, which for native TBs means we cannot release
535 the executable memory till we've returned our way back to iemTbExec as
536 that return path codes via the native code generated for the TB. */
537 Log7(("TB obsolete: %p at %04x:%08RX64\n", pVCpu->iem.s.pCurTbR3, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
538 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeTbExitObsoleteTb);
539 iemThreadedTbObsolete(pVCpu, pVCpu->iem.s.pCurTbR3, false /*fSafeToFree*/);
540 return VINF_IEM_REEXEC_BREAK;
541}
542
543
544/**
545 * Used by TB code when we need to switch to a TB with CS.LIM checking.
546 */
547IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpNeedCsLimChecking,(PVMCPUCC pVCpu))
548{
549 Log7(("TB need CS.LIM: %p at %04x:%08RX64; offFromLim=%#RX64 CS.LIM=%#RX32 CS.BASE=%#RX64\n",
550 pVCpu->iem.s.pCurTbR3, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
551 (int64_t)pVCpu->cpum.GstCtx.cs.u32Limit - (int64_t)pVCpu->cpum.GstCtx.rip,
552 pVCpu->cpum.GstCtx.cs.u32Limit, pVCpu->cpum.GstCtx.cs.u64Base));
553 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatCheckNeedCsLimChecking);
554 return VINF_IEM_REEXEC_BREAK;
555}
556
557
558/**
559 * Used by TB code when we missed a PC check after a branch.
560 */
561IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpCheckBranchMiss,(PVMCPUCC pVCpu))
562{
563 Log7(("TB jmp miss: %p at %04x:%08RX64; GCPhysWithOffset=%RGp, pbInstrBuf=%p\n",
564 pVCpu->iem.s.pCurTbR3, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
565 pVCpu->iem.s.GCPhysInstrBuf + pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base - pVCpu->iem.s.uInstrBufPc,
566 pVCpu->iem.s.pbInstrBuf));
567 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatCheckBranchMisses);
568 return VINF_IEM_REEXEC_BREAK;
569}
570
571
572
573/*********************************************************************************************************************************
574* Helpers: Segmented memory fetches and stores. *
575*********************************************************************************************************************************/
576
577/**
578 * Used by TB code to load unsigned 8-bit data w/ segmentation.
579 */
580IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
581{
582#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
583 return (uint64_t)iemMemFetchDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem);
584#else
585 return (uint64_t)iemMemFetchDataU8Jmp(pVCpu, iSegReg, GCPtrMem);
586#endif
587}
588
589
590/**
591 * Used by TB code to load signed 8-bit data w/ segmentation, sign extending it
592 * to 16 bits.
593 */
594IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
595{
596#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
597 return (uint64_t)(uint16_t)(int16_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem);
598#else
599 return (uint64_t)(uint16_t)(int16_t)(int8_t)iemMemFetchDataU8Jmp(pVCpu, iSegReg, GCPtrMem);
600#endif
601}
602
603
604/**
605 * Used by TB code to load signed 8-bit data w/ segmentation, sign extending it
606 * to 32 bits.
607 */
608IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
609{
610#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
611 return (uint64_t)(uint32_t)(int32_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem);
612#else
613 return (uint64_t)(uint32_t)(int32_t)(int8_t)iemMemFetchDataU8Jmp(pVCpu, iSegReg, GCPtrMem);
614#endif
615}
616
617/**
618 * Used by TB code to load signed 8-bit data w/ segmentation, sign extending it
619 * to 64 bits.
620 */
621IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
622{
623#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
624 return (uint64_t)(int64_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem);
625#else
626 return (uint64_t)(int64_t)(int8_t)iemMemFetchDataU8Jmp(pVCpu, iSegReg, GCPtrMem);
627#endif
628}
629
630
631/**
632 * Used by TB code to load unsigned 16-bit data w/ segmentation.
633 */
634IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
635{
636#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
637 return (uint64_t)iemMemFetchDataU16SafeJmp(pVCpu, iSegReg, GCPtrMem);
638#else
639 return (uint64_t)iemMemFetchDataU16Jmp(pVCpu, iSegReg, GCPtrMem);
640#endif
641}
642
643
644/**
645 * Used by TB code to load signed 16-bit data w/ segmentation, sign extending it
646 * to 32 bits.
647 */
648IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU16_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
649{
650#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
651 return (uint64_t)(uint32_t)(int32_t)(int16_t)iemMemFetchDataU16SafeJmp(pVCpu, iSegReg, GCPtrMem);
652#else
653 return (uint64_t)(uint32_t)(int32_t)(int16_t)iemMemFetchDataU16Jmp(pVCpu, iSegReg, GCPtrMem);
654#endif
655}
656
657
658/**
659 * Used by TB code to load signed 16-bit data w/ segmentation, sign extending it
660 * to 64 bits.
661 */
662IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU16_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
663{
664#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
665 return (uint64_t)(int64_t)(int16_t)iemMemFetchDataU16SafeJmp(pVCpu, iSegReg, GCPtrMem);
666#else
667 return (uint64_t)(int64_t)(int16_t)iemMemFetchDataU16Jmp(pVCpu, iSegReg, GCPtrMem);
668#endif
669}
670
671
672/**
673 * Used by TB code to load unsigned 32-bit data w/ segmentation.
674 */
675IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
676{
677#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
678 return (uint64_t)iemMemFetchDataU32SafeJmp(pVCpu, iSegReg, GCPtrMem);
679#else
680 return (uint64_t)iemMemFetchDataU32Jmp(pVCpu, iSegReg, GCPtrMem);
681#endif
682}
683
684
685/**
686 * Used by TB code to load signed 32-bit data w/ segmentation, sign extending it
687 * to 64 bits.
688 */
689IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU32_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
690{
691#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
692 return (uint64_t)(int64_t)(int32_t)iemMemFetchDataU32SafeJmp(pVCpu, iSegReg, GCPtrMem);
693#else
694 return (uint64_t)(int64_t)(int32_t)iemMemFetchDataU32Jmp(pVCpu, iSegReg, GCPtrMem);
695#endif
696}
697
698
699/**
700 * Used by TB code to load unsigned 64-bit data w/ segmentation.
701 */
702IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
703{
704#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
705 return iemMemFetchDataU64SafeJmp(pVCpu, iSegReg, GCPtrMem);
706#else
707 return iemMemFetchDataU64Jmp(pVCpu, iSegReg, GCPtrMem);
708#endif
709}
710
711
712#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
713/**
714 * Used by TB code to load 128-bit data w/ segmentation.
715 */
716IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFetchDataU128,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT128U pu128Dst))
717{
718#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
719 iemMemFetchDataU128SafeJmp(pVCpu, pu128Dst, iSegReg, GCPtrMem);
720#else
721 iemMemFetchDataU128Jmp(pVCpu, pu128Dst, iSegReg, GCPtrMem);
722#endif
723}
724
725
726/**
727 * Used by TB code to load 128-bit data w/ segmentation.
728 */
729IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFetchDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT128U pu128Dst))
730{
731#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
732 iemMemFetchDataU128AlignedSseSafeJmp(pVCpu, pu128Dst, iSegReg, GCPtrMem);
733#else
734 iemMemFetchDataU128AlignedSseJmp(pVCpu, pu128Dst, iSegReg, GCPtrMem);
735#endif
736}
737
738
739/**
740 * Used by TB code to load 128-bit data w/ segmentation.
741 */
742IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFetchDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT128U pu128Dst))
743{
744#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
745 iemMemFetchDataU128NoAcSafeJmp(pVCpu, pu128Dst, iSegReg, GCPtrMem);
746#else
747 iemMemFetchDataU128NoAcJmp(pVCpu, pu128Dst, iSegReg, GCPtrMem);
748#endif
749}
750
751
752/**
753 * Used by TB code to load 256-bit data w/ segmentation.
754 */
755IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFetchDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT256U pu256Dst))
756{
757#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
758 iemMemFetchDataU256NoAcSafeJmp(pVCpu, pu256Dst, iSegReg, GCPtrMem);
759#else
760 iemMemFetchDataU256NoAcJmp(pVCpu, pu256Dst, iSegReg, GCPtrMem);
761#endif
762}
763
764
765/**
766 * Used by TB code to load 256-bit data w/ segmentation.
767 */
768IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFetchDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT256U pu256Dst))
769{
770#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
771 iemMemFetchDataU256AlignedAvxSafeJmp(pVCpu, pu256Dst, iSegReg, GCPtrMem);
772#else
773 iemMemFetchDataU256AlignedAvxJmp(pVCpu, pu256Dst, iSegReg, GCPtrMem);
774#endif
775}
776#endif
777
778
779/**
780 * Used by TB code to store unsigned 8-bit data w/ segmentation.
781 */
782IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint8_t u8Value))
783{
784#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
785 iemMemStoreDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem, u8Value);
786#else
787 iemMemStoreDataU8Jmp(pVCpu, iSegReg, GCPtrMem, u8Value);
788#endif
789}
790
791
792/**
793 * Used by TB code to store unsigned 16-bit data w/ segmentation.
794 */
795IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint16_t u16Value))
796{
797#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
798 iemMemStoreDataU16SafeJmp(pVCpu, iSegReg, GCPtrMem, u16Value);
799#else
800 iemMemStoreDataU16Jmp(pVCpu, iSegReg, GCPtrMem, u16Value);
801#endif
802}
803
804
805/**
806 * Used by TB code to store unsigned 32-bit data w/ segmentation.
807 */
808IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint32_t u32Value))
809{
810#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
811 iemMemStoreDataU32SafeJmp(pVCpu, iSegReg, GCPtrMem, u32Value);
812#else
813 iemMemStoreDataU32Jmp(pVCpu, iSegReg, GCPtrMem, u32Value);
814#endif
815}
816
817
818/**
819 * Used by TB code to store unsigned 64-bit data w/ segmentation.
820 */
821IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint64_t u64Value))
822{
823#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
824 iemMemStoreDataU64SafeJmp(pVCpu, iSegReg, GCPtrMem, u64Value);
825#else
826 iemMemStoreDataU64Jmp(pVCpu, iSegReg, GCPtrMem, u64Value);
827#endif
828}
829
830
831#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
832/**
833 * Used by TB code to store unsigned 128-bit data w/ segmentation.
834 */
835IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src))
836{
837#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
838 iemMemStoreDataU128AlignedSseSafeJmp(pVCpu, iSegReg, GCPtrMem, pu128Src);
839#else
840 iemMemStoreDataU128AlignedSseJmp(pVCpu, iSegReg, GCPtrMem, pu128Src);
841#endif
842}
843
844
845/**
846 * Used by TB code to store unsigned 128-bit data w/ segmentation.
847 */
848IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src))
849{
850#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
851 iemMemStoreDataU128NoAcSafeJmp(pVCpu, iSegReg, GCPtrMem, pu128Src);
852#else
853 iemMemStoreDataU128NoAcJmp(pVCpu, iSegReg, GCPtrMem, pu128Src);
854#endif
855}
856
857
858/**
859 * Used by TB code to store unsigned 256-bit data w/ segmentation.
860 */
861IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT256U pu256Src))
862{
863#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
864 iemMemStoreDataU256NoAcSafeJmp(pVCpu, iSegReg, GCPtrMem, pu256Src);
865#else
866 iemMemStoreDataU256NoAcJmp(pVCpu, iSegReg, GCPtrMem, pu256Src);
867#endif
868}
869
870
871/**
872 * Used by TB code to store unsigned 256-bit data w/ segmentation.
873 */
874IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT256U pu256Src))
875{
876#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
877 iemMemStoreDataU256AlignedAvxSafeJmp(pVCpu, iSegReg, GCPtrMem, pu256Src);
878#else
879 iemMemStoreDataU256AlignedAvxJmp(pVCpu, iSegReg, GCPtrMem, pu256Src);
880#endif
881}
882#endif
883
884
885
886/**
887 * Used by TB code to store an unsigned 16-bit value onto a generic stack.
888 */
889IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value))
890{
891#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
892 iemMemStoreStackU16SafeJmp(pVCpu, GCPtrMem, u16Value);
893#else
894 iemMemStoreStackU16Jmp(pVCpu, GCPtrMem, u16Value);
895#endif
896}
897
898
899/**
900 * Used by TB code to store an unsigned 32-bit value onto a generic stack.
901 */
902IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
903{
904#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
905 iemMemStoreStackU32SafeJmp(pVCpu, GCPtrMem, u32Value);
906#else
907 iemMemStoreStackU32Jmp(pVCpu, GCPtrMem, u32Value);
908#endif
909}
910
911
912/**
913 * Used by TB code to store an 32-bit selector value onto a generic stack.
914 *
915 * Intel CPUs doesn't do write a whole dword, thus the special function.
916 */
917IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackStoreU32SReg,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
918{
919#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
920 iemMemStoreStackU32SRegSafeJmp(pVCpu, GCPtrMem, u32Value);
921#else
922 iemMemStoreStackU32SRegJmp(pVCpu, GCPtrMem, u32Value);
923#endif
924}
925
926
927/**
928 * Used by TB code to push unsigned 64-bit value onto a generic stack.
929 */
930IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackStoreU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value))
931{
932#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
933 iemMemStoreStackU64SafeJmp(pVCpu, GCPtrMem, u64Value);
934#else
935 iemMemStoreStackU64Jmp(pVCpu, GCPtrMem, u64Value);
936#endif
937}
938
939
940/**
941 * Used by TB code to fetch an unsigned 16-bit item off a generic stack.
942 */
943IEM_DECL_NATIVE_HLP_DEF(uint16_t, iemNativeHlpStackFetchU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
944{
945#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
946 return iemMemFetchStackU16SafeJmp(pVCpu, GCPtrMem);
947#else
948 return iemMemFetchStackU16Jmp(pVCpu, GCPtrMem);
949#endif
950}
951
952
953/**
954 * Used by TB code to fetch an unsigned 32-bit item off a generic stack.
955 */
956IEM_DECL_NATIVE_HLP_DEF(uint32_t, iemNativeHlpStackFetchU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
957{
958#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
959 return iemMemFetchStackU32SafeJmp(pVCpu, GCPtrMem);
960#else
961 return iemMemFetchStackU32Jmp(pVCpu, GCPtrMem);
962#endif
963}
964
965
966/**
967 * Used by TB code to fetch an unsigned 64-bit item off a generic stack.
968 */
969IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpStackFetchU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
970{
971#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
972 return iemMemFetchStackU64SafeJmp(pVCpu, GCPtrMem);
973#else
974 return iemMemFetchStackU64Jmp(pVCpu, GCPtrMem);
975#endif
976}
977
978
979
980/*********************************************************************************************************************************
981* Helpers: Flat memory fetches and stores. *
982*********************************************************************************************************************************/
983
984/**
985 * Used by TB code to load unsigned 8-bit data w/ flat address.
986 * @note Zero extending the value to 64-bit to simplify assembly.
987 */
988IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
989{
990#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
991 return (uint64_t)iemMemFetchDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
992#else
993 return (uint64_t)iemMemFlatFetchDataU8Jmp(pVCpu, GCPtrMem);
994#endif
995}
996
997
998/**
999 * Used by TB code to load signed 8-bit data w/ flat address, sign extending it
1000 * to 16 bits.
1001 * @note Zero extending the value to 64-bit to simplify assembly.
1002 */
1003IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1004{
1005#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1006 return (uint64_t)(uint16_t)(int16_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1007#else
1008 return (uint64_t)(uint16_t)(int16_t)(int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, GCPtrMem);
1009#endif
1010}
1011
1012
1013/**
1014 * Used by TB code to load signed 8-bit data w/ flat address, sign extending it
1015 * to 32 bits.
1016 * @note Zero extending the value to 64-bit to simplify assembly.
1017 */
1018IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1019{
1020#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1021 return (uint64_t)(uint32_t)(int32_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1022#else
1023 return (uint64_t)(uint32_t)(int32_t)(int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, GCPtrMem);
1024#endif
1025}
1026
1027
1028/**
1029 * Used by TB code to load signed 8-bit data w/ flat address, sign extending it
1030 * to 64 bits.
1031 */
1032IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1033{
1034#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1035 return (uint64_t)(int64_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1036#else
1037 return (uint64_t)(int64_t)(int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, GCPtrMem);
1038#endif
1039}
1040
1041
1042/**
1043 * Used by TB code to load unsigned 16-bit data w/ flat address.
1044 * @note Zero extending the value to 64-bit to simplify assembly.
1045 */
1046IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1047{
1048#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1049 return (uint64_t)iemMemFetchDataU16SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1050#else
1051 return (uint64_t)iemMemFlatFetchDataU16Jmp(pVCpu, GCPtrMem);
1052#endif
1053}
1054
1055
1056/**
1057 * Used by TB code to load signed 16-bit data w/ flat address, sign extending it
1058 * to 32 bits.
1059 * @note Zero extending the value to 64-bit to simplify assembly.
1060 */
1061IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU16_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1062{
1063#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1064 return (uint64_t)(uint32_t)(int32_t)(int16_t)iemMemFetchDataU16SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1065#else
1066 return (uint64_t)(uint32_t)(int32_t)(int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, GCPtrMem);
1067#endif
1068}
1069
1070
1071/**
1072 * Used by TB code to load signed 16-bit data w/ flat address, sign extending it
1073 * to 64 bits.
1074 * @note Zero extending the value to 64-bit to simplify assembly.
1075 */
1076IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU16_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1077{
1078#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1079 return (uint64_t)(int64_t)(int16_t)iemMemFetchDataU16SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1080#else
1081 return (uint64_t)(int64_t)(int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, GCPtrMem);
1082#endif
1083}
1084
1085
1086/**
1087 * Used by TB code to load unsigned 32-bit data w/ flat address.
1088 * @note Zero extending the value to 64-bit to simplify assembly.
1089 */
1090IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1091{
1092#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1093 return (uint64_t)iemMemFetchDataU32SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1094#else
1095 return (uint64_t)iemMemFlatFetchDataU32Jmp(pVCpu, GCPtrMem);
1096#endif
1097}
1098
1099
1100/**
1101 * Used by TB code to load signed 32-bit data w/ flat address, sign extending it
1102 * to 64 bits.
1103 * @note Zero extending the value to 64-bit to simplify assembly.
1104 */
1105IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU32_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1106{
1107#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1108 return (uint64_t)(int64_t)(int32_t)iemMemFetchDataU32SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1109#else
1110 return (uint64_t)(int64_t)(int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, GCPtrMem);
1111#endif
1112}
1113
1114
1115/**
1116 * Used by TB code to load unsigned 64-bit data w/ flat address.
1117 */
1118IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1119{
1120#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1121 return iemMemFetchDataU64SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1122#else
1123 return iemMemFlatFetchDataU64Jmp(pVCpu, GCPtrMem);
1124#endif
1125}
1126
1127
1128#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1129/**
1130 * Used by TB code to load unsigned 128-bit data w/ flat address.
1131 */
1132IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatFetchDataU128,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT128U pu128Dst))
1133{
1134#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1135 return iemMemFetchDataU128SafeJmp(pVCpu, pu128Dst, UINT8_MAX, GCPtrMem);
1136#else
1137 return iemMemFlatFetchDataU128Jmp(pVCpu, pu128Dst, GCPtrMem);
1138#endif
1139}
1140
1141
1142/**
1143 * Used by TB code to load unsigned 128-bit data w/ flat address.
1144 */
1145IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatFetchDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT128U pu128Dst))
1146{
1147#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1148 return iemMemFetchDataU128AlignedSseSafeJmp(pVCpu, pu128Dst, UINT8_MAX, GCPtrMem);
1149#else
1150 return iemMemFlatFetchDataU128AlignedSseJmp(pVCpu, pu128Dst, GCPtrMem);
1151#endif
1152}
1153
1154
1155/**
1156 * Used by TB code to load unsigned 128-bit data w/ flat address.
1157 */
1158IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatFetchDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT128U pu128Dst))
1159{
1160#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1161 return iemMemFetchDataU128NoAcSafeJmp(pVCpu, pu128Dst, UINT8_MAX, GCPtrMem);
1162#else
1163 return iemMemFlatFetchDataU128NoAcJmp(pVCpu, pu128Dst, GCPtrMem);
1164#endif
1165}
1166
1167
1168/**
1169 * Used by TB code to load unsigned 256-bit data w/ flat address.
1170 */
1171IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatFetchDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT256U pu256Dst))
1172{
1173#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1174 return iemMemFetchDataU256NoAcSafeJmp(pVCpu, pu256Dst, UINT8_MAX, GCPtrMem);
1175#else
1176 return iemMemFlatFetchDataU256NoAcJmp(pVCpu, pu256Dst, GCPtrMem);
1177#endif
1178}
1179
1180
1181/**
1182 * Used by TB code to load unsigned 256-bit data w/ flat address.
1183 */
1184IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatFetchDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT256U pu256Dst))
1185{
1186#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1187 return iemMemFetchDataU256AlignedAvxSafeJmp(pVCpu, pu256Dst, UINT8_MAX, GCPtrMem);
1188#else
1189 return iemMemFlatFetchDataU256AlignedAvxJmp(pVCpu, pu256Dst, GCPtrMem);
1190#endif
1191}
1192#endif
1193
1194
1195/**
1196 * Used by TB code to store unsigned 8-bit data w/ flat address.
1197 */
1198IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t u8Value))
1199{
1200#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1201 iemMemStoreDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem, u8Value);
1202#else
1203 iemMemFlatStoreDataU8Jmp(pVCpu, GCPtrMem, u8Value);
1204#endif
1205}
1206
1207
1208/**
1209 * Used by TB code to store unsigned 16-bit data w/ flat address.
1210 */
1211IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value))
1212{
1213#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1214 iemMemStoreDataU16SafeJmp(pVCpu, UINT8_MAX, GCPtrMem, u16Value);
1215#else
1216 iemMemFlatStoreDataU16Jmp(pVCpu, GCPtrMem, u16Value);
1217#endif
1218}
1219
1220
1221/**
1222 * Used by TB code to store unsigned 32-bit data w/ flat address.
1223 */
1224IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
1225{
1226#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1227 iemMemStoreDataU32SafeJmp(pVCpu, UINT8_MAX, GCPtrMem, u32Value);
1228#else
1229 iemMemFlatStoreDataU32Jmp(pVCpu, GCPtrMem, u32Value);
1230#endif
1231}
1232
1233
1234/**
1235 * Used by TB code to store unsigned 64-bit data w/ flat address.
1236 */
1237IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value))
1238{
1239#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1240 iemMemStoreDataU64SafeJmp(pVCpu, UINT8_MAX, GCPtrMem, u64Value);
1241#else
1242 iemMemFlatStoreDataU64Jmp(pVCpu, GCPtrMem, u64Value);
1243#endif
1244}
1245
1246
1247#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1248/**
1249 * Used by TB code to store unsigned 128-bit data w/ flat address.
1250 */
1251IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src))
1252{
1253#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1254 iemMemStoreDataU128AlignedSseSafeJmp(pVCpu, UINT8_MAX, GCPtrMem, pu128Src);
1255#else
1256 iemMemFlatStoreDataU128AlignedSseJmp(pVCpu, GCPtrMem, pu128Src);
1257#endif
1258}
1259
1260
1261/**
1262 * Used by TB code to store unsigned 128-bit data w/ flat address.
1263 */
1264IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src))
1265{
1266#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1267 iemMemStoreDataU128NoAcSafeJmp(pVCpu, UINT8_MAX, GCPtrMem, pu128Src);
1268#else
1269 iemMemFlatStoreDataU128NoAcJmp(pVCpu, GCPtrMem, pu128Src);
1270#endif
1271}
1272
1273
1274/**
1275 * Used by TB code to store unsigned 256-bit data w/ flat address.
1276 */
1277IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT256U pu256Src))
1278{
1279#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1280 iemMemStoreDataU256NoAcSafeJmp(pVCpu, UINT8_MAX, GCPtrMem, pu256Src);
1281#else
1282 iemMemFlatStoreDataU256NoAcJmp(pVCpu, GCPtrMem, pu256Src);
1283#endif
1284}
1285
1286
1287/**
1288 * Used by TB code to store unsigned 256-bit data w/ flat address.
1289 */
1290IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT256U pu256Src))
1291{
1292#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1293 iemMemStoreDataU256AlignedAvxSafeJmp(pVCpu, UINT8_MAX, GCPtrMem, pu256Src);
1294#else
1295 iemMemFlatStoreDataU256AlignedAvxJmp(pVCpu, GCPtrMem, pu256Src);
1296#endif
1297}
1298#endif
1299
1300
1301
1302/**
1303 * Used by TB code to store an unsigned 16-bit value onto a flat stack.
1304 */
1305IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackFlatStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value))
1306{
1307#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
1308 iemMemStoreStackU16SafeJmp(pVCpu, GCPtrMem, u16Value);
1309#else
1310 iemMemFlatStoreStackU16Jmp(pVCpu, GCPtrMem, u16Value);
1311#endif
1312}
1313
1314
1315/**
1316 * Used by TB code to store an unsigned 32-bit value onto a flat stack.
1317 */
1318IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackFlatStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
1319{
1320#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
1321 iemMemStoreStackU32SafeJmp(pVCpu, GCPtrMem, u32Value);
1322#else
1323 iemMemFlatStoreStackU32Jmp(pVCpu, GCPtrMem, u32Value);
1324#endif
1325}
1326
1327
1328/**
1329 * Used by TB code to store a segment selector value onto a flat stack.
1330 *
1331 * Intel CPUs doesn't do write a whole dword, thus the special function.
1332 */
1333IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackFlatStoreU32SReg,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
1334{
1335#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
1336 iemMemStoreStackU32SRegSafeJmp(pVCpu, GCPtrMem, u32Value);
1337#else
1338 iemMemFlatStoreStackU32SRegJmp(pVCpu, GCPtrMem, u32Value);
1339#endif
1340}
1341
1342
1343/**
1344 * Used by TB code to store an unsigned 64-bit value onto a flat stack.
1345 */
1346IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackFlatStoreU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value))
1347{
1348#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
1349 iemMemStoreStackU64SafeJmp(pVCpu, GCPtrMem, u64Value);
1350#else
1351 iemMemFlatStoreStackU64Jmp(pVCpu, GCPtrMem, u64Value);
1352#endif
1353}
1354
1355
1356/**
1357 * Used by TB code to fetch an unsigned 16-bit item off a generic stack.
1358 */
1359IEM_DECL_NATIVE_HLP_DEF(uint16_t, iemNativeHlpStackFlatFetchU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1360{
1361#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
1362 return iemMemFetchStackU16SafeJmp(pVCpu, GCPtrMem);
1363#else
1364 return iemMemFlatFetchStackU16Jmp(pVCpu, GCPtrMem);
1365#endif
1366}
1367
1368
1369/**
1370 * Used by TB code to fetch an unsigned 32-bit item off a generic stack.
1371 */
1372IEM_DECL_NATIVE_HLP_DEF(uint32_t, iemNativeHlpStackFlatFetchU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1373{
1374#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
1375 return iemMemFetchStackU32SafeJmp(pVCpu, GCPtrMem);
1376#else
1377 return iemMemFlatFetchStackU32Jmp(pVCpu, GCPtrMem);
1378#endif
1379}
1380
1381
1382/**
1383 * Used by TB code to fetch an unsigned 64-bit item off a generic stack.
1384 */
1385IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpStackFlatFetchU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1386{
1387#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
1388 return iemMemFetchStackU64SafeJmp(pVCpu, GCPtrMem);
1389#else
1390 return iemMemFlatFetchStackU64Jmp(pVCpu, GCPtrMem);
1391#endif
1392}
1393
1394
1395
1396/*********************************************************************************************************************************
1397* Helpers: Segmented memory mapping. *
1398*********************************************************************************************************************************/
1399
1400/**
1401 * Used by TB code to map unsigned 8-bit data for atomic read-write w/
1402 * segmentation.
1403 */
1404IEM_DECL_NATIVE_HLP_DEF(uint8_t *, iemNativeHlpMemMapDataU8Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1405 RTGCPTR GCPtrMem, uint8_t iSegReg))
1406{
1407#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1408 return iemMemMapDataU8AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1409#else
1410 return iemMemMapDataU8AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1411#endif
1412}
1413
1414
1415/**
1416 * Used by TB code to map unsigned 8-bit data read-write w/ segmentation.
1417 */
1418IEM_DECL_NATIVE_HLP_DEF(uint8_t *, iemNativeHlpMemMapDataU8Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1419 RTGCPTR GCPtrMem, uint8_t iSegReg))
1420{
1421#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1422 return iemMemMapDataU8RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1423#else
1424 return iemMemMapDataU8RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1425#endif
1426}
1427
1428
1429/**
1430 * Used by TB code to map unsigned 8-bit data writeonly w/ segmentation.
1431 */
1432IEM_DECL_NATIVE_HLP_DEF(uint8_t *, iemNativeHlpMemMapDataU8Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1433 RTGCPTR GCPtrMem, uint8_t iSegReg))
1434{
1435#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1436 return iemMemMapDataU8WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1437#else
1438 return iemMemMapDataU8WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1439#endif
1440}
1441
1442
1443/**
1444 * Used by TB code to map unsigned 8-bit data readonly w/ segmentation.
1445 */
1446IEM_DECL_NATIVE_HLP_DEF(uint8_t const *, iemNativeHlpMemMapDataU8Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1447 RTGCPTR GCPtrMem, uint8_t iSegReg))
1448{
1449#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1450 return iemMemMapDataU8RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1451#else
1452 return iemMemMapDataU8RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1453#endif
1454}
1455
1456
1457/**
1458 * Used by TB code to map unsigned 16-bit data for atomic read-write w/
1459 * segmentation.
1460 */
1461IEM_DECL_NATIVE_HLP_DEF(uint16_t *, iemNativeHlpMemMapDataU16Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1462 RTGCPTR GCPtrMem, uint8_t iSegReg))
1463{
1464#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1465 return iemMemMapDataU16AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1466#else
1467 return iemMemMapDataU16AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1468#endif
1469}
1470
1471
1472/**
1473 * Used by TB code to map unsigned 16-bit data read-write w/ segmentation.
1474 */
1475IEM_DECL_NATIVE_HLP_DEF(uint16_t *, iemNativeHlpMemMapDataU16Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1476 RTGCPTR GCPtrMem, uint8_t iSegReg))
1477{
1478#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1479 return iemMemMapDataU16RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1480#else
1481 return iemMemMapDataU16RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1482#endif
1483}
1484
1485
1486/**
1487 * Used by TB code to map unsigned 16-bit data writeonly w/ segmentation.
1488 */
1489IEM_DECL_NATIVE_HLP_DEF(uint16_t *, iemNativeHlpMemMapDataU16Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1490 RTGCPTR GCPtrMem, uint8_t iSegReg))
1491{
1492#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1493 return iemMemMapDataU16WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1494#else
1495 return iemMemMapDataU16WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1496#endif
1497}
1498
1499
1500/**
1501 * Used by TB code to map unsigned 16-bit data readonly w/ segmentation.
1502 */
1503IEM_DECL_NATIVE_HLP_DEF(uint16_t const *, iemNativeHlpMemMapDataU16Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1504 RTGCPTR GCPtrMem, uint8_t iSegReg))
1505{
1506#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1507 return iemMemMapDataU16RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1508#else
1509 return iemMemMapDataU16RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1510#endif
1511}
1512
1513
1514/**
1515 * Used by TB code to map unsigned 32-bit data for atomic read-write w/
1516 * segmentation.
1517 */
1518IEM_DECL_NATIVE_HLP_DEF(uint32_t *, iemNativeHlpMemMapDataU32Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1519 RTGCPTR GCPtrMem, uint8_t iSegReg))
1520{
1521#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1522 return iemMemMapDataU32AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1523#else
1524 return iemMemMapDataU32AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1525#endif
1526}
1527
1528
1529/**
1530 * Used by TB code to map unsigned 32-bit data read-write w/ segmentation.
1531 */
1532IEM_DECL_NATIVE_HLP_DEF(uint32_t *, iemNativeHlpMemMapDataU32Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1533 RTGCPTR GCPtrMem, uint8_t iSegReg))
1534{
1535#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1536 return iemMemMapDataU32RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1537#else
1538 return iemMemMapDataU32RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1539#endif
1540}
1541
1542
1543/**
1544 * Used by TB code to map unsigned 32-bit data writeonly w/ segmentation.
1545 */
1546IEM_DECL_NATIVE_HLP_DEF(uint32_t *, iemNativeHlpMemMapDataU32Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1547 RTGCPTR GCPtrMem, uint8_t iSegReg))
1548{
1549#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1550 return iemMemMapDataU32WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1551#else
1552 return iemMemMapDataU32WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1553#endif
1554}
1555
1556
1557/**
1558 * Used by TB code to map unsigned 32-bit data readonly w/ segmentation.
1559 */
1560IEM_DECL_NATIVE_HLP_DEF(uint32_t const *, iemNativeHlpMemMapDataU32Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1561 RTGCPTR GCPtrMem, uint8_t iSegReg))
1562{
1563#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1564 return iemMemMapDataU32RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1565#else
1566 return iemMemMapDataU32RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1567#endif
1568}
1569
1570
1571/**
1572 * Used by TB code to map unsigned 64-bit data for atomic read-write w/
1573 * segmentation.
1574 */
1575IEM_DECL_NATIVE_HLP_DEF(uint64_t *, iemNativeHlpMemMapDataU64Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1576 RTGCPTR GCPtrMem, uint8_t iSegReg))
1577{
1578#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1579 return iemMemMapDataU64AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1580#else
1581 return iemMemMapDataU64AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1582#endif
1583}
1584
1585
1586/**
1587 * Used by TB code to map unsigned 64-bit data read-write w/ segmentation.
1588 */
1589IEM_DECL_NATIVE_HLP_DEF(uint64_t *, iemNativeHlpMemMapDataU64Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1590 RTGCPTR GCPtrMem, uint8_t iSegReg))
1591{
1592#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1593 return iemMemMapDataU64RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1594#else
1595 return iemMemMapDataU64RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1596#endif
1597}
1598
1599
1600/**
1601 * Used by TB code to map unsigned 64-bit data writeonly w/ segmentation.
1602 */
1603IEM_DECL_NATIVE_HLP_DEF(uint64_t *, iemNativeHlpMemMapDataU64Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1604 RTGCPTR GCPtrMem, uint8_t iSegReg))
1605{
1606#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1607 return iemMemMapDataU64WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1608#else
1609 return iemMemMapDataU64WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1610#endif
1611}
1612
1613
1614/**
1615 * Used by TB code to map unsigned 64-bit data readonly w/ segmentation.
1616 */
1617IEM_DECL_NATIVE_HLP_DEF(uint64_t const *, iemNativeHlpMemMapDataU64Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1618 RTGCPTR GCPtrMem, uint8_t iSegReg))
1619{
1620#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1621 return iemMemMapDataU64RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1622#else
1623 return iemMemMapDataU64RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1624#endif
1625}
1626
1627
1628/**
1629 * Used by TB code to map 80-bit float data writeonly w/ segmentation.
1630 */
1631IEM_DECL_NATIVE_HLP_DEF(RTFLOAT80U *, iemNativeHlpMemMapDataR80Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1632 RTGCPTR GCPtrMem, uint8_t iSegReg))
1633{
1634#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1635 return iemMemMapDataR80WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1636#else
1637 return iemMemMapDataR80WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1638#endif
1639}
1640
1641
1642/**
1643 * Used by TB code to map 80-bit BCD data writeonly w/ segmentation.
1644 */
1645IEM_DECL_NATIVE_HLP_DEF(RTPBCD80U *, iemNativeHlpMemMapDataD80Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1646 RTGCPTR GCPtrMem, uint8_t iSegReg))
1647{
1648#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1649 return iemMemMapDataD80WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1650#else
1651 return iemMemMapDataD80WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1652#endif
1653}
1654
1655
1656/**
1657 * Used by TB code to map unsigned 128-bit data for atomic read-write w/
1658 * segmentation.
1659 */
1660IEM_DECL_NATIVE_HLP_DEF(RTUINT128U *, iemNativeHlpMemMapDataU128Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1661 RTGCPTR GCPtrMem, uint8_t iSegReg))
1662{
1663#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1664 return iemMemMapDataU128AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1665#else
1666 return iemMemMapDataU128AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1667#endif
1668}
1669
1670
1671/**
1672 * Used by TB code to map unsigned 128-bit data read-write w/ segmentation.
1673 */
1674IEM_DECL_NATIVE_HLP_DEF(RTUINT128U *, iemNativeHlpMemMapDataU128Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1675 RTGCPTR GCPtrMem, uint8_t iSegReg))
1676{
1677#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1678 return iemMemMapDataU128RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1679#else
1680 return iemMemMapDataU128RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1681#endif
1682}
1683
1684
1685/**
1686 * Used by TB code to map unsigned 128-bit data writeonly w/ segmentation.
1687 */
1688IEM_DECL_NATIVE_HLP_DEF(RTUINT128U *, iemNativeHlpMemMapDataU128Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1689 RTGCPTR GCPtrMem, uint8_t iSegReg))
1690{
1691#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1692 return iemMemMapDataU128WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1693#else
1694 return iemMemMapDataU128WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1695#endif
1696}
1697
1698
1699/**
1700 * Used by TB code to map unsigned 128-bit data readonly w/ segmentation.
1701 */
1702IEM_DECL_NATIVE_HLP_DEF(RTUINT128U const *, iemNativeHlpMemMapDataU128Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo,
1703 RTGCPTR GCPtrMem, uint8_t iSegReg))
1704{
1705#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1706 return iemMemMapDataU128RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1707#else
1708 return iemMemMapDataU128RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
1709#endif
1710}
1711
1712
1713/*********************************************************************************************************************************
1714* Helpers: Flat memory mapping. *
1715*********************************************************************************************************************************/
1716
1717/**
1718 * Used by TB code to map unsigned 8-bit data for atomic read-write w/ flat
1719 * address.
1720 */
1721IEM_DECL_NATIVE_HLP_DEF(uint8_t *, iemNativeHlpMemFlatMapDataU8Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1722{
1723#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1724 return iemMemMapDataU8AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1725#else
1726 return iemMemFlatMapDataU8AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1727#endif
1728}
1729
1730
1731/**
1732 * Used by TB code to map unsigned 8-bit data read-write w/ flat address.
1733 */
1734IEM_DECL_NATIVE_HLP_DEF(uint8_t *, iemNativeHlpMemFlatMapDataU8Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1735{
1736#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1737 return iemMemMapDataU8RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1738#else
1739 return iemMemFlatMapDataU8RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1740#endif
1741}
1742
1743
1744/**
1745 * Used by TB code to map unsigned 8-bit data writeonly w/ flat address.
1746 */
1747IEM_DECL_NATIVE_HLP_DEF(uint8_t *, iemNativeHlpMemFlatMapDataU8Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1748{
1749#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1750 return iemMemMapDataU8WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1751#else
1752 return iemMemFlatMapDataU8WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1753#endif
1754}
1755
1756
1757/**
1758 * Used by TB code to map unsigned 8-bit data readonly w/ flat address.
1759 */
1760IEM_DECL_NATIVE_HLP_DEF(uint8_t const *, iemNativeHlpMemFlatMapDataU8Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1761{
1762#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1763 return iemMemMapDataU8RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1764#else
1765 return iemMemFlatMapDataU8RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1766#endif
1767}
1768
1769
1770/**
1771 * Used by TB code to map unsigned 16-bit data for atomic read-write w/ flat
1772 * address.
1773 */
1774IEM_DECL_NATIVE_HLP_DEF(uint16_t *, iemNativeHlpMemFlatMapDataU16Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1775{
1776#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1777 return iemMemMapDataU16AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1778#else
1779 return iemMemFlatMapDataU16AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1780#endif
1781}
1782
1783
1784/**
1785 * Used by TB code to map unsigned 16-bit data read-write w/ flat address.
1786 */
1787IEM_DECL_NATIVE_HLP_DEF(uint16_t *, iemNativeHlpMemFlatMapDataU16Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1788{
1789#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1790 return iemMemMapDataU16RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1791#else
1792 return iemMemFlatMapDataU16RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1793#endif
1794}
1795
1796
1797/**
1798 * Used by TB code to map unsigned 16-bit data writeonly w/ flat address.
1799 */
1800IEM_DECL_NATIVE_HLP_DEF(uint16_t *, iemNativeHlpMemFlatMapDataU16Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1801{
1802#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1803 return iemMemMapDataU16WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1804#else
1805 return iemMemFlatMapDataU16WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1806#endif
1807}
1808
1809
1810/**
1811 * Used by TB code to map unsigned 16-bit data readonly w/ flat address.
1812 */
1813IEM_DECL_NATIVE_HLP_DEF(uint16_t const *, iemNativeHlpMemFlatMapDataU16Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1814{
1815#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1816 return iemMemMapDataU16RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1817#else
1818 return iemMemFlatMapDataU16RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1819#endif
1820}
1821
1822
1823/**
1824 * Used by TB code to map unsigned 32-bit data for atomic read-write w/ flat
1825 * address.
1826 */
1827IEM_DECL_NATIVE_HLP_DEF(uint32_t *, iemNativeHlpMemFlatMapDataU32Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1828{
1829#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1830 return iemMemMapDataU32AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1831#else
1832 return iemMemFlatMapDataU32AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1833#endif
1834}
1835
1836
1837/**
1838 * Used by TB code to map unsigned 32-bit data read-write w/ flat address.
1839 */
1840IEM_DECL_NATIVE_HLP_DEF(uint32_t *, iemNativeHlpMemFlatMapDataU32Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1841{
1842#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1843 return iemMemMapDataU32RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1844#else
1845 return iemMemFlatMapDataU32RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1846#endif
1847}
1848
1849
1850/**
1851 * Used by TB code to map unsigned 32-bit data writeonly w/ flat address.
1852 */
1853IEM_DECL_NATIVE_HLP_DEF(uint32_t *, iemNativeHlpMemFlatMapDataU32Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1854{
1855#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1856 return iemMemMapDataU32WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1857#else
1858 return iemMemFlatMapDataU32WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1859#endif
1860}
1861
1862
1863/**
1864 * Used by TB code to map unsigned 32-bit data readonly w/ flat address.
1865 */
1866IEM_DECL_NATIVE_HLP_DEF(uint32_t const *, iemNativeHlpMemFlatMapDataU32Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1867{
1868#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1869 return iemMemMapDataU32RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1870#else
1871 return iemMemFlatMapDataU32RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1872#endif
1873}
1874
1875
1876/**
1877 * Used by TB code to map unsigned 64-bit data for atomic read-write w/ flat
1878 * address.
1879 */
1880IEM_DECL_NATIVE_HLP_DEF(uint64_t *, iemNativeHlpMemFlatMapDataU64Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1881{
1882#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1883 return iemMemMapDataU64AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1884#else
1885 return iemMemFlatMapDataU64AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1886#endif
1887}
1888
1889
1890/**
1891 * Used by TB code to map unsigned 64-bit data read-write w/ flat address.
1892 */
1893IEM_DECL_NATIVE_HLP_DEF(uint64_t *, iemNativeHlpMemFlatMapDataU64Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1894{
1895#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1896 return iemMemMapDataU64RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1897#else
1898 return iemMemFlatMapDataU64RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1899#endif
1900}
1901
1902
1903/**
1904 * Used by TB code to map unsigned 64-bit data writeonly w/ flat address.
1905 */
1906IEM_DECL_NATIVE_HLP_DEF(uint64_t *, iemNativeHlpMemFlatMapDataU64Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1907{
1908#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1909 return iemMemMapDataU64WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1910#else
1911 return iemMemFlatMapDataU64WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1912#endif
1913}
1914
1915
1916/**
1917 * Used by TB code to map unsigned 64-bit data readonly w/ flat address.
1918 */
1919IEM_DECL_NATIVE_HLP_DEF(uint64_t const *, iemNativeHlpMemFlatMapDataU64Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1920{
1921#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1922 return iemMemMapDataU64RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1923#else
1924 return iemMemFlatMapDataU64RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1925#endif
1926}
1927
1928
1929/**
1930 * Used by TB code to map 80-bit float data writeonly w/ flat address.
1931 */
1932IEM_DECL_NATIVE_HLP_DEF(RTFLOAT80U *, iemNativeHlpMemFlatMapDataR80Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1933{
1934#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1935 return iemMemMapDataR80WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1936#else
1937 return iemMemFlatMapDataR80WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1938#endif
1939}
1940
1941
1942/**
1943 * Used by TB code to map 80-bit BCD data writeonly w/ flat address.
1944 */
1945IEM_DECL_NATIVE_HLP_DEF(RTPBCD80U *, iemNativeHlpMemFlatMapDataD80Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1946{
1947#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1948 return iemMemMapDataD80WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1949#else
1950 return iemMemFlatMapDataD80WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1951#endif
1952}
1953
1954
1955/**
1956 * Used by TB code to map unsigned 128-bit data for atomic read-write w/ flat
1957 * address.
1958 */
1959IEM_DECL_NATIVE_HLP_DEF(RTUINT128U *, iemNativeHlpMemFlatMapDataU128Atomic,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1960{
1961#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1962 return iemMemMapDataU128AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1963#else
1964 return iemMemFlatMapDataU128AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1965#endif
1966}
1967
1968
1969/**
1970 * Used by TB code to map unsigned 128-bit data read-write w/ flat address.
1971 */
1972IEM_DECL_NATIVE_HLP_DEF(RTUINT128U *, iemNativeHlpMemFlatMapDataU128Rw,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1973{
1974#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1975 return iemMemMapDataU128RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1976#else
1977 return iemMemFlatMapDataU128RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1978#endif
1979}
1980
1981
1982/**
1983 * Used by TB code to map unsigned 128-bit data writeonly w/ flat address.
1984 */
1985IEM_DECL_NATIVE_HLP_DEF(RTUINT128U *, iemNativeHlpMemFlatMapDataU128Wo,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1986{
1987#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
1988 return iemMemMapDataU128WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
1989#else
1990 return iemMemFlatMapDataU128WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
1991#endif
1992}
1993
1994
1995/**
1996 * Used by TB code to map unsigned 128-bit data readonly w/ flat address.
1997 */
1998IEM_DECL_NATIVE_HLP_DEF(RTUINT128U const *, iemNativeHlpMemFlatMapDataU128Ro,(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, RTGCPTR GCPtrMem))
1999{
2000#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2001 return iemMemMapDataU128RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2002#else
2003 return iemMemFlatMapDataU128RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2004#endif
2005}
2006
2007
2008/*********************************************************************************************************************************
2009* Helpers: Commit, rollback & unmap *
2010*********************************************************************************************************************************/
2011
2012/**
2013 * Used by TB code to commit and unmap a read-write memory mapping.
2014 */
2015IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemCommitAndUnmapAtomic,(PVMCPUCC pVCpu, uint8_t bUnmapInfo))
2016{
2017 return iemMemCommitAndUnmapAtSafeJmp(pVCpu, bUnmapInfo);
2018}
2019
2020
2021/**
2022 * Used by TB code to commit and unmap a read-write memory mapping.
2023 */
2024IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemCommitAndUnmapRw,(PVMCPUCC pVCpu, uint8_t bUnmapInfo))
2025{
2026 return iemMemCommitAndUnmapRwSafeJmp(pVCpu, bUnmapInfo);
2027}
2028
2029
2030/**
2031 * Used by TB code to commit and unmap a write-only memory mapping.
2032 */
2033IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemCommitAndUnmapWo,(PVMCPUCC pVCpu, uint8_t bUnmapInfo))
2034{
2035 return iemMemCommitAndUnmapWoSafeJmp(pVCpu, bUnmapInfo);
2036}
2037
2038
2039/**
2040 * Used by TB code to commit and unmap a read-only memory mapping.
2041 */
2042IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemCommitAndUnmapRo,(PVMCPUCC pVCpu, uint8_t bUnmapInfo))
2043{
2044 return iemMemCommitAndUnmapRoSafeJmp(pVCpu, bUnmapInfo);
2045}
2046
2047
2048/**
2049 * Reinitializes the native recompiler state.
2050 *
2051 * Called before starting a new recompile job.
2052 */
2053static PIEMRECOMPILERSTATE iemNativeReInit(PIEMRECOMPILERSTATE pReNative, PCIEMTB pTb)
2054{
2055 pReNative->cLabels = 0;
2056 pReNative->bmLabelTypes = 0;
2057 pReNative->cFixups = 0;
2058#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
2059 pReNative->cTbExitFixups = 0;
2060#endif
2061#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2062 pReNative->pDbgInfo->cEntries = 0;
2063 pReNative->pDbgInfo->offNativeLast = UINT32_MAX;
2064#endif
2065 pReNative->pTbOrg = pTb;
2066 pReNative->cCondDepth = 0;
2067 pReNative->uCondSeqNo = 0;
2068 pReNative->uCheckIrqSeqNo = 0;
2069 pReNative->uTlbSeqNo = 0;
2070
2071#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
2072 pReNative->Core.offPc = 0;
2073# if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) || defined(VBOX_WITH_STATISTICS)
2074 pReNative->Core.idxInstrPlusOneOfLastPcUpdate = 0;
2075# endif
2076# ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
2077 pReNative->Core.fDebugPcInitialized = false;
2078# endif
2079#endif
2080#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2081 pReNative->fSimdRaiseXcptChecksEmitted = 0;
2082#endif
2083 pReNative->Core.bmHstRegs = IEMNATIVE_REG_FIXED_MASK
2084#if IEMNATIVE_HST_GREG_COUNT < 32
2085 | ~(RT_BIT(IEMNATIVE_HST_GREG_COUNT) - 1U)
2086#endif
2087 ;
2088 pReNative->Core.bmHstRegsWithGstShadow = 0;
2089 pReNative->Core.bmGstRegShadows = 0;
2090#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
2091 pReNative->Core.bmGstRegShadowDirty = 0;
2092#endif
2093 pReNative->Core.bmVars = 0;
2094 pReNative->Core.bmStack = 0;
2095 AssertCompile(sizeof(pReNative->Core.bmStack) * 8 == IEMNATIVE_FRAME_VAR_SLOTS); /* Must set reserved slots to 1 otherwise. */
2096 pReNative->Core.u64ArgVars = UINT64_MAX;
2097
2098 AssertCompile(RT_ELEMENTS(pReNative->aidxUniqueLabels) == 23);
2099 pReNative->aidxUniqueLabels[0] = UINT32_MAX;
2100 pReNative->aidxUniqueLabels[1] = UINT32_MAX;
2101 pReNative->aidxUniqueLabels[2] = UINT32_MAX;
2102 pReNative->aidxUniqueLabels[3] = UINT32_MAX;
2103 pReNative->aidxUniqueLabels[4] = UINT32_MAX;
2104 pReNative->aidxUniqueLabels[5] = UINT32_MAX;
2105 pReNative->aidxUniqueLabels[6] = UINT32_MAX;
2106 pReNative->aidxUniqueLabels[7] = UINT32_MAX;
2107 pReNative->aidxUniqueLabels[8] = UINT32_MAX;
2108 pReNative->aidxUniqueLabels[9] = UINT32_MAX;
2109 pReNative->aidxUniqueLabels[10] = UINT32_MAX;
2110 pReNative->aidxUniqueLabels[11] = UINT32_MAX;
2111 pReNative->aidxUniqueLabels[12] = UINT32_MAX;
2112 pReNative->aidxUniqueLabels[13] = UINT32_MAX;
2113 pReNative->aidxUniqueLabels[14] = UINT32_MAX;
2114 pReNative->aidxUniqueLabels[15] = UINT32_MAX;
2115 pReNative->aidxUniqueLabels[16] = UINT32_MAX;
2116 pReNative->aidxUniqueLabels[17] = UINT32_MAX;
2117 pReNative->aidxUniqueLabels[18] = UINT32_MAX;
2118 pReNative->aidxUniqueLabels[19] = UINT32_MAX;
2119 pReNative->aidxUniqueLabels[20] = UINT32_MAX;
2120 pReNative->aidxUniqueLabels[21] = UINT32_MAX;
2121 pReNative->aidxUniqueLabels[22] = UINT32_MAX;
2122
2123 pReNative->idxLastCheckIrqCallNo = UINT32_MAX;
2124
2125 /* Full host register reinit: */
2126 for (unsigned i = 0; i < RT_ELEMENTS(pReNative->Core.aHstRegs); i++)
2127 {
2128 pReNative->Core.aHstRegs[i].fGstRegShadows = 0;
2129 pReNative->Core.aHstRegs[i].enmWhat = kIemNativeWhat_Invalid;
2130 pReNative->Core.aHstRegs[i].idxVar = UINT8_MAX;
2131 }
2132
2133 uint32_t fRegs = IEMNATIVE_REG_FIXED_MASK
2134 & ~( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU)
2135#ifdef IEMNATIVE_REG_FIXED_PCPUMCTX
2136 | RT_BIT_32(IEMNATIVE_REG_FIXED_PCPUMCTX)
2137#endif
2138#ifdef IEMNATIVE_REG_FIXED_PCPUMCTX
2139 | RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0)
2140#endif
2141#ifdef IEMNATIVE_REG_FIXED_TMP1
2142 | RT_BIT_32(IEMNATIVE_REG_FIXED_TMP1)
2143#endif
2144#ifdef IEMNATIVE_REG_FIXED_PC_DBG
2145 | RT_BIT_32(IEMNATIVE_REG_FIXED_PC_DBG)
2146#endif
2147 );
2148 for (uint32_t idxReg = ASMBitFirstSetU32(fRegs) - 1; fRegs != 0; idxReg = ASMBitFirstSetU32(fRegs) - 1)
2149 {
2150 fRegs &= ~RT_BIT_32(idxReg);
2151 pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_PVMCPU].enmWhat = kIemNativeWhat_FixedReserved;
2152 }
2153
2154 pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_PVMCPU].enmWhat = kIemNativeWhat_pVCpuFixed;
2155#ifdef IEMNATIVE_REG_FIXED_PCPUMCTX
2156 pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_PCPUMCTX].enmWhat = kIemNativeWhat_pCtxFixed;
2157#endif
2158#ifdef IEMNATIVE_REG_FIXED_TMP0
2159 pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_TMP0].enmWhat = kIemNativeWhat_FixedTmp;
2160#endif
2161#ifdef IEMNATIVE_REG_FIXED_TMP1
2162 pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_TMP1].enmWhat = kIemNativeWhat_FixedTmp;
2163#endif
2164#ifdef IEMNATIVE_REG_FIXED_PC_DBG
2165 pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_PC_DBG].enmWhat = kIemNativeWhat_PcShadow;
2166#endif
2167
2168#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2169 pReNative->Core.bmHstSimdRegs = IEMNATIVE_SIMD_REG_FIXED_MASK
2170# if IEMNATIVE_HST_SIMD_REG_COUNT < 32
2171 | ~(RT_BIT(IEMNATIVE_HST_SIMD_REG_COUNT) - 1U)
2172# endif
2173 ;
2174 pReNative->Core.bmHstSimdRegsWithGstShadow = 0;
2175 pReNative->Core.bmGstSimdRegShadows = 0;
2176 pReNative->Core.bmGstSimdRegShadowDirtyLo128 = 0;
2177 pReNative->Core.bmGstSimdRegShadowDirtyHi128 = 0;
2178
2179 /* Full host register reinit: */
2180 for (unsigned i = 0; i < RT_ELEMENTS(pReNative->Core.aHstSimdRegs); i++)
2181 {
2182 pReNative->Core.aHstSimdRegs[i].fGstRegShadows = 0;
2183 pReNative->Core.aHstSimdRegs[i].enmWhat = kIemNativeWhat_Invalid;
2184 pReNative->Core.aHstSimdRegs[i].idxVar = UINT8_MAX;
2185 pReNative->Core.aHstSimdRegs[i].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
2186 }
2187
2188 fRegs = IEMNATIVE_SIMD_REG_FIXED_MASK;
2189 for (uint32_t idxReg = ASMBitFirstSetU32(fRegs) - 1; fRegs != 0; idxReg = ASMBitFirstSetU32(fRegs) - 1)
2190 {
2191 fRegs &= ~RT_BIT_32(idxReg);
2192 pReNative->Core.aHstSimdRegs[idxReg].enmWhat = kIemNativeWhat_FixedReserved;
2193 }
2194
2195#ifdef IEMNATIVE_SIMD_REG_FIXED_TMP0
2196 pReNative->Core.aHstSimdRegs[IEMNATIVE_SIMD_REG_FIXED_TMP0].enmWhat = kIemNativeWhat_FixedTmp;
2197#endif
2198
2199#endif
2200
2201 return pReNative;
2202}
2203
2204
2205/**
2206 * Used when done emitting the per-chunk code and for iemNativeInit bailout.
2207 */
2208static void iemNativeTerm(PIEMRECOMPILERSTATE pReNative)
2209{
2210 RTMemFree(pReNative->pInstrBuf);
2211 RTMemFree(pReNative->paLabels);
2212 RTMemFree(pReNative->paFixups);
2213#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
2214 RTMemFree(pReNative->paTbExitFixups);
2215#endif
2216#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2217 RTMemFree(pReNative->pDbgInfo);
2218#endif
2219 RTMemFree(pReNative);
2220}
2221
2222
2223/**
2224 * Allocates and initializes the native recompiler state.
2225 *
2226 * This is called the first time an EMT wants to recompile something.
2227 *
2228 * @returns Pointer to the new recompiler state.
2229 * @param pVCpu The cross context virtual CPU structure of the calling
2230 * thread.
2231 * @param pTb The TB that's about to be recompiled. When this is NULL,
2232 * the recompiler state is for emitting the common per-chunk
2233 * code from iemNativeRecompileAttachExecMemChunkCtx.
2234 * @thread EMT(pVCpu)
2235 */
2236static PIEMRECOMPILERSTATE iemNativeInit(PVMCPUCC pVCpu, PCIEMTB pTb)
2237{
2238 VMCPU_ASSERT_EMT(pVCpu);
2239
2240 PIEMRECOMPILERSTATE pReNative = (PIEMRECOMPILERSTATE)RTMemAllocZ(sizeof(*pReNative));
2241 AssertReturn(pReNative, NULL);
2242
2243 /*
2244 * Try allocate all the buffers and stuff we need.
2245 */
2246 uint32_t const cFactor = pTb ? 1 : 32 /* per-chunk stuff doesn't really need anything but the code buffer */;
2247 pReNative->pInstrBuf = (PIEMNATIVEINSTR)RTMemAllocZ(_64K);
2248 pReNative->paLabels = (PIEMNATIVELABEL)RTMemAllocZ(sizeof(IEMNATIVELABEL) * _8K / cFactor);
2249 pReNative->paFixups = (PIEMNATIVEFIXUP)RTMemAllocZ(sizeof(IEMNATIVEFIXUP) * _16K / cFactor);
2250#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
2251 pReNative->paTbExitFixups = (PIEMNATIVEEXITFIXUP)RTMemAllocZ(sizeof(IEMNATIVEEXITFIXUP) * _8K / cFactor);
2252#endif
2253#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2254 pReNative->pDbgInfo = (PIEMTBDBG)RTMemAllocZ(RT_UOFFSETOF_DYN(IEMTBDBG, aEntries[_16K / cFactor]));
2255#endif
2256 if (RT_LIKELY( pReNative->pInstrBuf
2257 && pReNative->paLabels
2258 && pReNative->paFixups)
2259#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
2260 && pReNative->paTbExitFixups
2261#endif
2262#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2263 && pReNative->pDbgInfo
2264#endif
2265 )
2266 {
2267 /*
2268 * Set the buffer & array sizes on success.
2269 */
2270 pReNative->cInstrBufAlloc = _64K / sizeof(IEMNATIVEINSTR);
2271 pReNative->cLabelsAlloc = _8K / cFactor;
2272 pReNative->cFixupsAlloc = _16K / cFactor;
2273#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
2274 pReNative->cTbExitFixupsAlloc = _8K / cFactor;
2275#endif
2276#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2277 pReNative->cDbgInfoAlloc = _16K / cFactor;
2278#endif
2279
2280 /* Other constant stuff: */
2281 pReNative->pVCpu = pVCpu;
2282
2283 /*
2284 * Done, just reinit it.
2285 */
2286 return iemNativeReInit(pReNative, pTb);
2287 }
2288
2289 /*
2290 * Failed. Cleanup and return.
2291 */
2292 AssertFailed();
2293 iemNativeTerm(pReNative);
2294 return NULL;
2295}
2296
2297
2298/**
2299 * Creates a label
2300 *
2301 * If the label does not yet have a defined position,
2302 * call iemNativeLabelDefine() later to set it.
2303 *
2304 * @returns Label ID. Throws VBox status code on failure, so no need to check
2305 * the return value.
2306 * @param pReNative The native recompile state.
2307 * @param enmType The label type.
2308 * @param offWhere The instruction offset of the label. UINT32_MAX if the
2309 * label is not yet defined (default).
2310 * @param uData Data associated with the lable. Only applicable to
2311 * certain type of labels. Default is zero.
2312 */
2313DECL_HIDDEN_THROW(uint32_t)
2314iemNativeLabelCreate(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
2315 uint32_t offWhere /*= UINT32_MAX*/, uint16_t uData /*= 0*/)
2316{
2317 Assert(uData == 0 || enmType >= kIemNativeLabelType_FirstWithMultipleInstances);
2318#if defined(IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE) && defined(RT_ARCH_AMD64)
2319 Assert(enmType >= kIemNativeLabelType_LoopJumpTarget);
2320#endif
2321
2322 /*
2323 * Locate existing label definition.
2324 *
2325 * This is only allowed for forward declarations where offWhere=UINT32_MAX
2326 * and uData is zero.
2327 */
2328 PIEMNATIVELABEL paLabels = pReNative->paLabels;
2329 uint32_t const cLabels = pReNative->cLabels;
2330 if ( pReNative->bmLabelTypes & RT_BIT_64(enmType)
2331#ifndef VBOX_STRICT
2332 && enmType < kIemNativeLabelType_FirstWithMultipleInstances
2333 && offWhere == UINT32_MAX
2334 && uData == 0
2335#endif
2336 )
2337 {
2338#ifndef VBOX_STRICT
2339 AssertStmt(enmType > kIemNativeLabelType_Invalid && enmType < kIemNativeLabelType_FirstWithMultipleInstances,
2340 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
2341 uint32_t const idxLabel = pReNative->aidxUniqueLabels[enmType];
2342 if (idxLabel < pReNative->cLabels)
2343 return idxLabel;
2344#else
2345 for (uint32_t i = 0; i < cLabels; i++)
2346 if ( paLabels[i].enmType == enmType
2347 && paLabels[i].uData == uData)
2348 {
2349 AssertStmt(uData == 0, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
2350 AssertStmt(offWhere == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
2351 AssertStmt(paLabels[i].off == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_2));
2352 AssertStmt(enmType < kIemNativeLabelType_FirstWithMultipleInstances && pReNative->aidxUniqueLabels[enmType] == i,
2353 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
2354 return i;
2355 }
2356 AssertStmt( enmType >= kIemNativeLabelType_FirstWithMultipleInstances
2357 || pReNative->aidxUniqueLabels[enmType] == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
2358#endif
2359 }
2360
2361 /*
2362 * Make sure we've got room for another label.
2363 */
2364 if (RT_LIKELY(cLabels < pReNative->cLabelsAlloc))
2365 { /* likely */ }
2366 else
2367 {
2368 uint32_t cNew = pReNative->cLabelsAlloc;
2369 AssertStmt(cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_3));
2370 AssertStmt(cLabels == cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_3));
2371 cNew *= 2;
2372 AssertStmt(cNew <= _64K, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_TOO_MANY)); /* IEMNATIVEFIXUP::idxLabel type restrict this */
2373 paLabels = (PIEMNATIVELABEL)RTMemRealloc(paLabels, cNew * sizeof(paLabels[0]));
2374 AssertStmt(paLabels, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_OUT_OF_MEMORY));
2375 pReNative->paLabels = paLabels;
2376 pReNative->cLabelsAlloc = cNew;
2377 }
2378
2379 /*
2380 * Define a new label.
2381 */
2382 paLabels[cLabels].off = offWhere;
2383 paLabels[cLabels].enmType = enmType;
2384 paLabels[cLabels].uData = uData;
2385 pReNative->cLabels = cLabels + 1;
2386
2387 Assert((unsigned)enmType < 64);
2388 pReNative->bmLabelTypes |= RT_BIT_64(enmType);
2389
2390 if (enmType < kIemNativeLabelType_FirstWithMultipleInstances)
2391 {
2392 Assert(uData == 0);
2393 pReNative->aidxUniqueLabels[enmType] = cLabels;
2394 }
2395
2396 if (offWhere != UINT32_MAX)
2397 {
2398#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2399 iemNativeDbgInfoAddNativeOffset(pReNative, offWhere);
2400 iemNativeDbgInfoAddLabel(pReNative, enmType, uData);
2401#endif
2402 }
2403 return cLabels;
2404}
2405
2406
2407/**
2408 * Defines the location of an existing label.
2409 *
2410 * @param pReNative The native recompile state.
2411 * @param idxLabel The label to define.
2412 * @param offWhere The position.
2413 */
2414DECL_HIDDEN_THROW(void) iemNativeLabelDefine(PIEMRECOMPILERSTATE pReNative, uint32_t idxLabel, uint32_t offWhere)
2415{
2416 AssertStmt(idxLabel < pReNative->cLabels, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_4));
2417 PIEMNATIVELABEL const pLabel = &pReNative->paLabels[idxLabel];
2418 AssertStmt(pLabel->off == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_5));
2419 pLabel->off = offWhere;
2420#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2421 iemNativeDbgInfoAddNativeOffset(pReNative, offWhere);
2422 iemNativeDbgInfoAddLabel(pReNative, (IEMNATIVELABELTYPE)pLabel->enmType, pLabel->uData);
2423#endif
2424}
2425
2426
2427/**
2428 * Looks up a lable.
2429 *
2430 * @returns Label ID if found, UINT32_MAX if not.
2431 */
2432DECLHIDDEN(uint32_t) iemNativeLabelFind(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
2433 uint32_t offWhere /*= UINT32_MAX*/, uint16_t uData /*= 0*/) RT_NOEXCEPT
2434{
2435 Assert((unsigned)enmType < 64);
2436 if (RT_BIT_64(enmType) & pReNative->bmLabelTypes)
2437 {
2438 if (enmType < kIemNativeLabelType_FirstWithMultipleInstances)
2439 return pReNative->aidxUniqueLabels[enmType];
2440
2441 PIEMNATIVELABEL paLabels = pReNative->paLabels;
2442 uint32_t const cLabels = pReNative->cLabels;
2443 for (uint32_t i = 0; i < cLabels; i++)
2444 if ( paLabels[i].enmType == enmType
2445 && paLabels[i].uData == uData
2446 && ( paLabels[i].off == offWhere
2447 || offWhere == UINT32_MAX
2448 || paLabels[i].off == UINT32_MAX))
2449 return i;
2450 }
2451 return UINT32_MAX;
2452}
2453
2454
2455/**
2456 * Adds a fixup.
2457 *
2458 * @throws VBox status code (int) on failure.
2459 * @param pReNative The native recompile state.
2460 * @param offWhere The instruction offset of the fixup location.
2461 * @param idxLabel The target label ID for the fixup.
2462 * @param enmType The fixup type.
2463 * @param offAddend Fixup addend if applicable to the type. Default is 0.
2464 */
2465DECL_HIDDEN_THROW(void)
2466iemNativeAddFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, uint32_t idxLabel,
2467 IEMNATIVEFIXUPTYPE enmType, int8_t offAddend /*= 0*/)
2468{
2469 Assert(idxLabel <= UINT16_MAX);
2470 Assert((unsigned)enmType <= UINT8_MAX);
2471#ifdef RT_ARCH_ARM64
2472 AssertStmt( enmType != kIemNativeFixupType_RelImm14At5
2473 || pReNative->paLabels[idxLabel].enmType >= kIemNativeLabelType_LastWholeTbBranch,
2474 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_SHORT_JMP_TO_TAIL_LABEL));
2475#endif
2476
2477 /*
2478 * Make sure we've room.
2479 */
2480 PIEMNATIVEFIXUP paFixups = pReNative->paFixups;
2481 uint32_t const cFixups = pReNative->cFixups;
2482 if (RT_LIKELY(cFixups < pReNative->cFixupsAlloc))
2483 { /* likely */ }
2484 else
2485 {
2486 uint32_t cNew = pReNative->cFixupsAlloc;
2487 AssertStmt(cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_IPE_1));
2488 AssertStmt(cFixups == cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_IPE_1));
2489 cNew *= 2;
2490 AssertStmt(cNew <= _128K, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_TOO_MANY));
2491 paFixups = (PIEMNATIVEFIXUP)RTMemRealloc(paFixups, cNew * sizeof(paFixups[0]));
2492 AssertStmt(paFixups, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_OUT_OF_MEMORY));
2493 pReNative->paFixups = paFixups;
2494 pReNative->cFixupsAlloc = cNew;
2495 }
2496
2497 /*
2498 * Add the fixup.
2499 */
2500 paFixups[cFixups].off = offWhere;
2501 paFixups[cFixups].idxLabel = (uint16_t)idxLabel;
2502 paFixups[cFixups].enmType = enmType;
2503 paFixups[cFixups].offAddend = offAddend;
2504 pReNative->cFixups = cFixups + 1;
2505}
2506
2507
2508#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
2509/**
2510 * Adds a fixup to the per chunk tail code.
2511 *
2512 * @throws VBox status code (int) on failure.
2513 * @param pReNative The native recompile state.
2514 * @param offWhere The instruction offset of the fixup location.
2515 * @param enmExitReason The exit reason to jump to.
2516 */
2517DECL_HIDDEN_THROW(void)
2518iemNativeAddTbExitFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, IEMNATIVELABELTYPE enmExitReason)
2519{
2520 Assert(IEMNATIVELABELTYPE_IS_EXIT_REASON(enmExitReason));
2521
2522 /*
2523 * Make sure we've room.
2524 */
2525 PIEMNATIVEEXITFIXUP paTbExitFixups = pReNative->paTbExitFixups;
2526 uint32_t const cTbExitFixups = pReNative->cTbExitFixups;
2527 if (RT_LIKELY(cTbExitFixups < pReNative->cTbExitFixupsAlloc))
2528 { /* likely */ }
2529 else
2530 {
2531 uint32_t cNew = pReNative->cTbExitFixupsAlloc;
2532 AssertStmt(cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_IPE_1));
2533 AssertStmt(cTbExitFixups == cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_IPE_1));
2534 cNew *= 2;
2535 AssertStmt(cNew <= _128K, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_TOO_MANY));
2536 paTbExitFixups = (PIEMNATIVEEXITFIXUP)RTMemRealloc(paTbExitFixups, cNew * sizeof(paTbExitFixups[0]));
2537 AssertStmt(paTbExitFixups, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_OUT_OF_MEMORY));
2538 pReNative->paTbExitFixups = paTbExitFixups;
2539 pReNative->cTbExitFixupsAlloc = cNew;
2540 }
2541
2542 /*
2543 * Add the fixup.
2544 */
2545 paTbExitFixups[cTbExitFixups].off = offWhere;
2546 paTbExitFixups[cTbExitFixups].enmExitReason = enmExitReason;
2547 pReNative->cTbExitFixups = cTbExitFixups + 1;
2548}
2549#endif
2550
2551
2552/**
2553 * Slow code path for iemNativeInstrBufEnsure.
2554 */
2555DECL_HIDDEN_THROW(PIEMNATIVEINSTR) iemNativeInstrBufEnsureSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq)
2556{
2557 /* Double the buffer size till we meet the request. */
2558 uint32_t cNew = pReNative->cInstrBufAlloc;
2559 AssertStmt(cNew > 0, IEMNATIVE_DO_LONGJMP(pReNative, VERR_INTERNAL_ERROR_5)); /* impossible */
2560 do
2561 cNew *= 2;
2562 while (cNew < off + cInstrReq);
2563
2564 uint32_t const cbNew = cNew * sizeof(IEMNATIVEINSTR);
2565#ifdef RT_ARCH_ARM64
2566 uint32_t const cbMaxInstrBuf = _1M; /* Limited by the branch instruction range (18+2 bits). */
2567#else
2568 uint32_t const cbMaxInstrBuf = _2M;
2569#endif
2570 AssertStmt(cbNew <= cbMaxInstrBuf, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_INSTR_BUF_TOO_LARGE));
2571
2572 void *pvNew = RTMemRealloc(pReNative->pInstrBuf, cbNew);
2573 AssertStmt(pvNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_INSTR_BUF_OUT_OF_MEMORY));
2574
2575#ifdef VBOX_STRICT
2576 pReNative->offInstrBufChecked = off + cInstrReq;
2577#endif
2578 pReNative->cInstrBufAlloc = cNew;
2579 return pReNative->pInstrBuf = (PIEMNATIVEINSTR)pvNew;
2580}
2581
2582#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2583
2584/**
2585 * Grows the static debug info array used during recompilation.
2586 *
2587 * @returns Pointer to the new debug info block; throws VBox status code on
2588 * failure, so no need to check the return value.
2589 */
2590DECL_NO_INLINE(static, PIEMTBDBG) iemNativeDbgInfoGrow(PIEMRECOMPILERSTATE pReNative, PIEMTBDBG pDbgInfo)
2591{
2592 uint32_t cNew = pReNative->cDbgInfoAlloc * 2;
2593 AssertStmt(cNew < _1M && cNew != 0, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_DBGINFO_IPE_1));
2594 pDbgInfo = (PIEMTBDBG)RTMemRealloc(pDbgInfo, RT_UOFFSETOF_DYN(IEMTBDBG, aEntries[cNew]));
2595 AssertStmt(pDbgInfo, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_DBGINFO_OUT_OF_MEMORY));
2596 pReNative->pDbgInfo = pDbgInfo;
2597 pReNative->cDbgInfoAlloc = cNew;
2598 return pDbgInfo;
2599}
2600
2601
2602/**
2603 * Adds a new debug info uninitialized entry, returning the pointer to it.
2604 */
2605DECL_INLINE_THROW(PIEMTBDBGENTRY) iemNativeDbgInfoAddNewEntry(PIEMRECOMPILERSTATE pReNative, PIEMTBDBG pDbgInfo)
2606{
2607 if (RT_LIKELY(pDbgInfo->cEntries < pReNative->cDbgInfoAlloc))
2608 { /* likely */ }
2609 else
2610 pDbgInfo = iemNativeDbgInfoGrow(pReNative, pDbgInfo);
2611 return &pDbgInfo->aEntries[pDbgInfo->cEntries++];
2612}
2613
2614
2615/**
2616 * Debug Info: Adds a native offset record, if necessary.
2617 */
2618DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddNativeOffset(PIEMRECOMPILERSTATE pReNative, uint32_t off)
2619{
2620 PIEMTBDBG pDbgInfo = pReNative->pDbgInfo;
2621
2622 /*
2623 * Do we need this one?
2624 */
2625 uint32_t const offPrev = pDbgInfo->offNativeLast;
2626 if (offPrev == off)
2627 return;
2628 AssertStmt(offPrev < off || offPrev == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_DBGINFO_IPE_2));
2629
2630 /*
2631 * Add it.
2632 */
2633 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pDbgInfo);
2634 pEntry->NativeOffset.uType = kIemTbDbgEntryType_NativeOffset;
2635 pEntry->NativeOffset.offNative = off;
2636 pDbgInfo->offNativeLast = off;
2637}
2638
2639
2640/**
2641 * Debug Info: Record info about a label.
2642 */
2643static void iemNativeDbgInfoAddLabel(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType, uint16_t uData)
2644{
2645 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2646 pEntry->Label.uType = kIemTbDbgEntryType_Label;
2647 pEntry->Label.uUnused = 0;
2648 pEntry->Label.enmLabel = (uint8_t)enmType;
2649 pEntry->Label.uData = uData;
2650}
2651
2652
2653/**
2654 * Debug Info: Record info about a threaded call.
2655 */
2656static void iemNativeDbgInfoAddThreadedCall(PIEMRECOMPILERSTATE pReNative, IEMTHREADEDFUNCS enmCall, bool fRecompiled)
2657{
2658 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2659 pEntry->ThreadedCall.uType = kIemTbDbgEntryType_ThreadedCall;
2660 pEntry->ThreadedCall.fRecompiled = fRecompiled;
2661 pEntry->ThreadedCall.uUnused = 0;
2662 pEntry->ThreadedCall.enmCall = (uint16_t)enmCall;
2663}
2664
2665
2666/**
2667 * Debug Info: Record info about a new guest instruction.
2668 */
2669static void iemNativeDbgInfoAddGuestInstruction(PIEMRECOMPILERSTATE pReNative, uint32_t fExec)
2670{
2671 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2672 pEntry->GuestInstruction.uType = kIemTbDbgEntryType_GuestInstruction;
2673 pEntry->GuestInstruction.uUnused = 0;
2674 pEntry->GuestInstruction.fExec = fExec;
2675}
2676
2677
2678/**
2679 * Debug Info: Record info about guest register shadowing.
2680 */
2681DECL_HIDDEN_THROW(void)
2682iemNativeDbgInfoAddGuestRegShadowing(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTREG enmGstReg,
2683 uint8_t idxHstReg /*= UINT8_MAX*/, uint8_t idxHstRegPrev /*= UINT8_MAX*/)
2684{
2685 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2686 pEntry->GuestRegShadowing.uType = kIemTbDbgEntryType_GuestRegShadowing;
2687 pEntry->GuestRegShadowing.uUnused = 0;
2688 pEntry->GuestRegShadowing.idxGstReg = enmGstReg;
2689 pEntry->GuestRegShadowing.idxHstReg = idxHstReg;
2690 pEntry->GuestRegShadowing.idxHstRegPrev = idxHstRegPrev;
2691#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
2692 Assert( idxHstReg != UINT8_MAX
2693 || !(pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(enmGstReg)));
2694#endif
2695}
2696
2697
2698# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2699/**
2700 * Debug Info: Record info about guest register shadowing.
2701 */
2702DECL_HIDDEN_THROW(void)
2703iemNativeDbgInfoAddGuestSimdRegShadowing(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTSIMDREG enmGstSimdReg,
2704 uint8_t idxHstSimdReg /*= UINT8_MAX*/, uint8_t idxHstSimdRegPrev /*= UINT8_MAX*/)
2705{
2706 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2707 pEntry->GuestSimdRegShadowing.uType = kIemTbDbgEntryType_GuestSimdRegShadowing;
2708 pEntry->GuestSimdRegShadowing.uUnused = 0;
2709 pEntry->GuestSimdRegShadowing.idxGstSimdReg = enmGstSimdReg;
2710 pEntry->GuestSimdRegShadowing.idxHstSimdReg = idxHstSimdReg;
2711 pEntry->GuestSimdRegShadowing.idxHstSimdRegPrev = idxHstSimdRegPrev;
2712}
2713# endif
2714
2715
2716# ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
2717/**
2718 * Debug Info: Record info about delayed RIP updates.
2719 */
2720DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddDelayedPcUpdate(PIEMRECOMPILERSTATE pReNative, uint64_t offPc, uint32_t cInstrSkipped)
2721{
2722 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2723 pEntry->DelayedPcUpdate.uType = kIemTbDbgEntryType_DelayedPcUpdate;
2724 pEntry->DelayedPcUpdate.offPc = offPc; /** @todo support larger values */
2725 pEntry->DelayedPcUpdate.cInstrSkipped = cInstrSkipped;
2726}
2727# endif
2728
2729# if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) || defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
2730
2731/**
2732 * Debug Info: Record info about a dirty guest register.
2733 */
2734DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddGuestRegDirty(PIEMRECOMPILERSTATE pReNative, bool fSimdReg,
2735 uint8_t idxGstReg, uint8_t idxHstReg)
2736{
2737 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2738 pEntry->GuestRegDirty.uType = kIemTbDbgEntryType_GuestRegDirty;
2739 pEntry->GuestRegDirty.fSimdReg = fSimdReg ? 1 : 0;
2740 pEntry->GuestRegDirty.idxGstReg = idxGstReg;
2741 pEntry->GuestRegDirty.idxHstReg = idxHstReg;
2742}
2743
2744
2745/**
2746 * Debug Info: Record info about a dirty guest register writeback operation.
2747 */
2748DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddGuestRegWriteback(PIEMRECOMPILERSTATE pReNative, bool fSimdReg, uint64_t fGstReg)
2749{
2750 unsigned const cBitsGstRegMask = 25;
2751 uint32_t const fGstRegMask = RT_BIT_32(cBitsGstRegMask) - 1U;
2752
2753 /* The first block of 25 bits: */
2754 if (fGstReg & fGstRegMask)
2755 {
2756 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2757 pEntry->GuestRegWriteback.uType = kIemTbDbgEntryType_GuestRegWriteback;
2758 pEntry->GuestRegWriteback.fSimdReg = fSimdReg ? 1 : 0;
2759 pEntry->GuestRegWriteback.cShift = 0;
2760 pEntry->GuestRegWriteback.fGstReg = (uint32_t)(fGstReg & fGstRegMask);
2761 fGstReg &= ~(uint64_t)fGstRegMask;
2762 if (!fGstReg)
2763 return;
2764 }
2765
2766 /* The second block of 25 bits: */
2767 fGstReg >>= cBitsGstRegMask;
2768 if (fGstReg & fGstRegMask)
2769 {
2770 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2771 pEntry->GuestRegWriteback.uType = kIemTbDbgEntryType_GuestRegWriteback;
2772 pEntry->GuestRegWriteback.fSimdReg = fSimdReg ? 1 : 0;
2773 pEntry->GuestRegWriteback.cShift = 0;
2774 pEntry->GuestRegWriteback.fGstReg = (uint32_t)(fGstReg & fGstRegMask);
2775 fGstReg &= ~(uint64_t)fGstRegMask;
2776 if (!fGstReg)
2777 return;
2778 }
2779
2780 /* The last block with 14 bits: */
2781 fGstReg >>= cBitsGstRegMask;
2782 Assert(fGstReg & fGstRegMask);
2783 Assert((fGstReg & ~(uint64_t)fGstRegMask) == 0);
2784 PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
2785 pEntry->GuestRegWriteback.uType = kIemTbDbgEntryType_GuestRegWriteback;
2786 pEntry->GuestRegWriteback.fSimdReg = fSimdReg ? 1 : 0;
2787 pEntry->GuestRegWriteback.cShift = 2;
2788 pEntry->GuestRegWriteback.fGstReg = (uint32_t)(fGstReg & fGstRegMask);
2789}
2790
2791# endif /* defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) || defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR) */
2792
2793#endif /* IEMNATIVE_WITH_TB_DEBUG_INFO */
2794
2795
2796/*********************************************************************************************************************************
2797* Register Allocator *
2798*********************************************************************************************************************************/
2799
2800/**
2801 * Register parameter indexes (indexed by argument number).
2802 */
2803DECL_HIDDEN_CONST(uint8_t) const g_aidxIemNativeCallRegs[] =
2804{
2805 IEMNATIVE_CALL_ARG0_GREG,
2806 IEMNATIVE_CALL_ARG1_GREG,
2807 IEMNATIVE_CALL_ARG2_GREG,
2808 IEMNATIVE_CALL_ARG3_GREG,
2809#if defined(IEMNATIVE_CALL_ARG4_GREG)
2810 IEMNATIVE_CALL_ARG4_GREG,
2811# if defined(IEMNATIVE_CALL_ARG5_GREG)
2812 IEMNATIVE_CALL_ARG5_GREG,
2813# if defined(IEMNATIVE_CALL_ARG6_GREG)
2814 IEMNATIVE_CALL_ARG6_GREG,
2815# if defined(IEMNATIVE_CALL_ARG7_GREG)
2816 IEMNATIVE_CALL_ARG7_GREG,
2817# endif
2818# endif
2819# endif
2820#endif
2821};
2822AssertCompile(RT_ELEMENTS(g_aidxIemNativeCallRegs) == IEMNATIVE_CALL_ARG_GREG_COUNT);
2823
2824/**
2825 * Call register masks indexed by argument count.
2826 */
2827DECL_HIDDEN_CONST(uint32_t) const g_afIemNativeCallRegs[] =
2828{
2829 0,
2830 RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG),
2831 RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG),
2832 RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG),
2833 RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
2834 | RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG),
2835#if defined(IEMNATIVE_CALL_ARG4_GREG)
2836 RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
2837 | RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG),
2838# if defined(IEMNATIVE_CALL_ARG5_GREG)
2839 RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
2840 | RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG),
2841# if defined(IEMNATIVE_CALL_ARG6_GREG)
2842 RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
2843 | RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG)
2844 | RT_BIT_32(IEMNATIVE_CALL_ARG6_GREG),
2845# if defined(IEMNATIVE_CALL_ARG7_GREG)
2846 RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
2847 | RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG)
2848 | RT_BIT_32(IEMNATIVE_CALL_ARG6_GREG) | RT_BIT_32(IEMNATIVE_CALL_ARG7_GREG),
2849# endif
2850# endif
2851# endif
2852#endif
2853};
2854
2855#ifdef IEMNATIVE_FP_OFF_STACK_ARG0
2856/**
2857 * BP offset of the stack argument slots.
2858 *
2859 * This array is indexed by \#argument - IEMNATIVE_CALL_ARG_GREG_COUNT and has
2860 * IEMNATIVE_FRAME_STACK_ARG_COUNT entries.
2861 */
2862DECL_HIDDEN_CONST(int32_t) const g_aoffIemNativeCallStackArgBpDisp[] =
2863{
2864 IEMNATIVE_FP_OFF_STACK_ARG0,
2865# ifdef IEMNATIVE_FP_OFF_STACK_ARG1
2866 IEMNATIVE_FP_OFF_STACK_ARG1,
2867# endif
2868# ifdef IEMNATIVE_FP_OFF_STACK_ARG2
2869 IEMNATIVE_FP_OFF_STACK_ARG2,
2870# endif
2871# ifdef IEMNATIVE_FP_OFF_STACK_ARG3
2872 IEMNATIVE_FP_OFF_STACK_ARG3,
2873# endif
2874};
2875AssertCompile(RT_ELEMENTS(g_aoffIemNativeCallStackArgBpDisp) == IEMNATIVE_FRAME_STACK_ARG_COUNT);
2876#endif /* IEMNATIVE_FP_OFF_STACK_ARG0 */
2877
2878/**
2879 * Info about shadowed guest register values.
2880 * @see IEMNATIVEGSTREG
2881 */
2882DECL_HIDDEN_CONST(IEMANTIVEGSTREGINFO const) g_aGstShadowInfo[] =
2883{
2884#define CPUMCTX_OFF_AND_SIZE(a_Reg) (uint32_t)RT_UOFFSETOF(VMCPU, cpum.GstCtx. a_Reg), RT_SIZEOFMEMB(VMCPU, cpum.GstCtx. a_Reg)
2885 /* [kIemNativeGstReg_GprFirst + X86_GREG_xAX] = */ { CPUMCTX_OFF_AND_SIZE(rax), "rax", },
2886 /* [kIemNativeGstReg_GprFirst + X86_GREG_xCX] = */ { CPUMCTX_OFF_AND_SIZE(rcx), "rcx", },
2887 /* [kIemNativeGstReg_GprFirst + X86_GREG_xDX] = */ { CPUMCTX_OFF_AND_SIZE(rdx), "rdx", },
2888 /* [kIemNativeGstReg_GprFirst + X86_GREG_xBX] = */ { CPUMCTX_OFF_AND_SIZE(rbx), "rbx", },
2889 /* [kIemNativeGstReg_GprFirst + X86_GREG_xSP] = */ { CPUMCTX_OFF_AND_SIZE(rsp), "rsp", },
2890 /* [kIemNativeGstReg_GprFirst + X86_GREG_xBP] = */ { CPUMCTX_OFF_AND_SIZE(rbp), "rbp", },
2891 /* [kIemNativeGstReg_GprFirst + X86_GREG_xSI] = */ { CPUMCTX_OFF_AND_SIZE(rsi), "rsi", },
2892 /* [kIemNativeGstReg_GprFirst + X86_GREG_xDI] = */ { CPUMCTX_OFF_AND_SIZE(rdi), "rdi", },
2893 /* [kIemNativeGstReg_GprFirst + X86_GREG_x8 ] = */ { CPUMCTX_OFF_AND_SIZE(r8), "r8", },
2894 /* [kIemNativeGstReg_GprFirst + X86_GREG_x9 ] = */ { CPUMCTX_OFF_AND_SIZE(r9), "r9", },
2895 /* [kIemNativeGstReg_GprFirst + X86_GREG_x10] = */ { CPUMCTX_OFF_AND_SIZE(r10), "r10", },
2896 /* [kIemNativeGstReg_GprFirst + X86_GREG_x11] = */ { CPUMCTX_OFF_AND_SIZE(r11), "r11", },
2897 /* [kIemNativeGstReg_GprFirst + X86_GREG_x12] = */ { CPUMCTX_OFF_AND_SIZE(r12), "r12", },
2898 /* [kIemNativeGstReg_GprFirst + X86_GREG_x13] = */ { CPUMCTX_OFF_AND_SIZE(r13), "r13", },
2899 /* [kIemNativeGstReg_GprFirst + X86_GREG_x14] = */ { CPUMCTX_OFF_AND_SIZE(r14), "r14", },
2900 /* [kIemNativeGstReg_GprFirst + X86_GREG_x15] = */ { CPUMCTX_OFF_AND_SIZE(r15), "r15", },
2901 /* [kIemNativeGstReg_Pc] = */ { CPUMCTX_OFF_AND_SIZE(rip), "rip", },
2902 /* [kIemNativeGstReg_Cr0] = */ { CPUMCTX_OFF_AND_SIZE(cr0), "cr0", },
2903 /* [kIemNativeGstReg_FpuFcw] = */ { CPUMCTX_OFF_AND_SIZE(XState.x87.FCW), "fcw", },
2904 /* [kIemNativeGstReg_FpuFsw] = */ { CPUMCTX_OFF_AND_SIZE(XState.x87.FSW), "fsw", },
2905 /* [kIemNativeGstReg_SegBaseFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].u64Base), "es_base", },
2906 /* [kIemNativeGstReg_SegBaseFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].u64Base), "cs_base", },
2907 /* [kIemNativeGstReg_SegBaseFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[2].u64Base), "ss_base", },
2908 /* [kIemNativeGstReg_SegBaseFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[3].u64Base), "ds_base", },
2909 /* [kIemNativeGstReg_SegBaseFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[4].u64Base), "fs_base", },
2910 /* [kIemNativeGstReg_SegBaseFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[5].u64Base), "gs_base", },
2911 /* [kIemNativeGstReg_SegAttribFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].Attr.u), "es_attrib", },
2912 /* [kIemNativeGstReg_SegAttribFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].Attr.u), "cs_attrib", },
2913 /* [kIemNativeGstReg_SegAttribFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[2].Attr.u), "ss_attrib", },
2914 /* [kIemNativeGstReg_SegAttribFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[3].Attr.u), "ds_attrib", },
2915 /* [kIemNativeGstReg_SegAttribFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[4].Attr.u), "fs_attrib", },
2916 /* [kIemNativeGstReg_SegAttribFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[5].Attr.u), "gs_attrib", },
2917 /* [kIemNativeGstReg_SegLimitFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].u32Limit), "es_limit", },
2918 /* [kIemNativeGstReg_SegLimitFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].u32Limit), "cs_limit", },
2919 /* [kIemNativeGstReg_SegLimitFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[2].u32Limit), "ss_limit", },
2920 /* [kIemNativeGstReg_SegLimitFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[3].u32Limit), "ds_limit", },
2921 /* [kIemNativeGstReg_SegLimitFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[4].u32Limit), "fs_limit", },
2922 /* [kIemNativeGstReg_SegLimitFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[5].u32Limit), "gs_limit", },
2923 /* [kIemNativeGstReg_SegSelFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].Sel), "es", },
2924 /* [kIemNativeGstReg_SegSelFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].Sel), "cs", },
2925 /* [kIemNativeGstReg_SegSelFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[2].Sel), "ss", },
2926 /* [kIemNativeGstReg_SegSelFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[3].Sel), "ds", },
2927 /* [kIemNativeGstReg_SegSelFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[4].Sel), "fs", },
2928 /* [kIemNativeGstReg_SegSelFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[5].Sel), "gs", },
2929 /* [kIemNativeGstReg_Cr4] = */ { CPUMCTX_OFF_AND_SIZE(cr4), "cr4", },
2930 /* [kIemNativeGstReg_Xcr0] = */ { CPUMCTX_OFF_AND_SIZE(aXcr[0]), "xcr0", },
2931 /* [kIemNativeGstReg_MxCsr] = */ { CPUMCTX_OFF_AND_SIZE(XState.x87.MXCSR), "mxcsr", },
2932 /* [kIemNativeGstReg_EFlags] = */ { CPUMCTX_OFF_AND_SIZE(eflags), "eflags", },
2933#undef CPUMCTX_OFF_AND_SIZE
2934};
2935AssertCompile(RT_ELEMENTS(g_aGstShadowInfo) == kIemNativeGstReg_End);
2936
2937
2938/** Host CPU general purpose register names. */
2939DECL_HIDDEN_CONST(const char * const) g_apszIemNativeHstRegNames[] =
2940{
2941#ifdef RT_ARCH_AMD64
2942 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2943#elif RT_ARCH_ARM64
2944 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
2945 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "bp", "lr", "sp/xzr",
2946#else
2947# error "port me"
2948#endif
2949};
2950
2951
2952#if 0 /* unused */
2953/**
2954 * Tries to locate a suitable register in the given register mask.
2955 *
2956 * This ASSUMES the caller has done the minimal/optimal allocation checks and
2957 * failed.
2958 *
2959 * @returns Host register number on success, returns UINT8_MAX on failure.
2960 */
2961static uint8_t iemNativeRegTryAllocFree(PIEMRECOMPILERSTATE pReNative, uint32_t fRegMask)
2962{
2963 Assert(!(fRegMask & ~IEMNATIVE_HST_GREG_MASK));
2964 uint32_t fRegs = ~pReNative->Core.bmHstRegs & fRegMask;
2965 if (fRegs)
2966 {
2967 /** @todo pick better here: */
2968 unsigned const idxReg = ASMBitFirstSetU32(fRegs) - 1;
2969
2970 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows != 0);
2971 Assert( (pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadows)
2972 == pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
2973 Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg));
2974
2975 pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
2976 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
2977 pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
2978 return idxReg;
2979 }
2980 return UINT8_MAX;
2981}
2982#endif /* unused */
2983
2984#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
2985
2986/**
2987 * Stores the host reg @a idxHstReg into guest shadow register @a enmGstReg.
2988 *
2989 * @returns New code buffer offset on success, UINT32_MAX on failure.
2990 * @param pReNative .
2991 * @param off The current code buffer position.
2992 * @param enmGstReg The guest register to store to.
2993 * @param idxHstReg The host register to store from.
2994 */
2995DECL_FORCE_INLINE_THROW(uint32_t)
2996iemNativeEmitStoreGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEGSTREG enmGstReg, uint8_t idxHstReg)
2997{
2998 Assert((unsigned)enmGstReg < (unsigned)kIemNativeGstReg_End);
2999 Assert(g_aGstShadowInfo[enmGstReg].cb != 0);
3000
3001 switch (g_aGstShadowInfo[enmGstReg].cb)
3002 {
3003 case sizeof(uint64_t):
3004 return iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
3005 case sizeof(uint32_t):
3006 return iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
3007 case sizeof(uint16_t):
3008 return iemNativeEmitStoreGprToVCpuU16(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
3009# if 0 /* not present in the table. */
3010 case sizeof(uint8_t):
3011 return iemNativeEmitStoreGprToVCpuU8(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
3012# endif
3013 default:
3014 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IPE_NOT_REACHED_DEFAULT_CASE));
3015 }
3016}
3017
3018
3019/**
3020 * Emits code to flush a pending write of the given guest register,
3021 * version with alternative core state.
3022 *
3023 * @returns New code buffer offset.
3024 * @param pReNative The native recompile state.
3025 * @param off Current code buffer position.
3026 * @param pCore Alternative core state.
3027 * @param enmGstReg The guest register to flush.
3028 */
3029DECL_HIDDEN_THROW(uint32_t)
3030iemNativeRegFlushPendingWriteEx(PIEMRECOMPILERSTATE pReNative, uint32_t off, PIEMNATIVECORESTATE pCore, IEMNATIVEGSTREG enmGstReg)
3031{
3032 uint8_t const idxHstReg = pCore->aidxGstRegShadows[enmGstReg];
3033
3034 Assert( ( enmGstReg >= kIemNativeGstReg_GprFirst
3035 && enmGstReg <= kIemNativeGstReg_GprLast)
3036 || enmGstReg == kIemNativeGstReg_MxCsr);
3037 Assert( idxHstReg != UINT8_MAX
3038 && pCore->bmGstRegShadowDirty & RT_BIT_64(enmGstReg));
3039 Log12(("iemNativeRegFlushPendingWriteEx: Clearing guest register %s shadowed by host %s (off=%#x)\n",
3040 g_aGstShadowInfo[enmGstReg].pszName, g_apszIemNativeHstRegNames[idxHstReg], off));
3041
3042 off = iemNativeEmitStoreGprWithGstShadowReg(pReNative, off, enmGstReg, idxHstReg);
3043
3044 pCore->bmGstRegShadowDirty &= ~RT_BIT_64(enmGstReg);
3045 return off;
3046}
3047
3048
3049/**
3050 * Emits code to flush a pending write of the given guest register.
3051 *
3052 * @returns New code buffer offset.
3053 * @param pReNative The native recompile state.
3054 * @param off Current code buffer position.
3055 * @param enmGstReg The guest register to flush.
3056 */
3057DECL_HIDDEN_THROW(uint32_t)
3058iemNativeRegFlushPendingWrite(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEGSTREG enmGstReg)
3059{
3060 uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[enmGstReg];
3061
3062 Assert( ( enmGstReg >= kIemNativeGstReg_GprFirst
3063 && enmGstReg <= kIemNativeGstReg_GprLast)
3064 || enmGstReg == kIemNativeGstReg_MxCsr);
3065 Assert( idxHstReg != UINT8_MAX
3066 && pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(enmGstReg));
3067 Log12(("iemNativeRegFlushPendingWrite: Clearing guest register %s shadowed by host %s (off=%#x)\n",
3068 g_aGstShadowInfo[enmGstReg].pszName, g_apszIemNativeHstRegNames[idxHstReg], off));
3069
3070 off = iemNativeEmitStoreGprWithGstShadowReg(pReNative, off, enmGstReg, idxHstReg);
3071
3072 pReNative->Core.bmGstRegShadowDirty &= ~RT_BIT_64(enmGstReg);
3073 return off;
3074}
3075
3076
3077/**
3078 * Flush the given set of guest registers if marked as dirty.
3079 *
3080 * @returns New code buffer offset.
3081 * @param pReNative The native recompile state.
3082 * @param off Current code buffer position.
3083 * @param fFlushGstReg The guest register set to flush (default is flush everything).
3084 */
3085DECL_HIDDEN_THROW(uint32_t)
3086iemNativeRegFlushDirtyGuest(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint64_t fFlushGstReg /*= UINT64_MAX*/)
3087{
3088 uint64_t bmGstRegShadowDirty = pReNative->Core.bmGstRegShadowDirty & fFlushGstReg;
3089 if (bmGstRegShadowDirty)
3090 {
3091# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
3092 iemNativeDbgInfoAddNativeOffset(pReNative, off);
3093 iemNativeDbgInfoAddGuestRegWriteback(pReNative, false /*fSimdReg*/, bmGstRegShadowDirty);
3094# endif
3095 do
3096 {
3097 unsigned const idxGstReg = ASMBitFirstSetU64(bmGstRegShadowDirty) - 1;
3098 bmGstRegShadowDirty &= ~RT_BIT_64(idxGstReg);
3099 off = iemNativeRegFlushPendingWrite(pReNative, off, (IEMNATIVEGSTREG)idxGstReg);
3100 Assert(!(pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(idxGstReg)));
3101 } while (bmGstRegShadowDirty);
3102 }
3103
3104 return off;
3105}
3106
3107
3108/**
3109 * Flush all shadowed guest registers marked as dirty for the given host register.
3110 *
3111 * @returns New code buffer offset.
3112 * @param pReNative The native recompile state.
3113 * @param off Current code buffer position.
3114 * @param idxHstReg The host register.
3115 *
3116 * @note This doesn't do any unshadowing of guest registers from the host register.
3117 */
3118DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushDirtyGuestByHostRegShadow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstReg)
3119{
3120 /* We need to flush any pending guest register writes this host register shadows. */
3121 uint64_t fGstRegShadows = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
3122 if (pReNative->Core.bmGstRegShadowDirty & fGstRegShadows)
3123 {
3124# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
3125 iemNativeDbgInfoAddNativeOffset(pReNative, off);
3126 iemNativeDbgInfoAddGuestRegWriteback(pReNative, false /*fSimdReg*/, pReNative->Core.bmGstRegShadowDirty & fGstRegShadows);
3127# endif
3128 uint64_t bmGstRegShadowDirty = pReNative->Core.bmGstRegShadowDirty & fGstRegShadows;
3129 do
3130 {
3131 unsigned const idxGstReg = ASMBitFirstSetU64(bmGstRegShadowDirty) - 1;
3132 bmGstRegShadowDirty &= ~RT_BIT_64(idxGstReg);
3133 off = iemNativeRegFlushPendingWrite(pReNative, off, (IEMNATIVEGSTREG)idxGstReg);
3134 Assert(!(pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(idxGstReg)));
3135 } while (bmGstRegShadowDirty);
3136 }
3137
3138 return off;
3139}
3140
3141#endif /* IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK */
3142
3143
3144/**
3145 * Locate a register, possibly freeing one up.
3146 *
3147 * This ASSUMES the caller has done the minimal/optimal allocation checks and
3148 * failed.
3149 *
3150 * @returns Host register number on success. Returns UINT8_MAX if no registers
3151 * found, the caller is supposed to deal with this and raise a
3152 * allocation type specific status code (if desired).
3153 *
3154 * @throws VBox status code if we're run into trouble spilling a variable of
3155 * recording debug info. Does NOT throw anything if we're out of
3156 * registers, though.
3157 */
3158static uint8_t iemNativeRegAllocFindFree(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile,
3159 uint32_t fRegMask = IEMNATIVE_HST_GREG_MASK & ~IEMNATIVE_REG_FIXED_MASK)
3160{
3161 STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFree);
3162 Assert(!(fRegMask & ~IEMNATIVE_HST_GREG_MASK));
3163 Assert(!(fRegMask & IEMNATIVE_REG_FIXED_MASK));
3164
3165 /*
3166 * Try a freed register that's shadowing a guest register.
3167 */
3168 uint32_t fRegs = ~pReNative->Core.bmHstRegs & fRegMask;
3169 if (fRegs)
3170 {
3171 STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFreeNoVar);
3172
3173#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
3174 /*
3175 * When we have livness information, we use it to kick out all shadowed
3176 * guest register that will not be needed any more in this TB. If we're
3177 * lucky, this may prevent us from ending up here again.
3178 *
3179 * Note! We must consider the previous entry here so we don't free
3180 * anything that the current threaded function requires (current
3181 * entry is produced by the next threaded function).
3182 */
3183 uint32_t const idxCurCall = pReNative->idxCurCall;
3184 if (idxCurCall > 0)
3185 {
3186 PCIEMLIVENESSENTRY const pLivenessEntry = &pReNative->paLivenessEntries[idxCurCall - 1];
3187
3188# ifndef IEMLIVENESS_EXTENDED_LAYOUT
3189 /* Construct a mask of the guest registers in the UNUSED and XCPT_OR_CALL state. */
3190 AssertCompile(IEMLIVENESS_STATE_UNUSED == 1 && IEMLIVENESS_STATE_XCPT_OR_CALL == 2);
3191 uint64_t fToFreeMask = pLivenessEntry->Bit0.bm64 ^ pLivenessEntry->Bit1.bm64; /* mask of regs in either UNUSED */
3192#else
3193 /* Construct a mask of the registers not in the read or write state.
3194 Note! We could skips writes, if they aren't from us, as this is just
3195 a hack to prevent trashing registers that have just been written
3196 or will be written when we retire the current instruction. */
3197 uint64_t fToFreeMask = ~pLivenessEntry->aBits[IEMLIVENESS_BIT_READ].bm64
3198 & ~pLivenessEntry->aBits[IEMLIVENESS_BIT_WRITE].bm64
3199 & IEMLIVENESSBIT_MASK;
3200#endif
3201 /* Merge EFLAGS. */
3202 uint64_t fTmp = fToFreeMask & (fToFreeMask >> 3); /* AF2,PF2,CF2,Other2 = AF,PF,CF,Other & OF,SF,ZF,AF */
3203 fTmp &= fTmp >> 2; /* CF3,Other3 = AF2,PF2 & CF2,Other2 */
3204 fTmp &= fTmp >> 1; /* Other4 = CF3 & Other3 */
3205 fToFreeMask &= RT_BIT_64(kIemNativeGstReg_EFlags) - 1;
3206 fToFreeMask |= fTmp & RT_BIT_64(kIemNativeGstReg_EFlags);
3207
3208 /* If it matches any shadowed registers. */
3209 if (pReNative->Core.bmGstRegShadows & fToFreeMask)
3210 {
3211#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3212 /* Writeback any dirty shadow registers we are about to unshadow. */
3213 *poff = iemNativeRegFlushDirtyGuest(pReNative, *poff, fToFreeMask);
3214#endif
3215
3216 STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFreeLivenessUnshadowed);
3217 iemNativeRegFlushGuestShadows(pReNative, fToFreeMask);
3218 Assert(fRegs == (~pReNative->Core.bmHstRegs & fRegMask)); /* this shall not change. */
3219
3220 /* See if we've got any unshadowed registers we can return now. */
3221 uint32_t const fUnshadowedRegs = fRegs & ~pReNative->Core.bmHstRegsWithGstShadow;
3222 if (fUnshadowedRegs)
3223 {
3224 STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFreeLivenessHelped);
3225 return (fPreferVolatile
3226 ? ASMBitFirstSetU32(fUnshadowedRegs)
3227 : ASMBitLastSetU32( fUnshadowedRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
3228 ? fUnshadowedRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fUnshadowedRegs))
3229 - 1;
3230 }
3231 }
3232 }
3233#endif /* IEMNATIVE_WITH_LIVENESS_ANALYSIS */
3234
3235 unsigned const idxReg = (fPreferVolatile
3236 ? ASMBitFirstSetU32(fRegs)
3237 : ASMBitLastSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
3238 ? fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs))
3239 - 1;
3240
3241 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows != 0);
3242 Assert( (pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadows)
3243 == pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
3244 Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg));
3245
3246#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3247 /* We need to flush any pending guest register writes this host register shadows. */
3248 *poff = iemNativeRegFlushDirtyGuestByHostRegShadow(pReNative, *poff, idxReg);
3249#endif
3250
3251 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
3252 pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
3253 pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
3254 return idxReg;
3255 }
3256
3257 /*
3258 * Try free up a variable that's in a register.
3259 *
3260 * We do two rounds here, first evacuating variables we don't need to be
3261 * saved on the stack, then in the second round move things to the stack.
3262 */
3263 STAM_REL_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFreeVar);
3264 for (uint32_t iLoop = 0; iLoop < 2; iLoop++)
3265 {
3266 uint32_t fVars = pReNative->Core.bmVars;
3267 while (fVars)
3268 {
3269 uint32_t const idxVar = ASMBitFirstSetU32(fVars) - 1;
3270 uint8_t const idxReg = pReNative->Core.aVars[idxVar].idxReg;
3271#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
3272 if (pReNative->Core.aVars[idxVar].fSimdReg) /* Need to ignore SIMD variables here or we end up freeing random registers. */
3273 continue;
3274#endif
3275
3276 if ( idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs)
3277 && (RT_BIT_32(idxReg) & fRegMask)
3278 && ( iLoop == 0
3279 ? pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack
3280 : pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
3281 && !pReNative->Core.aVars[idxVar].fRegAcquired)
3282 {
3283 Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg));
3284 Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxReg].fGstRegShadows)
3285 == pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
3286 Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
3287 Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg))
3288 == RT_BOOL(pReNative->Core.aHstRegs[idxReg].fGstRegShadows));
3289#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3290 Assert(!(pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
3291#endif
3292
3293 if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
3294 {
3295 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
3296 *poff = iemNativeEmitStoreGprByBp(pReNative, *poff, iemNativeStackCalcBpDisp(idxStackSlot), idxReg);
3297 }
3298
3299 pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
3300 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxReg);
3301
3302 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
3303 pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
3304 pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
3305 return idxReg;
3306 }
3307 fVars &= ~RT_BIT_32(idxVar);
3308 }
3309 }
3310
3311 return UINT8_MAX;
3312}
3313
3314
3315/**
3316 * Reassigns a variable to a different register specified by the caller.
3317 *
3318 * @returns The new code buffer position.
3319 * @param pReNative The native recompile state.
3320 * @param off The current code buffer position.
3321 * @param idxVar The variable index.
3322 * @param idxRegOld The old host register number.
3323 * @param idxRegNew The new host register number.
3324 * @param pszCaller The caller for logging.
3325 */
3326static uint32_t iemNativeRegMoveVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
3327 uint8_t idxRegOld, uint8_t idxRegNew, const char *pszCaller)
3328{
3329 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
3330 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxRegOld);
3331#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
3332 Assert(!pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
3333#endif
3334 RT_NOREF(pszCaller);
3335
3336#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3337 Assert(!(pReNative->Core.aHstRegs[idxRegNew].fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
3338#endif
3339 iemNativeRegClearGstRegShadowing(pReNative, idxRegNew, off);
3340
3341 uint64_t fGstRegShadows = pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows;
3342#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3343 Assert(!(fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
3344#endif
3345 Log12(("%s: moving idxVar=%#x from %s to %s (fGstRegShadows=%RX64)\n",
3346 pszCaller, idxVar, g_apszIemNativeHstRegNames[idxRegOld], g_apszIemNativeHstRegNames[idxRegNew], fGstRegShadows));
3347 off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegNew, idxRegOld);
3348
3349 pReNative->Core.aHstRegs[idxRegNew].fGstRegShadows = fGstRegShadows;
3350 pReNative->Core.aHstRegs[idxRegNew].enmWhat = kIemNativeWhat_Var;
3351 pReNative->Core.aHstRegs[idxRegNew].idxVar = idxVar;
3352 if (fGstRegShadows)
3353 {
3354 pReNative->Core.bmHstRegsWithGstShadow = (pReNative->Core.bmHstRegsWithGstShadow & ~RT_BIT_32(idxRegOld))
3355 | RT_BIT_32(idxRegNew);
3356 while (fGstRegShadows)
3357 {
3358 unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegShadows) - 1;
3359 fGstRegShadows &= ~RT_BIT_64(idxGstReg);
3360
3361 Assert(pReNative->Core.aidxGstRegShadows[idxGstReg] == idxRegOld);
3362 pReNative->Core.aidxGstRegShadows[idxGstReg] = idxRegNew;
3363 }
3364 }
3365
3366 pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg = (uint8_t)idxRegNew;
3367 pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows = 0;
3368 pReNative->Core.bmHstRegs = RT_BIT_32(idxRegNew) | (pReNative->Core.bmHstRegs & ~RT_BIT_32(idxRegOld));
3369 return off;
3370}
3371
3372
3373/**
3374 * Moves a variable to a different register or spills it onto the stack.
3375 *
3376 * This must be a stack variable (kIemNativeVarKind_Stack) because the other
3377 * kinds can easily be recreated if needed later.
3378 *
3379 * @returns The new code buffer position.
3380 * @param pReNative The native recompile state.
3381 * @param off The current code buffer position.
3382 * @param idxVar The variable index.
3383 * @param fForbiddenRegs Mask of the forbidden registers. Defaults to
3384 * call-volatile registers.
3385 */
3386DECL_HIDDEN_THROW(uint32_t) iemNativeRegMoveOrSpillStackVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
3387 uint32_t fForbiddenRegs /*= IEMNATIVE_CALL_VOLATILE_GREG_MASK*/)
3388{
3389 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
3390 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
3391 Assert(pVar->enmKind == kIemNativeVarKind_Stack);
3392 Assert(!pVar->fRegAcquired);
3393
3394 uint8_t const idxRegOld = pVar->idxReg;
3395 Assert(idxRegOld < RT_ELEMENTS(pReNative->Core.aHstRegs));
3396 Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxRegOld));
3397 Assert(pReNative->Core.aHstRegs[idxRegOld].enmWhat == kIemNativeWhat_Var);
3398 Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows)
3399 == pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows);
3400 Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
3401 Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxRegOld))
3402 == RT_BOOL(pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows));
3403#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3404 Assert(!(pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
3405#endif
3406
3407
3408 /** @todo Add statistics on this.*/
3409 /** @todo Implement basic variable liveness analysis (python) so variables
3410 * can be freed immediately once no longer used. This has the potential to
3411 * be trashing registers and stack for dead variables.
3412 * Update: This is mostly done. (Not IEMNATIVE_WITH_LIVENESS_ANALYSIS.) */
3413
3414 /*
3415 * First try move it to a different register, as that's cheaper.
3416 */
3417 fForbiddenRegs |= RT_BIT_32(idxRegOld);
3418 fForbiddenRegs |= IEMNATIVE_REG_FIXED_MASK;
3419 uint32_t fRegs = ~pReNative->Core.bmHstRegs & ~fForbiddenRegs;
3420 if (fRegs)
3421 {
3422 /* Avoid using shadow registers, if possible. */
3423 if (fRegs & ~pReNative->Core.bmHstRegsWithGstShadow)
3424 fRegs &= ~pReNative->Core.bmHstRegsWithGstShadow;
3425 unsigned const idxRegNew = ASMBitFirstSetU32(fRegs) - 1;
3426 return iemNativeRegMoveVar(pReNative, off, idxVar, idxRegOld, idxRegNew, "iemNativeRegMoveOrSpillStackVar");
3427 }
3428
3429 /*
3430 * Otherwise we must spill the register onto the stack.
3431 */
3432 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
3433 Log12(("iemNativeRegMoveOrSpillStackVar: spilling idxVar=%#x/idxReg=%d onto the stack (slot %#x bp+%d, off=%#x)\n",
3434 idxVar, idxRegOld, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
3435 off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
3436
3437 pVar->idxReg = UINT8_MAX;
3438 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
3439 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxRegOld);
3440 pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows;
3441 pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows = 0;
3442 return off;
3443}
3444
3445
3446/**
3447 * Allocates a temporary host general purpose register.
3448 *
3449 * This may emit code to save register content onto the stack in order to free
3450 * up a register.
3451 *
3452 * @returns The host register number; throws VBox status code on failure,
3453 * so no need to check the return value.
3454 * @param pReNative The native recompile state.
3455 * @param poff Pointer to the variable with the code buffer position.
3456 * This will be update if we need to move a variable from
3457 * register to stack in order to satisfy the request.
3458 * @param fPreferVolatile Whether to prefer volatile over non-volatile
3459 * registers (@c true, default) or the other way around
3460 * (@c false, for iemNativeRegAllocTmpForGuestReg()).
3461 */
3462DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile /*= true*/)
3463{
3464 /*
3465 * Try find a completely unused register, preferably a call-volatile one.
3466 */
3467 uint8_t idxReg;
3468 uint32_t fRegs = ~pReNative->Core.bmHstRegs
3469 & ~pReNative->Core.bmHstRegsWithGstShadow
3470 & (~IEMNATIVE_REG_FIXED_MASK & IEMNATIVE_HST_GREG_MASK);
3471 if (fRegs)
3472 {
3473 if (fPreferVolatile)
3474 idxReg = (uint8_t)ASMBitFirstSetU32( fRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK
3475 ? fRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
3476 else
3477 idxReg = (uint8_t)ASMBitFirstSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
3478 ? fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
3479 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
3480 Assert(!(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg)));
3481 Log12(("iemNativeRegAllocTmp: %s\n", g_apszIemNativeHstRegNames[idxReg]));
3482 }
3483 else
3484 {
3485 idxReg = iemNativeRegAllocFindFree(pReNative, poff, fPreferVolatile);
3486 AssertStmt(idxReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_TMP));
3487 Log12(("iemNativeRegAllocTmp: %s (slow)\n", g_apszIemNativeHstRegNames[idxReg]));
3488 }
3489 return iemNativeRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Tmp);
3490}
3491
3492
3493/**
3494 * Alternative version of iemNativeRegAllocTmp that takes mask with acceptable
3495 * registers.
3496 *
3497 * @returns The host register number; throws VBox status code on failure,
3498 * so no need to check the return value.
3499 * @param pReNative The native recompile state.
3500 * @param poff Pointer to the variable with the code buffer position.
3501 * This will be update if we need to move a variable from
3502 * register to stack in order to satisfy the request.
3503 * @param fRegMask Mask of acceptable registers.
3504 * @param fPreferVolatile Whether to prefer volatile over non-volatile
3505 * registers (@c true, default) or the other way around
3506 * (@c false, for iemNativeRegAllocTmpForGuestReg()).
3507 */
3508DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
3509 bool fPreferVolatile /*= true*/)
3510{
3511 Assert(!(fRegMask & ~IEMNATIVE_HST_GREG_MASK));
3512 Assert(!(fRegMask & IEMNATIVE_REG_FIXED_MASK));
3513
3514 /*
3515 * Try find a completely unused register, preferably a call-volatile one.
3516 */
3517 uint8_t idxReg;
3518 uint32_t fRegs = ~pReNative->Core.bmHstRegs
3519 & ~pReNative->Core.bmHstRegsWithGstShadow
3520 & (~IEMNATIVE_REG_FIXED_MASK & IEMNATIVE_HST_GREG_MASK)
3521 & fRegMask;
3522 if (fRegs)
3523 {
3524 if (fPreferVolatile)
3525 idxReg = (uint8_t)ASMBitFirstSetU32( fRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK
3526 ? fRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
3527 else
3528 idxReg = (uint8_t)ASMBitFirstSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
3529 ? fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
3530 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
3531 Assert(!(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg)));
3532 Log12(("iemNativeRegAllocTmpEx: %s\n", g_apszIemNativeHstRegNames[idxReg]));
3533 }
3534 else
3535 {
3536 idxReg = iemNativeRegAllocFindFree(pReNative, poff, fPreferVolatile, fRegMask);
3537 AssertStmt(idxReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_TMP));
3538 Log12(("iemNativeRegAllocTmpEx: %s (slow)\n", g_apszIemNativeHstRegNames[idxReg]));
3539 }
3540 return iemNativeRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Tmp);
3541}
3542
3543
3544/**
3545 * Allocates a temporary register for loading an immediate value into.
3546 *
3547 * This will emit code to load the immediate, unless there happens to be an
3548 * unused register with the value already loaded.
3549 *
3550 * The caller will not modify the returned register, it must be considered
3551 * read-only. Free using iemNativeRegFreeTmpImm.
3552 *
3553 * @returns The host register number; throws VBox status code on failure, so no
3554 * need to check the return value.
3555 * @param pReNative The native recompile state.
3556 * @param poff Pointer to the variable with the code buffer position.
3557 * @param uImm The immediate value that the register must hold upon
3558 * return.
3559 * @param fPreferVolatile Whether to prefer volatile over non-volatile
3560 * registers (@c true, default) or the other way around
3561 * (@c false).
3562 *
3563 * @note Reusing immediate values has not been implemented yet.
3564 */
3565DECL_HIDDEN_THROW(uint8_t)
3566iemNativeRegAllocTmpImm(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint64_t uImm, bool fPreferVolatile /*= true*/)
3567{
3568 uint8_t const idxReg = iemNativeRegAllocTmp(pReNative, poff, fPreferVolatile);
3569 *poff = iemNativeEmitLoadGprImm64(pReNative, *poff, idxReg, uImm);
3570 return idxReg;
3571}
3572
3573
3574/**
3575 * Allocates a temporary host general purpose register for keeping a guest
3576 * register value.
3577 *
3578 * Since we may already have a register holding the guest register value,
3579 * code will be emitted to do the loading if that's not the case. Code may also
3580 * be emitted if we have to free up a register to satify the request.
3581 *
3582 * @returns The host register number; throws VBox status code on failure, so no
3583 * need to check the return value.
3584 * @param pReNative The native recompile state.
3585 * @param poff Pointer to the variable with the code buffer
3586 * position. This will be update if we need to move a
3587 * variable from register to stack in order to satisfy
3588 * the request.
3589 * @param enmGstReg The guest register that will is to be updated.
3590 * @param enmIntendedUse How the caller will be using the host register.
3591 * @param fNoVolatileRegs Set if no volatile register allowed, clear if any
3592 * register is okay (default). The ASSUMPTION here is
3593 * that the caller has already flushed all volatile
3594 * registers, so this is only applied if we allocate a
3595 * new register.
3596 * @param fSkipLivenessAssert Hack for liveness input validation of EFLAGS.
3597 * @sa iemNativeRegAllocTmpForGuestRegIfAlreadyPresent
3598 */
3599DECL_HIDDEN_THROW(uint8_t)
3600iemNativeRegAllocTmpForGuestReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, IEMNATIVEGSTREG enmGstReg,
3601 IEMNATIVEGSTREGUSE enmIntendedUse /*= kIemNativeGstRegUse_ReadOnly*/,
3602 bool fNoVolatileRegs /*= false*/, bool fSkipLivenessAssert /*= false*/)
3603{
3604 Assert(enmGstReg < kIemNativeGstReg_End && g_aGstShadowInfo[enmGstReg].cb != 0);
3605#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
3606 AssertMsg( fSkipLivenessAssert
3607 || pReNative->idxCurCall == 0
3608 || enmGstReg == kIemNativeGstReg_Pc
3609 || (enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
3610 ? IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))
3611 : enmIntendedUse == kIemNativeGstRegUse_ForUpdate
3612 ? IEMLIVENESS_STATE_IS_MODIFY_EXPECTED( iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))
3613 : IEMLIVENESS_STATE_IS_INPUT_EXPECTED( iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)) ),
3614 ("%s - %u\n", g_aGstShadowInfo[enmGstReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)));
3615#endif
3616 RT_NOREF(fSkipLivenessAssert);
3617#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
3618 static const char * const s_pszIntendedUse[] = { "fetch", "update", "full write", "destructive calc" };
3619#endif
3620 uint32_t const fRegMask = !fNoVolatileRegs
3621 ? IEMNATIVE_HST_GREG_MASK & ~IEMNATIVE_REG_FIXED_MASK
3622 : IEMNATIVE_HST_GREG_MASK & ~IEMNATIVE_REG_FIXED_MASK & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK;
3623
3624 /*
3625 * First check if the guest register value is already in a host register.
3626 */
3627 if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
3628 {
3629 uint8_t idxReg = pReNative->Core.aidxGstRegShadows[enmGstReg];
3630 Assert(idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
3631 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows & RT_BIT_64(enmGstReg));
3632 Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg));
3633
3634 /* It's not supposed to be allocated... */
3635 if (!(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg)))
3636 {
3637 /*
3638 * If the register will trash the guest shadow copy, try find a
3639 * completely unused register we can use instead. If that fails,
3640 * we need to disassociate the host reg from the guest reg.
3641 */
3642 /** @todo would be nice to know if preserving the register is in any way helpful. */
3643 /* If the purpose is calculations, try duplicate the register value as
3644 we'll be clobbering the shadow. */
3645 if ( enmIntendedUse == kIemNativeGstRegUse_Calculation
3646 && ( ~pReNative->Core.bmHstRegs
3647 & ~pReNative->Core.bmHstRegsWithGstShadow
3648 & (~IEMNATIVE_REG_FIXED_MASK & IEMNATIVE_HST_GREG_MASK)))
3649 {
3650 uint8_t const idxRegNew = iemNativeRegAllocTmpEx(pReNative, poff, fRegMask);
3651
3652 *poff = iemNativeEmitLoadGprFromGpr(pReNative, *poff, idxRegNew, idxReg);
3653
3654 Log12(("iemNativeRegAllocTmpForGuestReg: Duplicated %s for guest %s into %s for destructive calc\n",
3655 g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName,
3656 g_apszIemNativeHstRegNames[idxRegNew]));
3657 idxReg = idxRegNew;
3658 }
3659 /* If the current register matches the restrictions, go ahead and allocate
3660 it for the caller. */
3661 else if (fRegMask & RT_BIT_32(idxReg))
3662 {
3663 pReNative->Core.bmHstRegs |= RT_BIT_32(idxReg);
3664 pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Tmp;
3665 pReNative->Core.aHstRegs[idxReg].idxVar = UINT8_MAX;
3666 if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
3667 Log12(("iemNativeRegAllocTmpForGuestReg: Reusing %s for guest %s %s\n",
3668 g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName, s_pszIntendedUse[enmIntendedUse]));
3669 else
3670 {
3671 iemNativeRegClearGstRegShadowing(pReNative, idxReg, *poff);
3672 Log12(("iemNativeRegAllocTmpForGuestReg: Grabbing %s for guest %s - destructive calc\n",
3673 g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName));
3674 }
3675 }
3676 /* Otherwise, allocate a register that satisfies the caller and transfer
3677 the shadowing if compatible with the intended use. (This basically
3678 means the call wants a non-volatile register (RSP push/pop scenario).) */
3679 else
3680 {
3681 Assert(fNoVolatileRegs);
3682 uint8_t const idxRegNew = iemNativeRegAllocTmpEx(pReNative, poff, fRegMask & ~RT_BIT_32(idxReg),
3683 !fNoVolatileRegs
3684 && enmIntendedUse == kIemNativeGstRegUse_Calculation);
3685 *poff = iemNativeEmitLoadGprFromGpr(pReNative, *poff, idxRegNew, idxReg);
3686 if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
3687 {
3688 iemNativeRegTransferGstRegShadowing(pReNative, idxReg, idxRegNew, enmGstReg, *poff);
3689 Log12(("iemNativeRegAllocTmpForGuestReg: Transfering %s to %s for guest %s %s\n",
3690 g_apszIemNativeHstRegNames[idxReg], g_apszIemNativeHstRegNames[idxRegNew],
3691 g_aGstShadowInfo[enmGstReg].pszName, s_pszIntendedUse[enmIntendedUse]));
3692 }
3693 else
3694 Log12(("iemNativeRegAllocTmpForGuestReg: Duplicated %s for guest %s into %s for destructive calc\n",
3695 g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName,
3696 g_apszIemNativeHstRegNames[idxRegNew]));
3697 idxReg = idxRegNew;
3698 }
3699 }
3700 else
3701 {
3702 /*
3703 * Oops. Shadowed guest register already allocated!
3704 *
3705 * Allocate a new register, copy the value and, if updating, the
3706 * guest shadow copy assignment to the new register.
3707 */
3708 AssertMsg( enmIntendedUse != kIemNativeGstRegUse_ForUpdate
3709 && enmIntendedUse != kIemNativeGstRegUse_ForFullWrite,
3710 ("This shouldn't happen: idxReg=%d enmGstReg=%d enmIntendedUse=%s\n",
3711 idxReg, enmGstReg, s_pszIntendedUse[enmIntendedUse]));
3712
3713 /** @todo share register for readonly access. */
3714 uint8_t const idxRegNew = iemNativeRegAllocTmpEx(pReNative, poff, fRegMask,
3715 enmIntendedUse == kIemNativeGstRegUse_Calculation);
3716
3717 if (enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
3718 *poff = iemNativeEmitLoadGprFromGpr(pReNative, *poff, idxRegNew, idxReg);
3719
3720 if ( enmIntendedUse != kIemNativeGstRegUse_ForUpdate
3721 && enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
3722 Log12(("iemNativeRegAllocTmpForGuestReg: Duplicated %s for guest %s into %s for %s\n",
3723 g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName,
3724 g_apszIemNativeHstRegNames[idxRegNew], s_pszIntendedUse[enmIntendedUse]));
3725 else
3726 {
3727 iemNativeRegTransferGstRegShadowing(pReNative, idxReg, idxRegNew, enmGstReg, *poff);
3728 Log12(("iemNativeRegAllocTmpForGuestReg: Moved %s for guest %s into %s for %s\n",
3729 g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName,
3730 g_apszIemNativeHstRegNames[idxRegNew], s_pszIntendedUse[enmIntendedUse]));
3731 }
3732 idxReg = idxRegNew;
3733 }
3734 Assert(RT_BIT_32(idxReg) & fRegMask); /* See assumption in fNoVolatileRegs docs. */
3735
3736#ifdef VBOX_STRICT
3737 /* Strict builds: Check that the value is correct. */
3738 *poff = iemNativeEmitGuestRegValueCheck(pReNative, *poff, idxReg, enmGstReg);
3739#endif
3740
3741#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3742 /** @todo r=aeichner Implement for registers other than GPR as well. */
3743 if ( ( enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
3744 || enmIntendedUse == kIemNativeGstRegUse_ForUpdate)
3745 && ( ( enmGstReg >= kIemNativeGstReg_GprFirst
3746 && enmGstReg <= kIemNativeGstReg_GprLast)
3747 || enmGstReg == kIemNativeGstReg_MxCsr))
3748 {
3749# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
3750 iemNativeDbgInfoAddNativeOffset(pReNative, *poff);
3751 iemNativeDbgInfoAddGuestRegDirty(pReNative, false /*fSimdReg*/, enmGstReg, idxReg);
3752# endif
3753 pReNative->Core.bmGstRegShadowDirty |= RT_BIT_64(enmGstReg);
3754 }
3755#endif
3756
3757 return idxReg;
3758 }
3759
3760 /*
3761 * Allocate a new register, load it with the guest value and designate it as a copy of the
3762 */
3763 uint8_t const idxRegNew = iemNativeRegAllocTmpEx(pReNative, poff, fRegMask, enmIntendedUse == kIemNativeGstRegUse_Calculation);
3764
3765 if (enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
3766 *poff = iemNativeEmitLoadGprWithGstShadowReg(pReNative, *poff, idxRegNew, enmGstReg);
3767
3768 if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
3769 iemNativeRegMarkAsGstRegShadow(pReNative, idxRegNew, enmGstReg, *poff);
3770 Log12(("iemNativeRegAllocTmpForGuestReg: Allocated %s for guest %s %s\n",
3771 g_apszIemNativeHstRegNames[idxRegNew], g_aGstShadowInfo[enmGstReg].pszName, s_pszIntendedUse[enmIntendedUse]));
3772
3773#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3774 /** @todo r=aeichner Implement for registers other than GPR as well. */
3775 if ( ( enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
3776 || enmIntendedUse == kIemNativeGstRegUse_ForUpdate)
3777 && ( ( enmGstReg >= kIemNativeGstReg_GprFirst
3778 && enmGstReg <= kIemNativeGstReg_GprLast)
3779 || enmGstReg == kIemNativeGstReg_MxCsr))
3780 {
3781# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
3782 iemNativeDbgInfoAddNativeOffset(pReNative, *poff);
3783 iemNativeDbgInfoAddGuestRegDirty(pReNative, false /*fSimdReg*/, enmGstReg, idxRegNew);
3784# endif
3785 pReNative->Core.bmGstRegShadowDirty |= RT_BIT_64(enmGstReg);
3786 }
3787#endif
3788
3789 return idxRegNew;
3790}
3791
3792
3793/**
3794 * Allocates a temporary host general purpose register that already holds the
3795 * given guest register value.
3796 *
3797 * The use case for this function is places where the shadowing state cannot be
3798 * modified due to branching and such. This will fail if the we don't have a
3799 * current shadow copy handy or if it's incompatible. The only code that will
3800 * be emitted here is value checking code in strict builds.
3801 *
3802 * The intended use can only be readonly!
3803 *
3804 * @returns The host register number, UINT8_MAX if not present.
3805 * @param pReNative The native recompile state.
3806 * @param poff Pointer to the instruction buffer offset.
3807 * Will be updated in strict builds if a register is
3808 * found.
3809 * @param enmGstReg The guest register that will is to be updated.
3810 * @note In strict builds, this may throw instruction buffer growth failures.
3811 * Non-strict builds will not throw anything.
3812 * @sa iemNativeRegAllocTmpForGuestReg
3813 */
3814DECL_HIDDEN_THROW(uint8_t)
3815iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, IEMNATIVEGSTREG enmGstReg)
3816{
3817 Assert(enmGstReg < kIemNativeGstReg_End && g_aGstShadowInfo[enmGstReg].cb != 0);
3818#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
3819 AssertMsg( pReNative->idxCurCall == 0
3820 || IEMLIVENESS_STATE_IS_INPUT_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))
3821 || enmGstReg == kIemNativeGstReg_Pc,
3822 ("%s - %u\n", g_aGstShadowInfo[enmGstReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)));
3823#endif
3824
3825 /*
3826 * First check if the guest register value is already in a host register.
3827 */
3828 if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
3829 {
3830 uint8_t idxReg = pReNative->Core.aidxGstRegShadows[enmGstReg];
3831 Assert(idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
3832 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows & RT_BIT_64(enmGstReg));
3833 Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg));
3834
3835 if (!(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg)))
3836 {
3837 /*
3838 * We only do readonly use here, so easy compared to the other
3839 * variant of this code.
3840 */
3841 pReNative->Core.bmHstRegs |= RT_BIT_32(idxReg);
3842 pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Tmp;
3843 pReNative->Core.aHstRegs[idxReg].idxVar = UINT8_MAX;
3844 Log12(("iemNativeRegAllocTmpForGuestRegIfAlreadyPresent: Reusing %s for guest %s readonly\n",
3845 g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName));
3846
3847#ifdef VBOX_STRICT
3848 /* Strict builds: Check that the value is correct. */
3849 *poff = iemNativeEmitGuestRegValueCheck(pReNative, *poff, idxReg, enmGstReg);
3850#else
3851 RT_NOREF(poff);
3852#endif
3853 return idxReg;
3854 }
3855 }
3856
3857 return UINT8_MAX;
3858}
3859
3860
3861/**
3862 * Allocates argument registers for a function call.
3863 *
3864 * @returns New code buffer offset on success; throws VBox status code on failure, so no
3865 * need to check the return value.
3866 * @param pReNative The native recompile state.
3867 * @param off The current code buffer offset.
3868 * @param cArgs The number of arguments the function call takes.
3869 */
3870DECL_HIDDEN_THROW(uint32_t) iemNativeRegAllocArgs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs)
3871{
3872 AssertStmt(cArgs <= IEMNATIVE_CALL_ARG_GREG_COUNT + IEMNATIVE_FRAME_STACK_ARG_COUNT,
3873 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_4));
3874 Assert(RT_ELEMENTS(g_aidxIemNativeCallRegs) == IEMNATIVE_CALL_ARG_GREG_COUNT);
3875 Assert(RT_ELEMENTS(g_afIemNativeCallRegs) == IEMNATIVE_CALL_ARG_GREG_COUNT);
3876
3877 if (cArgs > RT_ELEMENTS(g_aidxIemNativeCallRegs))
3878 cArgs = RT_ELEMENTS(g_aidxIemNativeCallRegs);
3879 else if (cArgs == 0)
3880 return true;
3881
3882 /*
3883 * Do we get luck and all register are free and not shadowing anything?
3884 */
3885 if (((pReNative->Core.bmHstRegs | pReNative->Core.bmHstRegsWithGstShadow) & g_afIemNativeCallRegs[cArgs]) == 0)
3886 for (uint32_t i = 0; i < cArgs; i++)
3887 {
3888 uint8_t const idxReg = g_aidxIemNativeCallRegs[i];
3889 pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Arg;
3890 pReNative->Core.aHstRegs[idxReg].idxVar = UINT8_MAX;
3891 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
3892 }
3893 /*
3894 * Okay, not lucky so we have to free up the registers.
3895 */
3896 else
3897 for (uint32_t i = 0; i < cArgs; i++)
3898 {
3899 uint8_t const idxReg = g_aidxIemNativeCallRegs[i];
3900 if (pReNative->Core.bmHstRegs & RT_BIT_32(idxReg))
3901 {
3902 switch (pReNative->Core.aHstRegs[idxReg].enmWhat)
3903 {
3904 case kIemNativeWhat_Var:
3905 {
3906 uint8_t const idxVar = pReNative->Core.aHstRegs[idxReg].idxVar;
3907 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
3908 AssertStmt(IEMNATIVE_VAR_IDX_UNPACK(idxVar) < RT_ELEMENTS(pReNative->Core.aVars),
3909 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_5));
3910 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxReg);
3911#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
3912 Assert(!pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
3913#endif
3914
3915 if (pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].enmKind != kIemNativeVarKind_Stack)
3916 pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg = UINT8_MAX;
3917 else
3918 {
3919 off = iemNativeRegMoveOrSpillStackVar(pReNative, off, idxVar);
3920 Assert(!(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg)));
3921 }
3922 break;
3923 }
3924
3925 case kIemNativeWhat_Tmp:
3926 case kIemNativeWhat_Arg:
3927 case kIemNativeWhat_rc:
3928 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_5));
3929 default:
3930 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_6));
3931 }
3932
3933 }
3934 if (pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg))
3935 {
3936 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows != 0);
3937 Assert( (pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadows)
3938 == pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
3939#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
3940 Assert(!(pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
3941#endif
3942 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
3943 pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
3944 pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
3945 }
3946 else
3947 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
3948 pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Arg;
3949 pReNative->Core.aHstRegs[idxReg].idxVar = UINT8_MAX;
3950 }
3951 pReNative->Core.bmHstRegs |= g_afIemNativeCallRegs[cArgs];
3952 return true;
3953}
3954
3955
3956DECL_HIDDEN_THROW(uint8_t) iemNativeRegAssignRc(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg);
3957
3958
3959#if 0
3960/**
3961 * Frees a register assignment of any type.
3962 *
3963 * @param pReNative The native recompile state.
3964 * @param idxHstReg The register to free.
3965 *
3966 * @note Does not update variables.
3967 */
3968DECLHIDDEN(void) iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT
3969{
3970 Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
3971 Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg));
3972 Assert(!(IEMNATIVE_REG_FIXED_MASK & RT_BIT_32(idxHstReg)));
3973 Assert( pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Var
3974 || pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Tmp
3975 || pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Arg
3976 || pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_rc);
3977 Assert( pReNative->Core.aHstRegs[idxHstReg].enmWhat != kIemNativeWhat_Var
3978 || pReNative->Core.aVars[pReNative->Core.aHstRegs[idxHstReg].idxVar].idxReg == UINT8_MAX
3979 || (pReNative->Core.bmVars & RT_BIT_32(pReNative->Core.aHstRegs[idxHstReg].idxVar)));
3980 Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
3981 == pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows);
3982 Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg))
3983 == RT_BOOL(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
3984
3985 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
3986 /* no flushing, right:
3987 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
3988 pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
3989 pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
3990 */
3991}
3992#endif
3993
3994
3995/**
3996 * Frees a temporary register.
3997 *
3998 * Any shadow copies of guest registers assigned to the host register will not
3999 * be flushed by this operation.
4000 */
4001DECLHIDDEN(void) iemNativeRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT
4002{
4003 Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg));
4004 Assert(pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Tmp);
4005 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
4006 Log12(("iemNativeRegFreeTmp: %s (gst: %#RX64)\n",
4007 g_apszIemNativeHstRegNames[idxHstReg], pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
4008}
4009
4010
4011/**
4012 * Frees a temporary immediate register.
4013 *
4014 * It is assumed that the call has not modified the register, so it still hold
4015 * the same value as when it was allocated via iemNativeRegAllocTmpImm().
4016 */
4017DECLHIDDEN(void) iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT
4018{
4019 iemNativeRegFreeTmp(pReNative, idxHstReg);
4020}
4021
4022
4023/**
4024 * Frees a register assigned to a variable.
4025 *
4026 * The register will be disassociated from the variable.
4027 */
4028DECLHIDDEN(void) iemNativeRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT
4029{
4030 Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg));
4031 Assert(pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Var);
4032 uint8_t const idxVar = pReNative->Core.aHstRegs[idxHstReg].idxVar;
4033 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
4034 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxHstReg);
4035#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
4036 Assert(!pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
4037#endif
4038
4039 pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg = UINT8_MAX;
4040 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
4041 if (!fFlushShadows)
4042 Log12(("iemNativeRegFreeVar: %s (gst: %#RX64) idxVar=%#x\n",
4043 g_apszIemNativeHstRegNames[idxHstReg], pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows, idxVar));
4044 else
4045 {
4046 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
4047 uint64_t const fGstRegShadowsOld = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4048#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4049 Assert(!(pReNative->Core.bmGstRegShadowDirty & fGstRegShadowsOld));
4050#endif
4051 pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4052 pReNative->Core.bmGstRegShadows &= ~fGstRegShadowsOld;
4053 uint64_t fGstRegShadows = fGstRegShadowsOld;
4054 while (fGstRegShadows)
4055 {
4056 unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegShadows) - 1;
4057 fGstRegShadows &= ~RT_BIT_64(idxGstReg);
4058
4059 Assert(pReNative->Core.aidxGstRegShadows[idxGstReg] == idxHstReg);
4060 pReNative->Core.aidxGstRegShadows[idxGstReg] = UINT8_MAX;
4061 }
4062 Log12(("iemNativeRegFreeVar: %s (gst: %#RX64 -> 0) idxVar=%#x\n",
4063 g_apszIemNativeHstRegNames[idxHstReg], fGstRegShadowsOld, idxVar));
4064 }
4065}
4066
4067
4068#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
4069# if defined(LOG_ENABLED) || defined(IEMNATIVE_WITH_TB_DEBUG_INFO)
4070/** Host CPU SIMD register names. */
4071DECL_HIDDEN_CONST(const char * const) g_apszIemNativeHstSimdRegNames[] =
4072{
4073# ifdef RT_ARCH_AMD64
4074 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
4075# elif RT_ARCH_ARM64
4076 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
4077 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
4078# else
4079# error "port me"
4080# endif
4081};
4082# endif
4083
4084
4085/**
4086 * Frees a SIMD register assigned to a variable.
4087 *
4088 * The register will be disassociated from the variable.
4089 */
4090DECLHIDDEN(void) iemNativeSimdRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT
4091{
4092 Assert(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxHstReg));
4093 Assert(pReNative->Core.aHstSimdRegs[idxHstReg].enmWhat == kIemNativeWhat_Var);
4094 uint8_t const idxVar = pReNative->Core.aHstSimdRegs[idxHstReg].idxVar;
4095 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
4096 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxHstReg);
4097 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
4098
4099 pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg = UINT8_MAX;
4100 pReNative->Core.bmHstSimdRegs &= ~RT_BIT_32(idxHstReg);
4101 if (!fFlushShadows)
4102 Log12(("iemNativeSimdRegFreeVar: %s (gst: %#RX64) idxVar=%#x\n",
4103 g_apszIemNativeHstSimdRegNames[idxHstReg], pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows, idxVar));
4104 else
4105 {
4106 pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
4107 uint64_t const fGstRegShadowsOld = pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows;
4108 pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows = 0;
4109 pReNative->Core.bmGstSimdRegShadows &= ~fGstRegShadowsOld;
4110 uint64_t fGstRegShadows = fGstRegShadowsOld;
4111 while (fGstRegShadows)
4112 {
4113 unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegShadows) - 1;
4114 fGstRegShadows &= ~RT_BIT_64(idxGstReg);
4115
4116 Assert(pReNative->Core.aidxGstSimdRegShadows[idxGstReg] == idxHstReg);
4117 pReNative->Core.aidxGstSimdRegShadows[idxGstReg] = UINT8_MAX;
4118 }
4119 Log12(("iemNativeSimdRegFreeVar: %s (gst: %#RX64 -> 0) idxVar=%#x\n",
4120 g_apszIemNativeHstSimdRegNames[idxHstReg], fGstRegShadowsOld, idxVar));
4121 }
4122}
4123
4124
4125/**
4126 * Reassigns a variable to a different SIMD register specified by the caller.
4127 *
4128 * @returns The new code buffer position.
4129 * @param pReNative The native recompile state.
4130 * @param off The current code buffer position.
4131 * @param idxVar The variable index.
4132 * @param idxRegOld The old host register number.
4133 * @param idxRegNew The new host register number.
4134 * @param pszCaller The caller for logging.
4135 */
4136static uint32_t iemNativeSimdRegMoveVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
4137 uint8_t idxRegOld, uint8_t idxRegNew, const char *pszCaller)
4138{
4139 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
4140 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxRegOld);
4141 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
4142 RT_NOREF(pszCaller);
4143
4144 Assert(!( (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
4145 & pReNative->Core.aHstSimdRegs[idxRegNew].fGstRegShadows));
4146 iemNativeSimdRegClearGstSimdRegShadowing(pReNative, idxRegNew, off);
4147
4148 uint64_t fGstRegShadows = pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows;
4149 Assert(!( (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
4150 & pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows));
4151
4152 Log12(("%s: moving idxVar=%#x from %s to %s (fGstRegShadows=%RX64)\n",
4153 pszCaller, idxVar, g_apszIemNativeHstSimdRegNames[idxRegOld], g_apszIemNativeHstSimdRegNames[idxRegNew], fGstRegShadows));
4154 off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegNew, idxRegOld);
4155
4156 if (pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].cbVar == sizeof(RTUINT128U))
4157 off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxRegNew, idxRegOld);
4158 else
4159 {
4160 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].cbVar == sizeof(RTUINT256U));
4161 off = iemNativeEmitSimdLoadVecRegFromVecRegU256(pReNative, off, idxRegNew, idxRegOld);
4162 }
4163
4164 pReNative->Core.aHstSimdRegs[idxRegNew].fGstRegShadows = fGstRegShadows;
4165 pReNative->Core.aHstSimdRegs[idxRegNew].enmWhat = kIemNativeWhat_Var;
4166 pReNative->Core.aHstSimdRegs[idxRegNew].idxVar = idxVar;
4167 if (fGstRegShadows)
4168 {
4169 pReNative->Core.bmHstSimdRegsWithGstShadow = (pReNative->Core.bmHstSimdRegsWithGstShadow & ~RT_BIT_32(idxRegOld))
4170 | RT_BIT_32(idxRegNew);
4171 while (fGstRegShadows)
4172 {
4173 unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegShadows) - 1;
4174 fGstRegShadows &= ~RT_BIT_64(idxGstReg);
4175
4176 Assert(pReNative->Core.aidxGstSimdRegShadows[idxGstReg] == idxRegOld);
4177 pReNative->Core.aidxGstSimdRegShadows[idxGstReg] = idxRegNew;
4178 }
4179 }
4180
4181 pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg = (uint8_t)idxRegNew;
4182 pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows = 0;
4183 pReNative->Core.bmHstSimdRegs = RT_BIT_32(idxRegNew) | (pReNative->Core.bmHstSimdRegs & ~RT_BIT_32(idxRegOld));
4184 return off;
4185}
4186
4187
4188/**
4189 * Moves a variable to a different register or spills it onto the stack.
4190 *
4191 * This must be a stack variable (kIemNativeVarKind_Stack) because the other
4192 * kinds can easily be recreated if needed later.
4193 *
4194 * @returns The new code buffer position.
4195 * @param pReNative The native recompile state.
4196 * @param off The current code buffer position.
4197 * @param idxVar The variable index.
4198 * @param fForbiddenRegs Mask of the forbidden registers. Defaults to
4199 * call-volatile registers.
4200 */
4201DECL_HIDDEN_THROW(uint32_t) iemNativeSimdRegMoveOrSpillStackVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
4202 uint32_t fForbiddenRegs /*= IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK*/)
4203{
4204 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
4205 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
4206 Assert(pVar->enmKind == kIemNativeVarKind_Stack);
4207 Assert(!pVar->fRegAcquired);
4208 Assert(!pVar->fSimdReg);
4209
4210 uint8_t const idxRegOld = pVar->idxReg;
4211 Assert(idxRegOld < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
4212 Assert(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxRegOld));
4213 Assert(pReNative->Core.aHstSimdRegs[idxRegOld].enmWhat == kIemNativeWhat_Var);
4214 Assert( (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows)
4215 == pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows);
4216 Assert(pReNative->Core.bmGstSimdRegShadows < RT_BIT_64(kIemNativeGstReg_End));
4217 Assert( RT_BOOL(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxRegOld))
4218 == RT_BOOL(pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows));
4219 Assert(!( (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
4220 & pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows));
4221
4222 /** @todo Add statistics on this.*/
4223 /** @todo Implement basic variable liveness analysis (python) so variables
4224 * can be freed immediately once no longer used. This has the potential to
4225 * be trashing registers and stack for dead variables.
4226 * Update: This is mostly done. (Not IEMNATIVE_WITH_LIVENESS_ANALYSIS.) */
4227
4228 /*
4229 * First try move it to a different register, as that's cheaper.
4230 */
4231 fForbiddenRegs |= RT_BIT_32(idxRegOld);
4232 fForbiddenRegs |= IEMNATIVE_SIMD_REG_FIXED_MASK;
4233 uint32_t fRegs = ~pReNative->Core.bmHstSimdRegs & ~fForbiddenRegs;
4234 if (fRegs)
4235 {
4236 /* Avoid using shadow registers, if possible. */
4237 if (fRegs & ~pReNative->Core.bmHstSimdRegsWithGstShadow)
4238 fRegs &= ~pReNative->Core.bmHstSimdRegsWithGstShadow;
4239 unsigned const idxRegNew = ASMBitFirstSetU32(fRegs) - 1;
4240 return iemNativeSimdRegMoveVar(pReNative, off, idxVar, idxRegOld, idxRegNew, "iemNativeSimdRegMoveOrSpillStackVar");
4241 }
4242
4243 /*
4244 * Otherwise we must spill the register onto the stack.
4245 */
4246 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
4247 Log12(("iemNativeSimdRegMoveOrSpillStackVar: spilling idxVar=%#x/idxReg=%d onto the stack (slot %#x bp+%d, off=%#x)\n",
4248 idxVar, idxRegOld, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
4249
4250 if (pVar->cbVar == sizeof(RTUINT128U))
4251 off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
4252 else
4253 {
4254 Assert(pVar->cbVar == sizeof(RTUINT256U));
4255 off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
4256 }
4257
4258 pVar->idxReg = UINT8_MAX;
4259 pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
4260 pReNative->Core.bmHstSimdRegs &= ~RT_BIT_32(idxRegOld);
4261 pReNative->Core.bmGstSimdRegShadows &= ~pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows;
4262 pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows = 0;
4263 return off;
4264}
4265
4266
4267/**
4268 * Called right before emitting a call instruction to move anything important
4269 * out of call-volatile SIMD registers, free and flush the call-volatile SIMD registers,
4270 * optionally freeing argument variables.
4271 *
4272 * @returns New code buffer offset, UINT32_MAX on failure.
4273 * @param pReNative The native recompile state.
4274 * @param off The code buffer offset.
4275 * @param cArgs The number of arguments the function call takes.
4276 * It is presumed that the host register part of these have
4277 * been allocated as such already and won't need moving,
4278 * just freeing.
4279 * @param fKeepVars Mask of variables that should keep their register
4280 * assignments. Caller must take care to handle these.
4281 */
4282DECL_HIDDEN_THROW(uint32_t)
4283iemNativeSimdRegMoveAndFreeAndFlushAtCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs, uint32_t fKeepVars /*= 0*/)
4284{
4285 Assert(!cArgs); RT_NOREF(cArgs);
4286
4287 /* fKeepVars will reduce this mask. */
4288 uint32_t fSimdRegsToFree = IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK;
4289
4290 /*
4291 * Move anything important out of volatile registers.
4292 */
4293 uint32_t fSimdRegsToMove = IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK
4294#ifdef IEMNATIVE_SIMD_REG_FIXED_TMP0
4295 & ~RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0)
4296#endif
4297 ;
4298
4299 fSimdRegsToMove &= pReNative->Core.bmHstSimdRegs;
4300 if (!fSimdRegsToMove)
4301 { /* likely */ }
4302 else
4303 {
4304 Log12(("iemNativeSimdRegMoveAndFreeAndFlushAtCall: fSimdRegsToMove=%#x\n", fSimdRegsToMove));
4305 while (fSimdRegsToMove != 0)
4306 {
4307 unsigned const idxSimdReg = ASMBitFirstSetU32(fSimdRegsToMove) - 1;
4308 fSimdRegsToMove &= ~RT_BIT_32(idxSimdReg);
4309
4310 switch (pReNative->Core.aHstSimdRegs[idxSimdReg].enmWhat)
4311 {
4312 case kIemNativeWhat_Var:
4313 {
4314 uint8_t const idxVar = pReNative->Core.aHstRegs[idxSimdReg].idxVar;
4315 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
4316 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
4317 Assert(pVar->idxReg == idxSimdReg);
4318 Assert(pVar->fSimdReg);
4319 if (!(RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(idxVar)) & fKeepVars))
4320 {
4321 Log12(("iemNativeSimdRegMoveAndFreeAndFlushAtCall: idxVar=%#x enmKind=%d idxSimdReg=%d\n",
4322 idxVar, pVar->enmKind, pVar->idxReg));
4323 if (pVar->enmKind != kIemNativeVarKind_Stack)
4324 pVar->idxReg = UINT8_MAX;
4325 else
4326 off = iemNativeSimdRegMoveOrSpillStackVar(pReNative, off, idxVar);
4327 }
4328 else
4329 fSimdRegsToFree &= ~RT_BIT_32(idxSimdReg);
4330 continue;
4331 }
4332
4333 case kIemNativeWhat_Arg:
4334 AssertMsgFailed(("What?!?: %u\n", idxSimdReg));
4335 continue;
4336
4337 case kIemNativeWhat_rc:
4338 case kIemNativeWhat_Tmp:
4339 AssertMsgFailed(("Missing free: %u\n", idxSimdReg));
4340 continue;
4341
4342 case kIemNativeWhat_FixedReserved:
4343#ifdef RT_ARCH_ARM64
4344 continue; /* On ARM the upper half of the virtual 256-bit register. */
4345#endif
4346
4347 case kIemNativeWhat_FixedTmp:
4348 case kIemNativeWhat_pVCpuFixed:
4349 case kIemNativeWhat_pCtxFixed:
4350 case kIemNativeWhat_PcShadow:
4351 case kIemNativeWhat_Invalid:
4352 case kIemNativeWhat_End:
4353 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_1));
4354 }
4355 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_2));
4356 }
4357 }
4358
4359 /*
4360 * Do the actual freeing.
4361 */
4362 if (pReNative->Core.bmHstSimdRegs & fSimdRegsToFree)
4363 Log12(("iemNativeSimdRegMoveAndFreeAndFlushAtCall: bmHstSimdRegs %#x -> %#x\n",
4364 pReNative->Core.bmHstSimdRegs, pReNative->Core.bmHstSimdRegs & ~fSimdRegsToFree));
4365 pReNative->Core.bmHstSimdRegs &= ~fSimdRegsToFree;
4366
4367 /* If there are guest register shadows in any call-volatile register, we
4368 have to clear the corrsponding guest register masks for each register. */
4369 uint32_t fHstSimdRegsWithGstShadow = pReNative->Core.bmHstSimdRegsWithGstShadow & fSimdRegsToFree;
4370 if (fHstSimdRegsWithGstShadow)
4371 {
4372 Log12(("iemNativeSimdRegMoveAndFreeAndFlushAtCall: bmHstSimdRegsWithGstShadow %#RX32 -> %#RX32; removed %#RX32\n",
4373 pReNative->Core.bmHstSimdRegsWithGstShadow, pReNative->Core.bmHstSimdRegsWithGstShadow & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK, fHstSimdRegsWithGstShadow));
4374 pReNative->Core.bmHstSimdRegsWithGstShadow &= ~fHstSimdRegsWithGstShadow;
4375 do
4376 {
4377 unsigned const idxSimdReg = ASMBitFirstSetU32(fHstSimdRegsWithGstShadow) - 1;
4378 fHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxSimdReg);
4379
4380 AssertMsg(pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows != 0, ("idxSimdReg=%#x\n", idxSimdReg));
4381
4382#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4383 /*
4384 * Flush any pending writes now (might have been skipped earlier in iemEmitCallCommon() but it doesn't apply
4385 * to call volatile registers).
4386 */
4387 if ( (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
4388 & pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows)
4389 off = iemNativeSimdRegFlushDirtyGuestByHostSimdRegShadow(pReNative, off, idxSimdReg);
4390#endif
4391 Assert(!( (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
4392 & pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows));
4393
4394 pReNative->Core.bmGstSimdRegShadows &= ~pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows;
4395 pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows = 0;
4396 } while (fHstSimdRegsWithGstShadow != 0);
4397 }
4398
4399 return off;
4400}
4401#endif
4402
4403
4404/**
4405 * Called right before emitting a call instruction to move anything important
4406 * out of call-volatile registers, free and flush the call-volatile registers,
4407 * optionally freeing argument variables.
4408 *
4409 * @returns New code buffer offset, UINT32_MAX on failure.
4410 * @param pReNative The native recompile state.
4411 * @param off The code buffer offset.
4412 * @param cArgs The number of arguments the function call takes.
4413 * It is presumed that the host register part of these have
4414 * been allocated as such already and won't need moving,
4415 * just freeing.
4416 * @param fKeepVars Mask of variables that should keep their register
4417 * assignments. Caller must take care to handle these.
4418 */
4419DECL_HIDDEN_THROW(uint32_t)
4420iemNativeRegMoveAndFreeAndFlushAtCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs, uint32_t fKeepVars /*= 0*/)
4421{
4422 Assert(cArgs <= IEMNATIVE_CALL_MAX_ARG_COUNT);
4423
4424 /* fKeepVars will reduce this mask. */
4425 uint32_t fRegsToFree = IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK;
4426
4427#ifdef RT_ARCH_ARM64
4428AssertCompile(IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK == UINT32_C(0x37fff));
4429#endif
4430
4431 /*
4432 * Move anything important out of volatile registers.
4433 */
4434 if (cArgs > RT_ELEMENTS(g_aidxIemNativeCallRegs))
4435 cArgs = RT_ELEMENTS(g_aidxIemNativeCallRegs);
4436 uint32_t fRegsToMove = IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK
4437#ifdef IEMNATIVE_REG_FIXED_PC_DBG
4438 & ~RT_BIT_32(IEMNATIVE_REG_FIXED_PC_DBG)
4439#endif
4440 & ~g_afIemNativeCallRegs[cArgs];
4441
4442 fRegsToMove &= pReNative->Core.bmHstRegs;
4443 if (!fRegsToMove)
4444 { /* likely */ }
4445 else
4446 {
4447 Log12(("iemNativeRegMoveAndFreeAndFlushAtCall: fRegsToMove=%#x\n", fRegsToMove));
4448 while (fRegsToMove != 0)
4449 {
4450 unsigned const idxReg = ASMBitFirstSetU32(fRegsToMove) - 1;
4451 fRegsToMove &= ~RT_BIT_32(idxReg);
4452
4453 switch (pReNative->Core.aHstRegs[idxReg].enmWhat)
4454 {
4455 case kIemNativeWhat_Var:
4456 {
4457 uint8_t const idxVar = pReNative->Core.aHstRegs[idxReg].idxVar;
4458 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
4459 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
4460 Assert(pVar->idxReg == idxReg);
4461#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
4462 Assert(!pVar->fSimdReg);
4463#endif
4464 if (!(RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(idxVar)) & fKeepVars))
4465 {
4466 Log12(("iemNativeRegMoveAndFreeAndFlushAtCall: idxVar=%#x enmKind=%d idxReg=%d\n",
4467 idxVar, pVar->enmKind, pVar->idxReg));
4468 if (pVar->enmKind != kIemNativeVarKind_Stack)
4469 pVar->idxReg = UINT8_MAX;
4470 else
4471 off = iemNativeRegMoveOrSpillStackVar(pReNative, off, idxVar);
4472 }
4473 else
4474 fRegsToFree &= ~RT_BIT_32(idxReg);
4475 continue;
4476 }
4477
4478 case kIemNativeWhat_Arg:
4479 AssertMsgFailed(("What?!?: %u\n", idxReg));
4480 continue;
4481
4482 case kIemNativeWhat_rc:
4483 case kIemNativeWhat_Tmp:
4484 AssertMsgFailed(("Missing free: %u\n", idxReg));
4485 continue;
4486
4487 case kIemNativeWhat_FixedTmp:
4488 case kIemNativeWhat_pVCpuFixed:
4489 case kIemNativeWhat_pCtxFixed:
4490 case kIemNativeWhat_PcShadow:
4491 case kIemNativeWhat_FixedReserved:
4492 case kIemNativeWhat_Invalid:
4493 case kIemNativeWhat_End:
4494 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_1));
4495 }
4496 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_2));
4497 }
4498 }
4499
4500 /*
4501 * Do the actual freeing.
4502 */
4503 if (pReNative->Core.bmHstRegs & fRegsToFree)
4504 Log12(("iemNativeRegMoveAndFreeAndFlushAtCall: bmHstRegs %#x -> %#x\n",
4505 pReNative->Core.bmHstRegs, pReNative->Core.bmHstRegs & ~fRegsToFree));
4506 pReNative->Core.bmHstRegs &= ~fRegsToFree;
4507
4508 /* If there are guest register shadows in any call-volatile register, we
4509 have to clear the corrsponding guest register masks for each register. */
4510 uint32_t fHstRegsWithGstShadow = pReNative->Core.bmHstRegsWithGstShadow & fRegsToFree;
4511 if (fHstRegsWithGstShadow)
4512 {
4513 Log12(("iemNativeRegMoveAndFreeAndFlushAtCall: bmHstRegsWithGstShadow %#RX32 -> %#RX32; removed %#RX32\n",
4514 pReNative->Core.bmHstRegsWithGstShadow, pReNative->Core.bmHstRegsWithGstShadow & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK,
4515 fHstRegsWithGstShadow));
4516 pReNative->Core.bmHstRegsWithGstShadow &= ~fHstRegsWithGstShadow;
4517 do
4518 {
4519 unsigned const idxReg = ASMBitFirstSetU32(fHstRegsWithGstShadow) - 1;
4520 fHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
4521
4522 AssertMsg(pReNative->Core.aHstRegs[idxReg].fGstRegShadows != 0, ("idxReg=%#x\n", idxReg));
4523
4524#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4525 /*
4526 * Flush any pending writes now (might have been skipped earlier in iemEmitCallCommon() but it doesn't apply
4527 * to call volatile registers).
4528 */
4529 if (pReNative->Core.bmGstRegShadowDirty & pReNative->Core.aHstRegs[idxReg].fGstRegShadows)
4530 off = iemNativeRegFlushDirtyGuestByHostRegShadow(pReNative, off, idxReg);
4531 Assert(!(pReNative->Core.bmGstRegShadowDirty & pReNative->Core.aHstRegs[idxReg].fGstRegShadows));
4532#endif
4533
4534 pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
4535 pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
4536 } while (fHstRegsWithGstShadow != 0);
4537 }
4538
4539#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
4540 /* Now for the SIMD registers, no argument support for now. */
4541 off = iemNativeSimdRegMoveAndFreeAndFlushAtCall(pReNative, off, 0 /*cArgs*/, fKeepVars);
4542#endif
4543
4544 return off;
4545}
4546
4547
4548/**
4549 * Flushes a set of guest register shadow copies.
4550 *
4551 * This is usually done after calling a threaded function or a C-implementation
4552 * of an instruction.
4553 *
4554 * @param pReNative The native recompile state.
4555 * @param fGstRegs Set of guest registers to flush.
4556 */
4557DECLHIDDEN(void) iemNativeRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstRegs) RT_NOEXCEPT
4558{
4559 /*
4560 * Reduce the mask by what's currently shadowed
4561 */
4562 uint64_t const bmGstRegShadowsOld = pReNative->Core.bmGstRegShadows;
4563 fGstRegs &= bmGstRegShadowsOld;
4564 if (fGstRegs)
4565 {
4566 uint64_t const bmGstRegShadowsNew = bmGstRegShadowsOld & ~fGstRegs;
4567 Log12(("iemNativeRegFlushGuestShadows: flushing %#RX64 (%#RX64 -> %#RX64)\n", fGstRegs, bmGstRegShadowsOld, bmGstRegShadowsNew));
4568 pReNative->Core.bmGstRegShadows = bmGstRegShadowsNew;
4569 if (bmGstRegShadowsNew)
4570 {
4571 /*
4572 * Partial.
4573 */
4574 do
4575 {
4576 unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegs) - 1;
4577 uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[idxGstReg];
4578 Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aidxGstRegShadows));
4579 Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg));
4580 Assert(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & RT_BIT_64(idxGstReg));
4581#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4582 Assert(!(pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(idxGstReg)));
4583#endif
4584
4585 uint64_t const fInThisHstReg = (pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & fGstRegs) | RT_BIT_64(idxGstReg);
4586 fGstRegs &= ~fInThisHstReg;
4587 uint64_t const fGstRegShadowsNew = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & ~fInThisHstReg;
4588 pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = fGstRegShadowsNew;
4589 if (!fGstRegShadowsNew)
4590 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
4591 } while (fGstRegs != 0);
4592 }
4593 else
4594 {
4595 /*
4596 * Clear all.
4597 */
4598 do
4599 {
4600 unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegs) - 1;
4601 uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[idxGstReg];
4602 Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aidxGstRegShadows));
4603 Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg));
4604 Assert(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & RT_BIT_64(idxGstReg));
4605#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4606 Assert(!(pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(idxGstReg)));
4607#endif
4608
4609 fGstRegs &= ~(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows | RT_BIT_64(idxGstReg));
4610 pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4611 } while (fGstRegs != 0);
4612 pReNative->Core.bmHstRegsWithGstShadow = 0;
4613 }
4614 }
4615}
4616
4617
4618/**
4619 * Flushes guest register shadow copies held by a set of host registers.
4620 *
4621 * This is used with the TLB lookup code for ensuring that we don't carry on
4622 * with any guest shadows in volatile registers, as these will get corrupted by
4623 * a TLB miss.
4624 *
4625 * @param pReNative The native recompile state.
4626 * @param fHstRegs Set of host registers to flush guest shadows for.
4627 */
4628DECLHIDDEN(void) iemNativeRegFlushGuestShadowsByHostMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegs) RT_NOEXCEPT
4629{
4630 /*
4631 * Reduce the mask by what's currently shadowed.
4632 */
4633 uint32_t const bmHstRegsWithGstShadowOld = pReNative->Core.bmHstRegsWithGstShadow;
4634 fHstRegs &= bmHstRegsWithGstShadowOld;
4635 if (fHstRegs)
4636 {
4637 uint32_t const bmHstRegsWithGstShadowNew = bmHstRegsWithGstShadowOld & ~fHstRegs;
4638 Log12(("iemNativeRegFlushGuestShadowsByHostMask: flushing %#RX32 (%#RX32 -> %#RX32)\n",
4639 fHstRegs, bmHstRegsWithGstShadowOld, bmHstRegsWithGstShadowNew));
4640 pReNative->Core.bmHstRegsWithGstShadow = bmHstRegsWithGstShadowNew;
4641 if (bmHstRegsWithGstShadowNew)
4642 {
4643 /*
4644 * Partial (likely).
4645 */
4646 uint64_t fGstShadows = 0;
4647 do
4648 {
4649 unsigned const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
4650 Assert(!(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg)));
4651 Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
4652 == pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows);
4653#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4654 Assert(!(pReNative->Core.bmGstRegShadowDirty & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
4655#endif
4656
4657 fGstShadows |= pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4658 pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4659 fHstRegs &= ~RT_BIT_32(idxHstReg);
4660 } while (fHstRegs != 0);
4661 pReNative->Core.bmGstRegShadows &= ~fGstShadows;
4662 }
4663 else
4664 {
4665 /*
4666 * Clear all.
4667 */
4668 do
4669 {
4670 unsigned const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
4671 Assert(!(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg)));
4672 Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
4673 == pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows);
4674#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4675 Assert(!(pReNative->Core.bmGstRegShadowDirty & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
4676#endif
4677
4678 pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4679 fHstRegs &= ~RT_BIT_32(idxHstReg);
4680 } while (fHstRegs != 0);
4681 pReNative->Core.bmGstRegShadows = 0;
4682 }
4683 }
4684}
4685
4686
4687/**
4688 * Restores guest shadow copies in volatile registers.
4689 *
4690 * This is used after calling a helper function (think TLB miss) to restore the
4691 * register state of volatile registers.
4692 *
4693 * @param pReNative The native recompile state.
4694 * @param off The code buffer offset.
4695 * @param fHstRegsActiveShadows Set of host registers which are allowed to
4696 * be active (allocated) w/o asserting. Hack.
4697 * @see iemNativeVarSaveVolatileRegsPreHlpCall(),
4698 * iemNativeVarRestoreVolatileRegsPostHlpCall()
4699 */
4700DECL_HIDDEN_THROW(uint32_t)
4701iemNativeRegRestoreGuestShadowsInVolatileRegs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstRegsActiveShadows)
4702{
4703 uint32_t fHstRegs = pReNative->Core.bmHstRegsWithGstShadow & IEMNATIVE_CALL_VOLATILE_GREG_MASK;
4704 if (fHstRegs)
4705 {
4706 Log12(("iemNativeRegRestoreGuestShadowsInVolatileRegs: %#RX32\n", fHstRegs));
4707 do
4708 {
4709 unsigned const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
4710
4711 /* It's not fatal if a register is active holding a variable that
4712 shadowing a guest register, ASSUMING all pending guest register
4713 writes were flushed prior to the helper call. However, we'll be
4714 emitting duplicate restores, so it wasts code space. */
4715 Assert(!(pReNative->Core.bmHstRegs & ~fHstRegsActiveShadows & RT_BIT_32(idxHstReg)));
4716 RT_NOREF(fHstRegsActiveShadows);
4717
4718 uint64_t const fGstRegShadows = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4719#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4720 Assert(!(pReNative->Core.bmGstRegShadowDirty & fGstRegShadows));
4721#endif
4722 Assert((pReNative->Core.bmGstRegShadows & fGstRegShadows) == fGstRegShadows);
4723 AssertStmt(fGstRegShadows != 0 && fGstRegShadows < RT_BIT_64(kIemNativeGstReg_End),
4724 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_12));
4725
4726 unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegShadows) - 1;
4727 off = iemNativeEmitLoadGprWithGstShadowReg(pReNative, off, idxHstReg, (IEMNATIVEGSTREG)idxGstReg);
4728
4729 fHstRegs &= ~RT_BIT_32(idxHstReg);
4730 } while (fHstRegs != 0);
4731 }
4732 return off;
4733}
4734
4735
4736
4737
4738/*********************************************************************************************************************************
4739* SIMD register allocator (largely code duplication of the GPR allocator for now but might diverge) *
4740*********************************************************************************************************************************/
4741#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
4742
4743/**
4744 * Info about shadowed guest SIMD register values.
4745 * @see IEMNATIVEGSTSIMDREG
4746 */
4747static struct
4748{
4749 /** Offset in VMCPU of XMM (low 128-bit) registers. */
4750 uint32_t offXmm;
4751 /** Offset in VMCPU of YmmHi (high 128-bit) registers. */
4752 uint32_t offYmm;
4753 /** Name (for logging). */
4754 const char *pszName;
4755} const g_aGstSimdShadowInfo[] =
4756{
4757#define CPUMCTX_OFF_AND_SIZE(a_iSimdReg) (uint32_t)RT_UOFFSETOF(VMCPU, cpum.GstCtx.XState.x87.aXMM[a_iSimdReg]), \
4758 (uint32_t)RT_UOFFSETOF(VMCPU, cpum.GstCtx.XState.u.YmmHi.aYmmHi[a_iSimdReg])
4759 /* [kIemNativeGstSimdReg_SimdRegFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(0), "ymm0", },
4760 /* [kIemNativeGstSimdReg_SimdRegFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(1), "ymm1", },
4761 /* [kIemNativeGstSimdReg_SimdRegFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(2), "ymm2", },
4762 /* [kIemNativeGstSimdReg_SimdRegFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(3), "ymm3", },
4763 /* [kIemNativeGstSimdReg_SimdRegFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(4), "ymm4", },
4764 /* [kIemNativeGstSimdReg_SimdRegFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(5), "ymm5", },
4765 /* [kIemNativeGstSimdReg_SimdRegFirst + 6] = */ { CPUMCTX_OFF_AND_SIZE(6), "ymm6", },
4766 /* [kIemNativeGstSimdReg_SimdRegFirst + 7] = */ { CPUMCTX_OFF_AND_SIZE(7), "ymm7", },
4767 /* [kIemNativeGstSimdReg_SimdRegFirst + 8] = */ { CPUMCTX_OFF_AND_SIZE(8), "ymm8", },
4768 /* [kIemNativeGstSimdReg_SimdRegFirst + 9] = */ { CPUMCTX_OFF_AND_SIZE(9), "ymm9", },
4769 /* [kIemNativeGstSimdReg_SimdRegFirst + 10] = */ { CPUMCTX_OFF_AND_SIZE(10), "ymm10", },
4770 /* [kIemNativeGstSimdReg_SimdRegFirst + 11] = */ { CPUMCTX_OFF_AND_SIZE(11), "ymm11", },
4771 /* [kIemNativeGstSimdReg_SimdRegFirst + 12] = */ { CPUMCTX_OFF_AND_SIZE(12), "ymm12", },
4772 /* [kIemNativeGstSimdReg_SimdRegFirst + 13] = */ { CPUMCTX_OFF_AND_SIZE(13), "ymm13", },
4773 /* [kIemNativeGstSimdReg_SimdRegFirst + 14] = */ { CPUMCTX_OFF_AND_SIZE(14), "ymm14", },
4774 /* [kIemNativeGstSimdReg_SimdRegFirst + 15] = */ { CPUMCTX_OFF_AND_SIZE(15), "ymm15", },
4775#undef CPUMCTX_OFF_AND_SIZE
4776};
4777AssertCompile(RT_ELEMENTS(g_aGstSimdShadowInfo) == kIemNativeGstSimdReg_End);
4778
4779
4780/**
4781 * Frees a temporary SIMD register.
4782 *
4783 * Any shadow copies of guest registers assigned to the host register will not
4784 * be flushed by this operation.
4785 */
4786DECLHIDDEN(void) iemNativeSimdRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstSimdReg) RT_NOEXCEPT
4787{
4788 Assert(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxHstSimdReg));
4789 Assert(pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmWhat == kIemNativeWhat_Tmp);
4790 pReNative->Core.bmHstSimdRegs &= ~RT_BIT_32(idxHstSimdReg);
4791 Log12(("iemNativeSimdRegFreeTmp: %s (gst: %#RX64)\n",
4792 g_apszIemNativeHstSimdRegNames[idxHstSimdReg], pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows));
4793}
4794
4795
4796/**
4797 * Emits code to flush a pending write of the given SIMD register if any, also flushes the guest to host SIMD register association.
4798 *
4799 * @returns New code bufferoffset.
4800 * @param pReNative The native recompile state.
4801 * @param off Current code buffer position.
4802 * @param enmGstSimdReg The guest SIMD register to flush.
4803 */
4804DECL_HIDDEN_THROW(uint32_t)
4805iemNativeSimdRegFlushPendingWrite(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEGSTSIMDREG enmGstSimdReg)
4806{
4807 uint8_t const idxHstSimdReg = pReNative->Core.aidxGstSimdRegShadows[enmGstSimdReg];
4808
4809 Log12(("iemNativeSimdRegFlushPendingWrite: Clearing guest register %s shadowed by host %s with state DirtyLo:%u DirtyHi:%u\n",
4810 g_aGstSimdShadowInfo[enmGstSimdReg].pszName, g_apszIemNativeHstSimdRegNames[idxHstSimdReg],
4811 IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_LO_U128(pReNative, enmGstSimdReg),
4812 IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_HI_U128(pReNative, enmGstSimdReg)));
4813
4814 if (IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_LO_U128(pReNative, enmGstSimdReg))
4815 {
4816 Assert( pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_256
4817 || pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_Low128);
4818 off = iemNativeEmitSimdStoreVecRegToVCpuLowU128(pReNative, off, idxHstSimdReg, g_aGstSimdShadowInfo[enmGstSimdReg].offXmm);
4819 }
4820
4821 if (IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_HI_U128(pReNative, enmGstSimdReg))
4822 {
4823 Assert( pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_256
4824 || pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_High128);
4825 off = iemNativeEmitSimdStoreVecRegToVCpuHighU128(pReNative, off, idxHstSimdReg, g_aGstSimdShadowInfo[enmGstSimdReg].offYmm);
4826 }
4827
4828 IEMNATIVE_SIMD_REG_STATE_CLR_DIRTY(pReNative, enmGstSimdReg);
4829 return off;
4830}
4831
4832
4833/**
4834 * Flush the given set of guest SIMD registers if marked as dirty.
4835 *
4836 * @returns New code buffer offset.
4837 * @param pReNative The native recompile state.
4838 * @param off Current code buffer position.
4839 * @param fFlushGstSimdReg The guest SIMD register set to flush (default is flush everything).
4840 */
4841DECL_HIDDEN_THROW(uint32_t)
4842iemNativeSimdRegFlushDirtyGuest(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint64_t fFlushGstSimdReg /*= UINT64_MAX*/)
4843{
4844 uint64_t bmGstSimdRegShadowDirty = (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
4845 & fFlushGstSimdReg;
4846 if (bmGstSimdRegShadowDirty)
4847 {
4848# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
4849 iemNativeDbgInfoAddNativeOffset(pReNative, off);
4850 iemNativeDbgInfoAddGuestRegWriteback(pReNative, true /*fSimdReg*/, bmGstSimdRegShadowDirty);
4851# endif
4852
4853 do
4854 {
4855 unsigned const idxGstSimdReg = ASMBitFirstSetU64(bmGstSimdRegShadowDirty) - 1;
4856 bmGstSimdRegShadowDirty &= ~RT_BIT_64(idxGstSimdReg);
4857 off = iemNativeSimdRegFlushPendingWrite(pReNative, off, IEMNATIVEGSTSIMDREG_SIMD(idxGstSimdReg));
4858 } while (bmGstSimdRegShadowDirty);
4859 }
4860
4861 return off;
4862}
4863
4864
4865#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
4866/**
4867 * Flush all shadowed guest SIMD registers marked as dirty for the given host SIMD register.
4868 *
4869 * @returns New code buffer offset.
4870 * @param pReNative The native recompile state.
4871 * @param off Current code buffer position.
4872 * @param idxHstSimdReg The host SIMD register.
4873 *
4874 * @note This doesn't do any unshadowing of guest registers from the host register.
4875 */
4876DECL_HIDDEN_THROW(uint32_t) iemNativeSimdRegFlushDirtyGuestByHostSimdRegShadow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t const idxHstSimdReg)
4877{
4878 /* We need to flush any pending guest register writes this host register shadows. */
4879 uint64_t bmGstSimdRegShadowDirty = (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
4880 & pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows;
4881 if (bmGstSimdRegShadowDirty)
4882 {
4883# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
4884 iemNativeDbgInfoAddNativeOffset(pReNative, off);
4885 iemNativeDbgInfoAddGuestRegWriteback(pReNative, true /*fSimdReg*/, bmGstSimdRegShadowDirty);
4886# endif
4887
4888 do
4889 {
4890 unsigned const idxGstSimdReg = ASMBitFirstSetU64(bmGstSimdRegShadowDirty) - 1;
4891 bmGstSimdRegShadowDirty &= ~RT_BIT_64(idxGstSimdReg);
4892 off = iemNativeSimdRegFlushPendingWrite(pReNative, off, IEMNATIVEGSTSIMDREG_SIMD(idxGstSimdReg));
4893 Assert(!IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_U256(pReNative, idxGstSimdReg));
4894 } while (bmGstSimdRegShadowDirty);
4895 }
4896
4897 return off;
4898}
4899#endif
4900
4901
4902/**
4903 * Locate a register, possibly freeing one up.
4904 *
4905 * This ASSUMES the caller has done the minimal/optimal allocation checks and
4906 * failed.
4907 *
4908 * @returns Host register number on success. Returns UINT8_MAX if no registers
4909 * found, the caller is supposed to deal with this and raise a
4910 * allocation type specific status code (if desired).
4911 *
4912 * @throws VBox status code if we're run into trouble spilling a variable of
4913 * recording debug info. Does NOT throw anything if we're out of
4914 * registers, though.
4915 */
4916static uint8_t iemNativeSimdRegAllocFindFree(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile,
4917 uint32_t fRegMask = IEMNATIVE_HST_SIMD_REG_MASK & ~IEMNATIVE_SIMD_REG_FIXED_MASK)
4918{
4919 STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeSimdRegFindFree);
4920 Assert(!(fRegMask & ~IEMNATIVE_HST_SIMD_REG_MASK));
4921 Assert(!(fRegMask & IEMNATIVE_SIMD_REG_FIXED_MASK));
4922
4923 /*
4924 * Try a freed register that's shadowing a guest register.
4925 */
4926 uint32_t fRegs = ~pReNative->Core.bmHstSimdRegs & fRegMask;
4927 if (fRegs)
4928 {
4929 STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeSimdRegFindFreeNoVar);
4930
4931#if 0 /** @todo def IEMNATIVE_WITH_LIVENESS_ANALYSIS */
4932 /*
4933 * When we have livness information, we use it to kick out all shadowed
4934 * guest register that will not be needed any more in this TB. If we're
4935 * lucky, this may prevent us from ending up here again.
4936 *
4937 * Note! We must consider the previous entry here so we don't free
4938 * anything that the current threaded function requires (current
4939 * entry is produced by the next threaded function).
4940 */
4941 uint32_t const idxCurCall = pReNative->idxCurCall;
4942 if (idxCurCall > 0)
4943 {
4944 PCIEMLIVENESSENTRY const pLivenessEntry = &pReNative->paLivenessEntries[idxCurCall - 1];
4945
4946# ifndef IEMLIVENESS_EXTENDED_LAYOUT
4947 /* Construct a mask of the guest registers in the UNUSED and XCPT_OR_CALL state. */
4948 AssertCompile(IEMLIVENESS_STATE_UNUSED == 1 && IEMLIVENESS_STATE_XCPT_OR_CALL == 2);
4949 uint64_t fToFreeMask = pLivenessEntry->Bit0.bm64 ^ pLivenessEntry->Bit1.bm64; /* mask of regs in either UNUSED */
4950#else
4951 /* Construct a mask of the registers not in the read or write state.
4952 Note! We could skips writes, if they aren't from us, as this is just
4953 a hack to prevent trashing registers that have just been written
4954 or will be written when we retire the current instruction. */
4955 uint64_t fToFreeMask = ~pLivenessEntry->aBits[IEMLIVENESS_BIT_READ].bm64
4956 & ~pLivenessEntry->aBits[IEMLIVENESS_BIT_WRITE].bm64
4957 & IEMLIVENESSBIT_MASK;
4958#endif
4959 /* If it matches any shadowed registers. */
4960 if (pReNative->Core.bmGstRegShadows & fToFreeMask)
4961 {
4962 STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessUnshadowed);
4963 iemNativeRegFlushGuestShadows(pReNative, fToFreeMask);
4964 Assert(fRegs == (~pReNative->Core.bmHstRegs & fRegMask)); /* this shall not change. */
4965
4966 /* See if we've got any unshadowed registers we can return now. */
4967 uint32_t const fUnshadowedRegs = fRegs & ~pReNative->Core.bmHstRegsWithGstShadow;
4968 if (fUnshadowedRegs)
4969 {
4970 STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessHelped);
4971 return (fPreferVolatile
4972 ? ASMBitFirstSetU32(fUnshadowedRegs)
4973 : ASMBitLastSetU32( fUnshadowedRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
4974 ? fUnshadowedRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fUnshadowedRegs))
4975 - 1;
4976 }
4977 }
4978 }
4979#endif /* IEMNATIVE_WITH_LIVENESS_ANALYSIS */
4980
4981 unsigned const idxReg = (fPreferVolatile
4982 ? ASMBitFirstSetU32(fRegs)
4983 : ASMBitLastSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK
4984 ? fRegs & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK : fRegs))
4985 - 1;
4986
4987 Assert(pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows != 0);
4988 Assert( (pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstSimdRegShadows)
4989 == pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows);
4990 Assert(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxReg));
4991
4992 /* We need to flush any pending guest register writes this host SIMD register shadows. */
4993 *poff = iemNativeSimdRegFlushDirtyGuestByHostSimdRegShadow(pReNative, *poff, idxReg);
4994
4995 pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxReg);
4996 pReNative->Core.bmGstSimdRegShadows &= ~pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows;
4997 pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows = 0;
4998 pReNative->Core.aHstSimdRegs[idxReg].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
4999 return idxReg;
5000 }
5001
5002 AssertFailed(); /** @todo The following needs testing when it actually gets hit. */
5003
5004 /*
5005 * Try free up a variable that's in a register.
5006 *
5007 * We do two rounds here, first evacuating variables we don't need to be
5008 * saved on the stack, then in the second round move things to the stack.
5009 */
5010 STAM_REL_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeSimdRegFindFreeVar);
5011 for (uint32_t iLoop = 0; iLoop < 2; iLoop++)
5012 {
5013 uint32_t fVars = pReNative->Core.bmVars;
5014 while (fVars)
5015 {
5016 uint32_t const idxVar = ASMBitFirstSetU32(fVars) - 1;
5017 uint8_t const idxReg = pReNative->Core.aVars[idxVar].idxReg;
5018 if (!pReNative->Core.aVars[idxVar].fSimdReg) /* Ignore non SIMD variables here. */
5019 continue;
5020
5021 if ( idxReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs)
5022 && (RT_BIT_32(idxReg) & fRegMask)
5023 && ( iLoop == 0
5024 ? pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack
5025 : pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
5026 && !pReNative->Core.aVars[idxVar].fRegAcquired)
5027 {
5028 Assert(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxReg));
5029 Assert( (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows)
5030 == pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows);
5031 Assert(pReNative->Core.bmGstSimdRegShadows < RT_BIT_64(kIemNativeGstSimdReg_End));
5032 Assert( RT_BOOL(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxReg))
5033 == RT_BOOL(pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows));
5034
5035 if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
5036 {
5037 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
5038 *poff = iemNativeEmitStoreGprByBp(pReNative, *poff, iemNativeStackCalcBpDisp(idxStackSlot), idxReg);
5039 }
5040
5041 pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
5042 pReNative->Core.bmHstSimdRegs &= ~RT_BIT_32(idxReg);
5043
5044 pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxReg);
5045 pReNative->Core.bmGstSimdRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
5046 pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows = 0;
5047 return idxReg;
5048 }
5049 fVars &= ~RT_BIT_32(idxVar);
5050 }
5051 }
5052
5053 AssertFailed();
5054 return UINT8_MAX;
5055}
5056
5057
5058/**
5059 * Flushes a set of guest register shadow copies.
5060 *
5061 * This is usually done after calling a threaded function or a C-implementation
5062 * of an instruction.
5063 *
5064 * @param pReNative The native recompile state.
5065 * @param fGstSimdRegs Set of guest SIMD registers to flush.
5066 */
5067DECLHIDDEN(void) iemNativeSimdRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstSimdRegs) RT_NOEXCEPT
5068{
5069 /*
5070 * Reduce the mask by what's currently shadowed
5071 */
5072 uint64_t const bmGstSimdRegShadows = pReNative->Core.bmGstSimdRegShadows;
5073 fGstSimdRegs &= bmGstSimdRegShadows;
5074 if (fGstSimdRegs)
5075 {
5076 uint64_t const bmGstSimdRegShadowsNew = bmGstSimdRegShadows & ~fGstSimdRegs;
5077 Log12(("iemNativeSimdRegFlushGuestShadows: flushing %#RX64 (%#RX64 -> %#RX64)\n", fGstSimdRegs, bmGstSimdRegShadows, bmGstSimdRegShadowsNew));
5078 pReNative->Core.bmGstSimdRegShadows = bmGstSimdRegShadowsNew;
5079 if (bmGstSimdRegShadowsNew)
5080 {
5081 /*
5082 * Partial.
5083 */
5084 do
5085 {
5086 unsigned const idxGstReg = ASMBitFirstSetU64(fGstSimdRegs) - 1;
5087 uint8_t const idxHstReg = pReNative->Core.aidxGstSimdRegShadows[idxGstReg];
5088 Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aidxGstSimdRegShadows));
5089 Assert(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxHstReg));
5090 Assert(pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows & RT_BIT_64(idxGstReg));
5091 Assert(!IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_U256(pReNative, idxGstReg));
5092
5093 uint64_t const fInThisHstReg = (pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows & fGstSimdRegs) | RT_BIT_64(idxGstReg);
5094 fGstSimdRegs &= ~fInThisHstReg;
5095 uint64_t const fGstRegShadowsNew = pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows & ~fInThisHstReg;
5096 pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows = fGstRegShadowsNew;
5097 if (!fGstRegShadowsNew)
5098 {
5099 pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
5100 pReNative->Core.aHstSimdRegs[idxHstReg].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
5101 }
5102 } while (fGstSimdRegs != 0);
5103 }
5104 else
5105 {
5106 /*
5107 * Clear all.
5108 */
5109 do
5110 {
5111 unsigned const idxGstReg = ASMBitFirstSetU64(fGstSimdRegs) - 1;
5112 uint8_t const idxHstReg = pReNative->Core.aidxGstSimdRegShadows[idxGstReg];
5113 Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aidxGstSimdRegShadows));
5114 Assert(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxHstReg));
5115 Assert(pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows & RT_BIT_64(idxGstReg));
5116 Assert(!IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_U256(pReNative, idxGstReg));
5117
5118 fGstSimdRegs &= ~(pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows | RT_BIT_64(idxGstReg));
5119 pReNative->Core.aHstSimdRegs[idxHstReg].fGstRegShadows = 0;
5120 pReNative->Core.aHstSimdRegs[idxHstReg].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
5121 } while (fGstSimdRegs != 0);
5122 pReNative->Core.bmHstSimdRegsWithGstShadow = 0;
5123 }
5124 }
5125}
5126
5127
5128/**
5129 * Allocates a temporary host SIMD register.
5130 *
5131 * This may emit code to save register content onto the stack in order to free
5132 * up a register.
5133 *
5134 * @returns The host register number; throws VBox status code on failure,
5135 * so no need to check the return value.
5136 * @param pReNative The native recompile state.
5137 * @param poff Pointer to the variable with the code buffer position.
5138 * This will be update if we need to move a variable from
5139 * register to stack in order to satisfy the request.
5140 * @param fPreferVolatile Whether to prefer volatile over non-volatile
5141 * registers (@c true, default) or the other way around
5142 * (@c false, for iemNativeRegAllocTmpForGuestReg()).
5143 */
5144DECL_HIDDEN_THROW(uint8_t) iemNativeSimdRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile /*= true*/)
5145{
5146 /*
5147 * Try find a completely unused register, preferably a call-volatile one.
5148 */
5149 uint8_t idxSimdReg;
5150 uint32_t fRegs = ~pReNative->Core.bmHstRegs
5151 & ~pReNative->Core.bmHstRegsWithGstShadow
5152 & (~IEMNATIVE_SIMD_REG_FIXED_MASK & IEMNATIVE_HST_SIMD_REG_MASK);
5153 if (fRegs)
5154 {
5155 if (fPreferVolatile)
5156 idxSimdReg = (uint8_t)ASMBitFirstSetU32( fRegs & IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK
5157 ? fRegs & IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK : fRegs) - 1;
5158 else
5159 idxSimdReg = (uint8_t)ASMBitFirstSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK
5160 ? fRegs & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK : fRegs) - 1;
5161 Assert(pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows == 0);
5162 Assert(!(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxSimdReg)));
5163
5164 pReNative->Core.aHstSimdRegs[idxSimdReg].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
5165 Log12(("iemNativeSimdRegAllocTmp: %s\n", g_apszIemNativeHstSimdRegNames[idxSimdReg]));
5166 }
5167 else
5168 {
5169 idxSimdReg = iemNativeSimdRegAllocFindFree(pReNative, poff, fPreferVolatile);
5170 AssertStmt(idxSimdReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_TMP));
5171 Log12(("iemNativeSimdRegAllocTmp: %s (slow)\n", g_apszIemNativeHstSimdRegNames[idxSimdReg]));
5172 }
5173
5174 Assert(pReNative->Core.aHstSimdRegs[idxSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_Invalid);
5175 return iemNativeSimdRegMarkAllocated(pReNative, idxSimdReg, kIemNativeWhat_Tmp);
5176}
5177
5178
5179/**
5180 * Alternative version of iemNativeSimdRegAllocTmp that takes mask with acceptable
5181 * registers.
5182 *
5183 * @returns The host register number; throws VBox status code on failure,
5184 * so no need to check the return value.
5185 * @param pReNative The native recompile state.
5186 * @param poff Pointer to the variable with the code buffer position.
5187 * This will be update if we need to move a variable from
5188 * register to stack in order to satisfy the request.
5189 * @param fRegMask Mask of acceptable registers.
5190 * @param fPreferVolatile Whether to prefer volatile over non-volatile
5191 * registers (@c true, default) or the other way around
5192 * (@c false, for iemNativeRegAllocTmpForGuestReg()).
5193 */
5194DECL_HIDDEN_THROW(uint8_t) iemNativeSimdRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
5195 bool fPreferVolatile /*= true*/)
5196{
5197 Assert(!(fRegMask & ~IEMNATIVE_HST_SIMD_REG_MASK));
5198 Assert(!(fRegMask & IEMNATIVE_SIMD_REG_FIXED_MASK));
5199
5200 /*
5201 * Try find a completely unused register, preferably a call-volatile one.
5202 */
5203 uint8_t idxSimdReg;
5204 uint32_t fRegs = ~pReNative->Core.bmHstSimdRegs
5205 & ~pReNative->Core.bmHstSimdRegsWithGstShadow
5206 & (~IEMNATIVE_SIMD_REG_FIXED_MASK & IEMNATIVE_HST_SIMD_REG_MASK)
5207 & fRegMask;
5208 if (fRegs)
5209 {
5210 if (fPreferVolatile)
5211 idxSimdReg = (uint8_t)ASMBitFirstSetU32( fRegs & IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK
5212 ? fRegs & IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK : fRegs) - 1;
5213 else
5214 idxSimdReg = (uint8_t)ASMBitFirstSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK
5215 ? fRegs & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK : fRegs) - 1;
5216 Assert(pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows == 0);
5217 Assert(!(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxSimdReg)));
5218
5219 pReNative->Core.aHstSimdRegs[idxSimdReg].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
5220 Log12(("iemNativeSimdRegAllocTmpEx: %s\n", g_apszIemNativeHstSimdRegNames[idxSimdReg]));
5221 }
5222 else
5223 {
5224 idxSimdReg = iemNativeSimdRegAllocFindFree(pReNative, poff, fPreferVolatile, fRegMask);
5225 AssertStmt(idxSimdReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_TMP));
5226 Log12(("iemNativeSimdRegAllocTmpEx: %s (slow)\n", g_apszIemNativeHstSimdRegNames[idxSimdReg]));
5227 }
5228
5229 Assert(pReNative->Core.aHstSimdRegs[idxSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_Invalid);
5230 return iemNativeSimdRegMarkAllocated(pReNative, idxSimdReg, kIemNativeWhat_Tmp);
5231}
5232
5233
5234/**
5235 * Sets the indiactor for which part of the given SIMD register has valid data loaded.
5236 *
5237 * @param pReNative The native recompile state.
5238 * @param idxHstSimdReg The host SIMD register to update the state for.
5239 * @param enmLoadSz The load size to set.
5240 */
5241DECL_FORCE_INLINE(void) iemNativeSimdRegSetValidLoadFlag(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstSimdReg,
5242 IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz)
5243{
5244 /* Everything valid already? -> nothing to do. */
5245 if (pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_256)
5246 return;
5247
5248 if (pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_Invalid)
5249 pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded = enmLoadSz;
5250 else if (pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded != enmLoadSz)
5251 {
5252 Assert( ( pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_Low128
5253 && enmLoadSz == kIemNativeGstSimdRegLdStSz_High128)
5254 || ( pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_High128
5255 && enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128));
5256 pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded = kIemNativeGstSimdRegLdStSz_256;
5257 }
5258}
5259
5260
5261static uint32_t iemNativeSimdRegAllocLoadVecRegFromVecRegSz(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEGSTSIMDREG enmGstSimdRegDst,
5262 uint8_t idxHstSimdRegDst, uint8_t idxHstSimdRegSrc, IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSzDst)
5263{
5264 /* Easy case first, either the destination loads the same range as what the source has already loaded or the source has loaded everything. */
5265 if ( pReNative->Core.aHstSimdRegs[idxHstSimdRegSrc].enmLoaded == enmLoadSzDst
5266 || pReNative->Core.aHstSimdRegs[idxHstSimdRegSrc].enmLoaded == kIemNativeGstSimdRegLdStSz_256)
5267 {
5268# ifdef RT_ARCH_ARM64
5269 /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
5270 Assert(!(idxHstSimdRegDst & 0x1)); Assert(!(idxHstSimdRegSrc & 0x1));
5271# endif
5272
5273 if (idxHstSimdRegDst != idxHstSimdRegSrc)
5274 {
5275 switch (enmLoadSzDst)
5276 {
5277 case kIemNativeGstSimdRegLdStSz_256:
5278 off = iemNativeEmitSimdLoadVecRegFromVecRegU256(pReNative, off, idxHstSimdRegDst, idxHstSimdRegSrc);
5279 break;
5280 case kIemNativeGstSimdRegLdStSz_Low128:
5281 off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxHstSimdRegDst, idxHstSimdRegSrc);
5282 break;
5283 case kIemNativeGstSimdRegLdStSz_High128:
5284 off = iemNativeEmitSimdLoadVecRegHighU128FromVecRegHighU128(pReNative, off, idxHstSimdRegDst, idxHstSimdRegSrc);
5285 break;
5286 default:
5287 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IPE_NOT_REACHED_DEFAULT_CASE));
5288 }
5289
5290 iemNativeSimdRegSetValidLoadFlag(pReNative, idxHstSimdRegDst, enmLoadSzDst);
5291 }
5292 }
5293 else
5294 {
5295 /* The source doesn't has the part loaded, so load the register from CPUMCTX. */
5296 Assert(enmLoadSzDst == kIemNativeGstSimdRegLdStSz_Low128 || enmLoadSzDst == kIemNativeGstSimdRegLdStSz_High128);
5297 off = iemNativeEmitLoadSimdRegWithGstShadowSimdReg(pReNative, off, idxHstSimdRegDst, enmGstSimdRegDst, enmLoadSzDst);
5298 }
5299
5300 return off;
5301}
5302
5303
5304/**
5305 * Allocates a temporary host SIMD register for keeping a guest
5306 * SIMD register value.
5307 *
5308 * Since we may already have a register holding the guest register value,
5309 * code will be emitted to do the loading if that's not the case. Code may also
5310 * be emitted if we have to free up a register to satify the request.
5311 *
5312 * @returns The host register number; throws VBox status code on failure, so no
5313 * need to check the return value.
5314 * @param pReNative The native recompile state.
5315 * @param poff Pointer to the variable with the code buffer
5316 * position. This will be update if we need to move a
5317 * variable from register to stack in order to satisfy
5318 * the request.
5319 * @param enmGstSimdReg The guest SIMD register that will is to be updated.
5320 * @param enmIntendedUse How the caller will be using the host register.
5321 * @param fNoVolatileRegs Set if no volatile register allowed, clear if any
5322 * register is okay (default). The ASSUMPTION here is
5323 * that the caller has already flushed all volatile
5324 * registers, so this is only applied if we allocate a
5325 * new register.
5326 * @sa iemNativeRegAllocTmpForGuestRegIfAlreadyPresent
5327 */
5328DECL_HIDDEN_THROW(uint8_t)
5329iemNativeSimdRegAllocTmpForGuestSimdReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, IEMNATIVEGSTSIMDREG enmGstSimdReg,
5330 IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz, IEMNATIVEGSTREGUSE enmIntendedUse /*= kIemNativeGstRegUse_ReadOnly*/,
5331 bool fNoVolatileRegs /*= false*/)
5332{
5333 Assert(enmGstSimdReg < kIemNativeGstSimdReg_End);
5334#if defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) && 0 /** @todo r=aeichner */
5335 AssertMsg( pReNative->idxCurCall == 0
5336 || (enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
5337 ? IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstSimdReg))
5338 : enmIntendedUse == kIemNativeGstRegUse_ForUpdate
5339 ? IEMLIVENESS_STATE_IS_MODIFY_EXPECTED( iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstSimdReg))
5340 : IEMLIVENESS_STATE_IS_INPUT_EXPECTED( iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstSimdReg)) ),
5341 ("%s - %u\n", g_aGstSimdShadowInfo[enmGstSimdReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstSimdReg)));
5342#endif
5343#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
5344 static const char * const s_pszIntendedUse[] = { "fetch", "update", "full write", "destructive calc" };
5345#endif
5346 uint32_t const fRegMask = !fNoVolatileRegs
5347 ? IEMNATIVE_HST_SIMD_REG_MASK & ~IEMNATIVE_SIMD_REG_FIXED_MASK
5348 : IEMNATIVE_HST_SIMD_REG_MASK & ~IEMNATIVE_SIMD_REG_FIXED_MASK & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK;
5349
5350 /*
5351 * First check if the guest register value is already in a host register.
5352 */
5353 if (pReNative->Core.bmGstSimdRegShadows & RT_BIT_64(enmGstSimdReg))
5354 {
5355 uint8_t idxSimdReg = pReNative->Core.aidxGstSimdRegShadows[enmGstSimdReg];
5356 Assert(idxSimdReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
5357 Assert(pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows & RT_BIT_64(enmGstSimdReg));
5358 Assert(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxSimdReg));
5359
5360 /* It's not supposed to be allocated... */
5361 if (!(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxSimdReg)))
5362 {
5363 /*
5364 * If the register will trash the guest shadow copy, try find a
5365 * completely unused register we can use instead. If that fails,
5366 * we need to disassociate the host reg from the guest reg.
5367 */
5368 /** @todo would be nice to know if preserving the register is in any way helpful. */
5369 /* If the purpose is calculations, try duplicate the register value as
5370 we'll be clobbering the shadow. */
5371 if ( enmIntendedUse == kIemNativeGstRegUse_Calculation
5372 && ( ~pReNative->Core.bmHstSimdRegs
5373 & ~pReNative->Core.bmHstSimdRegsWithGstShadow
5374 & (~IEMNATIVE_SIMD_REG_FIXED_MASK & IEMNATIVE_HST_SIMD_REG_MASK)))
5375 {
5376 uint8_t const idxRegNew = iemNativeSimdRegAllocTmpEx(pReNative, poff, fRegMask);
5377
5378 *poff = iemNativeSimdRegAllocLoadVecRegFromVecRegSz(pReNative, *poff, enmGstSimdReg, idxRegNew, idxSimdReg, enmLoadSz);
5379
5380 Log12(("iemNativeSimdRegAllocTmpForGuestSimdReg: Duplicated %s for guest %s into %s for destructive calc\n",
5381 g_apszIemNativeHstSimdRegNames[idxSimdReg], g_aGstSimdShadowInfo[enmGstSimdReg].pszName,
5382 g_apszIemNativeHstSimdRegNames[idxRegNew]));
5383 idxSimdReg = idxRegNew;
5384 }
5385 /* If the current register matches the restrictions, go ahead and allocate
5386 it for the caller. */
5387 else if (fRegMask & RT_BIT_32(idxSimdReg))
5388 {
5389 pReNative->Core.bmHstSimdRegs |= RT_BIT_32(idxSimdReg);
5390 pReNative->Core.aHstSimdRegs[idxSimdReg].enmWhat = kIemNativeWhat_Tmp;
5391 if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
5392 {
5393 if (enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
5394 *poff = iemNativeSimdRegAllocLoadVecRegFromVecRegSz(pReNative, *poff, enmGstSimdReg, idxSimdReg, idxSimdReg, enmLoadSz);
5395 else
5396 iemNativeSimdRegSetValidLoadFlag(pReNative, idxSimdReg, enmLoadSz);
5397 Log12(("iemNativeSimdRegAllocTmpForGuestSimdReg: Reusing %s for guest %s %s\n",
5398 g_apszIemNativeHstSimdRegNames[idxSimdReg], g_aGstSimdShadowInfo[enmGstSimdReg].pszName, s_pszIntendedUse[enmIntendedUse]));
5399 }
5400 else
5401 {
5402 iemNativeSimdRegClearGstSimdRegShadowing(pReNative, idxSimdReg, *poff);
5403 Log12(("iemNativeSimdRegAllocTmpForGuestSimdReg: Grabbing %s for guest %s - destructive calc\n",
5404 g_apszIemNativeHstSimdRegNames[idxSimdReg], g_aGstSimdShadowInfo[enmGstSimdReg].pszName));
5405 }
5406 }
5407 /* Otherwise, allocate a register that satisfies the caller and transfer
5408 the shadowing if compatible with the intended use. (This basically
5409 means the call wants a non-volatile register (RSP push/pop scenario).) */
5410 else
5411 {
5412 Assert(fNoVolatileRegs);
5413 uint8_t const idxRegNew = iemNativeSimdRegAllocTmpEx(pReNative, poff, fRegMask & ~RT_BIT_32(idxSimdReg),
5414 !fNoVolatileRegs
5415 && enmIntendedUse == kIemNativeGstRegUse_Calculation);
5416 *poff = iemNativeSimdRegAllocLoadVecRegFromVecRegSz(pReNative, *poff, enmGstSimdReg, idxRegNew, idxSimdReg, enmLoadSz);
5417 if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
5418 {
5419 iemNativeSimdRegTransferGstSimdRegShadowing(pReNative, idxSimdReg, idxRegNew, enmGstSimdReg, *poff);
5420 Log12(("iemNativeSimdRegAllocTmpForGuestSimdReg: Transfering %s to %s for guest %s %s\n",
5421 g_apszIemNativeHstSimdRegNames[idxSimdReg], g_apszIemNativeHstSimdRegNames[idxRegNew],
5422 g_aGstSimdShadowInfo[enmGstSimdReg].pszName, s_pszIntendedUse[enmIntendedUse]));
5423 }
5424 else
5425 Log12(("iemNativeSimdRegAllocTmpForGuestSimdReg: Duplicated %s for guest %s into %s for destructive calc\n",
5426 g_apszIemNativeHstSimdRegNames[idxSimdReg], g_aGstSimdShadowInfo[enmGstSimdReg].pszName,
5427 g_apszIemNativeHstSimdRegNames[idxRegNew]));
5428 idxSimdReg = idxRegNew;
5429 }
5430 }
5431 else
5432 {
5433 /*
5434 * Oops. Shadowed guest register already allocated!
5435 *
5436 * Allocate a new register, copy the value and, if updating, the
5437 * guest shadow copy assignment to the new register.
5438 */
5439 AssertMsg( enmIntendedUse != kIemNativeGstRegUse_ForUpdate
5440 && enmIntendedUse != kIemNativeGstRegUse_ForFullWrite,
5441 ("This shouldn't happen: idxSimdReg=%d enmGstSimdReg=%d enmIntendedUse=%s\n",
5442 idxSimdReg, enmGstSimdReg, s_pszIntendedUse[enmIntendedUse]));
5443
5444 /** @todo share register for readonly access. */
5445 uint8_t const idxRegNew = iemNativeSimdRegAllocTmpEx(pReNative, poff, fRegMask,
5446 enmIntendedUse == kIemNativeGstRegUse_Calculation);
5447
5448 if (enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
5449 *poff = iemNativeSimdRegAllocLoadVecRegFromVecRegSz(pReNative, *poff, enmGstSimdReg, idxRegNew, idxSimdReg, enmLoadSz);
5450 else
5451 iemNativeSimdRegSetValidLoadFlag(pReNative, idxRegNew, enmLoadSz);
5452
5453 if ( enmIntendedUse != kIemNativeGstRegUse_ForUpdate
5454 && enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
5455 Log12(("iemNativeSimdRegAllocTmpForGuestSimdReg: Duplicated %s for guest %s into %s for %s\n",
5456 g_apszIemNativeHstSimdRegNames[idxSimdReg], g_aGstSimdShadowInfo[enmGstSimdReg].pszName,
5457 g_apszIemNativeHstSimdRegNames[idxRegNew], s_pszIntendedUse[enmIntendedUse]));
5458 else
5459 {
5460 iemNativeSimdRegTransferGstSimdRegShadowing(pReNative, idxSimdReg, idxRegNew, enmGstSimdReg, *poff);
5461 Log12(("iemNativeSimdRegAllocTmpForGuestSimdReg: Moved %s for guest %s into %s for %s\n",
5462 g_apszIemNativeHstSimdRegNames[idxSimdReg], g_aGstSimdShadowInfo[enmGstSimdReg].pszName,
5463 g_apszIemNativeHstSimdRegNames[idxRegNew], s_pszIntendedUse[enmIntendedUse]));
5464 }
5465 idxSimdReg = idxRegNew;
5466 }
5467 Assert(RT_BIT_32(idxSimdReg) & fRegMask); /* See assumption in fNoVolatileRegs docs. */
5468
5469#ifdef VBOX_STRICT
5470 /* Strict builds: Check that the value is correct. */
5471 if (enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
5472 *poff = iemNativeEmitGuestSimdRegValueCheck(pReNative, *poff, idxSimdReg, enmGstSimdReg, enmLoadSz);
5473#endif
5474
5475 if ( enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
5476 || enmIntendedUse == kIemNativeGstRegUse_ForUpdate)
5477 {
5478# if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) && defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
5479 iemNativeDbgInfoAddNativeOffset(pReNative, *poff);
5480 iemNativeDbgInfoAddGuestRegDirty(pReNative, true /*fSimdReg*/, enmGstSimdReg, idxSimdReg);
5481# endif
5482
5483 if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128)
5484 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(pReNative, enmGstSimdReg);
5485 else if (enmLoadSz == kIemNativeGstSimdRegLdStSz_High128)
5486 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_HI_U128(pReNative, enmGstSimdReg);
5487 else
5488 {
5489 Assert(enmLoadSz == kIemNativeGstSimdRegLdStSz_256);
5490 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(pReNative, enmGstSimdReg);
5491 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_HI_U128(pReNative, enmGstSimdReg);
5492 }
5493 }
5494
5495 return idxSimdReg;
5496 }
5497
5498 /*
5499 * Allocate a new register, load it with the guest value and designate it as a copy of the
5500 */
5501 uint8_t const idxRegNew = iemNativeSimdRegAllocTmpEx(pReNative, poff, fRegMask, enmIntendedUse == kIemNativeGstRegUse_Calculation);
5502
5503 if (enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
5504 *poff = iemNativeEmitLoadSimdRegWithGstShadowSimdReg(pReNative, *poff, idxRegNew, enmGstSimdReg, enmLoadSz);
5505 else
5506 iemNativeSimdRegSetValidLoadFlag(pReNative, idxRegNew, enmLoadSz);
5507
5508 if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
5509 iemNativeSimdRegMarkAsGstSimdRegShadow(pReNative, idxRegNew, enmGstSimdReg, *poff);
5510
5511 if ( enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
5512 || enmIntendedUse == kIemNativeGstRegUse_ForUpdate)
5513 {
5514# if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) && defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
5515 iemNativeDbgInfoAddNativeOffset(pReNative, *poff);
5516 iemNativeDbgInfoAddGuestRegDirty(pReNative, true /*fSimdReg*/, enmGstSimdReg, idxRegNew);
5517# endif
5518
5519 if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128)
5520 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(pReNative, enmGstSimdReg);
5521 else if (enmLoadSz == kIemNativeGstSimdRegLdStSz_High128)
5522 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_HI_U128(pReNative, enmGstSimdReg);
5523 else
5524 {
5525 Assert(enmLoadSz == kIemNativeGstSimdRegLdStSz_256);
5526 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(pReNative, enmGstSimdReg);
5527 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_HI_U128(pReNative, enmGstSimdReg);
5528 }
5529 }
5530
5531 Log12(("iemNativeRegAllocTmpForGuestSimdReg: Allocated %s for guest %s %s\n",
5532 g_apszIemNativeHstSimdRegNames[idxRegNew], g_aGstSimdShadowInfo[enmGstSimdReg].pszName, s_pszIntendedUse[enmIntendedUse]));
5533
5534 return idxRegNew;
5535}
5536
5537
5538/**
5539 * Flushes guest SIMD register shadow copies held by a set of host registers.
5540 *
5541 * This is used whenever calling an external helper for ensuring that we don't carry on
5542 * with any guest shadows in volatile registers, as these will get corrupted by the caller.
5543 *
5544 * @param pReNative The native recompile state.
5545 * @param fHstSimdRegs Set of host SIMD registers to flush guest shadows for.
5546 */
5547DECLHIDDEN(void) iemNativeSimdRegFlushGuestShadowsByHostMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstSimdRegs) RT_NOEXCEPT
5548{
5549 /*
5550 * Reduce the mask by what's currently shadowed.
5551 */
5552 uint32_t const bmHstSimdRegsWithGstShadowOld = pReNative->Core.bmHstSimdRegsWithGstShadow;
5553 fHstSimdRegs &= bmHstSimdRegsWithGstShadowOld;
5554 if (fHstSimdRegs)
5555 {
5556 uint32_t const bmHstSimdRegsWithGstShadowNew = bmHstSimdRegsWithGstShadowOld & ~fHstSimdRegs;
5557 Log12(("iemNativeSimdRegFlushGuestShadowsByHostMask: flushing %#RX32 (%#RX32 -> %#RX32)\n",
5558 fHstSimdRegs, bmHstSimdRegsWithGstShadowOld, bmHstSimdRegsWithGstShadowNew));
5559 pReNative->Core.bmHstSimdRegsWithGstShadow = bmHstSimdRegsWithGstShadowNew;
5560 if (bmHstSimdRegsWithGstShadowNew)
5561 {
5562 /*
5563 * Partial (likely).
5564 */
5565 uint64_t fGstShadows = 0;
5566 do
5567 {
5568 unsigned const idxHstSimdReg = ASMBitFirstSetU32(fHstSimdRegs) - 1;
5569 Assert(!(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxHstSimdReg)));
5570 Assert( (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows)
5571 == pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows);
5572 Assert(!(( pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
5573 & pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows));
5574
5575 fGstShadows |= pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows;
5576 pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows = 0;
5577 fHstSimdRegs &= ~RT_BIT_32(idxHstSimdReg);
5578 } while (fHstSimdRegs != 0);
5579 pReNative->Core.bmGstSimdRegShadows &= ~fGstShadows;
5580 }
5581 else
5582 {
5583 /*
5584 * Clear all.
5585 */
5586 do
5587 {
5588 unsigned const idxHstSimdReg = ASMBitFirstSetU32(fHstSimdRegs) - 1;
5589 Assert(!(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxHstSimdReg)));
5590 Assert( (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows)
5591 == pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows);
5592 Assert(!( (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
5593 & pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows));
5594
5595 pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows = 0;
5596 fHstSimdRegs &= ~RT_BIT_32(idxHstSimdReg);
5597 } while (fHstSimdRegs != 0);
5598 pReNative->Core.bmGstSimdRegShadows = 0;
5599 }
5600 }
5601}
5602#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
5603
5604
5605
5606/*********************************************************************************************************************************
5607* Code emitters for flushing pending guest register writes and sanity checks *
5608*********************************************************************************************************************************/
5609
5610#ifdef VBOX_STRICT
5611/**
5612 * Does internal register allocator sanity checks.
5613 */
5614DECLHIDDEN(void) iemNativeRegAssertSanity(PIEMRECOMPILERSTATE pReNative)
5615{
5616 /*
5617 * Iterate host registers building a guest shadowing set.
5618 */
5619 uint64_t bmGstRegShadows = 0;
5620 uint32_t bmHstRegsWithGstShadow = pReNative->Core.bmHstRegsWithGstShadow;
5621 AssertMsg(!(bmHstRegsWithGstShadow & IEMNATIVE_REG_FIXED_MASK), ("%#RX32\n", bmHstRegsWithGstShadow));
5622 while (bmHstRegsWithGstShadow)
5623 {
5624 unsigned const idxHstReg = ASMBitFirstSetU32(bmHstRegsWithGstShadow) - 1;
5625 Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
5626 bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
5627
5628 uint64_t fThisGstRegShadows = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
5629 AssertMsg(fThisGstRegShadows != 0, ("idxHstReg=%d\n", idxHstReg));
5630 AssertMsg(fThisGstRegShadows < RT_BIT_64(kIemNativeGstReg_End), ("idxHstReg=%d %#RX64\n", idxHstReg, fThisGstRegShadows));
5631 bmGstRegShadows |= fThisGstRegShadows;
5632 while (fThisGstRegShadows)
5633 {
5634 unsigned const idxGstReg = ASMBitFirstSetU64(fThisGstRegShadows) - 1;
5635 fThisGstRegShadows &= ~RT_BIT_64(idxGstReg);
5636 AssertMsg(pReNative->Core.aidxGstRegShadows[idxGstReg] == idxHstReg,
5637 ("idxHstReg=%d aidxGstRegShadows[idxGstReg=%d]=%d\n",
5638 idxHstReg, idxGstReg, pReNative->Core.aidxGstRegShadows[idxGstReg]));
5639 }
5640 }
5641 AssertMsg(bmGstRegShadows == pReNative->Core.bmGstRegShadows,
5642 ("%RX64 vs %RX64; diff %RX64\n", bmGstRegShadows, pReNative->Core.bmGstRegShadows,
5643 bmGstRegShadows ^ pReNative->Core.bmGstRegShadows));
5644
5645 /*
5646 * Now the other way around, checking the guest to host index array.
5647 */
5648 bmHstRegsWithGstShadow = 0;
5649 bmGstRegShadows = pReNative->Core.bmGstRegShadows;
5650 Assert(bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
5651 while (bmGstRegShadows)
5652 {
5653 unsigned const idxGstReg = ASMBitFirstSetU64(bmGstRegShadows) - 1;
5654 Assert(idxGstReg < RT_ELEMENTS(pReNative->Core.aidxGstRegShadows));
5655 bmGstRegShadows &= ~RT_BIT_64(idxGstReg);
5656
5657 uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[idxGstReg];
5658 AssertMsg(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs), ("aidxGstRegShadows[%d]=%d\n", idxGstReg, idxHstReg));
5659 AssertMsg(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & RT_BIT_64(idxGstReg),
5660 ("idxGstReg=%d idxHstReg=%d fGstRegShadows=%RX64\n",
5661 idxGstReg, idxHstReg, pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
5662 bmHstRegsWithGstShadow |= RT_BIT_32(idxHstReg);
5663 }
5664 AssertMsg(bmHstRegsWithGstShadow == pReNative->Core.bmHstRegsWithGstShadow,
5665 ("%RX64 vs %RX64; diff %RX64\n", bmHstRegsWithGstShadow, pReNative->Core.bmHstRegsWithGstShadow,
5666 bmHstRegsWithGstShadow ^ pReNative->Core.bmHstRegsWithGstShadow));
5667}
5668#endif /* VBOX_STRICT */
5669
5670
5671/**
5672 * Flushes any delayed guest register writes.
5673 *
5674 * This must be called prior to calling CImpl functions and any helpers that use
5675 * the guest state (like raising exceptions) and such.
5676 *
5677 * @note This function does not flush any shadowing information for guest registers. This needs to be done by
5678 * the caller if it wishes to do so.
5679 */
5680DECL_HIDDEN_THROW(uint32_t)
5681iemNativeRegFlushPendingWritesSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint64_t fGstShwExcept, uint64_t fGstSimdShwExcept)
5682{
5683#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
5684 if (!(fGstShwExcept & RT_BIT_64(kIemNativeGstReg_Pc)))
5685 off = iemNativeEmitPcWriteback(pReNative, off);
5686#else
5687 RT_NOREF(pReNative, fGstShwExcept);
5688#endif
5689
5690#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
5691 off = iemNativeRegFlushDirtyGuest(pReNative, off, ~fGstShwExcept);
5692#endif
5693
5694#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
5695 off = iemNativeSimdRegFlushDirtyGuest(pReNative, off, ~fGstSimdShwExcept);
5696#endif
5697
5698 return off;
5699}
5700
5701#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
5702
5703# ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
5704
5705/**
5706 * Checks if the value in @a idxPcReg matches IEMCPU::uPcUpdatingDebug.
5707 */
5708DECL_HIDDEN_THROW(uint32_t) iemNativeEmitPcDebugCheckWithReg(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxPcReg)
5709{
5710 Assert(idxPcReg != IEMNATIVE_REG_FIXED_TMP0);
5711 Assert(pReNative->Core.fDebugPcInitialized);
5712
5713 /* cmp [pVCpu->iem.s.uPcUpdatingDebug], pcreg */
5714# ifdef RT_ARCH_AMD64
5715 PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
5716 pCodeBuf[off++] = X86_OP_REX_W | (idxPcReg >= 8 ? X86_OP_REX_R : 0);
5717 pCodeBuf[off++] = 0x3b;
5718 off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, idxPcReg & 7, RT_UOFFSETOF(VMCPU, iem.s.uPcUpdatingDebug));
5719# else
5720 PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
5721 off = iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, IEMNATIVE_REG_FIXED_TMP0, RT_UOFFSETOF(VMCPU, iem.s.uPcUpdatingDebug));
5722 off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, IEMNATIVE_REG_FIXED_TMP0, idxPcReg);
5723# endif
5724
5725 uint32_t offFixup = off;
5726 off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off + 1, kIemNativeInstrCond_e);
5727 off = iemNativeEmitBrkEx(pCodeBuf, off, UINT32_C(0x2200));
5728 iemNativeFixupFixedJump(pReNative, offFixup, off);
5729
5730 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5731 return off;
5732}
5733
5734
5735/**
5736 * Checks that the current RIP+offPc matches IEMCPU::uPcUpdatingDebug.
5737 */
5738DECL_HIDDEN_THROW(uint32_t) iemNativeEmitPcDebugCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off)
5739{
5740 if (pReNative->Core.fDebugPcInitialized)
5741 {
5742 uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc);
5743 if (pReNative->Core.offPc)
5744 {
5745 uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
5746 PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, RT_ARCH_VAL == RT_ARCH_VAL_AMD64 ? 32 : 8);
5747 off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, idxTmpReg, idxPcReg, pReNative->Core.offPc);
5748 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5749 off = iemNativeEmitPcDebugCheckWithReg(pReNative, off, idxTmpReg);
5750 iemNativeRegFreeTmp(pReNative, idxTmpReg);
5751 }
5752 else
5753 off = iemNativeEmitPcDebugCheckWithReg(pReNative, off, idxPcReg);
5754 iemNativeRegFreeTmp(pReNative, idxPcReg);
5755 }
5756 return off;
5757}
5758
5759# endif /* IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG */
5760
5761/**
5762 * Emits code to update the guest RIP value by adding the current offset since the start of the last RIP update.
5763 */
5764DECL_HIDDEN_THROW(uint32_t) iemNativeEmitPcWritebackSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off)
5765{
5766 Assert(pReNative->Core.offPc);
5767# if !defined(IEMNATIVE_WITH_TB_DEBUG_INFO) && !defined(VBOX_WITH_STATISTICS)
5768 Log4(("iemNativeEmitPcWritebackSlow: offPc=%#RX64 -> 0; off=%#x\n", pReNative->Core.offPc, off));
5769# else
5770 uint8_t const idxOldInstrPlusOne = pReNative->Core.idxInstrPlusOneOfLastPcUpdate;
5771 uint8_t idxCurCall = pReNative->idxCurCall;
5772 uint8_t idxInstr = pReNative->pTbOrg->Thrd.paCalls[idxCurCall].idxInstr; /* unreliable*/
5773 while (idxInstr == 0 && idxInstr + 1 < idxOldInstrPlusOne && idxCurCall > 0)
5774 idxInstr = pReNative->pTbOrg->Thrd.paCalls[--idxCurCall].idxInstr;
5775 uint8_t const cInstrsSkipped = idxInstr <= pReNative->Core.idxInstrPlusOneOfLastPcUpdate ? 0
5776 : idxInstr - pReNative->Core.idxInstrPlusOneOfLastPcUpdate;
5777 Log4(("iemNativeEmitPcWritebackSlow: offPc=%#RX64 -> 0; off=%#x; idxInstr=%u cInstrsSkipped=%u\n",
5778 pReNative->Core.offPc, off, idxInstr, cInstrsSkipped));
5779
5780 pReNative->Core.idxInstrPlusOneOfLastPcUpdate = RT_MAX(idxInstr + 1, pReNative->Core.idxInstrPlusOneOfLastPcUpdate);
5781 STAM_COUNTER_ADD(&pReNative->pVCpu->iem.s.StatNativePcUpdateDelayed, cInstrsSkipped);
5782
5783# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
5784 iemNativeDbgInfoAddNativeOffset(pReNative, off);
5785 iemNativeDbgInfoAddDelayedPcUpdate(pReNative, pReNative->Core.offPc, cInstrsSkipped);
5786# endif
5787# endif
5788
5789# ifndef IEMNATIVE_REG_FIXED_PC_DBG
5790 /* Allocate a temporary PC register. */
5791 uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, kIemNativeGstRegUse_ForUpdate);
5792
5793 /* Perform the addition and store the result. */
5794 off = iemNativeEmitAddGprImm(pReNative, off, idxPcReg, pReNative->Core.offPc);
5795 off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
5796# ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
5797 off = iemNativeEmitPcDebugCheckWithReg(pReNative, off, idxPcReg);
5798# endif
5799
5800 /* Free but don't flush the PC register. */
5801 iemNativeRegFreeTmp(pReNative, idxPcReg);
5802# else
5803 /* Compare the shadow with the context value, they should match. */
5804 off = iemNativeEmitAddGprImm(pReNative, off, IEMNATIVE_REG_FIXED_PC_DBG, pReNative->Core.offPc);
5805 off = iemNativeEmitGuestRegValueCheck(pReNative, off, IEMNATIVE_REG_FIXED_PC_DBG, kIemNativeGstReg_Pc);
5806# endif
5807
5808 pReNative->Core.offPc = 0;
5809
5810 return off;
5811}
5812
5813#endif /* IEMNATIVE_WITH_DELAYED_PC_UPDATING */
5814
5815
5816/*********************************************************************************************************************************
5817* Code Emitters (larger snippets) *
5818*********************************************************************************************************************************/
5819
5820/**
5821 * Loads the guest shadow register @a enmGstReg into host reg @a idxHstReg, zero
5822 * extending to 64-bit width.
5823 *
5824 * @returns New code buffer offset on success, UINT32_MAX on failure.
5825 * @param pReNative .
5826 * @param off The current code buffer position.
5827 * @param idxHstReg The host register to load the guest register value into.
5828 * @param enmGstReg The guest register to load.
5829 *
5830 * @note This does not mark @a idxHstReg as having a shadow copy of @a enmGstReg,
5831 * that is something the caller needs to do if applicable.
5832 */
5833DECL_HIDDEN_THROW(uint32_t)
5834iemNativeEmitLoadGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg)
5835{
5836 Assert((unsigned)enmGstReg < (unsigned)kIemNativeGstReg_End);
5837 Assert(g_aGstShadowInfo[enmGstReg].cb != 0);
5838
5839 switch (g_aGstShadowInfo[enmGstReg].cb)
5840 {
5841 case sizeof(uint64_t):
5842 return iemNativeEmitLoadGprFromVCpuU64(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
5843 case sizeof(uint32_t):
5844 return iemNativeEmitLoadGprFromVCpuU32(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
5845 case sizeof(uint16_t):
5846 return iemNativeEmitLoadGprFromVCpuU16(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
5847#if 0 /* not present in the table. */
5848 case sizeof(uint8_t):
5849 return iemNativeEmitLoadGprFromVCpuU8(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
5850#endif
5851 default:
5852 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IPE_NOT_REACHED_DEFAULT_CASE));
5853 }
5854}
5855
5856
5857#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
5858/**
5859 * Loads the guest shadow SIMD register @a enmGstSimdReg into host SIMD reg @a idxHstSimdReg.
5860 *
5861 * @returns New code buffer offset on success, UINT32_MAX on failure.
5862 * @param pReNative The recompiler state.
5863 * @param off The current code buffer position.
5864 * @param idxHstSimdReg The host register to load the guest register value into.
5865 * @param enmGstSimdReg The guest register to load.
5866 * @param enmLoadSz The load size of the register.
5867 *
5868 * @note This does not mark @a idxHstReg as having a shadow copy of @a enmGstReg,
5869 * that is something the caller needs to do if applicable.
5870 */
5871DECL_HIDDEN_THROW(uint32_t)
5872iemNativeEmitLoadSimdRegWithGstShadowSimdReg(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstSimdReg,
5873 IEMNATIVEGSTSIMDREG enmGstSimdReg, IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz)
5874{
5875 Assert((unsigned)enmGstSimdReg < RT_ELEMENTS(g_aGstSimdShadowInfo));
5876
5877 iemNativeSimdRegSetValidLoadFlag(pReNative, idxHstSimdReg, enmLoadSz);
5878 switch (enmLoadSz)
5879 {
5880 case kIemNativeGstSimdRegLdStSz_256:
5881 off = iemNativeEmitSimdLoadVecRegFromVCpuLowU128(pReNative, off, idxHstSimdReg, g_aGstSimdShadowInfo[enmGstSimdReg].offXmm);
5882 return iemNativeEmitSimdLoadVecRegFromVCpuHighU128(pReNative, off, idxHstSimdReg, g_aGstSimdShadowInfo[enmGstSimdReg].offYmm);
5883 case kIemNativeGstSimdRegLdStSz_Low128:
5884 return iemNativeEmitSimdLoadVecRegFromVCpuLowU128(pReNative, off, idxHstSimdReg, g_aGstSimdShadowInfo[enmGstSimdReg].offXmm);
5885 case kIemNativeGstSimdRegLdStSz_High128:
5886 return iemNativeEmitSimdLoadVecRegFromVCpuHighU128(pReNative, off, idxHstSimdReg, g_aGstSimdShadowInfo[enmGstSimdReg].offYmm);
5887 default:
5888 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IPE_NOT_REACHED_DEFAULT_CASE));
5889 }
5890}
5891#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
5892
5893#ifdef VBOX_STRICT
5894
5895/**
5896 * Emitting code that checks that the value of @a idxReg is UINT32_MAX or less.
5897 *
5898 * @note May of course trash IEMNATIVE_REG_FIXED_TMP0.
5899 * Trashes EFLAGS on AMD64.
5900 */
5901DECL_HIDDEN_THROW(uint32_t)
5902iemNativeEmitTop32BitsClearCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxReg)
5903{
5904# ifdef RT_ARCH_AMD64
5905 uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 20);
5906
5907 /* rol reg64, 32 */
5908 pbCodeBuf[off++] = X86_OP_REX_W | (idxReg < 8 ? 0 : X86_OP_REX_B);
5909 pbCodeBuf[off++] = 0xc1;
5910 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxReg & 7);
5911 pbCodeBuf[off++] = 32;
5912
5913 /* test reg32, ffffffffh */
5914 if (idxReg >= 8)
5915 pbCodeBuf[off++] = X86_OP_REX_B;
5916 pbCodeBuf[off++] = 0xf7;
5917 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxReg & 7);
5918 pbCodeBuf[off++] = 0xff;
5919 pbCodeBuf[off++] = 0xff;
5920 pbCodeBuf[off++] = 0xff;
5921 pbCodeBuf[off++] = 0xff;
5922
5923 /* je/jz +1 */
5924 pbCodeBuf[off++] = 0x74;
5925 pbCodeBuf[off++] = 0x01;
5926
5927 /* int3 */
5928 pbCodeBuf[off++] = 0xcc;
5929
5930 /* rol reg64, 32 */
5931 pbCodeBuf[off++] = X86_OP_REX_W | (idxReg < 8 ? 0 : X86_OP_REX_B);
5932 pbCodeBuf[off++] = 0xc1;
5933 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxReg & 7);
5934 pbCodeBuf[off++] = 32;
5935
5936# elif defined(RT_ARCH_ARM64)
5937 uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
5938 /* lsr tmp0, reg64, #32 */
5939 pu32CodeBuf[off++] = Armv8A64MkInstrLsrImm(IEMNATIVE_REG_FIXED_TMP0, idxReg, 32);
5940 /* cbz tmp0, +1 */
5941 pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, 2, IEMNATIVE_REG_FIXED_TMP0);
5942 /* brk #0x1100 */
5943 pu32CodeBuf[off++] = Armv8A64MkInstrBrk(UINT32_C(0x1100));
5944
5945# else
5946# error "Port me!"
5947# endif
5948 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5949 return off;
5950}
5951
5952
5953/**
5954 * Emitting code that checks that the content of register @a idxReg is the same
5955 * as what's in the guest register @a enmGstReg, resulting in a breakpoint
5956 * instruction if that's not the case.
5957 *
5958 * @note May of course trash IEMNATIVE_REG_FIXED_TMP0.
5959 * Trashes EFLAGS on AMD64.
5960 */
5961DECL_HIDDEN_THROW(uint32_t)
5962iemNativeEmitGuestRegValueCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxReg, IEMNATIVEGSTREG enmGstReg)
5963{
5964#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
5965 /* We can't check the value against whats in CPUMCTX if the register is already marked as dirty, so skip the check. */
5966 if (pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(enmGstReg))
5967 return off;
5968#endif
5969
5970# ifdef RT_ARCH_AMD64
5971 uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
5972
5973 /* cmp reg, [mem] */
5974 if (g_aGstShadowInfo[enmGstReg].cb == sizeof(uint8_t))
5975 {
5976 if (idxReg >= 8)
5977 pbCodeBuf[off++] = X86_OP_REX_R;
5978 pbCodeBuf[off++] = 0x38;
5979 }
5980 else
5981 {
5982 if (g_aGstShadowInfo[enmGstReg].cb == sizeof(uint64_t))
5983 pbCodeBuf[off++] = X86_OP_REX_W | (idxReg < 8 ? 0 : X86_OP_REX_R);
5984 else
5985 {
5986 if (g_aGstShadowInfo[enmGstReg].cb == sizeof(uint16_t))
5987 pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
5988 else
5989 AssertStmt(g_aGstShadowInfo[enmGstReg].cb == sizeof(uint32_t),
5990 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_6));
5991 if (idxReg >= 8)
5992 pbCodeBuf[off++] = X86_OP_REX_R;
5993 }
5994 pbCodeBuf[off++] = 0x39;
5995 }
5996 off = iemNativeEmitGprByVCpuDisp(pbCodeBuf, off, idxReg, g_aGstShadowInfo[enmGstReg].off);
5997
5998 /* je/jz +1 */
5999 pbCodeBuf[off++] = 0x74;
6000 pbCodeBuf[off++] = 0x01;
6001
6002 /* int3 */
6003 pbCodeBuf[off++] = 0xcc;
6004
6005 /* For values smaller than the register size, we must check that the rest
6006 of the register is all zeros. */
6007 if (g_aGstShadowInfo[enmGstReg].cb < sizeof(uint32_t))
6008 {
6009 /* test reg64, imm32 */
6010 pbCodeBuf[off++] = X86_OP_REX_W | (idxReg < 8 ? 0 : X86_OP_REX_B);
6011 pbCodeBuf[off++] = 0xf7;
6012 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxReg & 7);
6013 pbCodeBuf[off++] = 0;
6014 pbCodeBuf[off++] = g_aGstShadowInfo[enmGstReg].cb > sizeof(uint8_t) ? 0 : 0xff;
6015 pbCodeBuf[off++] = 0xff;
6016 pbCodeBuf[off++] = 0xff;
6017
6018 /* je/jz +1 */
6019 pbCodeBuf[off++] = 0x74;
6020 pbCodeBuf[off++] = 0x01;
6021
6022 /* int3 */
6023 pbCodeBuf[off++] = 0xcc;
6024 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6025 }
6026 else
6027 {
6028 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6029 if (g_aGstShadowInfo[enmGstReg].cb == sizeof(uint32_t))
6030 iemNativeEmitTop32BitsClearCheck(pReNative, off, idxReg);
6031 }
6032
6033# elif defined(RT_ARCH_ARM64)
6034 /* mov TMP0, [gstreg] */
6035 off = iemNativeEmitLoadGprWithGstShadowReg(pReNative, off, IEMNATIVE_REG_FIXED_TMP0, enmGstReg);
6036
6037 uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
6038 /* sub tmp0, tmp0, idxReg */
6039 pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(true /*fSub*/, IEMNATIVE_REG_FIXED_TMP0, IEMNATIVE_REG_FIXED_TMP0, idxReg);
6040 /* cbz tmp0, +1 */
6041 pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, 2, IEMNATIVE_REG_FIXED_TMP0);
6042 /* brk #0x1000+enmGstReg */
6043 pu32CodeBuf[off++] = Armv8A64MkInstrBrk((uint32_t)enmGstReg | UINT32_C(0x1000));
6044 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6045
6046# else
6047# error "Port me!"
6048# endif
6049 return off;
6050}
6051
6052
6053# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
6054# ifdef RT_ARCH_AMD64
6055/**
6056 * Helper for AMD64 to emit code which checks the low 128-bits of the given SIMD register against the given vCPU offset.
6057 */
6058DECL_FORCE_INLINE_THROW(uint32_t) iemNativeEmitGuestSimdRegValueCheckVCpuU128(uint8_t * const pbCodeBuf, uint32_t off, uint8_t idxSimdReg, uint32_t offVCpu)
6059{
6060 /* pcmpeqq vectmp0, [gstreg] (ASSUMES SSE4.1) */
6061 pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
6062 if (idxSimdReg >= 8)
6063 pbCodeBuf[off++] = X86_OP_REX_R;
6064 pbCodeBuf[off++] = 0x0f;
6065 pbCodeBuf[off++] = 0x38;
6066 pbCodeBuf[off++] = 0x29;
6067 off = iemNativeEmitGprByVCpuDisp(pbCodeBuf, off, idxSimdReg, offVCpu);
6068
6069 /* pextrq tmp0, vectmp0, #0 (ASSUMES SSE4.1). */
6070 pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
6071 pbCodeBuf[off++] = X86_OP_REX_W
6072 | (idxSimdReg < 8 ? 0 : X86_OP_REX_R)
6073 | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
6074 pbCodeBuf[off++] = 0x0f;
6075 pbCodeBuf[off++] = 0x3a;
6076 pbCodeBuf[off++] = 0x16;
6077 pbCodeBuf[off++] = 0xeb;
6078 pbCodeBuf[off++] = 0x00;
6079
6080 /* cmp tmp0, 0xffffffffffffffff. */
6081 pbCodeBuf[off++] = X86_OP_REX_W | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
6082 pbCodeBuf[off++] = 0x83;
6083 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, IEMNATIVE_REG_FIXED_TMP0 & 7);
6084 pbCodeBuf[off++] = 0xff;
6085
6086 /* je/jz +1 */
6087 pbCodeBuf[off++] = 0x74;
6088 pbCodeBuf[off++] = 0x01;
6089
6090 /* int3 */
6091 pbCodeBuf[off++] = 0xcc;
6092
6093 /* pextrq tmp0, vectmp0, #1 (ASSUMES SSE4.1). */
6094 pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
6095 pbCodeBuf[off++] = X86_OP_REX_W
6096 | (idxSimdReg < 8 ? 0 : X86_OP_REX_R)
6097 | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
6098 pbCodeBuf[off++] = 0x0f;
6099 pbCodeBuf[off++] = 0x3a;
6100 pbCodeBuf[off++] = 0x16;
6101 pbCodeBuf[off++] = 0xeb;
6102 pbCodeBuf[off++] = 0x01;
6103
6104 /* cmp tmp0, 0xffffffffffffffff. */
6105 pbCodeBuf[off++] = X86_OP_REX_W | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
6106 pbCodeBuf[off++] = 0x83;
6107 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, IEMNATIVE_REG_FIXED_TMP0 & 7);
6108 pbCodeBuf[off++] = 0xff;
6109
6110 /* je/jz +1 */
6111 pbCodeBuf[off++] = 0x74;
6112 pbCodeBuf[off++] = 0x01;
6113
6114 /* int3 */
6115 pbCodeBuf[off++] = 0xcc;
6116
6117 return off;
6118}
6119# endif
6120
6121
6122/**
6123 * Emitting code that checks that the content of SIMD register @a idxSimdReg is the same
6124 * as what's in the guest register @a enmGstSimdReg, resulting in a breakpoint
6125 * instruction if that's not the case.
6126 *
6127 * @note May of course trash IEMNATIVE_SIMD_REG_FIXED_TMP0 and IEMNATIVE_REG_FIXED_TMP0.
6128 * Trashes EFLAGS on AMD64.
6129 */
6130DECL_HIDDEN_THROW(uint32_t)
6131iemNativeEmitGuestSimdRegValueCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxSimdReg,
6132 IEMNATIVEGSTSIMDREG enmGstSimdReg, IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz)
6133{
6134 /* We can't check the value against whats in CPUMCTX if the register is already marked as dirty, so skip the check. */
6135 if ( ( enmLoadSz == kIemNativeGstSimdRegLdStSz_256
6136 && ( IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_LO_U128(pReNative, enmGstSimdReg)
6137 || IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_HI_U128(pReNative, enmGstSimdReg)))
6138 || ( enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128
6139 && IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_LO_U128(pReNative, enmGstSimdReg))
6140 || ( enmLoadSz == kIemNativeGstSimdRegLdStSz_High128
6141 && IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_HI_U128(pReNative, enmGstSimdReg)))
6142 return off;
6143
6144# ifdef RT_ARCH_AMD64
6145 if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
6146 {
6147 /* movdqa vectmp0, idxSimdReg */
6148 off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, IEMNATIVE_SIMD_REG_FIXED_TMP0, idxSimdReg);
6149
6150 uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 44);
6151
6152 off = iemNativeEmitGuestSimdRegValueCheckVCpuU128(pbCodeBuf, off, IEMNATIVE_SIMD_REG_FIXED_TMP0,
6153 g_aGstSimdShadowInfo[enmGstSimdReg].offXmm);
6154 }
6155
6156 if (enmLoadSz == kIemNativeGstSimdRegLdStSz_High128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
6157 {
6158 /* Due to the fact that CPUMCTX stores the high 128-bit separately we need to do this all over again for the high part. */
6159 uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 50);
6160
6161 /* vextracti128 vectmp0, idxSimdReg, 1 */
6162 pbCodeBuf[off++] = X86_OP_VEX3;
6163 pbCodeBuf[off++] = (idxSimdReg < 8 ? X86_OP_VEX3_BYTE1_R : 0)
6164 | X86_OP_VEX3_BYTE1_X
6165 | (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? X86_OP_VEX3_BYTE1_B : 0)
6166 | 0x03; /* Opcode map */
6167 pbCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false /*f64BitOpSz*/, true /*f256BitAvx*/, X86_OP_VEX3_BYTE2_P_066H);
6168 pbCodeBuf[off++] = 0x39;
6169 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxSimdReg & 7, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7);
6170 pbCodeBuf[off++] = 0x01;
6171
6172 off = iemNativeEmitGuestSimdRegValueCheckVCpuU128(pbCodeBuf, off, IEMNATIVE_SIMD_REG_FIXED_TMP0,
6173 g_aGstSimdShadowInfo[enmGstSimdReg].offYmm);
6174 }
6175# elif defined(RT_ARCH_ARM64)
6176 /* mov vectmp0, [gstreg] */
6177 off = iemNativeEmitLoadSimdRegWithGstShadowSimdReg(pReNative, off, IEMNATIVE_SIMD_REG_FIXED_TMP0, enmGstSimdReg, enmLoadSz);
6178
6179 if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
6180 {
6181 uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6);
6182 /* eor vectmp0, vectmp0, idxSimdReg */
6183 pu32CodeBuf[off++] = Armv8A64MkVecInstrEor(IEMNATIVE_SIMD_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0, idxSimdReg);
6184 /* uaddlv vectmp0, vectmp0.16B */
6185 pu32CodeBuf[off++] = Armv8A64MkVecInstrUAddLV(IEMNATIVE_SIMD_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0, kArmv8InstrUAddLVSz_16B);
6186 /* umov tmp0, vectmp0.H[0] */
6187 pu32CodeBuf[off++] = Armv8A64MkVecInstrUmov(IEMNATIVE_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0,
6188 0 /*idxElem*/, kArmv8InstrUmovInsSz_U16, false /*f64Bit*/);
6189 /* cbz tmp0, +1 */
6190 pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, 2, IEMNATIVE_REG_FIXED_TMP0);
6191 /* brk #0x1000+enmGstReg */
6192 pu32CodeBuf[off++] = Armv8A64MkInstrBrk((uint32_t)enmGstSimdReg | UINT32_C(0x1000));
6193 }
6194
6195 if (enmLoadSz == kIemNativeGstSimdRegLdStSz_High128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
6196 {
6197 uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6);
6198 /* eor vectmp0 + 1, vectmp0 + 1, idxSimdReg */
6199 pu32CodeBuf[off++] = Armv8A64MkVecInstrEor(IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, idxSimdReg + 1);
6200 /* uaddlv vectmp0 + 1, (vectmp0 + 1).16B */
6201 pu32CodeBuf[off++] = Armv8A64MkVecInstrUAddLV(IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, kArmv8InstrUAddLVSz_16B);
6202 /* umov tmp0, (vectmp0 + 1).H[0] */
6203 pu32CodeBuf[off++] = Armv8A64MkVecInstrUmov(IEMNATIVE_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1,
6204 0 /*idxElem*/, kArmv8InstrUmovInsSz_U16, false /*f64Bit*/);
6205 /* cbz tmp0, +1 */
6206 pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, 2, IEMNATIVE_REG_FIXED_TMP0);
6207 /* brk #0x1000+enmGstReg */
6208 pu32CodeBuf[off++] = Armv8A64MkInstrBrk((uint32_t)enmGstSimdReg | UINT32_C(0x1000));
6209 }
6210
6211# else
6212# error "Port me!"
6213# endif
6214
6215 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6216 return off;
6217}
6218# endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
6219
6220
6221/**
6222 * Emitting code that checks that IEMCPU::fExec matches @a fExec for all
6223 * important bits.
6224 *
6225 * @note May of course trash IEMNATIVE_REG_FIXED_TMP0.
6226 * Trashes EFLAGS on AMD64.
6227 */
6228DECL_HIDDEN_THROW(uint32_t)
6229iemNativeEmitExecFlagsCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fExec)
6230{
6231 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off);
6232 off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, idxRegTmp, RT_UOFFSETOF(VMCPUCC, iem.s.fExec));
6233 off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegTmp, IEMTB_F_IEM_F_MASK & IEMTB_F_KEY_MASK);
6234 off = iemNativeEmitCmpGpr32WithImm(pReNative, off, idxRegTmp, fExec & IEMTB_F_KEY_MASK);
6235
6236#ifdef RT_ARCH_AMD64
6237 uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
6238
6239 /* je/jz +1 */
6240 pbCodeBuf[off++] = 0x74;
6241 pbCodeBuf[off++] = 0x01;
6242
6243 /* int3 */
6244 pbCodeBuf[off++] = 0xcc;
6245
6246# elif defined(RT_ARCH_ARM64)
6247 uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
6248
6249 /* b.eq +1 */
6250 pu32CodeBuf[off++] = Armv8A64MkInstrBCond(kArmv8InstrCond_Eq, 2);
6251 /* brk #0x2000 */
6252 pu32CodeBuf[off++] = Armv8A64MkInstrBrk(UINT32_C(0x2000));
6253
6254# else
6255# error "Port me!"
6256# endif
6257 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6258
6259 iemNativeRegFreeTmp(pReNative, idxRegTmp);
6260 return off;
6261}
6262
6263#endif /* VBOX_STRICT */
6264
6265
6266#ifdef IEMNATIVE_STRICT_EFLAGS_SKIPPING
6267/**
6268 * Worker for IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK.
6269 */
6270DECL_HIDDEN_THROW(uint32_t)
6271iemNativeEmitEFlagsSkippingCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fEflNeeded)
6272{
6273 uint32_t const offVCpu = RT_UOFFSETOF(VMCPU, iem.s.fSkippingEFlags);
6274
6275 fEflNeeded &= X86_EFL_STATUS_BITS;
6276 if (fEflNeeded)
6277 {
6278# ifdef RT_ARCH_AMD64
6279 /* test dword [pVCpu + offVCpu], imm32 */
6280 PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 13);
6281 if (fEflNeeded <= 0xff)
6282 {
6283 pCodeBuf[off++] = 0xf6;
6284 off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, 0, offVCpu);
6285 pCodeBuf[off++] = RT_BYTE1(fEflNeeded);
6286 }
6287 else
6288 {
6289 pCodeBuf[off++] = 0xf7;
6290 off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, 0, offVCpu);
6291 pCodeBuf[off++] = RT_BYTE1(fEflNeeded);
6292 pCodeBuf[off++] = RT_BYTE2(fEflNeeded);
6293 pCodeBuf[off++] = RT_BYTE3(fEflNeeded);
6294 pCodeBuf[off++] = RT_BYTE4(fEflNeeded);
6295 }
6296
6297 off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off + 3, kIemNativeInstrCond_e);
6298 pCodeBuf[off++] = 0xcc;
6299
6300 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6301
6302# else
6303 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off);
6304 off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, idxRegTmp, offVCpu);
6305 off = iemNativeEmitTestAnyBitsInGpr(pReNative, off, idxRegTmp, fEflNeeded);
6306# ifdef RT_ARCH_ARM64
6307 off = iemNativeEmitJzToFixed(pReNative, off, off + 2);
6308 off = iemNativeEmitBrk(pReNative, off, 0x7777);
6309# else
6310# error "Port me!"
6311# endif
6312 iemNativeRegFreeTmp(pReNative, idxRegTmp);
6313# endif
6314 }
6315 return off;
6316}
6317#endif /* IEMNATIVE_STRICT_EFLAGS_SKIPPING */
6318
6319
6320/**
6321 * Emits a code for checking the return code of a call and rcPassUp, returning
6322 * from the code if either are non-zero.
6323 */
6324DECL_HIDDEN_THROW(uint32_t)
6325iemNativeEmitCheckCallRetAndPassUp(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
6326{
6327#ifdef RT_ARCH_AMD64
6328 /*
6329 * AMD64: eax = call status code.
6330 */
6331
6332 /* edx = rcPassUp */
6333 off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, X86_GREG_xDX, RT_UOFFSETOF(VMCPUCC, iem.s.rcPassUp));
6334# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
6335 off = iemNativeEmitLoadGpr8Imm(pReNative, off, X86_GREG_xCX, idxInstr);
6336# endif
6337
6338 /* edx = eax | rcPassUp */
6339 uint8_t *pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
6340 pbCodeBuf[off++] = 0x0b; /* or edx, eax */
6341 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, X86_GREG_xDX, X86_GREG_xAX);
6342 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6343
6344 /* Jump to non-zero status return path. */
6345 off = iemNativeEmitJnzTbExit(pReNative, off, kIemNativeLabelType_NonZeroRetOrPassUp);
6346
6347 /* done. */
6348
6349#elif RT_ARCH_ARM64
6350 /*
6351 * ARM64: w0 = call status code.
6352 */
6353# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
6354 off = iemNativeEmitLoadGprImm64(pReNative, off, ARMV8_A64_REG_X2, idxInstr);
6355# endif
6356 off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, ARMV8_A64_REG_X3, RT_UOFFSETOF(VMCPUCC, iem.s.rcPassUp));
6357
6358 uint32_t *pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
6359
6360 pu32CodeBuf[off++] = Armv8A64MkInstrOrr(ARMV8_A64_REG_X4, ARMV8_A64_REG_X3, ARMV8_A64_REG_X0, false /*f64Bit*/);
6361
6362 off = iemNativeEmitTestIfGprIsNotZeroAndTbExitEx(pReNative, pu32CodeBuf, off, ARMV8_A64_REG_X4, true /*f64Bit*/,
6363 kIemNativeLabelType_NonZeroRetOrPassUp);
6364
6365#else
6366# error "port me"
6367#endif
6368 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6369 RT_NOREF_PV(idxInstr);
6370 return off;
6371}
6372
6373
6374/**
6375 * Emits a call to a CImpl function or something similar.
6376 */
6377DECL_HIDDEN_THROW(uint32_t)
6378iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, uint64_t fGstShwFlush, uintptr_t pfnCImpl,
6379 uint8_t cbInstr, uint8_t cAddParams, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6380{
6381 /* Writeback everything. */
6382 off = iemNativeRegFlushPendingWrites(pReNative, off);
6383
6384 /*
6385 * Flush stuff. PC and EFlags are implictly flushed, the latter because we
6386 * don't do with/without flags variants of defer-to-cimpl stuff at the moment.
6387 */
6388 fGstShwFlush = iemNativeCImplFlagsToGuestShadowFlushMask(pReNative->fCImpl,
6389 fGstShwFlush
6390 | RT_BIT_64(kIemNativeGstReg_Pc)
6391 | RT_BIT_64(kIemNativeGstReg_EFlags));
6392 iemNativeRegFlushGuestShadows(pReNative, fGstShwFlush);
6393
6394 off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, 4);
6395
6396 /*
6397 * Load the parameters.
6398 */
6399#if defined(RT_OS_WINDOWS) && defined(VBOXSTRICTRC_STRICT_ENABLED)
6400 /* Special code the hidden VBOXSTRICTRC pointer. */
6401 off = iemNativeEmitLoadGprFromGpr( pReNative, off, IEMNATIVE_CALL_ARG1_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
6402 off = iemNativeEmitLoadGprImm64( pReNative, off, IEMNATIVE_CALL_ARG2_GREG, cbInstr); /** @todo 8-bit reg load opt for amd64 */
6403 if (cAddParams > 0)
6404 off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG3_GREG, uParam0);
6405 if (cAddParams > 1)
6406 off = iemNativeEmitStoreImm64ByBp(pReNative, off, IEMNATIVE_FP_OFF_STACK_ARG0, uParam1);
6407 if (cAddParams > 2)
6408 off = iemNativeEmitStoreImm64ByBp(pReNative, off, IEMNATIVE_FP_OFF_STACK_ARG1, uParam2);
6409 off = iemNativeEmitLeaGprByBp(pReNative, off, X86_GREG_xCX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict */
6410
6411#else
6412 AssertCompile(IEMNATIVE_CALL_ARG_GREG_COUNT >= 4);
6413 off = iemNativeEmitLoadGprFromGpr( pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
6414 off = iemNativeEmitLoadGprImm64( pReNative, off, IEMNATIVE_CALL_ARG1_GREG, cbInstr); /** @todo 8-bit reg load opt for amd64 */
6415 if (cAddParams > 0)
6416 off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, uParam0);
6417 if (cAddParams > 1)
6418 off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG3_GREG, uParam1);
6419 if (cAddParams > 2)
6420# if IEMNATIVE_CALL_ARG_GREG_COUNT >= 5
6421 off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG4_GREG, uParam2);
6422# else
6423 off = iemNativeEmitStoreImm64ByBp(pReNative, off, IEMNATIVE_FP_OFF_STACK_ARG0, uParam2);
6424# endif
6425#endif
6426
6427 /*
6428 * Make the call.
6429 */
6430 off = iemNativeEmitCallImm(pReNative, off, pfnCImpl);
6431
6432#if defined(RT_ARCH_AMD64) && defined(VBOXSTRICTRC_STRICT_ENABLED) && defined(RT_OS_WINDOWS)
6433 off = iemNativeEmitLoadGprByBpU32(pReNative, off, X86_GREG_xAX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict (see above) */
6434#endif
6435
6436#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
6437 pReNative->Core.fDebugPcInitialized = false;
6438 Log4(("fDebugPcInitialized=false cimpl off=%#x (v2)\n", off));
6439#endif
6440
6441 /*
6442 * Check the status code.
6443 */
6444 return iemNativeEmitCheckCallRetAndPassUp(pReNative, off, idxInstr);
6445}
6446
6447
6448/**
6449 * Emits a call to a threaded worker function.
6450 */
6451DECL_HIDDEN_THROW(uint32_t)
6452iemNativeEmitThreadedCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
6453{
6454 IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK(pReNative, off, X86_EFL_STATUS_BITS);
6455
6456 /* We don't know what the threaded function is doing so we must flush all pending writes. */
6457 off = iemNativeRegFlushPendingWrites(pReNative, off);
6458
6459 iemNativeRegFlushGuestShadows(pReNative, UINT64_MAX); /** @todo optimize this */
6460 off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, 4);
6461
6462#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
6463 /* The threaded function may throw / long jmp, so set current instruction
6464 number if we're counting. */
6465 off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, pCallEntry->idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
6466#endif
6467
6468 uint8_t const cParams = g_acIemThreadedFunctionUsedArgs[pCallEntry->enmFunction];
6469
6470#ifdef RT_ARCH_AMD64
6471 /* Load the parameters and emit the call. */
6472# ifdef RT_OS_WINDOWS
6473# ifndef VBOXSTRICTRC_STRICT_ENABLED
6474 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xCX, IEMNATIVE_REG_FIXED_PVMCPU);
6475 if (cParams > 0)
6476 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_xDX, pCallEntry->auParams[0]);
6477 if (cParams > 1)
6478 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x8, pCallEntry->auParams[1]);
6479 if (cParams > 2)
6480 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x9, pCallEntry->auParams[2]);
6481# else /* VBOXSTRICTRC: Returned via hidden parameter. Sigh. */
6482 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDX, IEMNATIVE_REG_FIXED_PVMCPU);
6483 if (cParams > 0)
6484 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x8, pCallEntry->auParams[0]);
6485 if (cParams > 1)
6486 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x9, pCallEntry->auParams[1]);
6487 if (cParams > 2)
6488 {
6489 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x10, pCallEntry->auParams[2]);
6490 off = iemNativeEmitStoreGprByBp(pReNative, off, IEMNATIVE_FP_OFF_STACK_ARG0, X86_GREG_x10);
6491 }
6492 off = iemNativeEmitLeaGprByBp(pReNative, off, X86_GREG_xCX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict */
6493# endif /* VBOXSTRICTRC_STRICT_ENABLED */
6494# else
6495 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDI, IEMNATIVE_REG_FIXED_PVMCPU);
6496 if (cParams > 0)
6497 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_xSI, pCallEntry->auParams[0]);
6498 if (cParams > 1)
6499 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_xDX, pCallEntry->auParams[1]);
6500 if (cParams > 2)
6501 off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_xCX, pCallEntry->auParams[2]);
6502# endif
6503
6504 off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)g_apfnIemThreadedFunctions[pCallEntry->enmFunction]);
6505
6506# if defined(VBOXSTRICTRC_STRICT_ENABLED) && defined(RT_OS_WINDOWS)
6507 off = iemNativeEmitLoadGprByBpU32(pReNative, off, X86_GREG_xAX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict (see above) */
6508# endif
6509
6510#elif RT_ARCH_ARM64
6511 /*
6512 * ARM64:
6513 */
6514 off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
6515 if (cParams > 0)
6516 off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, pCallEntry->auParams[0]);
6517 if (cParams > 1)
6518 off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, pCallEntry->auParams[1]);
6519 if (cParams > 2)
6520 off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG3_GREG, pCallEntry->auParams[2]);
6521
6522 off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)g_apfnIemThreadedFunctions[pCallEntry->enmFunction]);
6523
6524#else
6525# error "port me"
6526#endif
6527
6528#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
6529 pReNative->Core.fDebugPcInitialized = false;
6530 Log4(("fDebugPcInitialized=false todo off=%#x (v2)\n", off));
6531#endif
6532
6533 /*
6534 * Check the status code.
6535 */
6536 off = iemNativeEmitCheckCallRetAndPassUp(pReNative, off, pCallEntry->idxInstr);
6537
6538 return off;
6539}
6540
6541#ifdef VBOX_WITH_STATISTICS
6542
6543/**
6544 * Emits code to update the thread call statistics.
6545 */
6546DECL_INLINE_THROW(uint32_t)
6547iemNativeEmitThreadCallStats(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
6548{
6549 /*
6550 * Update threaded function stats.
6551 */
6552 uint32_t const offVCpu = RT_UOFFSETOF_DYN(VMCPUCC, iem.s.acThreadedFuncStats[pCallEntry->enmFunction]);
6553 AssertCompile(sizeof(pReNative->pVCpu->iem.s.acThreadedFuncStats[pCallEntry->enmFunction]) == sizeof(uint32_t));
6554# if defined(RT_ARCH_ARM64)
6555 uint8_t const idxTmp1 = iemNativeRegAllocTmp(pReNative, &off);
6556 uint8_t const idxTmp2 = iemNativeRegAllocTmp(pReNative, &off);
6557 off = iemNativeEmitIncU32CounterInVCpu(pReNative, off, idxTmp1, idxTmp2, offVCpu);
6558 iemNativeRegFreeTmp(pReNative, idxTmp1);
6559 iemNativeRegFreeTmp(pReNative, idxTmp2);
6560# else
6561 off = iemNativeEmitIncU32CounterInVCpu(pReNative, off, UINT8_MAX, UINT8_MAX, offVCpu);
6562# endif
6563 return off;
6564}
6565
6566
6567/**
6568 * Emits code to update the TB exit reason statistics.
6569 */
6570DECL_INLINE_THROW(uint32_t)
6571iemNativeEmitNativeTbExitStats(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t const offVCpu)
6572{
6573 uint8_t const idxStatsTmp1 = iemNativeRegAllocTmp(pReNative, &off);
6574 uint8_t const idxStatsTmp2 = iemNativeRegAllocTmp(pReNative, &off);
6575 off = iemNativeEmitIncStamCounterInVCpu(pReNative, off, idxStatsTmp1, idxStatsTmp2, offVCpu);
6576 iemNativeRegFreeTmp(pReNative, idxStatsTmp1);
6577 iemNativeRegFreeTmp(pReNative, idxStatsTmp2);
6578
6579 return off;
6580}
6581
6582#endif /* VBOX_WITH_STATISTICS */
6583
6584/**
6585 * Worker for iemNativeEmitViaLookupDoOne and iemNativeRecompileAttachExecMemChunkCtx.
6586 */
6587static uint32_t
6588iemNativeEmitCoreViaLookupDoOne(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t offReturnBreak, uintptr_t pfnHelper)
6589{
6590 off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
6591 off = iemNativeEmitCallImm(pReNative, off, pfnHelper);
6592
6593 /* Jump to ReturnBreak if the return register is NULL. */
6594 off = iemNativeEmitTestIfGprIsZeroAndJmpToFixed(pReNative, off, IEMNATIVE_CALL_RET_GREG,
6595 true /*f64Bit*/, offReturnBreak);
6596
6597 /* Okay, continue executing the next TB. */
6598 off = iemNativeEmitJmpViaGpr(pReNative, off, IEMNATIVE_CALL_RET_GREG);
6599 return off;
6600}
6601
6602#ifndef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
6603
6604/**
6605 * Worker for iemNativeEmitReturnBreakViaLookup.
6606 */
6607static uint32_t iemNativeEmitViaLookupDoOne(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t offReturnBreak,
6608 IEMNATIVELABELTYPE enmLabel, uintptr_t pfnHelper)
6609{
6610 uint32_t const idxLabel = iemNativeLabelFind(pReNative, enmLabel);
6611 if (idxLabel != UINT32_MAX)
6612 {
6613 iemNativeLabelDefine(pReNative, idxLabel, off);
6614 off = iemNativeEmitCoreViaLookupDoOne(pReNative, off, offReturnBreak, pfnHelper);
6615 }
6616 return off;
6617}
6618
6619
6620/**
6621 * Emits the code at the ReturnBreakViaLookup, ReturnBreakViaLookupWithIrq,
6622 * ReturnBreakViaLookupWithTlb and ReturnBreakViaLookupWithTlbAndIrq labels
6623 * (returns VINF_IEM_REEXEC_FINISH_WITH_FLAGS or jumps to the next TB).
6624 */
6625static uint32_t iemNativeEmitReturnBreakViaLookup(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnBreakLabel)
6626{
6627 uint32_t const offReturnBreak = pReNative->paLabels[idxReturnBreakLabel].off;
6628 Assert(offReturnBreak < off);
6629
6630 /*
6631 * The lookup table index is in IEMNATIVE_CALL_ARG1_GREG for all.
6632 * The GCPhysPc is in IEMNATIVE_CALL_ARG2_GREG for ReturnBreakViaLookupWithPc.
6633 */
6634 off = iemNativeEmitViaLookupDoOne(pReNative, off, offReturnBreak, kIemNativeLabelType_ReturnBreakViaLookup,
6635 (uintptr_t)iemNativeHlpReturnBreakViaLookup<false /*a_fWithIrqCheck*/>);
6636 off = iemNativeEmitViaLookupDoOne(pReNative, off, offReturnBreak, kIemNativeLabelType_ReturnBreakViaLookupWithIrq,
6637 (uintptr_t)iemNativeHlpReturnBreakViaLookup<true /*a_fWithIrqCheck*/>);
6638 off = iemNativeEmitViaLookupDoOne(pReNative, off, offReturnBreak, kIemNativeLabelType_ReturnBreakViaLookupWithTlb,
6639 (uintptr_t)iemNativeHlpReturnBreakViaLookupWithTlb<false /*a_fWithIrqCheck*/>);
6640 off = iemNativeEmitViaLookupDoOne(pReNative, off, offReturnBreak, kIemNativeLabelType_ReturnBreakViaLookupWithTlbAndIrq,
6641 (uintptr_t)iemNativeHlpReturnBreakViaLookupWithTlb<true /*a_fWithIrqCheck*/>);
6642 return off;
6643}
6644
6645#endif /* !IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE */
6646
6647/**
6648 * Emits the code at the ReturnWithFlags label (returns VINF_IEM_REEXEC_FINISH_WITH_FLAGS).
6649 */
6650static uint32_t iemNativeEmitCoreReturnWithFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6651{
6652 /* set the return status */
6653 return iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_RET_GREG, VINF_IEM_REEXEC_FINISH_WITH_FLAGS);
6654}
6655
6656
6657#ifndef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
6658/**
6659 * Emits the code at the ReturnWithFlags label (returns VINF_IEM_REEXEC_FINISH_WITH_FLAGS).
6660 */
6661static uint32_t iemNativeEmitReturnWithFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
6662{
6663 uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_ReturnWithFlags);
6664 if (idxLabel != UINT32_MAX)
6665 {
6666 iemNativeLabelDefine(pReNative, idxLabel, off);
6667 /* set the return status */
6668 off = iemNativeEmitCoreReturnWithFlags(pReNative, off);
6669 /* jump back to the return sequence. */
6670 off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
6671 }
6672 return off;
6673}
6674#endif
6675
6676
6677/**
6678 * Emits the code at the ReturnBreakFF label (returns VINF_IEM_REEXEC_BREAK_FF).
6679 */
6680static uint32_t iemNativeEmitCoreReturnBreakFF(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6681{
6682 /* set the return status */
6683 return iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_RET_GREG, VINF_IEM_REEXEC_BREAK_FF);
6684}
6685
6686
6687#ifndef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
6688/**
6689 * Emits the code at the ReturnBreakFF label (returns VINF_IEM_REEXEC_BREAK_FF).
6690 */
6691static uint32_t iemNativeEmitReturnBreakFF(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
6692{
6693 uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_ReturnBreakFF);
6694 if (idxLabel != UINT32_MAX)
6695 {
6696 iemNativeLabelDefine(pReNative, idxLabel, off);
6697 /* set the return status */
6698 off = iemNativeEmitCoreReturnBreakFF(pReNative, off);
6699 /* jump back to the return sequence. */
6700 off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
6701 }
6702 return off;
6703}
6704#endif
6705
6706
6707/**
6708 * Emits the code at the ReturnBreak label (returns VINF_IEM_REEXEC_BREAK).
6709 */
6710static uint32_t iemNativeEmitCoreReturnBreak(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6711{
6712 /* set the return status */
6713 return iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_RET_GREG, VINF_IEM_REEXEC_BREAK);
6714}
6715
6716
6717#ifndef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
6718/**
6719 * Emits the code at the ReturnBreak label (returns VINF_IEM_REEXEC_BREAK).
6720 */
6721static uint32_t iemNativeEmitReturnBreak(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
6722{
6723 uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_ReturnBreak);
6724 if (idxLabel != UINT32_MAX)
6725 {
6726 iemNativeLabelDefine(pReNative, idxLabel, off);
6727 /* set the return status */
6728 off = iemNativeEmitCoreReturnBreak(pReNative, off);
6729 /* jump back to the return sequence. */
6730 off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
6731 }
6732 return off;
6733}
6734#endif
6735
6736
6737/**
6738 * Emits the RC fiddling code for handling non-zero return code or rcPassUp.
6739 */
6740static uint32_t iemNativeEmitCoreRcFiddling(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6741{
6742 /*
6743 * Generate the rc + rcPassUp fiddling code.
6744 */
6745 /* iemNativeHlpExecStatusCodeFiddling(PVMCPUCC pVCpu, int rc, uint8_t idxInstr) */
6746#ifdef RT_ARCH_AMD64
6747# ifdef RT_OS_WINDOWS
6748# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
6749 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_x8, X86_GREG_xCX); /* cl = instruction number */
6750# endif
6751 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xCX, IEMNATIVE_REG_FIXED_PVMCPU);
6752 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDX, X86_GREG_xAX);
6753# else
6754 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDI, IEMNATIVE_REG_FIXED_PVMCPU);
6755 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xSI, X86_GREG_xAX);
6756# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
6757 off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDX, X86_GREG_xCX); /* cl = instruction number */
6758# endif
6759# endif
6760# ifndef IEMNATIVE_WITH_INSTRUCTION_COUNTING
6761 off = iemNativeEmitLoadGpr8Imm(pReNative, off, X86_GREG_xCX, 0);
6762# endif
6763
6764#else
6765 off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, IEMNATIVE_CALL_RET_GREG);
6766 off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
6767 /* IEMNATIVE_CALL_ARG2_GREG is already set. */
6768#endif
6769
6770 off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)iemNativeHlpExecStatusCodeFiddling);
6771 return off;
6772}
6773
6774
6775#ifndef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
6776/**
6777 * Emits the RC fiddling code for handling non-zero return code or rcPassUp.
6778 */
6779static uint32_t iemNativeEmitRcFiddling(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
6780{
6781 /*
6782 * Generate the rc + rcPassUp fiddling code if needed.
6783 */
6784 uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_NonZeroRetOrPassUp);
6785 if (idxLabel != UINT32_MAX)
6786 {
6787 iemNativeLabelDefine(pReNative, idxLabel, off);
6788 off = iemNativeEmitCoreRcFiddling(pReNative, off);
6789 off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
6790 }
6791 return off;
6792}
6793#endif
6794
6795
6796/**
6797 * Emits a standard epilog.
6798 */
6799static uint32_t iemNativeEmitCoreEpilog(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6800{
6801 pReNative->Core.bmHstRegs |= RT_BIT_32(IEMNATIVE_CALL_RET_GREG); /* HACK: For IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK (return register is already set to status code). */
6802
6803 IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK(pReNative, off, X86_EFL_STATUS_BITS);
6804
6805 /* HACK: For IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK (return register is already set to status code). */
6806 pReNative->Core.bmHstRegs &= ~RT_BIT_32(IEMNATIVE_CALL_RET_GREG);
6807
6808 /*
6809 * Restore registers and return.
6810 */
6811#ifdef RT_ARCH_AMD64
6812 uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 20);
6813
6814 /* Reposition esp at the r15 restore point. */
6815 pbCodeBuf[off++] = X86_OP_REX_W;
6816 pbCodeBuf[off++] = 0x8d; /* lea rsp, [rbp - (gcc ? 5 : 7) * 8] */
6817 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM1, X86_GREG_xSP, X86_GREG_xBP);
6818 pbCodeBuf[off++] = (uint8_t)IEMNATIVE_FP_OFF_LAST_PUSH;
6819
6820 /* Pop non-volatile registers and return */
6821 pbCodeBuf[off++] = X86_OP_REX_B; /* pop r15 */
6822 pbCodeBuf[off++] = 0x58 + X86_GREG_x15 - 8;
6823 pbCodeBuf[off++] = X86_OP_REX_B; /* pop r14 */
6824 pbCodeBuf[off++] = 0x58 + X86_GREG_x14 - 8;
6825 pbCodeBuf[off++] = X86_OP_REX_B; /* pop r13 */
6826 pbCodeBuf[off++] = 0x58 + X86_GREG_x13 - 8;
6827 pbCodeBuf[off++] = X86_OP_REX_B; /* pop r12 */
6828 pbCodeBuf[off++] = 0x58 + X86_GREG_x12 - 8;
6829# ifdef RT_OS_WINDOWS
6830 pbCodeBuf[off++] = 0x58 + X86_GREG_xDI; /* pop rdi */
6831 pbCodeBuf[off++] = 0x58 + X86_GREG_xSI; /* pop rsi */
6832# endif
6833 pbCodeBuf[off++] = 0x58 + X86_GREG_xBX; /* pop rbx */
6834 pbCodeBuf[off++] = 0xc9; /* leave */
6835 pbCodeBuf[off++] = 0xc3; /* ret */
6836 pbCodeBuf[off++] = 0xcc; /* int3 poison */
6837
6838#elif RT_ARCH_ARM64
6839 uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 10);
6840
6841 /* ldp x19, x20, [sp #IEMNATIVE_FRAME_VAR_SIZE]! ; Unallocate the variable space and restore x19+x20. */
6842 AssertCompile(IEMNATIVE_FRAME_VAR_SIZE < 64*8);
6843 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_PreIndex,
6844 ARMV8_A64_REG_X19, ARMV8_A64_REG_X20, ARMV8_A64_REG_SP,
6845 IEMNATIVE_FRAME_VAR_SIZE / 8);
6846 /* Restore x21 thru x28 + BP and LR (ret address) (SP remains unchanged in the kSigned variant). */
6847 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6848 ARMV8_A64_REG_X21, ARMV8_A64_REG_X22, ARMV8_A64_REG_SP, 2);
6849 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6850 ARMV8_A64_REG_X23, ARMV8_A64_REG_X24, ARMV8_A64_REG_SP, 4);
6851 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6852 ARMV8_A64_REG_X25, ARMV8_A64_REG_X26, ARMV8_A64_REG_SP, 6);
6853 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6854 ARMV8_A64_REG_X27, ARMV8_A64_REG_X28, ARMV8_A64_REG_SP, 8);
6855 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6856 ARMV8_A64_REG_BP, ARMV8_A64_REG_LR, ARMV8_A64_REG_SP, 10);
6857 AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE / 8 == 12);
6858
6859 /* add sp, sp, IEMNATIVE_FRAME_SAVE_REG_SIZE ; */
6860 AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE < 4096);
6861 pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /*fSub*/, ARMV8_A64_REG_SP, ARMV8_A64_REG_SP,
6862 IEMNATIVE_FRAME_SAVE_REG_SIZE);
6863
6864 /* retab / ret */
6865# ifdef RT_OS_DARWIN /** @todo See todo on pacibsp in the prolog. */
6866 if (1)
6867 pu32CodeBuf[off++] = ARMV8_A64_INSTR_RETAB;
6868 else
6869# endif
6870 pu32CodeBuf[off++] = ARMV8_A64_INSTR_RET;
6871
6872#else
6873# error "port me"
6874#endif
6875 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6876
6877 /* HACK: For IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK. */
6878 pReNative->Core.bmHstRegs &= ~RT_BIT_32(IEMNATIVE_CALL_RET_GREG);
6879
6880 return off;
6881}
6882
6883
6884#ifndef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
6885/**
6886 * Emits a standard epilog.
6887 */
6888static uint32_t iemNativeEmitEpilog(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t *pidxReturnLabel)
6889{
6890 /*
6891 * Define label for common return point.
6892 */
6893 *pidxReturnLabel = UINT32_MAX;
6894 uint32_t const idxReturn = iemNativeLabelCreate(pReNative, kIemNativeLabelType_Return, off);
6895 *pidxReturnLabel = idxReturn;
6896
6897 /*
6898 * Emit the code.
6899 */
6900 return iemNativeEmitCoreEpilog(pReNative, off);
6901}
6902#endif
6903
6904
6905#ifndef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON
6906/**
6907 * Emits a standard prolog.
6908 */
6909static uint32_t iemNativeEmitProlog(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6910{
6911#ifdef RT_ARCH_AMD64
6912 /*
6913 * Set up a regular xBP stack frame, pushing all non-volatile GPRs,
6914 * reserving 64 bytes for stack variables plus 4 non-register argument
6915 * slots. Fixed register assignment: xBX = pReNative;
6916 *
6917 * Since we always do the same register spilling, we can use the same
6918 * unwind description for all the code.
6919 */
6920 uint8_t *const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
6921 pbCodeBuf[off++] = 0x50 + X86_GREG_xBP; /* push rbp */
6922 pbCodeBuf[off++] = X86_OP_REX_W; /* mov rbp, rsp */
6923 pbCodeBuf[off++] = 0x8b;
6924 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, X86_GREG_xBP, X86_GREG_xSP);
6925 pbCodeBuf[off++] = 0x50 + X86_GREG_xBX; /* push rbx */
6926 AssertCompile(IEMNATIVE_REG_FIXED_PVMCPU == X86_GREG_xBX);
6927# ifdef RT_OS_WINDOWS
6928 pbCodeBuf[off++] = X86_OP_REX_W; /* mov rbx, rcx ; RBX = pVCpu */
6929 pbCodeBuf[off++] = 0x8b;
6930 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, X86_GREG_xBX, X86_GREG_xCX);
6931 pbCodeBuf[off++] = 0x50 + X86_GREG_xSI; /* push rsi */
6932 pbCodeBuf[off++] = 0x50 + X86_GREG_xDI; /* push rdi */
6933# else
6934 pbCodeBuf[off++] = X86_OP_REX_W; /* mov rbx, rdi ; RBX = pVCpu */
6935 pbCodeBuf[off++] = 0x8b;
6936 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, X86_GREG_xBX, X86_GREG_xDI);
6937# endif
6938 pbCodeBuf[off++] = X86_OP_REX_B; /* push r12 */
6939 pbCodeBuf[off++] = 0x50 + X86_GREG_x12 - 8;
6940 pbCodeBuf[off++] = X86_OP_REX_B; /* push r13 */
6941 pbCodeBuf[off++] = 0x50 + X86_GREG_x13 - 8;
6942 pbCodeBuf[off++] = X86_OP_REX_B; /* push r14 */
6943 pbCodeBuf[off++] = 0x50 + X86_GREG_x14 - 8;
6944 pbCodeBuf[off++] = X86_OP_REX_B; /* push r15 */
6945 pbCodeBuf[off++] = 0x50 + X86_GREG_x15 - 8;
6946
6947# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
6948 /* Save the frame pointer. */
6949 off = iemNativeEmitStoreGprToVCpuU64Ex(pbCodeBuf, off, X86_GREG_xBP, RT_UOFFSETOF(VMCPUCC, iem.s.pvTbFramePointerR3));
6950# endif
6951
6952 off = iemNativeEmitSubGprImm(pReNative, off, /* sub rsp, byte 28h */
6953 X86_GREG_xSP,
6954 IEMNATIVE_FRAME_ALIGN_SIZE
6955 + IEMNATIVE_FRAME_VAR_SIZE
6956 + IEMNATIVE_FRAME_STACK_ARG_COUNT * 8
6957 + IEMNATIVE_FRAME_SHADOW_ARG_COUNT * 8);
6958 AssertCompile(!(IEMNATIVE_FRAME_VAR_SIZE & 0xf));
6959 AssertCompile(!(IEMNATIVE_FRAME_STACK_ARG_COUNT & 0x1));
6960 AssertCompile(!(IEMNATIVE_FRAME_SHADOW_ARG_COUNT & 0x1));
6961
6962#elif RT_ARCH_ARM64
6963 /*
6964 * We set up a stack frame exactly like on x86, only we have to push the
6965 * return address our selves here. We save all non-volatile registers.
6966 */
6967 uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 16);
6968
6969# ifdef RT_OS_DARWIN /** @todo This seems to be requirement by libunwind for JIT FDEs. Investigate further as been unable
6970 * to figure out where the BRK following AUTHB*+XPACB* stuff comes from in libunwind. It's
6971 * definitely the dwarf stepping code, but till found it's very tedious to figure out whether it's
6972 * in any way conditional, so just emitting this instructions now and hoping for the best... */
6973 /* pacibsp */
6974 pu32CodeBuf[off++] = ARMV8_A64_INSTR_PACIBSP;
6975# endif
6976
6977 /* stp x19, x20, [sp, #-IEMNATIVE_FRAME_SAVE_REG_SIZE] ; Allocate space for saving registers and place x19+x20 at the bottom. */
6978 AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE < 64*8);
6979 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_PreIndex,
6980 ARMV8_A64_REG_X19, ARMV8_A64_REG_X20, ARMV8_A64_REG_SP,
6981 -IEMNATIVE_FRAME_SAVE_REG_SIZE / 8);
6982 /* Save x21 thru x28 (SP remains unchanged in the kSigned variant). */
6983 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6984 ARMV8_A64_REG_X21, ARMV8_A64_REG_X22, ARMV8_A64_REG_SP, 2);
6985 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6986 ARMV8_A64_REG_X23, ARMV8_A64_REG_X24, ARMV8_A64_REG_SP, 4);
6987 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6988 ARMV8_A64_REG_X25, ARMV8_A64_REG_X26, ARMV8_A64_REG_SP, 6);
6989 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6990 ARMV8_A64_REG_X27, ARMV8_A64_REG_X28, ARMV8_A64_REG_SP, 8);
6991 /* Save the BP and LR (ret address) registers at the top of the frame. */
6992 pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /*fLoad*/, 2 /*64-bit*/, kArm64InstrStLdPairType_Signed,
6993 ARMV8_A64_REG_BP, ARMV8_A64_REG_LR, ARMV8_A64_REG_SP, 10);
6994 AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE / 8 == 12);
6995 /* add bp, sp, IEMNATIVE_FRAME_SAVE_REG_SIZE - 16 ; Set BP to point to the old BP stack address. */
6996 pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /*fSub*/, ARMV8_A64_REG_BP,
6997 ARMV8_A64_REG_SP, IEMNATIVE_FRAME_SAVE_REG_SIZE - 16);
6998
6999 /* sub sp, sp, IEMNATIVE_FRAME_VAR_SIZE ; Allocate the variable area from SP. */
7000 pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_SP, ARMV8_A64_REG_SP, IEMNATIVE_FRAME_VAR_SIZE);
7001
7002 /* mov r28, r0 */
7003 off = iemNativeEmitLoadGprFromGprEx(pu32CodeBuf, off, IEMNATIVE_REG_FIXED_PVMCPU, IEMNATIVE_CALL_ARG0_GREG);
7004 /* mov r27, r1 */
7005 off = iemNativeEmitLoadGprFromGprEx(pu32CodeBuf, off, IEMNATIVE_REG_FIXED_PCPUMCTX, IEMNATIVE_CALL_ARG1_GREG);
7006
7007# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
7008 /* Save the frame pointer. */
7009 off = iemNativeEmitStoreGprToVCpuU64Ex(pu32CodeBuf, off, ARMV8_A64_REG_BP, RT_UOFFSETOF(VMCPUCC, iem.s.pvTbFramePointerR3),
7010 ARMV8_A64_REG_X2);
7011# endif
7012
7013#else
7014# error "port me"
7015#endif
7016 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
7017 return off;
7018}
7019#endif
7020
7021
7022/*********************************************************************************************************************************
7023* Emitters for IEM_MC_ARG_XXX, IEM_MC_LOCAL, IEM_MC_LOCAL_CONST, ++ *
7024*********************************************************************************************************************************/
7025
7026/**
7027 * Internal work that allocates a variable with kind set to
7028 * kIemNativeVarKind_Invalid and no current stack allocation.
7029 *
7030 * The kind will either be set by the caller or later when the variable is first
7031 * assigned a value.
7032 *
7033 * @returns Unpacked index.
7034 * @internal
7035 */
7036static uint8_t iemNativeVarAllocInt(PIEMRECOMPILERSTATE pReNative, uint8_t cbType)
7037{
7038 Assert(cbType > 0 && cbType <= 64);
7039 unsigned const idxVar = ASMBitFirstSetU32(~pReNative->Core.bmVars) - 1;
7040 AssertStmt(idxVar < RT_ELEMENTS(pReNative->Core.aVars), IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_EXHAUSTED));
7041 pReNative->Core.bmVars |= RT_BIT_32(idxVar);
7042 pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_Invalid;
7043 pReNative->Core.aVars[idxVar].cbVar = cbType;
7044 pReNative->Core.aVars[idxVar].idxStackSlot = UINT8_MAX;
7045 pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
7046 pReNative->Core.aVars[idxVar].uArgNo = UINT8_MAX;
7047 pReNative->Core.aVars[idxVar].idxReferrerVar = UINT8_MAX;
7048 pReNative->Core.aVars[idxVar].enmGstReg = kIemNativeGstReg_End;
7049 pReNative->Core.aVars[idxVar].fRegAcquired = false;
7050 pReNative->Core.aVars[idxVar].u.uValue = 0;
7051#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
7052 pReNative->Core.aVars[idxVar].fSimdReg = false;
7053#endif
7054 return idxVar;
7055}
7056
7057
7058/**
7059 * Internal work that allocates an argument variable w/o setting enmKind.
7060 *
7061 * @returns Unpacked index.
7062 * @internal
7063 */
7064static uint8_t iemNativeArgAllocInt(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType)
7065{
7066 iArgNo += iemNativeArgGetHiddenArgCount(pReNative);
7067 AssertStmt(iArgNo < RT_ELEMENTS(pReNative->Core.aidxArgVars), IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_1));
7068 AssertStmt(pReNative->Core.aidxArgVars[iArgNo] == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_DUP_ARG_NO));
7069
7070 uint8_t const idxVar = iemNativeVarAllocInt(pReNative, cbType);
7071 pReNative->Core.aidxArgVars[iArgNo] = idxVar; /* (unpacked) */
7072 pReNative->Core.aVars[idxVar].uArgNo = iArgNo;
7073 return idxVar;
7074}
7075
7076
7077/**
7078 * Gets the stack slot for a stack variable, allocating one if necessary.
7079 *
7080 * Calling this function implies that the stack slot will contain a valid
7081 * variable value. The caller deals with any register currently assigned to the
7082 * variable, typically by spilling it into the stack slot.
7083 *
7084 * @returns The stack slot number.
7085 * @param pReNative The recompiler state.
7086 * @param idxVar The variable.
7087 * @throws VERR_IEM_VAR_OUT_OF_STACK_SLOTS
7088 */
7089DECL_HIDDEN_THROW(uint8_t) iemNativeVarGetStackSlot(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
7090{
7091 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7092 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
7093 Assert(pVar->enmKind == kIemNativeVarKind_Stack);
7094
7095 /* Already got a slot? */
7096 uint8_t const idxStackSlot = pVar->idxStackSlot;
7097 if (idxStackSlot != UINT8_MAX)
7098 {
7099 Assert(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS);
7100 return idxStackSlot;
7101 }
7102
7103 /*
7104 * A single slot is easy to allocate.
7105 * Allocate them from the top end, closest to BP, to reduce the displacement.
7106 */
7107 if (pVar->cbVar <= sizeof(uint64_t))
7108 {
7109 unsigned const iSlot = ASMBitLastSetU32(~pReNative->Core.bmStack) - 1;
7110 AssertStmt(iSlot < IEMNATIVE_FRAME_VAR_SLOTS, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_OUT_OF_STACK_SLOTS));
7111 pReNative->Core.bmStack |= RT_BIT_32(iSlot);
7112 pVar->idxStackSlot = (uint8_t)iSlot;
7113 Log11(("iemNativeVarGetStackSlot: idxVar=%#x iSlot=%#x\n", idxVar, iSlot));
7114 return (uint8_t)iSlot;
7115 }
7116
7117 /*
7118 * We need more than one stack slot.
7119 *
7120 * cbVar -> fBitAlignMask: 16 -> 1; 32 -> 3; 64 -> 7;
7121 */
7122 AssertCompile(RT_IS_POWER_OF_TWO(IEMNATIVE_FRAME_VAR_SLOTS)); /* If not we have to add an overflow check. */
7123 Assert(pVar->cbVar <= 64);
7124 uint32_t const fBitAlignMask = RT_BIT_32(ASMBitLastSetU32(pVar->cbVar) - 4) - 1;
7125 uint32_t fBitAllocMask = RT_BIT_32((pVar->cbVar + 7) >> 3) - 1;
7126 uint32_t bmStack = pReNative->Core.bmStack;
7127 while (bmStack != UINT32_MAX)
7128 {
7129 unsigned iSlot = ASMBitLastSetU32(~bmStack);
7130 AssertStmt(iSlot, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_OUT_OF_STACK_SLOTS));
7131 iSlot = (iSlot - 1) & ~fBitAlignMask;
7132 if ((bmStack & ~(fBitAllocMask << iSlot)) == bmStack)
7133 {
7134 pReNative->Core.bmStack |= (fBitAllocMask << iSlot);
7135 pVar->idxStackSlot = (uint8_t)iSlot;
7136 Log11(("iemNativeVarGetStackSlot: idxVar=%#x iSlot=%#x/%#x (cbVar=%#x)\n",
7137 idxVar, iSlot, fBitAllocMask, pVar->cbVar));
7138 return (uint8_t)iSlot;
7139 }
7140
7141 bmStack |= (fBitAllocMask << iSlot);
7142 }
7143 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_OUT_OF_STACK_SLOTS));
7144}
7145
7146
7147/**
7148 * Changes the variable to a stack variable.
7149 *
7150 * Currently this is s only possible to do the first time the variable is used,
7151 * switching later is can be implemented but not done.
7152 *
7153 * @param pReNative The recompiler state.
7154 * @param idxVar The variable.
7155 * @throws VERR_IEM_VAR_IPE_2
7156 */
7157DECL_HIDDEN_THROW(void) iemNativeVarSetKindToStack(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
7158{
7159 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7160 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
7161 if (pVar->enmKind != kIemNativeVarKind_Stack)
7162 {
7163 /* We could in theory transition from immediate to stack as well, but it
7164 would involve the caller doing work storing the value on the stack. So,
7165 till that's required we only allow transition from invalid. */
7166 AssertStmt(pVar->enmKind == kIemNativeVarKind_Invalid, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7167 AssertStmt(pVar->idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7168 pVar->enmKind = kIemNativeVarKind_Stack;
7169
7170 /* Note! We don't allocate a stack slot here, that's only done when a
7171 slot is actually needed to hold a variable value. */
7172 }
7173}
7174
7175
7176/**
7177 * Sets it to a variable with a constant value.
7178 *
7179 * This does not require stack storage as we know the value and can always
7180 * reload it, unless of course it's referenced.
7181 *
7182 * @param pReNative The recompiler state.
7183 * @param idxVar The variable.
7184 * @param uValue The immediate value.
7185 * @throws VERR_IEM_VAR_OUT_OF_STACK_SLOTS, VERR_IEM_VAR_IPE_2
7186 */
7187DECL_HIDDEN_THROW(void) iemNativeVarSetKindToConst(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint64_t uValue)
7188{
7189 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7190 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
7191 if (pVar->enmKind != kIemNativeVarKind_Immediate)
7192 {
7193 /* Only simple transitions for now. */
7194 AssertStmt(pVar->enmKind == kIemNativeVarKind_Invalid, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7195 pVar->enmKind = kIemNativeVarKind_Immediate;
7196 }
7197 AssertStmt(pVar->idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7198
7199 pVar->u.uValue = uValue;
7200 AssertMsg( pVar->cbVar >= sizeof(uint64_t)
7201 || pVar->u.uValue < RT_BIT_64(pVar->cbVar * 8),
7202 ("idxVar=%d cbVar=%u uValue=%#RX64\n", idxVar, pVar->cbVar, uValue));
7203}
7204
7205
7206/**
7207 * Sets the variable to a reference (pointer) to @a idxOtherVar.
7208 *
7209 * This does not require stack storage as we know the value and can always
7210 * reload it. Loading is postponed till needed.
7211 *
7212 * @param pReNative The recompiler state.
7213 * @param idxVar The variable. Unpacked.
7214 * @param idxOtherVar The variable to take the (stack) address of. Unpacked.
7215 *
7216 * @throws VERR_IEM_VAR_OUT_OF_STACK_SLOTS, VERR_IEM_VAR_IPE_2
7217 * @internal
7218 */
7219static void iemNativeVarSetKindToLocalRef(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint8_t idxOtherVar)
7220{
7221 Assert(idxVar < RT_ELEMENTS(pReNative->Core.aVars) && (pReNative->Core.bmVars & RT_BIT_32(idxVar)));
7222 Assert(idxOtherVar < RT_ELEMENTS(pReNative->Core.aVars) && (pReNative->Core.bmVars & RT_BIT_32(idxOtherVar)));
7223
7224 if (pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_VarRef)
7225 {
7226 /* Only simple transitions for now. */
7227 AssertStmt(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Invalid,
7228 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7229 pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_VarRef;
7230 }
7231 AssertStmt(pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7232
7233 pReNative->Core.aVars[idxVar].u.idxRefVar = idxOtherVar; /* unpacked */
7234
7235 /* Update the other variable, ensure it's a stack variable. */
7236 /** @todo handle variables with const values... that'll go boom now. */
7237 pReNative->Core.aVars[idxOtherVar].idxReferrerVar = idxVar;
7238 iemNativeVarSetKindToStack(pReNative, IEMNATIVE_VAR_IDX_PACK(idxOtherVar));
7239}
7240
7241
7242/**
7243 * Sets the variable to a reference (pointer) to a guest register reference.
7244 *
7245 * This does not require stack storage as we know the value and can always
7246 * reload it. Loading is postponed till needed.
7247 *
7248 * @param pReNative The recompiler state.
7249 * @param idxVar The variable.
7250 * @param enmRegClass The class guest registers to reference.
7251 * @param idxReg The register within @a enmRegClass to reference.
7252 *
7253 * @throws VERR_IEM_VAR_IPE_2
7254 */
7255DECL_HIDDEN_THROW(void) iemNativeVarSetKindToGstRegRef(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
7256 IEMNATIVEGSTREGREF enmRegClass, uint8_t idxReg)
7257{
7258 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7259 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
7260
7261 if (pVar->enmKind != kIemNativeVarKind_GstRegRef)
7262 {
7263 /* Only simple transitions for now. */
7264 AssertStmt(pVar->enmKind == kIemNativeVarKind_Invalid, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7265 pVar->enmKind = kIemNativeVarKind_GstRegRef;
7266 }
7267 AssertStmt(pVar->idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7268
7269 pVar->u.GstRegRef.enmClass = enmRegClass;
7270 pVar->u.GstRegRef.idx = idxReg;
7271}
7272
7273
7274DECL_HIDDEN_THROW(uint8_t) iemNativeArgAlloc(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType)
7275{
7276 return IEMNATIVE_VAR_IDX_PACK(iemNativeArgAllocInt(pReNative, iArgNo, cbType));
7277}
7278
7279
7280DECL_HIDDEN_THROW(uint8_t) iemNativeArgAllocConst(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType, uint64_t uValue)
7281{
7282 uint8_t const idxVar = IEMNATIVE_VAR_IDX_PACK(iemNativeArgAllocInt(pReNative, iArgNo, cbType));
7283
7284 /* Since we're using a generic uint64_t value type, we must truncate it if
7285 the variable is smaller otherwise we may end up with too large value when
7286 scaling up a imm8 w/ sign-extension.
7287
7288 This caused trouble with a "add bx, 0xffff" instruction (around f000:ac60
7289 in the bios, bx=1) when running on arm, because clang expect 16-bit
7290 register parameters to have bits 16 and up set to zero. Instead of
7291 setting x1 = 0xffff we ended up with x1 = 0xffffffffffffff and the wrong
7292 CF value in the result. */
7293 switch (cbType)
7294 {
7295 case sizeof(uint8_t): uValue &= UINT64_C(0xff); break;
7296 case sizeof(uint16_t): uValue &= UINT64_C(0xffff); break;
7297 case sizeof(uint32_t): uValue &= UINT64_C(0xffffffff); break;
7298 }
7299 iemNativeVarSetKindToConst(pReNative, idxVar, uValue);
7300 return idxVar;
7301}
7302
7303
7304DECL_HIDDEN_THROW(uint8_t) iemNativeArgAllocLocalRef(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t idxOtherVar)
7305{
7306 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxOtherVar);
7307 idxOtherVar = IEMNATIVE_VAR_IDX_UNPACK(idxOtherVar);
7308 AssertStmt( idxOtherVar < RT_ELEMENTS(pReNative->Core.aVars)
7309 && (pReNative->Core.bmVars & RT_BIT_32(idxOtherVar))
7310 && pReNative->Core.aVars[idxOtherVar].uArgNo == UINT8_MAX,
7311 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_1));
7312
7313 uint8_t const idxArgVar = iemNativeArgAlloc(pReNative, iArgNo, sizeof(uintptr_t));
7314 iemNativeVarSetKindToLocalRef(pReNative, IEMNATIVE_VAR_IDX_UNPACK(idxArgVar), idxOtherVar);
7315 return idxArgVar;
7316}
7317
7318
7319DECL_HIDDEN_THROW(uint8_t) iemNativeVarAlloc(PIEMRECOMPILERSTATE pReNative, uint8_t cbType)
7320{
7321 uint8_t const idxVar = IEMNATIVE_VAR_IDX_PACK(iemNativeVarAllocInt(pReNative, cbType));
7322 /* Don't set to stack now, leave that to the first use as for instance
7323 IEM_MC_CALC_RM_EFF_ADDR may produce a const/immediate result (esp. in DOS). */
7324 return idxVar;
7325}
7326
7327
7328DECL_HIDDEN_THROW(uint8_t) iemNativeVarAllocConst(PIEMRECOMPILERSTATE pReNative, uint8_t cbType, uint64_t uValue)
7329{
7330 uint8_t const idxVar = IEMNATIVE_VAR_IDX_PACK(iemNativeVarAllocInt(pReNative, cbType));
7331
7332 /* Since we're using a generic uint64_t value type, we must truncate it if
7333 the variable is smaller otherwise we may end up with too large value when
7334 scaling up a imm8 w/ sign-extension. */
7335 switch (cbType)
7336 {
7337 case sizeof(uint8_t): uValue &= UINT64_C(0xff); break;
7338 case sizeof(uint16_t): uValue &= UINT64_C(0xffff); break;
7339 case sizeof(uint32_t): uValue &= UINT64_C(0xffffffff); break;
7340 }
7341 iemNativeVarSetKindToConst(pReNative, idxVar, uValue);
7342 return idxVar;
7343}
7344
7345
7346DECL_HIDDEN_THROW(uint8_t) iemNativeVarAllocAssign(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t cbType, uint8_t idxVarOther)
7347{
7348 uint8_t const idxVar = IEMNATIVE_VAR_IDX_PACK(iemNativeVarAllocInt(pReNative, cbType));
7349 iemNativeVarSetKindToStack(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
7350
7351 uint8_t const idxVarOtherReg = iemNativeVarRegisterAcquire(pReNative, idxVarOther, poff, true /*fInitialized*/);
7352 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxVar, poff);
7353
7354 *poff = iemNativeEmitLoadGprFromGpr(pReNative, *poff, idxVarReg, idxVarOtherReg);
7355
7356 /* Truncate the value to this variables size. */
7357 switch (cbType)
7358 {
7359 case sizeof(uint8_t): *poff = iemNativeEmitAndGpr32ByImm(pReNative, *poff, idxVarReg, UINT64_C(0xff)); break;
7360 case sizeof(uint16_t): *poff = iemNativeEmitAndGpr32ByImm(pReNative, *poff, idxVarReg, UINT64_C(0xffff)); break;
7361 case sizeof(uint32_t): *poff = iemNativeEmitAndGpr32ByImm(pReNative, *poff, idxVarReg, UINT64_C(0xffffffff)); break;
7362 }
7363
7364 iemNativeVarRegisterRelease(pReNative, idxVarOther);
7365 iemNativeVarRegisterRelease(pReNative, idxVar);
7366 return idxVar;
7367}
7368
7369
7370/**
7371 * Makes sure variable @a idxVar has a register assigned to it and that it stays
7372 * fixed till we call iemNativeVarRegisterRelease.
7373 *
7374 * @returns The host register number.
7375 * @param pReNative The recompiler state.
7376 * @param idxVar The variable.
7377 * @param poff Pointer to the instruction buffer offset.
7378 * In case a register needs to be freed up or the value
7379 * loaded off the stack.
7380 * @param fInitialized Set if the variable must already have been initialized.
7381 * Will throw VERR_IEM_VAR_NOT_INITIALIZED if this is not
7382 * the case.
7383 * @param idxRegPref Preferred register number or UINT8_MAX.
7384 */
7385DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
7386 bool fInitialized /*= false*/, uint8_t idxRegPref /*= UINT8_MAX*/)
7387{
7388 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7389 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
7390 Assert(pVar->cbVar <= 8);
7391 Assert(!pVar->fRegAcquired);
7392
7393 uint8_t idxReg = pVar->idxReg;
7394 if (idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
7395 {
7396 Assert( pVar->enmKind > kIemNativeVarKind_Invalid
7397 && pVar->enmKind < kIemNativeVarKind_End);
7398 pVar->fRegAcquired = true;
7399 return idxReg;
7400 }
7401
7402 /*
7403 * If the kind of variable has not yet been set, default to 'stack'.
7404 */
7405 Assert( pVar->enmKind >= kIemNativeVarKind_Invalid
7406 && pVar->enmKind < kIemNativeVarKind_End);
7407 if (pVar->enmKind == kIemNativeVarKind_Invalid)
7408 iemNativeVarSetKindToStack(pReNative, idxVar);
7409
7410 /*
7411 * We have to allocate a register for the variable, even if its a stack one
7412 * as we don't know if there are modification being made to it before its
7413 * finalized (todo: analyze and insert hints about that?).
7414 *
7415 * If we can, we try get the correct register for argument variables. This
7416 * is assuming that most argument variables are fetched as close as possible
7417 * to the actual call, so that there aren't any interfering hidden calls
7418 * (memory accesses, etc) inbetween.
7419 *
7420 * If we cannot or it's a variable, we make sure no argument registers
7421 * that will be used by this MC block will be allocated here, and we always
7422 * prefer non-volatile registers to avoid needing to spill stuff for internal
7423 * call.
7424 */
7425 /** @todo Detect too early argument value fetches and warn about hidden
7426 * calls causing less optimal code to be generated in the python script. */
7427
7428 uint8_t const uArgNo = pVar->uArgNo;
7429 if ( uArgNo < RT_ELEMENTS(g_aidxIemNativeCallRegs)
7430 && !(pReNative->Core.bmHstRegs & RT_BIT_32(g_aidxIemNativeCallRegs[uArgNo])))
7431 {
7432 idxReg = g_aidxIemNativeCallRegs[uArgNo];
7433
7434#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
7435 /* Writeback any dirty shadow registers we are about to unshadow. */
7436 *poff = iemNativeRegFlushDirtyGuestByHostRegShadow(pReNative, *poff, idxReg);
7437#endif
7438
7439 iemNativeRegClearGstRegShadowing(pReNative, idxReg, *poff);
7440 Log11(("iemNativeVarRegisterAcquire: idxVar=%#x idxReg=%u (matching arg %u)\n", idxVar, idxReg, uArgNo));
7441 }
7442 else if ( idxRegPref >= RT_ELEMENTS(pReNative->Core.aHstRegs)
7443 || (pReNative->Core.bmHstRegs & RT_BIT_32(idxRegPref)))
7444 {
7445 /** @todo there must be a better way for this and boot cArgsX? */
7446 uint32_t const fNotArgsMask = ~g_afIemNativeCallRegs[RT_MIN(pReNative->cArgsX, IEMNATIVE_CALL_ARG_GREG_COUNT)];
7447 uint32_t const fRegs = ~pReNative->Core.bmHstRegs
7448 & ~pReNative->Core.bmHstRegsWithGstShadow
7449 & (~IEMNATIVE_REG_FIXED_MASK & IEMNATIVE_HST_GREG_MASK)
7450 & fNotArgsMask;
7451 if (fRegs)
7452 {
7453 /* Pick from the top as that both arm64 and amd64 have a block of non-volatile registers there. */
7454 idxReg = (uint8_t)ASMBitLastSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
7455 ? fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
7456 Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
7457 Assert(!(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg)));
7458 Log11(("iemNativeVarRegisterAcquire: idxVar=%#x idxReg=%u (uArgNo=%u)\n", idxVar, idxReg, uArgNo));
7459 }
7460 else
7461 {
7462 idxReg = iemNativeRegAllocFindFree(pReNative, poff, false /*fPreferVolatile*/,
7463 IEMNATIVE_HST_GREG_MASK & ~IEMNATIVE_REG_FIXED_MASK & fNotArgsMask);
7464 AssertStmt(idxReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_VAR));
7465 Log11(("iemNativeVarRegisterAcquire: idxVar=%#x idxReg=%u (slow, uArgNo=%u)\n", idxVar, idxReg, uArgNo));
7466 }
7467 }
7468 else
7469 {
7470 idxReg = idxRegPref;
7471 iemNativeRegClearGstRegShadowing(pReNative, idxReg, *poff);
7472 Log11(("iemNativeVarRegisterAcquire: idxVar=%#x idxReg=%u (preferred)\n", idxVar, idxReg));
7473 }
7474 iemNativeRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Var, idxVar);
7475 pVar->idxReg = idxReg;
7476
7477#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
7478 pVar->fSimdReg = false;
7479#endif
7480
7481 /*
7482 * Load it off the stack if we've got a stack slot.
7483 */
7484 uint8_t const idxStackSlot = pVar->idxStackSlot;
7485 if (idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS)
7486 {
7487 Assert(fInitialized);
7488 int32_t const offDispBp = iemNativeStackCalcBpDisp(idxStackSlot);
7489 switch (pVar->cbVar)
7490 {
7491 case 1: *poff = iemNativeEmitLoadGprByBpU8( pReNative, *poff, idxReg, offDispBp); break;
7492 case 2: *poff = iemNativeEmitLoadGprByBpU16(pReNative, *poff, idxReg, offDispBp); break;
7493 case 3: AssertFailed(); RT_FALL_THRU();
7494 case 4: *poff = iemNativeEmitLoadGprByBpU32(pReNative, *poff, idxReg, offDispBp); break;
7495 default: AssertFailed(); RT_FALL_THRU();
7496 case 8: *poff = iemNativeEmitLoadGprByBp( pReNative, *poff, idxReg, offDispBp); break;
7497 }
7498 }
7499 else
7500 {
7501 Assert(idxStackSlot == UINT8_MAX);
7502 if (pVar->enmKind != kIemNativeVarKind_Immediate)
7503 AssertStmt(!fInitialized, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
7504 else
7505 {
7506 /*
7507 * Convert from immediate to stack/register. This is currently only
7508 * required by IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR, IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR
7509 * and IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR in connection with BT, BTS, BTR, and BTC.
7510 */
7511 AssertStmt(fInitialized, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
7512 Log11(("iemNativeVarRegisterAcquire: idxVar=%#x idxReg=%u uValue=%RX64 converting from immediate to stack\n",
7513 idxVar, idxReg, pVar->u.uValue));
7514 *poff = iemNativeEmitLoadGprImm64(pReNative, *poff, idxReg, pVar->u.uValue);
7515 pVar->enmKind = kIemNativeVarKind_Stack;
7516 }
7517 }
7518
7519 pVar->fRegAcquired = true;
7520 return idxReg;
7521}
7522
7523
7524#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
7525/**
7526 * Makes sure variable @a idxVar has a SIMD register assigned to it and that it stays
7527 * fixed till we call iemNativeVarRegisterRelease.
7528 *
7529 * @returns The host register number.
7530 * @param pReNative The recompiler state.
7531 * @param idxVar The variable.
7532 * @param poff Pointer to the instruction buffer offset.
7533 * In case a register needs to be freed up or the value
7534 * loaded off the stack.
7535 * @param fInitialized Set if the variable must already have been initialized.
7536 * Will throw VERR_IEM_VAR_NOT_INITIALIZED if this is not
7537 * the case.
7538 * @param idxRegPref Preferred SIMD register number or UINT8_MAX.
7539 */
7540DECL_HIDDEN_THROW(uint8_t) iemNativeVarSimdRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
7541 bool fInitialized /*= false*/, uint8_t idxRegPref /*= UINT8_MAX*/)
7542{
7543 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7544 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
7545 Assert( pVar->cbVar == sizeof(RTUINT128U)
7546 || pVar->cbVar == sizeof(RTUINT256U));
7547 Assert(!pVar->fRegAcquired);
7548
7549 uint8_t idxReg = pVar->idxReg;
7550 if (idxReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs))
7551 {
7552 Assert( pVar->enmKind > kIemNativeVarKind_Invalid
7553 && pVar->enmKind < kIemNativeVarKind_End);
7554 pVar->fRegAcquired = true;
7555 return idxReg;
7556 }
7557
7558 /*
7559 * If the kind of variable has not yet been set, default to 'stack'.
7560 */
7561 Assert( pVar->enmKind >= kIemNativeVarKind_Invalid
7562 && pVar->enmKind < kIemNativeVarKind_End);
7563 if (pVar->enmKind == kIemNativeVarKind_Invalid)
7564 iemNativeVarSetKindToStack(pReNative, idxVar);
7565
7566 /*
7567 * We have to allocate a register for the variable, even if its a stack one
7568 * as we don't know if there are modification being made to it before its
7569 * finalized (todo: analyze and insert hints about that?).
7570 *
7571 * If we can, we try get the correct register for argument variables. This
7572 * is assuming that most argument variables are fetched as close as possible
7573 * to the actual call, so that there aren't any interfering hidden calls
7574 * (memory accesses, etc) inbetween.
7575 *
7576 * If we cannot or it's a variable, we make sure no argument registers
7577 * that will be used by this MC block will be allocated here, and we always
7578 * prefer non-volatile registers to avoid needing to spill stuff for internal
7579 * call.
7580 */
7581 /** @todo Detect too early argument value fetches and warn about hidden
7582 * calls causing less optimal code to be generated in the python script. */
7583
7584 uint8_t const uArgNo = pVar->uArgNo;
7585 Assert(uArgNo == UINT8_MAX); RT_NOREF(uArgNo); /* No SIMD registers as arguments for now. */
7586
7587 /* SIMD is bit simpler for now because there is no support for arguments. */
7588 if ( idxRegPref >= RT_ELEMENTS(pReNative->Core.aHstSimdRegs)
7589 || (pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxRegPref)))
7590 {
7591 uint32_t const fNotArgsMask = UINT32_MAX; //~g_afIemNativeCallRegs[RT_MIN(pReNative->cArgs, IEMNATIVE_CALL_ARG_GREG_COUNT)];
7592 uint32_t const fRegs = ~pReNative->Core.bmHstSimdRegs
7593 & ~pReNative->Core.bmHstSimdRegsWithGstShadow
7594 & (~IEMNATIVE_SIMD_REG_FIXED_MASK & IEMNATIVE_HST_SIMD_REG_MASK)
7595 & fNotArgsMask;
7596 if (fRegs)
7597 {
7598 idxReg = (uint8_t)ASMBitLastSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK
7599 ? fRegs & ~IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK : fRegs) - 1;
7600 Assert(pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows == 0);
7601 Assert(!(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxReg)));
7602 Log11(("iemNativeVarSimdRegisterAcquire: idxVar=%#x idxReg=%u (uArgNo=%u)\n", idxVar, idxReg, uArgNo));
7603 }
7604 else
7605 {
7606 idxReg = iemNativeSimdRegAllocFindFree(pReNative, poff, false /*fPreferVolatile*/,
7607 IEMNATIVE_HST_SIMD_REG_MASK & ~IEMNATIVE_SIMD_REG_FIXED_MASK & fNotArgsMask);
7608 AssertStmt(idxReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_VAR));
7609 Log11(("iemNativeVarSimdRegisterAcquire: idxVar=%#x idxReg=%u (slow, uArgNo=%u)\n", idxVar, idxReg, uArgNo));
7610 }
7611 }
7612 else
7613 {
7614 idxReg = idxRegPref;
7615 AssertReleaseFailed(); //iemNativeRegClearGstRegShadowing(pReNative, idxReg, *poff);
7616 Log11(("iemNativeVarSimdRegisterAcquire: idxVar=%#x idxReg=%u (preferred)\n", idxVar, idxReg));
7617 }
7618 iemNativeSimdRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Var, idxVar);
7619
7620 pVar->fSimdReg = true;
7621 pVar->idxReg = idxReg;
7622
7623 /*
7624 * Load it off the stack if we've got a stack slot.
7625 */
7626 uint8_t const idxStackSlot = pVar->idxStackSlot;
7627 if (idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS)
7628 {
7629 Assert(fInitialized);
7630 int32_t const offDispBp = iemNativeStackCalcBpDisp(idxStackSlot);
7631 switch (pVar->cbVar)
7632 {
7633 case sizeof(RTUINT128U): *poff = iemNativeEmitLoadVecRegByBpU128(pReNative, *poff, idxReg, offDispBp); break;
7634 default: AssertFailed(); RT_FALL_THRU();
7635 case sizeof(RTUINT256U): *poff = iemNativeEmitLoadVecRegByBpU256(pReNative, *poff, idxReg, offDispBp); break;
7636 }
7637 }
7638 else
7639 {
7640 Assert(idxStackSlot == UINT8_MAX);
7641 AssertStmt(!fInitialized, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
7642 }
7643 pVar->fRegAcquired = true;
7644 return idxReg;
7645}
7646#endif
7647
7648
7649/**
7650 * The value of variable @a idxVar will be written in full to the @a enmGstReg
7651 * guest register.
7652 *
7653 * This function makes sure there is a register for it and sets it to be the
7654 * current shadow copy of @a enmGstReg.
7655 *
7656 * @returns The host register number.
7657 * @param pReNative The recompiler state.
7658 * @param idxVar The variable.
7659 * @param enmGstReg The guest register this variable will be written to
7660 * after this call.
7661 * @param poff Pointer to the instruction buffer offset.
7662 * In case a register needs to be freed up or if the
7663 * variable content needs to be loaded off the stack.
7664 *
7665 * @note We DO NOT expect @a idxVar to be an argument variable,
7666 * because we can only in the commit stage of an instruction when this
7667 * function is used.
7668 */
7669DECL_HIDDEN_THROW(uint8_t)
7670iemNativeVarRegisterAcquireForGuestReg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, IEMNATIVEGSTREG enmGstReg, uint32_t *poff)
7671{
7672 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7673 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
7674 Assert(!pVar->fRegAcquired);
7675 AssertMsgStmt( pVar->cbVar <= 8
7676 && ( pVar->enmKind == kIemNativeVarKind_Immediate
7677 || pVar->enmKind == kIemNativeVarKind_Stack),
7678 ("idxVar=%#x cbVar=%d enmKind=%d enmGstReg=%s\n", idxVar, pVar->cbVar,
7679 pVar->enmKind, g_aGstShadowInfo[enmGstReg].pszName),
7680 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_6));
7681
7682 /*
7683 * This shouldn't ever be used for arguments, unless it's in a weird else
7684 * branch that doesn't do any calling and even then it's questionable.
7685 *
7686 * However, in case someone writes crazy wrong MC code and does register
7687 * updates before making calls, just use the regular register allocator to
7688 * ensure we get a register suitable for the intended argument number.
7689 */
7690 AssertStmt(pVar->uArgNo == UINT8_MAX, iemNativeVarRegisterAcquire(pReNative, idxVar, poff));
7691
7692 /*
7693 * If there is already a register for the variable, we transfer/set the
7694 * guest shadow copy assignment to it.
7695 */
7696 uint8_t idxReg = pVar->idxReg;
7697 if (idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
7698 {
7699#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
7700 if (enmGstReg >= kIemNativeGstReg_GprFirst && enmGstReg <= kIemNativeGstReg_GprLast)
7701 {
7702# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
7703 iemNativeDbgInfoAddNativeOffset(pReNative, *poff);
7704 iemNativeDbgInfoAddGuestRegDirty(pReNative, false /*fSimdReg*/, enmGstReg, idxReg);
7705# endif
7706 pReNative->Core.bmGstRegShadowDirty |= RT_BIT_64(enmGstReg);
7707 }
7708#endif
7709
7710 if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
7711 {
7712 uint8_t const idxRegOld = pReNative->Core.aidxGstRegShadows[enmGstReg];
7713 iemNativeRegTransferGstRegShadowing(pReNative, idxRegOld, idxReg, enmGstReg, *poff);
7714 Log12(("iemNativeVarRegisterAcquireForGuestReg: Moved %s for guest %s into %s for full write\n",
7715 g_apszIemNativeHstRegNames[idxRegOld], g_aGstShadowInfo[enmGstReg].pszName, g_apszIemNativeHstRegNames[idxReg]));
7716 }
7717 else
7718 {
7719 iemNativeRegMarkAsGstRegShadow(pReNative, idxReg, enmGstReg, *poff);
7720 Log12(("iemNativeVarRegisterAcquireForGuestReg: Marking %s as copy of guest %s (full write)\n",
7721 g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName));
7722 }
7723 /** @todo figure this one out. We need some way of making sure the register isn't
7724 * modified after this point, just in case we start writing crappy MC code. */
7725 pVar->enmGstReg = enmGstReg;
7726 pVar->fRegAcquired = true;
7727 return idxReg;
7728 }
7729 Assert(pVar->uArgNo == UINT8_MAX);
7730
7731 /*
7732 * Because this is supposed to be the commit stage, we're just tag along with the
7733 * temporary register allocator and upgrade it to a variable register.
7734 */
7735 idxReg = iemNativeRegAllocTmpForGuestReg(pReNative, poff, enmGstReg, kIemNativeGstRegUse_ForFullWrite);
7736 Assert(pReNative->Core.aHstRegs[idxReg].enmWhat == kIemNativeWhat_Tmp);
7737 Assert(pReNative->Core.aHstRegs[idxReg].idxVar == UINT8_MAX);
7738 pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Var;
7739 pReNative->Core.aHstRegs[idxReg].idxVar = idxVar;
7740 pVar->idxReg = idxReg;
7741
7742 /*
7743 * Now we need to load the register value.
7744 */
7745 if (pVar->enmKind == kIemNativeVarKind_Immediate)
7746 *poff = iemNativeEmitLoadGprImm64(pReNative, *poff, idxReg, pVar->u.uValue);
7747 else
7748 {
7749 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
7750 int32_t const offDispBp = iemNativeStackCalcBpDisp(idxStackSlot);
7751 switch (pVar->cbVar)
7752 {
7753 case sizeof(uint64_t):
7754 *poff = iemNativeEmitLoadGprByBp(pReNative, *poff, idxReg, offDispBp);
7755 break;
7756 case sizeof(uint32_t):
7757 *poff = iemNativeEmitLoadGprByBpU32(pReNative, *poff, idxReg, offDispBp);
7758 break;
7759 case sizeof(uint16_t):
7760 *poff = iemNativeEmitLoadGprByBpU16(pReNative, *poff, idxReg, offDispBp);
7761 break;
7762 case sizeof(uint8_t):
7763 *poff = iemNativeEmitLoadGprByBpU8(pReNative, *poff, idxReg, offDispBp);
7764 break;
7765 default:
7766 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_6));
7767 }
7768 }
7769
7770 pVar->fRegAcquired = true;
7771 return idxReg;
7772}
7773
7774
7775/**
7776 * Emit code to save volatile registers prior to a call to a helper (TLB miss).
7777 *
7778 * This is used together with iemNativeVarRestoreVolatileRegsPostHlpCall() and
7779 * optionally iemNativeRegRestoreGuestShadowsInVolatileRegs() to bypass the
7780 * requirement of flushing anything in volatile host registers when making a
7781 * call.
7782 *
7783 * @returns New @a off value.
7784 * @param pReNative The recompiler state.
7785 * @param off The code buffer position.
7786 * @param fHstRegsNotToSave Set of registers not to save & restore.
7787 */
7788DECL_HIDDEN_THROW(uint32_t)
7789iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstRegsNotToSave)
7790{
7791 uint32_t fHstRegs = pReNative->Core.bmHstRegs & IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK & ~fHstRegsNotToSave;
7792 if (fHstRegs)
7793 {
7794 do
7795 {
7796 unsigned int const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
7797 fHstRegs &= ~RT_BIT_32(idxHstReg);
7798
7799 if (pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Var)
7800 {
7801 uint8_t const idxVar = pReNative->Core.aHstRegs[idxHstReg].idxVar;
7802 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7803 AssertStmt( IEMNATIVE_VAR_IDX_UNPACK(idxVar) < RT_ELEMENTS(pReNative->Core.aVars)
7804 && (pReNative->Core.bmVars & RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(idxVar)))
7805 && pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxHstReg,
7806 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_12));
7807 switch (pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].enmKind)
7808 {
7809 case kIemNativeVarKind_Stack:
7810 {
7811 /* Temporarily spill the variable register. */
7812 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
7813 Log12(("iemNativeVarSaveVolatileRegsPreHlpCall: spilling idxVar=%#x/idxReg=%d onto the stack (slot %#x bp+%d, off=%#x)\n",
7814 idxVar, idxHstReg, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
7815 off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxHstReg);
7816 continue;
7817 }
7818
7819 case kIemNativeVarKind_Immediate:
7820 case kIemNativeVarKind_VarRef:
7821 case kIemNativeVarKind_GstRegRef:
7822 /* It is weird to have any of these loaded at this point. */
7823 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_13));
7824 continue;
7825
7826 case kIemNativeVarKind_End:
7827 case kIemNativeVarKind_Invalid:
7828 break;
7829 }
7830 AssertFailed();
7831 }
7832 else
7833 {
7834 /*
7835 * Allocate a temporary stack slot and spill the register to it.
7836 */
7837 unsigned const idxStackSlot = ASMBitLastSetU32(~pReNative->Core.bmStack) - 1;
7838 AssertStmt(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS,
7839 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_OUT_OF_STACK_SLOTS));
7840 pReNative->Core.bmStack |= RT_BIT_32(idxStackSlot);
7841 pReNative->Core.aHstRegs[idxHstReg].idxStackSlot = (uint8_t)idxStackSlot;
7842 Log12(("iemNativeVarSaveVolatileRegsPreHlpCall: spilling idxReg=%d onto the stack (slot %#x bp+%d, off=%#x)\n",
7843 idxHstReg, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
7844 off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxHstReg);
7845 }
7846 } while (fHstRegs);
7847 }
7848#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
7849
7850 /*
7851 * Guest register shadows are flushed to CPUMCTX at the moment and don't need allocating a stack slot
7852 * which would be more difficult due to spanning multiple stack slots and different sizes
7853 * (besides we only have a limited amount of slots at the moment).
7854 *
7855 * However the shadows need to be flushed out as the guest SIMD register might get corrupted by
7856 * the callee. This asserts that the registers were written back earlier and are not in the dirty state.
7857 */
7858 iemNativeSimdRegFlushGuestShadowsByHostMask(pReNative, IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK);
7859
7860 fHstRegs = pReNative->Core.bmHstSimdRegs & IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK;
7861 if (fHstRegs)
7862 {
7863 do
7864 {
7865 unsigned int const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
7866 fHstRegs &= ~RT_BIT_32(idxHstReg);
7867
7868 /* Fixed reserved and temporary registers don't need saving. */
7869 if ( pReNative->Core.aHstSimdRegs[idxHstReg].enmWhat == kIemNativeWhat_FixedReserved
7870 || pReNative->Core.aHstSimdRegs[idxHstReg].enmWhat == kIemNativeWhat_FixedTmp)
7871 continue;
7872
7873 Assert(pReNative->Core.aHstSimdRegs[idxHstReg].enmWhat == kIemNativeWhat_Var);
7874
7875 uint8_t const idxVar = pReNative->Core.aHstSimdRegs[idxHstReg].idxVar;
7876 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7877 AssertStmt( IEMNATIVE_VAR_IDX_UNPACK(idxVar) < RT_ELEMENTS(pReNative->Core.aVars)
7878 && (pReNative->Core.bmVars & RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(idxVar)))
7879 && pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxHstReg
7880 && pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg
7881 && ( pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].cbVar == sizeof(RTUINT128U)
7882 || pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].cbVar == sizeof(RTUINT256U)),
7883 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_12));
7884 switch (pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].enmKind)
7885 {
7886 case kIemNativeVarKind_Stack:
7887 {
7888 /* Temporarily spill the variable register. */
7889 uint8_t const cbVar = pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].cbVar;
7890 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
7891 Log12(("iemNativeVarSaveVolatileRegsPreHlpCall: spilling idxVar=%#x/idxReg=%d onto the stack (slot %#x bp+%d, off=%#x)\n",
7892 idxVar, idxHstReg, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
7893 if (cbVar == sizeof(RTUINT128U))
7894 off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxHstReg);
7895 else
7896 off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxHstReg);
7897 continue;
7898 }
7899
7900 case kIemNativeVarKind_Immediate:
7901 case kIemNativeVarKind_VarRef:
7902 case kIemNativeVarKind_GstRegRef:
7903 /* It is weird to have any of these loaded at this point. */
7904 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_13));
7905 continue;
7906
7907 case kIemNativeVarKind_End:
7908 case kIemNativeVarKind_Invalid:
7909 break;
7910 }
7911 AssertFailed();
7912 } while (fHstRegs);
7913 }
7914#endif
7915 return off;
7916}
7917
7918
7919/**
7920 * Emit code to restore volatile registers after to a call to a helper.
7921 *
7922 * @returns New @a off value.
7923 * @param pReNative The recompiler state.
7924 * @param off The code buffer position.
7925 * @param fHstRegsNotToSave Set of registers not to save & restore.
7926 * @see iemNativeVarSaveVolatileRegsPreHlpCall(),
7927 * iemNativeRegRestoreGuestShadowsInVolatileRegs()
7928 */
7929DECL_HIDDEN_THROW(uint32_t)
7930iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstRegsNotToSave)
7931{
7932 uint32_t fHstRegs = pReNative->Core.bmHstRegs & IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK & ~fHstRegsNotToSave;
7933 if (fHstRegs)
7934 {
7935 do
7936 {
7937 unsigned int const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
7938 fHstRegs &= ~RT_BIT_32(idxHstReg);
7939
7940 if (pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Var)
7941 {
7942 uint8_t const idxVar = pReNative->Core.aHstRegs[idxHstReg].idxVar;
7943 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7944 AssertStmt( IEMNATIVE_VAR_IDX_UNPACK(idxVar) < RT_ELEMENTS(pReNative->Core.aVars)
7945 && (pReNative->Core.bmVars & RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(idxVar)))
7946 && pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxHstReg,
7947 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_12));
7948 switch (pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].enmKind)
7949 {
7950 case kIemNativeVarKind_Stack:
7951 {
7952 /* Unspill the variable register. */
7953 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
7954 Log12(("iemNativeVarRestoreVolatileRegsPostHlpCall: unspilling idxVar=%#x/idxReg=%d (slot %#x bp+%d, off=%#x)\n",
7955 idxVar, idxHstReg, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
7956 off = iemNativeEmitLoadGprByBp(pReNative, off, idxHstReg, iemNativeStackCalcBpDisp(idxStackSlot));
7957 continue;
7958 }
7959
7960 case kIemNativeVarKind_Immediate:
7961 case kIemNativeVarKind_VarRef:
7962 case kIemNativeVarKind_GstRegRef:
7963 /* It is weird to have any of these loaded at this point. */
7964 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_13));
7965 continue;
7966
7967 case kIemNativeVarKind_End:
7968 case kIemNativeVarKind_Invalid:
7969 break;
7970 }
7971 AssertFailed();
7972 }
7973 else
7974 {
7975 /*
7976 * Restore from temporary stack slot.
7977 */
7978 uint8_t const idxStackSlot = pReNative->Core.aHstRegs[idxHstReg].idxStackSlot;
7979 AssertContinue(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS && (pReNative->Core.bmStack & RT_BIT_32(idxStackSlot)));
7980 pReNative->Core.bmStack &= ~RT_BIT_32(idxStackSlot);
7981 pReNative->Core.aHstRegs[idxHstReg].idxStackSlot = UINT8_MAX;
7982
7983 off = iemNativeEmitLoadGprByBp(pReNative, off, idxHstReg, iemNativeStackCalcBpDisp(idxStackSlot));
7984 }
7985 } while (fHstRegs);
7986 }
7987#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
7988 fHstRegs = pReNative->Core.bmHstSimdRegs & IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK;
7989 if (fHstRegs)
7990 {
7991 do
7992 {
7993 unsigned int const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
7994 fHstRegs &= ~RT_BIT_32(idxHstReg);
7995
7996 if ( pReNative->Core.aHstSimdRegs[idxHstReg].enmWhat == kIemNativeWhat_FixedTmp
7997 || pReNative->Core.aHstSimdRegs[idxHstReg].enmWhat == kIemNativeWhat_FixedReserved)
7998 continue;
7999 Assert(pReNative->Core.aHstSimdRegs[idxHstReg].enmWhat == kIemNativeWhat_Var);
8000
8001 uint8_t const idxVar = pReNative->Core.aHstSimdRegs[idxHstReg].idxVar;
8002 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
8003 AssertStmt( IEMNATIVE_VAR_IDX_UNPACK(idxVar) < RT_ELEMENTS(pReNative->Core.aVars)
8004 && (pReNative->Core.bmVars & RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(idxVar)))
8005 && pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxHstReg
8006 && pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg
8007 && ( pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].cbVar == sizeof(RTUINT128U)
8008 || pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].cbVar == sizeof(RTUINT256U)),
8009 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_12));
8010 switch (pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].enmKind)
8011 {
8012 case kIemNativeVarKind_Stack:
8013 {
8014 /* Unspill the variable register. */
8015 uint8_t const cbVar = pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].cbVar;
8016 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
8017 Log12(("iemNativeVarRestoreVolatileRegsPostHlpCall: unspilling idxVar=%#x/idxReg=%d (slot %#x bp+%d, off=%#x)\n",
8018 idxVar, idxHstReg, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
8019
8020 if (cbVar == sizeof(RTUINT128U))
8021 off = iemNativeEmitLoadVecRegByBpU128(pReNative, off, idxHstReg, iemNativeStackCalcBpDisp(idxStackSlot));
8022 else
8023 off = iemNativeEmitLoadVecRegByBpU256(pReNative, off, idxHstReg, iemNativeStackCalcBpDisp(idxStackSlot));
8024 continue;
8025 }
8026
8027 case kIemNativeVarKind_Immediate:
8028 case kIemNativeVarKind_VarRef:
8029 case kIemNativeVarKind_GstRegRef:
8030 /* It is weird to have any of these loaded at this point. */
8031 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_13));
8032 continue;
8033
8034 case kIemNativeVarKind_End:
8035 case kIemNativeVarKind_Invalid:
8036 break;
8037 }
8038 AssertFailed();
8039 } while (fHstRegs);
8040 }
8041#endif
8042 return off;
8043}
8044
8045
8046/**
8047 * Worker that frees the stack slots for variable @a idxVar if any allocated.
8048 *
8049 * This is used both by iemNativeVarFreeOneWorker and iemNativeEmitCallCommon.
8050 *
8051 * ASSUMES that @a idxVar is valid and unpacked.
8052 */
8053DECL_FORCE_INLINE(void) iemNativeVarFreeStackSlots(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
8054{
8055 Assert(idxVar < RT_ELEMENTS(pReNative->Core.aVars)); /* unpacked! */
8056 uint8_t const idxStackSlot = pReNative->Core.aVars[idxVar].idxStackSlot;
8057 if (idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS)
8058 {
8059 uint8_t const cbVar = pReNative->Core.aVars[idxVar].cbVar;
8060 uint8_t const cSlots = (cbVar + sizeof(uint64_t) - 1) / sizeof(uint64_t);
8061 uint32_t const fAllocMask = (uint32_t)(RT_BIT_32(cSlots) - 1U);
8062 Assert(cSlots > 0);
8063 Assert(((pReNative->Core.bmStack >> idxStackSlot) & fAllocMask) == fAllocMask);
8064 Log11(("iemNativeVarFreeStackSlots: idxVar=%d/%#x iSlot=%#x/%#x (cbVar=%#x)\n",
8065 idxVar, IEMNATIVE_VAR_IDX_PACK(idxVar), idxStackSlot, fAllocMask, cbVar));
8066 pReNative->Core.bmStack &= ~(fAllocMask << idxStackSlot);
8067 pReNative->Core.aVars[idxVar].idxStackSlot = UINT8_MAX;
8068 }
8069 else
8070 Assert(idxStackSlot == UINT8_MAX);
8071}
8072
8073
8074/**
8075 * Worker that frees a single variable.
8076 *
8077 * ASSUMES that @a idxVar is valid and unpacked.
8078 */
8079DECLHIDDEN(void) iemNativeVarFreeOneWorker(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
8080{
8081 Assert( pReNative->Core.aVars[idxVar].enmKind >= kIemNativeVarKind_Invalid /* Including invalid as we may have unused */
8082 && pReNative->Core.aVars[idxVar].enmKind < kIemNativeVarKind_End); /* variables in conditional branches. */
8083 Assert(!pReNative->Core.aVars[idxVar].fRegAcquired);
8084
8085 /* Free the host register first if any assigned. */
8086 uint8_t const idxHstReg = pReNative->Core.aVars[idxVar].idxReg;
8087#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
8088 if ( idxHstReg != UINT8_MAX
8089 && pReNative->Core.aVars[idxVar].fSimdReg)
8090 {
8091 Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
8092 Assert(pReNative->Core.aHstSimdRegs[idxHstReg].idxVar == IEMNATIVE_VAR_IDX_PACK(idxVar));
8093 pReNative->Core.aHstSimdRegs[idxHstReg].idxVar = UINT8_MAX;
8094 pReNative->Core.bmHstSimdRegs &= ~RT_BIT_32(idxHstReg);
8095 }
8096 else
8097#endif
8098 if (idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
8099 {
8100 Assert(pReNative->Core.aHstRegs[idxHstReg].idxVar == IEMNATIVE_VAR_IDX_PACK(idxVar));
8101 pReNative->Core.aHstRegs[idxHstReg].idxVar = UINT8_MAX;
8102 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
8103 }
8104
8105 /* Free argument mapping. */
8106 uint8_t const uArgNo = pReNative->Core.aVars[idxVar].uArgNo;
8107 if (uArgNo < RT_ELEMENTS(pReNative->Core.aidxArgVars))
8108 pReNative->Core.aidxArgVars[uArgNo] = UINT8_MAX;
8109
8110 /* Free the stack slots. */
8111 iemNativeVarFreeStackSlots(pReNative, idxVar);
8112
8113 /* Free the actual variable. */
8114 pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_Invalid;
8115 pReNative->Core.bmVars &= ~RT_BIT_32(idxVar);
8116}
8117
8118
8119/**
8120 * Worker for iemNativeVarFreeAll that's called when there is anything to do.
8121 */
8122DECLHIDDEN(void) iemNativeVarFreeAllSlow(PIEMRECOMPILERSTATE pReNative, uint32_t bmVars)
8123{
8124 while (bmVars != 0)
8125 {
8126 uint8_t const idxVar = ASMBitFirstSetU32(bmVars) - 1;
8127 bmVars &= ~RT_BIT_32(idxVar);
8128
8129#if 1 /** @todo optimize by simplifying this later... */
8130 iemNativeVarFreeOneWorker(pReNative, idxVar);
8131#else
8132 /* Only need to free the host register, the rest is done as bulk updates below. */
8133 uint8_t const idxHstReg = pReNative->Core.aVars[idxVar].idxReg;
8134 if (idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
8135 {
8136 Assert(pReNative->Core.aHstRegs[idxHstReg].idxVar == IEMNATIVE_VAR_IDX_PACK(idxVar));
8137 pReNative->Core.aHstRegs[idxHstReg].idxVar = UINT8_MAX;
8138 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
8139 }
8140#endif
8141 }
8142#if 0 /** @todo optimize by simplifying this later... */
8143 pReNative->Core.bmVars = 0;
8144 pReNative->Core.bmStack = 0;
8145 pReNative->Core.u64ArgVars = UINT64_MAX;
8146#endif
8147}
8148
8149
8150
8151/*********************************************************************************************************************************
8152* Emitters for IEM_MC_CALL_CIMPL_XXX *
8153*********************************************************************************************************************************/
8154
8155/**
8156 * Emits code to load a reference to the given guest register into @a idxGprDst.
8157 */
8158DECL_HIDDEN_THROW(uint32_t)
8159iemNativeEmitLeaGprByGstRegRef(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxGprDst,
8160 IEMNATIVEGSTREGREF enmClass, uint8_t idxRegInClass)
8161{
8162#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
8163 /** @todo If we ever gonna allow referencing the RIP register we need to update guest value here. */
8164#endif
8165
8166 /*
8167 * Get the offset relative to the CPUMCTX structure.
8168 */
8169 uint32_t offCpumCtx;
8170 switch (enmClass)
8171 {
8172 case kIemNativeGstRegRef_Gpr:
8173 Assert(idxRegInClass < 16);
8174 offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, aGRegs[idxRegInClass]);
8175 break;
8176
8177 case kIemNativeGstRegRef_GprHighByte: /**< AH, CH, DH, BH*/
8178 Assert(idxRegInClass < 4);
8179 offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, aGRegs[0].bHi) + idxRegInClass * sizeof(CPUMCTXGREG);
8180 break;
8181
8182 case kIemNativeGstRegRef_EFlags:
8183 Assert(idxRegInClass == 0);
8184 offCpumCtx = RT_UOFFSETOF(CPUMCTX, eflags);
8185 break;
8186
8187 case kIemNativeGstRegRef_MxCsr:
8188 Assert(idxRegInClass == 0);
8189 offCpumCtx = RT_UOFFSETOF(CPUMCTX, XState.x87.MXCSR);
8190 break;
8191
8192 case kIemNativeGstRegRef_FpuReg:
8193 Assert(idxRegInClass < 8);
8194 AssertFailed(); /** @todo what kind of indexing? */
8195 offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, XState.x87.aRegs[idxRegInClass]);
8196 break;
8197
8198 case kIemNativeGstRegRef_MReg:
8199 Assert(idxRegInClass < 8);
8200 AssertFailed(); /** @todo what kind of indexing? */
8201 offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, XState.x87.aRegs[idxRegInClass]);
8202 break;
8203
8204 case kIemNativeGstRegRef_XReg:
8205 Assert(idxRegInClass < 16);
8206 offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, XState.x87.aXMM[idxRegInClass]);
8207 break;
8208
8209 case kIemNativeGstRegRef_X87: /* Not a register actually but we would just duplicate code otherwise. */
8210 Assert(idxRegInClass == 0);
8211 offCpumCtx = RT_UOFFSETOF(CPUMCTX, XState.x87);
8212 break;
8213
8214 case kIemNativeGstRegRef_XState: /* Not a register actually but we would just duplicate code otherwise. */
8215 Assert(idxRegInClass == 0);
8216 offCpumCtx = RT_UOFFSETOF(CPUMCTX, XState);
8217 break;
8218
8219 default:
8220 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_5));
8221 }
8222
8223 /*
8224 * Load the value into the destination register.
8225 */
8226#ifdef RT_ARCH_AMD64
8227 off = iemNativeEmitLeaGprByVCpu(pReNative, off, idxGprDst, offCpumCtx + RT_UOFFSETOF(VMCPUCC, cpum.GstCtx));
8228
8229#elif defined(RT_ARCH_ARM64)
8230 uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
8231 Assert(offCpumCtx < 4096);
8232 pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /*fSub*/, idxGprDst, IEMNATIVE_REG_FIXED_PCPUMCTX, offCpumCtx);
8233
8234#else
8235# error "Port me!"
8236#endif
8237
8238 return off;
8239}
8240
8241
8242/**
8243 * Common code for CIMPL and AIMPL calls.
8244 *
8245 * These are calls that uses argument variables and such. They should not be
8246 * confused with internal calls required to implement an MC operation,
8247 * like a TLB load and similar.
8248 *
8249 * Upon return all that is left to do is to load any hidden arguments and
8250 * perform the call. All argument variables are freed.
8251 *
8252 * @returns New code buffer offset; throws VBox status code on error.
8253 * @param pReNative The native recompile state.
8254 * @param off The code buffer offset.
8255 * @param cArgs The total nubmer of arguments (includes hidden
8256 * count).
8257 * @param cHiddenArgs The number of hidden arguments. The hidden
8258 * arguments must not have any variable declared for
8259 * them, whereas all the regular arguments must
8260 * (tstIEMCheckMc ensures this).
8261 * @param fFlushPendingWrites Flag whether to flush pending writes (default true),
8262 * this will still flush pending writes in call volatile registers if false.
8263 */
8264DECL_HIDDEN_THROW(uint32_t)
8265iemNativeEmitCallCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs, uint8_t cHiddenArgs,
8266 bool fFlushPendingWrites /*= true*/)
8267{
8268#ifdef VBOX_STRICT
8269 /*
8270 * Assert sanity.
8271 */
8272 Assert(cArgs <= IEMNATIVE_CALL_MAX_ARG_COUNT);
8273 Assert(cHiddenArgs < IEMNATIVE_CALL_ARG_GREG_COUNT);
8274 for (unsigned i = 0; i < cHiddenArgs; i++)
8275 Assert(pReNative->Core.aidxArgVars[i] == UINT8_MAX);
8276 for (unsigned i = cHiddenArgs; i < cArgs; i++)
8277 {
8278 Assert(pReNative->Core.aidxArgVars[i] != UINT8_MAX); /* checked by tstIEMCheckMc.cpp */
8279 Assert(pReNative->Core.bmVars & RT_BIT_32(pReNative->Core.aidxArgVars[i]));
8280 }
8281 iemNativeRegAssertSanity(pReNative);
8282#endif
8283
8284 /* We don't know what the called function makes use of, so flush any pending register writes. */
8285 RT_NOREF(fFlushPendingWrites);
8286#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
8287 if (fFlushPendingWrites)
8288#endif
8289 off = iemNativeRegFlushPendingWrites(pReNative, off);
8290
8291 /*
8292 * Before we do anything else, go over variables that are referenced and
8293 * make sure they are not in a register.
8294 */
8295 uint32_t bmVars = pReNative->Core.bmVars;
8296 if (bmVars)
8297 {
8298 do
8299 {
8300 uint8_t const idxVar = ASMBitFirstSetU32(bmVars) - 1;
8301 bmVars &= ~RT_BIT_32(idxVar);
8302
8303 if (pReNative->Core.aVars[idxVar].idxReferrerVar != UINT8_MAX)
8304 {
8305 uint8_t const idxRegOld = pReNative->Core.aVars[idxVar].idxReg;
8306#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
8307 if ( idxRegOld != UINT8_MAX
8308 && pReNative->Core.aVars[idxVar].fSimdReg)
8309 {
8310 Assert(idxRegOld < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
8311 Assert(pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT128U) || pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT256U));
8312
8313 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
8314 Log12(("iemNativeEmitCallCommon: spilling idxVar=%d/%#x/idxReg=%d (referred to by %d) onto the stack (slot %#x bp+%d, off=%#x)\n",
8315 idxVar, IEMNATIVE_VAR_IDX_PACK(idxVar), idxRegOld, pReNative->Core.aVars[idxVar].idxReferrerVar,
8316 idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
8317 if (pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT128U))
8318 off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
8319 else
8320 off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
8321
8322 Assert(!( (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
8323 & pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows));
8324
8325 pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
8326 pReNative->Core.bmHstSimdRegs &= ~RT_BIT_32(idxRegOld);
8327 pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
8328 pReNative->Core.bmGstSimdRegShadows &= ~pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows;
8329 pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows = 0;
8330 }
8331 else
8332#endif
8333 if (idxRegOld < RT_ELEMENTS(pReNative->Core.aHstRegs))
8334 {
8335 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
8336 Log12(("iemNativeEmitCallCommon: spilling idxVar=%d/%#x/idxReg=%d (referred to by %d) onto the stack (slot %#x bp+%d, off=%#x)\n",
8337 idxVar, IEMNATIVE_VAR_IDX_PACK(idxVar), idxRegOld, pReNative->Core.aVars[idxVar].idxReferrerVar,
8338 idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
8339 off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
8340
8341 pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
8342 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxRegOld);
8343 pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
8344 pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows;
8345 pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows = 0;
8346 }
8347 }
8348 } while (bmVars != 0);
8349#if 0 //def VBOX_STRICT
8350 iemNativeRegAssertSanity(pReNative);
8351#endif
8352 }
8353
8354 uint8_t const cRegArgs = RT_MIN(cArgs, RT_ELEMENTS(g_aidxIemNativeCallRegs));
8355
8356#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
8357 /*
8358 * At the very first step go over the host registers that will be used for arguments
8359 * don't shadow anything which needs writing back first.
8360 */
8361 for (uint32_t i = 0; i < cRegArgs; i++)
8362 {
8363 uint8_t const idxArgReg = g_aidxIemNativeCallRegs[i];
8364
8365 /* Writeback any dirty guest shadows before using this register. */
8366 if (pReNative->Core.bmGstRegShadowDirty & pReNative->Core.aHstRegs[idxArgReg].fGstRegShadows)
8367 off = iemNativeRegFlushDirtyGuestByHostRegShadow(pReNative, off, idxArgReg);
8368 Assert(!(pReNative->Core.bmGstRegShadowDirty & pReNative->Core.aHstRegs[idxArgReg].fGstRegShadows));
8369 }
8370#endif
8371
8372 /*
8373 * First, go over the host registers that will be used for arguments and make
8374 * sure they either hold the desired argument or are free.
8375 */
8376 if (pReNative->Core.bmHstRegs & g_afIemNativeCallRegs[cRegArgs])
8377 {
8378 for (uint32_t i = 0; i < cRegArgs; i++)
8379 {
8380 uint8_t const idxArgReg = g_aidxIemNativeCallRegs[i];
8381 if (pReNative->Core.bmHstRegs & RT_BIT_32(idxArgReg))
8382 {
8383 if (pReNative->Core.aHstRegs[idxArgReg].enmWhat == kIemNativeWhat_Var)
8384 {
8385 uint8_t const idxVar = pReNative->Core.aHstRegs[idxArgReg].idxVar;
8386 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
8387 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
8388 Assert(pVar->idxReg == idxArgReg);
8389 uint8_t const uArgNo = pVar->uArgNo;
8390 if (uArgNo == i)
8391 { /* prefect */ }
8392 /* The variable allocator logic should make sure this is impossible,
8393 except for when the return register is used as a parameter (ARM,
8394 but not x86). */
8395#if RT_BIT_32(IEMNATIVE_CALL_RET_GREG) & IEMNATIVE_CALL_ARGS_GREG_MASK
8396 else if (idxArgReg == IEMNATIVE_CALL_RET_GREG && uArgNo != UINT8_MAX)
8397 {
8398# ifdef IEMNATIVE_FP_OFF_STACK_ARG0
8399# error "Implement this"
8400# endif
8401 Assert(uArgNo < IEMNATIVE_CALL_ARG_GREG_COUNT);
8402 uint8_t const idxFinalArgReg = g_aidxIemNativeCallRegs[uArgNo];
8403 AssertStmt(!(pReNative->Core.bmHstRegs & RT_BIT_32(idxFinalArgReg)),
8404 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_10));
8405 off = iemNativeRegMoveVar(pReNative, off, idxVar, idxArgReg, idxFinalArgReg, "iemNativeEmitCallCommon");
8406 }
8407#endif
8408 else
8409 {
8410 AssertStmt(uArgNo == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_10));
8411
8412 if (pVar->enmKind == kIemNativeVarKind_Stack)
8413 off = iemNativeRegMoveOrSpillStackVar(pReNative, off, idxVar);
8414 else
8415 {
8416 /* just free it, can be reloaded if used again */
8417 pVar->idxReg = UINT8_MAX;
8418 pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxArgReg);
8419 iemNativeRegClearGstRegShadowing(pReNative, idxArgReg, off);
8420 }
8421 }
8422 }
8423 else
8424 AssertStmt(pReNative->Core.aHstRegs[idxArgReg].enmWhat == kIemNativeWhat_Arg,
8425 IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_8));
8426 }
8427 }
8428#if 0 //def VBOX_STRICT
8429 iemNativeRegAssertSanity(pReNative);
8430#endif
8431 }
8432
8433 Assert(!(pReNative->Core.bmHstRegs & g_afIemNativeCallRegs[cHiddenArgs])); /* No variables for hidden arguments. */
8434
8435#ifdef IEMNATIVE_FP_OFF_STACK_ARG0
8436 /*
8437 * If there are any stack arguments, make sure they are in their place as well.
8438 *
8439 * We can use IEMNATIVE_CALL_ARG0_GREG as temporary register since we'll (or
8440 * the caller) be loading it later and it must be free (see first loop).
8441 */
8442 if (cArgs > IEMNATIVE_CALL_ARG_GREG_COUNT)
8443 {
8444 for (unsigned i = IEMNATIVE_CALL_ARG_GREG_COUNT; i < cArgs; i++)
8445 {
8446 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]]; /* unpacked */
8447 int32_t const offBpDisp = g_aoffIemNativeCallStackArgBpDisp[i - IEMNATIVE_CALL_ARG_GREG_COUNT];
8448 if (pVar->idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
8449 {
8450 Assert(pVar->enmKind == kIemNativeVarKind_Stack); /* Imm as well? */
8451 off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDisp, pVar->idxReg);
8452 pReNative->Core.bmHstRegs &= ~RT_BIT_32(pVar->idxReg);
8453 pVar->idxReg = UINT8_MAX;
8454 }
8455 else
8456 {
8457 /* Use ARG0 as temp for stuff we need registers for. */
8458 switch (pVar->enmKind)
8459 {
8460 case kIemNativeVarKind_Stack:
8461 {
8462 uint8_t const idxStackSlot = pVar->idxStackSlot;
8463 AssertStmt(idxStackSlot != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
8464 off = iemNativeEmitLoadGprByBp(pReNative, off, IEMNATIVE_CALL_ARG0_GREG /* is free */,
8465 iemNativeStackCalcBpDisp(idxStackSlot));
8466 off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDisp, IEMNATIVE_CALL_ARG0_GREG);
8467 continue;
8468 }
8469
8470 case kIemNativeVarKind_Immediate:
8471 off = iemNativeEmitStoreImm64ByBp(pReNative, off, offBpDisp, pVar->u.uValue);
8472 continue;
8473
8474 case kIemNativeVarKind_VarRef:
8475 {
8476 uint8_t const idxOtherVar = pVar->u.idxRefVar; /* unpacked */
8477 Assert(idxOtherVar < RT_ELEMENTS(pReNative->Core.aVars));
8478 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxOtherVar));
8479 int32_t const offBpDispOther = iemNativeStackCalcBpDisp(idxStackSlot);
8480 uint8_t const idxRegOther = pReNative->Core.aVars[idxOtherVar].idxReg;
8481# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
8482 bool const fSimdReg = pReNative->Core.aVars[idxOtherVar].fSimdReg;
8483 uint8_t const cbVar = pReNative->Core.aVars[idxOtherVar].cbVar;
8484 if ( fSimdReg
8485 && idxRegOther != UINT8_MAX)
8486 {
8487 Assert(idxRegOther < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
8488 if (cbVar == sizeof(RTUINT128U))
8489 off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, offBpDispOther, idxRegOther);
8490 else
8491 off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, offBpDispOther, idxRegOther);
8492 iemNativeSimdRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
8493 Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8494 }
8495 else
8496# endif
8497 if (idxRegOther < RT_ELEMENTS(pReNative->Core.aHstRegs))
8498 {
8499 off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDispOther, idxRegOther);
8500 iemNativeRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
8501 Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8502 }
8503 Assert( pReNative->Core.aVars[idxOtherVar].idxStackSlot != UINT8_MAX
8504 && pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8505 off = iemNativeEmitLeaGprByBp(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, offBpDispOther);
8506 off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDisp, IEMNATIVE_CALL_ARG0_GREG);
8507 continue;
8508 }
8509
8510 case kIemNativeVarKind_GstRegRef:
8511 off = iemNativeEmitLeaGprByGstRegRef(pReNative, off, IEMNATIVE_CALL_ARG0_GREG,
8512 pVar->u.GstRegRef.enmClass, pVar->u.GstRegRef.idx);
8513 off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDisp, IEMNATIVE_CALL_ARG0_GREG);
8514 continue;
8515
8516 case kIemNativeVarKind_Invalid:
8517 case kIemNativeVarKind_End:
8518 break;
8519 }
8520 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_3));
8521 }
8522 }
8523# if 0 //def VBOX_STRICT
8524 iemNativeRegAssertSanity(pReNative);
8525# endif
8526 }
8527#else
8528 AssertCompile(IEMNATIVE_CALL_MAX_ARG_COUNT <= IEMNATIVE_CALL_ARG_GREG_COUNT);
8529#endif
8530
8531 /*
8532 * Make sure the argument variables are loaded into their respective registers.
8533 *
8534 * We can optimize this by ASSUMING that any register allocations are for
8535 * registeres that have already been loaded and are ready. The previous step
8536 * saw to that.
8537 */
8538 if (~pReNative->Core.bmHstRegs & (g_afIemNativeCallRegs[cRegArgs] & ~g_afIemNativeCallRegs[cHiddenArgs]))
8539 {
8540 for (unsigned i = cHiddenArgs; i < cRegArgs; i++)
8541 {
8542 uint8_t const idxArgReg = g_aidxIemNativeCallRegs[i];
8543 if (pReNative->Core.bmHstRegs & RT_BIT_32(idxArgReg))
8544 Assert( pReNative->Core.aHstRegs[idxArgReg].idxVar == IEMNATIVE_VAR_IDX_PACK(pReNative->Core.aidxArgVars[i])
8545 && pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]].uArgNo == i
8546 && pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]].idxReg == idxArgReg);
8547 else
8548 {
8549 PIEMNATIVEVAR const pVar = &pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]]; /* unpacked */
8550 if (pVar->idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
8551 {
8552 Assert(pVar->enmKind == kIemNativeVarKind_Stack);
8553 off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxArgReg, pVar->idxReg);
8554 pReNative->Core.bmHstRegs = (pReNative->Core.bmHstRegs & ~RT_BIT_32(pVar->idxReg))
8555 | RT_BIT_32(idxArgReg);
8556 pVar->idxReg = idxArgReg;
8557 }
8558 else
8559 {
8560 /* Use ARG0 as temp for stuff we need registers for. */
8561 switch (pVar->enmKind)
8562 {
8563 case kIemNativeVarKind_Stack:
8564 {
8565 uint8_t const idxStackSlot = pVar->idxStackSlot;
8566 AssertStmt(idxStackSlot != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
8567 off = iemNativeEmitLoadGprByBp(pReNative, off, idxArgReg, iemNativeStackCalcBpDisp(idxStackSlot));
8568 continue;
8569 }
8570
8571 case kIemNativeVarKind_Immediate:
8572 off = iemNativeEmitLoadGprImm64(pReNative, off, idxArgReg, pVar->u.uValue);
8573 continue;
8574
8575 case kIemNativeVarKind_VarRef:
8576 {
8577 uint8_t const idxOtherVar = pVar->u.idxRefVar; /* unpacked */
8578 Assert(idxOtherVar < RT_ELEMENTS(pReNative->Core.aVars));
8579 uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative,
8580 IEMNATIVE_VAR_IDX_PACK(idxOtherVar));
8581 int32_t const offBpDispOther = iemNativeStackCalcBpDisp(idxStackSlot);
8582 uint8_t const idxRegOther = pReNative->Core.aVars[idxOtherVar].idxReg;
8583#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
8584 bool const fSimdReg = pReNative->Core.aVars[idxOtherVar].fSimdReg;
8585 uint8_t const cbVar = pReNative->Core.aVars[idxOtherVar].cbVar;
8586 if ( fSimdReg
8587 && idxRegOther != UINT8_MAX)
8588 {
8589 Assert(idxRegOther < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
8590 if (cbVar == sizeof(RTUINT128U))
8591 off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, offBpDispOther, idxRegOther);
8592 else
8593 off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, offBpDispOther, idxRegOther);
8594 iemNativeSimdRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
8595 Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8596 }
8597 else
8598#endif
8599 if (idxRegOther < RT_ELEMENTS(pReNative->Core.aHstRegs))
8600 {
8601 off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDispOther, idxRegOther);
8602 iemNativeRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
8603 Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8604 }
8605 Assert( pReNative->Core.aVars[idxOtherVar].idxStackSlot != UINT8_MAX
8606 && pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8607 off = iemNativeEmitLeaGprByBp(pReNative, off, idxArgReg, offBpDispOther);
8608 continue;
8609 }
8610
8611 case kIemNativeVarKind_GstRegRef:
8612 off = iemNativeEmitLeaGprByGstRegRef(pReNative, off, idxArgReg,
8613 pVar->u.GstRegRef.enmClass, pVar->u.GstRegRef.idx);
8614 continue;
8615
8616 case kIemNativeVarKind_Invalid:
8617 case kIemNativeVarKind_End:
8618 break;
8619 }
8620 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_3));
8621 }
8622 }
8623 }
8624#if 0 //def VBOX_STRICT
8625 iemNativeRegAssertSanity(pReNative);
8626#endif
8627 }
8628#ifdef VBOX_STRICT
8629 else
8630 for (unsigned i = cHiddenArgs; i < cRegArgs; i++)
8631 {
8632 Assert(pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]].uArgNo == i);
8633 Assert(pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]].idxReg == g_aidxIemNativeCallRegs[i]);
8634 }
8635#endif
8636
8637 /*
8638 * Free all argument variables (simplified).
8639 * Their lifetime always expires with the call they are for.
8640 */
8641 /** @todo Make the python script check that arguments aren't used after
8642 * IEM_MC_CALL_XXXX. */
8643 /** @todo There is a special with IEM_MC_MEM_MAP_U16_RW and friends requiring
8644 * a IEM_MC_MEM_COMMIT_AND_UNMAP_RW after a AIMPL call typically with
8645 * an argument value. There is also some FPU stuff. */
8646 for (uint32_t i = cHiddenArgs; i < cArgs; i++)
8647 {
8648 uint8_t const idxVar = pReNative->Core.aidxArgVars[i]; /* unpacked */
8649 Assert(idxVar < RT_ELEMENTS(pReNative->Core.aVars));
8650
8651 /* no need to free registers: */
8652 AssertMsg(i < IEMNATIVE_CALL_ARG_GREG_COUNT
8653 ? pReNative->Core.aVars[idxVar].idxReg == g_aidxIemNativeCallRegs[i]
8654 || pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX
8655 : pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX,
8656 ("i=%d idxVar=%d idxReg=%d, expected %d\n", i, idxVar, pReNative->Core.aVars[idxVar].idxReg,
8657 i < IEMNATIVE_CALL_ARG_GREG_COUNT ? g_aidxIemNativeCallRegs[i] : UINT8_MAX));
8658
8659 pReNative->Core.aidxArgVars[i] = UINT8_MAX;
8660 pReNative->Core.bmVars &= ~RT_BIT_32(idxVar);
8661 iemNativeVarFreeStackSlots(pReNative, idxVar);
8662 }
8663 Assert(pReNative->Core.u64ArgVars == UINT64_MAX);
8664
8665 /*
8666 * Flush volatile registers as we make the call.
8667 */
8668 off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, cRegArgs);
8669
8670 return off;
8671}
8672
8673
8674
8675/*********************************************************************************************************************************
8676* TLB Lookup. *
8677*********************************************************************************************************************************/
8678
8679/**
8680 * This is called via iemNativeHlpAsmSafeWrapCheckTlbLookup.
8681 */
8682DECLASM(void) iemNativeHlpCheckTlbLookup(PVMCPU pVCpu, uintptr_t uResult, uint64_t GCPtr, uint64_t uSegAndSizeAndAccessAndDisp)
8683{
8684 uint8_t const iSegReg = RT_BYTE1(uSegAndSizeAndAccessAndDisp);
8685 uint8_t const cbMem = RT_BYTE2(uSegAndSizeAndAccessAndDisp);
8686 uint32_t const fAccess = (uint32_t)uSegAndSizeAndAccessAndDisp >> 16;
8687 uint8_t const offDisp = RT_BYTE5(uSegAndSizeAndAccessAndDisp);
8688 Log(("iemNativeHlpCheckTlbLookup: %x:%#RX64+%#x LB %#x fAccess=%#x -> %#RX64\n", iSegReg, GCPtr, offDisp, cbMem, fAccess, uResult));
8689
8690 /* Do the lookup manually. */
8691 RTGCPTR const GCPtrFlat = (iSegReg == UINT8_MAX ? GCPtr : GCPtr + pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base) + offDisp;
8692 uint64_t const uTagNoRev = IEMTLB_CALC_TAG_NO_REV(GCPtrFlat);
8693 PCIEMTLBENTRY pTlbe = IEMTLB_TAG_TO_EVEN_ENTRY(&pVCpu->iem.s.DataTlb, uTagNoRev);
8694 if (RT_LIKELY( pTlbe->uTag == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevision)
8695 || (pTlbe = pTlbe + 1)->uTag == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevisionGlobal)))
8696 {
8697 /*
8698 * Check TLB page table level access flags.
8699 */
8700 AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
8701 uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER;
8702 uint64_t const fNoWriteNoDirty = !(fAccess & IEM_ACCESS_TYPE_WRITE) ? 0
8703 : IEMTLBE_F_PT_NO_WRITE | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PG_NO_WRITE;
8704 uint64_t const fFlagsAndPhysRev = pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV | IEMTLBE_F_NO_MAPPINGR3
8705 | IEMTLBE_F_PG_UNASSIGNED
8706 | IEMTLBE_F_PT_NO_ACCESSED
8707 | fNoWriteNoDirty | fNoUser);
8708 uint64_t const uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev;
8709 if (RT_LIKELY(fFlagsAndPhysRev == uTlbPhysRev))
8710 {
8711 /*
8712 * Return the address.
8713 */
8714 uint8_t const * const pbAddr = &pTlbe->pbMappingR3[GCPtrFlat & GUEST_PAGE_OFFSET_MASK];
8715 if ((uintptr_t)pbAddr == uResult)
8716 return;
8717 RT_NOREF(cbMem);
8718 AssertFailed();
8719 }
8720 else
8721 AssertMsgFailed(("fFlagsAndPhysRev=%#RX64 vs uTlbPhysRev=%#RX64: %#RX64\n",
8722 fFlagsAndPhysRev, uTlbPhysRev, fFlagsAndPhysRev ^ uTlbPhysRev));
8723 }
8724 else
8725 AssertFailed();
8726 RT_BREAKPOINT();
8727}
8728
8729/* The rest of the code is in IEMN8veRecompilerTlbLookup.h. */
8730
8731
8732
8733/*********************************************************************************************************************************
8734* Recompiler Core. *
8735*********************************************************************************************************************************/
8736
8737/** @callback_method_impl{FNDISREADBYTES, Dummy.} */
8738static DECLCALLBACK(int) iemNativeDisasReadBytesDummy(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
8739{
8740 RT_BZERO(&pDis->Instr.ab[offInstr], cbMaxRead);
8741 pDis->cbCachedInstr += cbMaxRead;
8742 RT_NOREF(cbMinRead);
8743 return VERR_NO_DATA;
8744}
8745
8746
8747DECLHIDDEN(const char *) iemNativeDbgVCpuOffsetToName(uint32_t off)
8748{
8749 static struct { uint32_t off; const char *pszName; } const s_aMembers[] =
8750 {
8751#define ENTRY(a_Member) { (uint32_t)RT_UOFFSETOF(VMCPUCC, a_Member), #a_Member } /* cast is for stupid MSC */
8752 ENTRY(fLocalForcedActions),
8753 ENTRY(iem.s.rcPassUp),
8754 ENTRY(iem.s.fExec),
8755 ENTRY(iem.s.pbInstrBuf),
8756 ENTRY(iem.s.uInstrBufPc),
8757 ENTRY(iem.s.GCPhysInstrBuf),
8758 ENTRY(iem.s.cbInstrBufTotal),
8759 ENTRY(iem.s.idxTbCurInstr),
8760 ENTRY(iem.s.fSkippingEFlags),
8761#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
8762 ENTRY(iem.s.uPcUpdatingDebug),
8763#endif
8764#ifdef VBOX_WITH_STATISTICS
8765 ENTRY(iem.s.StatNativeTlbHitsForFetch),
8766 ENTRY(iem.s.StatNativeTlbHitsForStore),
8767 ENTRY(iem.s.StatNativeTlbHitsForStack),
8768 ENTRY(iem.s.StatNativeTlbHitsForMapped),
8769 ENTRY(iem.s.StatNativeCodeTlbMissesNewPage),
8770 ENTRY(iem.s.StatNativeCodeTlbHitsForNewPage),
8771 ENTRY(iem.s.StatNativeCodeTlbMissesNewPageWithOffset),
8772 ENTRY(iem.s.StatNativeCodeTlbHitsForNewPageWithOffset),
8773#endif
8774 ENTRY(iem.s.DataTlb.uTlbRevision),
8775 ENTRY(iem.s.DataTlb.uTlbPhysRev),
8776 ENTRY(iem.s.DataTlb.cTlbCoreHits),
8777 ENTRY(iem.s.DataTlb.cTlbInlineCodeHits),
8778 ENTRY(iem.s.DataTlb.cTlbNativeMissTag),
8779 ENTRY(iem.s.DataTlb.cTlbNativeMissFlagsAndPhysRev),
8780 ENTRY(iem.s.DataTlb.cTlbNativeMissAlignment),
8781 ENTRY(iem.s.DataTlb.cTlbNativeMissCrossPage),
8782 ENTRY(iem.s.DataTlb.cTlbNativeMissNonCanonical),
8783 ENTRY(iem.s.DataTlb.aEntries),
8784 ENTRY(iem.s.CodeTlb.uTlbRevision),
8785 ENTRY(iem.s.CodeTlb.uTlbPhysRev),
8786 ENTRY(iem.s.CodeTlb.cTlbCoreHits),
8787 ENTRY(iem.s.CodeTlb.cTlbNativeMissTag),
8788 ENTRY(iem.s.CodeTlb.cTlbNativeMissFlagsAndPhysRev),
8789 ENTRY(iem.s.CodeTlb.cTlbNativeMissAlignment),
8790 ENTRY(iem.s.CodeTlb.cTlbNativeMissCrossPage),
8791 ENTRY(iem.s.CodeTlb.cTlbNativeMissNonCanonical),
8792 ENTRY(iem.s.CodeTlb.aEntries),
8793 ENTRY(pVMR3),
8794 ENTRY(cpum.GstCtx.rax),
8795 ENTRY(cpum.GstCtx.ah),
8796 ENTRY(cpum.GstCtx.rcx),
8797 ENTRY(cpum.GstCtx.ch),
8798 ENTRY(cpum.GstCtx.rdx),
8799 ENTRY(cpum.GstCtx.dh),
8800 ENTRY(cpum.GstCtx.rbx),
8801 ENTRY(cpum.GstCtx.bh),
8802 ENTRY(cpum.GstCtx.rsp),
8803 ENTRY(cpum.GstCtx.rbp),
8804 ENTRY(cpum.GstCtx.rsi),
8805 ENTRY(cpum.GstCtx.rdi),
8806 ENTRY(cpum.GstCtx.r8),
8807 ENTRY(cpum.GstCtx.r9),
8808 ENTRY(cpum.GstCtx.r10),
8809 ENTRY(cpum.GstCtx.r11),
8810 ENTRY(cpum.GstCtx.r12),
8811 ENTRY(cpum.GstCtx.r13),
8812 ENTRY(cpum.GstCtx.r14),
8813 ENTRY(cpum.GstCtx.r15),
8814 ENTRY(cpum.GstCtx.es.Sel),
8815 ENTRY(cpum.GstCtx.es.u64Base),
8816 ENTRY(cpum.GstCtx.es.u32Limit),
8817 ENTRY(cpum.GstCtx.es.Attr),
8818 ENTRY(cpum.GstCtx.cs.Sel),
8819 ENTRY(cpum.GstCtx.cs.u64Base),
8820 ENTRY(cpum.GstCtx.cs.u32Limit),
8821 ENTRY(cpum.GstCtx.cs.Attr),
8822 ENTRY(cpum.GstCtx.ss.Sel),
8823 ENTRY(cpum.GstCtx.ss.u64Base),
8824 ENTRY(cpum.GstCtx.ss.u32Limit),
8825 ENTRY(cpum.GstCtx.ss.Attr),
8826 ENTRY(cpum.GstCtx.ds.Sel),
8827 ENTRY(cpum.GstCtx.ds.u64Base),
8828 ENTRY(cpum.GstCtx.ds.u32Limit),
8829 ENTRY(cpum.GstCtx.ds.Attr),
8830 ENTRY(cpum.GstCtx.fs.Sel),
8831 ENTRY(cpum.GstCtx.fs.u64Base),
8832 ENTRY(cpum.GstCtx.fs.u32Limit),
8833 ENTRY(cpum.GstCtx.fs.Attr),
8834 ENTRY(cpum.GstCtx.gs.Sel),
8835 ENTRY(cpum.GstCtx.gs.u64Base),
8836 ENTRY(cpum.GstCtx.gs.u32Limit),
8837 ENTRY(cpum.GstCtx.gs.Attr),
8838 ENTRY(cpum.GstCtx.rip),
8839 ENTRY(cpum.GstCtx.eflags),
8840 ENTRY(cpum.GstCtx.uRipInhibitInt),
8841 ENTRY(cpum.GstCtx.cr0),
8842 ENTRY(cpum.GstCtx.cr4),
8843 ENTRY(cpum.GstCtx.aXcr[0]),
8844 ENTRY(cpum.GstCtx.aXcr[1]),
8845#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
8846 ENTRY(cpum.GstCtx.XState.x87.MXCSR),
8847 ENTRY(cpum.GstCtx.XState.x87.aXMM[0]),
8848 ENTRY(cpum.GstCtx.XState.x87.aXMM[1]),
8849 ENTRY(cpum.GstCtx.XState.x87.aXMM[2]),
8850 ENTRY(cpum.GstCtx.XState.x87.aXMM[3]),
8851 ENTRY(cpum.GstCtx.XState.x87.aXMM[4]),
8852 ENTRY(cpum.GstCtx.XState.x87.aXMM[5]),
8853 ENTRY(cpum.GstCtx.XState.x87.aXMM[6]),
8854 ENTRY(cpum.GstCtx.XState.x87.aXMM[7]),
8855 ENTRY(cpum.GstCtx.XState.x87.aXMM[8]),
8856 ENTRY(cpum.GstCtx.XState.x87.aXMM[9]),
8857 ENTRY(cpum.GstCtx.XState.x87.aXMM[10]),
8858 ENTRY(cpum.GstCtx.XState.x87.aXMM[11]),
8859 ENTRY(cpum.GstCtx.XState.x87.aXMM[12]),
8860 ENTRY(cpum.GstCtx.XState.x87.aXMM[13]),
8861 ENTRY(cpum.GstCtx.XState.x87.aXMM[14]),
8862 ENTRY(cpum.GstCtx.XState.x87.aXMM[15]),
8863 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[0]),
8864 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[1]),
8865 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[2]),
8866 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[3]),
8867 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[4]),
8868 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[5]),
8869 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[6]),
8870 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[7]),
8871 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[8]),
8872 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[9]),
8873 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[10]),
8874 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[11]),
8875 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[12]),
8876 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[13]),
8877 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[14]),
8878 ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[15])
8879#endif
8880#undef ENTRY
8881 };
8882#ifdef VBOX_STRICT
8883 static bool s_fOrderChecked = false;
8884 if (!s_fOrderChecked)
8885 {
8886 s_fOrderChecked = true;
8887 uint32_t offPrev = s_aMembers[0].off;
8888 for (unsigned i = 1; i < RT_ELEMENTS(s_aMembers); i++)
8889 {
8890 Assert(s_aMembers[i].off > offPrev);
8891 offPrev = s_aMembers[i].off;
8892 }
8893 }
8894#endif
8895
8896 /*
8897 * Binary lookup.
8898 */
8899 unsigned iStart = 0;
8900 unsigned iEnd = RT_ELEMENTS(s_aMembers);
8901 for (;;)
8902 {
8903 unsigned const iCur = iStart + (iEnd - iStart) / 2;
8904 uint32_t const offCur = s_aMembers[iCur].off;
8905 if (off < offCur)
8906 {
8907 if (iCur != iStart)
8908 iEnd = iCur;
8909 else
8910 break;
8911 }
8912 else if (off > offCur)
8913 {
8914 if (iCur + 1 < iEnd)
8915 iStart = iCur + 1;
8916 else
8917 break;
8918 }
8919 else
8920 return s_aMembers[iCur].pszName;
8921 }
8922#ifdef VBOX_WITH_STATISTICS
8923 if (off - RT_UOFFSETOF(VMCPUCC, iem.s.acThreadedFuncStats) < RT_SIZEOFMEMB(VMCPUCC, iem.s.acThreadedFuncStats))
8924 return "iem.s.acThreadedFuncStats[iFn]";
8925#endif
8926 return NULL;
8927}
8928
8929
8930/**
8931 * Translates a label to a name.
8932 */
8933static const char *iemNativeGetLabelName(IEMNATIVELABELTYPE enmLabel, bool fCommonCode /*= false*/)
8934{
8935 switch (enmLabel)
8936 {
8937#define STR_CASE_CMN(a_Label) case kIemNativeLabelType_ ## a_Label: return fCommonCode ? "Chunk_" #a_Label : #a_Label;
8938 STR_CASE_CMN(Invalid);
8939 STR_CASE_CMN(RaiseDe);
8940 STR_CASE_CMN(RaiseUd);
8941 STR_CASE_CMN(RaiseSseRelated);
8942 STR_CASE_CMN(RaiseAvxRelated);
8943 STR_CASE_CMN(RaiseSseAvxFpRelated);
8944 STR_CASE_CMN(RaiseNm);
8945 STR_CASE_CMN(RaiseGp0);
8946 STR_CASE_CMN(RaiseMf);
8947 STR_CASE_CMN(RaiseXf);
8948 STR_CASE_CMN(ObsoleteTb);
8949 STR_CASE_CMN(NeedCsLimChecking);
8950 STR_CASE_CMN(CheckBranchMiss);
8951 STR_CASE_CMN(Return);
8952 STR_CASE_CMN(ReturnBreak);
8953 STR_CASE_CMN(ReturnBreakFF);
8954 STR_CASE_CMN(ReturnWithFlags);
8955 STR_CASE_CMN(ReturnBreakViaLookup);
8956 STR_CASE_CMN(ReturnBreakViaLookupWithIrq);
8957 STR_CASE_CMN(ReturnBreakViaLookupWithTlb);
8958 STR_CASE_CMN(ReturnBreakViaLookupWithTlbAndIrq);
8959 STR_CASE_CMN(NonZeroRetOrPassUp);
8960#undef STR_CASE_CMN
8961#define STR_CASE_LBL(a_Label) case kIemNativeLabelType_ ## a_Label: return #a_Label;
8962 STR_CASE_LBL(LoopJumpTarget);
8963 STR_CASE_LBL(If);
8964 STR_CASE_LBL(Else);
8965 STR_CASE_LBL(Endif);
8966 STR_CASE_LBL(CheckIrq);
8967 STR_CASE_LBL(TlbLookup);
8968 STR_CASE_LBL(TlbMiss);
8969 STR_CASE_LBL(TlbDone);
8970 case kIemNativeLabelType_End: break;
8971 }
8972 return NULL;
8973}
8974
8975
8976/** Info for the symbols resolver used when disassembling. */
8977typedef struct IEMNATIVDISASMSYMCTX
8978{
8979 PVMCPU pVCpu;
8980 PCIEMTB pTb;
8981# ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
8982 PCIEMNATIVEPERCHUNKCTX pCtx;
8983# endif
8984# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
8985 PCIEMTBDBG pDbgInfo;
8986# endif
8987} IEMNATIVDISASMSYMCTX;
8988typedef IEMNATIVDISASMSYMCTX *PIEMNATIVDISASMSYMCTX;
8989
8990
8991/**
8992 * Resolve address to symbol, if we can.
8993 */
8994static const char *iemNativeDisasmGetSymbol(PIEMNATIVDISASMSYMCTX pSymCtx, uintptr_t uAddress, char *pszBuf, size_t cbBuf)
8995{
8996#if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) || defined(IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE)
8997 PCIEMTB const pTb = pSymCtx->pTb;
8998 uintptr_t const offNative = (uAddress - (uintptr_t)pTb->Native.paInstructions) / sizeof(IEMNATIVEINSTR);
8999 if (offNative <= pTb->Native.cInstructions)
9000 {
9001# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
9002 /*
9003 * Scan debug info for a matching label.
9004 * Since the debug info should be 100% linear, we can do a binary search here.
9005 */
9006 PCIEMTBDBG const pDbgInfo = pSymCtx->pDbgInfo;
9007 if (pDbgInfo)
9008 {
9009 uint32_t const cEntries = pDbgInfo->cEntries;
9010 uint32_t idxEnd = cEntries;
9011 uint32_t idxStart = 0;
9012 for (;;)
9013 {
9014 /* Find a NativeOffset record close to the midpoint. */
9015 uint32_t idx = idxStart + (idxEnd - idxStart) / 2;
9016 while (idx > idxStart && pDbgInfo->aEntries[idx].Gen.uType != kIemTbDbgEntryType_NativeOffset)
9017 idx--;
9018 if (pDbgInfo->aEntries[idx].Gen.uType != kIemTbDbgEntryType_NativeOffset)
9019 {
9020 idx = idxStart + (idxEnd - idxStart) / 2 + 1;
9021 while (idx < idxEnd && pDbgInfo->aEntries[idx].Gen.uType != kIemTbDbgEntryType_NativeOffset)
9022 idx++;
9023 if (idx >= idxEnd)
9024 break;
9025 }
9026
9027 /* Do the binary searching thing. */
9028 if (offNative < pDbgInfo->aEntries[idx].NativeOffset.offNative)
9029 {
9030 if (idx > idxStart)
9031 idxEnd = idx;
9032 else
9033 break;
9034 }
9035 else if (offNative > pDbgInfo->aEntries[idx].NativeOffset.offNative)
9036 {
9037 idx += 1;
9038 if (idx < idxEnd)
9039 idxStart = idx;
9040 else
9041 break;
9042 }
9043 else
9044 {
9045 /* Got a matching offset, scan forward till we hit a label, but
9046 stop when the native offset changes. */
9047 while (++idx < cEntries)
9048 switch (pDbgInfo->aEntries[idx].Gen.uType)
9049 {
9050 case kIemTbDbgEntryType_Label:
9051 {
9052 IEMNATIVELABELTYPE const enmLabel = (IEMNATIVELABELTYPE)pDbgInfo->aEntries[idx].Label.enmLabel;
9053 const char * const pszName = iemNativeGetLabelName(enmLabel);
9054 if (enmLabel < kIemNativeLabelType_FirstWithMultipleInstances)
9055 return pszName;
9056 RTStrPrintf(pszBuf, cbBuf, "%s_%u", pszName, pDbgInfo->aEntries[idx].Label.uData);
9057 return pszBuf;
9058 }
9059
9060 case kIemTbDbgEntryType_NativeOffset:
9061 if (pDbgInfo->aEntries[idx].NativeOffset.offNative != offNative)
9062 return NULL;
9063 break;
9064 }
9065 break;
9066 }
9067 }
9068 }
9069# endif
9070 }
9071# ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
9072 else
9073 {
9074 PCIEMNATIVEPERCHUNKCTX const pChunkCtx = pSymCtx->pCtx;
9075 if (pChunkCtx)
9076 for (uint32_t i = 1; i < RT_ELEMENTS(pChunkCtx->apExitLabels); i++)
9077 if ((PIEMNATIVEINSTR)uAddress == pChunkCtx->apExitLabels[i])
9078 return iemNativeGetLabelName((IEMNATIVELABELTYPE)i, true /*fCommonCode*/);
9079 }
9080# endif
9081#endif
9082 RT_NOREF(pSymCtx, uAddress, pszBuf, cbBuf);
9083 return NULL;
9084}
9085
9086#ifndef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
9087
9088/**
9089 * @callback_method_impl{FNDISGETSYMBOL}
9090 */
9091static DECLCALLBACK(int) iemNativeDisasmGetSymbolCb(PCDISSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
9092 char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser)
9093{
9094 const char * const pszSym = iemNativeDisasmGetSymbol((PIEMNATIVDISASMSYMCTX)pvUser, uAddress, pszBuf, cchBuf);
9095 if (pszSym)
9096 {
9097 *poff = 0;
9098 if (pszSym != pszBuf)
9099 return RTStrCopy(pszBuf, cchBuf, pszSym);
9100 return VINF_SUCCESS;
9101 }
9102 RT_NOREF(pDis, u32Sel);
9103 return VERR_SYMBOL_NOT_FOUND;
9104}
9105
9106#else /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
9107
9108/**
9109 * Annotates an instruction decoded by the capstone disassembler.
9110 */
9111static const char *
9112iemNativeDisasmAnnotateCapstone(PIEMNATIVDISASMSYMCTX pSymCtx, cs_insn const *pInstr, char *pszBuf, size_t cchBuf)
9113{
9114# if defined(RT_ARCH_ARM64)
9115 if ( (pInstr->id >= ARM64_INS_LD1 && pInstr->id < ARM64_INS_LSL)
9116 || (pInstr->id >= ARM64_INS_ST1 && pInstr->id < ARM64_INS_SUB))
9117 {
9118 /* This is bit crappy, but the disassembler provides incomplete addressing details. */
9119 AssertCompile(IEMNATIVE_REG_FIXED_PVMCPU == 28 && IEMNATIVE_REG_FIXED_PCPUMCTX == 27);
9120 char const *psz = strchr(pInstr->op_str, '[');
9121 if (psz && psz[1] == 'x' && psz[2] == '2' && (psz[3] == '7' || psz[3] == '8'))
9122 {
9123 uint32_t const offVCpu = psz[3] == '8'? 0 : RT_UOFFSETOF(VMCPU, cpum.GstCtx);
9124 int32_t off = -1;
9125 psz += 4;
9126 if (*psz == ']')
9127 off = 0;
9128 else if (*psz == ',')
9129 {
9130 psz = RTStrStripL(psz + 1);
9131 if (*psz == '#')
9132 off = RTStrToInt32(&psz[1]);
9133 /** @todo deal with index registers and LSL as well... */
9134 }
9135 if (off >= 0)
9136 return iemNativeDbgVCpuOffsetToName(offVCpu + (uint32_t)off);
9137 }
9138 }
9139 else if (pInstr->id == ARM64_INS_B || pInstr->id == ARM64_INS_BL)
9140 {
9141 const char *pszAddr = strchr(pInstr->op_str, '#');
9142 if (pszAddr)
9143 {
9144 uint64_t uAddr = RTStrToUInt64(pszAddr + 1);
9145 if (uAddr != 0)
9146 return iemNativeDisasmGetSymbol(pSymCtx, uAddr, pszBuf, cchBuf);
9147 }
9148 }
9149# endif
9150 RT_NOREF(pSymCtx, pInstr, pszBuf, cchBuf);
9151 return NULL;
9152}
9153#endif /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
9154
9155
9156DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT
9157{
9158 AssertReturnVoid((pTb->fFlags & IEMTB_F_TYPE_MASK) == IEMTB_F_TYPE_NATIVE);
9159#if defined(RT_ARCH_AMD64)
9160 static const char * const a_apszMarkers[] =
9161 {
9162 /*[0]=*/ "unknown0", "CheckCsLim", "ConsiderLimChecking", "CheckOpcodes",
9163 /*[4]=*/ "PcAfterBranch", "LoadTlbForNewPage", "LoadTlbAfterBranch"
9164 };
9165#endif
9166
9167 char szDisBuf[512];
9168 DISSTATE Dis;
9169 PCIEMNATIVEINSTR const paNative = pTb->Native.paInstructions;
9170 uint32_t const cNative = pTb->Native.cInstructions;
9171 uint32_t offNative = 0;
9172#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
9173 PCIEMTBDBG const pDbgInfo = pTb->pDbgInfo;
9174#endif
9175 DISCPUMODE enmGstCpuMode = (pTb->fFlags & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT ? DISCPUMODE_16BIT
9176 : (pTb->fFlags & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT ? DISCPUMODE_32BIT
9177 : DISCPUMODE_64BIT;
9178#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
9179# ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
9180 IEMNATIVDISASMSYMCTX SymCtx = { pVCpu, pTb, iemExecMemGetTbChunkCtx(pVCpu, pTb), pDbgInfo };
9181# else
9182 IEMNATIVDISASMSYMCTX SymCtx = { pVCpu, pTb, iemExecMemGetTbChunkCtx(pVCpu, pTb) };
9183# endif
9184#elif defined(IEMNATIVE_WITH_TB_DEBUG_INFO)
9185 IEMNATIVDISASMSYMCTX SymCtx = { pVCpu, pTb, pDbgInfo };
9186#else
9187 IEMNATIVDISASMSYMCTX SymCtx = { pVCpu, pTb };
9188#endif
9189#if defined(RT_ARCH_AMD64) && !defined(VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER)
9190 DISCPUMODE const enmHstCpuMode = DISCPUMODE_64BIT;
9191#elif defined(RT_ARCH_ARM64) && !defined(VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER)
9192 DISCPUMODE const enmHstCpuMode = DISCPUMODE_ARMV8_A64;
9193#elif !defined(VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER)
9194# error "Port me"
9195#else
9196 csh hDisasm = ~(size_t)0;
9197# if defined(RT_ARCH_AMD64)
9198 cs_err rcCs = cs_open(CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN | CS_MODE_64, &hDisasm);
9199# elif defined(RT_ARCH_ARM64)
9200 cs_err rcCs = cs_open(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, &hDisasm);
9201# else
9202# error "Port me"
9203# endif
9204 AssertMsgReturnVoid(rcCs == CS_ERR_OK, ("%d (%#x)\n", rcCs, rcCs));
9205
9206 //rcCs = cs_option(hDisasm, CS_OPT_DETAIL, CS_OPT_ON); - not needed as pInstr->detail doesn't provide full memory detail.
9207 //Assert(rcCs == CS_ERR_OK);
9208#endif
9209
9210 /*
9211 * Print TB info.
9212 */
9213 pHlp->pfnPrintf(pHlp,
9214 "pTb=%p: GCPhysPc=%RGp (%%%RGv) cInstructions=%u LB %#x cRanges=%u\n"
9215 "pTb=%p: cUsed=%u msLastUsed=%u fFlags=%#010x %s\n",
9216 pTb, pTb->GCPhysPc,
9217#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
9218 pTb->pDbgInfo ? pTb->pDbgInfo->FlatPc : RTGCPTR_MAX,
9219#else
9220 pTb->FlatPc,
9221#endif
9222 pTb->cInstructions, pTb->cbOpcodes, pTb->cRanges,
9223 pTb, pTb->cUsed, pTb->msLastUsed, pTb->fFlags, iemTbFlagsToString(pTb->fFlags, szDisBuf, sizeof(szDisBuf)));
9224#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
9225 if (pDbgInfo && pDbgInfo->cEntries > 1)
9226 {
9227 Assert(pDbgInfo->aEntries[0].Gen.uType == kIemTbDbgEntryType_NativeOffset);
9228
9229 /*
9230 * This disassembly is driven by the debug info which follows the native
9231 * code and indicates when it starts with the next guest instructions,
9232 * where labels are and such things.
9233 */
9234 uint32_t idxThreadedCall = 0;
9235 uint32_t idxGuestInstr = 0;
9236 uint32_t fExec = pTb->fFlags & UINT32_C(0x00ffffff);
9237 uint8_t idxRange = UINT8_MAX;
9238 uint8_t const cRanges = RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges));
9239 uint32_t offRange = 0;
9240 uint32_t offOpcodes = 0;
9241 uint32_t const cbOpcodes = pTb->cbOpcodes;
9242 RTGCPHYS GCPhysPc = pTb->GCPhysPc;
9243 uint32_t const cDbgEntries = pDbgInfo->cEntries;
9244 uint32_t iDbgEntry = 1;
9245 uint32_t offDbgNativeNext = pDbgInfo->aEntries[0].NativeOffset.offNative;
9246
9247 while (offNative < cNative)
9248 {
9249 /* If we're at or have passed the point where the next chunk of debug
9250 info starts, process it. */
9251 if (offDbgNativeNext <= offNative)
9252 {
9253 offDbgNativeNext = UINT32_MAX;
9254 for (; iDbgEntry < cDbgEntries; iDbgEntry++)
9255 {
9256 switch (pDbgInfo->aEntries[iDbgEntry].Gen.uType)
9257 {
9258 case kIemTbDbgEntryType_GuestInstruction:
9259 {
9260 /* Did the exec flag change? */
9261 if (fExec != pDbgInfo->aEntries[iDbgEntry].GuestInstruction.fExec)
9262 {
9263 pHlp->pfnPrintf(pHlp,
9264 " fExec change %#08x -> %#08x %s\n",
9265 fExec, pDbgInfo->aEntries[iDbgEntry].GuestInstruction.fExec,
9266 iemTbFlagsToString(pDbgInfo->aEntries[iDbgEntry].GuestInstruction.fExec,
9267 szDisBuf, sizeof(szDisBuf)));
9268 fExec = pDbgInfo->aEntries[iDbgEntry].GuestInstruction.fExec;
9269 enmGstCpuMode = (fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT ? DISCPUMODE_16BIT
9270 : (fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT ? DISCPUMODE_32BIT
9271 : DISCPUMODE_64BIT;
9272 }
9273
9274 /* New opcode range? We need to fend up a spurious debug info entry here for cases
9275 where the compilation was aborted before the opcode was recorded and the actual
9276 instruction was translated to a threaded call. This may happen when we run out
9277 of ranges, or when some complicated interrupts/FFs are found to be pending or
9278 similar. So, we just deal with it here rather than in the compiler code as it
9279 is a lot simpler to do here. */
9280 if ( idxRange == UINT8_MAX
9281 || idxRange >= cRanges
9282 || offRange >= pTb->aRanges[idxRange].cbOpcodes)
9283 {
9284 idxRange += 1;
9285 if (idxRange < cRanges)
9286 offRange = !idxRange ? 0 : offRange - pTb->aRanges[idxRange - 1].cbOpcodes;
9287 else
9288 continue;
9289 Assert(offOpcodes == pTb->aRanges[idxRange].offOpcodes + offRange);
9290 GCPhysPc = pTb->aRanges[idxRange].offPhysPage
9291 + (pTb->aRanges[idxRange].idxPhysPage == 0
9292 ? pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK
9293 : pTb->aGCPhysPages[pTb->aRanges[idxRange].idxPhysPage - 1]);
9294 pHlp->pfnPrintf(pHlp, " Range #%u: GCPhysPc=%RGp LB %#x [idxPg=%d]\n",
9295 idxRange, GCPhysPc, pTb->aRanges[idxRange].cbOpcodes,
9296 pTb->aRanges[idxRange].idxPhysPage);
9297 GCPhysPc += offRange;
9298 }
9299
9300 /* Disassemble the instruction. */
9301 //uint8_t const cbInstrMax = RT_MIN(pTb->aRanges[idxRange].cbOpcodes - offRange, 15);
9302 uint8_t const cbInstrMax = RT_MIN(cbOpcodes - offOpcodes, 15);
9303 uint32_t cbInstr = 1;
9304 int rc = DISInstrWithPrefetchedBytes(GCPhysPc, enmGstCpuMode, DISOPTYPE_ALL,
9305 &pTb->pabOpcodes[offOpcodes], cbInstrMax,
9306 iemNativeDisasReadBytesDummy, NULL, &Dis, &cbInstr);
9307 if (RT_SUCCESS(rc))
9308 {
9309 size_t cch = DISFormatYasmEx(&Dis, szDisBuf, sizeof(szDisBuf),
9310 DIS_FMT_FLAGS_BYTES_WIDTH_MAKE(10) | DIS_FMT_FLAGS_BYTES_LEFT
9311 | DIS_FMT_FLAGS_RELATIVE_BRANCH | DIS_FMT_FLAGS_C_HEX,
9312 NULL /*pfnGetSymbol*/, NULL /*pvUser*/);
9313
9314 static unsigned const s_offMarker = 55;
9315 static char const s_szMarker[] = " ; <--- guest";
9316 if (cch < s_offMarker)
9317 {
9318 memset(&szDisBuf[cch], ' ', s_offMarker - cch);
9319 cch = s_offMarker;
9320 }
9321 if (cch + sizeof(s_szMarker) <= sizeof(szDisBuf))
9322 memcpy(&szDisBuf[cch], s_szMarker, sizeof(s_szMarker));
9323
9324 pHlp->pfnPrintf(pHlp, "\n %%%%%RGp: %s #%u\n", GCPhysPc, szDisBuf, idxGuestInstr);
9325 }
9326 else
9327 {
9328 pHlp->pfnPrintf(pHlp, "\n %%%%%RGp: %.*Rhxs - guest disassembly failure %Rrc\n",
9329 GCPhysPc, cbInstrMax, &pTb->pabOpcodes[offOpcodes], rc);
9330 cbInstr = 1;
9331 }
9332 idxGuestInstr++;
9333 GCPhysPc += cbInstr;
9334 offOpcodes += cbInstr;
9335 offRange += cbInstr;
9336 continue;
9337 }
9338
9339 case kIemTbDbgEntryType_ThreadedCall:
9340 pHlp->pfnPrintf(pHlp,
9341 " Call #%u to %s (%u args) - %s\n",
9342 idxThreadedCall,
9343 g_apszIemThreadedFunctions[pDbgInfo->aEntries[iDbgEntry].ThreadedCall.enmCall],
9344 g_acIemThreadedFunctionUsedArgs[pDbgInfo->aEntries[iDbgEntry].ThreadedCall.enmCall],
9345 pDbgInfo->aEntries[iDbgEntry].ThreadedCall.fRecompiled ? "recompiled" : "todo");
9346 idxThreadedCall++;
9347 continue;
9348
9349 case kIemTbDbgEntryType_GuestRegShadowing:
9350 {
9351 PCIEMTBDBGENTRY const pEntry = &pDbgInfo->aEntries[iDbgEntry];
9352 const char * const pszGstReg = g_aGstShadowInfo[pEntry->GuestRegShadowing.idxGstReg].pszName;
9353 if (pEntry->GuestRegShadowing.idxHstReg == UINT8_MAX)
9354 pHlp->pfnPrintf(pHlp, " Guest register %s != host register %s\n", pszGstReg,
9355 g_apszIemNativeHstRegNames[pEntry->GuestRegShadowing.idxHstRegPrev]);
9356 else if (pEntry->GuestRegShadowing.idxHstRegPrev == UINT8_MAX)
9357 pHlp->pfnPrintf(pHlp, " Guest register %s == host register %s \n", pszGstReg,
9358 g_apszIemNativeHstRegNames[pEntry->GuestRegShadowing.idxHstReg]);
9359 else
9360 pHlp->pfnPrintf(pHlp, " Guest register %s == host register %s (previously in %s)\n", pszGstReg,
9361 g_apszIemNativeHstRegNames[pEntry->GuestRegShadowing.idxHstReg],
9362 g_apszIemNativeHstRegNames[pEntry->GuestRegShadowing.idxHstRegPrev]);
9363 continue;
9364 }
9365
9366#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
9367 case kIemTbDbgEntryType_GuestSimdRegShadowing:
9368 {
9369 PCIEMTBDBGENTRY const pEntry = &pDbgInfo->aEntries[iDbgEntry];
9370 const char * const pszGstReg = g_aGstSimdShadowInfo[pEntry->GuestSimdRegShadowing.idxGstSimdReg].pszName;
9371 if (pEntry->GuestSimdRegShadowing.idxHstSimdReg == UINT8_MAX)
9372 pHlp->pfnPrintf(pHlp, " Guest SIMD register %s != host SIMD register %s\n", pszGstReg,
9373 g_apszIemNativeHstSimdRegNames[pEntry->GuestSimdRegShadowing.idxHstSimdRegPrev]);
9374 else if (pEntry->GuestSimdRegShadowing.idxHstSimdRegPrev == UINT8_MAX)
9375 pHlp->pfnPrintf(pHlp, " Guest SIMD register %s == host SIMD register %s\n", pszGstReg,
9376 g_apszIemNativeHstSimdRegNames[pEntry->GuestSimdRegShadowing.idxHstSimdReg]);
9377 else
9378 pHlp->pfnPrintf(pHlp, " Guest SIMD register %s == host SIMD register %s (previously in %s)\n", pszGstReg,
9379 g_apszIemNativeHstSimdRegNames[pEntry->GuestSimdRegShadowing.idxHstSimdReg],
9380 g_apszIemNativeHstSimdRegNames[pEntry->GuestSimdRegShadowing.idxHstSimdRegPrev]);
9381 continue;
9382 }
9383#endif
9384
9385 case kIemTbDbgEntryType_Label:
9386 {
9387 const char *pszName = iemNativeGetLabelName((IEMNATIVELABELTYPE)pDbgInfo->aEntries[iDbgEntry].Label.enmLabel);
9388 if (pDbgInfo->aEntries[iDbgEntry].Label.enmLabel >= kIemNativeLabelType_FirstWithMultipleInstances)
9389 {
9390 const char *pszComment = pDbgInfo->aEntries[iDbgEntry].Label.enmLabel == kIemNativeLabelType_Else
9391 ? " ; regs state restored pre-if-block" : "";
9392 pHlp->pfnPrintf(pHlp, " %s_%u:%s\n", pszName, pDbgInfo->aEntries[iDbgEntry].Label.uData, pszComment);
9393 }
9394 else
9395 pHlp->pfnPrintf(pHlp, " %s:\n", pszName);
9396 continue;
9397 }
9398
9399 case kIemTbDbgEntryType_NativeOffset:
9400 offDbgNativeNext = pDbgInfo->aEntries[iDbgEntry].NativeOffset.offNative;
9401 Assert(offDbgNativeNext >= offNative);
9402 break;
9403
9404#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
9405 case kIemTbDbgEntryType_DelayedPcUpdate:
9406 pHlp->pfnPrintf(pHlp, " Updating guest PC value by %u (cInstrSkipped=%u)\n",
9407 pDbgInfo->aEntries[iDbgEntry].DelayedPcUpdate.offPc,
9408 pDbgInfo->aEntries[iDbgEntry].DelayedPcUpdate.cInstrSkipped);
9409 continue;
9410#endif
9411
9412#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
9413 case kIemTbDbgEntryType_GuestRegDirty:
9414 {
9415 PCIEMTBDBGENTRY const pEntry = &pDbgInfo->aEntries[iDbgEntry];
9416 const char * const pszGstReg = pEntry->GuestRegDirty.fSimdReg
9417 ? g_aGstSimdShadowInfo[pEntry->GuestRegDirty.idxGstReg].pszName
9418 : g_aGstShadowInfo[pEntry->GuestRegDirty.idxGstReg].pszName;
9419 const char * const pszHstReg = pEntry->GuestRegDirty.fSimdReg
9420 ? g_apszIemNativeHstSimdRegNames[pEntry->GuestRegDirty.idxHstReg]
9421 : g_apszIemNativeHstRegNames[pEntry->GuestRegDirty.idxHstReg];
9422 pHlp->pfnPrintf(pHlp, " Guest register %s (shadowed by %s) is now marked dirty (intent)\n",
9423 pszGstReg, pszHstReg);
9424 continue;
9425 }
9426
9427 case kIemTbDbgEntryType_GuestRegWriteback:
9428 pHlp->pfnPrintf(pHlp, " Writing dirty %s registers (gst %#RX32)\n",
9429 pDbgInfo->aEntries[iDbgEntry].GuestRegWriteback.fSimdReg ? "SIMD" : "general",
9430 (uint64_t)pDbgInfo->aEntries[iDbgEntry].GuestRegWriteback.fGstReg
9431 << (pDbgInfo->aEntries[iDbgEntry].GuestRegWriteback.cShift * 25));
9432 continue;
9433#endif
9434
9435 default:
9436 AssertFailed();
9437 }
9438 iDbgEntry++;
9439 break;
9440 }
9441 }
9442
9443 /*
9444 * Disassemble the next native instruction.
9445 */
9446 PCIEMNATIVEINSTR const pNativeCur = &paNative[offNative];
9447# ifndef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
9448 uint32_t cbInstr = sizeof(paNative[0]);
9449 int const rc = DISInstr(pNativeCur, enmHstCpuMode, &Dis, &cbInstr);
9450 if (RT_SUCCESS(rc))
9451 {
9452# if defined(RT_ARCH_AMD64)
9453 if (Dis.pCurInstr->uOpcode == OP_NOP && cbInstr == 7) /* iemNativeEmitMarker */
9454 {
9455 uint32_t const uInfo = *(uint32_t const *)&Dis.Instr.ab[3];
9456 if (RT_HIWORD(uInfo) < kIemThreadedFunc_End)
9457 pHlp->pfnPrintf(pHlp, " %p: nop ; marker: call #%u to %s (%u args) - %s\n",
9458 pNativeCur, uInfo & 0x7fff, g_apszIemThreadedFunctions[RT_HIWORD(uInfo)],
9459 g_acIemThreadedFunctionUsedArgs[RT_HIWORD(uInfo)],
9460 uInfo & 0x8000 ? "recompiled" : "todo");
9461 else if ((uInfo & ~RT_BIT_32(31)) < RT_ELEMENTS(a_apszMarkers))
9462 pHlp->pfnPrintf(pHlp, " %p: nop ; marker: %s\n", pNativeCur, a_apszMarkers[uInfo & ~RT_BIT_32(31)]);
9463 else
9464 pHlp->pfnPrintf(pHlp, " %p: nop ; unknown marker: %#x (%d)\n", pNativeCur, uInfo, uInfo);
9465 }
9466 else
9467# endif
9468 {
9469 const char *pszAnnotation = NULL;
9470# ifdef RT_ARCH_AMD64
9471 DISFormatYasmEx(&Dis, szDisBuf, sizeof(szDisBuf),
9472 DIS_FMT_FLAGS_BYTES_WIDTH_MAKE(10) | DIS_FMT_FLAGS_BYTES_LEFT
9473 | DIS_FMT_FLAGS_RELATIVE_BRANCH | DIS_FMT_FLAGS_C_HEX,
9474 iemNativeDisasmGetSymbolCb, &SymCtx);
9475 PCDISOPPARAM pMemOp;
9476 if (DISUSE_IS_EFFECTIVE_ADDR(Dis.aParams[0].fUse))
9477 pMemOp = &Dis.aParams[0];
9478 else if (DISUSE_IS_EFFECTIVE_ADDR(Dis.aParams[1].fUse))
9479 pMemOp = &Dis.aParams[1];
9480 else if (DISUSE_IS_EFFECTIVE_ADDR(Dis.aParams[2].fUse))
9481 pMemOp = &Dis.aParams[2];
9482 else
9483 pMemOp = NULL;
9484 if ( pMemOp
9485 && pMemOp->x86.Base.idxGenReg == IEMNATIVE_REG_FIXED_PVMCPU
9486 && (pMemOp->fUse & (DISUSE_BASE | DISUSE_REG_GEN64)) == (DISUSE_BASE | DISUSE_REG_GEN64))
9487 pszAnnotation = iemNativeDbgVCpuOffsetToName(pMemOp->fUse & DISUSE_DISPLACEMENT32
9488 ? pMemOp->x86.uDisp.u32 : pMemOp->x86.uDisp.u8);
9489
9490# elif defined(RT_ARCH_ARM64)
9491 DISFormatArmV8Ex(&Dis, szDisBuf, sizeof(szDisBuf),
9492 DIS_FMT_FLAGS_BYTES_LEFT | DIS_FMT_FLAGS_RELATIVE_BRANCH | DIS_FMT_FLAGS_C_HEX,
9493 iemNativeDisasmGetSymbolCb, &SymCtx);
9494# else
9495# error "Port me"
9496# endif
9497 if (pszAnnotation)
9498 {
9499 static unsigned const s_offAnnotation = 55;
9500 size_t const cchAnnotation = strlen(pszAnnotation);
9501 size_t cchDis = strlen(szDisBuf);
9502 if (RT_MAX(cchDis, s_offAnnotation) + sizeof(" ; ") + cchAnnotation <= sizeof(szDisBuf))
9503 {
9504 if (cchDis < s_offAnnotation)
9505 {
9506 memset(&szDisBuf[cchDis], ' ', s_offAnnotation - cchDis);
9507 cchDis = s_offAnnotation;
9508 }
9509 szDisBuf[cchDis++] = ' ';
9510 szDisBuf[cchDis++] = ';';
9511 szDisBuf[cchDis++] = ' ';
9512 memcpy(&szDisBuf[cchDis], pszAnnotation, cchAnnotation + 1);
9513 }
9514 }
9515 pHlp->pfnPrintf(pHlp, " %p: %s\n", pNativeCur, szDisBuf);
9516 }
9517 }
9518 else
9519 {
9520# if defined(RT_ARCH_AMD64)
9521 pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs - disassembly failure %Rrc\n",
9522 pNativeCur, RT_MIN(cNative - offNative, 16), pNativeCur, rc);
9523# elif defined(RT_ARCH_ARM64)
9524 pHlp->pfnPrintf(pHlp, " %p: %#010RX32 - disassembly failure %Rrc\n", pNativeCur, *pNativeCur, rc);
9525# else
9526# error "Port me"
9527# endif
9528 cbInstr = sizeof(paNative[0]);
9529 }
9530 offNative += cbInstr / sizeof(paNative[0]);
9531
9532# else /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
9533 cs_insn *pInstr;
9534 size_t cInstrs = cs_disasm(hDisasm, (const uint8_t *)pNativeCur, (cNative - offNative) * sizeof(*pNativeCur),
9535 (uintptr_t)pNativeCur, 1, &pInstr);
9536 if (cInstrs > 0)
9537 {
9538 Assert(cInstrs == 1);
9539 const char * const pszAnnotation = iemNativeDisasmAnnotateCapstone(&SymCtx, pInstr, szDisBuf, sizeof(szDisBuf));
9540 size_t const cchOp = strlen(pInstr->op_str);
9541# if defined(RT_ARCH_AMD64)
9542 if (pszAnnotation)
9543 pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs %-7s %s%*s ; %s\n",
9544 pNativeCur, pInstr->size, pNativeCur, pInstr->mnemonic, pInstr->op_str,
9545 cchOp < 55 ? 55 - cchOp : 0, "", pszAnnotation);
9546 else
9547 pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs %-7s %s\n",
9548 pNativeCur, pInstr->size, pNativeCur, pInstr->mnemonic, pInstr->op_str);
9549
9550# else
9551 if (pszAnnotation)
9552 pHlp->pfnPrintf(pHlp, " %p: %#010RX32 %-7s %s%*s ; %s\n",
9553 pNativeCur, *pNativeCur, pInstr->mnemonic, pInstr->op_str,
9554 cchOp < 55 ? 55 - cchOp : 0, "", pszAnnotation);
9555 else
9556 pHlp->pfnPrintf(pHlp, " %p: %#010RX32 %-7s %s\n",
9557 pNativeCur, *pNativeCur, pInstr->mnemonic, pInstr->op_str);
9558# endif
9559 offNative += pInstr->size / sizeof(*pNativeCur);
9560 cs_free(pInstr, cInstrs);
9561 }
9562 else
9563 {
9564# if defined(RT_ARCH_AMD64)
9565 pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs - disassembly failure %d\n",
9566 pNativeCur, RT_MIN(cNative - offNative, 16), pNativeCur, cs_errno(hDisasm)));
9567# else
9568 pHlp->pfnPrintf(pHlp, " %p: %#010RX32 - disassembly failure %d\n", pNativeCur, *pNativeCur, cs_errno(hDisasm));
9569# endif
9570 offNative++;
9571 }
9572# endif /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
9573 }
9574 }
9575 else
9576#endif /* IEMNATIVE_WITH_TB_DEBUG_INFO */
9577 {
9578 /*
9579 * No debug info, just disassemble the x86 code and then the native code.
9580 *
9581 * First the guest code:
9582 */
9583 for (unsigned i = 0; i < pTb->cRanges; i++)
9584 {
9585 RTGCPHYS GCPhysPc = pTb->aRanges[i].offPhysPage
9586 + (pTb->aRanges[i].idxPhysPage == 0
9587 ? pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK
9588 : pTb->aGCPhysPages[pTb->aRanges[i].idxPhysPage - 1]);
9589 pHlp->pfnPrintf(pHlp, " Range #%u: GCPhysPc=%RGp LB %#x [idxPg=%d]\n",
9590 i, GCPhysPc, pTb->aRanges[i].cbOpcodes, pTb->aRanges[i].idxPhysPage);
9591 unsigned off = pTb->aRanges[i].offOpcodes;
9592 /** @todo this ain't working when crossing pages! */
9593 unsigned const cbOpcodes = pTb->aRanges[i].cbOpcodes + off;
9594 while (off < cbOpcodes)
9595 {
9596 uint32_t cbInstr = 1;
9597 int rc = DISInstrWithPrefetchedBytes(GCPhysPc, enmGstCpuMode, DISOPTYPE_ALL,
9598 &pTb->pabOpcodes[off], cbOpcodes - off,
9599 iemNativeDisasReadBytesDummy, NULL, &Dis, &cbInstr);
9600 if (RT_SUCCESS(rc))
9601 {
9602 DISFormatYasmEx(&Dis, szDisBuf, sizeof(szDisBuf),
9603 DIS_FMT_FLAGS_BYTES_WIDTH_MAKE(10) | DIS_FMT_FLAGS_BYTES_LEFT
9604 | DIS_FMT_FLAGS_RELATIVE_BRANCH | DIS_FMT_FLAGS_C_HEX,
9605 NULL /*pfnGetSymbol*/, NULL /*pvUser*/);
9606 pHlp->pfnPrintf(pHlp, " %%%%%RGp: %s\n", GCPhysPc, szDisBuf);
9607 GCPhysPc += cbInstr;
9608 off += cbInstr;
9609 }
9610 else
9611 {
9612 pHlp->pfnPrintf(pHlp, " %%%%%RGp: %.*Rhxs - disassembly failure %Rrc\n",
9613 GCPhysPc, cbOpcodes - off, &pTb->pabOpcodes[off], rc);
9614 break;
9615 }
9616 }
9617 }
9618
9619 /*
9620 * Then the native code:
9621 */
9622 pHlp->pfnPrintf(pHlp, " Native code %p L %#x\n", paNative, cNative);
9623 while (offNative < cNative)
9624 {
9625 PCIEMNATIVEINSTR const pNativeCur = &paNative[offNative];
9626# ifndef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
9627 uint32_t cbInstr = sizeof(paNative[0]);
9628 int const rc = DISInstr(pNativeCur, enmHstCpuMode, &Dis, &cbInstr);
9629 if (RT_SUCCESS(rc))
9630 {
9631# if defined(RT_ARCH_AMD64)
9632 if (Dis.pCurInstr->uOpcode == OP_NOP && cbInstr == 7) /* iemNativeEmitMarker */
9633 {
9634 uint32_t const uInfo = *(uint32_t const *)&Dis.Instr.ab[3];
9635 if (RT_HIWORD(uInfo) < kIemThreadedFunc_End)
9636 pHlp->pfnPrintf(pHlp, "\n %p: nop ; marker: call #%u to %s (%u args) - %s\n",
9637 pNativeCur, uInfo & 0x7fff, g_apszIemThreadedFunctions[RT_HIWORD(uInfo)],
9638 g_acIemThreadedFunctionUsedArgs[RT_HIWORD(uInfo)],
9639 uInfo & 0x8000 ? "recompiled" : "todo");
9640 else if ((uInfo & ~RT_BIT_32(31)) < RT_ELEMENTS(a_apszMarkers))
9641 pHlp->pfnPrintf(pHlp, " %p: nop ; marker: %s\n", pNativeCur, a_apszMarkers[uInfo & ~RT_BIT_32(31)]);
9642 else
9643 pHlp->pfnPrintf(pHlp, " %p: nop ; unknown marker: %#x (%d)\n", pNativeCur, uInfo, uInfo);
9644 }
9645 else
9646# endif
9647 {
9648# ifdef RT_ARCH_AMD64
9649 DISFormatYasmEx(&Dis, szDisBuf, sizeof(szDisBuf),
9650 DIS_FMT_FLAGS_BYTES_WIDTH_MAKE(10) | DIS_FMT_FLAGS_BYTES_LEFT
9651 | DIS_FMT_FLAGS_RELATIVE_BRANCH | DIS_FMT_FLAGS_C_HEX,
9652 iemNativeDisasmGetSymbolCb, &SymCtx);
9653# elif defined(RT_ARCH_ARM64)
9654 DISFormatArmV8Ex(&Dis, szDisBuf, sizeof(szDisBuf),
9655 DIS_FMT_FLAGS_BYTES_LEFT | DIS_FMT_FLAGS_RELATIVE_BRANCH | DIS_FMT_FLAGS_C_HEX,
9656 iemNativeDisasmGetSymbolCb, &SymCtx);
9657# else
9658# error "Port me"
9659# endif
9660 pHlp->pfnPrintf(pHlp, " %p: %s\n", pNativeCur, szDisBuf);
9661 }
9662 }
9663 else
9664 {
9665# if defined(RT_ARCH_AMD64)
9666 pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs - disassembly failure %Rrc\n",
9667 pNativeCur, RT_MIN(cNative - offNative, 16), pNativeCur, rc);
9668# else
9669 pHlp->pfnPrintf(pHlp, " %p: %#010RX32 - disassembly failure %Rrc\n", pNativeCur, *pNativeCur, rc);
9670# endif
9671 cbInstr = sizeof(paNative[0]);
9672 }
9673 offNative += cbInstr / sizeof(paNative[0]);
9674
9675# else /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
9676 cs_insn *pInstr;
9677 size_t cInstrs = cs_disasm(hDisasm, (const uint8_t *)pNativeCur, (cNative - offNative) * sizeof(*pNativeCur),
9678 (uintptr_t)pNativeCur, 1, &pInstr);
9679 if (cInstrs > 0)
9680 {
9681 Assert(cInstrs == 1);
9682 const char * const pszAnnotation = iemNativeDisasmAnnotateCapstone(&SymCtx, pInstr, szDisBuf, sizeof(szDisBuf));
9683 size_t const cchOp = strlen(pInstr->op_str);
9684# if defined(RT_ARCH_AMD64)
9685 if (pszAnnotation)
9686 pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs %-7s %s%*s ; %s\n",
9687 pNativeCur, pInstr->size, pNativeCur, pInstr->mnemonic, pInstr->op_str,
9688 cchOp < 55 ? 55 - cchOp : 0, "", pszAnnotation);
9689 else
9690 pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs %-7s %s\n",
9691 pNativeCur, pInstr->size, pNativeCur, pInstr->mnemonic, pInstr->op_str);
9692
9693# else
9694 if (pszAnnotation)
9695 pHlp->pfnPrintf(pHlp, " %p: %#010RX32 %-7s %s%*s ; %s\n",
9696 pNativeCur, *pNativeCur, pInstr->mnemonic, pInstr->op_str,
9697 cchOp < 55 ? 55 - cchOp : 0, "", pszAnnotation);
9698 else
9699 pHlp->pfnPrintf(pHlp, " %p: %#010RX32 %-7s %s\n",
9700 pNativeCur, *pNativeCur, pInstr->mnemonic, pInstr->op_str);
9701# endif
9702 offNative += pInstr->size / sizeof(*pNativeCur);
9703 cs_free(pInstr, cInstrs);
9704 }
9705 else
9706 {
9707# if defined(RT_ARCH_AMD64)
9708 pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs - disassembly failure %d\n",
9709 pNativeCur, RT_MIN(cNative - offNative, 16), pNativeCur, cs_errno(hDisasm)));
9710# else
9711 pHlp->pfnPrintf(pHlp, " %p: %#010RX32 - disassembly failure %d\n", pNativeCur, *pNativeCur, cs_errno(hDisasm));
9712# endif
9713 offNative++;
9714 }
9715# endif /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
9716 }
9717 }
9718
9719#ifdef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
9720 /* Cleanup. */
9721 cs_close(&hDisasm);
9722#endif
9723}
9724
9725
9726#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
9727
9728/** Emit alignment padding between labels / functions. */
9729DECL_INLINE_THROW(uint32_t)
9730iemNativeRecompileEmitAlignmentPadding(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fAlignMask)
9731{
9732 if (off & fAlignMask)
9733 {
9734 PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, fAlignMask + 1);
9735 while (off & fAlignMask)
9736# if defined(RT_ARCH_AMD64)
9737 pCodeBuf[off++] = 0xcc;
9738# elif defined(RT_ARCH_ARM64)
9739 pCodeBuf[off++] = Armv8A64MkInstrBrk(0xcccc);
9740# else
9741# error "port me"
9742# endif
9743 }
9744 return off;
9745}
9746
9747
9748/**
9749 * Called when a new chunk is allocate to emit common per-chunk code.
9750 *
9751 * Allocates a per-chunk context directly from the chunk itself and place the
9752 * common code there.
9753 *
9754 * @returns Pointer to the chunk context start.
9755 * @param pVCpu The cross context virtual CPU structure of the calling
9756 * thread.
9757 * @param idxChunk The index of the chunk being added and requiring a
9758 * common code context.
9759 */
9760DECLHIDDEN(PCIEMNATIVEPERCHUNKCTX) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk)
9761{
9762 /*
9763 * Allocate a new recompiler state (since we're likely to be called while
9764 * the default one is fully loaded already with a recompiled TB).
9765 *
9766 * This is a bit of overkill, but this isn't a frequently used code path.
9767 */
9768 PIEMRECOMPILERSTATE pReNative = iemNativeInit(pVCpu, NULL);
9769 AssertReturn(pReNative, NULL);
9770
9771# if defined(RT_ARCH_AMD64)
9772 uint32_t const fAlignMask = 15;
9773# elif defined(RT_ARCH_ARM64)
9774 uint32_t const fAlignMask = 31 / 4;
9775# else
9776# error "port me"
9777# endif
9778 uint32_t aoffLabels[kIemNativeLabelType_LastTbExit + 1] = {0};
9779 int rc = VINF_SUCCESS;
9780 uint32_t off = 0;
9781
9782 IEMNATIVE_TRY_SETJMP(pReNative, rc)
9783 {
9784 /*
9785 * Emit the epilog code.
9786 */
9787 aoffLabels[kIemNativeLabelType_Return] = off;
9788 off = iemNativeEmitCoreEpilog(pReNative, off);
9789
9790 /*
9791 * Generate special jump labels. All of these gets a copy of the epilog code.
9792 */
9793 static struct
9794 {
9795 IEMNATIVELABELTYPE enmExitReason;
9796 uint32_t (*pfnEmitCore)(PIEMRECOMPILERSTATE pReNative, uint32_t off);
9797 } const s_aSpecialWithEpilogs[] =
9798 {
9799 { kIemNativeLabelType_NonZeroRetOrPassUp, iemNativeEmitCoreRcFiddling },
9800 { kIemNativeLabelType_ReturnBreak, iemNativeEmitCoreReturnBreak },
9801 { kIemNativeLabelType_ReturnBreakFF, iemNativeEmitCoreReturnBreakFF },
9802 { kIemNativeLabelType_ReturnWithFlags, iemNativeEmitCoreReturnWithFlags },
9803 };
9804 for (uint32_t i = 0; i < RT_ELEMENTS(s_aSpecialWithEpilogs); i++)
9805 {
9806 off = iemNativeRecompileEmitAlignmentPadding(pReNative, off, fAlignMask);
9807 Assert(aoffLabels[s_aSpecialWithEpilogs[i].enmExitReason] == 0);
9808 aoffLabels[s_aSpecialWithEpilogs[i].enmExitReason] = off;
9809 off = s_aSpecialWithEpilogs[i].pfnEmitCore(pReNative, off);
9810 off = iemNativeEmitCoreEpilog(pReNative, off);
9811 }
9812
9813 /*
9814 * Do what iemNativeEmitReturnBreakViaLookup does.
9815 */
9816 static struct
9817 {
9818 IEMNATIVELABELTYPE enmExitReason;
9819 uintptr_t pfnHelper;
9820 } const s_aViaLookup[] =
9821 {
9822 { kIemNativeLabelType_ReturnBreakViaLookup,
9823 (uintptr_t)iemNativeHlpReturnBreakViaLookup<false /*a_fWithIrqCheck*/> },
9824 { kIemNativeLabelType_ReturnBreakViaLookupWithIrq,
9825 (uintptr_t)iemNativeHlpReturnBreakViaLookup<true /*a_fWithIrqCheck*/> },
9826 { kIemNativeLabelType_ReturnBreakViaLookupWithTlb,
9827 (uintptr_t)iemNativeHlpReturnBreakViaLookupWithTlb<false /*a_fWithIrqCheck*/> },
9828 { kIemNativeLabelType_ReturnBreakViaLookupWithTlbAndIrq,
9829 (uintptr_t)iemNativeHlpReturnBreakViaLookupWithTlb<true /*a_fWithIrqCheck*/> },
9830 };
9831 uint32_t const offReturnBreak = aoffLabels[kIemNativeLabelType_ReturnBreak]; Assert(offReturnBreak != 0);
9832 for (uint32_t i = 0; i < RT_ELEMENTS(s_aViaLookup); i++)
9833 {
9834 off = iemNativeRecompileEmitAlignmentPadding(pReNative, off, fAlignMask);
9835 Assert(aoffLabels[s_aViaLookup[i].enmExitReason] == 0);
9836 aoffLabels[s_aViaLookup[i].enmExitReason] = off;
9837 off = iemNativeEmitCoreViaLookupDoOne(pReNative, off, offReturnBreak, s_aViaLookup[i].pfnHelper);
9838 }
9839
9840 /*
9841 * Generate simple TB tail labels that just calls a help with a pVCpu
9842 * arg and either return or longjmps/throws a non-zero status.
9843 */
9844 typedef IEM_DECL_NATIVE_HLP_PTR(int, PFNIEMNATIVESIMPLETAILLABELCALL,(PVMCPUCC pVCpu));
9845 static struct
9846 {
9847 IEMNATIVELABELTYPE enmExitReason;
9848 bool fWithEpilog;
9849 PFNIEMNATIVESIMPLETAILLABELCALL pfnCallback;
9850 } const s_aSimpleTailLabels[] =
9851 {
9852 { kIemNativeLabelType_RaiseDe, false, iemNativeHlpExecRaiseDe },
9853 { kIemNativeLabelType_RaiseUd, false, iemNativeHlpExecRaiseUd },
9854 { kIemNativeLabelType_RaiseSseRelated, false, iemNativeHlpExecRaiseSseRelated },
9855 { kIemNativeLabelType_RaiseAvxRelated, false, iemNativeHlpExecRaiseAvxRelated },
9856 { kIemNativeLabelType_RaiseSseAvxFpRelated, false, iemNativeHlpExecRaiseSseAvxFpRelated },
9857 { kIemNativeLabelType_RaiseNm, false, iemNativeHlpExecRaiseNm },
9858 { kIemNativeLabelType_RaiseGp0, false, iemNativeHlpExecRaiseGp0 },
9859 { kIemNativeLabelType_RaiseMf, false, iemNativeHlpExecRaiseMf },
9860 { kIemNativeLabelType_RaiseXf, false, iemNativeHlpExecRaiseXf },
9861 { kIemNativeLabelType_ObsoleteTb, true, iemNativeHlpObsoleteTb },
9862 { kIemNativeLabelType_NeedCsLimChecking, true, iemNativeHlpNeedCsLimChecking },
9863 { kIemNativeLabelType_CheckBranchMiss, true, iemNativeHlpCheckBranchMiss },
9864 };
9865 for (uint32_t i = 0; i < RT_ELEMENTS(s_aSimpleTailLabels); i++)
9866 {
9867 off = iemNativeRecompileEmitAlignmentPadding(pReNative, off, fAlignMask);
9868 Assert(!aoffLabels[s_aSimpleTailLabels[i].enmExitReason]);
9869 aoffLabels[s_aSimpleTailLabels[i].enmExitReason] = off;
9870
9871 /* int pfnCallback(PVMCPUCC pVCpu) */
9872 off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
9873 off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)s_aSimpleTailLabels[i].pfnCallback);
9874
9875 /* jump back to the return sequence / generate a return sequence. */
9876 if (!s_aSimpleTailLabels[i].fWithEpilog)
9877 off = iemNativeEmitJmpToFixed(pReNative, off, aoffLabels[kIemNativeLabelType_Return]);
9878 else
9879 off = iemNativeEmitCoreEpilog(pReNative, off);
9880 }
9881
9882
9883# ifdef VBOX_STRICT
9884 /* Make sure we've generate code for all labels. */
9885 for (uint32_t i = kIemNativeLabelType_Invalid + 1; i < RT_ELEMENTS(aoffLabels); i++)
9886 Assert(aoffLabels[i] != 0 || i == kIemNativeLabelType_Return);
9887#endif
9888 }
9889 IEMNATIVE_CATCH_LONGJMP_BEGIN(pReNative, rc);
9890 {
9891 Log(("iemNativeRecompileAttachExecMemChunkCtx: Caught %Rrc while recompiling!\n", rc));
9892 iemNativeTerm(pReNative);
9893 return NULL;
9894 }
9895 IEMNATIVE_CATCH_LONGJMP_END(pReNative);
9896
9897 /*
9898 * Allocate memory for the context (first) and the common code (last).
9899 */
9900 PIEMNATIVEPERCHUNKCTX pCtx;
9901 uint32_t const cbCtx = RT_ALIGN_32(sizeof(*pCtx), 64);
9902 uint32_t const cbCode = off * sizeof(IEMNATIVEINSTR);
9903 PIEMNATIVEINSTR paFinalCommonCodeRx = NULL;
9904 pCtx = (PIEMNATIVEPERCHUNKCTX)iemExecMemAllocatorAllocFromChunk(pVCpu, idxChunk, cbCtx + cbCode, &paFinalCommonCodeRx);
9905 AssertLogRelMsgReturn(pCtx, ("cbCtx=%#x cbCode=%#x idxChunk=%#x\n", cbCtx, cbCode, idxChunk), NULL);
9906
9907 /*
9908 * Copy over the generated code.
9909 * There should be no fixups or labels defined here.
9910 */
9911 paFinalCommonCodeRx = (PIEMNATIVEINSTR)((uintptr_t)paFinalCommonCodeRx + cbCtx);
9912 memcpy((PIEMNATIVEINSTR)((uintptr_t)pCtx + cbCtx), pReNative->pInstrBuf, cbCode);
9913
9914 Assert(pReNative->cFixups == 0);
9915 Assert(pReNative->cLabels == 0);
9916
9917 /*
9918 * Initialize the context.
9919 */
9920 AssertCompile(kIemNativeLabelType_Invalid == 0);
9921 AssertCompile(RT_ELEMENTS(pCtx->apExitLabels) == RT_ELEMENTS(aoffLabels));
9922 pCtx->apExitLabels[kIemNativeLabelType_Invalid] = 0;
9923 for (uint32_t i = kIemNativeLabelType_Invalid + 1; i < RT_ELEMENTS(pCtx->apExitLabels); i++)
9924 {
9925 Assert(aoffLabels[i] != 0 || i == kIemNativeLabelType_Return);
9926 pCtx->apExitLabels[i] = &paFinalCommonCodeRx[aoffLabels[i]];
9927 Log10((" apExitLabels[%u]=%p %s\n", i, pCtx->apExitLabels[i], iemNativeGetLabelName((IEMNATIVELABELTYPE)i, true)));
9928 }
9929
9930 iemExecMemAllocatorReadyForUse(pVCpu, pCtx, cbCtx + cbCode);
9931
9932 iemNativeTerm(pReNative);
9933 return pCtx;
9934}
9935
9936#endif /* IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE */
9937
9938/**
9939 * Recompiles the given threaded TB into a native one.
9940 *
9941 * In case of failure the translation block will be returned as-is.
9942 *
9943 * @returns pTb.
9944 * @param pVCpu The cross context virtual CPU structure of the calling
9945 * thread.
9946 * @param pTb The threaded translation to recompile to native.
9947 */
9948DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT
9949{
9950#if 0 /* For profiling the native recompiler code. */
9951l_profile_again:
9952#endif
9953 STAM_REL_PROFILE_START(&pVCpu->iem.s.StatNativeRecompilation, a);
9954
9955 /*
9956 * The first time thru, we allocate the recompiler state and save it,
9957 * all the other times we'll just reuse the saved one after a quick reset.
9958 */
9959 PIEMRECOMPILERSTATE pReNative = pVCpu->iem.s.pNativeRecompilerStateR3;
9960 if (RT_LIKELY(pReNative))
9961 iemNativeReInit(pReNative, pTb);
9962 else
9963 {
9964 pReNative = iemNativeInit(pVCpu, pTb);
9965 AssertReturn(pReNative, pTb);
9966 pVCpu->iem.s.pNativeRecompilerStateR3 = pReNative; /* save it */
9967 }
9968
9969#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
9970 /*
9971 * First do liveness analysis. This is done backwards.
9972 */
9973 {
9974 uint32_t idxCall = pTb->Thrd.cCalls;
9975 if (idxCall <= pReNative->cLivenessEntriesAlloc)
9976 { /* likely */ }
9977 else
9978 {
9979 uint32_t cAlloc = RT_MAX(pReNative->cLivenessEntriesAlloc, _4K);
9980 while (idxCall > cAlloc)
9981 cAlloc *= 2;
9982 void *pvNew = RTMemRealloc(pReNative->paLivenessEntries, sizeof(pReNative->paLivenessEntries[0]) * cAlloc);
9983 AssertReturn(pvNew, pTb);
9984 pReNative->paLivenessEntries = (PIEMLIVENESSENTRY)pvNew;
9985 pReNative->cLivenessEntriesAlloc = cAlloc;
9986 }
9987 AssertReturn(idxCall > 0, pTb);
9988 PIEMLIVENESSENTRY const paLivenessEntries = pReNative->paLivenessEntries;
9989
9990 /* The initial (final) entry. */
9991 idxCall--;
9992 IEM_LIVENESS_RAW_INIT_AS_UNUSED(&paLivenessEntries[idxCall]);
9993
9994 /* Loop backwards thru the calls and fill in the other entries. */
9995 PCIEMTHRDEDCALLENTRY pCallEntry = &pTb->Thrd.paCalls[idxCall];
9996 while (idxCall > 0)
9997 {
9998 PFNIEMNATIVELIVENESSFUNC const pfnLiveness = g_apfnIemNativeLivenessFunctions[pCallEntry->enmFunction];
9999 if (pfnLiveness)
10000 pfnLiveness(pCallEntry, &paLivenessEntries[idxCall], &paLivenessEntries[idxCall - 1]);
10001 else
10002 IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(&paLivenessEntries[idxCall - 1], &paLivenessEntries[idxCall]);
10003 pCallEntry--;
10004 idxCall--;
10005 }
10006
10007# ifdef VBOX_WITH_STATISTICS
10008 /* Check if there are any EFLAGS optimization to be had here. This requires someone settings them
10009 to 'clobbered' rather that 'input'. */
10010 /** @todo */
10011# endif
10012 }
10013#endif
10014
10015 /*
10016 * Recompiling and emitting code is done using try/throw/catch or setjmp/longjmp
10017 * for aborting if an error happens.
10018 */
10019 uint32_t cCallsLeft = pTb->Thrd.cCalls;
10020#ifdef LOG_ENABLED
10021 uint32_t const cCallsOrg = cCallsLeft;
10022#endif
10023 uint32_t off = 0;
10024 int rc = VINF_SUCCESS;
10025 IEMNATIVE_TRY_SETJMP(pReNative, rc)
10026 {
10027#ifndef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON
10028 /*
10029 * Emit prolog code (fixed).
10030 */
10031 off = iemNativeEmitProlog(pReNative, off);
10032#endif
10033
10034 /*
10035 * Convert the calls to native code.
10036 */
10037#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
10038 int32_t iGstInstr = -1;
10039#endif
10040#ifndef VBOX_WITHOUT_RELEASE_STATISTICS
10041 uint32_t cThreadedCalls = 0;
10042 uint32_t cRecompiledCalls = 0;
10043#endif
10044#if defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) || defined(IEM_WITH_INTRA_TB_JUMPS) || defined(VBOX_STRICT) || defined(LOG_ENABLED) || defined(VBOX_WITH_STATISTICS) || defined(IEMNATIVE_WITH_DELAYED_PC_UPDATING)
10045 uint32_t idxCurCall = 0;
10046#endif
10047 PCIEMTHRDEDCALLENTRY pCallEntry = pTb->Thrd.paCalls;
10048 pReNative->fExec = pTb->fFlags & IEMTB_F_IEM_F_MASK;
10049 while (cCallsLeft-- > 0)
10050 {
10051 PFNIEMNATIVERECOMPFUNC const pfnRecom = g_apfnIemNativeRecompileFunctions[pCallEntry->enmFunction];
10052#if defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) || defined(VBOX_WITH_STATISTICS) || defined(IEMNATIVE_WITH_DELAYED_PC_UPDATING)
10053 pReNative->idxCurCall = idxCurCall;
10054#endif
10055
10056#ifdef IEM_WITH_INTRA_TB_JUMPS
10057 /*
10058 * Define label for jump targets (currently only the first entry).
10059 */
10060 if (!(pCallEntry->fFlags & IEMTHREADEDCALLENTRY_F_JUMP_TARGET))
10061 { /* likely */ }
10062 else
10063 {
10064 iemNativeLabelCreate(pReNative, kIemNativeLabelType_LoopJumpTarget, off);
10065 Assert(idxCurCall == 0); /** @todo when jumping elsewhere, we have to save the register state. */
10066 }
10067#endif
10068
10069 /*
10070 * Debug info, assembly markup and statistics.
10071 */
10072#if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) || !defined(IEMNATIVE_WITH_BLTIN_CHECKMODE)
10073 if (pCallEntry->enmFunction == kIemThreadedFunc_BltIn_CheckMode)
10074 pReNative->fExec = pCallEntry->auParams[0] & IEMTB_F_IEM_F_MASK;
10075#endif
10076#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
10077 iemNativeDbgInfoAddNativeOffset(pReNative, off);
10078 if (iGstInstr < (int32_t)pCallEntry->idxInstr)
10079 {
10080 if (iGstInstr < (int32_t)pTb->cInstructions)
10081 iemNativeDbgInfoAddGuestInstruction(pReNative, pReNative->fExec);
10082 else
10083 Assert(iGstInstr == pTb->cInstructions);
10084 iGstInstr = pCallEntry->idxInstr;
10085 }
10086 iemNativeDbgInfoAddThreadedCall(pReNative, (IEMTHREADEDFUNCS)pCallEntry->enmFunction, pfnRecom != NULL);
10087#endif
10088#if defined(VBOX_STRICT)
10089 off = iemNativeEmitMarker(pReNative, off,
10090 RT_MAKE_U32(idxCurCall | (pfnRecom ? 0x8000 : 0), pCallEntry->enmFunction));
10091#endif
10092#if defined(VBOX_STRICT)
10093 iemNativeRegAssertSanity(pReNative);
10094#endif
10095#ifdef VBOX_WITH_STATISTICS
10096 off = iemNativeEmitThreadCallStats(pReNative, off, pCallEntry);
10097#endif
10098
10099#if 0
10100 if ( pTb->GCPhysPc == 0x00000000000c1240
10101 && idxCurCall == 67)
10102 off = iemNativeEmitBrk(pReNative, off, 0xf000);
10103#endif
10104
10105 /*
10106 * Actual work.
10107 */
10108 Log2(("%u[%u]: %s%s (off=%#x)\n", idxCurCall, pCallEntry->idxInstr,
10109 g_apszIemThreadedFunctions[pCallEntry->enmFunction], pfnRecom ? "(recompiled)" : "(todo)", off));
10110 if (pfnRecom) /** @todo stats on this. */
10111 {
10112 off = pfnRecom(pReNative, off, pCallEntry);
10113 STAM_REL_STATS({cRecompiledCalls++;});
10114 }
10115 else
10116 {
10117 off = iemNativeEmitThreadedCall(pReNative, off, pCallEntry);
10118 STAM_REL_STATS({cThreadedCalls++;});
10119 }
10120 Assert(off <= pReNative->cInstrBufAlloc);
10121 Assert(pReNative->cCondDepth == 0);
10122
10123#if defined(LOG_ENABLED) && defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS)
10124 if (LogIs2Enabled())
10125 {
10126 PCIEMLIVENESSENTRY pLivenessEntry = &pReNative->paLivenessEntries[idxCurCall];
10127# ifndef IEMLIVENESS_EXTENDED_LAYOUT
10128 static const char s_achState[] = "CUXI";
10129# else
10130 static const char s_achState[] = "UxRrWwMmCcQqKkNn";
10131# endif
10132
10133 char szGpr[17];
10134 for (unsigned i = 0; i < 16; i++)
10135 szGpr[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_GprFirst)];
10136 szGpr[16] = '\0';
10137
10138 char szSegBase[X86_SREG_COUNT + 1];
10139 char szSegLimit[X86_SREG_COUNT + 1];
10140 char szSegAttrib[X86_SREG_COUNT + 1];
10141 char szSegSel[X86_SREG_COUNT + 1];
10142 for (unsigned i = 0; i < X86_SREG_COUNT; i++)
10143 {
10144 szSegBase[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_SegBaseFirst)];
10145 szSegAttrib[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_SegAttribFirst)];
10146 szSegLimit[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_SegLimitFirst)];
10147 szSegSel[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_SegSelFirst)];
10148 }
10149 szSegBase[X86_SREG_COUNT] = szSegAttrib[X86_SREG_COUNT] = szSegLimit[X86_SREG_COUNT]
10150 = szSegSel[X86_SREG_COUNT] = '\0';
10151
10152 char szEFlags[8];
10153 for (unsigned i = 0; i < 7; i++)
10154 szEFlags[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_EFlags)];
10155 szEFlags[7] = '\0';
10156
10157 Log2(("liveness: grp=%s segbase=%s segattr=%s seglim=%s segsel=%s efl=%s\n",
10158 szGpr, szSegBase, szSegAttrib, szSegLimit, szSegSel, szEFlags));
10159 }
10160#endif
10161
10162 /*
10163 * Advance.
10164 */
10165 pCallEntry++;
10166#if defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) || defined(IEM_WITH_INTRA_TB_JUMPS) || defined(VBOX_STRICT) || defined(LOG_ENABLED) || defined(VBOX_WITH_STATISTICS) || defined(IEMNATIVE_WITH_DELAYED_PC_UPDATING)
10167 idxCurCall++;
10168#endif
10169 }
10170
10171 STAM_REL_PROFILE_ADD_PERIOD(&pVCpu->iem.s.StatNativeCallsRecompiled, cRecompiledCalls);
10172 STAM_REL_PROFILE_ADD_PERIOD(&pVCpu->iem.s.StatNativeCallsThreaded, cThreadedCalls);
10173 if (!cThreadedCalls)
10174 STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeFullyRecompiledTbs);
10175
10176#ifdef VBOX_WITH_STATISTICS
10177 off = iemNativeEmitNativeTbExitStats(pReNative, off, RT_UOFFSETOF(VMCPUCC, iem.s.StatNativeTbFinished));
10178#endif
10179
10180 /* Flush any pending writes before returning from the last instruction (RIP updates, etc.). */
10181 off = iemNativeRegFlushPendingWrites(pReNative, off);
10182
10183 /*
10184 * Successful return, so clear the return register (eax, w0).
10185 */
10186 off = iemNativeEmitGprZero(pReNative, off, IEMNATIVE_CALL_RET_GREG);
10187
10188#ifndef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
10189 /*
10190 * Emit the epilog code.
10191 */
10192 uint32_t idxReturnLabel;
10193 off = iemNativeEmitEpilog(pReNative, off, &idxReturnLabel);
10194#else
10195 /*
10196 * Jump to the common per-chunk epilog code.
10197 */
10198 //off = iemNativeEmitBrk(pReNative, off, 0x1227);
10199 off = iemNativeEmitTbExit(pReNative, off, kIemNativeLabelType_Return);
10200#endif
10201
10202#ifndef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
10203 /*
10204 * Generate special jump labels.
10205 */
10206 off = iemNativeEmitRcFiddling(pReNative, off, idxReturnLabel);
10207
10208 bool const fReturnBreakViaLookup = RT_BOOL( pReNative->bmLabelTypes
10209 & ( RT_BIT_64(kIemNativeLabelType_ReturnBreakViaLookup)
10210 | RT_BIT_64(kIemNativeLabelType_ReturnBreakViaLookupWithIrq)
10211 | RT_BIT_64(kIemNativeLabelType_ReturnBreakViaLookupWithTlb)
10212 | RT_BIT_64(kIemNativeLabelType_ReturnBreakViaLookupWithTlbAndIrq)));
10213 if (fReturnBreakViaLookup)
10214 {
10215 uint32_t const idxReturnBreakLabel = iemNativeLabelCreate(pReNative, kIemNativeLabelType_ReturnBreak);
10216 off = iemNativeEmitReturnBreak(pReNative, off, idxReturnLabel);
10217 off = iemNativeEmitReturnBreakViaLookup(pReNative, off, idxReturnBreakLabel);
10218 }
10219 else if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_ReturnBreak))
10220 off = iemNativeEmitReturnBreak(pReNative, off, idxReturnLabel);
10221
10222 if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_ReturnBreakFF))
10223 off = iemNativeEmitReturnBreakFF(pReNative, off, idxReturnLabel);
10224
10225 if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_ReturnWithFlags))
10226 off = iemNativeEmitReturnWithFlags(pReNative, off, idxReturnLabel);
10227
10228 /*
10229 * Generate simple TB tail labels that just calls a help with a pVCpu
10230 * arg and either return or longjmps/throws a non-zero status.
10231 *
10232 * The array entries must be ordered by enmLabel value so we can index
10233 * using fTailLabels bit numbers.
10234 */
10235 typedef IEM_DECL_NATIVE_HLP_PTR(int, PFNIEMNATIVESIMPLETAILLABELCALL,(PVMCPUCC pVCpu));
10236 static struct
10237 {
10238 IEMNATIVELABELTYPE enmLabel;
10239 PFNIEMNATIVESIMPLETAILLABELCALL pfnCallback;
10240 } const g_aSimpleTailLabels[] =
10241 {
10242 { kIemNativeLabelType_Invalid, NULL },
10243 { kIemNativeLabelType_RaiseDe, iemNativeHlpExecRaiseDe },
10244 { kIemNativeLabelType_RaiseUd, iemNativeHlpExecRaiseUd },
10245 { kIemNativeLabelType_RaiseSseRelated, iemNativeHlpExecRaiseSseRelated },
10246 { kIemNativeLabelType_RaiseAvxRelated, iemNativeHlpExecRaiseAvxRelated },
10247 { kIemNativeLabelType_RaiseSseAvxFpRelated, iemNativeHlpExecRaiseSseAvxFpRelated },
10248 { kIemNativeLabelType_RaiseNm, iemNativeHlpExecRaiseNm },
10249 { kIemNativeLabelType_RaiseGp0, iemNativeHlpExecRaiseGp0 },
10250 { kIemNativeLabelType_RaiseMf, iemNativeHlpExecRaiseMf },
10251 { kIemNativeLabelType_RaiseXf, iemNativeHlpExecRaiseXf },
10252 { kIemNativeLabelType_ObsoleteTb, iemNativeHlpObsoleteTb },
10253 { kIemNativeLabelType_NeedCsLimChecking, iemNativeHlpNeedCsLimChecking },
10254 { kIemNativeLabelType_CheckBranchMiss, iemNativeHlpCheckBranchMiss },
10255 };
10256
10257 AssertCompile(RT_ELEMENTS(g_aSimpleTailLabels) == (unsigned)kIemNativeLabelType_LastSimple + 1U);
10258 AssertCompile(kIemNativeLabelType_Invalid == 0);
10259 uint64_t fTailLabels = pReNative->bmLabelTypes & (RT_BIT_64(kIemNativeLabelType_LastSimple + 1U) - 2U);
10260 if (fTailLabels)
10261 {
10262 do
10263 {
10264 IEMNATIVELABELTYPE const enmLabel = (IEMNATIVELABELTYPE)(ASMBitFirstSetU64(fTailLabels) - 1U);
10265 fTailLabels &= ~RT_BIT_64(enmLabel);
10266 Assert(g_aSimpleTailLabels[enmLabel].enmLabel == enmLabel);
10267
10268 uint32_t const idxLabel = iemNativeLabelFind(pReNative, enmLabel);
10269 Assert(idxLabel != UINT32_MAX);
10270 if (idxLabel != UINT32_MAX)
10271 {
10272 iemNativeLabelDefine(pReNative, idxLabel, off);
10273
10274 /* int pfnCallback(PVMCPUCC pVCpu) */
10275 off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
10276 off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)g_aSimpleTailLabels[enmLabel].pfnCallback);
10277
10278 /* jump back to the return sequence. */
10279 off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
10280 }
10281
10282 } while (fTailLabels);
10283 }
10284
10285#else /* IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE */
10286 /*
10287 * Generate tail labels with jumps to the common per-chunk code.
10288 */
10289# ifndef RT_ARCH_AMD64
10290 Assert(!(pReNative->bmLabelTypes & (RT_BIT_64(kIemNativeLabelType_Return) | RT_BIT_64(kIemNativeLabelType_Invalid))));
10291 AssertCompile(kIemNativeLabelType_Invalid == 0);
10292 uint64_t fTailLabels = pReNative->bmLabelTypes & (RT_BIT_64(kIemNativeLabelType_LastTbExit + 1U) - 2U);
10293 if (fTailLabels)
10294 {
10295 do
10296 {
10297 IEMNATIVELABELTYPE const enmLabel = (IEMNATIVELABELTYPE)(ASMBitFirstSetU64(fTailLabels) - 1U);
10298 fTailLabels &= ~RT_BIT_64(enmLabel);
10299
10300 uint32_t const idxLabel = iemNativeLabelFind(pReNative, enmLabel);
10301 AssertContinue(idxLabel != UINT32_MAX);
10302 iemNativeLabelDefine(pReNative, idxLabel, off);
10303 off = iemNativeEmitTbExit(pReNative, off, enmLabel);
10304 } while (fTailLabels);
10305 }
10306# else
10307 Assert(!(pReNative->bmLabelTypes & (RT_BIT_64(kIemNativeLabelType_LastTbExit + 1) - 1U))); /* Should not be used! */
10308# endif
10309#endif /* IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE */
10310 }
10311 IEMNATIVE_CATCH_LONGJMP_BEGIN(pReNative, rc);
10312 {
10313 Log(("iemNativeRecompile: Caught %Rrc while recompiling!\n", rc));
10314 return pTb;
10315 }
10316 IEMNATIVE_CATCH_LONGJMP_END(pReNative);
10317 Assert(off <= pReNative->cInstrBufAlloc);
10318
10319 /*
10320 * Make sure all labels has been defined.
10321 */
10322 PIEMNATIVELABEL const paLabels = pReNative->paLabels;
10323#ifdef VBOX_STRICT
10324 uint32_t const cLabels = pReNative->cLabels;
10325 for (uint32_t i = 0; i < cLabels; i++)
10326 AssertMsgReturn(paLabels[i].off < off, ("i=%d enmType=%d\n", i, paLabels[i].enmType), pTb);
10327#endif
10328
10329#if 0 /* For profiling the native recompiler code. */
10330 if (pTb->Thrd.cCalls >= 136)
10331 {
10332 STAM_REL_PROFILE_STOP(&pVCpu->iem.s.StatNativeRecompilation, a);
10333 goto l_profile_again;
10334 }
10335#endif
10336
10337 /*
10338 * Allocate executable memory, copy over the code we've generated.
10339 */
10340 PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
10341 if (pTbAllocator->pDelayedFreeHead)
10342 iemTbAllocatorProcessDelayedFrees(pVCpu, pVCpu->iem.s.pTbAllocatorR3);
10343
10344 PIEMNATIVEINSTR paFinalInstrBufRx = NULL;
10345#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
10346 PCIEMNATIVEPERCHUNKCTX pCtx = NULL;
10347 PIEMNATIVEINSTR const paFinalInstrBuf = iemExecMemAllocatorAlloc(pVCpu, off * sizeof(IEMNATIVEINSTR), pTb,
10348 &paFinalInstrBufRx, &pCtx);
10349
10350#else
10351 PIEMNATIVEINSTR const paFinalInstrBuf = iemExecMemAllocatorAlloc(pVCpu, off * sizeof(IEMNATIVEINSTR), pTb,
10352 &paFinalInstrBufRx, NULL);
10353#endif
10354 AssertReturn(paFinalInstrBuf, pTb);
10355 memcpy(paFinalInstrBuf, pReNative->pInstrBuf, off * sizeof(paFinalInstrBuf[0]));
10356
10357 /*
10358 * Apply fixups.
10359 */
10360 PIEMNATIVEFIXUP const paFixups = pReNative->paFixups;
10361 uint32_t const cFixups = pReNative->cFixups;
10362 for (uint32_t i = 0; i < cFixups; i++)
10363 {
10364 Assert(paFixups[i].off < off);
10365 Assert(paFixups[i].idxLabel < cLabels);
10366 AssertMsg(paLabels[paFixups[i].idxLabel].off < off,
10367 ("idxLabel=%d enmType=%d off=%#x (max %#x)\n", paFixups[i].idxLabel,
10368 paLabels[paFixups[i].idxLabel].enmType, paLabels[paFixups[i].idxLabel].off, off));
10369 RTPTRUNION const Ptr = { &paFinalInstrBuf[paFixups[i].off] };
10370 switch (paFixups[i].enmType)
10371 {
10372#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
10373 case kIemNativeFixupType_Rel32:
10374 Assert(paFixups[i].off + 4 <= off);
10375 *Ptr.pi32 = paLabels[paFixups[i].idxLabel].off - paFixups[i].off + paFixups[i].offAddend;
10376 continue;
10377
10378#elif defined(RT_ARCH_ARM64)
10379 case kIemNativeFixupType_RelImm26At0:
10380 {
10381 Assert(paFixups[i].off < off);
10382 int32_t const offDisp = paLabels[paFixups[i].idxLabel].off - paFixups[i].off + paFixups[i].offAddend;
10383 Assert(offDisp >= -33554432 && offDisp < 33554432);
10384 *Ptr.pu32 = (*Ptr.pu32 & UINT32_C(0xfc000000)) | ((uint32_t)offDisp & UINT32_C(0x03ffffff));
10385 continue;
10386 }
10387
10388 case kIemNativeFixupType_RelImm19At5:
10389 {
10390 Assert(paFixups[i].off < off);
10391 int32_t const offDisp = paLabels[paFixups[i].idxLabel].off - paFixups[i].off + paFixups[i].offAddend;
10392 Assert(offDisp >= -262144 && offDisp < 262144);
10393 *Ptr.pu32 = (*Ptr.pu32 & UINT32_C(0xff00001f)) | (((uint32_t)offDisp & UINT32_C(0x0007ffff)) << 5);
10394 continue;
10395 }
10396
10397 case kIemNativeFixupType_RelImm14At5:
10398 {
10399 Assert(paFixups[i].off < off);
10400 int32_t const offDisp = paLabels[paFixups[i].idxLabel].off - paFixups[i].off + paFixups[i].offAddend;
10401 Assert(offDisp >= -8192 && offDisp < 8192);
10402 *Ptr.pu32 = (*Ptr.pu32 & UINT32_C(0xfff8001f)) | (((uint32_t)offDisp & UINT32_C(0x00003fff)) << 5);
10403 continue;
10404 }
10405
10406#endif
10407 case kIemNativeFixupType_Invalid:
10408 case kIemNativeFixupType_End:
10409 break;
10410 }
10411 AssertFailed();
10412 }
10413
10414#ifdef IEMNATIVE_WITH_RECOMPILER_PER_CHUNK_TAIL_CODE
10415 /*
10416 * Apply TB exit fixups.
10417 */
10418 PIEMNATIVEEXITFIXUP const paTbExitFixups = pReNative->paTbExitFixups;
10419 uint32_t const cTbExitFixups = pReNative->cTbExitFixups;
10420 for (uint32_t i = 0; i < cTbExitFixups; i++)
10421 {
10422 Assert(paTbExitFixups[i].off < off);
10423 Assert(IEMNATIVELABELTYPE_IS_EXIT_REASON(paTbExitFixups[i].enmExitReason));
10424 RTPTRUNION const Ptr = { &paFinalInstrBuf[paTbExitFixups[i].off] };
10425
10426# if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
10427 Assert(paTbExitFixups[i].off + 4 <= off);
10428 intptr_t const offDisp = pCtx->apExitLabels[paTbExitFixups[i].enmExitReason] - &paFinalInstrBufRx[paTbExitFixups[i].off + 4];
10429 Assert(offDisp >= INT32_MIN && offDisp <= INT32_MAX);
10430 *Ptr.pi32 = (int32_t)offDisp;
10431
10432# elif defined(RT_ARCH_ARM64)
10433 intptr_t const offDisp = pCtx->apExitLabels[paTbExitFixups[i].enmExitReason] - &paFinalInstrBufRx[paTbExitFixups[i].off];
10434 Assert(offDisp >= -33554432 && offDisp < 33554432);
10435 *Ptr.pu32 = (*Ptr.pu32 & UINT32_C(0xfc000000)) | ((uint32_t)offDisp & UINT32_C(0x03ffffff));
10436
10437# else
10438# error "Port me!"
10439# endif
10440 }
10441#endif
10442
10443 iemExecMemAllocatorReadyForUse(pVCpu, paFinalInstrBufRx, off * sizeof(IEMNATIVEINSTR));
10444 STAM_REL_PROFILE_ADD_PERIOD(&pVCpu->iem.s.StatTbNativeCode, off * sizeof(IEMNATIVEINSTR));
10445
10446 /*
10447 * Convert the translation block.
10448 */
10449 RTMemFree(pTb->Thrd.paCalls);
10450 pTb->Native.paInstructions = paFinalInstrBufRx;
10451 pTb->Native.cInstructions = off;
10452 pTb->fFlags = (pTb->fFlags & ~IEMTB_F_TYPE_MASK) | IEMTB_F_TYPE_NATIVE;
10453#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
10454 pReNative->pDbgInfo->FlatPc = pTb->FlatPc;
10455 pTb->pDbgInfo = (PIEMTBDBG)RTMemDup(pReNative->pDbgInfo, /* non-fatal, so not return check. */
10456 RT_UOFFSETOF_DYN(IEMTBDBG, aEntries[pReNative->pDbgInfo->cEntries]));
10457#endif
10458
10459 Assert(pTbAllocator->cThreadedTbs > 0);
10460 pTbAllocator->cThreadedTbs -= 1;
10461 pTbAllocator->cNativeTbs += 1;
10462 Assert(pTbAllocator->cNativeTbs <= pTbAllocator->cTotalTbs);
10463
10464#ifdef LOG_ENABLED
10465 /*
10466 * Disassemble to the log if enabled.
10467 */
10468 if (LogIs3Enabled())
10469 {
10470 Log3(("----------------------------------------- %d calls ---------------------------------------\n", cCallsOrg));
10471 iemNativeDisassembleTb(pVCpu, pTb, DBGFR3InfoLogHlp());
10472# if defined(DEBUG_bird) || defined(DEBUG_aeichner)
10473 RTLogFlush(NULL);
10474# endif
10475 }
10476#endif
10477 /*iemNativeDisassembleTb(pTb, DBGFR3InfoLogRelHlp());*/
10478
10479 STAM_REL_PROFILE_STOP(&pVCpu->iem.s.StatNativeRecompilation, a);
10480 return pTb;
10481}
10482
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