VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA-arm64.S@ 105184

Last change on this file since 105184 was 104798, checked in by vboxsync, 9 months ago

VMM/IEM: Introduce IEMNATIVE_WITH_RECOMPILER_EPILOGUE_SINGLETON as an experiment to unify the epilog for all TBs into single instance, enabling it only for arm64 right now, bugref:10677

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 8.2 KB
Line 
1/* $Id: IEMAllN8veHlpA-arm64.S 104798 2024-05-28 07:04:30Z vboxsync $ */
2/** @file
3 * IEM - Native Recompiler Assembly Helpers, ARM64 variant.
4 */
5
6/*
7 * Copyright (C) 2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#include <iprt/asmdefs-arm.h>
33#include <iprt/armv8.h>
34
35#include "IEMInternal.h"
36#include "IEMN8veRecompiler.h"
37#include "IEMAssemblyOffsets.h"
38
39
40/*********************************************************************************************************************************
41* Defined Constants And Macros *
42*********************************************************************************************************************************/
43#define IEM_HLP_FUNCTION_ALIGNMENT 0x20
44
45
46/*********************************************************************************************************************************
47* External Functions *
48*********************************************************************************************************************************/
49.extern NAME(iemThreadedFunc_BltIn_LogCpuStateWorker)
50
51
52BEGINCODE
53
54/**
55 * This is the common prologue of a TB, saving all volatile registers
56 * and creating the stack frame for saving temporary values.
57 *
58 * @param pVCpu (x0) The cross-context vCPU structure pointer.
59 * @param pCpumCtx (x1) The cross-context CPUM context structure pointer.
60 * @param pTbStart (x2) The TB instruction start pointer.
61 */
62ALIGNCODE(IEM_HLP_FUNCTION_ALIGNMENT)
63BEGINPROC_HIDDEN iemNativeTbEntry
64#ifdef RT_OS_DARWIN
65 pacibsp
66#endif
67 /*
68 * We set up a stack frame exactly like on x86, only we have to push the
69 * return address our selves here. We save all non-volatile registers.
70 */
71 /* Allocate space for saving registers and place x19+x20 at the bottom. */
72 stp x19, x20, [sp, #-IEMNATIVE_FRAME_SAVE_REG_SIZE]!
73 /* Save x21 thru x28 (SP remains unchanged). */
74 stp x21, x22, [sp, #0x10]
75 stp x23, x24, [sp, #0x20]
76 stp x25, x26, [sp, #0x30]
77 stp x27, x28, [sp, #0x40]
78 /* Save the BP (x29) and LR (x30) (ret address) registers at the top of the frame. */
79 stp x29, x30, [sp, #0x50]
80 /* Set BP to point to the old BP stack address */
81 add x29, sp, #(IEMNATIVE_FRAME_SAVE_REG_SIZE - 16)
82 /* Allocate the variable area from SP. */
83 sub sp, sp, #IEMNATIVE_FRAME_VAR_SIZE
84 /* Load the fixed register values from parameters. */
85 mov IEMNATIVE_REG_FIXED_PVMCPU_ASM, x0
86 mov IEMNATIVE_REG_FIXED_PCPUMCTX_ASM, x1
87#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
88 /* Save the frame pointer to pvTbFramePointerR3 */
89 str x29, [IEMNATIVE_REG_FIXED_PVMCPU_ASM, #(VMCPU_OFF_iem + IEMCPU_OFF_pvTbFramePointerR3)]
90#endif
91
92 /*
93 * Everything is done, jump to the start of the TB.
94 */
95 br x2
96
97#ifdef IEMNATIVE_WITH_RECOMPILER_EPILOGUE_SINGLETON
98/**
99 * This is the common epilog for all TBs, restoring all volatile registers
100 * and cleaning up the stack frame. This is a direct jump target and not a
101 * real function to call using bl/blr.
102 */
103ALIGNCODE(IEM_HLP_FUNCTION_ALIGNMENT)
104BEGINPROC_HIDDEN iemNativeTbEpilog
105 ldp x19, x20, [sp, #IEMNATIVE_FRAME_VAR_SIZE]!
106 ldp x21, x22, [sp, #0x10]
107 ldp x23, x24, [sp, #0x20]
108 ldp x25, x26, [sp, #0x30]
109 ldp x27, x28, [sp, #0x40]
110 ldp x29, x30, [sp, #0x50]
111 add sp, sp, #IEMNATIVE_FRAME_SAVE_REG_SIZE
112# ifdef RT_OS_DARWIN
113 retab
114# else
115 ret
116# endif
117#endif
118
119
120/**
121 * This does the epilogue of a TB, given the RBP for the frame and eax value to return.
122 *
123 * @param pFrame (x0) The frame pointer.
124 * @param rc (w1) The return value.
125 *
126 * @note This doesn't really work for MSC since xmm6 thru xmm15 are non-volatile
127 * and since we don't save them in the TB prolog we'll potentially return
128 * with different values if any functions on the calling stack uses them
129 * as they're unlikely to restore them till they return.
130 *
131 * For the GCC calling convention all xmm registers are volatile and the
132 * only worry would be someone fiddling the control bits of MXCSR or FCW
133 * without restoring them. This is highly unlikely, unless we're doing
134 * it ourselves, I think.
135 */
136ALIGNCODE(IEM_HLP_FUNCTION_ALIGNMENT)
137BEGINPROC_HIDDEN iemNativeTbLongJmp
138 /*
139 * This must exactly match what iemNativeEmitEpilog does.
140 */
141 sub sp, x0, #0x50
142 ldp x19, x20, [sp, #0x00]
143 ldp x21, x22, [sp, #0x10]
144 ldp x23, x24, [sp, #0x20]
145 ldp x25, x26, [sp, #0x30]
146 ldp x27, x28, [sp, #0x40]
147 ldp x29, x30, [sp, #0x50] /* the pFrame address points to this entry */
148 add sp, sp, #0x60
149 mov w0, w1 /* The return value */
150#ifdef RT_OS_DARWIN
151 retab
152#else
153 ret
154#endif
155 brk #1
156
157
158
159#define IEMNATIVE_HLP_FRAME_SIZE (11 * 16)
160
161/**
162 * This is wrapper function that saves and restores all volatile registers
163 * so the impact of inserting LogCpuState is minimal to the other TB code.
164 */
165ALIGNCODE(IEM_HLP_FUNCTION_ALIGNMENT)
166BEGINPROC_HIDDEN iemNativeHlpAsmSafeWrapLogCpuState
167#ifdef RT_OS_DARWIN
168 pacibsp
169#endif
170
171 /*
172 * Save all volatile registers.
173 */
174 stp x29, x30, [sp, #-IEMNATIVE_HLP_FRAME_SIZE]!
175 stp x0, x1, [sp, #( 1 * 16)]
176 stp x2, x3, [sp, #( 2 * 16)]
177 stp x4, x5, [sp, #( 3 * 16)]
178 stp x5, x6, [sp, #( 4 * 16)]
179 stp x7, x8, [sp, #( 5 * 16)]
180 stp x9, x10, [sp, #( 6 * 16)]
181 stp x11, x12, [sp, #( 7 * 16)]
182 stp x13, x14, [sp, #( 8 * 16)]
183 stp x15, x16, [sp, #( 9 * 16)]
184 stp x17, x18, [sp, #(10 * 16)]
185
186 /*
187 * Move the pVCpu pointer from the fixed register to the first argument.
188 * @todo This needs syncing with what we use in IEMN8veRecompiler.h
189 * but we can't include that header right now, would need some #ifndef IN_ASM_CODE...
190 * in the header or splitting up the header into a asm safe one and a one included from C/C++.
191 */
192 mov x0, x28
193
194 /*
195 * Call C function to do the actual work.
196 */
197 bl NAME(iemThreadedFunc_BltIn_LogCpuStateWorker)
198
199 /*
200 * Restore volatile registers and return to the TB code.
201 */
202 ldp x29, x30, [sp, #( 0 * 16)]
203 ldp x0, x1, [sp, #( 1 * 16)]
204 ldp x2, x3, [sp, #( 2 * 16)]
205 ldp x4, x5, [sp, #( 3 * 16)]
206 ldp x5, x6, [sp, #( 4 * 16)]
207 ldp x7, x8, [sp, #( 5 * 16)]
208 ldp x9, x10, [sp, #( 6 * 16)]
209 ldp x11, x12, [sp, #( 7 * 16)]
210 ldp x13, x14, [sp, #( 8 * 16)]
211 ldp x15, x16, [sp, #( 9 * 16)]
212 ldp x17, x18, [sp, #(10 * 16)]
213 add sp, sp, #IEMNATIVE_HLP_FRAME_SIZE
214
215#ifdef RT_OS_DARWIN
216 retab
217#else
218 ret
219#endif
220 brk #1
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette