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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h@ 98122

Last change on this file since 98122 was 98103, checked in by vboxsync, 22 months ago

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1/* $Id: IEMAllInstructionsVexMap1.cpp.h 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 1
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128
39 * - vpxxx ymm0, ymm1, ymm2/mem256
40 *
41 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
42 */
43FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, PCIEMOPMEDIAF3, pImpl)
44{
45 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
46 if (IEM_IS_MODRM_REG_MODE(bRm))
47 {
48 /*
49 * Register, register.
50 */
51 if (pVCpu->iem.s.uVexLength)
52 {
53 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
54 IEM_MC_BEGIN(4, 3);
55 IEM_MC_LOCAL(RTUINT256U, uDst);
56 IEM_MC_LOCAL(RTUINT256U, uSrc1);
57 IEM_MC_LOCAL(RTUINT256U, uSrc2);
58 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
59 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 1);
60 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 2);
61 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 3);
62 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
63 IEM_MC_PREPARE_AVX_USAGE();
64 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
65 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
66 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
67 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
68 IEM_MC_ADVANCE_RIP_AND_FINISH();
69 IEM_MC_END();
70 }
71 else
72 {
73 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
74 IEM_MC_BEGIN(4, 0);
75 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
76 IEM_MC_ARG(PRTUINT128U, puDst, 1);
77 IEM_MC_ARG(PCRTUINT128U, puSrc1, 2);
78 IEM_MC_ARG(PCRTUINT128U, puSrc2, 3);
79 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
80 IEM_MC_PREPARE_AVX_USAGE();
81 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
82 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
83 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
84 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
85 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
86 IEM_MC_ADVANCE_RIP_AND_FINISH();
87 IEM_MC_END();
88 }
89 }
90 else
91 {
92 /*
93 * Register, memory.
94 */
95 if (pVCpu->iem.s.uVexLength)
96 {
97 IEM_MC_BEGIN(4, 4);
98 IEM_MC_LOCAL(RTUINT256U, uDst);
99 IEM_MC_LOCAL(RTUINT256U, uSrc1);
100 IEM_MC_LOCAL(RTUINT256U, uSrc2);
101 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
102 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
103 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 1);
104 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 2);
105 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 3);
106
107 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
108 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
109 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
110 IEM_MC_PREPARE_AVX_USAGE();
111
112 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
113 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
114 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
115 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
116
117 IEM_MC_ADVANCE_RIP_AND_FINISH();
118 IEM_MC_END();
119 }
120 else
121 {
122 IEM_MC_BEGIN(4, 2);
123 IEM_MC_LOCAL(RTUINT128U, uSrc2);
124 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
126 IEM_MC_ARG(PRTUINT128U, puDst, 1);
127 IEM_MC_ARG(PCRTUINT128U, puSrc1, 2);
128 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 3);
129
130 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
131 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
132 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
133 IEM_MC_PREPARE_AVX_USAGE();
134
135 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
136 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
137 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
138 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
139 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
140
141 IEM_MC_ADVANCE_RIP_AND_FINISH();
142 IEM_MC_END();
143 }
144 }
145}
146
147
148/**
149 * Common worker for AVX2 instructions on the forms:
150 * - vpxxx xmm0, xmm1, xmm2/mem128
151 * - vpxxx ymm0, ymm1, ymm2/mem256
152 *
153 * Takes function table for function w/o implicit state parameter.
154 *
155 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
156 */
157FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, PCIEMOPMEDIAOPTF3, pImpl)
158{
159 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
160 if (IEM_IS_MODRM_REG_MODE(bRm))
161 {
162 /*
163 * Register, register.
164 */
165 if (pVCpu->iem.s.uVexLength)
166 {
167 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
168 IEM_MC_BEGIN(3, 3);
169 IEM_MC_LOCAL(RTUINT256U, uDst);
170 IEM_MC_LOCAL(RTUINT256U, uSrc1);
171 IEM_MC_LOCAL(RTUINT256U, uSrc2);
172 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
173 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
174 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
175 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
176 IEM_MC_PREPARE_AVX_USAGE();
177 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
178 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
179 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
180 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
181 IEM_MC_ADVANCE_RIP_AND_FINISH();
182 IEM_MC_END();
183 }
184 else
185 {
186 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
187 IEM_MC_BEGIN(3, 0);
188 IEM_MC_ARG(PRTUINT128U, puDst, 0);
189 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
190 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
191 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
192 IEM_MC_PREPARE_AVX_USAGE();
193 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
194 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
195 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
196 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
197 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
198 IEM_MC_ADVANCE_RIP_AND_FINISH();
199 IEM_MC_END();
200 }
201 }
202 else
203 {
204 /*
205 * Register, memory.
206 */
207 if (pVCpu->iem.s.uVexLength)
208 {
209 IEM_MC_BEGIN(3, 4);
210 IEM_MC_LOCAL(RTUINT256U, uDst);
211 IEM_MC_LOCAL(RTUINT256U, uSrc1);
212 IEM_MC_LOCAL(RTUINT256U, uSrc2);
213 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
214 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
215 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
216 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
217
218 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
219 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
220 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
221 IEM_MC_PREPARE_AVX_USAGE();
222
223 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
224 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
225 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
226 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
227
228 IEM_MC_ADVANCE_RIP_AND_FINISH();
229 IEM_MC_END();
230 }
231 else
232 {
233 IEM_MC_BEGIN(3, 2);
234 IEM_MC_LOCAL(RTUINT128U, uSrc2);
235 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
236 IEM_MC_ARG(PRTUINT128U, puDst, 0);
237 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
238 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
239
240 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
241 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
242 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
243 IEM_MC_PREPARE_AVX_USAGE();
244
245 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
246 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
247 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
248 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
249 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
250
251 IEM_MC_ADVANCE_RIP_AND_FINISH();
252 IEM_MC_END();
253 }
254 }
255}
256
257
258/**
259 * Common worker for AVX2 instructions on the forms:
260 * - vpunpckhxx xmm0, xmm1, xmm2/mem128
261 * - vpunpckhxx ymm0, ymm1, ymm2/mem256
262 *
263 * The 128-bit memory version of this instruction may elect to skip fetching the
264 * lower 64 bits of the operand. We, however, do not.
265 *
266 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
267 */
268FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, PCIEMOPMEDIAOPTF3, pImpl)
269{
270 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
271}
272
273
274/**
275 * Common worker for AVX2 instructions on the forms:
276 * - vpunpcklxx xmm0, xmm1, xmm2/mem128
277 * - vpunpcklxx ymm0, ymm1, ymm2/mem256
278 *
279 * The 128-bit memory version of this instruction may elect to skip fetching the
280 * higher 64 bits of the operand. We, however, do not.
281 *
282 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
283 */
284FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, PCIEMOPMEDIAOPTF3, pImpl)
285{
286 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
287}
288
289
290/**
291 * Common worker for AVX2 instructions on the forms:
292 * - vpxxx xmm0, xmm1/mem128
293 * - vpxxx ymm0, ymm1/mem256
294 *
295 * Takes function table for function w/o implicit state parameter.
296 *
297 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
298 */
299FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, PCIEMOPMEDIAOPTF2, pImpl)
300{
301 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
302 if (IEM_IS_MODRM_REG_MODE(bRm))
303 {
304 /*
305 * Register, register.
306 */
307 if (pVCpu->iem.s.uVexLength)
308 {
309 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
310 IEM_MC_BEGIN(2, 2);
311 IEM_MC_LOCAL(RTUINT256U, uDst);
312 IEM_MC_LOCAL(RTUINT256U, uSrc);
313 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
314 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
315 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
316 IEM_MC_PREPARE_AVX_USAGE();
317 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
318 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
319 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
320 IEM_MC_ADVANCE_RIP_AND_FINISH();
321 IEM_MC_END();
322 }
323 else
324 {
325 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
326 IEM_MC_BEGIN(2, 0);
327 IEM_MC_ARG(PRTUINT128U, puDst, 0);
328 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
329 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
330 IEM_MC_PREPARE_AVX_USAGE();
331 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
332 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
333 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
334 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
335 IEM_MC_ADVANCE_RIP_AND_FINISH();
336 IEM_MC_END();
337 }
338 }
339 else
340 {
341 /*
342 * Register, memory.
343 */
344 if (pVCpu->iem.s.uVexLength)
345 {
346 IEM_MC_BEGIN(2, 3);
347 IEM_MC_LOCAL(RTUINT256U, uDst);
348 IEM_MC_LOCAL(RTUINT256U, uSrc);
349 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
350 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
351 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
352
353 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
354 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
355 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
356 IEM_MC_PREPARE_AVX_USAGE();
357
358 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
359 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
360 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
361
362 IEM_MC_ADVANCE_RIP_AND_FINISH();
363 IEM_MC_END();
364 }
365 else
366 {
367 IEM_MC_BEGIN(2, 2);
368 IEM_MC_LOCAL(RTUINT128U, uSrc);
369 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
370 IEM_MC_ARG(PRTUINT128U, puDst, 0);
371 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
372
373 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
374 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
375 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
376 IEM_MC_PREPARE_AVX_USAGE();
377
378 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
379 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
380 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
381 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
382
383 IEM_MC_ADVANCE_RIP_AND_FINISH();
384 IEM_MC_END();
385 }
386 }
387}
388
389
390/* Opcode VEX.0F 0x00 - invalid */
391/* Opcode VEX.0F 0x01 - invalid */
392/* Opcode VEX.0F 0x02 - invalid */
393/* Opcode VEX.0F 0x03 - invalid */
394/* Opcode VEX.0F 0x04 - invalid */
395/* Opcode VEX.0F 0x05 - invalid */
396/* Opcode VEX.0F 0x06 - invalid */
397/* Opcode VEX.0F 0x07 - invalid */
398/* Opcode VEX.0F 0x08 - invalid */
399/* Opcode VEX.0F 0x09 - invalid */
400/* Opcode VEX.0F 0x0a - invalid */
401
402/** Opcode VEX.0F 0x0b. */
403FNIEMOP_DEF(iemOp_vud2)
404{
405 IEMOP_MNEMONIC(vud2, "vud2");
406 return IEMOP_RAISE_INVALID_OPCODE();
407}
408
409/* Opcode VEX.0F 0x0c - invalid */
410/* Opcode VEX.0F 0x0d - invalid */
411/* Opcode VEX.0F 0x0e - invalid */
412/* Opcode VEX.0F 0x0f - invalid */
413
414
415/**
416 * @opcode 0x10
417 * @oppfx none
418 * @opcpuid avx
419 * @opgroup og_avx_simdfp_datamove
420 * @opxcpttype 4UA
421 * @optest op1=1 op2=2 -> op1=2
422 * @optest op1=0 op2=-22 -> op1=-22
423 */
424FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
425{
426 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
427 Assert(pVCpu->iem.s.uVexLength <= 1);
428 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
429 if (IEM_IS_MODRM_REG_MODE(bRm))
430 {
431 /*
432 * Register, register.
433 */
434 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
435 IEM_MC_BEGIN(0, 0);
436 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
437 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
438 if (pVCpu->iem.s.uVexLength == 0)
439 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
440 IEM_GET_MODRM_RM(pVCpu, bRm));
441 else
442 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
443 IEM_GET_MODRM_RM(pVCpu, bRm));
444 IEM_MC_ADVANCE_RIP_AND_FINISH();
445 IEM_MC_END();
446 }
447 else if (pVCpu->iem.s.uVexLength == 0)
448 {
449 /*
450 * 128-bit: Register, Memory
451 */
452 IEM_MC_BEGIN(0, 2);
453 IEM_MC_LOCAL(RTUINT128U, uSrc);
454 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
455
456 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
457 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
458 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
459 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
460
461 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
462 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
463
464 IEM_MC_ADVANCE_RIP_AND_FINISH();
465 IEM_MC_END();
466 }
467 else
468 {
469 /*
470 * 256-bit: Register, Memory
471 */
472 IEM_MC_BEGIN(0, 2);
473 IEM_MC_LOCAL(RTUINT256U, uSrc);
474 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
475
476 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
477 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
478 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
479 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
480
481 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
482 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
483
484 IEM_MC_ADVANCE_RIP_AND_FINISH();
485 IEM_MC_END();
486 }
487}
488
489
490/**
491 * @opcode 0x10
492 * @oppfx 0x66
493 * @opcpuid avx
494 * @opgroup og_avx_simdfp_datamove
495 * @opxcpttype 4UA
496 * @optest op1=1 op2=2 -> op1=2
497 * @optest op1=0 op2=-22 -> op1=-22
498 */
499FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
500{
501 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
502 Assert(pVCpu->iem.s.uVexLength <= 1);
503 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
504 if (IEM_IS_MODRM_REG_MODE(bRm))
505 {
506 /*
507 * Register, register.
508 */
509 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
510 IEM_MC_BEGIN(0, 0);
511 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
512 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
513 if (pVCpu->iem.s.uVexLength == 0)
514 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
515 IEM_GET_MODRM_RM(pVCpu, bRm));
516 else
517 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
518 IEM_GET_MODRM_RM(pVCpu, bRm));
519 IEM_MC_ADVANCE_RIP_AND_FINISH();
520 IEM_MC_END();
521 }
522 else if (pVCpu->iem.s.uVexLength == 0)
523 {
524 /*
525 * 128-bit: Memory, register.
526 */
527 IEM_MC_BEGIN(0, 2);
528 IEM_MC_LOCAL(RTUINT128U, uSrc);
529 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
530
531 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
532 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
533 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
534 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
535
536 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
537 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
538
539 IEM_MC_ADVANCE_RIP_AND_FINISH();
540 IEM_MC_END();
541 }
542 else
543 {
544 /*
545 * 256-bit: Memory, register.
546 */
547 IEM_MC_BEGIN(0, 2);
548 IEM_MC_LOCAL(RTUINT256U, uSrc);
549 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
550
551 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
552 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
553 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
554 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
555
556 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
557 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
558
559 IEM_MC_ADVANCE_RIP_AND_FINISH();
560 IEM_MC_END();
561 }
562}
563
564
565FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
566{
567 Assert(pVCpu->iem.s.uVexLength <= 1);
568 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
569 if (IEM_IS_MODRM_REG_MODE(bRm))
570 {
571 /**
572 * @opcode 0x10
573 * @oppfx 0xf3
574 * @opcodesub 11 mr/reg
575 * @opcpuid avx
576 * @opgroup og_avx_simdfp_datamerge
577 * @opxcpttype 5
578 * @optest op1=1 op2=0 op3=2 -> op1=2
579 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
580 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
581 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
582 * @note HssHi refers to bits 127:32.
583 */
584 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
585 IEMOP_HLP_DONE_VEX_DECODING();
586 IEM_MC_BEGIN(0, 0);
587
588 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
589 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
590 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
591 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
592 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
593 IEM_MC_ADVANCE_RIP_AND_FINISH();
594 IEM_MC_END();
595 }
596 else
597 {
598 /**
599 * @opdone
600 * @opcode 0x10
601 * @oppfx 0xf3
602 * @opcodesub !11 mr/reg
603 * @opcpuid avx
604 * @opgroup og_avx_simdfp_datamove
605 * @opxcpttype 5
606 * @opfunction iemOp_vmovss_Vss_Hss_Wss
607 * @optest op1=1 op2=2 -> op1=2
608 * @optest op1=0 op2=-22 -> op1=-22
609 */
610 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
611 IEM_MC_BEGIN(0, 2);
612 IEM_MC_LOCAL(uint32_t, uSrc);
613 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
614
615 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
616 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
617 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
618 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
619
620 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
621 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
622
623 IEM_MC_ADVANCE_RIP_AND_FINISH();
624 IEM_MC_END();
625 }
626}
627
628
629FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
630{
631 Assert(pVCpu->iem.s.uVexLength <= 1);
632 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
633 if (IEM_IS_MODRM_REG_MODE(bRm))
634 {
635 /**
636 * @opcode 0x10
637 * @oppfx 0xf2
638 * @opcodesub 11 mr/reg
639 * @opcpuid avx
640 * @opgroup og_avx_simdfp_datamerge
641 * @opxcpttype 5
642 * @optest op1=1 op2=0 op3=2 -> op1=2
643 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
644 * @optest op1=3 op2=-1 op3=0x77 ->
645 * op1=0xffffffffffffffff0000000000000077
646 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
647 */
648 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
649 IEMOP_HLP_DONE_VEX_DECODING();
650 IEM_MC_BEGIN(0, 0);
651
652 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
653 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
654 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
655 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
656 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
657 IEM_MC_ADVANCE_RIP_AND_FINISH();
658 IEM_MC_END();
659 }
660 else
661 {
662 /**
663 * @opdone
664 * @opcode 0x10
665 * @oppfx 0xf2
666 * @opcodesub !11 mr/reg
667 * @opcpuid avx
668 * @opgroup og_avx_simdfp_datamove
669 * @opxcpttype 5
670 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
671 * @optest op1=1 op2=2 -> op1=2
672 * @optest op1=0 op2=-22 -> op1=-22
673 */
674 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
675 IEM_MC_BEGIN(0, 2);
676 IEM_MC_LOCAL(uint64_t, uSrc);
677 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
678
679 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
680 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
681 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
682 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
683
684 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
685 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
686
687 IEM_MC_ADVANCE_RIP_AND_FINISH();
688 IEM_MC_END();
689 }
690}
691
692
693/**
694 * @opcode 0x11
695 * @oppfx none
696 * @opcpuid avx
697 * @opgroup og_avx_simdfp_datamove
698 * @opxcpttype 4UA
699 * @optest op1=1 op2=2 -> op1=2
700 * @optest op1=0 op2=-22 -> op1=-22
701 */
702FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
703{
704 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
705 Assert(pVCpu->iem.s.uVexLength <= 1);
706 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
707 if (IEM_IS_MODRM_REG_MODE(bRm))
708 {
709 /*
710 * Register, register.
711 */
712 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
713 IEM_MC_BEGIN(0, 0);
714 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
715 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
716 if (pVCpu->iem.s.uVexLength == 0)
717 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
718 IEM_GET_MODRM_REG(pVCpu, bRm));
719 else
720 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
721 IEM_GET_MODRM_REG(pVCpu, bRm));
722 IEM_MC_ADVANCE_RIP_AND_FINISH();
723 IEM_MC_END();
724 }
725 else if (pVCpu->iem.s.uVexLength == 0)
726 {
727 /*
728 * 128-bit: Memory, register.
729 */
730 IEM_MC_BEGIN(0, 2);
731 IEM_MC_LOCAL(RTUINT128U, uSrc);
732 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
733
734 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
735 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
736 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
737 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
738
739 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
740 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
741
742 IEM_MC_ADVANCE_RIP_AND_FINISH();
743 IEM_MC_END();
744 }
745 else
746 {
747 /*
748 * 256-bit: Memory, register.
749 */
750 IEM_MC_BEGIN(0, 2);
751 IEM_MC_LOCAL(RTUINT256U, uSrc);
752 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
753
754 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
755 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
756 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
757 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
758
759 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
760 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
761
762 IEM_MC_ADVANCE_RIP_AND_FINISH();
763 IEM_MC_END();
764 }
765}
766
767
768/**
769 * @opcode 0x11
770 * @oppfx 0x66
771 * @opcpuid avx
772 * @opgroup og_avx_simdfp_datamove
773 * @opxcpttype 4UA
774 * @optest op1=1 op2=2 -> op1=2
775 * @optest op1=0 op2=-22 -> op1=-22
776 */
777FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
778{
779 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
780 Assert(pVCpu->iem.s.uVexLength <= 1);
781 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
782 if (IEM_IS_MODRM_REG_MODE(bRm))
783 {
784 /*
785 * Register, register.
786 */
787 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
788 IEM_MC_BEGIN(0, 0);
789 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
790 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
791 if (pVCpu->iem.s.uVexLength == 0)
792 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
793 IEM_GET_MODRM_REG(pVCpu, bRm));
794 else
795 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
796 IEM_GET_MODRM_REG(pVCpu, bRm));
797 IEM_MC_ADVANCE_RIP_AND_FINISH();
798 IEM_MC_END();
799 }
800 else if (pVCpu->iem.s.uVexLength == 0)
801 {
802 /*
803 * 128-bit: Memory, register.
804 */
805 IEM_MC_BEGIN(0, 2);
806 IEM_MC_LOCAL(RTUINT128U, uSrc);
807 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
808
809 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
810 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
811 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
812 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
813
814 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
815 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
816
817 IEM_MC_ADVANCE_RIP_AND_FINISH();
818 IEM_MC_END();
819 }
820 else
821 {
822 /*
823 * 256-bit: Memory, register.
824 */
825 IEM_MC_BEGIN(0, 2);
826 IEM_MC_LOCAL(RTUINT256U, uSrc);
827 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
828
829 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
830 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
831 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
832 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
833
834 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
835 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
836
837 IEM_MC_ADVANCE_RIP_AND_FINISH();
838 IEM_MC_END();
839 }
840}
841
842
843FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
844{
845 Assert(pVCpu->iem.s.uVexLength <= 1);
846 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
847 if (IEM_IS_MODRM_REG_MODE(bRm))
848 {
849 /**
850 * @opcode 0x11
851 * @oppfx 0xf3
852 * @opcodesub 11 mr/reg
853 * @opcpuid avx
854 * @opgroup og_avx_simdfp_datamerge
855 * @opxcpttype 5
856 * @optest op1=1 op2=0 op3=2 -> op1=2
857 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
858 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
859 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
860 */
861 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
862 IEMOP_HLP_DONE_VEX_DECODING();
863 IEM_MC_BEGIN(0, 0);
864
865 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
866 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
867 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
868 IEM_GET_MODRM_REG(pVCpu, bRm),
869 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
870 IEM_MC_ADVANCE_RIP_AND_FINISH();
871 IEM_MC_END();
872 }
873 else
874 {
875 /**
876 * @opdone
877 * @opcode 0x11
878 * @oppfx 0xf3
879 * @opcodesub !11 mr/reg
880 * @opcpuid avx
881 * @opgroup og_avx_simdfp_datamove
882 * @opxcpttype 5
883 * @opfunction iemOp_vmovss_Vss_Hss_Wss
884 * @optest op1=1 op2=2 -> op1=2
885 * @optest op1=0 op2=-22 -> op1=-22
886 */
887 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
888 IEM_MC_BEGIN(0, 2);
889 IEM_MC_LOCAL(uint32_t, uSrc);
890 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
891
892 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
893 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
894 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
895 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
896
897 IEM_MC_FETCH_YREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
898 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
899
900 IEM_MC_ADVANCE_RIP_AND_FINISH();
901 IEM_MC_END();
902 }
903}
904
905
906FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
907{
908 Assert(pVCpu->iem.s.uVexLength <= 1);
909 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
910 if (IEM_IS_MODRM_REG_MODE(bRm))
911 {
912 /**
913 * @opcode 0x11
914 * @oppfx 0xf2
915 * @opcodesub 11 mr/reg
916 * @opcpuid avx
917 * @opgroup og_avx_simdfp_datamerge
918 * @opxcpttype 5
919 * @optest op1=1 op2=0 op3=2 -> op1=2
920 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
921 * @optest op1=3 op2=-1 op3=0x77 ->
922 * op1=0xffffffffffffffff0000000000000077
923 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
924 */
925 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
926 IEMOP_HLP_DONE_VEX_DECODING();
927 IEM_MC_BEGIN(0, 0);
928
929 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
930 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
931 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
932 IEM_GET_MODRM_REG(pVCpu, bRm),
933 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
934 IEM_MC_ADVANCE_RIP_AND_FINISH();
935 IEM_MC_END();
936 }
937 else
938 {
939 /**
940 * @opdone
941 * @opcode 0x11
942 * @oppfx 0xf2
943 * @opcodesub !11 mr/reg
944 * @opcpuid avx
945 * @opgroup og_avx_simdfp_datamove
946 * @opxcpttype 5
947 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
948 * @optest op1=1 op2=2 -> op1=2
949 * @optest op1=0 op2=-22 -> op1=-22
950 */
951 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
952 IEM_MC_BEGIN(0, 2);
953 IEM_MC_LOCAL(uint64_t, uSrc);
954 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
955
956 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
957 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
958 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
959 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
960
961 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
962 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
963
964 IEM_MC_ADVANCE_RIP_AND_FINISH();
965 IEM_MC_END();
966 }
967}
968
969
970FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
971{
972 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
973 if (IEM_IS_MODRM_REG_MODE(bRm))
974 {
975 /**
976 * @opcode 0x12
977 * @opcodesub 11 mr/reg
978 * @oppfx none
979 * @opcpuid avx
980 * @opgroup og_avx_simdfp_datamerge
981 * @opxcpttype 7LZ
982 * @optest op2=0x2200220122022203
983 * op3=0x3304330533063307
984 * -> op1=0x22002201220222033304330533063307
985 * @optest op2=-1 op3=-42 -> op1=-42
986 * @note op3 and op2 are only the 8-byte high XMM register halfs.
987 */
988 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
989
990 IEMOP_HLP_DONE_VEX_DECODING_L0();
991 IEM_MC_BEGIN(0, 0);
992
993 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
994 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
995 IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
996 IEM_GET_MODRM_RM(pVCpu, bRm),
997 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
998
999 IEM_MC_ADVANCE_RIP_AND_FINISH();
1000 IEM_MC_END();
1001 }
1002 else
1003 {
1004 /**
1005 * @opdone
1006 * @opcode 0x12
1007 * @opcodesub !11 mr/reg
1008 * @oppfx none
1009 * @opcpuid avx
1010 * @opgroup og_avx_simdfp_datamove
1011 * @opxcpttype 5LZ
1012 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
1013 * @optest op1=1 op2=0 op3=0 -> op1=0
1014 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
1015 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
1016 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
1017 */
1018 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1019
1020 IEM_MC_BEGIN(0, 2);
1021 IEM_MC_LOCAL(uint64_t, uSrc);
1022 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1023
1024 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1025 IEMOP_HLP_DONE_VEX_DECODING_L0();
1026 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1027 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1028
1029 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1030 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1031 uSrc,
1032 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1033
1034 IEM_MC_ADVANCE_RIP_AND_FINISH();
1035 IEM_MC_END();
1036 }
1037}
1038
1039
1040/**
1041 * @opcode 0x12
1042 * @opcodesub !11 mr/reg
1043 * @oppfx 0x66
1044 * @opcpuid avx
1045 * @opgroup og_avx_pcksclr_datamerge
1046 * @opxcpttype 5LZ
1047 * @optest op2=0 op3=2 -> op1=2
1048 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
1049 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
1050 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
1051 */
1052FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
1053{
1054 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1055 if (IEM_IS_MODRM_MEM_MODE(bRm))
1056 {
1057 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1058
1059 IEM_MC_BEGIN(0, 2);
1060 IEM_MC_LOCAL(uint64_t, uSrc);
1061 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1062
1063 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1064 IEMOP_HLP_DONE_VEX_DECODING_L0();
1065 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1066 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1067
1068 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1069 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1070 uSrc,
1071 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1072
1073 IEM_MC_ADVANCE_RIP_AND_FINISH();
1074 IEM_MC_END();
1075 }
1076
1077 /**
1078 * @opdone
1079 * @opmnemonic udvex660f12m3
1080 * @opcode 0x12
1081 * @opcodesub 11 mr/reg
1082 * @oppfx 0x66
1083 * @opunused immediate
1084 * @opcpuid avx
1085 * @optest ->
1086 */
1087 else
1088 return IEMOP_RAISE_INVALID_OPCODE();
1089}
1090
1091
1092/**
1093 * @opcode 0x12
1094 * @oppfx 0xf3
1095 * @opcpuid avx
1096 * @opgroup og_avx_pcksclr_datamove
1097 * @opxcpttype 4
1098 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
1099 * -> op1=0x00000002000000020000000100000001
1100 * @optest vex.l==1 /
1101 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
1102 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
1103 */
1104FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
1105{
1106 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1107 Assert(pVCpu->iem.s.uVexLength <= 1);
1108 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1109 if (IEM_IS_MODRM_REG_MODE(bRm))
1110 {
1111 /*
1112 * Register, register.
1113 */
1114 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1115 if (pVCpu->iem.s.uVexLength == 0)
1116 {
1117 IEM_MC_BEGIN(0, 1);
1118 IEM_MC_LOCAL(RTUINT128U, uSrc);
1119
1120 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1121 IEM_MC_PREPARE_AVX_USAGE();
1122
1123 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1124 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1125 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1126 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1127 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1128 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1129
1130 IEM_MC_ADVANCE_RIP_AND_FINISH();
1131 IEM_MC_END();
1132 }
1133 else
1134 {
1135 IEM_MC_BEGIN(3, 0);
1136 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1137 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1138 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1139
1140 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1141 IEM_MC_PREPARE_AVX_USAGE();
1142 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rr, iYRegDst, iYRegSrc);
1143
1144 IEM_MC_ADVANCE_RIP_AND_FINISH();
1145 IEM_MC_END();
1146 }
1147 }
1148 else
1149 {
1150 /*
1151 * Register, memory.
1152 */
1153 if (pVCpu->iem.s.uVexLength == 0)
1154 {
1155 IEM_MC_BEGIN(0, 2);
1156 IEM_MC_LOCAL(RTUINT128U, uSrc);
1157 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1158
1159 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1160 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1161 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1162 IEM_MC_PREPARE_AVX_USAGE();
1163
1164 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1165 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1166 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1167 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1168 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1169 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1170
1171 IEM_MC_ADVANCE_RIP_AND_FINISH();
1172 IEM_MC_END();
1173 }
1174 else
1175 {
1176 IEM_MC_BEGIN(3, 2);
1177 IEM_MC_LOCAL(RTUINT256U, uSrc);
1178 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1179 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1180 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1181 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1182
1183 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1184 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1185 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1186 IEM_MC_PREPARE_AVX_USAGE();
1187
1188 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1189 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rm, iYRegDst, puSrc);
1190
1191 IEM_MC_ADVANCE_RIP_AND_FINISH();
1192 IEM_MC_END();
1193 }
1194 }
1195}
1196
1197
1198/**
1199 * @opcode 0x12
1200 * @oppfx 0xf2
1201 * @opcpuid avx
1202 * @opgroup og_avx_pcksclr_datamove
1203 * @opxcpttype 5
1204 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
1205 * -> op1=0x22222222111111112222222211111111
1206 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
1207 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
1208 */
1209FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
1210{
1211 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1212 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1213 if (IEM_IS_MODRM_REG_MODE(bRm))
1214 {
1215 /*
1216 * Register, register.
1217 */
1218 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1219 if (pVCpu->iem.s.uVexLength == 0)
1220 {
1221 IEM_MC_BEGIN(1, 0);
1222 IEM_MC_ARG(uint64_t, uSrc, 0);
1223
1224 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1225 IEM_MC_PREPARE_AVX_USAGE();
1226
1227 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/);
1228 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1229 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1230 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1231
1232 IEM_MC_ADVANCE_RIP_AND_FINISH();
1233 IEM_MC_END();
1234 }
1235 else
1236 {
1237 IEM_MC_BEGIN(3, 0);
1238 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1239 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1240 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1241
1242 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1243 IEM_MC_PREPARE_AVX_USAGE();
1244 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rr, iYRegDst, iYRegSrc);
1245
1246 IEM_MC_ADVANCE_RIP_AND_FINISH();
1247 IEM_MC_END();
1248 }
1249 }
1250 else
1251 {
1252 /*
1253 * Register, memory.
1254 */
1255 if (pVCpu->iem.s.uVexLength == 0)
1256 {
1257 IEM_MC_BEGIN(1, 1);
1258 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1259 IEM_MC_ARG(uint64_t, uSrc, 0);
1260
1261 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1262 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1263 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1264 IEM_MC_PREPARE_AVX_USAGE();
1265
1266 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1267 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1268 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1269 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1270
1271 IEM_MC_ADVANCE_RIP_AND_FINISH();
1272 IEM_MC_END();
1273 }
1274 else
1275 {
1276 IEM_MC_BEGIN(3, 2);
1277 IEM_MC_LOCAL(RTUINT256U, uSrc);
1278 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1279 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1280 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1281 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1282
1283 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1284 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1285 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1286 IEM_MC_PREPARE_AVX_USAGE();
1287
1288 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1289 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rm, iYRegDst, puSrc);
1290
1291 IEM_MC_ADVANCE_RIP_AND_FINISH();
1292 IEM_MC_END();
1293 }
1294 }
1295}
1296
1297
1298/**
1299 * @opcode 0x13
1300 * @opcodesub !11 mr/reg
1301 * @oppfx none
1302 * @opcpuid avx
1303 * @opgroup og_avx_simdfp_datamove
1304 * @opxcpttype 5
1305 * @optest op1=1 op2=2 -> op1=2
1306 * @optest op1=0 op2=-42 -> op1=-42
1307 */
1308FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
1309{
1310 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1311 if (IEM_IS_MODRM_MEM_MODE(bRm))
1312 {
1313 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1314
1315 IEM_MC_BEGIN(0, 2);
1316 IEM_MC_LOCAL(uint64_t, uSrc);
1317 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1318
1319 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1320 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1321 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1322 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1323
1324 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1325 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1326
1327 IEM_MC_ADVANCE_RIP_AND_FINISH();
1328 IEM_MC_END();
1329 }
1330
1331 /**
1332 * @opdone
1333 * @opmnemonic udvex0f13m3
1334 * @opcode 0x13
1335 * @opcodesub 11 mr/reg
1336 * @oppfx none
1337 * @opunused immediate
1338 * @opcpuid avx
1339 * @optest ->
1340 */
1341 else
1342 return IEMOP_RAISE_INVALID_OPCODE();
1343}
1344
1345
1346/**
1347 * @opcode 0x13
1348 * @opcodesub !11 mr/reg
1349 * @oppfx 0x66
1350 * @opcpuid avx
1351 * @opgroup og_avx_pcksclr_datamove
1352 * @opxcpttype 5
1353 * @optest op1=1 op2=2 -> op1=2
1354 * @optest op1=0 op2=-42 -> op1=-42
1355 */
1356FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1357{
1358 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1359 if (IEM_IS_MODRM_MEM_MODE(bRm))
1360 {
1361 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1362 IEM_MC_BEGIN(0, 2);
1363 IEM_MC_LOCAL(uint64_t, uSrc);
1364 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1365
1366 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1367 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1368 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1369 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1370
1371 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1372 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1373
1374 IEM_MC_ADVANCE_RIP_AND_FINISH();
1375 IEM_MC_END();
1376 }
1377
1378 /**
1379 * @opdone
1380 * @opmnemonic udvex660f13m3
1381 * @opcode 0x13
1382 * @opcodesub 11 mr/reg
1383 * @oppfx 0x66
1384 * @opunused immediate
1385 * @opcpuid avx
1386 * @optest ->
1387 */
1388 else
1389 return IEMOP_RAISE_INVALID_OPCODE();
1390}
1391
1392/* Opcode VEX.F3.0F 0x13 - invalid */
1393/* Opcode VEX.F2.0F 0x13 - invalid */
1394
1395/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1396FNIEMOP_DEF(iemOp_vunpcklps_Vx_Hx_Wx)
1397{
1398 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPS, vunpcklps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1399 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklps);
1400 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1401}
1402
1403
1404/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1405FNIEMOP_DEF(iemOp_vunpcklpd_Vx_Hx_Wx)
1406{
1407 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPD, vunpcklpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1408 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklpd);
1409 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1410}
1411
1412
1413/* Opcode VEX.F3.0F 0x14 - invalid */
1414/* Opcode VEX.F2.0F 0x14 - invalid */
1415
1416
1417/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1418FNIEMOP_DEF(iemOp_vunpckhps_Vx_Hx_Wx)
1419{
1420 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPS, vunpckhps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1421 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhps);
1422 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1423}
1424
1425
1426/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1427FNIEMOP_DEF(iemOp_vunpckhpd_Vx_Hx_Wx)
1428{
1429 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPD, vunpckhpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1430 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhpd);
1431 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1432}
1433
1434
1435/* Opcode VEX.F3.0F 0x15 - invalid */
1436/* Opcode VEX.F2.0F 0x15 - invalid */
1437
1438
1439FNIEMOP_DEF(iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq)
1440{
1441 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1442 if (IEM_IS_MODRM_REG_MODE(bRm))
1443 {
1444 /**
1445 * @opcode 0x16
1446 * @opcodesub 11 mr/reg
1447 * @oppfx none
1448 * @opcpuid avx
1449 * @opgroup og_avx_simdfp_datamerge
1450 * @opxcpttype 7LZ
1451 */
1452 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1453
1454 IEMOP_HLP_DONE_VEX_DECODING_L0();
1455 IEM_MC_BEGIN(0, 0);
1456
1457 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1458 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1459 IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1460 IEM_GET_MODRM_RM(pVCpu, bRm),
1461 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1462
1463 IEM_MC_ADVANCE_RIP_AND_FINISH();
1464 IEM_MC_END();
1465 }
1466 else
1467 {
1468 /**
1469 * @opdone
1470 * @opcode 0x16
1471 * @opcodesub !11 mr/reg
1472 * @oppfx none
1473 * @opcpuid avx
1474 * @opgroup og_avx_simdfp_datamove
1475 * @opxcpttype 5LZ
1476 * @opfunction iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq
1477 */
1478 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPS, vmovhps, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1479
1480 IEM_MC_BEGIN(0, 2);
1481 IEM_MC_LOCAL(uint64_t, uSrc);
1482 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1483
1484 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1485 IEMOP_HLP_DONE_VEX_DECODING_L0();
1486 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1487 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1488
1489 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1490 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1491 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1492 uSrc);
1493
1494 IEM_MC_ADVANCE_RIP_AND_FINISH();
1495 IEM_MC_END();
1496 }
1497}
1498
1499
1500/**
1501 * @opcode 0x16
1502 * @opcodesub !11 mr/reg
1503 * @oppfx 0x66
1504 * @opcpuid avx
1505 * @opgroup og_avx_pcksclr_datamerge
1506 * @opxcpttype 5LZ
1507 */
1508FNIEMOP_DEF(iemOp_vmovhpd_Vdq_Hq_Mq)
1509{
1510 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1511 if (IEM_IS_MODRM_MEM_MODE(bRm))
1512 {
1513 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPD, vmovhpd, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1514
1515 IEM_MC_BEGIN(0, 2);
1516 IEM_MC_LOCAL(uint64_t, uSrc);
1517 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1518
1519 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1520 IEMOP_HLP_DONE_VEX_DECODING_L0();
1521 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1522 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1523
1524 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1525 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1526 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1527 uSrc);
1528
1529 IEM_MC_ADVANCE_RIP_AND_FINISH();
1530 IEM_MC_END();
1531 }
1532
1533 /**
1534 * @opdone
1535 * @opmnemonic udvex660f16m3
1536 * @opcode 0x12
1537 * @opcodesub 11 mr/reg
1538 * @oppfx 0x66
1539 * @opunused immediate
1540 * @opcpuid avx
1541 * @optest ->
1542 */
1543 else
1544 return IEMOP_RAISE_INVALID_OPCODE();
1545}
1546
1547
1548/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1549/**
1550 * @opcode 0x16
1551 * @oppfx 0xf3
1552 * @opcpuid avx
1553 * @opgroup og_avx_pcksclr_datamove
1554 * @opxcpttype 4
1555 */
1556FNIEMOP_DEF(iemOp_vmovshdup_Vx_Wx)
1557{
1558 IEMOP_MNEMONIC2(VEX_RM, VMOVSHDUP, vmovshdup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1559 Assert(pVCpu->iem.s.uVexLength <= 1);
1560 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1561 if (IEM_IS_MODRM_REG_MODE(bRm))
1562 {
1563 /*
1564 * Register, register.
1565 */
1566 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1567 if (pVCpu->iem.s.uVexLength == 0)
1568 {
1569 IEM_MC_BEGIN(0, 1);
1570 IEM_MC_LOCAL(RTUINT128U, uSrc);
1571
1572 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1573 IEM_MC_PREPARE_AVX_USAGE();
1574
1575 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1576 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1577 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1578 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1579 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1580 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1581
1582 IEM_MC_ADVANCE_RIP_AND_FINISH();
1583 IEM_MC_END();
1584 }
1585 else
1586 {
1587 IEM_MC_BEGIN(3, 0);
1588 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1589 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1590 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1591
1592 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1593 IEM_MC_PREPARE_AVX_USAGE();
1594 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rr, iYRegDst, iYRegSrc);
1595
1596 IEM_MC_ADVANCE_RIP_AND_FINISH();
1597 IEM_MC_END();
1598 }
1599 }
1600 else
1601 {
1602 /*
1603 * Register, memory.
1604 */
1605 if (pVCpu->iem.s.uVexLength == 0)
1606 {
1607 IEM_MC_BEGIN(0, 2);
1608 IEM_MC_LOCAL(RTUINT128U, uSrc);
1609 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1610
1611 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1612 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1613 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1614 IEM_MC_PREPARE_AVX_USAGE();
1615
1616 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1617 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1618 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1619 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1620 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1621 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1622
1623 IEM_MC_ADVANCE_RIP_AND_FINISH();
1624 IEM_MC_END();
1625 }
1626 else
1627 {
1628 IEM_MC_BEGIN(3, 2);
1629 IEM_MC_LOCAL(RTUINT256U, uSrc);
1630 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1631 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1632 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1633 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1634
1635 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1636 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1637 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1638 IEM_MC_PREPARE_AVX_USAGE();
1639
1640 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1641 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rm, iYRegDst, puSrc);
1642
1643 IEM_MC_ADVANCE_RIP_AND_FINISH();
1644 IEM_MC_END();
1645 }
1646 }
1647}
1648
1649
1650/* Opcode VEX.F2.0F 0x16 - invalid */
1651
1652
1653/**
1654 * @opcode 0x17
1655 * @opcodesub !11 mr/reg
1656 * @oppfx none
1657 * @opcpuid avx
1658 * @opgroup og_avx_simdfp_datamove
1659 * @opxcpttype 5
1660 */
1661FNIEMOP_DEF(iemOp_vmovhps_Mq_Vq)
1662{
1663 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1664 if (IEM_IS_MODRM_MEM_MODE(bRm))
1665 {
1666 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPS, vmovhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1667
1668 IEM_MC_BEGIN(0, 2);
1669 IEM_MC_LOCAL(uint64_t, uSrc);
1670 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1671
1672 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1673 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1674 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1675 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1676
1677 IEM_MC_FETCH_YREG_2ND_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1678 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1679
1680 IEM_MC_ADVANCE_RIP_AND_FINISH();
1681 IEM_MC_END();
1682 }
1683
1684 /**
1685 * @opdone
1686 * @opmnemonic udvex0f17m3
1687 * @opcode 0x17
1688 * @opcodesub 11 mr/reg
1689 * @oppfx none
1690 * @opunused immediate
1691 * @opcpuid avx
1692 * @optest ->
1693 */
1694 else
1695 return IEMOP_RAISE_INVALID_OPCODE();
1696}
1697
1698
1699/**
1700 * @opcode 0x17
1701 * @opcodesub !11 mr/reg
1702 * @oppfx 0x66
1703 * @opcpuid avx
1704 * @opgroup og_avx_pcksclr_datamove
1705 * @opxcpttype 5
1706 */
1707FNIEMOP_DEF(iemOp_vmovhpd_Mq_Vq)
1708{
1709 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1710 if (IEM_IS_MODRM_MEM_MODE(bRm))
1711 {
1712 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPD, vmovhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1713 IEM_MC_BEGIN(0, 2);
1714 IEM_MC_LOCAL(uint64_t, uSrc);
1715 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1716
1717 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1718 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1719 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1720 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1721
1722 IEM_MC_FETCH_YREG_2ND_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1723 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1724
1725 IEM_MC_ADVANCE_RIP_AND_FINISH();
1726 IEM_MC_END();
1727 }
1728
1729 /**
1730 * @opdone
1731 * @opmnemonic udvex660f17m3
1732 * @opcode 0x17
1733 * @opcodesub 11 mr/reg
1734 * @oppfx 0x66
1735 * @opunused immediate
1736 * @opcpuid avx
1737 * @optest ->
1738 */
1739 else
1740 return IEMOP_RAISE_INVALID_OPCODE();
1741}
1742
1743
1744/* Opcode VEX.F3.0F 0x17 - invalid */
1745/* Opcode VEX.F2.0F 0x17 - invalid */
1746
1747
1748/* Opcode VEX.0F 0x18 - invalid */
1749/* Opcode VEX.0F 0x19 - invalid */
1750/* Opcode VEX.0F 0x1a - invalid */
1751/* Opcode VEX.0F 0x1b - invalid */
1752/* Opcode VEX.0F 0x1c - invalid */
1753/* Opcode VEX.0F 0x1d - invalid */
1754/* Opcode VEX.0F 0x1e - invalid */
1755/* Opcode VEX.0F 0x1f - invalid */
1756
1757/* Opcode VEX.0F 0x20 - invalid */
1758/* Opcode VEX.0F 0x21 - invalid */
1759/* Opcode VEX.0F 0x22 - invalid */
1760/* Opcode VEX.0F 0x23 - invalid */
1761/* Opcode VEX.0F 0x24 - invalid */
1762/* Opcode VEX.0F 0x25 - invalid */
1763/* Opcode VEX.0F 0x26 - invalid */
1764/* Opcode VEX.0F 0x27 - invalid */
1765
1766/**
1767 * @opcode 0x28
1768 * @oppfx none
1769 * @opcpuid avx
1770 * @opgroup og_avx_pcksclr_datamove
1771 * @opxcpttype 1
1772 * @optest op1=1 op2=2 -> op1=2
1773 * @optest op1=0 op2=-42 -> op1=-42
1774 * @note Almost identical to vmovapd.
1775 */
1776FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1777{
1778 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1779 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1780 Assert(pVCpu->iem.s.uVexLength <= 1);
1781 if (IEM_IS_MODRM_REG_MODE(bRm))
1782 {
1783 /*
1784 * Register, register.
1785 */
1786 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1787 IEM_MC_BEGIN(1, 0);
1788
1789 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1790 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1791 if (pVCpu->iem.s.uVexLength == 0)
1792 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1793 IEM_GET_MODRM_RM(pVCpu, bRm));
1794 else
1795 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1796 IEM_GET_MODRM_RM(pVCpu, bRm));
1797 IEM_MC_ADVANCE_RIP_AND_FINISH();
1798 IEM_MC_END();
1799 }
1800 else
1801 {
1802 /*
1803 * Register, memory.
1804 */
1805 if (pVCpu->iem.s.uVexLength == 0)
1806 {
1807 IEM_MC_BEGIN(0, 2);
1808 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1809 IEM_MC_LOCAL(RTUINT128U, uSrc);
1810
1811 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1812 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1813 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1814 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1815
1816 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1817 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1818
1819 IEM_MC_ADVANCE_RIP_AND_FINISH();
1820 IEM_MC_END();
1821 }
1822 else
1823 {
1824 IEM_MC_BEGIN(0, 2);
1825 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1826 IEM_MC_LOCAL(RTUINT256U, uSrc);
1827
1828 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1829 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1830 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1831 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1832
1833 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1834 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1835
1836 IEM_MC_ADVANCE_RIP_AND_FINISH();
1837 IEM_MC_END();
1838 }
1839 }
1840}
1841
1842
1843/**
1844 * @opcode 0x28
1845 * @oppfx 66
1846 * @opcpuid avx
1847 * @opgroup og_avx_pcksclr_datamove
1848 * @opxcpttype 1
1849 * @optest op1=1 op2=2 -> op1=2
1850 * @optest op1=0 op2=-42 -> op1=-42
1851 * @note Almost identical to vmovaps
1852 */
1853FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
1854{
1855 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1856 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1857 Assert(pVCpu->iem.s.uVexLength <= 1);
1858 if (IEM_IS_MODRM_REG_MODE(bRm))
1859 {
1860 /*
1861 * Register, register.
1862 */
1863 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1864 IEM_MC_BEGIN(1, 0);
1865
1866 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1867 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1868 if (pVCpu->iem.s.uVexLength == 0)
1869 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1870 IEM_GET_MODRM_RM(pVCpu, bRm));
1871 else
1872 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1873 IEM_GET_MODRM_RM(pVCpu, bRm));
1874 IEM_MC_ADVANCE_RIP_AND_FINISH();
1875 IEM_MC_END();
1876 }
1877 else
1878 {
1879 /*
1880 * Register, memory.
1881 */
1882 if (pVCpu->iem.s.uVexLength == 0)
1883 {
1884 IEM_MC_BEGIN(0, 2);
1885 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1886 IEM_MC_LOCAL(RTUINT128U, uSrc);
1887
1888 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1889 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1890 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1891 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1892
1893 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1894 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1895
1896 IEM_MC_ADVANCE_RIP_AND_FINISH();
1897 IEM_MC_END();
1898 }
1899 else
1900 {
1901 IEM_MC_BEGIN(0, 2);
1902 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1903 IEM_MC_LOCAL(RTUINT256U, uSrc);
1904
1905 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1906 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1907 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1908 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1909
1910 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1911 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1912
1913 IEM_MC_ADVANCE_RIP_AND_FINISH();
1914 IEM_MC_END();
1915 }
1916 }
1917}
1918
1919/**
1920 * @opmnemonic udvexf30f28
1921 * @opcode 0x28
1922 * @oppfx 0xf3
1923 * @opunused vex.modrm
1924 * @opcpuid avx
1925 * @optest ->
1926 * @opdone
1927 */
1928
1929/**
1930 * @opmnemonic udvexf20f28
1931 * @opcode 0x28
1932 * @oppfx 0xf2
1933 * @opunused vex.modrm
1934 * @opcpuid avx
1935 * @optest ->
1936 * @opdone
1937 */
1938
1939/**
1940 * @opcode 0x29
1941 * @oppfx none
1942 * @opcpuid avx
1943 * @opgroup og_avx_pcksclr_datamove
1944 * @opxcpttype 1
1945 * @optest op1=1 op2=2 -> op1=2
1946 * @optest op1=0 op2=-42 -> op1=-42
1947 * @note Almost identical to vmovapd.
1948 */
1949FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
1950{
1951 IEMOP_MNEMONIC2(VEX_MR, VMOVAPS, vmovaps, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1952 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1953 Assert(pVCpu->iem.s.uVexLength <= 1);
1954 if (IEM_IS_MODRM_REG_MODE(bRm))
1955 {
1956 /*
1957 * Register, register.
1958 */
1959 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1960 IEM_MC_BEGIN(1, 0);
1961
1962 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1963 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1964 if (pVCpu->iem.s.uVexLength == 0)
1965 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1966 IEM_GET_MODRM_REG(pVCpu, bRm));
1967 else
1968 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1969 IEM_GET_MODRM_REG(pVCpu, bRm));
1970 IEM_MC_ADVANCE_RIP_AND_FINISH();
1971 IEM_MC_END();
1972 }
1973 else
1974 {
1975 /*
1976 * Register, memory.
1977 */
1978 if (pVCpu->iem.s.uVexLength == 0)
1979 {
1980 IEM_MC_BEGIN(0, 2);
1981 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1982 IEM_MC_LOCAL(RTUINT128U, uSrc);
1983
1984 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1985 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1986 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1987 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1988
1989 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1990 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1991
1992 IEM_MC_ADVANCE_RIP_AND_FINISH();
1993 IEM_MC_END();
1994 }
1995 else
1996 {
1997 IEM_MC_BEGIN(0, 2);
1998 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1999 IEM_MC_LOCAL(RTUINT256U, uSrc);
2000
2001 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2002 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2003 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2004 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2005
2006 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2007 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2008
2009 IEM_MC_ADVANCE_RIP_AND_FINISH();
2010 IEM_MC_END();
2011 }
2012 }
2013}
2014
2015/**
2016 * @opcode 0x29
2017 * @oppfx 66
2018 * @opcpuid avx
2019 * @opgroup og_avx_pcksclr_datamove
2020 * @opxcpttype 1
2021 * @optest op1=1 op2=2 -> op1=2
2022 * @optest op1=0 op2=-42 -> op1=-42
2023 * @note Almost identical to vmovaps
2024 */
2025FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
2026{
2027 IEMOP_MNEMONIC2(VEX_MR, VMOVAPD, vmovapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2028 Assert(pVCpu->iem.s.uVexLength <= 1);
2029 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2030 if (IEM_IS_MODRM_REG_MODE(bRm))
2031 {
2032 /*
2033 * Register, register.
2034 */
2035 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2036 IEM_MC_BEGIN(1, 0);
2037
2038 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2039 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2040 if (pVCpu->iem.s.uVexLength == 0)
2041 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2042 IEM_GET_MODRM_REG(pVCpu, bRm));
2043 else
2044 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2045 IEM_GET_MODRM_REG(pVCpu, bRm));
2046 IEM_MC_ADVANCE_RIP_AND_FINISH();
2047 IEM_MC_END();
2048 }
2049 else
2050 {
2051 /*
2052 * Register, memory.
2053 */
2054 if (pVCpu->iem.s.uVexLength == 0)
2055 {
2056 IEM_MC_BEGIN(0, 2);
2057 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2058 IEM_MC_LOCAL(RTUINT128U, uSrc);
2059
2060 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2061 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2062 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2063 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2064
2065 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2066 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2067
2068 IEM_MC_ADVANCE_RIP_AND_FINISH();
2069 IEM_MC_END();
2070 }
2071 else
2072 {
2073 IEM_MC_BEGIN(0, 2);
2074 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2075 IEM_MC_LOCAL(RTUINT256U, uSrc);
2076
2077 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2078 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2079 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2080 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2081
2082 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2083 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2084
2085 IEM_MC_ADVANCE_RIP_AND_FINISH();
2086 IEM_MC_END();
2087 }
2088 }
2089}
2090
2091
2092/**
2093 * @opmnemonic udvexf30f29
2094 * @opcode 0x29
2095 * @oppfx 0xf3
2096 * @opunused vex.modrm
2097 * @opcpuid avx
2098 * @optest ->
2099 * @opdone
2100 */
2101
2102/**
2103 * @opmnemonic udvexf20f29
2104 * @opcode 0x29
2105 * @oppfx 0xf2
2106 * @opunused vex.modrm
2107 * @opcpuid avx
2108 * @optest ->
2109 * @opdone
2110 */
2111
2112
2113/** Opcode VEX.0F 0x2a - invalid */
2114/** Opcode VEX.66.0F 0x2a - invalid */
2115/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
2116FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
2117/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
2118FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
2119
2120
2121/**
2122 * @opcode 0x2b
2123 * @opcodesub !11 mr/reg
2124 * @oppfx none
2125 * @opcpuid avx
2126 * @opgroup og_avx_cachect
2127 * @opxcpttype 1
2128 * @optest op1=1 op2=2 -> op1=2
2129 * @optest op1=0 op2=-42 -> op1=-42
2130 * @note Identical implementation to vmovntpd
2131 */
2132FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
2133{
2134 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPS, vmovntps, Mps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2135 Assert(pVCpu->iem.s.uVexLength <= 1);
2136 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2137 if (IEM_IS_MODRM_MEM_MODE(bRm))
2138 {
2139 /*
2140 * memory, register.
2141 */
2142 if (pVCpu->iem.s.uVexLength == 0)
2143 {
2144 IEM_MC_BEGIN(0, 2);
2145 IEM_MC_LOCAL(RTUINT128U, uSrc);
2146 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2147
2148 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2149 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2150 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2151 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2152
2153 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2154 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2155
2156 IEM_MC_ADVANCE_RIP_AND_FINISH();
2157 IEM_MC_END();
2158 }
2159 else
2160 {
2161 IEM_MC_BEGIN(0, 2);
2162 IEM_MC_LOCAL(RTUINT256U, uSrc);
2163 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2164
2165 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2166 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2167 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2168 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2169
2170 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2171 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2172
2173 IEM_MC_ADVANCE_RIP_AND_FINISH();
2174 IEM_MC_END();
2175 }
2176 }
2177 /* The register, register encoding is invalid. */
2178 else
2179 return IEMOP_RAISE_INVALID_OPCODE();
2180}
2181
2182/**
2183 * @opcode 0x2b
2184 * @opcodesub !11 mr/reg
2185 * @oppfx 0x66
2186 * @opcpuid avx
2187 * @opgroup og_avx_cachect
2188 * @opxcpttype 1
2189 * @optest op1=1 op2=2 -> op1=2
2190 * @optest op1=0 op2=-42 -> op1=-42
2191 * @note Identical implementation to vmovntps
2192 */
2193FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
2194{
2195 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPD, vmovntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2196 Assert(pVCpu->iem.s.uVexLength <= 1);
2197 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2198 if (IEM_IS_MODRM_MEM_MODE(bRm))
2199 {
2200 /*
2201 * memory, register.
2202 */
2203 if (pVCpu->iem.s.uVexLength == 0)
2204 {
2205 IEM_MC_BEGIN(0, 2);
2206 IEM_MC_LOCAL(RTUINT128U, uSrc);
2207 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2208
2209 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2210 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2211 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2212 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2213
2214 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2215 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2216
2217 IEM_MC_ADVANCE_RIP_AND_FINISH();
2218 IEM_MC_END();
2219 }
2220 else
2221 {
2222 IEM_MC_BEGIN(0, 2);
2223 IEM_MC_LOCAL(RTUINT256U, uSrc);
2224 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2225
2226 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2227 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2228 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2229 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2230
2231 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2232 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2233
2234 IEM_MC_ADVANCE_RIP_AND_FINISH();
2235 IEM_MC_END();
2236 }
2237 }
2238 /* The register, register encoding is invalid. */
2239 else
2240 return IEMOP_RAISE_INVALID_OPCODE();
2241}
2242
2243/**
2244 * @opmnemonic udvexf30f2b
2245 * @opcode 0x2b
2246 * @oppfx 0xf3
2247 * @opunused vex.modrm
2248 * @opcpuid avx
2249 * @optest ->
2250 * @opdone
2251 */
2252
2253/**
2254 * @opmnemonic udvexf20f2b
2255 * @opcode 0x2b
2256 * @oppfx 0xf2
2257 * @opunused vex.modrm
2258 * @opcpuid avx
2259 * @optest ->
2260 * @opdone
2261 */
2262
2263
2264/* Opcode VEX.0F 0x2c - invalid */
2265/* Opcode VEX.66.0F 0x2c - invalid */
2266/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
2267FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
2268/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
2269FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
2270
2271/* Opcode VEX.0F 0x2d - invalid */
2272/* Opcode VEX.66.0F 0x2d - invalid */
2273/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
2274FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
2275/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
2276FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
2277
2278
2279/** Opcode VEX.0F 0x2e - vucomiss Vss, Wss */
2280FNIEMOP_DEF(iemOp_vucomiss_Vss_Wss)
2281{
2282 IEMOP_MNEMONIC2(RM, VUCOMISS, vucomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2283 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2284 if (IEM_IS_MODRM_REG_MODE(bRm))
2285 {
2286 /*
2287 * Register, register.
2288 */
2289 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2290 IEM_MC_BEGIN(4, 1);
2291 IEM_MC_LOCAL(uint32_t, fEFlags);
2292 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2293 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2294 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2295 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3);
2296 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2297 IEM_MC_PREPARE_AVX_USAGE();
2298 IEM_MC_FETCH_EFLAGS(fEFlags);
2299 IEM_MC_REF_MXCSR(pfMxcsr);
2300 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2301 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2302 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2303 pfMxcsr, pEFlags, puSrc1, puSrc2);
2304 IEM_MC_IF_MXCSR_XCPT_PENDING()
2305 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2306 IEM_MC_ELSE()
2307 IEM_MC_COMMIT_EFLAGS(fEFlags);
2308 IEM_MC_ENDIF();
2309
2310 IEM_MC_ADVANCE_RIP_AND_FINISH();
2311 IEM_MC_END();
2312 }
2313 else
2314 {
2315 /*
2316 * Register, memory.
2317 */
2318 IEM_MC_BEGIN(4, 3);
2319 IEM_MC_LOCAL(uint32_t, fEFlags);
2320 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2321 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2322 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2323 IEM_MC_LOCAL(X86XMMREG, uSrc2);
2324 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);
2325 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2326
2327 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2328 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2329 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2330 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2331
2332 IEM_MC_PREPARE_AVX_USAGE();
2333 IEM_MC_FETCH_EFLAGS(fEFlags);
2334 IEM_MC_REF_MXCSR(pfMxcsr);
2335 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2336 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2337 pfMxcsr, pEFlags, puSrc1, puSrc2);
2338 IEM_MC_IF_MXCSR_XCPT_PENDING()
2339 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2340 IEM_MC_ELSE()
2341 IEM_MC_COMMIT_EFLAGS(fEFlags);
2342 IEM_MC_ENDIF();
2343
2344 IEM_MC_ADVANCE_RIP_AND_FINISH();
2345 IEM_MC_END();
2346 }
2347}
2348
2349
2350/** Opcode VEX.66.0F 0x2e - vucomisd Vsd, Wsd */
2351FNIEMOP_DEF(iemOp_vucomisd_Vsd_Wsd)
2352{
2353 IEMOP_MNEMONIC2(RM, VUCOMISD, vucomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2354 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2355 if (IEM_IS_MODRM_REG_MODE(bRm))
2356 {
2357 /*
2358 * Register, register.
2359 */
2360 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2361 IEM_MC_BEGIN(4, 1);
2362 IEM_MC_LOCAL(uint32_t, fEFlags);
2363 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2364 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2365 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2366 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3);
2367 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2368 IEM_MC_PREPARE_AVX_USAGE();
2369 IEM_MC_FETCH_EFLAGS(fEFlags);
2370 IEM_MC_REF_MXCSR(pfMxcsr);
2371 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2372 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2373 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2374 pfMxcsr, pEFlags, puSrc1, puSrc2);
2375 IEM_MC_IF_MXCSR_XCPT_PENDING()
2376 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2377 IEM_MC_ELSE()
2378 IEM_MC_COMMIT_EFLAGS(fEFlags);
2379 IEM_MC_ENDIF();
2380
2381 IEM_MC_ADVANCE_RIP_AND_FINISH();
2382 IEM_MC_END();
2383 }
2384 else
2385 {
2386 /*
2387 * Register, memory.
2388 */
2389 IEM_MC_BEGIN(4, 3);
2390 IEM_MC_LOCAL(uint32_t, fEFlags);
2391 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2392 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2393 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2394 IEM_MC_LOCAL(X86XMMREG, uSrc2);
2395 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);
2396 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2397
2398 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2399 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2400 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2401 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2402
2403 IEM_MC_PREPARE_AVX_USAGE();
2404 IEM_MC_FETCH_EFLAGS(fEFlags);
2405 IEM_MC_REF_MXCSR(pfMxcsr);
2406 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2407 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2408 pfMxcsr, pEFlags, puSrc1, puSrc2);
2409 IEM_MC_IF_MXCSR_XCPT_PENDING()
2410 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2411 IEM_MC_ELSE()
2412 IEM_MC_COMMIT_EFLAGS(fEFlags);
2413 IEM_MC_ENDIF();
2414
2415 IEM_MC_ADVANCE_RIP_AND_FINISH();
2416 IEM_MC_END();
2417 }
2418}
2419
2420
2421/* Opcode VEX.F3.0F 0x2e - invalid */
2422/* Opcode VEX.F2.0F 0x2e - invalid */
2423
2424/** Opcode VEX.0F 0x2f - vcomiss Vss, Wss */
2425FNIEMOP_DEF(iemOp_vcomiss_Vss_Wss)
2426{
2427 IEMOP_MNEMONIC2(RM, VCOMISS, vcomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2428 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2429 if (IEM_IS_MODRM_REG_MODE(bRm))
2430 {
2431 /*
2432 * Register, register.
2433 */
2434 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2435 IEM_MC_BEGIN(4, 1);
2436 IEM_MC_LOCAL(uint32_t, fEFlags);
2437 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2438 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2439 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2440 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3);
2441 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2442 IEM_MC_PREPARE_AVX_USAGE();
2443 IEM_MC_FETCH_EFLAGS(fEFlags);
2444 IEM_MC_REF_MXCSR(pfMxcsr);
2445 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2446 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2447 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2448 pfMxcsr, pEFlags, puSrc1, puSrc2);
2449 IEM_MC_IF_MXCSR_XCPT_PENDING()
2450 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2451 IEM_MC_ELSE()
2452 IEM_MC_COMMIT_EFLAGS(fEFlags);
2453 IEM_MC_ENDIF();
2454
2455 IEM_MC_ADVANCE_RIP_AND_FINISH();
2456 IEM_MC_END();
2457 }
2458 else
2459 {
2460 /*
2461 * Register, memory.
2462 */
2463 IEM_MC_BEGIN(4, 3);
2464 IEM_MC_LOCAL(uint32_t, fEFlags);
2465 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2466 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2467 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2468 IEM_MC_LOCAL(X86XMMREG, uSrc2);
2469 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);
2470 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2471
2472 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2473 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2474 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2475 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2476
2477 IEM_MC_PREPARE_AVX_USAGE();
2478 IEM_MC_FETCH_EFLAGS(fEFlags);
2479 IEM_MC_REF_MXCSR(pfMxcsr);
2480 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2481 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2482 pfMxcsr, pEFlags, puSrc1, puSrc2);
2483 IEM_MC_IF_MXCSR_XCPT_PENDING()
2484 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2485 IEM_MC_ELSE()
2486 IEM_MC_COMMIT_EFLAGS(fEFlags);
2487 IEM_MC_ENDIF();
2488
2489 IEM_MC_ADVANCE_RIP_AND_FINISH();
2490 IEM_MC_END();
2491 }
2492}
2493
2494
2495/** Opcode VEX.66.0F 0x2f - vcomisd Vsd, Wsd */
2496FNIEMOP_DEF(iemOp_vcomisd_Vsd_Wsd)
2497{
2498 IEMOP_MNEMONIC2(RM, VCOMISD, vcomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2499 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2500 if (IEM_IS_MODRM_REG_MODE(bRm))
2501 {
2502 /*
2503 * Register, register.
2504 */
2505 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2506 IEM_MC_BEGIN(4, 1);
2507 IEM_MC_LOCAL(uint32_t, fEFlags);
2508 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2509 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2510 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2511 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3);
2512 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2513 IEM_MC_PREPARE_AVX_USAGE();
2514 IEM_MC_FETCH_EFLAGS(fEFlags);
2515 IEM_MC_REF_MXCSR(pfMxcsr);
2516 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2517 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2518 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2519 pfMxcsr, pEFlags, puSrc1, puSrc2);
2520 IEM_MC_IF_MXCSR_XCPT_PENDING()
2521 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2522 IEM_MC_ELSE()
2523 IEM_MC_COMMIT_EFLAGS(fEFlags);
2524 IEM_MC_ENDIF();
2525
2526 IEM_MC_ADVANCE_RIP_AND_FINISH();
2527 IEM_MC_END();
2528 }
2529 else
2530 {
2531 /*
2532 * Register, memory.
2533 */
2534 IEM_MC_BEGIN(4, 3);
2535 IEM_MC_LOCAL(uint32_t, fEFlags);
2536 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2537 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2538 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2539 IEM_MC_LOCAL(X86XMMREG, uSrc2);
2540 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);
2541 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2542
2543 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2544 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2545 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2546 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2547
2548 IEM_MC_PREPARE_AVX_USAGE();
2549 IEM_MC_FETCH_EFLAGS(fEFlags);
2550 IEM_MC_REF_MXCSR(pfMxcsr);
2551 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2552 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2553 pfMxcsr, pEFlags, puSrc1, puSrc2);
2554 IEM_MC_IF_MXCSR_XCPT_PENDING()
2555 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2556 IEM_MC_ELSE()
2557 IEM_MC_COMMIT_EFLAGS(fEFlags);
2558 IEM_MC_ENDIF();
2559
2560 IEM_MC_ADVANCE_RIP_AND_FINISH();
2561 IEM_MC_END();
2562 }
2563}
2564
2565
2566/* Opcode VEX.F3.0F 0x2f - invalid */
2567/* Opcode VEX.F2.0F 0x2f - invalid */
2568
2569/* Opcode VEX.0F 0x30 - invalid */
2570/* Opcode VEX.0F 0x31 - invalid */
2571/* Opcode VEX.0F 0x32 - invalid */
2572/* Opcode VEX.0F 0x33 - invalid */
2573/* Opcode VEX.0F 0x34 - invalid */
2574/* Opcode VEX.0F 0x35 - invalid */
2575/* Opcode VEX.0F 0x36 - invalid */
2576/* Opcode VEX.0F 0x37 - invalid */
2577/* Opcode VEX.0F 0x38 - invalid */
2578/* Opcode VEX.0F 0x39 - invalid */
2579/* Opcode VEX.0F 0x3a - invalid */
2580/* Opcode VEX.0F 0x3b - invalid */
2581/* Opcode VEX.0F 0x3c - invalid */
2582/* Opcode VEX.0F 0x3d - invalid */
2583/* Opcode VEX.0F 0x3e - invalid */
2584/* Opcode VEX.0F 0x3f - invalid */
2585/* Opcode VEX.0F 0x40 - invalid */
2586/* Opcode VEX.0F 0x41 - invalid */
2587/* Opcode VEX.0F 0x42 - invalid */
2588/* Opcode VEX.0F 0x43 - invalid */
2589/* Opcode VEX.0F 0x44 - invalid */
2590/* Opcode VEX.0F 0x45 - invalid */
2591/* Opcode VEX.0F 0x46 - invalid */
2592/* Opcode VEX.0F 0x47 - invalid */
2593/* Opcode VEX.0F 0x48 - invalid */
2594/* Opcode VEX.0F 0x49 - invalid */
2595/* Opcode VEX.0F 0x4a - invalid */
2596/* Opcode VEX.0F 0x4b - invalid */
2597/* Opcode VEX.0F 0x4c - invalid */
2598/* Opcode VEX.0F 0x4d - invalid */
2599/* Opcode VEX.0F 0x4e - invalid */
2600/* Opcode VEX.0F 0x4f - invalid */
2601
2602
2603/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
2604FNIEMOP_DEF(iemOp_vmovmskps_Gy_Ups)
2605{
2606 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPS, vmovmskps, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2607 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2608 if (IEM_IS_MODRM_REG_MODE(bRm))
2609 {
2610 /*
2611 * Register, register.
2612 */
2613 if (pVCpu->iem.s.uVexLength == 0)
2614 {
2615 IEMOP_HLP_DONE_VEX_DECODING();
2616 IEM_MC_BEGIN(2, 1);
2617 IEM_MC_LOCAL(uint8_t, u8Dst);
2618 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2619 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2620 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2621 IEM_MC_PREPARE_AVX_USAGE();
2622 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2623 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskps_u128, iemAImpl_vmovmskps_u128_fallback),
2624 pu8Dst, puSrc);
2625 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2626 IEM_MC_ADVANCE_RIP_AND_FINISH();
2627 IEM_MC_END();
2628 }
2629 else
2630 {
2631 IEMOP_HLP_DONE_VEX_DECODING();
2632 IEM_MC_BEGIN(2, 2);
2633 IEM_MC_LOCAL(uint8_t, u8Dst);
2634 IEM_MC_LOCAL(RTUINT256U, uSrc);
2635 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2636 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2637
2638 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
2639 IEM_MC_PREPARE_AVX_USAGE();
2640 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2641 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskps_u256, iemAImpl_vmovmskps_u256_fallback),
2642 pu8Dst, puSrc);
2643 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2644 IEM_MC_ADVANCE_RIP_AND_FINISH();
2645 IEM_MC_END();
2646 }
2647 }
2648 /* No memory operand. */
2649 else
2650 return IEMOP_RAISE_INVALID_OPCODE();
2651}
2652
2653
2654/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
2655FNIEMOP_DEF(iemOp_vmovmskpd_Gy_Upd)
2656{
2657 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPD, vmovmskpd, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2658 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2659 if (IEM_IS_MODRM_REG_MODE(bRm))
2660 {
2661 /*
2662 * Register, register.
2663 */
2664 if (pVCpu->iem.s.uVexLength == 0)
2665 {
2666 IEMOP_HLP_DONE_VEX_DECODING();
2667 IEM_MC_BEGIN(2, 1);
2668 IEM_MC_LOCAL(uint8_t, u8Dst);
2669 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2670 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2671 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2672 IEM_MC_PREPARE_AVX_USAGE();
2673 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2674 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskpd_u128, iemAImpl_vmovmskpd_u128_fallback),
2675 pu8Dst, puSrc);
2676 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2677 IEM_MC_ADVANCE_RIP_AND_FINISH();
2678 IEM_MC_END();
2679 }
2680 else
2681 {
2682 IEMOP_HLP_DONE_VEX_DECODING();
2683 IEM_MC_BEGIN(2, 2);
2684 IEM_MC_LOCAL(uint8_t, u8Dst);
2685 IEM_MC_LOCAL(RTUINT256U, uSrc);
2686 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2687 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2688
2689 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
2690 IEM_MC_PREPARE_AVX_USAGE();
2691 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2692 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskpd_u256, iemAImpl_vmovmskpd_u256_fallback),
2693 pu8Dst, puSrc);
2694 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2695 IEM_MC_ADVANCE_RIP_AND_FINISH();
2696 IEM_MC_END();
2697 }
2698 }
2699 /* No memory operand. */
2700 else
2701 return IEMOP_RAISE_INVALID_OPCODE();
2702}
2703
2704
2705/* Opcode VEX.F3.0F 0x50 - invalid */
2706/* Opcode VEX.F2.0F 0x50 - invalid */
2707
2708/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
2709FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
2710/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
2711FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
2712/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
2713FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
2714/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
2715FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
2716
2717/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
2718FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
2719/* Opcode VEX.66.0F 0x52 - invalid */
2720/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
2721FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
2722/* Opcode VEX.F2.0F 0x52 - invalid */
2723
2724/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
2725FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
2726/* Opcode VEX.66.0F 0x53 - invalid */
2727/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
2728FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
2729/* Opcode VEX.F2.0F 0x53 - invalid */
2730
2731
2732/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
2733FNIEMOP_DEF(iemOp_vandps_Vps_Hps_Wps)
2734{
2735 IEMOP_MNEMONIC3(VEX_RVM, VANDPS, vandps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2736 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2737 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2738}
2739
2740
2741/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
2742FNIEMOP_DEF(iemOp_vandpd_Vpd_Hpd_Wpd)
2743{
2744 IEMOP_MNEMONIC3(VEX_RVM, VANDPD, vandpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2745 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2746 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2747}
2748
2749
2750/* Opcode VEX.F3.0F 0x54 - invalid */
2751/* Opcode VEX.F2.0F 0x54 - invalid */
2752
2753
2754/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
2755FNIEMOP_DEF(iemOp_vandnps_Vps_Hps_Wps)
2756{
2757 IEMOP_MNEMONIC3(VEX_RVM, VANDNPS, vandnps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2758 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2759 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2760}
2761
2762
2763/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
2764FNIEMOP_DEF(iemOp_vandnpd_Vpd_Hpd_Wpd)
2765{
2766 IEMOP_MNEMONIC3(VEX_RVM, VANDNPD, vandnpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2767 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2768 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2769}
2770
2771
2772/* Opcode VEX.F3.0F 0x55 - invalid */
2773/* Opcode VEX.F2.0F 0x55 - invalid */
2774
2775/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
2776FNIEMOP_DEF(iemOp_vorps_Vps_Hps_Wps)
2777{
2778 IEMOP_MNEMONIC3(VEX_RVM, VORPS, vorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2779 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2780 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2781}
2782
2783
2784/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
2785FNIEMOP_DEF(iemOp_vorpd_Vpd_Hpd_Wpd)
2786{
2787 IEMOP_MNEMONIC3(VEX_RVM, VORPD, vorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2788 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2789 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2790}
2791
2792
2793/* Opcode VEX.F3.0F 0x56 - invalid */
2794/* Opcode VEX.F2.0F 0x56 - invalid */
2795
2796
2797/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
2798FNIEMOP_DEF(iemOp_vxorps_Vps_Hps_Wps)
2799{
2800 IEMOP_MNEMONIC3(VEX_RVM, VXORPS, vxorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2801 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2802 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2803}
2804
2805
2806/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
2807FNIEMOP_DEF(iemOp_vxorpd_Vpd_Hpd_Wpd)
2808{
2809 IEMOP_MNEMONIC3(VEX_RVM, VXORPD, vxorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2810 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2811 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2812}
2813
2814
2815/* Opcode VEX.F3.0F 0x57 - invalid */
2816/* Opcode VEX.F2.0F 0x57 - invalid */
2817
2818/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
2819FNIEMOP_STUB(iemOp_vaddps_Vps_Hps_Wps);
2820/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
2821FNIEMOP_STUB(iemOp_vaddpd_Vpd_Hpd_Wpd);
2822/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
2823FNIEMOP_STUB(iemOp_vaddss_Vss_Hss_Wss);
2824/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
2825FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
2826
2827/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
2828FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
2829/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
2830FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
2831/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
2832FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
2833/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
2834FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
2835
2836/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
2837FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
2838/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
2839FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
2840/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
2841FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
2842/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
2843FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
2844
2845/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
2846FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
2847/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
2848FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
2849/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
2850FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
2851/* Opcode VEX.F2.0F 0x5b - invalid */
2852
2853/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
2854FNIEMOP_STUB(iemOp_vsubps_Vps_Hps_Wps);
2855/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
2856FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
2857/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
2858FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
2859/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
2860FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
2861
2862/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
2863FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
2864/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
2865FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
2866/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
2867FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
2868/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
2869FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
2870
2871/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
2872FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
2873/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
2874FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
2875/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
2876FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
2877/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
2878FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
2879
2880/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
2881FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
2882/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
2883FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
2884/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
2885FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
2886/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
2887FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
2888
2889
2890/* Opcode VEX.0F 0x60 - invalid */
2891
2892
2893/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, Wx */
2894FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
2895{
2896 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLBW, vpunpcklbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2897 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklbw);
2898 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2899}
2900
2901
2902/* Opcode VEX.F3.0F 0x60 - invalid */
2903
2904
2905/* Opcode VEX.0F 0x61 - invalid */
2906
2907
2908/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
2909FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
2910{
2911 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLWD, vpunpcklwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2912 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklwd);
2913 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2914}
2915
2916
2917/* Opcode VEX.F3.0F 0x61 - invalid */
2918
2919
2920/* Opcode VEX.0F 0x62 - invalid */
2921
2922/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
2923FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
2924{
2925 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLDQ, vpunpckldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2926 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckldq);
2927 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2928}
2929
2930
2931/* Opcode VEX.F3.0F 0x62 - invalid */
2932
2933
2934
2935/* Opcode VEX.0F 0x63 - invalid */
2936
2937
2938/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
2939FNIEMOP_DEF(iemOp_vpacksswb_Vx_Hx_Wx)
2940{
2941 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSWB, vpacksswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2942 IEMOPMEDIAOPTF3_INIT_VARS( vpacksswb);
2943 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2944}
2945
2946
2947/* Opcode VEX.F3.0F 0x63 - invalid */
2948
2949/* Opcode VEX.0F 0x64 - invalid */
2950
2951
2952/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
2953FNIEMOP_DEF(iemOp_vpcmpgtb_Vx_Hx_Wx)
2954{
2955 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTB, vpcmpgtb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2956 IEMOPMEDIAF3_INIT_VARS( vpcmpgtb);
2957 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2958}
2959
2960
2961/* Opcode VEX.F3.0F 0x64 - invalid */
2962
2963/* Opcode VEX.0F 0x65 - invalid */
2964
2965
2966/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
2967FNIEMOP_DEF(iemOp_vpcmpgtw_Vx_Hx_Wx)
2968{
2969 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTW, vpcmpgtw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2970 IEMOPMEDIAF3_INIT_VARS( vpcmpgtw);
2971 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2972}
2973
2974
2975/* Opcode VEX.F3.0F 0x65 - invalid */
2976
2977/* Opcode VEX.0F 0x66 - invalid */
2978
2979
2980/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
2981FNIEMOP_DEF(iemOp_vpcmpgtd_Vx_Hx_Wx)
2982{
2983 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTD, vpcmpgtd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2984 IEMOPMEDIAF3_INIT_VARS( vpcmpgtd);
2985 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2986}
2987
2988
2989/* Opcode VEX.F3.0F 0x66 - invalid */
2990
2991/* Opcode VEX.0F 0x67 - invalid */
2992
2993
2994/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
2995FNIEMOP_DEF(iemOp_vpackuswb_Vx_Hx_W)
2996{
2997 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSWB, vpackuswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2998 IEMOPMEDIAOPTF3_INIT_VARS( vpackuswb);
2999 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3000}
3001
3002
3003/* Opcode VEX.F3.0F 0x67 - invalid */
3004
3005
3006///**
3007// * Common worker for SSE2 instructions on the form:
3008// * pxxxx xmm1, xmm2/mem128
3009// *
3010// * The 2nd operand is the second half of a register, which in the memory case
3011// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
3012// * where it may read the full 128 bits or only the upper 64 bits.
3013// *
3014// * Exceptions type 4.
3015// */
3016//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
3017//{
3018// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3019// if (IEM_IS_MODRM_REG_MODE(bRm))
3020// {
3021// /*
3022// * Register, register.
3023// */
3024// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3025// IEM_MC_BEGIN(2, 0);
3026// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3027// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3028// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3029// IEM_MC_PREPARE_SSE_USAGE();
3030// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3031// IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3032// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3033// IEM_MC_ADVANCE_RIP_AND_FINISH();
3034// IEM_MC_END();
3035// }
3036// else
3037// {
3038// /*
3039// * Register, memory.
3040// */
3041// IEM_MC_BEGIN(2, 2);
3042// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3043// IEM_MC_LOCAL(RTUINT128U, uSrc);
3044// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3045// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3046//
3047// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3048// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3049// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3050// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
3051//
3052// IEM_MC_PREPARE_SSE_USAGE();
3053// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3054// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3055//
3056// IEM_MC_ADVANCE_RIP_AND_FINISH();
3057// IEM_MC_END();
3058// }
3059// return VINF_SUCCESS;
3060//}
3061
3062
3063/* Opcode VEX.0F 0x68 - invalid */
3064
3065/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
3066FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
3067{
3068 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHBW, vpunpckhbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3069 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhbw);
3070 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3071}
3072
3073
3074/* Opcode VEX.F3.0F 0x68 - invalid */
3075
3076
3077/* Opcode VEX.0F 0x69 - invalid */
3078
3079
3080/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
3081FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
3082{
3083 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHWD, vpunpckhwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3084 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhwd);
3085 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3086}
3087
3088
3089/* Opcode VEX.F3.0F 0x69 - invalid */
3090
3091
3092/* Opcode VEX.0F 0x6a - invalid */
3093
3094
3095/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
3096FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
3097{
3098 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHDQ, vpunpckhdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3099 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhdq);
3100 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3101}
3102
3103
3104/* Opcode VEX.F3.0F 0x6a - invalid */
3105
3106
3107/* Opcode VEX.0F 0x6b - invalid */
3108
3109
3110/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
3111FNIEMOP_DEF(iemOp_vpackssdw_Vx_Hx_Wx)
3112{
3113 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSDW, vpackssdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3114 IEMOPMEDIAOPTF3_INIT_VARS( vpackssdw);
3115 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3116}
3117
3118
3119/* Opcode VEX.F3.0F 0x6b - invalid */
3120
3121
3122/* Opcode VEX.0F 0x6c - invalid */
3123
3124
3125/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
3126FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
3127{
3128 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLQDQ, vpunpcklqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3129 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklqdq);
3130 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3131}
3132
3133
3134/* Opcode VEX.F3.0F 0x6c - invalid */
3135/* Opcode VEX.F2.0F 0x6c - invalid */
3136
3137
3138/* Opcode VEX.0F 0x6d - invalid */
3139
3140
3141/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
3142FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
3143{
3144 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHQDQ, vpunpckhqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3145 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhqdq);
3146 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3147}
3148
3149
3150/* Opcode VEX.F3.0F 0x6d - invalid */
3151
3152
3153/* Opcode VEX.0F 0x6e - invalid */
3154
3155FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
3156{
3157 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3158 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3159 {
3160 /**
3161 * @opcode 0x6e
3162 * @opcodesub rex.w=1
3163 * @oppfx 0x66
3164 * @opcpuid avx
3165 * @opgroup og_avx_simdint_datamov
3166 * @opxcpttype 5
3167 * @optest 64-bit / op1=1 op2=2 -> op1=2
3168 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3169 */
3170 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3171 if (IEM_IS_MODRM_REG_MODE(bRm))
3172 {
3173 /* XMM, greg64 */
3174 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3175 IEM_MC_BEGIN(0, 1);
3176 IEM_MC_LOCAL(uint64_t, u64Tmp);
3177
3178 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3179 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3180
3181 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3182 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3183
3184 IEM_MC_ADVANCE_RIP_AND_FINISH();
3185 IEM_MC_END();
3186 }
3187 else
3188 {
3189 /* XMM, [mem64] */
3190 IEM_MC_BEGIN(0, 2);
3191 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3192 IEM_MC_LOCAL(uint64_t, u64Tmp);
3193
3194 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3195 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3196 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3197 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3198
3199 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3200 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3201
3202 IEM_MC_ADVANCE_RIP_AND_FINISH();
3203 IEM_MC_END();
3204 }
3205 }
3206 else
3207 {
3208 /**
3209 * @opdone
3210 * @opcode 0x6e
3211 * @opcodesub rex.w=0
3212 * @oppfx 0x66
3213 * @opcpuid avx
3214 * @opgroup og_avx_simdint_datamov
3215 * @opxcpttype 5
3216 * @opfunction iemOp_vmovd_q_Vy_Ey
3217 * @optest op1=1 op2=2 -> op1=2
3218 * @optest op1=0 op2=-42 -> op1=-42
3219 */
3220 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3221 if (IEM_IS_MODRM_REG_MODE(bRm))
3222 {
3223 /* XMM, greg32 */
3224 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3225 IEM_MC_BEGIN(0, 1);
3226 IEM_MC_LOCAL(uint32_t, u32Tmp);
3227
3228 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3229 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3230
3231 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3232 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3233
3234 IEM_MC_ADVANCE_RIP_AND_FINISH();
3235 IEM_MC_END();
3236 }
3237 else
3238 {
3239 /* XMM, [mem32] */
3240 IEM_MC_BEGIN(0, 2);
3241 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3242 IEM_MC_LOCAL(uint32_t, u32Tmp);
3243
3244 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3245 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3246 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3247 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3248
3249 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3250 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3251
3252 IEM_MC_ADVANCE_RIP_AND_FINISH();
3253 IEM_MC_END();
3254 }
3255 }
3256}
3257
3258
3259/* Opcode VEX.F3.0F 0x6e - invalid */
3260
3261
3262/* Opcode VEX.0F 0x6f - invalid */
3263
3264/**
3265 * @opcode 0x6f
3266 * @oppfx 0x66
3267 * @opcpuid avx
3268 * @opgroup og_avx_simdint_datamove
3269 * @opxcpttype 1
3270 * @optest op1=1 op2=2 -> op1=2
3271 * @optest op1=0 op2=-42 -> op1=-42
3272 */
3273FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
3274{
3275 IEMOP_MNEMONIC2(VEX_RM, VMOVDQA, vmovdqa, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3276 Assert(pVCpu->iem.s.uVexLength <= 1);
3277 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3278 if (IEM_IS_MODRM_REG_MODE(bRm))
3279 {
3280 /*
3281 * Register, register.
3282 */
3283 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3284 IEM_MC_BEGIN(0, 0);
3285
3286 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3287 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3288 if (pVCpu->iem.s.uVexLength == 0)
3289 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3290 IEM_GET_MODRM_RM(pVCpu, bRm));
3291 else
3292 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3293 IEM_GET_MODRM_RM(pVCpu, bRm));
3294 IEM_MC_ADVANCE_RIP_AND_FINISH();
3295 IEM_MC_END();
3296 }
3297 else if (pVCpu->iem.s.uVexLength == 0)
3298 {
3299 /*
3300 * Register, memory128.
3301 */
3302 IEM_MC_BEGIN(0, 2);
3303 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3304 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3305
3306 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3307 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3308 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3309 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3310
3311 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3312 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3313
3314 IEM_MC_ADVANCE_RIP_AND_FINISH();
3315 IEM_MC_END();
3316 }
3317 else
3318 {
3319 /*
3320 * Register, memory256.
3321 */
3322 IEM_MC_BEGIN(0, 2);
3323 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3324 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3325
3326 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3327 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3328 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3329 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3330
3331 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3332 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3333
3334 IEM_MC_ADVANCE_RIP_AND_FINISH();
3335 IEM_MC_END();
3336 }
3337}
3338
3339/**
3340 * @opcode 0x6f
3341 * @oppfx 0xf3
3342 * @opcpuid avx
3343 * @opgroup og_avx_simdint_datamove
3344 * @opxcpttype 4UA
3345 * @optest op1=1 op2=2 -> op1=2
3346 * @optest op1=0 op2=-42 -> op1=-42
3347 */
3348FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
3349{
3350 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3351 Assert(pVCpu->iem.s.uVexLength <= 1);
3352 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3353 if (IEM_IS_MODRM_REG_MODE(bRm))
3354 {
3355 /*
3356 * Register, register.
3357 */
3358 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3359 IEM_MC_BEGIN(0, 0);
3360
3361 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3362 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3363 if (pVCpu->iem.s.uVexLength == 0)
3364 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3365 IEM_GET_MODRM_RM(pVCpu, bRm));
3366 else
3367 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3368 IEM_GET_MODRM_RM(pVCpu, bRm));
3369 IEM_MC_ADVANCE_RIP_AND_FINISH();
3370 IEM_MC_END();
3371 }
3372 else if (pVCpu->iem.s.uVexLength == 0)
3373 {
3374 /*
3375 * Register, memory128.
3376 */
3377 IEM_MC_BEGIN(0, 2);
3378 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3379 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3380
3381 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3382 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3383 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3384 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3385
3386 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3387 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3388
3389 IEM_MC_ADVANCE_RIP_AND_FINISH();
3390 IEM_MC_END();
3391 }
3392 else
3393 {
3394 /*
3395 * Register, memory256.
3396 */
3397 IEM_MC_BEGIN(0, 2);
3398 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3399 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3400
3401 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3402 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3403 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3404 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3405
3406 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3407 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3408
3409 IEM_MC_ADVANCE_RIP_AND_FINISH();
3410 IEM_MC_END();
3411 }
3412}
3413
3414
3415/* Opcode VEX.0F 0x70 - invalid */
3416
3417
3418/**
3419 * Common worker for AVX/AVX2 instructions on the forms:
3420 * - vpxxx xmm0, xmm2/mem128, imm8
3421 * - vpxxx ymm0, ymm2/mem256, imm8
3422 *
3423 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3424 */
3425FNIEMOP_DEF_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3426{
3427 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3428 if (IEM_IS_MODRM_REG_MODE(bRm))
3429 {
3430 /*
3431 * Register, register.
3432 */
3433 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3434 if (pVCpu->iem.s.uVexLength)
3435 {
3436 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3437 IEM_MC_BEGIN(3, 2);
3438 IEM_MC_LOCAL(RTUINT256U, uDst);
3439 IEM_MC_LOCAL(RTUINT256U, uSrc);
3440 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3441 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3442 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3443 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3444 IEM_MC_PREPARE_AVX_USAGE();
3445 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3446 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3447 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3448 IEM_MC_ADVANCE_RIP_AND_FINISH();
3449 IEM_MC_END();
3450 }
3451 else
3452 {
3453 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3454 IEM_MC_BEGIN(3, 0);
3455 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3456 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3457 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3458 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3459 IEM_MC_PREPARE_AVX_USAGE();
3460 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3461 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3462 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3463 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3464 IEM_MC_ADVANCE_RIP_AND_FINISH();
3465 IEM_MC_END();
3466 }
3467 }
3468 else
3469 {
3470 /*
3471 * Register, memory.
3472 */
3473 if (pVCpu->iem.s.uVexLength)
3474 {
3475 IEM_MC_BEGIN(3, 3);
3476 IEM_MC_LOCAL(RTUINT256U, uDst);
3477 IEM_MC_LOCAL(RTUINT256U, uSrc);
3478 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3479 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3480 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3481
3482 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3483 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3484 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3485 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3486 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3487 IEM_MC_PREPARE_AVX_USAGE();
3488
3489 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3490 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3491 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3492
3493 IEM_MC_ADVANCE_RIP_AND_FINISH();
3494 IEM_MC_END();
3495 }
3496 else
3497 {
3498 IEM_MC_BEGIN(3, 1);
3499 IEM_MC_LOCAL(RTUINT128U, uSrc);
3500 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3501 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3502 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
3503
3504 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3505 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3506 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3507 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3508 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3509 IEM_MC_PREPARE_AVX_USAGE();
3510
3511 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3512 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3513 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3514 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3515
3516 IEM_MC_ADVANCE_RIP_AND_FINISH();
3517 IEM_MC_END();
3518 }
3519 }
3520}
3521
3522
3523/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
3524FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
3525{
3526 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFD, vpshufd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3527 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufd_u128,
3528 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufd_u256, iemAImpl_vpshufd_u256_fallback));
3529
3530}
3531
3532
3533/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
3534FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
3535{
3536 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFHW, vpshufhw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3537 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufhw_u128,
3538 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufhw_u256, iemAImpl_vpshufhw_u256_fallback));
3539
3540}
3541
3542
3543/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
3544FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
3545{
3546 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFLW, vpshuflw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3547 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshuflw_u128,
3548 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshuflw_u256, iemAImpl_vpshuflw_u256_fallback));
3549}
3550
3551
3552/* Opcode VEX.0F 0x71 11/2 - invalid. */
3553/** Opcode VEX.66.0F 0x71 11/2. */
3554FNIEMOP_STUB_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
3555
3556/* Opcode VEX.0F 0x71 11/4 - invalid */
3557/** Opcode VEX.66.0F 0x71 11/4. */
3558FNIEMOP_STUB_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm);
3559
3560/* Opcode VEX.0F 0x71 11/6 - invalid */
3561/** Opcode VEX.66.0F 0x71 11/6. */
3562FNIEMOP_STUB_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm);
3563
3564
3565/**
3566 * VEX Group 12 jump table for register variant.
3567 */
3568IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
3569{
3570 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3571 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3572 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3573 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3574 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3575 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3576 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3577 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3578};
3579AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
3580
3581
3582/** Opcode VEX.0F 0x71. */
3583FNIEMOP_DEF(iemOp_VGrp12)
3584{
3585 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3586 if (IEM_IS_MODRM_REG_MODE(bRm))
3587 /* register, register */
3588 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3589 + pVCpu->iem.s.idxPrefix], bRm);
3590 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3591}
3592
3593
3594/* Opcode VEX.0F 0x72 11/2 - invalid. */
3595/** Opcode VEX.66.0F 0x72 11/2. */
3596FNIEMOP_STUB_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
3597
3598/* Opcode VEX.0F 0x72 11/4 - invalid. */
3599/** Opcode VEX.66.0F 0x72 11/4. */
3600FNIEMOP_STUB_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm);
3601
3602/* Opcode VEX.0F 0x72 11/6 - invalid. */
3603/** Opcode VEX.66.0F 0x72 11/6. */
3604FNIEMOP_STUB_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm);
3605
3606
3607/**
3608 * Group 13 jump table for register variant.
3609 */
3610IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
3611{
3612 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3613 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3614 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3615 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3616 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3617 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3618 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3619 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3620};
3621AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
3622
3623/** Opcode VEX.0F 0x72. */
3624FNIEMOP_DEF(iemOp_VGrp13)
3625{
3626 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3627 if (IEM_IS_MODRM_REG_MODE(bRm))
3628 /* register, register */
3629 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3630 + pVCpu->iem.s.idxPrefix], bRm);
3631 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3632}
3633
3634
3635/* Opcode VEX.0F 0x73 11/2 - invalid. */
3636/** Opcode VEX.66.0F 0x73 11/2. */
3637FNIEMOP_STUB_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
3638
3639/** Opcode VEX.66.0F 0x73 11/3. */
3640FNIEMOP_STUB_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm);
3641
3642/* Opcode VEX.0F 0x73 11/6 - invalid. */
3643/** Opcode VEX.66.0F 0x73 11/6. */
3644FNIEMOP_STUB_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm);
3645
3646/** Opcode VEX.66.0F 0x73 11/7. */
3647FNIEMOP_STUB_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm);
3648
3649/**
3650 * Group 14 jump table for register variant.
3651 */
3652IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
3653{
3654 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3655 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3656 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3657 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3658 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3659 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3660 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3661 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3662};
3663AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
3664
3665
3666/** Opcode VEX.0F 0x73. */
3667FNIEMOP_DEF(iemOp_VGrp14)
3668{
3669 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3670 if (IEM_IS_MODRM_REG_MODE(bRm))
3671 /* register, register */
3672 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3673 + pVCpu->iem.s.idxPrefix], bRm);
3674 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3675}
3676
3677
3678/* Opcode VEX.0F 0x74 - invalid */
3679
3680
3681/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
3682FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
3683{
3684 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQB, vpcmpeqb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3685 IEMOPMEDIAF3_INIT_VARS( vpcmpeqb);
3686 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3687}
3688
3689/* Opcode VEX.F3.0F 0x74 - invalid */
3690/* Opcode VEX.F2.0F 0x74 - invalid */
3691
3692
3693/* Opcode VEX.0F 0x75 - invalid */
3694
3695
3696/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
3697FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
3698{
3699 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQW, vpcmpeqw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3700 IEMOPMEDIAF3_INIT_VARS( vpcmpeqw);
3701 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3702}
3703
3704
3705/* Opcode VEX.F3.0F 0x75 - invalid */
3706/* Opcode VEX.F2.0F 0x75 - invalid */
3707
3708
3709/* Opcode VEX.0F 0x76 - invalid */
3710
3711
3712/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
3713FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
3714{
3715 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQD, vpcmpeqd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3716 IEMOPMEDIAF3_INIT_VARS( vpcmpeqd);
3717 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3718}
3719
3720
3721/* Opcode VEX.F3.0F 0x76 - invalid */
3722/* Opcode VEX.F2.0F 0x76 - invalid */
3723
3724
3725/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
3726FNIEMOP_DEF(iemOp_vzeroupperv__vzeroallv)
3727{
3728 Assert(pVCpu->iem.s.uVexLength <= 1);
3729 if (pVCpu->iem.s.uVexLength == 0)
3730 {
3731 /*
3732 * 128-bit: vzeroupper
3733 */
3734 IEMOP_MNEMONIC(vzeroupper, "vzeroupper");
3735 IEM_MC_BEGIN(0, 0);
3736
3737 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3738 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3739 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3740
3741 IEM_MC_CLEAR_YREG_128_UP(0);
3742 IEM_MC_CLEAR_YREG_128_UP(1);
3743 IEM_MC_CLEAR_YREG_128_UP(2);
3744 IEM_MC_CLEAR_YREG_128_UP(3);
3745 IEM_MC_CLEAR_YREG_128_UP(4);
3746 IEM_MC_CLEAR_YREG_128_UP(5);
3747 IEM_MC_CLEAR_YREG_128_UP(6);
3748 IEM_MC_CLEAR_YREG_128_UP(7);
3749
3750 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
3751 {
3752 IEM_MC_CLEAR_YREG_128_UP( 8);
3753 IEM_MC_CLEAR_YREG_128_UP( 9);
3754 IEM_MC_CLEAR_YREG_128_UP(10);
3755 IEM_MC_CLEAR_YREG_128_UP(11);
3756 IEM_MC_CLEAR_YREG_128_UP(12);
3757 IEM_MC_CLEAR_YREG_128_UP(13);
3758 IEM_MC_CLEAR_YREG_128_UP(14);
3759 IEM_MC_CLEAR_YREG_128_UP(15);
3760 }
3761
3762 IEM_MC_ADVANCE_RIP_AND_FINISH();
3763 IEM_MC_END();
3764 }
3765 else
3766 {
3767 /*
3768 * 256-bit: vzeroall
3769 */
3770 IEMOP_MNEMONIC(vzeroall, "vzeroall");
3771 IEM_MC_BEGIN(0, 1);
3772 IEM_MC_LOCAL(uint32_t, uZero);
3773
3774 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3775 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3776 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3777
3778 IEM_MC_ASSIGN(uZero, 0);
3779 IEM_MC_STORE_YREG_U32_ZX_VLMAX(0, uZero);
3780 IEM_MC_STORE_YREG_U32_ZX_VLMAX(1, uZero);
3781 IEM_MC_STORE_YREG_U32_ZX_VLMAX(2, uZero);
3782 IEM_MC_STORE_YREG_U32_ZX_VLMAX(3, uZero);
3783 IEM_MC_STORE_YREG_U32_ZX_VLMAX(4, uZero);
3784 IEM_MC_STORE_YREG_U32_ZX_VLMAX(5, uZero);
3785 IEM_MC_STORE_YREG_U32_ZX_VLMAX(6, uZero);
3786 IEM_MC_STORE_YREG_U32_ZX_VLMAX(7, uZero);
3787
3788 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
3789 {
3790 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 8, uZero);
3791 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 9, uZero);
3792 IEM_MC_STORE_YREG_U32_ZX_VLMAX(10, uZero);
3793 IEM_MC_STORE_YREG_U32_ZX_VLMAX(11, uZero);
3794 IEM_MC_STORE_YREG_U32_ZX_VLMAX(12, uZero);
3795 IEM_MC_STORE_YREG_U32_ZX_VLMAX(13, uZero);
3796 IEM_MC_STORE_YREG_U32_ZX_VLMAX(14, uZero);
3797 IEM_MC_STORE_YREG_U32_ZX_VLMAX(15, uZero);
3798 }
3799
3800 IEM_MC_ADVANCE_RIP_AND_FINISH();
3801 IEM_MC_END();
3802 }
3803}
3804
3805
3806/* Opcode VEX.66.0F 0x77 - invalid */
3807/* Opcode VEX.F3.0F 0x77 - invalid */
3808/* Opcode VEX.F2.0F 0x77 - invalid */
3809
3810/* Opcode VEX.0F 0x78 - invalid */
3811/* Opcode VEX.66.0F 0x78 - invalid */
3812/* Opcode VEX.F3.0F 0x78 - invalid */
3813/* Opcode VEX.F2.0F 0x78 - invalid */
3814
3815/* Opcode VEX.0F 0x79 - invalid */
3816/* Opcode VEX.66.0F 0x79 - invalid */
3817/* Opcode VEX.F3.0F 0x79 - invalid */
3818/* Opcode VEX.F2.0F 0x79 - invalid */
3819
3820/* Opcode VEX.0F 0x7a - invalid */
3821/* Opcode VEX.66.0F 0x7a - invalid */
3822/* Opcode VEX.F3.0F 0x7a - invalid */
3823/* Opcode VEX.F2.0F 0x7a - invalid */
3824
3825/* Opcode VEX.0F 0x7b - invalid */
3826/* Opcode VEX.66.0F 0x7b - invalid */
3827/* Opcode VEX.F3.0F 0x7b - invalid */
3828/* Opcode VEX.F2.0F 0x7b - invalid */
3829
3830/* Opcode VEX.0F 0x7c - invalid */
3831/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
3832FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
3833/* Opcode VEX.F3.0F 0x7c - invalid */
3834/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
3835FNIEMOP_STUB(iemOp_vhaddps_Vps_Hps_Wps);
3836
3837/* Opcode VEX.0F 0x7d - invalid */
3838/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
3839FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
3840/* Opcode VEX.F3.0F 0x7d - invalid */
3841/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
3842FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
3843
3844
3845/* Opcode VEX.0F 0x7e - invalid */
3846
3847FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
3848{
3849 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3850 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3851 {
3852 /**
3853 * @opcode 0x7e
3854 * @opcodesub rex.w=1
3855 * @oppfx 0x66
3856 * @opcpuid avx
3857 * @opgroup og_avx_simdint_datamov
3858 * @opxcpttype 5
3859 * @optest 64-bit / op1=1 op2=2 -> op1=2
3860 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3861 */
3862 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3863 if (IEM_IS_MODRM_REG_MODE(bRm))
3864 {
3865 /* greg64, XMM */
3866 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3867 IEM_MC_BEGIN(0, 1);
3868 IEM_MC_LOCAL(uint64_t, u64Tmp);
3869
3870 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3871 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3872
3873 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3874 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp);
3875
3876 IEM_MC_ADVANCE_RIP_AND_FINISH();
3877 IEM_MC_END();
3878 }
3879 else
3880 {
3881 /* [mem64], XMM */
3882 IEM_MC_BEGIN(0, 2);
3883 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3884 IEM_MC_LOCAL(uint64_t, u64Tmp);
3885
3886 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3887 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3888 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3889 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3890
3891 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3892 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
3893
3894 IEM_MC_ADVANCE_RIP_AND_FINISH();
3895 IEM_MC_END();
3896 }
3897 }
3898 else
3899 {
3900 /**
3901 * @opdone
3902 * @opcode 0x7e
3903 * @opcodesub rex.w=0
3904 * @oppfx 0x66
3905 * @opcpuid avx
3906 * @opgroup og_avx_simdint_datamov
3907 * @opxcpttype 5
3908 * @opfunction iemOp_vmovd_q_Vy_Ey
3909 * @optest op1=1 op2=2 -> op1=2
3910 * @optest op1=0 op2=-42 -> op1=-42
3911 */
3912 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3913 if (IEM_IS_MODRM_REG_MODE(bRm))
3914 {
3915 /* greg32, XMM */
3916 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3917 IEM_MC_BEGIN(0, 1);
3918 IEM_MC_LOCAL(uint32_t, u32Tmp);
3919
3920 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3921 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3922
3923 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3924 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp);
3925
3926 IEM_MC_ADVANCE_RIP_AND_FINISH();
3927 IEM_MC_END();
3928 }
3929 else
3930 {
3931 /* [mem32], XMM */
3932 IEM_MC_BEGIN(0, 2);
3933 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3934 IEM_MC_LOCAL(uint32_t, u32Tmp);
3935
3936 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3937 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3938 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3939 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3940
3941 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3942 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
3943
3944 IEM_MC_ADVANCE_RIP_AND_FINISH();
3945 IEM_MC_END();
3946 }
3947 }
3948}
3949
3950
3951/**
3952 * @opcode 0x7e
3953 * @oppfx 0xf3
3954 * @opcpuid avx
3955 * @opgroup og_avx_pcksclr_datamove
3956 * @opxcpttype none
3957 * @optest op1=1 op2=2 -> op1=2
3958 * @optest op1=0 op2=-42 -> op1=-42
3959 */
3960FNIEMOP_DEF(iemOp_vmovq_Vq_Wq)
3961{
3962 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
3963 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3964 if (IEM_IS_MODRM_REG_MODE(bRm))
3965 {
3966 /*
3967 * Register, register.
3968 */
3969 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3970 IEM_MC_BEGIN(0, 0);
3971
3972 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3973 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3974
3975 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3976 IEM_GET_MODRM_RM(pVCpu, bRm));
3977 IEM_MC_ADVANCE_RIP_AND_FINISH();
3978 IEM_MC_END();
3979 }
3980 else
3981 {
3982 /*
3983 * Memory, register.
3984 */
3985 IEM_MC_BEGIN(0, 2);
3986 IEM_MC_LOCAL(uint64_t, uSrc);
3987 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3988
3989 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3990 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3991 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3992 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3993
3994 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3995 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
3996
3997 IEM_MC_ADVANCE_RIP_AND_FINISH();
3998 IEM_MC_END();
3999 }
4000
4001}
4002/* Opcode VEX.F2.0F 0x7e - invalid */
4003
4004
4005/* Opcode VEX.0F 0x7f - invalid */
4006
4007/**
4008 * @opcode 0x7f
4009 * @oppfx 0x66
4010 * @opcpuid avx
4011 * @opgroup og_avx_simdint_datamove
4012 * @opxcpttype 1
4013 * @optest op1=1 op2=2 -> op1=2
4014 * @optest op1=0 op2=-42 -> op1=-42
4015 */
4016FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
4017{
4018 IEMOP_MNEMONIC2(VEX_MR, VMOVDQA, vmovdqa, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4019 Assert(pVCpu->iem.s.uVexLength <= 1);
4020 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4021 if (IEM_IS_MODRM_REG_MODE(bRm))
4022 {
4023 /*
4024 * Register, register.
4025 */
4026 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4027 IEM_MC_BEGIN(0, 0);
4028
4029 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4030 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4031 if (pVCpu->iem.s.uVexLength == 0)
4032 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4033 IEM_GET_MODRM_REG(pVCpu, bRm));
4034 else
4035 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4036 IEM_GET_MODRM_REG(pVCpu, bRm));
4037 IEM_MC_ADVANCE_RIP_AND_FINISH();
4038 IEM_MC_END();
4039 }
4040 else if (pVCpu->iem.s.uVexLength == 0)
4041 {
4042 /*
4043 * Register, memory128.
4044 */
4045 IEM_MC_BEGIN(0, 2);
4046 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4047 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4048
4049 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4050 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4051 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4052 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4053
4054 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4055 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4056
4057 IEM_MC_ADVANCE_RIP_AND_FINISH();
4058 IEM_MC_END();
4059 }
4060 else
4061 {
4062 /*
4063 * Register, memory256.
4064 */
4065 IEM_MC_BEGIN(0, 2);
4066 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4067 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4068
4069 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4070 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4071 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4072 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4073
4074 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4075 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4076
4077 IEM_MC_ADVANCE_RIP_AND_FINISH();
4078 IEM_MC_END();
4079 }
4080}
4081
4082
4083/**
4084 * @opcode 0x7f
4085 * @oppfx 0xf3
4086 * @opcpuid avx
4087 * @opgroup og_avx_simdint_datamove
4088 * @opxcpttype 4UA
4089 * @optest op1=1 op2=2 -> op1=2
4090 * @optest op1=0 op2=-42 -> op1=-42
4091 */
4092FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
4093{
4094 IEMOP_MNEMONIC2(VEX_MR, VMOVDQU, vmovdqu, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4095 Assert(pVCpu->iem.s.uVexLength <= 1);
4096 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4097 if (IEM_IS_MODRM_REG_MODE(bRm))
4098 {
4099 /*
4100 * Register, register.
4101 */
4102 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4103 IEM_MC_BEGIN(0, 0);
4104
4105 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4106 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4107 if (pVCpu->iem.s.uVexLength == 0)
4108 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4109 IEM_GET_MODRM_REG(pVCpu, bRm));
4110 else
4111 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4112 IEM_GET_MODRM_REG(pVCpu, bRm));
4113 IEM_MC_ADVANCE_RIP_AND_FINISH();
4114 IEM_MC_END();
4115 }
4116 else if (pVCpu->iem.s.uVexLength == 0)
4117 {
4118 /*
4119 * Register, memory128.
4120 */
4121 IEM_MC_BEGIN(0, 2);
4122 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4123 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4124
4125 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4126 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4127 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4128 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4129
4130 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4131 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4132
4133 IEM_MC_ADVANCE_RIP_AND_FINISH();
4134 IEM_MC_END();
4135 }
4136 else
4137 {
4138 /*
4139 * Register, memory256.
4140 */
4141 IEM_MC_BEGIN(0, 2);
4142 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4143 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4144
4145 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4146 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4147 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4148 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4149
4150 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4151 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4152
4153 IEM_MC_ADVANCE_RIP_AND_FINISH();
4154 IEM_MC_END();
4155 }
4156}
4157
4158/* Opcode VEX.F2.0F 0x7f - invalid */
4159
4160
4161/* Opcode VEX.0F 0x80 - invalid */
4162/* Opcode VEX.0F 0x81 - invalid */
4163/* Opcode VEX.0F 0x82 - invalid */
4164/* Opcode VEX.0F 0x83 - invalid */
4165/* Opcode VEX.0F 0x84 - invalid */
4166/* Opcode VEX.0F 0x85 - invalid */
4167/* Opcode VEX.0F 0x86 - invalid */
4168/* Opcode VEX.0F 0x87 - invalid */
4169/* Opcode VEX.0F 0x88 - invalid */
4170/* Opcode VEX.0F 0x89 - invalid */
4171/* Opcode VEX.0F 0x8a - invalid */
4172/* Opcode VEX.0F 0x8b - invalid */
4173/* Opcode VEX.0F 0x8c - invalid */
4174/* Opcode VEX.0F 0x8d - invalid */
4175/* Opcode VEX.0F 0x8e - invalid */
4176/* Opcode VEX.0F 0x8f - invalid */
4177/* Opcode VEX.0F 0x90 - invalid */
4178/* Opcode VEX.0F 0x91 - invalid */
4179/* Opcode VEX.0F 0x92 - invalid */
4180/* Opcode VEX.0F 0x93 - invalid */
4181/* Opcode VEX.0F 0x94 - invalid */
4182/* Opcode VEX.0F 0x95 - invalid */
4183/* Opcode VEX.0F 0x96 - invalid */
4184/* Opcode VEX.0F 0x97 - invalid */
4185/* Opcode VEX.0F 0x98 - invalid */
4186/* Opcode VEX.0F 0x99 - invalid */
4187/* Opcode VEX.0F 0x9a - invalid */
4188/* Opcode VEX.0F 0x9b - invalid */
4189/* Opcode VEX.0F 0x9c - invalid */
4190/* Opcode VEX.0F 0x9d - invalid */
4191/* Opcode VEX.0F 0x9e - invalid */
4192/* Opcode VEX.0F 0x9f - invalid */
4193/* Opcode VEX.0F 0xa0 - invalid */
4194/* Opcode VEX.0F 0xa1 - invalid */
4195/* Opcode VEX.0F 0xa2 - invalid */
4196/* Opcode VEX.0F 0xa3 - invalid */
4197/* Opcode VEX.0F 0xa4 - invalid */
4198/* Opcode VEX.0F 0xa5 - invalid */
4199/* Opcode VEX.0F 0xa6 - invalid */
4200/* Opcode VEX.0F 0xa7 - invalid */
4201/* Opcode VEX.0F 0xa8 - invalid */
4202/* Opcode VEX.0F 0xa9 - invalid */
4203/* Opcode VEX.0F 0xaa - invalid */
4204/* Opcode VEX.0F 0xab - invalid */
4205/* Opcode VEX.0F 0xac - invalid */
4206/* Opcode VEX.0F 0xad - invalid */
4207
4208
4209/* Opcode VEX.0F 0xae mem/0 - invalid. */
4210/* Opcode VEX.0F 0xae mem/1 - invalid. */
4211
4212/**
4213 * @ opmaps grp15
4214 * @ opcode !11/2
4215 * @ oppfx none
4216 * @ opcpuid sse
4217 * @ opgroup og_sse_mxcsrsm
4218 * @ opxcpttype 5
4219 * @ optest op1=0 -> mxcsr=0
4220 * @ optest op1=0x2083 -> mxcsr=0x2083
4221 * @ optest op1=0xfffffffe -> value.xcpt=0xd
4222 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
4223 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
4224 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
4225 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
4226 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
4227 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4228 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4229 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4230 */
4231FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
4232//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
4233//{
4234// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
4235// if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
4236// return IEMOP_RAISE_INVALID_OPCODE();
4237//
4238// IEM_MC_BEGIN(2, 0);
4239// IEM_MC_ARG(uint8_t, iEffSeg, 0);
4240// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4241// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4242// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4243// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4244// IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
4245// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
4246// IEM_MC_END();
4247// return VINF_SUCCESS;
4248//}
4249
4250
4251/**
4252 * @opmaps vexgrp15
4253 * @opcode !11/3
4254 * @oppfx none
4255 * @opcpuid avx
4256 * @opgroup og_avx_mxcsrsm
4257 * @opxcpttype 5
4258 * @optest mxcsr=0 -> op1=0
4259 * @optest mxcsr=0x2083 -> op1=0x2083
4260 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
4261 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
4262 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
4263 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
4264 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
4265 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
4266 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
4267 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
4268 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
4269 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
4270 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4271 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
4272 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4273 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
4274 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4275 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
4276 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
4277 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
4278 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
4279 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
4280 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
4281 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
4282 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
4283 * -> value.xcpt=0x6
4284 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
4285 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
4286 * APMv4 rev 3.17 page 509.
4287 * @todo Test this instruction on AMD Ryzen.
4288 */
4289FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
4290{
4291 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4292 IEM_MC_BEGIN(2, 0);
4293 IEM_MC_ARG(uint8_t, iEffSeg, 0);
4294 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4295 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4296 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
4297 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4298 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
4299 IEM_MC_CALL_CIMPL_2(iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
4300 IEM_MC_END();
4301 return VINF_SUCCESS;
4302}
4303
4304/* Opcode VEX.0F 0xae mem/4 - invalid. */
4305/* Opcode VEX.0F 0xae mem/5 - invalid. */
4306/* Opcode VEX.0F 0xae mem/6 - invalid. */
4307/* Opcode VEX.0F 0xae mem/7 - invalid. */
4308
4309/* Opcode VEX.0F 0xae 11b/0 - invalid. */
4310/* Opcode VEX.0F 0xae 11b/1 - invalid. */
4311/* Opcode VEX.0F 0xae 11b/2 - invalid. */
4312/* Opcode VEX.0F 0xae 11b/3 - invalid. */
4313/* Opcode VEX.0F 0xae 11b/4 - invalid. */
4314/* Opcode VEX.0F 0xae 11b/5 - invalid. */
4315/* Opcode VEX.0F 0xae 11b/6 - invalid. */
4316/* Opcode VEX.0F 0xae 11b/7 - invalid. */
4317
4318/**
4319 * Vex group 15 jump table for memory variant.
4320 */
4321IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
4322{ /* pfx: none, 066h, 0f3h, 0f2h */
4323 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4324 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4325 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4326 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4327 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4328 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4329 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4330 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4331};
4332AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
4333
4334
4335/** Opcode vex. 0xae. */
4336FNIEMOP_DEF(iemOp_VGrp15)
4337{
4338 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4339 if (IEM_IS_MODRM_REG_MODE(bRm))
4340 /* register, register */
4341 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
4342
4343 /* memory, register */
4344 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4345 + pVCpu->iem.s.idxPrefix], bRm);
4346}
4347
4348
4349/* Opcode VEX.0F 0xaf - invalid. */
4350
4351/* Opcode VEX.0F 0xb0 - invalid. */
4352/* Opcode VEX.0F 0xb1 - invalid. */
4353/* Opcode VEX.0F 0xb2 - invalid. */
4354/* Opcode VEX.0F 0xb2 - invalid. */
4355/* Opcode VEX.0F 0xb3 - invalid. */
4356/* Opcode VEX.0F 0xb4 - invalid. */
4357/* Opcode VEX.0F 0xb5 - invalid. */
4358/* Opcode VEX.0F 0xb6 - invalid. */
4359/* Opcode VEX.0F 0xb7 - invalid. */
4360/* Opcode VEX.0F 0xb8 - invalid. */
4361/* Opcode VEX.0F 0xb9 - invalid. */
4362/* Opcode VEX.0F 0xba - invalid. */
4363/* Opcode VEX.0F 0xbb - invalid. */
4364/* Opcode VEX.0F 0xbc - invalid. */
4365/* Opcode VEX.0F 0xbd - invalid. */
4366/* Opcode VEX.0F 0xbe - invalid. */
4367/* Opcode VEX.0F 0xbf - invalid. */
4368
4369/* Opcode VEX.0F 0xc0 - invalid. */
4370/* Opcode VEX.66.0F 0xc0 - invalid. */
4371/* Opcode VEX.F3.0F 0xc0 - invalid. */
4372/* Opcode VEX.F2.0F 0xc0 - invalid. */
4373
4374/* Opcode VEX.0F 0xc1 - invalid. */
4375/* Opcode VEX.66.0F 0xc1 - invalid. */
4376/* Opcode VEX.F3.0F 0xc1 - invalid. */
4377/* Opcode VEX.F2.0F 0xc1 - invalid. */
4378
4379/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
4380FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
4381/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
4382FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
4383/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
4384FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
4385/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
4386FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
4387
4388/* Opcode VEX.0F 0xc3 - invalid */
4389/* Opcode VEX.66.0F 0xc3 - invalid */
4390/* Opcode VEX.F3.0F 0xc3 - invalid */
4391/* Opcode VEX.F2.0F 0xc3 - invalid */
4392
4393/* Opcode VEX.0F 0xc4 - invalid */
4394
4395
4396/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
4397FNIEMOP_DEF(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib)
4398{
4399 /*IEMOP_MNEMONIC4(VEX_RMV, VPINSRW, vpinsrw, Vdq, Vdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
4400 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4401 if (IEM_IS_MODRM_REG_MODE(bRm))
4402 {
4403 /*
4404 * Register, register.
4405 */
4406 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4407 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4408 IEM_MC_BEGIN(4, 0);
4409 IEM_MC_ARG(PRTUINT128U, puDst, 0);
4410 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4411 IEM_MC_ARG(uint16_t, u16Src, 2);
4412 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
4413 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4414 IEM_MC_PREPARE_AVX_USAGE();
4415 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4416 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4417 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, bRm));
4418 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpinsrw_u128, iemAImpl_vpinsrw_u128_fallback),
4419 puDst, puSrc, u16Src, bImmArg);
4420 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
4421 IEM_MC_ADVANCE_RIP_AND_FINISH();
4422 IEM_MC_END();
4423 }
4424 else
4425 {
4426 /*
4427 * Register, memory.
4428 */
4429 IEM_MC_BEGIN(4, 1);
4430 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4431 IEM_MC_ARG(PRTUINT128U, puDst, 0);
4432 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4433 IEM_MC_ARG(uint16_t, u16Src, 2);
4434
4435 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4436 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4437 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
4438 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4439 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4440 IEM_MC_PREPARE_AVX_USAGE();
4441
4442 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4443 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4444 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4445 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpinsrw_u128, iemAImpl_vpinsrw_u128_fallback),
4446 puDst, puSrc, u16Src, bImmArg);
4447 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
4448
4449 IEM_MC_ADVANCE_RIP_AND_FINISH();
4450 IEM_MC_END();
4451 }
4452}
4453
4454
4455/* Opcode VEX.F3.0F 0xc4 - invalid */
4456/* Opcode VEX.F2.0F 0xc4 - invalid */
4457
4458/* Opcode VEX.0F 0xc5 - invlid */
4459
4460
4461/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
4462FNIEMOP_DEF(iemOp_vpextrw_Gd_Udq_Ib)
4463{
4464 IEMOP_MNEMONIC3(VEX_RMI_REG, VPEXTRW, vpextrw, Gd, Ux, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
4465 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4466 if (IEM_IS_MODRM_REG_MODE(bRm))
4467 {
4468 /*
4469 * Register, register.
4470 */
4471 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4472 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4473 IEM_MC_BEGIN(3, 1);
4474 IEM_MC_LOCAL(uint16_t, u16Dst);
4475 IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Dst, u16Dst, 0);
4476 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4477 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
4478 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4479 IEM_MC_PREPARE_AVX_USAGE();
4480 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4481 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpextrw_u128, iemAImpl_vpextrw_u128_fallback),
4482 pu16Dst, puSrc, bImmArg);
4483 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst);
4484 IEM_MC_ADVANCE_RIP_AND_FINISH();
4485 IEM_MC_END();
4486 }
4487 /* No memory operand. */
4488 else
4489 return IEMOP_RAISE_INVALID_OPCODE();
4490}
4491
4492
4493/* Opcode VEX.F3.0F 0xc5 - invalid */
4494/* Opcode VEX.F2.0F 0xc5 - invalid */
4495
4496
4497#define VSHUFP_X(a_Instr) \
4498 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
4499 if (IEM_IS_MODRM_REG_MODE(bRm)) \
4500 { \
4501 /* \
4502 * Register, register. \
4503 */ \
4504 if (pVCpu->iem.s.uVexLength) \
4505 { \
4506 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4507 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4508 IEM_MC_BEGIN(4, 3); \
4509 IEM_MC_LOCAL(RTUINT256U, uDst); \
4510 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4511 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4512 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4513 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4514 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4515 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4516 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4517 IEM_MC_PREPARE_AVX_USAGE(); \
4518 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4519 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4520 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4521 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4522 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4523 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4524 IEM_MC_END(); \
4525 } \
4526 else \
4527 { \
4528 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4529 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4530 IEM_MC_BEGIN(4, 0); \
4531 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4532 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4533 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2); \
4534 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4535 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4536 IEM_MC_PREPARE_AVX_USAGE(); \
4537 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4538 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4539 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4540 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4541 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4542 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4543 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4544 IEM_MC_END(); \
4545 } \
4546 } \
4547 else \
4548 { \
4549 /* \
4550 * Register, memory. \
4551 */ \
4552 if (pVCpu->iem.s.uVexLength) \
4553 { \
4554 IEM_MC_BEGIN(4, 4); \
4555 IEM_MC_LOCAL(RTUINT256U, uDst); \
4556 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4557 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4558 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4559 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4560 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4561 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4562 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
4563 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4564 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4565 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4566 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4567 IEM_MC_PREPARE_AVX_USAGE(); \
4568 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4569 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4570 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4571 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4572 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4573 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4574 IEM_MC_END(); \
4575 } \
4576 else \
4577 { \
4578 IEM_MC_BEGIN(4, 2); \
4579 IEM_MC_LOCAL(RTUINT128U, uSrc2); \
4580 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4581 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4582 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4583 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); \
4584 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
4585 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4586 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4587 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4588 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4589 IEM_MC_PREPARE_AVX_USAGE(); \
4590 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4591 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4592 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4593 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4594 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4595 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4596 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4597 IEM_MC_END(); \
4598 } \
4599 } \
4600 (void)0
4601
4602/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
4603FNIEMOP_DEF(iemOp_vshufps_Vps_Hps_Wps_Ib)
4604{
4605 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPS, vshufps, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4606 VSHUFP_X(vshufps);
4607}
4608
4609
4610/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
4611FNIEMOP_DEF(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib)
4612{
4613 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPD, vshufpd, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4614 VSHUFP_X(vshufpd);
4615}
4616#undef VSHUFP_X
4617
4618
4619/* Opcode VEX.F3.0F 0xc6 - invalid */
4620/* Opcode VEX.F2.0F 0xc6 - invalid */
4621
4622/* Opcode VEX.0F 0xc7 - invalid */
4623/* Opcode VEX.66.0F 0xc7 - invalid */
4624/* Opcode VEX.F3.0F 0xc7 - invalid */
4625/* Opcode VEX.F2.0F 0xc7 - invalid */
4626
4627/* Opcode VEX.0F 0xc8 - invalid */
4628/* Opcode VEX.0F 0xc9 - invalid */
4629/* Opcode VEX.0F 0xca - invalid */
4630/* Opcode VEX.0F 0xcb - invalid */
4631/* Opcode VEX.0F 0xcc - invalid */
4632/* Opcode VEX.0F 0xcd - invalid */
4633/* Opcode VEX.0F 0xce - invalid */
4634/* Opcode VEX.0F 0xcf - invalid */
4635
4636
4637/* Opcode VEX.0F 0xd0 - invalid */
4638/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
4639FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
4640/* Opcode VEX.F3.0F 0xd0 - invalid */
4641/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
4642FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
4643
4644/* Opcode VEX.0F 0xd1 - invalid */
4645/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
4646FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
4647/* Opcode VEX.F3.0F 0xd1 - invalid */
4648/* Opcode VEX.F2.0F 0xd1 - invalid */
4649
4650/* Opcode VEX.0F 0xd2 - invalid */
4651/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
4652FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
4653/* Opcode VEX.F3.0F 0xd2 - invalid */
4654/* Opcode VEX.F2.0F 0xd2 - invalid */
4655
4656/* Opcode VEX.0F 0xd3 - invalid */
4657/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
4658FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
4659/* Opcode VEX.F3.0F 0xd3 - invalid */
4660/* Opcode VEX.F2.0F 0xd3 - invalid */
4661
4662/* Opcode VEX.0F 0xd4 - invalid */
4663
4664
4665/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
4666FNIEMOP_DEF(iemOp_vpaddq_Vx_Hx_Wx)
4667{
4668 IEMOP_MNEMONIC3(VEX_RVM, VPADDQ, vpaddq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4669 IEMOPMEDIAF3_INIT_VARS( vpaddq);
4670 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4671}
4672
4673
4674/* Opcode VEX.F3.0F 0xd4 - invalid */
4675/* Opcode VEX.F2.0F 0xd4 - invalid */
4676
4677/* Opcode VEX.0F 0xd5 - invalid */
4678
4679
4680/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
4681FNIEMOP_DEF(iemOp_vpmullw_Vx_Hx_Wx)
4682{
4683 IEMOP_MNEMONIC3(VEX_RVM, VPMULLW, vpmullw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4684 IEMOPMEDIAOPTF3_INIT_VARS(vpmullw);
4685 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4686}
4687
4688
4689/* Opcode VEX.F3.0F 0xd5 - invalid */
4690/* Opcode VEX.F2.0F 0xd5 - invalid */
4691
4692/* Opcode VEX.0F 0xd6 - invalid */
4693
4694/**
4695 * @opcode 0xd6
4696 * @oppfx 0x66
4697 * @opcpuid avx
4698 * @opgroup og_avx_pcksclr_datamove
4699 * @opxcpttype none
4700 * @optest op1=-1 op2=2 -> op1=2
4701 * @optest op1=0 op2=-42 -> op1=-42
4702 */
4703FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
4704{
4705 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4706 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4707 if (IEM_IS_MODRM_REG_MODE(bRm))
4708 {
4709 /*
4710 * Register, register.
4711 */
4712 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
4713 IEM_MC_BEGIN(0, 0);
4714
4715 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4716 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4717
4718 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4719 IEM_GET_MODRM_REG(pVCpu, bRm));
4720 IEM_MC_ADVANCE_RIP_AND_FINISH();
4721 IEM_MC_END();
4722 }
4723 else
4724 {
4725 /*
4726 * Memory, register.
4727 */
4728 IEM_MC_BEGIN(0, 2);
4729 IEM_MC_LOCAL(uint64_t, uSrc);
4730 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4731
4732 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4733 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
4734 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4735 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4736
4737 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4738 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4739
4740 IEM_MC_ADVANCE_RIP_AND_FINISH();
4741 IEM_MC_END();
4742 }
4743}
4744
4745/* Opcode VEX.F3.0F 0xd6 - invalid */
4746/* Opcode VEX.F2.0F 0xd6 - invalid */
4747
4748
4749/* Opcode VEX.0F 0xd7 - invalid */
4750
4751/** Opcode VEX.66.0F 0xd7 - */
4752FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
4753{
4754 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4755 /* Docs says register only. */
4756 if (IEM_IS_MODRM_REG_MODE(bRm)) /** @todo test that this is registers only. */
4757 {
4758 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
4759 IEMOP_MNEMONIC2(RM_REG, VPMOVMSKB, vpmovmskb, Gd, Ux, DISOPTYPE_SSE | DISOPTYPE_HARMLESS, 0);
4760 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4761 if (pVCpu->iem.s.uVexLength)
4762 {
4763 IEM_MC_BEGIN(2, 1);
4764 IEM_MC_ARG(uint64_t *, puDst, 0);
4765 IEM_MC_LOCAL(RTUINT256U, uSrc);
4766 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
4767 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
4768 IEM_MC_PREPARE_AVX_USAGE();
4769 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4770 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4771 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpmovmskb_u256,
4772 iemAImpl_vpmovmskb_u256_fallback), puDst, puSrc);
4773 IEM_MC_ADVANCE_RIP_AND_FINISH();
4774 IEM_MC_END();
4775 }
4776 else
4777 {
4778 IEM_MC_BEGIN(2, 0);
4779 IEM_MC_ARG(uint64_t *, puDst, 0);
4780 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4781 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
4782 IEM_MC_PREPARE_AVX_USAGE();
4783 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4784 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4785 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc);
4786 IEM_MC_ADVANCE_RIP_AND_FINISH();
4787 IEM_MC_END();
4788 }
4789 }
4790 else
4791 return IEMOP_RAISE_INVALID_OPCODE();
4792}
4793
4794
4795/* Opcode VEX.F3.0F 0xd7 - invalid */
4796/* Opcode VEX.F2.0F 0xd7 - invalid */
4797
4798
4799/* Opcode VEX.0F 0xd8 - invalid */
4800/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, W */
4801FNIEMOP_STUB(iemOp_vpsubusb_Vx_Hx_W);
4802/* Opcode VEX.F3.0F 0xd8 - invalid */
4803/* Opcode VEX.F2.0F 0xd8 - invalid */
4804
4805/* Opcode VEX.0F 0xd9 - invalid */
4806/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
4807FNIEMOP_STUB(iemOp_vpsubusw_Vx_Hx_Wx);
4808/* Opcode VEX.F3.0F 0xd9 - invalid */
4809/* Opcode VEX.F2.0F 0xd9 - invalid */
4810
4811/* Opcode VEX.0F 0xda - invalid */
4812
4813
4814/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
4815FNIEMOP_DEF(iemOp_vpminub_Vx_Hx_Wx)
4816{
4817 IEMOP_MNEMONIC3(VEX_RVM, VPMINUB, vpminub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4818 IEMOPMEDIAF3_INIT_VARS(vpminub);
4819 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4820}
4821
4822
4823/* Opcode VEX.F3.0F 0xda - invalid */
4824/* Opcode VEX.F2.0F 0xda - invalid */
4825
4826/* Opcode VEX.0F 0xdb - invalid */
4827
4828
4829/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, Wx */
4830FNIEMOP_DEF(iemOp_vpand_Vx_Hx_Wx)
4831{
4832 IEMOP_MNEMONIC3(VEX_RVM, VPAND, vpand, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4833 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4834 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
4835}
4836
4837
4838/* Opcode VEX.F3.0F 0xdb - invalid */
4839/* Opcode VEX.F2.0F 0xdb - invalid */
4840
4841/* Opcode VEX.0F 0xdc - invalid */
4842/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
4843FNIEMOP_STUB(iemOp_vpaddusb_Vx_Hx_Wx);
4844/* Opcode VEX.F3.0F 0xdc - invalid */
4845/* Opcode VEX.F2.0F 0xdc - invalid */
4846
4847/* Opcode VEX.0F 0xdd - invalid */
4848/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
4849FNIEMOP_STUB(iemOp_vpaddusw_Vx_Hx_Wx);
4850/* Opcode VEX.F3.0F 0xdd - invalid */
4851/* Opcode VEX.F2.0F 0xdd - invalid */
4852
4853/* Opcode VEX.0F 0xde - invalid */
4854
4855
4856/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, Wx */
4857FNIEMOP_DEF(iemOp_vpmaxub_Vx_Hx_Wx)
4858{
4859 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUB, vpmaxub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4860 IEMOPMEDIAF3_INIT_VARS(vpmaxub);
4861 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4862}
4863
4864
4865/* Opcode VEX.F3.0F 0xde - invalid */
4866/* Opcode VEX.F2.0F 0xde - invalid */
4867
4868/* Opcode VEX.0F 0xdf - invalid */
4869
4870
4871/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
4872FNIEMOP_DEF(iemOp_vpandn_Vx_Hx_Wx)
4873{
4874 IEMOP_MNEMONIC3(VEX_RVM, VPANDN, vpandn, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4875 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4876 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
4877}
4878
4879
4880/* Opcode VEX.F3.0F 0xdf - invalid */
4881/* Opcode VEX.F2.0F 0xdf - invalid */
4882
4883/* Opcode VEX.0F 0xe0 - invalid */
4884
4885
4886/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
4887FNIEMOP_DEF(iemOp_vpavgb_Vx_Hx_Wx)
4888{
4889 IEMOP_MNEMONIC3(VEX_RVM, VPAVGB, vpavgb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4890 IEMOPMEDIAOPTF3_INIT_VARS(vpavgb);
4891 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4892}
4893
4894
4895/* Opcode VEX.F3.0F 0xe0 - invalid */
4896/* Opcode VEX.F2.0F 0xe0 - invalid */
4897
4898/* Opcode VEX.0F 0xe1 - invalid */
4899/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
4900FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W);
4901/* Opcode VEX.F3.0F 0xe1 - invalid */
4902/* Opcode VEX.F2.0F 0xe1 - invalid */
4903
4904/* Opcode VEX.0F 0xe2 - invalid */
4905/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
4906FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx);
4907/* Opcode VEX.F3.0F 0xe2 - invalid */
4908/* Opcode VEX.F2.0F 0xe2 - invalid */
4909
4910/* Opcode VEX.0F 0xe3 - invalid */
4911
4912
4913/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
4914FNIEMOP_DEF(iemOp_vpavgw_Vx_Hx_Wx)
4915{
4916 IEMOP_MNEMONIC3(VEX_RVM, VPAVGW, vpavgw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4917 IEMOPMEDIAOPTF3_INIT_VARS(vpavgw);
4918 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4919}
4920
4921
4922/* Opcode VEX.F3.0F 0xe3 - invalid */
4923/* Opcode VEX.F2.0F 0xe3 - invalid */
4924
4925/* Opcode VEX.0F 0xe4 - invalid */
4926
4927
4928/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, Wx */
4929FNIEMOP_DEF(iemOp_vpmulhuw_Vx_Hx_Wx)
4930{
4931 IEMOP_MNEMONIC3(VEX_RVM, VPMULHUW, vpmulhuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4932 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhuw);
4933 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4934}
4935
4936
4937/* Opcode VEX.F3.0F 0xe4 - invalid */
4938/* Opcode VEX.F2.0F 0xe4 - invalid */
4939
4940/* Opcode VEX.0F 0xe5 - invalid */
4941
4942
4943/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
4944FNIEMOP_DEF(iemOp_vpmulhw_Vx_Hx_Wx)
4945{
4946 IEMOP_MNEMONIC3(VEX_RVM, VPMULHW, vpmulhw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4947 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhw);
4948 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4949}
4950
4951
4952/* Opcode VEX.F3.0F 0xe5 - invalid */
4953/* Opcode VEX.F2.0F 0xe5 - invalid */
4954
4955/* Opcode VEX.0F 0xe6 - invalid */
4956/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
4957FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
4958/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
4959FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
4960/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
4961FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
4962
4963
4964/* Opcode VEX.0F 0xe7 - invalid */
4965
4966/**
4967 * @opcode 0xe7
4968 * @opcodesub !11 mr/reg
4969 * @oppfx 0x66
4970 * @opcpuid avx
4971 * @opgroup og_avx_cachect
4972 * @opxcpttype 1
4973 * @optest op1=-1 op2=2 -> op1=2
4974 * @optest op1=0 op2=-42 -> op1=-42
4975 */
4976FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
4977{
4978 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4979 Assert(pVCpu->iem.s.uVexLength <= 1);
4980 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4981 if (IEM_IS_MODRM_MEM_MODE(bRm))
4982 {
4983 if (pVCpu->iem.s.uVexLength == 0)
4984 {
4985 /*
4986 * 128-bit: Memory, register.
4987 */
4988 IEM_MC_BEGIN(0, 2);
4989 IEM_MC_LOCAL(RTUINT128U, uSrc);
4990 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4991
4992 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4993 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4994 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4995 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4996
4997 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4998 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4999
5000 IEM_MC_ADVANCE_RIP_AND_FINISH();
5001 IEM_MC_END();
5002 }
5003 else
5004 {
5005 /*
5006 * 256-bit: Memory, register.
5007 */
5008 IEM_MC_BEGIN(0, 2);
5009 IEM_MC_LOCAL(RTUINT256U, uSrc);
5010 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5011
5012 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5013 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
5014 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5015 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5016
5017 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5018 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5019
5020 IEM_MC_ADVANCE_RIP_AND_FINISH();
5021 IEM_MC_END();
5022 }
5023 }
5024 /**
5025 * @opdone
5026 * @opmnemonic udvex660fe7reg
5027 * @opcode 0xe7
5028 * @opcodesub 11 mr/reg
5029 * @oppfx 0x66
5030 * @opunused immediate
5031 * @opcpuid avx
5032 * @optest ->
5033 */
5034 else
5035 return IEMOP_RAISE_INVALID_OPCODE();
5036}
5037
5038/* Opcode VEX.F3.0F 0xe7 - invalid */
5039/* Opcode VEX.F2.0F 0xe7 - invalid */
5040
5041
5042/* Opcode VEX.0F 0xe8 - invalid */
5043/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, W */
5044FNIEMOP_STUB(iemOp_vpsubsb_Vx_Hx_W);
5045/* Opcode VEX.F3.0F 0xe8 - invalid */
5046/* Opcode VEX.F2.0F 0xe8 - invalid */
5047
5048/* Opcode VEX.0F 0xe9 - invalid */
5049/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
5050FNIEMOP_STUB(iemOp_vpsubsw_Vx_Hx_Wx);
5051/* Opcode VEX.F3.0F 0xe9 - invalid */
5052/* Opcode VEX.F2.0F 0xe9 - invalid */
5053
5054/* Opcode VEX.0F 0xea - invalid */
5055
5056
5057/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
5058FNIEMOP_DEF(iemOp_vpminsw_Vx_Hx_Wx)
5059{
5060 IEMOP_MNEMONIC3(VEX_RVM, VPMINSW, vpminsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5061 IEMOPMEDIAF3_INIT_VARS(vpminsw);
5062 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5063}
5064
5065
5066/* Opcode VEX.F3.0F 0xea - invalid */
5067/* Opcode VEX.F2.0F 0xea - invalid */
5068
5069/* Opcode VEX.0F 0xeb - invalid */
5070
5071
5072/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, Wx */
5073FNIEMOP_DEF(iemOp_vpor_Vx_Hx_Wx)
5074{
5075 IEMOP_MNEMONIC3(VEX_RVM, VPOR, vpor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5076 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
5077 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
5078}
5079
5080
5081
5082/* Opcode VEX.F3.0F 0xeb - invalid */
5083/* Opcode VEX.F2.0F 0xeb - invalid */
5084
5085/* Opcode VEX.0F 0xec - invalid */
5086/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
5087FNIEMOP_STUB(iemOp_vpaddsb_Vx_Hx_Wx);
5088/* Opcode VEX.F3.0F 0xec - invalid */
5089/* Opcode VEX.F2.0F 0xec - invalid */
5090
5091/* Opcode VEX.0F 0xed - invalid */
5092/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
5093FNIEMOP_STUB(iemOp_vpaddsw_Vx_Hx_Wx);
5094/* Opcode VEX.F3.0F 0xed - invalid */
5095/* Opcode VEX.F2.0F 0xed - invalid */
5096
5097/* Opcode VEX.0F 0xee - invalid */
5098
5099
5100/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, Wx */
5101FNIEMOP_DEF(iemOp_vpmaxsw_Vx_Hx_Wx)
5102{
5103 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSW, vpmaxsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5104 IEMOPMEDIAF3_INIT_VARS(vpmaxsw);
5105 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5106}
5107
5108
5109/* Opcode VEX.F3.0F 0xee - invalid */
5110/* Opcode VEX.F2.0F 0xee - invalid */
5111
5112
5113/* Opcode VEX.0F 0xef - invalid */
5114
5115
5116/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
5117FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
5118{
5119 IEMOP_MNEMONIC3(VEX_RVM, VPXOR, vpxor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5120 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
5121 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
5122}
5123
5124
5125/* Opcode VEX.F3.0F 0xef - invalid */
5126/* Opcode VEX.F2.0F 0xef - invalid */
5127
5128/* Opcode VEX.0F 0xf0 - invalid */
5129/* Opcode VEX.66.0F 0xf0 - invalid */
5130
5131
5132/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
5133FNIEMOP_DEF(iemOp_vlddqu_Vx_Mx)
5134{
5135 IEMOP_MNEMONIC2(VEX_RM_MEM, VLDDQU, vlddqu, Vx_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5136 Assert(pVCpu->iem.s.uVexLength <= 1);
5137 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5138 if (IEM_IS_MODRM_REG_MODE(bRm))
5139 {
5140 /*
5141 * Register, register - (not implemented, assuming it raises \#UD).
5142 */
5143 return IEMOP_RAISE_INVALID_OPCODE();
5144 }
5145 else if (pVCpu->iem.s.uVexLength == 0)
5146 {
5147 /*
5148 * Register, memory128.
5149 */
5150 IEM_MC_BEGIN(0, 2);
5151 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
5152 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5153
5154 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5155 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
5156 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5157 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5158
5159 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5160 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
5161
5162 IEM_MC_ADVANCE_RIP_AND_FINISH();
5163 IEM_MC_END();
5164 }
5165 else
5166 {
5167 /*
5168 * Register, memory256.
5169 */
5170 IEM_MC_BEGIN(0, 2);
5171 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
5172 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5173
5174 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5175 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
5176 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5177 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5178
5179 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5180 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
5181
5182 IEM_MC_ADVANCE_RIP_AND_FINISH();
5183 IEM_MC_END();
5184 }
5185}
5186
5187
5188/* Opcode VEX.0F 0xf1 - invalid */
5189/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
5190FNIEMOP_STUB(iemOp_vpsllw_Vx_Hx_W);
5191/* Opcode VEX.F2.0F 0xf1 - invalid */
5192
5193/* Opcode VEX.0F 0xf2 - invalid */
5194/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
5195FNIEMOP_STUB(iemOp_vpslld_Vx_Hx_Wx);
5196/* Opcode VEX.F2.0F 0xf2 - invalid */
5197
5198/* Opcode VEX.0F 0xf3 - invalid */
5199/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
5200FNIEMOP_STUB(iemOp_vpsllq_Vx_Hx_Wx);
5201/* Opcode VEX.F2.0F 0xf3 - invalid */
5202
5203/* Opcode VEX.0F 0xf4 - invalid */
5204
5205
5206/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
5207FNIEMOP_DEF(iemOp_vpmuludq_Vx_Hx_W)
5208{
5209 IEMOP_MNEMONIC3(VEX_RVM, VPMULUDQ, vpmuludq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5210 IEMOPMEDIAOPTF3_INIT_VARS(vpmuludq);
5211 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5212}
5213
5214
5215/* Opcode VEX.F2.0F 0xf4 - invalid */
5216
5217/* Opcode VEX.0F 0xf5 - invalid */
5218/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
5219FNIEMOP_STUB(iemOp_vpmaddwd_Vx_Hx_Wx);
5220/* Opcode VEX.F2.0F 0xf5 - invalid */
5221
5222/* Opcode VEX.0F 0xf6 - invalid */
5223
5224
5225/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
5226FNIEMOP_DEF(iemOp_vpsadbw_Vx_Hx_Wx)
5227{
5228 IEMOP_MNEMONIC3(VEX_RVM, VPSADBW, vpsadbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5229 IEMOPMEDIAOPTF3_INIT_VARS(vpsadbw);
5230 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5231}
5232
5233
5234/* Opcode VEX.F2.0F 0xf6 - invalid */
5235
5236/* Opcode VEX.0F 0xf7 - invalid */
5237/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
5238FNIEMOP_STUB(iemOp_vmaskmovdqu_Vdq_Udq);
5239/* Opcode VEX.F2.0F 0xf7 - invalid */
5240
5241/* Opcode VEX.0F 0xf8 - invalid */
5242
5243
5244/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
5245FNIEMOP_DEF(iemOp_vpsubb_Vx_Hx_Wx)
5246{
5247 IEMOP_MNEMONIC3(VEX_RVM, VPSUBB, vpsubb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5248 IEMOPMEDIAF3_INIT_VARS( vpsubb);
5249 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5250}
5251
5252
5253/* Opcode VEX.F2.0F 0xf8 - invalid */
5254
5255/* Opcode VEX.0F 0xf9 - invalid */
5256
5257
5258/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
5259FNIEMOP_DEF(iemOp_vpsubw_Vx_Hx_Wx)
5260{
5261 IEMOP_MNEMONIC3(VEX_RVM, VPSUBW, vpsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5262 IEMOPMEDIAF3_INIT_VARS( vpsubw);
5263 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5264}
5265
5266
5267/* Opcode VEX.F2.0F 0xf9 - invalid */
5268
5269/* Opcode VEX.0F 0xfa - invalid */
5270
5271
5272/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
5273FNIEMOP_DEF(iemOp_vpsubd_Vx_Hx_Wx)
5274{
5275 IEMOP_MNEMONIC3(VEX_RVM, VPSUBD, vpsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5276 IEMOPMEDIAF3_INIT_VARS( vpsubd);
5277 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5278}
5279
5280
5281/* Opcode VEX.F2.0F 0xfa - invalid */
5282
5283/* Opcode VEX.0F 0xfb - invalid */
5284
5285
5286/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
5287FNIEMOP_DEF(iemOp_vpsubq_Vx_Hx_Wx)
5288{
5289 IEMOP_MNEMONIC3(VEX_RVM, VPSUBQ, vpsubq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5290 IEMOPMEDIAF3_INIT_VARS( vpsubq);
5291 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5292}
5293
5294
5295/* Opcode VEX.F2.0F 0xfb - invalid */
5296
5297/* Opcode VEX.0F 0xfc - invalid */
5298
5299
5300/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
5301FNIEMOP_DEF(iemOp_vpaddb_Vx_Hx_Wx)
5302{
5303 IEMOP_MNEMONIC3(VEX_RVM, VPADDB, vpaddb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5304 IEMOPMEDIAF3_INIT_VARS( vpaddb);
5305 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5306}
5307
5308
5309/* Opcode VEX.F2.0F 0xfc - invalid */
5310
5311/* Opcode VEX.0F 0xfd - invalid */
5312
5313
5314/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
5315FNIEMOP_DEF(iemOp_vpaddw_Vx_Hx_Wx)
5316{
5317 IEMOP_MNEMONIC3(VEX_RVM, VPADDW, vpaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5318 IEMOPMEDIAF3_INIT_VARS( vpaddw);
5319 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5320}
5321
5322
5323/* Opcode VEX.F2.0F 0xfd - invalid */
5324
5325/* Opcode VEX.0F 0xfe - invalid */
5326
5327
5328/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
5329FNIEMOP_DEF(iemOp_vpaddd_Vx_Hx_Wx)
5330{
5331 IEMOP_MNEMONIC3(VEX_RVM, VPADDD, vpaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5332 IEMOPMEDIAF3_INIT_VARS( vpaddd);
5333 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5334}
5335
5336
5337/* Opcode VEX.F2.0F 0xfe - invalid */
5338
5339
5340/** Opcode **** 0x0f 0xff - UD0 */
5341FNIEMOP_DEF(iemOp_vud0)
5342{
5343 IEMOP_MNEMONIC(vud0, "vud0");
5344 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5345 {
5346 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
5347#ifndef TST_IEM_CHECK_MC
5348 RTGCPTR GCPtrEff;
5349 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
5350 if (rcStrict != VINF_SUCCESS)
5351 return rcStrict;
5352#endif
5353 IEMOP_HLP_DONE_DECODING();
5354 }
5355 return IEMOP_RAISE_INVALID_OPCODE();
5356}
5357
5358
5359
5360/**
5361 * VEX opcode map \#1.
5362 *
5363 * @sa g_apfnTwoByteMap
5364 */
5365IEM_STATIC const PFNIEMOP g_apfnVexMap1[] =
5366{
5367 /* no prefix, 066h prefix f3h prefix, f2h prefix */
5368 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
5369 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
5370 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
5371 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
5372 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
5373 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
5374 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
5375 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
5376 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
5377 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
5378 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
5379 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
5380 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
5381 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
5382 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
5383 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
5384
5385 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
5386 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
5387 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
5388 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5389 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5390 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5391 /* 0x16 */ iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpd_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
5392 /* 0x17 */ iemOp_vmovhps_Mq_Vq, iemOp_vmovhpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5393 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
5394 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
5395 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
5396 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
5397 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
5398 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
5399 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
5400 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
5401
5402 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
5403 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
5404 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
5405 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
5406 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
5407 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
5408 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
5409 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
5410 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5411 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5412 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
5413 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5414 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
5415 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
5416 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5417 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5418
5419 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
5420 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
5421 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
5422 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
5423 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
5424 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
5425 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
5426 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
5427 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5428 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5429 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5430 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5431 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5432 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5433 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5434 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5435
5436 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
5437 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
5438 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
5439 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
5440 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
5441 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
5442 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
5443 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
5444 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
5445 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
5446 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
5447 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
5448 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
5449 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
5450 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
5451 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
5452
5453 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5454 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
5455 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
5456 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
5457 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5458 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5459 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5460 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5461 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
5462 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
5463 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
5464 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
5465 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
5466 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
5467 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
5468 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
5469
5470 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5471 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5472 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5473 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5474 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5475 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5476 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5477 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5478 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5479 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5480 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5481 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5482 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5483 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5484 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5485 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
5486
5487 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
5488 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5489 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5490 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5491 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5492 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5493 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5494 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5495 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
5496 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
5497 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
5498 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
5499 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
5500 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
5501 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
5502 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
5503
5504 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
5505 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
5506 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
5507 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
5508 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
5509 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
5510 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
5511 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
5512 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
5513 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
5514 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
5515 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
5516 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
5517 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
5518 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
5519 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
5520
5521 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
5522 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
5523 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
5524 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
5525 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
5526 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
5527 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
5528 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
5529 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
5530 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
5531 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
5532 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
5533 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
5534 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
5535 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
5536 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
5537
5538 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5539 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5540 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5541 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5542 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
5543 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
5544 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
5545 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5546 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5547 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5548 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
5549 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
5550 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
5551 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
5552 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
5553 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
5554
5555 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5556 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5557 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5558 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5559 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
5560 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
5561 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
5562 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5563 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5564 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5565 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
5566 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
5567 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
5568 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
5569 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
5570 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
5571
5572 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5573 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5574 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
5575 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5576 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
5577 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
5578 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
5579 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5580 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5581 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5582 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
5583 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
5584 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
5585 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
5586 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
5587 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
5588
5589 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
5590 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5591 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5592 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5593 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5594 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5595 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5596 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5597 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5598 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5599 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5600 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5601 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5602 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5603 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5604 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5605
5606 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5607 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5608 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5609 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5610 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5611 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5612 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
5613 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5614 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5615 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5616 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5617 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5618 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5619 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5620 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5621 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5622
5623 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
5624 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5625 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5626 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5627 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5628 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5629 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5630 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5631 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5632 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5633 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5634 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5635 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5636 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5637 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5638 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
5639};
5640AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
5641/** @} */
5642
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