VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h@ 96622

Last change on this file since 96622 was 96435, checked in by vboxsync, 2 years ago

VMM/IEM: Implement [v]lddqu instructions, bugref:9898
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1/* $Id: IEMAllInstructionsVexMap1.cpp.h 96435 2022-08-23 10:40:19Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 1
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128
39 * - vpxxx ymm0, ymm1, ymm2/mem256
40 *
41 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
42 */
43FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, PCIEMOPMEDIAF3, pImpl)
44{
45 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
46 if (IEM_IS_MODRM_REG_MODE(bRm))
47 {
48 /*
49 * Register, register.
50 */
51 if (pVCpu->iem.s.uVexLength)
52 {
53 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
54 IEM_MC_BEGIN(4, 3);
55 IEM_MC_LOCAL(RTUINT256U, uDst);
56 IEM_MC_LOCAL(RTUINT256U, uSrc1);
57 IEM_MC_LOCAL(RTUINT256U, uSrc2);
58 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
59 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 1);
60 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 2);
61 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 3);
62 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
63 IEM_MC_PREPARE_AVX_USAGE();
64 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
65 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
66 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
67 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
68 IEM_MC_ADVANCE_RIP();
69 IEM_MC_END();
70 }
71 else
72 {
73 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
74 IEM_MC_BEGIN(4, 0);
75 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
76 IEM_MC_ARG(PRTUINT128U, puDst, 1);
77 IEM_MC_ARG(PCRTUINT128U, puSrc1, 2);
78 IEM_MC_ARG(PCRTUINT128U, puSrc2, 3);
79 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
80 IEM_MC_PREPARE_AVX_USAGE();
81 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
82 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
83 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
84 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
85 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
86 IEM_MC_ADVANCE_RIP();
87 IEM_MC_END();
88 }
89 }
90 else
91 {
92 /*
93 * Register, memory.
94 */
95 if (pVCpu->iem.s.uVexLength)
96 {
97 IEM_MC_BEGIN(4, 4);
98 IEM_MC_LOCAL(RTUINT256U, uDst);
99 IEM_MC_LOCAL(RTUINT256U, uSrc1);
100 IEM_MC_LOCAL(RTUINT256U, uSrc2);
101 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
102 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
103 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 1);
104 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 2);
105 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 3);
106
107 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
108 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
109 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
110 IEM_MC_PREPARE_AVX_USAGE();
111
112 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
113 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
114 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
115 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
116
117 IEM_MC_ADVANCE_RIP();
118 IEM_MC_END();
119 }
120 else
121 {
122 IEM_MC_BEGIN(4, 2);
123 IEM_MC_LOCAL(RTUINT128U, uSrc2);
124 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
126 IEM_MC_ARG(PRTUINT128U, puDst, 1);
127 IEM_MC_ARG(PCRTUINT128U, puSrc1, 2);
128 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 3);
129
130 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
131 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
132 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
133 IEM_MC_PREPARE_AVX_USAGE();
134
135 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
136 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
137 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
138 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
139 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
140
141 IEM_MC_ADVANCE_RIP();
142 IEM_MC_END();
143 }
144 }
145 return VINF_SUCCESS;
146}
147
148
149/**
150 * Common worker for AVX2 instructions on the forms:
151 * - vpxxx xmm0, xmm1, xmm2/mem128
152 * - vpxxx ymm0, ymm1, ymm2/mem256
153 *
154 * Takes function table for function w/o implicit state parameter.
155 *
156 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
157 */
158FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, PCIEMOPMEDIAOPTF3, pImpl)
159{
160 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
161 if (IEM_IS_MODRM_REG_MODE(bRm))
162 {
163 /*
164 * Register, register.
165 */
166 if (pVCpu->iem.s.uVexLength)
167 {
168 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
169 IEM_MC_BEGIN(3, 3);
170 IEM_MC_LOCAL(RTUINT256U, uDst);
171 IEM_MC_LOCAL(RTUINT256U, uSrc1);
172 IEM_MC_LOCAL(RTUINT256U, uSrc2);
173 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
174 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
175 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
176 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
177 IEM_MC_PREPARE_AVX_USAGE();
178 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
179 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
180 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
181 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
182 IEM_MC_ADVANCE_RIP();
183 IEM_MC_END();
184 }
185 else
186 {
187 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
188 IEM_MC_BEGIN(3, 0);
189 IEM_MC_ARG(PRTUINT128U, puDst, 0);
190 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
191 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
192 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
193 IEM_MC_PREPARE_AVX_USAGE();
194 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
195 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
196 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
197 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
198 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
199 IEM_MC_ADVANCE_RIP();
200 IEM_MC_END();
201 }
202 }
203 else
204 {
205 /*
206 * Register, memory.
207 */
208 if (pVCpu->iem.s.uVexLength)
209 {
210 IEM_MC_BEGIN(3, 4);
211 IEM_MC_LOCAL(RTUINT256U, uDst);
212 IEM_MC_LOCAL(RTUINT256U, uSrc1);
213 IEM_MC_LOCAL(RTUINT256U, uSrc2);
214 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
215 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
216 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
217 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
218
219 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
220 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
221 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
222 IEM_MC_PREPARE_AVX_USAGE();
223
224 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
225 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
226 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
227 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
228
229 IEM_MC_ADVANCE_RIP();
230 IEM_MC_END();
231 }
232 else
233 {
234 IEM_MC_BEGIN(3, 2);
235 IEM_MC_LOCAL(RTUINT128U, uSrc2);
236 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
237 IEM_MC_ARG(PRTUINT128U, puDst, 0);
238 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
239 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
240
241 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
242 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
243 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
244 IEM_MC_PREPARE_AVX_USAGE();
245
246 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
247 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
248 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
249 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
250 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
251
252 IEM_MC_ADVANCE_RIP();
253 IEM_MC_END();
254 }
255 }
256 return VINF_SUCCESS;
257}
258
259
260/**
261 * Common worker for AVX2 instructions on the forms:
262 * - vpunpckhxx xmm0, xmm1, xmm2/mem128
263 * - vpunpckhxx ymm0, ymm1, ymm2/mem256
264 *
265 * The 128-bit memory version of this instruction may elect to skip fetching the
266 * lower 64 bits of the operand. We, however, do not.
267 *
268 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
269 */
270FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, PCIEMOPMEDIAOPTF3, pImpl)
271{
272 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
273}
274
275
276/**
277 * Common worker for AVX2 instructions on the forms:
278 * - vpunpcklxx xmm0, xmm1, xmm2/mem128
279 * - vpunpcklxx ymm0, ymm1, ymm2/mem256
280 *
281 * The 128-bit memory version of this instruction may elect to skip fetching the
282 * higher 64 bits of the operand. We, however, do not.
283 *
284 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
285 */
286FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, PCIEMOPMEDIAOPTF3, pImpl)
287{
288 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
289}
290
291
292/**
293 * Common worker for AVX2 instructions on the forms:
294 * - vpxxx xmm0, xmm1/mem128
295 * - vpxxx ymm0, ymm1/mem256
296 *
297 * Takes function table for function w/o implicit state parameter.
298 *
299 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
300 */
301FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, PCIEMOPMEDIAOPTF2, pImpl)
302{
303 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
304 if (IEM_IS_MODRM_REG_MODE(bRm))
305 {
306 /*
307 * Register, register.
308 */
309 if (pVCpu->iem.s.uVexLength)
310 {
311 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
312 IEM_MC_BEGIN(2, 2);
313 IEM_MC_LOCAL(RTUINT256U, uDst);
314 IEM_MC_LOCAL(RTUINT256U, uSrc);
315 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
316 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
317 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
318 IEM_MC_PREPARE_AVX_USAGE();
319 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
320 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
321 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
322 IEM_MC_ADVANCE_RIP();
323 IEM_MC_END();
324 }
325 else
326 {
327 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
328 IEM_MC_BEGIN(2, 0);
329 IEM_MC_ARG(PRTUINT128U, puDst, 0);
330 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
331 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
332 IEM_MC_PREPARE_AVX_USAGE();
333 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
334 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
335 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
336 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
337 IEM_MC_ADVANCE_RIP();
338 IEM_MC_END();
339 }
340 }
341 else
342 {
343 /*
344 * Register, memory.
345 */
346 if (pVCpu->iem.s.uVexLength)
347 {
348 IEM_MC_BEGIN(2, 3);
349 IEM_MC_LOCAL(RTUINT256U, uDst);
350 IEM_MC_LOCAL(RTUINT256U, uSrc);
351 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
352 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
353 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
354
355 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
356 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
357 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
358 IEM_MC_PREPARE_AVX_USAGE();
359
360 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
361 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
362 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
363
364 IEM_MC_ADVANCE_RIP();
365 IEM_MC_END();
366 }
367 else
368 {
369 IEM_MC_BEGIN(2, 2);
370 IEM_MC_LOCAL(RTUINT128U, uSrc);
371 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
372 IEM_MC_ARG(PRTUINT128U, puDst, 0);
373 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
374
375 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
376 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
377 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
378 IEM_MC_PREPARE_AVX_USAGE();
379
380 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
381 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
382 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
383 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
384
385 IEM_MC_ADVANCE_RIP();
386 IEM_MC_END();
387 }
388 }
389 return VINF_SUCCESS;
390}
391
392
393/* Opcode VEX.0F 0x00 - invalid */
394/* Opcode VEX.0F 0x01 - invalid */
395/* Opcode VEX.0F 0x02 - invalid */
396/* Opcode VEX.0F 0x03 - invalid */
397/* Opcode VEX.0F 0x04 - invalid */
398/* Opcode VEX.0F 0x05 - invalid */
399/* Opcode VEX.0F 0x06 - invalid */
400/* Opcode VEX.0F 0x07 - invalid */
401/* Opcode VEX.0F 0x08 - invalid */
402/* Opcode VEX.0F 0x09 - invalid */
403/* Opcode VEX.0F 0x0a - invalid */
404
405/** Opcode VEX.0F 0x0b. */
406FNIEMOP_DEF(iemOp_vud2)
407{
408 IEMOP_MNEMONIC(vud2, "vud2");
409 return IEMOP_RAISE_INVALID_OPCODE();
410}
411
412/* Opcode VEX.0F 0x0c - invalid */
413/* Opcode VEX.0F 0x0d - invalid */
414/* Opcode VEX.0F 0x0e - invalid */
415/* Opcode VEX.0F 0x0f - invalid */
416
417
418/**
419 * @opcode 0x10
420 * @oppfx none
421 * @opcpuid avx
422 * @opgroup og_avx_simdfp_datamove
423 * @opxcpttype 4UA
424 * @optest op1=1 op2=2 -> op1=2
425 * @optest op1=0 op2=-22 -> op1=-22
426 */
427FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
428{
429 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
430 Assert(pVCpu->iem.s.uVexLength <= 1);
431 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
432 if (IEM_IS_MODRM_REG_MODE(bRm))
433 {
434 /*
435 * Register, register.
436 */
437 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
438 IEM_MC_BEGIN(0, 0);
439 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
440 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
441 if (pVCpu->iem.s.uVexLength == 0)
442 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
443 IEM_GET_MODRM_RM(pVCpu, bRm));
444 else
445 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
446 IEM_GET_MODRM_RM(pVCpu, bRm));
447 IEM_MC_ADVANCE_RIP();
448 IEM_MC_END();
449 }
450 else if (pVCpu->iem.s.uVexLength == 0)
451 {
452 /*
453 * 128-bit: Register, Memory
454 */
455 IEM_MC_BEGIN(0, 2);
456 IEM_MC_LOCAL(RTUINT128U, uSrc);
457 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
458
459 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
460 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
461 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
462 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
463
464 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
465 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
466
467 IEM_MC_ADVANCE_RIP();
468 IEM_MC_END();
469 }
470 else
471 {
472 /*
473 * 256-bit: Register, Memory
474 */
475 IEM_MC_BEGIN(0, 2);
476 IEM_MC_LOCAL(RTUINT256U, uSrc);
477 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
478
479 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
480 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
481 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
482 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
483
484 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
485 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
486
487 IEM_MC_ADVANCE_RIP();
488 IEM_MC_END();
489 }
490 return VINF_SUCCESS;
491}
492
493
494/**
495 * @opcode 0x10
496 * @oppfx 0x66
497 * @opcpuid avx
498 * @opgroup og_avx_simdfp_datamove
499 * @opxcpttype 4UA
500 * @optest op1=1 op2=2 -> op1=2
501 * @optest op1=0 op2=-22 -> op1=-22
502 */
503FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
504{
505 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
506 Assert(pVCpu->iem.s.uVexLength <= 1);
507 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
508 if (IEM_IS_MODRM_REG_MODE(bRm))
509 {
510 /*
511 * Register, register.
512 */
513 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
514 IEM_MC_BEGIN(0, 0);
515 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
516 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
517 if (pVCpu->iem.s.uVexLength == 0)
518 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
519 IEM_GET_MODRM_RM(pVCpu, bRm));
520 else
521 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
522 IEM_GET_MODRM_RM(pVCpu, bRm));
523 IEM_MC_ADVANCE_RIP();
524 IEM_MC_END();
525 }
526 else if (pVCpu->iem.s.uVexLength == 0)
527 {
528 /*
529 * 128-bit: Memory, register.
530 */
531 IEM_MC_BEGIN(0, 2);
532 IEM_MC_LOCAL(RTUINT128U, uSrc);
533 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
534
535 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
536 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
537 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
538 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
539
540 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
541 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
542
543 IEM_MC_ADVANCE_RIP();
544 IEM_MC_END();
545 }
546 else
547 {
548 /*
549 * 256-bit: Memory, register.
550 */
551 IEM_MC_BEGIN(0, 2);
552 IEM_MC_LOCAL(RTUINT256U, uSrc);
553 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
554
555 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
556 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
557 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
558 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
559
560 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
561 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
562
563 IEM_MC_ADVANCE_RIP();
564 IEM_MC_END();
565 }
566 return VINF_SUCCESS;
567}
568
569
570FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
571{
572 Assert(pVCpu->iem.s.uVexLength <= 1);
573 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
574 if (IEM_IS_MODRM_REG_MODE(bRm))
575 {
576 /**
577 * @opcode 0x10
578 * @oppfx 0xf3
579 * @opcodesub 11 mr/reg
580 * @opcpuid avx
581 * @opgroup og_avx_simdfp_datamerge
582 * @opxcpttype 5
583 * @optest op1=1 op2=0 op3=2 -> op1=2
584 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
585 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
586 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
587 * @note HssHi refers to bits 127:32.
588 */
589 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
590 IEMOP_HLP_DONE_VEX_DECODING();
591 IEM_MC_BEGIN(0, 0);
592
593 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
594 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
595 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
596 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
597 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
598 IEM_MC_ADVANCE_RIP();
599 IEM_MC_END();
600 }
601 else
602 {
603 /**
604 * @opdone
605 * @opcode 0x10
606 * @oppfx 0xf3
607 * @opcodesub !11 mr/reg
608 * @opcpuid avx
609 * @opgroup og_avx_simdfp_datamove
610 * @opxcpttype 5
611 * @opfunction iemOp_vmovss_Vss_Hss_Wss
612 * @optest op1=1 op2=2 -> op1=2
613 * @optest op1=0 op2=-22 -> op1=-22
614 */
615 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
616 IEM_MC_BEGIN(0, 2);
617 IEM_MC_LOCAL(uint32_t, uSrc);
618 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
619
620 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
621 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
622 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
623 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
624
625 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
626 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
627
628 IEM_MC_ADVANCE_RIP();
629 IEM_MC_END();
630 }
631
632 return VINF_SUCCESS;
633}
634
635
636FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
637{
638 Assert(pVCpu->iem.s.uVexLength <= 1);
639 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
640 if (IEM_IS_MODRM_REG_MODE(bRm))
641 {
642 /**
643 * @opcode 0x10
644 * @oppfx 0xf2
645 * @opcodesub 11 mr/reg
646 * @opcpuid avx
647 * @opgroup og_avx_simdfp_datamerge
648 * @opxcpttype 5
649 * @optest op1=1 op2=0 op3=2 -> op1=2
650 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
651 * @optest op1=3 op2=-1 op3=0x77 ->
652 * op1=0xffffffffffffffff0000000000000077
653 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
654 */
655 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
656 IEMOP_HLP_DONE_VEX_DECODING();
657 IEM_MC_BEGIN(0, 0);
658
659 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
660 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
661 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
662 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
663 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
664 IEM_MC_ADVANCE_RIP();
665 IEM_MC_END();
666 }
667 else
668 {
669 /**
670 * @opdone
671 * @opcode 0x10
672 * @oppfx 0xf2
673 * @opcodesub !11 mr/reg
674 * @opcpuid avx
675 * @opgroup og_avx_simdfp_datamove
676 * @opxcpttype 5
677 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
678 * @optest op1=1 op2=2 -> op1=2
679 * @optest op1=0 op2=-22 -> op1=-22
680 */
681 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
682 IEM_MC_BEGIN(0, 2);
683 IEM_MC_LOCAL(uint64_t, uSrc);
684 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
685
686 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
687 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
688 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
689 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
690
691 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
692 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
693
694 IEM_MC_ADVANCE_RIP();
695 IEM_MC_END();
696 }
697
698 return VINF_SUCCESS;
699}
700
701
702/**
703 * @opcode 0x11
704 * @oppfx none
705 * @opcpuid avx
706 * @opgroup og_avx_simdfp_datamove
707 * @opxcpttype 4UA
708 * @optest op1=1 op2=2 -> op1=2
709 * @optest op1=0 op2=-22 -> op1=-22
710 */
711FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
712{
713 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
714 Assert(pVCpu->iem.s.uVexLength <= 1);
715 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
716 if (IEM_IS_MODRM_REG_MODE(bRm))
717 {
718 /*
719 * Register, register.
720 */
721 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
722 IEM_MC_BEGIN(0, 0);
723 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
724 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
725 if (pVCpu->iem.s.uVexLength == 0)
726 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
727 IEM_GET_MODRM_REG(pVCpu, bRm));
728 else
729 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
730 IEM_GET_MODRM_REG(pVCpu, bRm));
731 IEM_MC_ADVANCE_RIP();
732 IEM_MC_END();
733 }
734 else if (pVCpu->iem.s.uVexLength == 0)
735 {
736 /*
737 * 128-bit: Memory, register.
738 */
739 IEM_MC_BEGIN(0, 2);
740 IEM_MC_LOCAL(RTUINT128U, uSrc);
741 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
742
743 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
744 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
745 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
746 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
747
748 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
749 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
750
751 IEM_MC_ADVANCE_RIP();
752 IEM_MC_END();
753 }
754 else
755 {
756 /*
757 * 256-bit: Memory, register.
758 */
759 IEM_MC_BEGIN(0, 2);
760 IEM_MC_LOCAL(RTUINT256U, uSrc);
761 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
762
763 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
764 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
765 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
766 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
767
768 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
769 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
770
771 IEM_MC_ADVANCE_RIP();
772 IEM_MC_END();
773 }
774 return VINF_SUCCESS;
775}
776
777
778/**
779 * @opcode 0x11
780 * @oppfx 0x66
781 * @opcpuid avx
782 * @opgroup og_avx_simdfp_datamove
783 * @opxcpttype 4UA
784 * @optest op1=1 op2=2 -> op1=2
785 * @optest op1=0 op2=-22 -> op1=-22
786 */
787FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
788{
789 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
790 Assert(pVCpu->iem.s.uVexLength <= 1);
791 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
792 if (IEM_IS_MODRM_REG_MODE(bRm))
793 {
794 /*
795 * Register, register.
796 */
797 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
798 IEM_MC_BEGIN(0, 0);
799 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
800 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
801 if (pVCpu->iem.s.uVexLength == 0)
802 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
803 IEM_GET_MODRM_REG(pVCpu, bRm));
804 else
805 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
806 IEM_GET_MODRM_REG(pVCpu, bRm));
807 IEM_MC_ADVANCE_RIP();
808 IEM_MC_END();
809 }
810 else if (pVCpu->iem.s.uVexLength == 0)
811 {
812 /*
813 * 128-bit: Memory, register.
814 */
815 IEM_MC_BEGIN(0, 2);
816 IEM_MC_LOCAL(RTUINT128U, uSrc);
817 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
818
819 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
820 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
821 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
822 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
823
824 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
825 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
826
827 IEM_MC_ADVANCE_RIP();
828 IEM_MC_END();
829 }
830 else
831 {
832 /*
833 * 256-bit: Memory, register.
834 */
835 IEM_MC_BEGIN(0, 2);
836 IEM_MC_LOCAL(RTUINT256U, uSrc);
837 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
838
839 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
840 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
841 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
842 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
843
844 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
845 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
846
847 IEM_MC_ADVANCE_RIP();
848 IEM_MC_END();
849 }
850 return VINF_SUCCESS;
851}
852
853
854FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
855{
856 Assert(pVCpu->iem.s.uVexLength <= 1);
857 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
858 if (IEM_IS_MODRM_REG_MODE(bRm))
859 {
860 /**
861 * @opcode 0x11
862 * @oppfx 0xf3
863 * @opcodesub 11 mr/reg
864 * @opcpuid avx
865 * @opgroup og_avx_simdfp_datamerge
866 * @opxcpttype 5
867 * @optest op1=1 op2=0 op3=2 -> op1=2
868 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
869 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
870 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
871 */
872 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
873 IEMOP_HLP_DONE_VEX_DECODING();
874 IEM_MC_BEGIN(0, 0);
875
876 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
877 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
878 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
879 IEM_GET_MODRM_REG(pVCpu, bRm),
880 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
881 IEM_MC_ADVANCE_RIP();
882 IEM_MC_END();
883 }
884 else
885 {
886 /**
887 * @opdone
888 * @opcode 0x11
889 * @oppfx 0xf3
890 * @opcodesub !11 mr/reg
891 * @opcpuid avx
892 * @opgroup og_avx_simdfp_datamove
893 * @opxcpttype 5
894 * @opfunction iemOp_vmovss_Vss_Hss_Wss
895 * @optest op1=1 op2=2 -> op1=2
896 * @optest op1=0 op2=-22 -> op1=-22
897 */
898 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
899 IEM_MC_BEGIN(0, 2);
900 IEM_MC_LOCAL(uint32_t, uSrc);
901 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
902
903 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
904 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
905 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
906 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
907
908 IEM_MC_FETCH_YREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
909 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
910
911 IEM_MC_ADVANCE_RIP();
912 IEM_MC_END();
913 }
914
915 return VINF_SUCCESS;
916}
917
918
919FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
920{
921 Assert(pVCpu->iem.s.uVexLength <= 1);
922 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
923 if (IEM_IS_MODRM_REG_MODE(bRm))
924 {
925 /**
926 * @opcode 0x11
927 * @oppfx 0xf2
928 * @opcodesub 11 mr/reg
929 * @opcpuid avx
930 * @opgroup og_avx_simdfp_datamerge
931 * @opxcpttype 5
932 * @optest op1=1 op2=0 op3=2 -> op1=2
933 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
934 * @optest op1=3 op2=-1 op3=0x77 ->
935 * op1=0xffffffffffffffff0000000000000077
936 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
937 */
938 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
939 IEMOP_HLP_DONE_VEX_DECODING();
940 IEM_MC_BEGIN(0, 0);
941
942 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
943 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
944 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
945 IEM_GET_MODRM_REG(pVCpu, bRm),
946 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
947 IEM_MC_ADVANCE_RIP();
948 IEM_MC_END();
949 }
950 else
951 {
952 /**
953 * @opdone
954 * @opcode 0x11
955 * @oppfx 0xf2
956 * @opcodesub !11 mr/reg
957 * @opcpuid avx
958 * @opgroup og_avx_simdfp_datamove
959 * @opxcpttype 5
960 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
961 * @optest op1=1 op2=2 -> op1=2
962 * @optest op1=0 op2=-22 -> op1=-22
963 */
964 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
965 IEM_MC_BEGIN(0, 2);
966 IEM_MC_LOCAL(uint64_t, uSrc);
967 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
968
969 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
970 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
971 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
972 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
973
974 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
975 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
976
977 IEM_MC_ADVANCE_RIP();
978 IEM_MC_END();
979 }
980
981 return VINF_SUCCESS;
982}
983
984
985FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
986{
987 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
988 if (IEM_IS_MODRM_REG_MODE(bRm))
989 {
990 /**
991 * @opcode 0x12
992 * @opcodesub 11 mr/reg
993 * @oppfx none
994 * @opcpuid avx
995 * @opgroup og_avx_simdfp_datamerge
996 * @opxcpttype 7LZ
997 * @optest op2=0x2200220122022203
998 * op3=0x3304330533063307
999 * -> op1=0x22002201220222033304330533063307
1000 * @optest op2=-1 op3=-42 -> op1=-42
1001 * @note op3 and op2 are only the 8-byte high XMM register halfs.
1002 */
1003 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1004
1005 IEMOP_HLP_DONE_VEX_DECODING_L0();
1006 IEM_MC_BEGIN(0, 0);
1007
1008 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1009 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1010 IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1011 IEM_GET_MODRM_RM(pVCpu, bRm),
1012 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1013
1014 IEM_MC_ADVANCE_RIP();
1015 IEM_MC_END();
1016 }
1017 else
1018 {
1019 /**
1020 * @opdone
1021 * @opcode 0x12
1022 * @opcodesub !11 mr/reg
1023 * @oppfx none
1024 * @opcpuid avx
1025 * @opgroup og_avx_simdfp_datamove
1026 * @opxcpttype 5LZ
1027 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
1028 * @optest op1=1 op2=0 op3=0 -> op1=0
1029 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
1030 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
1031 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
1032 */
1033 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1034
1035 IEM_MC_BEGIN(0, 2);
1036 IEM_MC_LOCAL(uint64_t, uSrc);
1037 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1038
1039 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1040 IEMOP_HLP_DONE_VEX_DECODING_L0();
1041 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1042 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1043
1044 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1045 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1046 uSrc,
1047 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1048
1049 IEM_MC_ADVANCE_RIP();
1050 IEM_MC_END();
1051 }
1052 return VINF_SUCCESS;
1053}
1054
1055
1056/**
1057 * @opcode 0x12
1058 * @opcodesub !11 mr/reg
1059 * @oppfx 0x66
1060 * @opcpuid avx
1061 * @opgroup og_avx_pcksclr_datamerge
1062 * @opxcpttype 5LZ
1063 * @optest op2=0 op3=2 -> op1=2
1064 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
1065 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
1066 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
1067 */
1068FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
1069{
1070 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1071 if (IEM_IS_MODRM_MEM_MODE(bRm))
1072 {
1073 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1074
1075 IEM_MC_BEGIN(0, 2);
1076 IEM_MC_LOCAL(uint64_t, uSrc);
1077 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1078
1079 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1080 IEMOP_HLP_DONE_VEX_DECODING_L0();
1081 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1082 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1083
1084 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1085 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1086 uSrc,
1087 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1088
1089 IEM_MC_ADVANCE_RIP();
1090 IEM_MC_END();
1091 return VINF_SUCCESS;
1092 }
1093
1094 /**
1095 * @opdone
1096 * @opmnemonic udvex660f12m3
1097 * @opcode 0x12
1098 * @opcodesub 11 mr/reg
1099 * @oppfx 0x66
1100 * @opunused immediate
1101 * @opcpuid avx
1102 * @optest ->
1103 */
1104 return IEMOP_RAISE_INVALID_OPCODE();
1105}
1106
1107
1108/**
1109 * @opcode 0x12
1110 * @oppfx 0xf3
1111 * @opcpuid avx
1112 * @opgroup og_avx_pcksclr_datamove
1113 * @opxcpttype 4
1114 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
1115 * -> op1=0x00000002000000020000000100000001
1116 * @optest vex.l==1 /
1117 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
1118 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
1119 */
1120FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
1121{
1122 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1123 Assert(pVCpu->iem.s.uVexLength <= 1);
1124 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1125 if (IEM_IS_MODRM_REG_MODE(bRm))
1126 {
1127 /*
1128 * Register, register.
1129 */
1130 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1131 if (pVCpu->iem.s.uVexLength == 0)
1132 {
1133 IEM_MC_BEGIN(2, 0);
1134 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1135 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1136
1137 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1138 IEM_MC_PREPARE_AVX_USAGE();
1139
1140 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1141 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1142 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
1143 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1144
1145 IEM_MC_ADVANCE_RIP();
1146 IEM_MC_END();
1147 }
1148 else
1149 {
1150 IEM_MC_BEGIN(3, 0);
1151 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1152 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1153 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1154
1155 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1156 IEM_MC_PREPARE_AVX_USAGE();
1157 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rr, iYRegDst, iYRegSrc);
1158
1159 IEM_MC_ADVANCE_RIP();
1160 IEM_MC_END();
1161 }
1162 }
1163 else
1164 {
1165 /*
1166 * Register, memory.
1167 */
1168 if (pVCpu->iem.s.uVexLength == 0)
1169 {
1170 IEM_MC_BEGIN(2, 2);
1171 IEM_MC_LOCAL(RTUINT128U, uSrc);
1172 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1173 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1174 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1175
1176 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1177 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1178 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1179 IEM_MC_PREPARE_AVX_USAGE();
1180
1181 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1182 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1183 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
1184 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1185
1186 IEM_MC_ADVANCE_RIP();
1187 IEM_MC_END();
1188 }
1189 else
1190 {
1191 IEM_MC_BEGIN(3, 2);
1192 IEM_MC_LOCAL(RTUINT256U, uSrc);
1193 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1194 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1195 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1196 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1197
1198 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1199 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1200 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1201 IEM_MC_PREPARE_AVX_USAGE();
1202
1203 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1204 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rm, iYRegDst, puSrc);
1205
1206 IEM_MC_ADVANCE_RIP();
1207 IEM_MC_END();
1208 }
1209 }
1210 return VINF_SUCCESS;
1211}
1212
1213
1214/**
1215 * @opcode 0x12
1216 * @oppfx 0xf2
1217 * @opcpuid avx
1218 * @opgroup og_avx_pcksclr_datamove
1219 * @opxcpttype 5
1220 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
1221 * -> op1=0x22222222111111112222222211111111
1222 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
1223 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
1224 */
1225FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
1226{
1227 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1228 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1229 if (IEM_IS_MODRM_REG_MODE(bRm))
1230 {
1231 /*
1232 * Register, register.
1233 */
1234 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1235 if (pVCpu->iem.s.uVexLength == 0)
1236 {
1237 IEM_MC_BEGIN(2, 0);
1238 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1239 IEM_MC_ARG(uint64_t, uSrc, 1);
1240
1241 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1242 IEM_MC_PREPARE_AVX_USAGE();
1243
1244 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1245 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1246 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
1247 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1248
1249 IEM_MC_ADVANCE_RIP();
1250 IEM_MC_END();
1251 }
1252 else
1253 {
1254 IEM_MC_BEGIN(3, 0);
1255 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1256 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1257 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1258
1259 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1260 IEM_MC_PREPARE_AVX_USAGE();
1261 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rr, iYRegDst, iYRegSrc);
1262
1263 IEM_MC_ADVANCE_RIP();
1264 IEM_MC_END();
1265 }
1266 }
1267 else
1268 {
1269 /*
1270 * Register, memory.
1271 */
1272 if (pVCpu->iem.s.uVexLength == 0)
1273 {
1274 IEM_MC_BEGIN(2, 2);
1275 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1276 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1277 IEM_MC_ARG(uint64_t, uSrc, 1);
1278
1279 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1280 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1281 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1282 IEM_MC_PREPARE_AVX_USAGE();
1283
1284 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1285 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1286 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
1287 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1288
1289 IEM_MC_ADVANCE_RIP();
1290 IEM_MC_END();
1291 }
1292 else
1293 {
1294 IEM_MC_BEGIN(3, 2);
1295 IEM_MC_LOCAL(RTUINT256U, uSrc);
1296 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1297 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1298 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1299 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1300
1301 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1302 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1303 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1304 IEM_MC_PREPARE_AVX_USAGE();
1305
1306 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1307 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rm, iYRegDst, puSrc);
1308
1309 IEM_MC_ADVANCE_RIP();
1310 IEM_MC_END();
1311 }
1312 }
1313 return VINF_SUCCESS;
1314}
1315
1316
1317/**
1318 * @opcode 0x13
1319 * @opcodesub !11 mr/reg
1320 * @oppfx none
1321 * @opcpuid avx
1322 * @opgroup og_avx_simdfp_datamove
1323 * @opxcpttype 5
1324 * @optest op1=1 op2=2 -> op1=2
1325 * @optest op1=0 op2=-42 -> op1=-42
1326 */
1327FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
1328{
1329 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1330 if (IEM_IS_MODRM_MEM_MODE(bRm))
1331 {
1332 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1333
1334 IEM_MC_BEGIN(0, 2);
1335 IEM_MC_LOCAL(uint64_t, uSrc);
1336 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1337
1338 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1339 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1340 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1341 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1342
1343 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1344 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1345
1346 IEM_MC_ADVANCE_RIP();
1347 IEM_MC_END();
1348 return VINF_SUCCESS;
1349 }
1350
1351 /**
1352 * @opdone
1353 * @opmnemonic udvex0f13m3
1354 * @opcode 0x13
1355 * @opcodesub 11 mr/reg
1356 * @oppfx none
1357 * @opunused immediate
1358 * @opcpuid avx
1359 * @optest ->
1360 */
1361 return IEMOP_RAISE_INVALID_OPCODE();
1362}
1363
1364
1365/**
1366 * @opcode 0x13
1367 * @opcodesub !11 mr/reg
1368 * @oppfx 0x66
1369 * @opcpuid avx
1370 * @opgroup og_avx_pcksclr_datamove
1371 * @opxcpttype 5
1372 * @optest op1=1 op2=2 -> op1=2
1373 * @optest op1=0 op2=-42 -> op1=-42
1374 */
1375FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1376{
1377 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1378 if (IEM_IS_MODRM_MEM_MODE(bRm))
1379 {
1380 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1381 IEM_MC_BEGIN(0, 2);
1382 IEM_MC_LOCAL(uint64_t, uSrc);
1383 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1384
1385 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1386 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1387 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1388 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1389
1390 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1391 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1392
1393 IEM_MC_ADVANCE_RIP();
1394 IEM_MC_END();
1395 return VINF_SUCCESS;
1396 }
1397
1398 /**
1399 * @opdone
1400 * @opmnemonic udvex660f13m3
1401 * @opcode 0x13
1402 * @opcodesub 11 mr/reg
1403 * @oppfx 0x66
1404 * @opunused immediate
1405 * @opcpuid avx
1406 * @optest ->
1407 */
1408 return IEMOP_RAISE_INVALID_OPCODE();
1409}
1410
1411/* Opcode VEX.F3.0F 0x13 - invalid */
1412/* Opcode VEX.F2.0F 0x13 - invalid */
1413
1414/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1415FNIEMOP_DEF(iemOp_vunpcklps_Vx_Hx_Wx)
1416{
1417 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPS, vunpcklps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1418 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklps);
1419 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1420}
1421
1422
1423/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1424FNIEMOP_DEF(iemOp_vunpcklpd_Vx_Hx_Wx)
1425{
1426 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPD, vunpcklpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1427 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklpd);
1428 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1429}
1430
1431
1432/* Opcode VEX.F3.0F 0x14 - invalid */
1433/* Opcode VEX.F2.0F 0x14 - invalid */
1434
1435
1436/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1437FNIEMOP_DEF(iemOp_vunpckhps_Vx_Hx_Wx)
1438{
1439 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPS, vunpckhps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1440 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhps);
1441 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1442}
1443
1444
1445/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1446FNIEMOP_DEF(iemOp_vunpckhpd_Vx_Hx_Wx)
1447{
1448 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPD, vunpckhpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1449 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhpd);
1450 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1451}
1452
1453
1454/* Opcode VEX.F3.0F 0x15 - invalid */
1455/* Opcode VEX.F2.0F 0x15 - invalid */
1456
1457
1458FNIEMOP_DEF(iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq)
1459{
1460 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1461 if (IEM_IS_MODRM_REG_MODE(bRm))
1462 {
1463 /**
1464 * @opcode 0x16
1465 * @opcodesub 11 mr/reg
1466 * @oppfx none
1467 * @opcpuid avx
1468 * @opgroup og_avx_simdfp_datamerge
1469 * @opxcpttype 7LZ
1470 */
1471 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1472
1473 IEMOP_HLP_DONE_VEX_DECODING_L0();
1474 IEM_MC_BEGIN(0, 0);
1475
1476 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1477 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1478 IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1479 IEM_GET_MODRM_RM(pVCpu, bRm),
1480 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1481
1482 IEM_MC_ADVANCE_RIP();
1483 IEM_MC_END();
1484 }
1485 else
1486 {
1487 /**
1488 * @opdone
1489 * @opcode 0x16
1490 * @opcodesub !11 mr/reg
1491 * @oppfx none
1492 * @opcpuid avx
1493 * @opgroup og_avx_simdfp_datamove
1494 * @opxcpttype 5LZ
1495 * @opfunction iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq
1496 */
1497 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPS, vmovhps, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1498
1499 IEM_MC_BEGIN(0, 2);
1500 IEM_MC_LOCAL(uint64_t, uSrc);
1501 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1502
1503 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1504 IEMOP_HLP_DONE_VEX_DECODING_L0();
1505 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1506 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1507
1508 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1509 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1510 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1511 uSrc);
1512
1513 IEM_MC_ADVANCE_RIP();
1514 IEM_MC_END();
1515 }
1516 return VINF_SUCCESS;
1517}
1518
1519
1520/**
1521 * @opcode 0x16
1522 * @opcodesub !11 mr/reg
1523 * @oppfx 0x66
1524 * @opcpuid avx
1525 * @opgroup og_avx_pcksclr_datamerge
1526 * @opxcpttype 5LZ
1527 */
1528FNIEMOP_DEF(iemOp_vmovhpd_Vdq_Hq_Mq)
1529{
1530 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1531 if (IEM_IS_MODRM_MEM_MODE(bRm))
1532 {
1533 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPD, vmovhpd, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1534
1535 IEM_MC_BEGIN(0, 2);
1536 IEM_MC_LOCAL(uint64_t, uSrc);
1537 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1538
1539 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1540 IEMOP_HLP_DONE_VEX_DECODING_L0();
1541 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1542 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1543
1544 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1545 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1546 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1547 uSrc);
1548
1549 IEM_MC_ADVANCE_RIP();
1550 IEM_MC_END();
1551 return VINF_SUCCESS;
1552 }
1553
1554 /**
1555 * @opdone
1556 * @opmnemonic udvex660f16m3
1557 * @opcode 0x12
1558 * @opcodesub 11 mr/reg
1559 * @oppfx 0x66
1560 * @opunused immediate
1561 * @opcpuid avx
1562 * @optest ->
1563 */
1564 return IEMOP_RAISE_INVALID_OPCODE();
1565}
1566
1567
1568/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1569/**
1570 * @opcode 0x16
1571 * @oppfx 0xf3
1572 * @opcpuid avx
1573 * @opgroup og_avx_pcksclr_datamove
1574 * @opxcpttype 4
1575 */
1576FNIEMOP_DEF(iemOp_vmovshdup_Vx_Wx)
1577{
1578 IEMOP_MNEMONIC2(VEX_RM, VMOVSHDUP, vmovshdup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1579 Assert(pVCpu->iem.s.uVexLength <= 1);
1580 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1581 if (IEM_IS_MODRM_REG_MODE(bRm))
1582 {
1583 /*
1584 * Register, register.
1585 */
1586 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1587 if (pVCpu->iem.s.uVexLength == 0)
1588 {
1589 IEM_MC_BEGIN(2, 0);
1590 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1591 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1592
1593 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1594 IEM_MC_PREPARE_AVX_USAGE();
1595
1596 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1597 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1598 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movshdup, puDst, puSrc);
1599 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1600
1601 IEM_MC_ADVANCE_RIP();
1602 IEM_MC_END();
1603 }
1604 else
1605 {
1606 IEM_MC_BEGIN(3, 0);
1607 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1608 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1609 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1610
1611 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1612 IEM_MC_PREPARE_AVX_USAGE();
1613 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rr, iYRegDst, iYRegSrc);
1614
1615 IEM_MC_ADVANCE_RIP();
1616 IEM_MC_END();
1617 }
1618 }
1619 else
1620 {
1621 /*
1622 * Register, memory.
1623 */
1624 if (pVCpu->iem.s.uVexLength == 0)
1625 {
1626 IEM_MC_BEGIN(2, 2);
1627 IEM_MC_LOCAL(RTUINT128U, uSrc);
1628 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1629 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1630 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1631
1632 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1633 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1634 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1635 IEM_MC_PREPARE_AVX_USAGE();
1636
1637 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1638 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1639 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movshdup, puDst, puSrc);
1640 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1641
1642 IEM_MC_ADVANCE_RIP();
1643 IEM_MC_END();
1644 }
1645 else
1646 {
1647 IEM_MC_BEGIN(3, 2);
1648 IEM_MC_LOCAL(RTUINT256U, uSrc);
1649 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1650 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1651 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1652 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1653
1654 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1655 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1656 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1657 IEM_MC_PREPARE_AVX_USAGE();
1658
1659 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1660 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rm, iYRegDst, puSrc);
1661
1662 IEM_MC_ADVANCE_RIP();
1663 IEM_MC_END();
1664 }
1665 }
1666 return VINF_SUCCESS;
1667}
1668
1669
1670/* Opcode VEX.F2.0F 0x16 - invalid */
1671
1672
1673/**
1674 * @opcode 0x17
1675 * @opcodesub !11 mr/reg
1676 * @oppfx none
1677 * @opcpuid avx
1678 * @opgroup og_avx_simdfp_datamove
1679 * @opxcpttype 5
1680 */
1681FNIEMOP_DEF(iemOp_vmovhps_Mq_Vq)
1682{
1683 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1684 if (IEM_IS_MODRM_MEM_MODE(bRm))
1685 {
1686 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPS, vmovhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1687
1688 IEM_MC_BEGIN(0, 2);
1689 IEM_MC_LOCAL(uint64_t, uSrc);
1690 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1691
1692 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1693 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1694 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1695 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1696
1697 IEM_MC_FETCH_YREG_2ND_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1698 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1699
1700 IEM_MC_ADVANCE_RIP();
1701 IEM_MC_END();
1702 return VINF_SUCCESS;
1703 }
1704
1705 /**
1706 * @opdone
1707 * @opmnemonic udvex0f17m3
1708 * @opcode 0x17
1709 * @opcodesub 11 mr/reg
1710 * @oppfx none
1711 * @opunused immediate
1712 * @opcpuid avx
1713 * @optest ->
1714 */
1715 return IEMOP_RAISE_INVALID_OPCODE();
1716}
1717
1718
1719/**
1720 * @opcode 0x17
1721 * @opcodesub !11 mr/reg
1722 * @oppfx 0x66
1723 * @opcpuid avx
1724 * @opgroup og_avx_pcksclr_datamove
1725 * @opxcpttype 5
1726 */
1727FNIEMOP_DEF(iemOp_vmovhpd_Mq_Vq)
1728{
1729 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1730 if (IEM_IS_MODRM_MEM_MODE(bRm))
1731 {
1732 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPD, vmovhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1733 IEM_MC_BEGIN(0, 2);
1734 IEM_MC_LOCAL(uint64_t, uSrc);
1735 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1736
1737 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1738 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1739 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1740 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1741
1742 IEM_MC_FETCH_YREG_2ND_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1743 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1744
1745 IEM_MC_ADVANCE_RIP();
1746 IEM_MC_END();
1747 return VINF_SUCCESS;
1748 }
1749
1750 /**
1751 * @opdone
1752 * @opmnemonic udvex660f17m3
1753 * @opcode 0x17
1754 * @opcodesub 11 mr/reg
1755 * @oppfx 0x66
1756 * @opunused immediate
1757 * @opcpuid avx
1758 * @optest ->
1759 */
1760 return IEMOP_RAISE_INVALID_OPCODE();
1761}
1762
1763
1764/* Opcode VEX.F3.0F 0x17 - invalid */
1765/* Opcode VEX.F2.0F 0x17 - invalid */
1766
1767
1768/* Opcode VEX.0F 0x18 - invalid */
1769/* Opcode VEX.0F 0x19 - invalid */
1770/* Opcode VEX.0F 0x1a - invalid */
1771/* Opcode VEX.0F 0x1b - invalid */
1772/* Opcode VEX.0F 0x1c - invalid */
1773/* Opcode VEX.0F 0x1d - invalid */
1774/* Opcode VEX.0F 0x1e - invalid */
1775/* Opcode VEX.0F 0x1f - invalid */
1776
1777/* Opcode VEX.0F 0x20 - invalid */
1778/* Opcode VEX.0F 0x21 - invalid */
1779/* Opcode VEX.0F 0x22 - invalid */
1780/* Opcode VEX.0F 0x23 - invalid */
1781/* Opcode VEX.0F 0x24 - invalid */
1782/* Opcode VEX.0F 0x25 - invalid */
1783/* Opcode VEX.0F 0x26 - invalid */
1784/* Opcode VEX.0F 0x27 - invalid */
1785
1786/**
1787 * @opcode 0x28
1788 * @oppfx none
1789 * @opcpuid avx
1790 * @opgroup og_avx_pcksclr_datamove
1791 * @opxcpttype 1
1792 * @optest op1=1 op2=2 -> op1=2
1793 * @optest op1=0 op2=-42 -> op1=-42
1794 * @note Almost identical to vmovapd.
1795 */
1796FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1797{
1798 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1799 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1800 Assert(pVCpu->iem.s.uVexLength <= 1);
1801 if (IEM_IS_MODRM_REG_MODE(bRm))
1802 {
1803 /*
1804 * Register, register.
1805 */
1806 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1807 IEM_MC_BEGIN(1, 0);
1808
1809 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1810 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1811 if (pVCpu->iem.s.uVexLength == 0)
1812 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1813 IEM_GET_MODRM_RM(pVCpu, bRm));
1814 else
1815 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1816 IEM_GET_MODRM_RM(pVCpu, bRm));
1817 IEM_MC_ADVANCE_RIP();
1818 IEM_MC_END();
1819 }
1820 else
1821 {
1822 /*
1823 * Register, memory.
1824 */
1825 if (pVCpu->iem.s.uVexLength == 0)
1826 {
1827 IEM_MC_BEGIN(0, 2);
1828 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1829 IEM_MC_LOCAL(RTUINT128U, uSrc);
1830
1831 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1832 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1833 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1834 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1835
1836 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1837 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1838
1839 IEM_MC_ADVANCE_RIP();
1840 IEM_MC_END();
1841 }
1842 else
1843 {
1844 IEM_MC_BEGIN(0, 2);
1845 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1846 IEM_MC_LOCAL(RTUINT256U, uSrc);
1847
1848 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1849 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1850 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1851 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1852
1853 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1854 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1855
1856 IEM_MC_ADVANCE_RIP();
1857 IEM_MC_END();
1858 }
1859 }
1860 return VINF_SUCCESS;
1861}
1862
1863
1864/**
1865 * @opcode 0x28
1866 * @oppfx 66
1867 * @opcpuid avx
1868 * @opgroup og_avx_pcksclr_datamove
1869 * @opxcpttype 1
1870 * @optest op1=1 op2=2 -> op1=2
1871 * @optest op1=0 op2=-42 -> op1=-42
1872 * @note Almost identical to vmovaps
1873 */
1874FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
1875{
1876 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1877 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1878 Assert(pVCpu->iem.s.uVexLength <= 1);
1879 if (IEM_IS_MODRM_REG_MODE(bRm))
1880 {
1881 /*
1882 * Register, register.
1883 */
1884 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1885 IEM_MC_BEGIN(1, 0);
1886
1887 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1888 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1889 if (pVCpu->iem.s.uVexLength == 0)
1890 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1891 IEM_GET_MODRM_RM(pVCpu, bRm));
1892 else
1893 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1894 IEM_GET_MODRM_RM(pVCpu, bRm));
1895 IEM_MC_ADVANCE_RIP();
1896 IEM_MC_END();
1897 }
1898 else
1899 {
1900 /*
1901 * Register, memory.
1902 */
1903 if (pVCpu->iem.s.uVexLength == 0)
1904 {
1905 IEM_MC_BEGIN(0, 2);
1906 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1907 IEM_MC_LOCAL(RTUINT128U, uSrc);
1908
1909 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1910 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1911 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1912 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1913
1914 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1915 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1916
1917 IEM_MC_ADVANCE_RIP();
1918 IEM_MC_END();
1919 }
1920 else
1921 {
1922 IEM_MC_BEGIN(0, 2);
1923 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1924 IEM_MC_LOCAL(RTUINT256U, uSrc);
1925
1926 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1927 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1928 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1929 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1930
1931 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1932 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1933
1934 IEM_MC_ADVANCE_RIP();
1935 IEM_MC_END();
1936 }
1937 }
1938 return VINF_SUCCESS;
1939}
1940
1941/**
1942 * @opmnemonic udvexf30f28
1943 * @opcode 0x28
1944 * @oppfx 0xf3
1945 * @opunused vex.modrm
1946 * @opcpuid avx
1947 * @optest ->
1948 * @opdone
1949 */
1950
1951/**
1952 * @opmnemonic udvexf20f28
1953 * @opcode 0x28
1954 * @oppfx 0xf2
1955 * @opunused vex.modrm
1956 * @opcpuid avx
1957 * @optest ->
1958 * @opdone
1959 */
1960
1961/**
1962 * @opcode 0x29
1963 * @oppfx none
1964 * @opcpuid avx
1965 * @opgroup og_avx_pcksclr_datamove
1966 * @opxcpttype 1
1967 * @optest op1=1 op2=2 -> op1=2
1968 * @optest op1=0 op2=-42 -> op1=-42
1969 * @note Almost identical to vmovapd.
1970 */
1971FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
1972{
1973 IEMOP_MNEMONIC2(VEX_MR, VMOVAPS, vmovaps, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1974 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1975 Assert(pVCpu->iem.s.uVexLength <= 1);
1976 if (IEM_IS_MODRM_REG_MODE(bRm))
1977 {
1978 /*
1979 * Register, register.
1980 */
1981 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1982 IEM_MC_BEGIN(1, 0);
1983
1984 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1985 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1986 if (pVCpu->iem.s.uVexLength == 0)
1987 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1988 IEM_GET_MODRM_REG(pVCpu, bRm));
1989 else
1990 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1991 IEM_GET_MODRM_REG(pVCpu, bRm));
1992 IEM_MC_ADVANCE_RIP();
1993 IEM_MC_END();
1994 }
1995 else
1996 {
1997 /*
1998 * Register, memory.
1999 */
2000 if (pVCpu->iem.s.uVexLength == 0)
2001 {
2002 IEM_MC_BEGIN(0, 2);
2003 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2004 IEM_MC_LOCAL(RTUINT128U, uSrc);
2005
2006 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2007 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2008 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2009 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2010
2011 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2012 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2013
2014 IEM_MC_ADVANCE_RIP();
2015 IEM_MC_END();
2016 }
2017 else
2018 {
2019 IEM_MC_BEGIN(0, 2);
2020 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2021 IEM_MC_LOCAL(RTUINT256U, uSrc);
2022
2023 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2024 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2025 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2026 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2027
2028 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2029 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2030
2031 IEM_MC_ADVANCE_RIP();
2032 IEM_MC_END();
2033 }
2034 }
2035 return VINF_SUCCESS;
2036}
2037
2038/**
2039 * @opcode 0x29
2040 * @oppfx 66
2041 * @opcpuid avx
2042 * @opgroup og_avx_pcksclr_datamove
2043 * @opxcpttype 1
2044 * @optest op1=1 op2=2 -> op1=2
2045 * @optest op1=0 op2=-42 -> op1=-42
2046 * @note Almost identical to vmovaps
2047 */
2048FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
2049{
2050 IEMOP_MNEMONIC2(VEX_MR, VMOVAPD, vmovapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2051 Assert(pVCpu->iem.s.uVexLength <= 1);
2052 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2053 if (IEM_IS_MODRM_REG_MODE(bRm))
2054 {
2055 /*
2056 * Register, register.
2057 */
2058 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2059 IEM_MC_BEGIN(1, 0);
2060
2061 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2062 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2063 if (pVCpu->iem.s.uVexLength == 0)
2064 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2065 IEM_GET_MODRM_REG(pVCpu, bRm));
2066 else
2067 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2068 IEM_GET_MODRM_REG(pVCpu, bRm));
2069 IEM_MC_ADVANCE_RIP();
2070 IEM_MC_END();
2071 }
2072 else
2073 {
2074 /*
2075 * Register, memory.
2076 */
2077 if (pVCpu->iem.s.uVexLength == 0)
2078 {
2079 IEM_MC_BEGIN(0, 2);
2080 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2081 IEM_MC_LOCAL(RTUINT128U, uSrc);
2082
2083 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2084 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2085 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2086 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2087
2088 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2089 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2090
2091 IEM_MC_ADVANCE_RIP();
2092 IEM_MC_END();
2093 }
2094 else
2095 {
2096 IEM_MC_BEGIN(0, 2);
2097 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2098 IEM_MC_LOCAL(RTUINT256U, uSrc);
2099
2100 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2101 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2102 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2103 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2104
2105 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2106 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2107
2108 IEM_MC_ADVANCE_RIP();
2109 IEM_MC_END();
2110 }
2111 }
2112 return VINF_SUCCESS;
2113}
2114
2115
2116/**
2117 * @opmnemonic udvexf30f29
2118 * @opcode 0x29
2119 * @oppfx 0xf3
2120 * @opunused vex.modrm
2121 * @opcpuid avx
2122 * @optest ->
2123 * @opdone
2124 */
2125
2126/**
2127 * @opmnemonic udvexf20f29
2128 * @opcode 0x29
2129 * @oppfx 0xf2
2130 * @opunused vex.modrm
2131 * @opcpuid avx
2132 * @optest ->
2133 * @opdone
2134 */
2135
2136
2137/** Opcode VEX.0F 0x2a - invalid */
2138/** Opcode VEX.66.0F 0x2a - invalid */
2139/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
2140FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
2141/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
2142FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
2143
2144
2145/**
2146 * @opcode 0x2b
2147 * @opcodesub !11 mr/reg
2148 * @oppfx none
2149 * @opcpuid avx
2150 * @opgroup og_avx_cachect
2151 * @opxcpttype 1
2152 * @optest op1=1 op2=2 -> op1=2
2153 * @optest op1=0 op2=-42 -> op1=-42
2154 * @note Identical implementation to vmovntpd
2155 */
2156FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
2157{
2158 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPS, vmovntps, Mps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2159 Assert(pVCpu->iem.s.uVexLength <= 1);
2160 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2161 if (IEM_IS_MODRM_MEM_MODE(bRm))
2162 {
2163 /*
2164 * memory, register.
2165 */
2166 if (pVCpu->iem.s.uVexLength == 0)
2167 {
2168 IEM_MC_BEGIN(0, 2);
2169 IEM_MC_LOCAL(RTUINT128U, uSrc);
2170 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2171
2172 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2173 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2174 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2175 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2176
2177 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2178 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2179
2180 IEM_MC_ADVANCE_RIP();
2181 IEM_MC_END();
2182 }
2183 else
2184 {
2185 IEM_MC_BEGIN(0, 2);
2186 IEM_MC_LOCAL(RTUINT256U, uSrc);
2187 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2188
2189 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2190 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2191 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2192 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2193
2194 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2195 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2196
2197 IEM_MC_ADVANCE_RIP();
2198 IEM_MC_END();
2199 }
2200 }
2201 /* The register, register encoding is invalid. */
2202 else
2203 return IEMOP_RAISE_INVALID_OPCODE();
2204 return VINF_SUCCESS;
2205}
2206
2207/**
2208 * @opcode 0x2b
2209 * @opcodesub !11 mr/reg
2210 * @oppfx 0x66
2211 * @opcpuid avx
2212 * @opgroup og_avx_cachect
2213 * @opxcpttype 1
2214 * @optest op1=1 op2=2 -> op1=2
2215 * @optest op1=0 op2=-42 -> op1=-42
2216 * @note Identical implementation to vmovntps
2217 */
2218FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
2219{
2220 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPD, vmovntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2221 Assert(pVCpu->iem.s.uVexLength <= 1);
2222 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2223 if (IEM_IS_MODRM_MEM_MODE(bRm))
2224 {
2225 /*
2226 * memory, register.
2227 */
2228 if (pVCpu->iem.s.uVexLength == 0)
2229 {
2230 IEM_MC_BEGIN(0, 2);
2231 IEM_MC_LOCAL(RTUINT128U, uSrc);
2232 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2233
2234 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2235 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2236 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2237 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2238
2239 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2240 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2241
2242 IEM_MC_ADVANCE_RIP();
2243 IEM_MC_END();
2244 }
2245 else
2246 {
2247 IEM_MC_BEGIN(0, 2);
2248 IEM_MC_LOCAL(RTUINT256U, uSrc);
2249 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2250
2251 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2252 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2253 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2254 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2255
2256 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2257 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2258
2259 IEM_MC_ADVANCE_RIP();
2260 IEM_MC_END();
2261 }
2262 }
2263 /* The register, register encoding is invalid. */
2264 else
2265 return IEMOP_RAISE_INVALID_OPCODE();
2266 return VINF_SUCCESS;
2267}
2268
2269/**
2270 * @opmnemonic udvexf30f2b
2271 * @opcode 0x2b
2272 * @oppfx 0xf3
2273 * @opunused vex.modrm
2274 * @opcpuid avx
2275 * @optest ->
2276 * @opdone
2277 */
2278
2279/**
2280 * @opmnemonic udvexf20f2b
2281 * @opcode 0x2b
2282 * @oppfx 0xf2
2283 * @opunused vex.modrm
2284 * @opcpuid avx
2285 * @optest ->
2286 * @opdone
2287 */
2288
2289
2290/* Opcode VEX.0F 0x2c - invalid */
2291/* Opcode VEX.66.0F 0x2c - invalid */
2292/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
2293FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
2294/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
2295FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
2296
2297/* Opcode VEX.0F 0x2d - invalid */
2298/* Opcode VEX.66.0F 0x2d - invalid */
2299/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
2300FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
2301/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
2302FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
2303
2304/** Opcode VEX.0F 0x2e - vucomiss Vss, Wss */
2305FNIEMOP_STUB(iemOp_vucomiss_Vss_Wss);
2306/** Opcode VEX.66.0F 0x2e - vucomisd Vsd, Wsd */
2307FNIEMOP_STUB(iemOp_vucomisd_Vsd_Wsd);
2308/* Opcode VEX.F3.0F 0x2e - invalid */
2309/* Opcode VEX.F2.0F 0x2e - invalid */
2310
2311/** Opcode VEX.0F 0x2f - vcomiss Vss, Wss */
2312FNIEMOP_STUB(iemOp_vcomiss_Vss_Wss);
2313/** Opcode VEX.66.0F 0x2f - vcomisd Vsd, Wsd */
2314FNIEMOP_STUB(iemOp_vcomisd_Vsd_Wsd);
2315/* Opcode VEX.F3.0F 0x2f - invalid */
2316/* Opcode VEX.F2.0F 0x2f - invalid */
2317
2318/* Opcode VEX.0F 0x30 - invalid */
2319/* Opcode VEX.0F 0x31 - invalid */
2320/* Opcode VEX.0F 0x32 - invalid */
2321/* Opcode VEX.0F 0x33 - invalid */
2322/* Opcode VEX.0F 0x34 - invalid */
2323/* Opcode VEX.0F 0x35 - invalid */
2324/* Opcode VEX.0F 0x36 - invalid */
2325/* Opcode VEX.0F 0x37 - invalid */
2326/* Opcode VEX.0F 0x38 - invalid */
2327/* Opcode VEX.0F 0x39 - invalid */
2328/* Opcode VEX.0F 0x3a - invalid */
2329/* Opcode VEX.0F 0x3b - invalid */
2330/* Opcode VEX.0F 0x3c - invalid */
2331/* Opcode VEX.0F 0x3d - invalid */
2332/* Opcode VEX.0F 0x3e - invalid */
2333/* Opcode VEX.0F 0x3f - invalid */
2334/* Opcode VEX.0F 0x40 - invalid */
2335/* Opcode VEX.0F 0x41 - invalid */
2336/* Opcode VEX.0F 0x42 - invalid */
2337/* Opcode VEX.0F 0x43 - invalid */
2338/* Opcode VEX.0F 0x44 - invalid */
2339/* Opcode VEX.0F 0x45 - invalid */
2340/* Opcode VEX.0F 0x46 - invalid */
2341/* Opcode VEX.0F 0x47 - invalid */
2342/* Opcode VEX.0F 0x48 - invalid */
2343/* Opcode VEX.0F 0x49 - invalid */
2344/* Opcode VEX.0F 0x4a - invalid */
2345/* Opcode VEX.0F 0x4b - invalid */
2346/* Opcode VEX.0F 0x4c - invalid */
2347/* Opcode VEX.0F 0x4d - invalid */
2348/* Opcode VEX.0F 0x4e - invalid */
2349/* Opcode VEX.0F 0x4f - invalid */
2350
2351/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
2352FNIEMOP_STUB(iemOp_vmovmskps_Gy_Ups);
2353/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
2354FNIEMOP_STUB(iemOp_vmovmskpd_Gy_Upd);
2355/* Opcode VEX.F3.0F 0x50 - invalid */
2356/* Opcode VEX.F2.0F 0x50 - invalid */
2357
2358/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
2359FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
2360/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
2361FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
2362/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
2363FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
2364/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
2365FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
2366
2367/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
2368FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
2369/* Opcode VEX.66.0F 0x52 - invalid */
2370/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
2371FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
2372/* Opcode VEX.F2.0F 0x52 - invalid */
2373
2374/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
2375FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
2376/* Opcode VEX.66.0F 0x53 - invalid */
2377/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
2378FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
2379/* Opcode VEX.F2.0F 0x53 - invalid */
2380
2381
2382/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
2383FNIEMOP_DEF(iemOp_vandps_Vps_Hps_Wps)
2384{
2385 IEMOP_MNEMONIC3(VEX_RVM, VANDPS, vandps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2386 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2387 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2388}
2389
2390
2391/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
2392FNIEMOP_DEF(iemOp_vandpd_Vpd_Hpd_Wpd)
2393{
2394 IEMOP_MNEMONIC3(VEX_RVM, VANDPD, vandpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2395 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2396 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2397}
2398
2399
2400/* Opcode VEX.F3.0F 0x54 - invalid */
2401/* Opcode VEX.F2.0F 0x54 - invalid */
2402
2403
2404/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
2405FNIEMOP_DEF(iemOp_vandnps_Vps_Hps_Wps)
2406{
2407 IEMOP_MNEMONIC3(VEX_RVM, VANDNPS, vandnps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2408 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2409 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2410}
2411
2412
2413/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
2414FNIEMOP_DEF(iemOp_vandnpd_Vpd_Hpd_Wpd)
2415{
2416 IEMOP_MNEMONIC3(VEX_RVM, VANDNPD, vandnpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2417 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2418 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2419}
2420
2421
2422/* Opcode VEX.F3.0F 0x55 - invalid */
2423/* Opcode VEX.F2.0F 0x55 - invalid */
2424
2425/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
2426FNIEMOP_DEF(iemOp_vorps_Vps_Hps_Wps)
2427{
2428 IEMOP_MNEMONIC3(VEX_RVM, VORPS, vorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2429 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2430 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2431}
2432
2433
2434/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
2435FNIEMOP_DEF(iemOp_vorpd_Vpd_Hpd_Wpd)
2436{
2437 IEMOP_MNEMONIC3(VEX_RVM, VORPD, vorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2438 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2439 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2440}
2441
2442
2443/* Opcode VEX.F3.0F 0x56 - invalid */
2444/* Opcode VEX.F2.0F 0x56 - invalid */
2445
2446
2447/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
2448FNIEMOP_DEF(iemOp_vxorps_Vps_Hps_Wps)
2449{
2450 IEMOP_MNEMONIC3(VEX_RVM, VXORPS, vxorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2451 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2452 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2453}
2454
2455
2456/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
2457FNIEMOP_DEF(iemOp_vxorpd_Vpd_Hpd_Wpd)
2458{
2459 IEMOP_MNEMONIC3(VEX_RVM, VXORPD, vxorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2460 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2461 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2462}
2463
2464
2465/* Opcode VEX.F3.0F 0x57 - invalid */
2466/* Opcode VEX.F2.0F 0x57 - invalid */
2467
2468/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
2469FNIEMOP_STUB(iemOp_vaddps_Vps_Hps_Wps);
2470/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
2471FNIEMOP_STUB(iemOp_vaddpd_Vpd_Hpd_Wpd);
2472/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
2473FNIEMOP_STUB(iemOp_vaddss_Vss_Hss_Wss);
2474/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
2475FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
2476
2477/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
2478FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
2479/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
2480FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
2481/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
2482FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
2483/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
2484FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
2485
2486/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
2487FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
2488/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
2489FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
2490/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
2491FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
2492/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
2493FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
2494
2495/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
2496FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
2497/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
2498FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
2499/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
2500FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
2501/* Opcode VEX.F2.0F 0x5b - invalid */
2502
2503/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
2504FNIEMOP_STUB(iemOp_vsubps_Vps_Hps_Wps);
2505/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
2506FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
2507/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
2508FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
2509/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
2510FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
2511
2512/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
2513FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
2514/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
2515FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
2516/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
2517FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
2518/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
2519FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
2520
2521/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
2522FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
2523/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
2524FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
2525/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
2526FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
2527/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
2528FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
2529
2530/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
2531FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
2532/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
2533FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
2534/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
2535FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
2536/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
2537FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
2538
2539
2540/* Opcode VEX.0F 0x60 - invalid */
2541
2542
2543/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, Wx */
2544FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
2545{
2546 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLBW, vpunpcklbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2547 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklbw);
2548 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2549}
2550
2551
2552/* Opcode VEX.F3.0F 0x60 - invalid */
2553
2554
2555/* Opcode VEX.0F 0x61 - invalid */
2556
2557
2558/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
2559FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
2560{
2561 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLWD, vpunpcklwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2562 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklwd);
2563 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2564}
2565
2566
2567/* Opcode VEX.F3.0F 0x61 - invalid */
2568
2569
2570/* Opcode VEX.0F 0x62 - invalid */
2571
2572/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
2573FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
2574{
2575 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLDQ, vpunpckldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2576 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckldq);
2577 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2578}
2579
2580
2581/* Opcode VEX.F3.0F 0x62 - invalid */
2582
2583
2584
2585/* Opcode VEX.0F 0x63 - invalid */
2586
2587
2588/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
2589FNIEMOP_DEF(iemOp_vpacksswb_Vx_Hx_Wx)
2590{
2591 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSWB, vpacksswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2592 IEMOPMEDIAOPTF3_INIT_VARS( vpacksswb);
2593 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2594}
2595
2596
2597/* Opcode VEX.F3.0F 0x63 - invalid */
2598
2599/* Opcode VEX.0F 0x64 - invalid */
2600
2601
2602/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
2603FNIEMOP_DEF(iemOp_vpcmpgtb_Vx_Hx_Wx)
2604{
2605 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTB, vpcmpgtb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2606 IEMOPMEDIAF3_INIT_VARS( vpcmpgtb);
2607 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2608}
2609
2610
2611/* Opcode VEX.F3.0F 0x64 - invalid */
2612
2613/* Opcode VEX.0F 0x65 - invalid */
2614
2615
2616/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
2617FNIEMOP_DEF(iemOp_vpcmpgtw_Vx_Hx_Wx)
2618{
2619 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTW, vpcmpgtw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2620 IEMOPMEDIAF3_INIT_VARS( vpcmpgtw);
2621 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2622}
2623
2624
2625/* Opcode VEX.F3.0F 0x65 - invalid */
2626
2627/* Opcode VEX.0F 0x66 - invalid */
2628
2629
2630/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
2631FNIEMOP_DEF(iemOp_vpcmpgtd_Vx_Hx_Wx)
2632{
2633 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTD, vpcmpgtd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2634 IEMOPMEDIAF3_INIT_VARS( vpcmpgtd);
2635 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2636}
2637
2638
2639/* Opcode VEX.F3.0F 0x66 - invalid */
2640
2641/* Opcode VEX.0F 0x67 - invalid */
2642
2643
2644/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
2645FNIEMOP_DEF(iemOp_vpackuswb_Vx_Hx_W)
2646{
2647 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSWB, vpackuswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2648 IEMOPMEDIAOPTF3_INIT_VARS( vpackuswb);
2649 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2650}
2651
2652
2653/* Opcode VEX.F3.0F 0x67 - invalid */
2654
2655
2656///**
2657// * Common worker for SSE2 instructions on the form:
2658// * pxxxx xmm1, xmm2/mem128
2659// *
2660// * The 2nd operand is the second half of a register, which in the memory case
2661// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
2662// * where it may read the full 128 bits or only the upper 64 bits.
2663// *
2664// * Exceptions type 4.
2665// */
2666//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
2667//{
2668// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2669// if (IEM_IS_MODRM_REG_MODE(bRm))
2670// {
2671// /*
2672// * Register, register.
2673// */
2674// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2675// IEM_MC_BEGIN(2, 0);
2676// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2677// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2678// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2679// IEM_MC_PREPARE_SSE_USAGE();
2680// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2681// IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2682// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2683// IEM_MC_ADVANCE_RIP();
2684// IEM_MC_END();
2685// }
2686// else
2687// {
2688// /*
2689// * Register, memory.
2690// */
2691// IEM_MC_BEGIN(2, 2);
2692// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2693// IEM_MC_LOCAL(RTUINT128U, uSrc);
2694// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2695// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2696//
2697// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2698// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2699// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2700// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
2701//
2702// IEM_MC_PREPARE_SSE_USAGE();
2703// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2704// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2705//
2706// IEM_MC_ADVANCE_RIP();
2707// IEM_MC_END();
2708// }
2709// return VINF_SUCCESS;
2710//}
2711
2712
2713/* Opcode VEX.0F 0x68 - invalid */
2714
2715/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
2716FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
2717{
2718 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHBW, vpunpckhbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2719 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhbw);
2720 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2721}
2722
2723
2724/* Opcode VEX.F3.0F 0x68 - invalid */
2725
2726
2727/* Opcode VEX.0F 0x69 - invalid */
2728
2729
2730/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
2731FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
2732{
2733 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHWD, vpunpckhwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2734 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhwd);
2735 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2736}
2737
2738
2739/* Opcode VEX.F3.0F 0x69 - invalid */
2740
2741
2742/* Opcode VEX.0F 0x6a - invalid */
2743
2744
2745/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
2746FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
2747{
2748 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHDQ, vpunpckhdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2749 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhdq);
2750 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2751}
2752
2753
2754/* Opcode VEX.F3.0F 0x6a - invalid */
2755
2756
2757/* Opcode VEX.0F 0x6b - invalid */
2758
2759
2760/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
2761FNIEMOP_DEF(iemOp_vpackssdw_Vx_Hx_Wx)
2762{
2763 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSDW, vpackssdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2764 IEMOPMEDIAOPTF3_INIT_VARS( vpackssdw);
2765 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2766}
2767
2768
2769/* Opcode VEX.F3.0F 0x6b - invalid */
2770
2771
2772/* Opcode VEX.0F 0x6c - invalid */
2773
2774
2775/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
2776FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
2777{
2778 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLQDQ, vpunpcklqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2779 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklqdq);
2780 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2781}
2782
2783
2784/* Opcode VEX.F3.0F 0x6c - invalid */
2785/* Opcode VEX.F2.0F 0x6c - invalid */
2786
2787
2788/* Opcode VEX.0F 0x6d - invalid */
2789
2790
2791/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
2792FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
2793{
2794 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHQDQ, vpunpckhqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2795 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhqdq);
2796 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2797}
2798
2799
2800/* Opcode VEX.F3.0F 0x6d - invalid */
2801
2802
2803/* Opcode VEX.0F 0x6e - invalid */
2804
2805FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
2806{
2807 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2808 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2809 {
2810 /**
2811 * @opcode 0x6e
2812 * @opcodesub rex.w=1
2813 * @oppfx 0x66
2814 * @opcpuid avx
2815 * @opgroup og_avx_simdint_datamov
2816 * @opxcpttype 5
2817 * @optest 64-bit / op1=1 op2=2 -> op1=2
2818 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
2819 */
2820 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
2821 if (IEM_IS_MODRM_REG_MODE(bRm))
2822 {
2823 /* XMM, greg64 */
2824 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2825 IEM_MC_BEGIN(0, 1);
2826 IEM_MC_LOCAL(uint64_t, u64Tmp);
2827
2828 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2829 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2830
2831 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
2832 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
2833
2834 IEM_MC_ADVANCE_RIP();
2835 IEM_MC_END();
2836 }
2837 else
2838 {
2839 /* XMM, [mem64] */
2840 IEM_MC_BEGIN(0, 2);
2841 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2842 IEM_MC_LOCAL(uint64_t, u64Tmp);
2843
2844 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2845 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2846 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2847 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2848
2849 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2850 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
2851
2852 IEM_MC_ADVANCE_RIP();
2853 IEM_MC_END();
2854 }
2855 }
2856 else
2857 {
2858 /**
2859 * @opdone
2860 * @opcode 0x6e
2861 * @opcodesub rex.w=0
2862 * @oppfx 0x66
2863 * @opcpuid avx
2864 * @opgroup og_avx_simdint_datamov
2865 * @opxcpttype 5
2866 * @opfunction iemOp_vmovd_q_Vy_Ey
2867 * @optest op1=1 op2=2 -> op1=2
2868 * @optest op1=0 op2=-42 -> op1=-42
2869 */
2870 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
2871 if (IEM_IS_MODRM_REG_MODE(bRm))
2872 {
2873 /* XMM, greg32 */
2874 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2875 IEM_MC_BEGIN(0, 1);
2876 IEM_MC_LOCAL(uint32_t, u32Tmp);
2877
2878 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2879 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2880
2881 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
2882 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
2883
2884 IEM_MC_ADVANCE_RIP();
2885 IEM_MC_END();
2886 }
2887 else
2888 {
2889 /* XMM, [mem32] */
2890 IEM_MC_BEGIN(0, 2);
2891 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2892 IEM_MC_LOCAL(uint32_t, u32Tmp);
2893
2894 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2895 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2896 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2897 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2898
2899 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2900 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
2901
2902 IEM_MC_ADVANCE_RIP();
2903 IEM_MC_END();
2904 }
2905 }
2906 return VINF_SUCCESS;
2907}
2908
2909
2910/* Opcode VEX.F3.0F 0x6e - invalid */
2911
2912
2913/* Opcode VEX.0F 0x6f - invalid */
2914
2915/**
2916 * @opcode 0x6f
2917 * @oppfx 0x66
2918 * @opcpuid avx
2919 * @opgroup og_avx_simdint_datamove
2920 * @opxcpttype 1
2921 * @optest op1=1 op2=2 -> op1=2
2922 * @optest op1=0 op2=-42 -> op1=-42
2923 */
2924FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
2925{
2926 IEMOP_MNEMONIC2(VEX_RM, VMOVDQA, vmovdqa, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2927 Assert(pVCpu->iem.s.uVexLength <= 1);
2928 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2929 if (IEM_IS_MODRM_REG_MODE(bRm))
2930 {
2931 /*
2932 * Register, register.
2933 */
2934 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2935 IEM_MC_BEGIN(0, 0);
2936
2937 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2938 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2939 if (pVCpu->iem.s.uVexLength == 0)
2940 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
2941 IEM_GET_MODRM_RM(pVCpu, bRm));
2942 else
2943 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
2944 IEM_GET_MODRM_RM(pVCpu, bRm));
2945 IEM_MC_ADVANCE_RIP();
2946 IEM_MC_END();
2947 }
2948 else if (pVCpu->iem.s.uVexLength == 0)
2949 {
2950 /*
2951 * Register, memory128.
2952 */
2953 IEM_MC_BEGIN(0, 2);
2954 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2955 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2956
2957 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2958 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2959 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2960 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2961
2962 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2963 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
2964
2965 IEM_MC_ADVANCE_RIP();
2966 IEM_MC_END();
2967 }
2968 else
2969 {
2970 /*
2971 * Register, memory256.
2972 */
2973 IEM_MC_BEGIN(0, 2);
2974 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
2975 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2976
2977 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2978 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2979 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2980 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2981
2982 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2983 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
2984
2985 IEM_MC_ADVANCE_RIP();
2986 IEM_MC_END();
2987 }
2988 return VINF_SUCCESS;
2989}
2990
2991/**
2992 * @opcode 0x6f
2993 * @oppfx 0xf3
2994 * @opcpuid avx
2995 * @opgroup og_avx_simdint_datamove
2996 * @opxcpttype 4UA
2997 * @optest op1=1 op2=2 -> op1=2
2998 * @optest op1=0 op2=-42 -> op1=-42
2999 */
3000FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
3001{
3002 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3003 Assert(pVCpu->iem.s.uVexLength <= 1);
3004 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3005 if (IEM_IS_MODRM_REG_MODE(bRm))
3006 {
3007 /*
3008 * Register, register.
3009 */
3010 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3011 IEM_MC_BEGIN(0, 0);
3012
3013 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3014 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3015 if (pVCpu->iem.s.uVexLength == 0)
3016 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3017 IEM_GET_MODRM_RM(pVCpu, bRm));
3018 else
3019 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3020 IEM_GET_MODRM_RM(pVCpu, bRm));
3021 IEM_MC_ADVANCE_RIP();
3022 IEM_MC_END();
3023 }
3024 else if (pVCpu->iem.s.uVexLength == 0)
3025 {
3026 /*
3027 * Register, memory128.
3028 */
3029 IEM_MC_BEGIN(0, 2);
3030 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3031 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3032
3033 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3034 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3035 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3036 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3037
3038 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3039 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3040
3041 IEM_MC_ADVANCE_RIP();
3042 IEM_MC_END();
3043 }
3044 else
3045 {
3046 /*
3047 * Register, memory256.
3048 */
3049 IEM_MC_BEGIN(0, 2);
3050 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3051 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3052
3053 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3054 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3055 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3056 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3057
3058 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3059 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3060
3061 IEM_MC_ADVANCE_RIP();
3062 IEM_MC_END();
3063 }
3064 return VINF_SUCCESS;
3065}
3066
3067
3068/* Opcode VEX.0F 0x70 - invalid */
3069
3070
3071/**
3072 * Common worker for AVX/AVX2 instructions on the forms:
3073 * - vpxxx xmm0, xmm2/mem128, imm8
3074 * - vpxxx ymm0, ymm2/mem256, imm8
3075 *
3076 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3077 */
3078FNIEMOP_DEF_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3079{
3080 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3081 if (IEM_IS_MODRM_REG_MODE(bRm))
3082 {
3083 /*
3084 * Register, register.
3085 */
3086 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3087 if (pVCpu->iem.s.uVexLength)
3088 {
3089 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3090 IEM_MC_BEGIN(3, 2);
3091 IEM_MC_LOCAL(RTUINT256U, uDst);
3092 IEM_MC_LOCAL(RTUINT256U, uSrc);
3093 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3094 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3095 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3096 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3097 IEM_MC_PREPARE_AVX_USAGE();
3098 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3099 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bEvilArg);
3100 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3101 IEM_MC_ADVANCE_RIP();
3102 IEM_MC_END();
3103 }
3104 else
3105 {
3106 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3107 IEM_MC_BEGIN(3, 0);
3108 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3109 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3110 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3111 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3112 IEM_MC_PREPARE_AVX_USAGE();
3113 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3114 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3115 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bEvilArg);
3116 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3117 IEM_MC_ADVANCE_RIP();
3118 IEM_MC_END();
3119 }
3120 }
3121 else
3122 {
3123 /*
3124 * Register, memory.
3125 */
3126 if (pVCpu->iem.s.uVexLength)
3127 {
3128 IEM_MC_BEGIN(3, 3);
3129 IEM_MC_LOCAL(RTUINT256U, uDst);
3130 IEM_MC_LOCAL(RTUINT256U, uSrc);
3131 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3132 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3133 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3134
3135 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3136 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3137 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3138 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3139 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3140 IEM_MC_PREPARE_AVX_USAGE();
3141
3142 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3143 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bEvilArg);
3144 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3145
3146 IEM_MC_ADVANCE_RIP();
3147 IEM_MC_END();
3148 }
3149 else
3150 {
3151 IEM_MC_BEGIN(3, 1);
3152 IEM_MC_LOCAL(RTUINT128U, uSrc);
3153 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3154 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3155 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
3156
3157 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3158 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3159 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3160 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3161 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3162 IEM_MC_PREPARE_AVX_USAGE();
3163
3164 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3165 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3166 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bEvilArg);
3167 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3168
3169 IEM_MC_ADVANCE_RIP();
3170 IEM_MC_END();
3171 }
3172 }
3173 return VINF_SUCCESS;
3174}
3175
3176
3177/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
3178FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
3179{
3180 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFD, vpshufd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3181 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufd_u128,
3182 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufd_u256, iemAImpl_vpshufd_u256_fallback));
3183
3184}
3185
3186
3187/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
3188FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
3189{
3190 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFHW, vpshufhw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3191 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufhw_u128,
3192 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufhw_u256, iemAImpl_vpshufhw_u256_fallback));
3193
3194}
3195
3196
3197/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
3198FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
3199{
3200 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFLW, vpshuflw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3201 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshuflw_u128,
3202 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshuflw_u256, iemAImpl_vpshuflw_u256_fallback));
3203}
3204
3205
3206/* Opcode VEX.0F 0x71 11/2 - invalid. */
3207/** Opcode VEX.66.0F 0x71 11/2. */
3208FNIEMOP_STUB_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
3209
3210/* Opcode VEX.0F 0x71 11/4 - invalid */
3211/** Opcode VEX.66.0F 0x71 11/4. */
3212FNIEMOP_STUB_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm);
3213
3214/* Opcode VEX.0F 0x71 11/6 - invalid */
3215/** Opcode VEX.66.0F 0x71 11/6. */
3216FNIEMOP_STUB_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm);
3217
3218
3219/**
3220 * VEX Group 12 jump table for register variant.
3221 */
3222IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
3223{
3224 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3225 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3226 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3227 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3228 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3229 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3230 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3231 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3232};
3233AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
3234
3235
3236/** Opcode VEX.0F 0x71. */
3237FNIEMOP_DEF(iemOp_VGrp12)
3238{
3239 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3240 if (IEM_IS_MODRM_REG_MODE(bRm))
3241 /* register, register */
3242 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3243 + pVCpu->iem.s.idxPrefix], bRm);
3244 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3245}
3246
3247
3248/* Opcode VEX.0F 0x72 11/2 - invalid. */
3249/** Opcode VEX.66.0F 0x72 11/2. */
3250FNIEMOP_STUB_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
3251
3252/* Opcode VEX.0F 0x72 11/4 - invalid. */
3253/** Opcode VEX.66.0F 0x72 11/4. */
3254FNIEMOP_STUB_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm);
3255
3256/* Opcode VEX.0F 0x72 11/6 - invalid. */
3257/** Opcode VEX.66.0F 0x72 11/6. */
3258FNIEMOP_STUB_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm);
3259
3260
3261/**
3262 * Group 13 jump table for register variant.
3263 */
3264IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
3265{
3266 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3267 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3268 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3269 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3270 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3271 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3272 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3273 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3274};
3275AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
3276
3277/** Opcode VEX.0F 0x72. */
3278FNIEMOP_DEF(iemOp_VGrp13)
3279{
3280 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3281 if (IEM_IS_MODRM_REG_MODE(bRm))
3282 /* register, register */
3283 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3284 + pVCpu->iem.s.idxPrefix], bRm);
3285 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3286}
3287
3288
3289/* Opcode VEX.0F 0x73 11/2 - invalid. */
3290/** Opcode VEX.66.0F 0x73 11/2. */
3291FNIEMOP_STUB_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
3292
3293/** Opcode VEX.66.0F 0x73 11/3. */
3294FNIEMOP_STUB_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm);
3295
3296/* Opcode VEX.0F 0x73 11/6 - invalid. */
3297/** Opcode VEX.66.0F 0x73 11/6. */
3298FNIEMOP_STUB_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm);
3299
3300/** Opcode VEX.66.0F 0x73 11/7. */
3301FNIEMOP_STUB_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm);
3302
3303/**
3304 * Group 14 jump table for register variant.
3305 */
3306IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
3307{
3308 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3309 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3310 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3311 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3312 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3313 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3314 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3315 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3316};
3317AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
3318
3319
3320/** Opcode VEX.0F 0x73. */
3321FNIEMOP_DEF(iemOp_VGrp14)
3322{
3323 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3324 if (IEM_IS_MODRM_REG_MODE(bRm))
3325 /* register, register */
3326 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3327 + pVCpu->iem.s.idxPrefix], bRm);
3328 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3329}
3330
3331
3332/* Opcode VEX.0F 0x74 - invalid */
3333
3334
3335/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
3336FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
3337{
3338 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQB, vpcmpeqb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3339 IEMOPMEDIAF3_INIT_VARS( vpcmpeqb);
3340 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3341}
3342
3343/* Opcode VEX.F3.0F 0x74 - invalid */
3344/* Opcode VEX.F2.0F 0x74 - invalid */
3345
3346
3347/* Opcode VEX.0F 0x75 - invalid */
3348
3349
3350/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
3351FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
3352{
3353 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQW, vpcmpeqw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3354 IEMOPMEDIAF3_INIT_VARS( vpcmpeqw);
3355 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3356}
3357
3358
3359/* Opcode VEX.F3.0F 0x75 - invalid */
3360/* Opcode VEX.F2.0F 0x75 - invalid */
3361
3362
3363/* Opcode VEX.0F 0x76 - invalid */
3364
3365
3366/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
3367FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
3368{
3369 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQD, vpcmpeqd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3370 IEMOPMEDIAF3_INIT_VARS( vpcmpeqd);
3371 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3372}
3373
3374
3375/* Opcode VEX.F3.0F 0x76 - invalid */
3376/* Opcode VEX.F2.0F 0x76 - invalid */
3377
3378
3379/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
3380FNIEMOP_STUB(iemOp_vzeroupperv__vzeroallv);
3381/* Opcode VEX.66.0F 0x77 - invalid */
3382/* Opcode VEX.F3.0F 0x77 - invalid */
3383/* Opcode VEX.F2.0F 0x77 - invalid */
3384
3385/* Opcode VEX.0F 0x78 - invalid */
3386/* Opcode VEX.66.0F 0x78 - invalid */
3387/* Opcode VEX.F3.0F 0x78 - invalid */
3388/* Opcode VEX.F2.0F 0x78 - invalid */
3389
3390/* Opcode VEX.0F 0x79 - invalid */
3391/* Opcode VEX.66.0F 0x79 - invalid */
3392/* Opcode VEX.F3.0F 0x79 - invalid */
3393/* Opcode VEX.F2.0F 0x79 - invalid */
3394
3395/* Opcode VEX.0F 0x7a - invalid */
3396/* Opcode VEX.66.0F 0x7a - invalid */
3397/* Opcode VEX.F3.0F 0x7a - invalid */
3398/* Opcode VEX.F2.0F 0x7a - invalid */
3399
3400/* Opcode VEX.0F 0x7b - invalid */
3401/* Opcode VEX.66.0F 0x7b - invalid */
3402/* Opcode VEX.F3.0F 0x7b - invalid */
3403/* Opcode VEX.F2.0F 0x7b - invalid */
3404
3405/* Opcode VEX.0F 0x7c - invalid */
3406/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
3407FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
3408/* Opcode VEX.F3.0F 0x7c - invalid */
3409/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
3410FNIEMOP_STUB(iemOp_vhaddps_Vps_Hps_Wps);
3411
3412/* Opcode VEX.0F 0x7d - invalid */
3413/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
3414FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
3415/* Opcode VEX.F3.0F 0x7d - invalid */
3416/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
3417FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
3418
3419
3420/* Opcode VEX.0F 0x7e - invalid */
3421
3422FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
3423{
3424 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3425 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3426 {
3427 /**
3428 * @opcode 0x7e
3429 * @opcodesub rex.w=1
3430 * @oppfx 0x66
3431 * @opcpuid avx
3432 * @opgroup og_avx_simdint_datamov
3433 * @opxcpttype 5
3434 * @optest 64-bit / op1=1 op2=2 -> op1=2
3435 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3436 */
3437 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3438 if (IEM_IS_MODRM_REG_MODE(bRm))
3439 {
3440 /* greg64, XMM */
3441 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3442 IEM_MC_BEGIN(0, 1);
3443 IEM_MC_LOCAL(uint64_t, u64Tmp);
3444
3445 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3446 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3447
3448 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3449 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp);
3450
3451 IEM_MC_ADVANCE_RIP();
3452 IEM_MC_END();
3453 }
3454 else
3455 {
3456 /* [mem64], XMM */
3457 IEM_MC_BEGIN(0, 2);
3458 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3459 IEM_MC_LOCAL(uint64_t, u64Tmp);
3460
3461 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3462 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3463 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3464 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3465
3466 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3467 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
3468
3469 IEM_MC_ADVANCE_RIP();
3470 IEM_MC_END();
3471 }
3472 }
3473 else
3474 {
3475 /**
3476 * @opdone
3477 * @opcode 0x7e
3478 * @opcodesub rex.w=0
3479 * @oppfx 0x66
3480 * @opcpuid avx
3481 * @opgroup og_avx_simdint_datamov
3482 * @opxcpttype 5
3483 * @opfunction iemOp_vmovd_q_Vy_Ey
3484 * @optest op1=1 op2=2 -> op1=2
3485 * @optest op1=0 op2=-42 -> op1=-42
3486 */
3487 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3488 if (IEM_IS_MODRM_REG_MODE(bRm))
3489 {
3490 /* greg32, XMM */
3491 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3492 IEM_MC_BEGIN(0, 1);
3493 IEM_MC_LOCAL(uint32_t, u32Tmp);
3494
3495 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3496 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3497
3498 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3499 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp);
3500
3501 IEM_MC_ADVANCE_RIP();
3502 IEM_MC_END();
3503 }
3504 else
3505 {
3506 /* [mem32], XMM */
3507 IEM_MC_BEGIN(0, 2);
3508 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3509 IEM_MC_LOCAL(uint32_t, u32Tmp);
3510
3511 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3512 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3513 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3514 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3515
3516 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3517 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
3518
3519 IEM_MC_ADVANCE_RIP();
3520 IEM_MC_END();
3521 }
3522 }
3523 return VINF_SUCCESS;
3524}
3525
3526/**
3527 * @opcode 0x7e
3528 * @oppfx 0xf3
3529 * @opcpuid avx
3530 * @opgroup og_avx_pcksclr_datamove
3531 * @opxcpttype none
3532 * @optest op1=1 op2=2 -> op1=2
3533 * @optest op1=0 op2=-42 -> op1=-42
3534 */
3535FNIEMOP_DEF(iemOp_vmovq_Vq_Wq)
3536{
3537 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
3538 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3539 if (IEM_IS_MODRM_REG_MODE(bRm))
3540 {
3541 /*
3542 * Register, register.
3543 */
3544 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3545 IEM_MC_BEGIN(0, 0);
3546
3547 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3548 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3549
3550 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3551 IEM_GET_MODRM_RM(pVCpu, bRm));
3552 IEM_MC_ADVANCE_RIP();
3553 IEM_MC_END();
3554 }
3555 else
3556 {
3557 /*
3558 * Memory, register.
3559 */
3560 IEM_MC_BEGIN(0, 2);
3561 IEM_MC_LOCAL(uint64_t, uSrc);
3562 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3563
3564 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3565 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3566 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3567 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3568
3569 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3570 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
3571
3572 IEM_MC_ADVANCE_RIP();
3573 IEM_MC_END();
3574 }
3575 return VINF_SUCCESS;
3576
3577}
3578/* Opcode VEX.F2.0F 0x7e - invalid */
3579
3580
3581/* Opcode VEX.0F 0x7f - invalid */
3582
3583/**
3584 * @opcode 0x7f
3585 * @oppfx 0x66
3586 * @opcpuid avx
3587 * @opgroup og_avx_simdint_datamove
3588 * @opxcpttype 1
3589 * @optest op1=1 op2=2 -> op1=2
3590 * @optest op1=0 op2=-42 -> op1=-42
3591 */
3592FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
3593{
3594 IEMOP_MNEMONIC2(VEX_MR, VMOVDQA, vmovdqa, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3595 Assert(pVCpu->iem.s.uVexLength <= 1);
3596 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3597 if (IEM_IS_MODRM_REG_MODE(bRm))
3598 {
3599 /*
3600 * Register, register.
3601 */
3602 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3603 IEM_MC_BEGIN(0, 0);
3604
3605 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3606 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3607 if (pVCpu->iem.s.uVexLength == 0)
3608 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
3609 IEM_GET_MODRM_REG(pVCpu, bRm));
3610 else
3611 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
3612 IEM_GET_MODRM_REG(pVCpu, bRm));
3613 IEM_MC_ADVANCE_RIP();
3614 IEM_MC_END();
3615 }
3616 else if (pVCpu->iem.s.uVexLength == 0)
3617 {
3618 /*
3619 * Register, memory128.
3620 */
3621 IEM_MC_BEGIN(0, 2);
3622 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3623 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3624
3625 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3626 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3627 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3628 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3629
3630 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3631 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
3632
3633 IEM_MC_ADVANCE_RIP();
3634 IEM_MC_END();
3635 }
3636 else
3637 {
3638 /*
3639 * Register, memory256.
3640 */
3641 IEM_MC_BEGIN(0, 2);
3642 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3643 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3644
3645 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3646 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3647 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3648 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3649
3650 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3651 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
3652
3653 IEM_MC_ADVANCE_RIP();
3654 IEM_MC_END();
3655 }
3656 return VINF_SUCCESS;
3657}
3658
3659/**
3660 * @opcode 0x7f
3661 * @oppfx 0xf3
3662 * @opcpuid avx
3663 * @opgroup og_avx_simdint_datamove
3664 * @opxcpttype 4UA
3665 * @optest op1=1 op2=2 -> op1=2
3666 * @optest op1=0 op2=-42 -> op1=-42
3667 */
3668FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
3669{
3670 IEMOP_MNEMONIC2(VEX_MR, VMOVDQU, vmovdqu, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3671 Assert(pVCpu->iem.s.uVexLength <= 1);
3672 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3673 if (IEM_IS_MODRM_REG_MODE(bRm))
3674 {
3675 /*
3676 * Register, register.
3677 */
3678 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3679 IEM_MC_BEGIN(0, 0);
3680
3681 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3682 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3683 if (pVCpu->iem.s.uVexLength == 0)
3684 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
3685 IEM_GET_MODRM_REG(pVCpu, bRm));
3686 else
3687 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
3688 IEM_GET_MODRM_REG(pVCpu, bRm));
3689 IEM_MC_ADVANCE_RIP();
3690 IEM_MC_END();
3691 }
3692 else if (pVCpu->iem.s.uVexLength == 0)
3693 {
3694 /*
3695 * Register, memory128.
3696 */
3697 IEM_MC_BEGIN(0, 2);
3698 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3699 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3700
3701 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3702 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3703 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3704 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3705
3706 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3707 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
3708
3709 IEM_MC_ADVANCE_RIP();
3710 IEM_MC_END();
3711 }
3712 else
3713 {
3714 /*
3715 * Register, memory256.
3716 */
3717 IEM_MC_BEGIN(0, 2);
3718 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3719 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3720
3721 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3722 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3723 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3724 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3725
3726 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3727 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
3728
3729 IEM_MC_ADVANCE_RIP();
3730 IEM_MC_END();
3731 }
3732 return VINF_SUCCESS;
3733}
3734
3735/* Opcode VEX.F2.0F 0x7f - invalid */
3736
3737
3738/* Opcode VEX.0F 0x80 - invalid */
3739/* Opcode VEX.0F 0x81 - invalid */
3740/* Opcode VEX.0F 0x82 - invalid */
3741/* Opcode VEX.0F 0x83 - invalid */
3742/* Opcode VEX.0F 0x84 - invalid */
3743/* Opcode VEX.0F 0x85 - invalid */
3744/* Opcode VEX.0F 0x86 - invalid */
3745/* Opcode VEX.0F 0x87 - invalid */
3746/* Opcode VEX.0F 0x88 - invalid */
3747/* Opcode VEX.0F 0x89 - invalid */
3748/* Opcode VEX.0F 0x8a - invalid */
3749/* Opcode VEX.0F 0x8b - invalid */
3750/* Opcode VEX.0F 0x8c - invalid */
3751/* Opcode VEX.0F 0x8d - invalid */
3752/* Opcode VEX.0F 0x8e - invalid */
3753/* Opcode VEX.0F 0x8f - invalid */
3754/* Opcode VEX.0F 0x90 - invalid */
3755/* Opcode VEX.0F 0x91 - invalid */
3756/* Opcode VEX.0F 0x92 - invalid */
3757/* Opcode VEX.0F 0x93 - invalid */
3758/* Opcode VEX.0F 0x94 - invalid */
3759/* Opcode VEX.0F 0x95 - invalid */
3760/* Opcode VEX.0F 0x96 - invalid */
3761/* Opcode VEX.0F 0x97 - invalid */
3762/* Opcode VEX.0F 0x98 - invalid */
3763/* Opcode VEX.0F 0x99 - invalid */
3764/* Opcode VEX.0F 0x9a - invalid */
3765/* Opcode VEX.0F 0x9b - invalid */
3766/* Opcode VEX.0F 0x9c - invalid */
3767/* Opcode VEX.0F 0x9d - invalid */
3768/* Opcode VEX.0F 0x9e - invalid */
3769/* Opcode VEX.0F 0x9f - invalid */
3770/* Opcode VEX.0F 0xa0 - invalid */
3771/* Opcode VEX.0F 0xa1 - invalid */
3772/* Opcode VEX.0F 0xa2 - invalid */
3773/* Opcode VEX.0F 0xa3 - invalid */
3774/* Opcode VEX.0F 0xa4 - invalid */
3775/* Opcode VEX.0F 0xa5 - invalid */
3776/* Opcode VEX.0F 0xa6 - invalid */
3777/* Opcode VEX.0F 0xa7 - invalid */
3778/* Opcode VEX.0F 0xa8 - invalid */
3779/* Opcode VEX.0F 0xa9 - invalid */
3780/* Opcode VEX.0F 0xaa - invalid */
3781/* Opcode VEX.0F 0xab - invalid */
3782/* Opcode VEX.0F 0xac - invalid */
3783/* Opcode VEX.0F 0xad - invalid */
3784
3785
3786/* Opcode VEX.0F 0xae mem/0 - invalid. */
3787/* Opcode VEX.0F 0xae mem/1 - invalid. */
3788
3789/**
3790 * @ opmaps grp15
3791 * @ opcode !11/2
3792 * @ oppfx none
3793 * @ opcpuid sse
3794 * @ opgroup og_sse_mxcsrsm
3795 * @ opxcpttype 5
3796 * @ optest op1=0 -> mxcsr=0
3797 * @ optest op1=0x2083 -> mxcsr=0x2083
3798 * @ optest op1=0xfffffffe -> value.xcpt=0xd
3799 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
3800 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
3801 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
3802 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
3803 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
3804 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
3805 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
3806 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
3807 */
3808FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
3809//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
3810//{
3811// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
3812// if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
3813// return IEMOP_RAISE_INVALID_OPCODE();
3814//
3815// IEM_MC_BEGIN(2, 0);
3816// IEM_MC_ARG(uint8_t, iEffSeg, 0);
3817// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
3818// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
3819// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3820// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3821// IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
3822// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
3823// IEM_MC_END();
3824// return VINF_SUCCESS;
3825//}
3826
3827
3828/**
3829 * @opmaps vexgrp15
3830 * @opcode !11/3
3831 * @oppfx none
3832 * @opcpuid avx
3833 * @opgroup og_avx_mxcsrsm
3834 * @opxcpttype 5
3835 * @optest mxcsr=0 -> op1=0
3836 * @optest mxcsr=0x2083 -> op1=0x2083
3837 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
3838 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
3839 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
3840 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
3841 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
3842 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
3843 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
3844 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
3845 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
3846 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
3847 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
3848 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
3849 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
3850 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
3851 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
3852 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
3853 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
3854 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
3855 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
3856 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
3857 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
3858 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
3859 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
3860 * -> value.xcpt=0x6
3861 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
3862 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
3863 * APMv4 rev 3.17 page 509.
3864 * @todo Test this instruction on AMD Ryzen.
3865 */
3866FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
3867{
3868 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
3869 IEM_MC_BEGIN(2, 0);
3870 IEM_MC_ARG(uint8_t, iEffSeg, 0);
3871 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
3872 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
3873 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3874 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3875 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
3876 IEM_MC_CALL_CIMPL_2(iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
3877 IEM_MC_END();
3878 return VINF_SUCCESS;
3879}
3880
3881/* Opcode VEX.0F 0xae mem/4 - invalid. */
3882/* Opcode VEX.0F 0xae mem/5 - invalid. */
3883/* Opcode VEX.0F 0xae mem/6 - invalid. */
3884/* Opcode VEX.0F 0xae mem/7 - invalid. */
3885
3886/* Opcode VEX.0F 0xae 11b/0 - invalid. */
3887/* Opcode VEX.0F 0xae 11b/1 - invalid. */
3888/* Opcode VEX.0F 0xae 11b/2 - invalid. */
3889/* Opcode VEX.0F 0xae 11b/3 - invalid. */
3890/* Opcode VEX.0F 0xae 11b/4 - invalid. */
3891/* Opcode VEX.0F 0xae 11b/5 - invalid. */
3892/* Opcode VEX.0F 0xae 11b/6 - invalid. */
3893/* Opcode VEX.0F 0xae 11b/7 - invalid. */
3894
3895/**
3896 * Vex group 15 jump table for memory variant.
3897 */
3898IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
3899{ /* pfx: none, 066h, 0f3h, 0f2h */
3900 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3901 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3902 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3903 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3904 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3905 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3906 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3907 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3908};
3909AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
3910
3911
3912/** Opcode vex. 0xae. */
3913FNIEMOP_DEF(iemOp_VGrp15)
3914{
3915 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3916 if (IEM_IS_MODRM_REG_MODE(bRm))
3917 /* register, register */
3918 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
3919
3920 /* memory, register */
3921 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3922 + pVCpu->iem.s.idxPrefix], bRm);
3923}
3924
3925
3926/* Opcode VEX.0F 0xaf - invalid. */
3927
3928/* Opcode VEX.0F 0xb0 - invalid. */
3929/* Opcode VEX.0F 0xb1 - invalid. */
3930/* Opcode VEX.0F 0xb2 - invalid. */
3931/* Opcode VEX.0F 0xb2 - invalid. */
3932/* Opcode VEX.0F 0xb3 - invalid. */
3933/* Opcode VEX.0F 0xb4 - invalid. */
3934/* Opcode VEX.0F 0xb5 - invalid. */
3935/* Opcode VEX.0F 0xb6 - invalid. */
3936/* Opcode VEX.0F 0xb7 - invalid. */
3937/* Opcode VEX.0F 0xb8 - invalid. */
3938/* Opcode VEX.0F 0xb9 - invalid. */
3939/* Opcode VEX.0F 0xba - invalid. */
3940/* Opcode VEX.0F 0xbb - invalid. */
3941/* Opcode VEX.0F 0xbc - invalid. */
3942/* Opcode VEX.0F 0xbd - invalid. */
3943/* Opcode VEX.0F 0xbe - invalid. */
3944/* Opcode VEX.0F 0xbf - invalid. */
3945
3946/* Opcode VEX.0F 0xc0 - invalid. */
3947/* Opcode VEX.66.0F 0xc0 - invalid. */
3948/* Opcode VEX.F3.0F 0xc0 - invalid. */
3949/* Opcode VEX.F2.0F 0xc0 - invalid. */
3950
3951/* Opcode VEX.0F 0xc1 - invalid. */
3952/* Opcode VEX.66.0F 0xc1 - invalid. */
3953/* Opcode VEX.F3.0F 0xc1 - invalid. */
3954/* Opcode VEX.F2.0F 0xc1 - invalid. */
3955
3956/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
3957FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
3958/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
3959FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
3960/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
3961FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
3962/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
3963FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
3964
3965/* Opcode VEX.0F 0xc3 - invalid */
3966/* Opcode VEX.66.0F 0xc3 - invalid */
3967/* Opcode VEX.F3.0F 0xc3 - invalid */
3968/* Opcode VEX.F2.0F 0xc3 - invalid */
3969
3970/* Opcode VEX.0F 0xc4 - invalid */
3971/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
3972FNIEMOP_STUB(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib);
3973/* Opcode VEX.F3.0F 0xc4 - invalid */
3974/* Opcode VEX.F2.0F 0xc4 - invalid */
3975
3976/* Opcode VEX.0F 0xc5 - invlid */
3977/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
3978FNIEMOP_STUB(iemOp_vpextrw_Gd_Udq_Ib);
3979/* Opcode VEX.F3.0F 0xc5 - invalid */
3980/* Opcode VEX.F2.0F 0xc5 - invalid */
3981
3982
3983#define VSHUFP_X(a_Instr) \
3984 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
3985 if (IEM_IS_MODRM_REG_MODE(bRm)) \
3986 { \
3987 /* \
3988 * Register, register. \
3989 */ \
3990 if (pVCpu->iem.s.uVexLength) \
3991 { \
3992 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil); \
3993 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
3994 IEM_MC_BEGIN(4, 3); \
3995 IEM_MC_LOCAL(RTUINT256U, uDst); \
3996 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
3997 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
3998 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
3999 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4000 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4001 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3); \
4002 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4003 IEM_MC_PREPARE_AVX_USAGE(); \
4004 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4005 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4006 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4007 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bEvilArg); \
4008 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4009 IEM_MC_ADVANCE_RIP(); \
4010 IEM_MC_END(); \
4011 } \
4012 else \
4013 { \
4014 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil); \
4015 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4016 IEM_MC_BEGIN(4, 0); \
4017 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4018 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4019 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2); \
4020 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3); \
4021 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4022 IEM_MC_PREPARE_AVX_USAGE(); \
4023 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4024 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4025 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4026 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4027 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bEvilArg); \
4028 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4029 IEM_MC_ADVANCE_RIP(); \
4030 IEM_MC_END(); \
4031 } \
4032 } \
4033 else \
4034 { \
4035 /* \
4036 * Register, memory. \
4037 */ \
4038 if (pVCpu->iem.s.uVexLength) \
4039 { \
4040 IEM_MC_BEGIN(4, 4); \
4041 IEM_MC_LOCAL(RTUINT256U, uDst); \
4042 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4043 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4044 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4045 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4046 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4047 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4048 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
4049 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil); \
4050 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3); \
4051 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4052 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4053 IEM_MC_PREPARE_AVX_USAGE(); \
4054 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4055 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4056 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4057 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bEvilArg); \
4058 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4059 IEM_MC_ADVANCE_RIP(); \
4060 IEM_MC_END(); \
4061 } \
4062 else \
4063 { \
4064 IEM_MC_BEGIN(4, 2); \
4065 IEM_MC_LOCAL(RTUINT128U, uSrc2); \
4066 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4067 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4068 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4069 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); \
4070 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
4071 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil); \
4072 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3); \
4073 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4074 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4075 IEM_MC_PREPARE_AVX_USAGE(); \
4076 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4077 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4078 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4079 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4080 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bEvilArg); \
4081 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4082 IEM_MC_ADVANCE_RIP(); \
4083 IEM_MC_END(); \
4084 } \
4085 } \
4086 return VINF_SUCCESS;
4087
4088/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
4089FNIEMOP_DEF(iemOp_vshufps_Vps_Hps_Wps_Ib)
4090{
4091 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPS, vshufps, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4092 VSHUFP_X(vshufps);
4093}
4094
4095
4096/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
4097FNIEMOP_DEF(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib)
4098{
4099 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPD, vshufpd, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4100 VSHUFP_X(vshufpd);
4101}
4102#undef VSHUFP_X
4103
4104
4105/* Opcode VEX.F3.0F 0xc6 - invalid */
4106/* Opcode VEX.F2.0F 0xc6 - invalid */
4107
4108/* Opcode VEX.0F 0xc7 - invalid */
4109/* Opcode VEX.66.0F 0xc7 - invalid */
4110/* Opcode VEX.F3.0F 0xc7 - invalid */
4111/* Opcode VEX.F2.0F 0xc7 - invalid */
4112
4113/* Opcode VEX.0F 0xc8 - invalid */
4114/* Opcode VEX.0F 0xc9 - invalid */
4115/* Opcode VEX.0F 0xca - invalid */
4116/* Opcode VEX.0F 0xcb - invalid */
4117/* Opcode VEX.0F 0xcc - invalid */
4118/* Opcode VEX.0F 0xcd - invalid */
4119/* Opcode VEX.0F 0xce - invalid */
4120/* Opcode VEX.0F 0xcf - invalid */
4121
4122
4123/* Opcode VEX.0F 0xd0 - invalid */
4124/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
4125FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
4126/* Opcode VEX.F3.0F 0xd0 - invalid */
4127/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
4128FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
4129
4130/* Opcode VEX.0F 0xd1 - invalid */
4131/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
4132FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
4133/* Opcode VEX.F3.0F 0xd1 - invalid */
4134/* Opcode VEX.F2.0F 0xd1 - invalid */
4135
4136/* Opcode VEX.0F 0xd2 - invalid */
4137/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
4138FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
4139/* Opcode VEX.F3.0F 0xd2 - invalid */
4140/* Opcode VEX.F2.0F 0xd2 - invalid */
4141
4142/* Opcode VEX.0F 0xd3 - invalid */
4143/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
4144FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
4145/* Opcode VEX.F3.0F 0xd3 - invalid */
4146/* Opcode VEX.F2.0F 0xd3 - invalid */
4147
4148/* Opcode VEX.0F 0xd4 - invalid */
4149
4150
4151/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
4152FNIEMOP_DEF(iemOp_vpaddq_Vx_Hx_Wx)
4153{
4154 IEMOP_MNEMONIC3(VEX_RVM, VPADDQ, vpaddq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4155 IEMOPMEDIAF3_INIT_VARS( vpaddq);
4156 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4157}
4158
4159
4160/* Opcode VEX.F3.0F 0xd4 - invalid */
4161/* Opcode VEX.F2.0F 0xd4 - invalid */
4162
4163/* Opcode VEX.0F 0xd5 - invalid */
4164
4165
4166/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
4167FNIEMOP_DEF(iemOp_vpmullw_Vx_Hx_Wx)
4168{
4169 IEMOP_MNEMONIC3(VEX_RVM, VPMULLW, vpmullw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4170 IEMOPMEDIAOPTF3_INIT_VARS(vpmullw);
4171 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4172}
4173
4174
4175/* Opcode VEX.F3.0F 0xd5 - invalid */
4176/* Opcode VEX.F2.0F 0xd5 - invalid */
4177
4178/* Opcode VEX.0F 0xd6 - invalid */
4179
4180/**
4181 * @opcode 0xd6
4182 * @oppfx 0x66
4183 * @opcpuid avx
4184 * @opgroup og_avx_pcksclr_datamove
4185 * @opxcpttype none
4186 * @optest op1=-1 op2=2 -> op1=2
4187 * @optest op1=0 op2=-42 -> op1=-42
4188 */
4189FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
4190{
4191 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4192 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4193 if (IEM_IS_MODRM_REG_MODE(bRm))
4194 {
4195 /*
4196 * Register, register.
4197 */
4198 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
4199 IEM_MC_BEGIN(0, 0);
4200
4201 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4202 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4203
4204 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4205 IEM_GET_MODRM_REG(pVCpu, bRm));
4206 IEM_MC_ADVANCE_RIP();
4207 IEM_MC_END();
4208 }
4209 else
4210 {
4211 /*
4212 * Memory, register.
4213 */
4214 IEM_MC_BEGIN(0, 2);
4215 IEM_MC_LOCAL(uint64_t, uSrc);
4216 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4217
4218 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4219 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
4220 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4221 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4222
4223 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4224 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4225
4226 IEM_MC_ADVANCE_RIP();
4227 IEM_MC_END();
4228 }
4229 return VINF_SUCCESS;
4230}
4231
4232/* Opcode VEX.F3.0F 0xd6 - invalid */
4233/* Opcode VEX.F2.0F 0xd6 - invalid */
4234
4235
4236/* Opcode VEX.0F 0xd7 - invalid */
4237
4238/** Opcode VEX.66.0F 0xd7 - */
4239FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
4240{
4241 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4242 /* Docs says register only. */
4243 if (IEM_IS_MODRM_REG_MODE(bRm)) /** @todo test that this is registers only. */
4244 {
4245 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
4246 IEMOP_MNEMONIC2(RM_REG, VPMOVMSKB, vpmovmskb, Gd, Ux, DISOPTYPE_SSE | DISOPTYPE_HARMLESS, 0);
4247 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4248 if (pVCpu->iem.s.uVexLength)
4249 {
4250 IEM_MC_BEGIN(2, 1);
4251 IEM_MC_ARG(uint64_t *, puDst, 0);
4252 IEM_MC_LOCAL(RTUINT256U, uSrc);
4253 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
4254 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
4255 IEM_MC_PREPARE_AVX_USAGE();
4256 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4257 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4258 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpmovmskb_u256,
4259 iemAImpl_vpmovmskb_u256_fallback), puDst, puSrc);
4260 IEM_MC_ADVANCE_RIP();
4261 IEM_MC_END();
4262 }
4263 else
4264 {
4265 IEM_MC_BEGIN(2, 0);
4266 IEM_MC_ARG(uint64_t *, puDst, 0);
4267 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4268 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
4269 IEM_MC_PREPARE_AVX_USAGE();
4270 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4271 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4272 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc);
4273 IEM_MC_ADVANCE_RIP();
4274 IEM_MC_END();
4275 }
4276 return VINF_SUCCESS;
4277 }
4278 return IEMOP_RAISE_INVALID_OPCODE();
4279}
4280
4281
4282/* Opcode VEX.F3.0F 0xd7 - invalid */
4283/* Opcode VEX.F2.0F 0xd7 - invalid */
4284
4285
4286/* Opcode VEX.0F 0xd8 - invalid */
4287/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, W */
4288FNIEMOP_STUB(iemOp_vpsubusb_Vx_Hx_W);
4289/* Opcode VEX.F3.0F 0xd8 - invalid */
4290/* Opcode VEX.F2.0F 0xd8 - invalid */
4291
4292/* Opcode VEX.0F 0xd9 - invalid */
4293/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
4294FNIEMOP_STUB(iemOp_vpsubusw_Vx_Hx_Wx);
4295/* Opcode VEX.F3.0F 0xd9 - invalid */
4296/* Opcode VEX.F2.0F 0xd9 - invalid */
4297
4298/* Opcode VEX.0F 0xda - invalid */
4299
4300
4301/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
4302FNIEMOP_DEF(iemOp_vpminub_Vx_Hx_Wx)
4303{
4304 IEMOP_MNEMONIC3(VEX_RVM, VPMINUB, vpminub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4305 IEMOPMEDIAF3_INIT_VARS(vpminub);
4306 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4307}
4308
4309
4310/* Opcode VEX.F3.0F 0xda - invalid */
4311/* Opcode VEX.F2.0F 0xda - invalid */
4312
4313/* Opcode VEX.0F 0xdb - invalid */
4314
4315
4316/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, Wx */
4317FNIEMOP_DEF(iemOp_vpand_Vx_Hx_Wx)
4318{
4319 IEMOP_MNEMONIC3(VEX_RVM, VPAND, vpand, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4320 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4321 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
4322}
4323
4324
4325/* Opcode VEX.F3.0F 0xdb - invalid */
4326/* Opcode VEX.F2.0F 0xdb - invalid */
4327
4328/* Opcode VEX.0F 0xdc - invalid */
4329/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
4330FNIEMOP_STUB(iemOp_vpaddusb_Vx_Hx_Wx);
4331/* Opcode VEX.F3.0F 0xdc - invalid */
4332/* Opcode VEX.F2.0F 0xdc - invalid */
4333
4334/* Opcode VEX.0F 0xdd - invalid */
4335/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
4336FNIEMOP_STUB(iemOp_vpaddusw_Vx_Hx_Wx);
4337/* Opcode VEX.F3.0F 0xdd - invalid */
4338/* Opcode VEX.F2.0F 0xdd - invalid */
4339
4340/* Opcode VEX.0F 0xde - invalid */
4341
4342
4343/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, Wx */
4344FNIEMOP_DEF(iemOp_vpmaxub_Vx_Hx_Wx)
4345{
4346 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUB, vpmaxub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4347 IEMOPMEDIAF3_INIT_VARS(vpmaxub);
4348 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4349}
4350
4351
4352/* Opcode VEX.F3.0F 0xde - invalid */
4353/* Opcode VEX.F2.0F 0xde - invalid */
4354
4355/* Opcode VEX.0F 0xdf - invalid */
4356
4357
4358/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
4359FNIEMOP_DEF(iemOp_vpandn_Vx_Hx_Wx)
4360{
4361 IEMOP_MNEMONIC3(VEX_RVM, VPANDN, vpandn, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4362 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4363 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
4364}
4365
4366
4367/* Opcode VEX.F3.0F 0xdf - invalid */
4368/* Opcode VEX.F2.0F 0xdf - invalid */
4369
4370/* Opcode VEX.0F 0xe0 - invalid */
4371
4372
4373/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
4374FNIEMOP_DEF(iemOp_vpavgb_Vx_Hx_Wx)
4375{
4376 IEMOP_MNEMONIC3(VEX_RVM, VPAVGB, vpavgb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4377 IEMOPMEDIAOPTF3_INIT_VARS(vpavgb);
4378 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4379}
4380
4381
4382/* Opcode VEX.F3.0F 0xe0 - invalid */
4383/* Opcode VEX.F2.0F 0xe0 - invalid */
4384
4385/* Opcode VEX.0F 0xe1 - invalid */
4386/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
4387FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W);
4388/* Opcode VEX.F3.0F 0xe1 - invalid */
4389/* Opcode VEX.F2.0F 0xe1 - invalid */
4390
4391/* Opcode VEX.0F 0xe2 - invalid */
4392/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
4393FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx);
4394/* Opcode VEX.F3.0F 0xe2 - invalid */
4395/* Opcode VEX.F2.0F 0xe2 - invalid */
4396
4397/* Opcode VEX.0F 0xe3 - invalid */
4398
4399
4400/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
4401FNIEMOP_DEF(iemOp_vpavgw_Vx_Hx_Wx)
4402{
4403 IEMOP_MNEMONIC3(VEX_RVM, VPAVGW, vpavgw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4404 IEMOPMEDIAOPTF3_INIT_VARS(vpavgw);
4405 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4406}
4407
4408
4409/* Opcode VEX.F3.0F 0xe3 - invalid */
4410/* Opcode VEX.F2.0F 0xe3 - invalid */
4411
4412/* Opcode VEX.0F 0xe4 - invalid */
4413
4414
4415/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, Wx */
4416FNIEMOP_DEF(iemOp_vpmulhuw_Vx_Hx_Wx)
4417{
4418 IEMOP_MNEMONIC3(VEX_RVM, VPMULHUW, vpmulhuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4419 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhuw);
4420 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4421}
4422
4423
4424/* Opcode VEX.F3.0F 0xe4 - invalid */
4425/* Opcode VEX.F2.0F 0xe4 - invalid */
4426
4427/* Opcode VEX.0F 0xe5 - invalid */
4428
4429
4430/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
4431FNIEMOP_DEF(iemOp_vpmulhw_Vx_Hx_Wx)
4432{
4433 IEMOP_MNEMONIC3(VEX_RVM, VPMULHW, vpmulhw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4434 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhw);
4435 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4436}
4437
4438
4439/* Opcode VEX.F3.0F 0xe5 - invalid */
4440/* Opcode VEX.F2.0F 0xe5 - invalid */
4441
4442/* Opcode VEX.0F 0xe6 - invalid */
4443/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
4444FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
4445/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
4446FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
4447/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
4448FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
4449
4450
4451/* Opcode VEX.0F 0xe7 - invalid */
4452
4453/**
4454 * @opcode 0xe7
4455 * @opcodesub !11 mr/reg
4456 * @oppfx 0x66
4457 * @opcpuid avx
4458 * @opgroup og_avx_cachect
4459 * @opxcpttype 1
4460 * @optest op1=-1 op2=2 -> op1=2
4461 * @optest op1=0 op2=-42 -> op1=-42
4462 */
4463FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
4464{
4465 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4466 Assert(pVCpu->iem.s.uVexLength <= 1);
4467 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4468 if (IEM_IS_MODRM_MEM_MODE(bRm))
4469 {
4470 if (pVCpu->iem.s.uVexLength == 0)
4471 {
4472 /*
4473 * 128-bit: Memory, register.
4474 */
4475 IEM_MC_BEGIN(0, 2);
4476 IEM_MC_LOCAL(RTUINT128U, uSrc);
4477 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4478
4479 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4480 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4481 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4482 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4483
4484 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4485 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4486
4487 IEM_MC_ADVANCE_RIP();
4488 IEM_MC_END();
4489 }
4490 else
4491 {
4492 /*
4493 * 256-bit: Memory, register.
4494 */
4495 IEM_MC_BEGIN(0, 2);
4496 IEM_MC_LOCAL(RTUINT256U, uSrc);
4497 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4498
4499 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4500 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4501 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4502 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4503
4504 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4505 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4506
4507 IEM_MC_ADVANCE_RIP();
4508 IEM_MC_END();
4509 }
4510 return VINF_SUCCESS;
4511 }
4512 /**
4513 * @opdone
4514 * @opmnemonic udvex660fe7reg
4515 * @opcode 0xe7
4516 * @opcodesub 11 mr/reg
4517 * @oppfx 0x66
4518 * @opunused immediate
4519 * @opcpuid avx
4520 * @optest ->
4521 */
4522 return IEMOP_RAISE_INVALID_OPCODE();
4523}
4524
4525/* Opcode VEX.F3.0F 0xe7 - invalid */
4526/* Opcode VEX.F2.0F 0xe7 - invalid */
4527
4528
4529/* Opcode VEX.0F 0xe8 - invalid */
4530/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, W */
4531FNIEMOP_STUB(iemOp_vpsubsb_Vx_Hx_W);
4532/* Opcode VEX.F3.0F 0xe8 - invalid */
4533/* Opcode VEX.F2.0F 0xe8 - invalid */
4534
4535/* Opcode VEX.0F 0xe9 - invalid */
4536/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
4537FNIEMOP_STUB(iemOp_vpsubsw_Vx_Hx_Wx);
4538/* Opcode VEX.F3.0F 0xe9 - invalid */
4539/* Opcode VEX.F2.0F 0xe9 - invalid */
4540
4541/* Opcode VEX.0F 0xea - invalid */
4542
4543
4544/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
4545FNIEMOP_DEF(iemOp_vpminsw_Vx_Hx_Wx)
4546{
4547 IEMOP_MNEMONIC3(VEX_RVM, VPMINSW, vpminsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4548 IEMOPMEDIAF3_INIT_VARS(vpminsw);
4549 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4550}
4551
4552
4553/* Opcode VEX.F3.0F 0xea - invalid */
4554/* Opcode VEX.F2.0F 0xea - invalid */
4555
4556/* Opcode VEX.0F 0xeb - invalid */
4557
4558
4559/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, Wx */
4560FNIEMOP_DEF(iemOp_vpor_Vx_Hx_Wx)
4561{
4562 IEMOP_MNEMONIC3(VEX_RVM, VPOR, vpor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4563 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4564 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
4565}
4566
4567
4568
4569/* Opcode VEX.F3.0F 0xeb - invalid */
4570/* Opcode VEX.F2.0F 0xeb - invalid */
4571
4572/* Opcode VEX.0F 0xec - invalid */
4573/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
4574FNIEMOP_STUB(iemOp_vpaddsb_Vx_Hx_Wx);
4575/* Opcode VEX.F3.0F 0xec - invalid */
4576/* Opcode VEX.F2.0F 0xec - invalid */
4577
4578/* Opcode VEX.0F 0xed - invalid */
4579/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
4580FNIEMOP_STUB(iemOp_vpaddsw_Vx_Hx_Wx);
4581/* Opcode VEX.F3.0F 0xed - invalid */
4582/* Opcode VEX.F2.0F 0xed - invalid */
4583
4584/* Opcode VEX.0F 0xee - invalid */
4585
4586
4587/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, Wx */
4588FNIEMOP_DEF(iemOp_vpmaxsw_Vx_Hx_Wx)
4589{
4590 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSW, vpmaxsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4591 IEMOPMEDIAF3_INIT_VARS(vpmaxsw);
4592 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4593}
4594
4595
4596/* Opcode VEX.F3.0F 0xee - invalid */
4597/* Opcode VEX.F2.0F 0xee - invalid */
4598
4599
4600/* Opcode VEX.0F 0xef - invalid */
4601
4602
4603/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
4604FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
4605{
4606 IEMOP_MNEMONIC3(VEX_RVM, VPXOR, vpxor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4607 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4608 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
4609}
4610
4611
4612/* Opcode VEX.F3.0F 0xef - invalid */
4613/* Opcode VEX.F2.0F 0xef - invalid */
4614
4615/* Opcode VEX.0F 0xf0 - invalid */
4616/* Opcode VEX.66.0F 0xf0 - invalid */
4617
4618
4619/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
4620FNIEMOP_DEF(iemOp_vlddqu_Vx_Mx)
4621{
4622 IEMOP_MNEMONIC2(VEX_RM_MEM, VLDDQU, vlddqu, Vx_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4623 Assert(pVCpu->iem.s.uVexLength <= 1);
4624 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4625 if (IEM_IS_MODRM_REG_MODE(bRm))
4626 {
4627 /*
4628 * Register, register - (not implemented, assuming it raises \#UD).
4629 */
4630 return IEMOP_RAISE_INVALID_OPCODE();
4631 }
4632 else if (pVCpu->iem.s.uVexLength == 0)
4633 {
4634 /*
4635 * Register, memory128.
4636 */
4637 IEM_MC_BEGIN(0, 2);
4638 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4639 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4640
4641 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4642 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4643 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4644 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4645
4646 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4647 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
4648
4649 IEM_MC_ADVANCE_RIP();
4650 IEM_MC_END();
4651 }
4652 else
4653 {
4654 /*
4655 * Register, memory256.
4656 */
4657 IEM_MC_BEGIN(0, 2);
4658 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4659 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4660
4661 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4662 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4663 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4664 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4665
4666 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4667 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
4668
4669 IEM_MC_ADVANCE_RIP();
4670 IEM_MC_END();
4671 }
4672 return VINF_SUCCESS;
4673}
4674
4675
4676/* Opcode VEX.0F 0xf1 - invalid */
4677/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
4678FNIEMOP_STUB(iemOp_vpsllw_Vx_Hx_W);
4679/* Opcode VEX.F2.0F 0xf1 - invalid */
4680
4681/* Opcode VEX.0F 0xf2 - invalid */
4682/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
4683FNIEMOP_STUB(iemOp_vpslld_Vx_Hx_Wx);
4684/* Opcode VEX.F2.0F 0xf2 - invalid */
4685
4686/* Opcode VEX.0F 0xf3 - invalid */
4687/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
4688FNIEMOP_STUB(iemOp_vpsllq_Vx_Hx_Wx);
4689/* Opcode VEX.F2.0F 0xf3 - invalid */
4690
4691/* Opcode VEX.0F 0xf4 - invalid */
4692
4693
4694/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
4695FNIEMOP_DEF(iemOp_vpmuludq_Vx_Hx_W)
4696{
4697 IEMOP_MNEMONIC3(VEX_RVM, VPMULUDQ, vpmuludq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4698 IEMOPMEDIAOPTF3_INIT_VARS(vpmuludq);
4699 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4700}
4701
4702
4703/* Opcode VEX.F2.0F 0xf4 - invalid */
4704
4705/* Opcode VEX.0F 0xf5 - invalid */
4706/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
4707FNIEMOP_STUB(iemOp_vpmaddwd_Vx_Hx_Wx);
4708/* Opcode VEX.F2.0F 0xf5 - invalid */
4709
4710/* Opcode VEX.0F 0xf6 - invalid */
4711
4712
4713/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
4714FNIEMOP_DEF(iemOp_vpsadbw_Vx_Hx_Wx)
4715{
4716 IEMOP_MNEMONIC3(VEX_RVM, VPSADBW, vpsadbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4717 IEMOPMEDIAOPTF3_INIT_VARS(vpsadbw);
4718 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4719}
4720
4721
4722/* Opcode VEX.F2.0F 0xf6 - invalid */
4723
4724/* Opcode VEX.0F 0xf7 - invalid */
4725/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
4726FNIEMOP_STUB(iemOp_vmaskmovdqu_Vdq_Udq);
4727/* Opcode VEX.F2.0F 0xf7 - invalid */
4728
4729/* Opcode VEX.0F 0xf8 - invalid */
4730
4731
4732/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
4733FNIEMOP_DEF(iemOp_vpsubb_Vx_Hx_Wx)
4734{
4735 IEMOP_MNEMONIC3(VEX_RVM, VPSUBB, vpsubb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4736 IEMOPMEDIAF3_INIT_VARS( vpsubb);
4737 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4738}
4739
4740
4741/* Opcode VEX.F2.0F 0xf8 - invalid */
4742
4743/* Opcode VEX.0F 0xf9 - invalid */
4744
4745
4746/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
4747FNIEMOP_DEF(iemOp_vpsubw_Vx_Hx_Wx)
4748{
4749 IEMOP_MNEMONIC3(VEX_RVM, VPSUBW, vpsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4750 IEMOPMEDIAF3_INIT_VARS( vpsubw);
4751 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4752}
4753
4754
4755/* Opcode VEX.F2.0F 0xf9 - invalid */
4756
4757/* Opcode VEX.0F 0xfa - invalid */
4758
4759
4760/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
4761FNIEMOP_DEF(iemOp_vpsubd_Vx_Hx_Wx)
4762{
4763 IEMOP_MNEMONIC3(VEX_RVM, VPSUBD, vpsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4764 IEMOPMEDIAF3_INIT_VARS( vpsubd);
4765 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4766}
4767
4768
4769/* Opcode VEX.F2.0F 0xfa - invalid */
4770
4771/* Opcode VEX.0F 0xfb - invalid */
4772
4773
4774/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
4775FNIEMOP_DEF(iemOp_vpsubq_Vx_Hx_Wx)
4776{
4777 IEMOP_MNEMONIC3(VEX_RVM, VPSUBQ, vpsubq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4778 IEMOPMEDIAF3_INIT_VARS( vpsubq);
4779 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4780}
4781
4782
4783/* Opcode VEX.F2.0F 0xfb - invalid */
4784
4785/* Opcode VEX.0F 0xfc - invalid */
4786
4787
4788/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
4789FNIEMOP_DEF(iemOp_vpaddb_Vx_Hx_Wx)
4790{
4791 IEMOP_MNEMONIC3(VEX_RVM, VPADDB, vpaddb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4792 IEMOPMEDIAF3_INIT_VARS( vpaddb);
4793 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4794}
4795
4796
4797/* Opcode VEX.F2.0F 0xfc - invalid */
4798
4799/* Opcode VEX.0F 0xfd - invalid */
4800
4801
4802/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
4803FNIEMOP_DEF(iemOp_vpaddw_Vx_Hx_Wx)
4804{
4805 IEMOP_MNEMONIC3(VEX_RVM, VPADDW, vpaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4806 IEMOPMEDIAF3_INIT_VARS( vpaddw);
4807 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4808}
4809
4810
4811/* Opcode VEX.F2.0F 0xfd - invalid */
4812
4813/* Opcode VEX.0F 0xfe - invalid */
4814
4815
4816/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
4817FNIEMOP_DEF(iemOp_vpaddd_Vx_Hx_Wx)
4818{
4819 IEMOP_MNEMONIC3(VEX_RVM, VPADDD, vpaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4820 IEMOPMEDIAF3_INIT_VARS( vpaddd);
4821 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4822}
4823
4824
4825/* Opcode VEX.F2.0F 0xfe - invalid */
4826
4827
4828/** Opcode **** 0x0f 0xff - UD0 */
4829FNIEMOP_DEF(iemOp_vud0)
4830{
4831 IEMOP_MNEMONIC(vud0, "vud0");
4832 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4833 {
4834 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
4835#ifndef TST_IEM_CHECK_MC
4836 RTGCPTR GCPtrEff;
4837 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
4838 if (rcStrict != VINF_SUCCESS)
4839 return rcStrict;
4840#endif
4841 IEMOP_HLP_DONE_DECODING();
4842 }
4843 return IEMOP_RAISE_INVALID_OPCODE();
4844}
4845
4846
4847
4848/**
4849 * VEX opcode map \#1.
4850 *
4851 * @sa g_apfnTwoByteMap
4852 */
4853IEM_STATIC const PFNIEMOP g_apfnVexMap1[] =
4854{
4855 /* no prefix, 066h prefix f3h prefix, f2h prefix */
4856 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
4857 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
4858 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
4859 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
4860 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
4861 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
4862 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
4863 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
4864 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
4865 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
4866 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
4867 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
4868 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
4869 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
4870 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
4871 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
4872
4873 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
4874 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
4875 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
4876 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4877 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4878 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4879 /* 0x16 */ iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpd_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
4880 /* 0x17 */ iemOp_vmovhps_Mq_Vq, iemOp_vmovhpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4881 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
4882 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
4883 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
4884 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
4885 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
4886 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
4887 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
4888 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
4889
4890 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
4891 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
4892 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
4893 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
4894 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
4895 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
4896 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
4897 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
4898 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4899 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4900 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
4901 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4902 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
4903 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
4904 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4905 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4906
4907 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
4908 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
4909 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
4910 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
4911 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
4912 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
4913 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
4914 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
4915 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
4916 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
4917 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
4918 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
4919 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
4920 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
4921 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
4922 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
4923
4924 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
4925 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
4926 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
4927 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
4928 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
4929 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
4930 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
4931 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
4932 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
4933 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
4934 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
4935 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
4936 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
4937 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
4938 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
4939 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
4940
4941 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4942 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
4943 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
4944 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
4945 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4946 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4947 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4948 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4949 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
4950 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
4951 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
4952 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
4953 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
4954 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
4955 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
4956 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
4957
4958 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4959 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4960 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4961 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4962 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4963 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4964 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4965 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4966 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4967 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4968 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4969 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4970 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4971 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4972 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4973 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
4974
4975 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
4976 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4977 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4978 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4979 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4980 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4981 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4982 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
4983 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
4984 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
4985 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
4986 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
4987 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
4988 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
4989 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
4990 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
4991
4992 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
4993 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
4994 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
4995 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
4996 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
4997 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
4998 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
4999 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
5000 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
5001 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
5002 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
5003 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
5004 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
5005 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
5006 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
5007 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
5008
5009 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
5010 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
5011 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
5012 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
5013 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
5014 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
5015 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
5016 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
5017 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
5018 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
5019 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
5020 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
5021 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
5022 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
5023 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
5024 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
5025
5026 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5027 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5028 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5029 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5030 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
5031 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
5032 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
5033 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5034 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5035 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5036 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
5037 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
5038 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
5039 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
5040 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
5041 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
5042
5043 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5044 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5045 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5046 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5047 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
5048 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
5049 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
5050 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5051 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5052 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5053 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
5054 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
5055 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
5056 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
5057 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
5058 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
5059
5060 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5061 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5062 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
5063 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5064 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
5065 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
5066 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
5067 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5068 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5069 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5070 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
5071 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
5072 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
5073 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
5074 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
5075 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
5076
5077 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
5078 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5079 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5080 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5081 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5082 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5083 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5084 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5085 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5086 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5087 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5088 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5089 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5090 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5091 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5092 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5093
5094 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5095 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5096 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5097 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5098 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5099 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5100 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
5101 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5102 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5103 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5104 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5105 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5106 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5107 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5108 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5109 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5110
5111 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
5112 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5113 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5114 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5115 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5116 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5117 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5118 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5119 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5120 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5121 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5122 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5123 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5124 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5125 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5126 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
5127};
5128AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
5129/** @} */
5130
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