IEMAllInstructionsThree0f38.cpp.h@ 95453

Last change on this file since 95453 was 95453, checked in by vboxsync, 2 years ago
VMM/IEM: [v]pcmpeqq and [v]pcmpgtq. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 46.6 KB

Line
1	/* $Id: IEMAllInstructionsThree0f38.cpp.h 95453 2022-06-30 09:43:46Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsVexMap2.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name Three byte opcodes with first two bytes 0x0f 0x38
23	* @{
24	*/
25
26	/* Opcode 0x0f 0x38 0x00. */
27	FNIEMOP_STUB(iemOp_pshufb_Pq_Qq);
28	/* Opcode 0x66 0x0f 0x38 0x00. */
29	FNIEMOP_STUB(iemOp_pshufb_Vx_Wx);
30	/* Opcode 0x0f 0x38 0x01. */
31	FNIEMOP_STUB(iemOp_phaddw_Pq_Qq);
32	/** Opcode 0x66 0x0f 0x38 0x01. */
33	FNIEMOP_STUB(iemOp_phaddw_Vx_Wx);
34	/** Opcode 0x0f 0x38 0x02. */
35	FNIEMOP_STUB(iemOp_phaddd_Pq_Qq);
36	/** Opcode 0x66 0x0f 0x38 0x02. */
37	FNIEMOP_STUB(iemOp_phaddd_Vx_Wx);
38	/** Opcode 0x0f 0x38 0x03. */
39	FNIEMOP_STUB(iemOp_phaddsw_Pq_Qq);
40	/** Opcode 0x66 0x0f 0x38 0x03. */
41	FNIEMOP_STUB(iemOp_phaddsw_Vx_Wx);
42	/** Opcode 0x0f 0x38 0x04. */
43	FNIEMOP_STUB(iemOp_pmaddubsw_Pq_Qq);
44	/** Opcode 0x66 0x0f 0x38 0x04. */
45	FNIEMOP_STUB(iemOp_pmaddubsw_Vx_Wx);
46	/** Opcode 0x0f 0x38 0x05. */
47	FNIEMOP_STUB(iemOp_phsubw_Pq_Qq);
48	/** Opcode 0x66 0x0f 0x38 0x05. */
49	FNIEMOP_STUB(iemOp_phsubw_Vx_Wx);
50	/** Opcode 0x0f 0x38 0x06. */
51	FNIEMOP_STUB(iemOp_phsubd_Pq_Qq);
52	/** Opcode 0x66 0x0f 0x38 0x06. */
53	FNIEMOP_STUB(iemOp_phsubdq_Vx_Wx);
54	/** Opcode 0x0f 0x38 0x07. */
55	FNIEMOP_STUB(iemOp_phsubsw_Pq_Qq);
56	/** Opcode 0x66 0x0f 0x38 0x07. */
57	FNIEMOP_STUB(iemOp_phsubsw_Vx_Wx);
58	/** Opcode 0x0f 0x38 0x08. */
59	FNIEMOP_STUB(iemOp_psignb_Pq_Qq);
60	/** Opcode 0x66 0x0f 0x38 0x08. */
61	FNIEMOP_STUB(iemOp_psignb_Vx_Wx);
62	/** Opcode 0x0f 0x38 0x09. */
63	FNIEMOP_STUB(iemOp_psignw_Pq_Qq);
64	/** Opcode 0x66 0x0f 0x38 0x09. */
65	FNIEMOP_STUB(iemOp_psignw_Vx_Wx);
66	/** Opcode 0x0f 0x38 0x0a. */
67	FNIEMOP_STUB(iemOp_psignd_Pq_Qq);
68	/** Opcode 0x66 0x0f 0x38 0x0a. */
69	FNIEMOP_STUB(iemOp_psignd_Vx_Wx);
70	/** Opcode 0x0f 0x38 0x0b. */
71	FNIEMOP_STUB(iemOp_pmulhrsw_Pq_Qq);
72	/** Opcode 0x66 0x0f 0x38 0x0b. */
73	FNIEMOP_STUB(iemOp_pmulhrsw_Vx_Wx);
74	/* Opcode 0x0f 0x38 0x0c - invalid. */
75	/* Opcode 0x66 0x0f 0x38 0x0c - invalid (vex only). */
76	/* Opcode 0x0f 0x38 0x0d - invalid. */
77	/* Opcode 0x66 0x0f 0x38 0x0d - invalid (vex only). */
78	/* Opcode 0x0f 0x38 0x0e - invalid. */
79	/* Opcode 0x66 0x0f 0x38 0x0e - invalid (vex only). */
80	/* Opcode 0x0f 0x38 0x0f - invalid. */
81	/* Opcode 0x66 0x0f 0x38 0x0f - invalid (vex only). */
82
83
84	/* Opcode 0x0f 0x38 0x10 - invalid */
85	/** Opcode 0x66 0x0f 0x38 0x10 (legacy only). */
86	FNIEMOP_STUB(iemOp_pblendvb_Vdq_Wdq);
87	/* Opcode 0x0f 0x38 0x11 - invalid */
88	/* Opcode 0x66 0x0f 0x38 0x11 - invalid */
89	/* Opcode 0x0f 0x38 0x12 - invalid */
90	/* Opcode 0x66 0x0f 0x38 0x12 - invalid */
91	/* Opcode 0x0f 0x38 0x13 - invalid */
92	/* Opcode 0x66 0x0f 0x38 0x13 - invalid (vex only). */
93	/* Opcode 0x0f 0x38 0x14 - invalid */
94	/** Opcode 0x66 0x0f 0x38 0x14 (legacy only). */
95	FNIEMOP_STUB(iemOp_blendvps_Vdq_Wdq);
96	/* Opcode 0x0f 0x38 0x15 - invalid */
97	/** Opcode 0x66 0x0f 0x38 0x15 (legacy only). */
98	FNIEMOP_STUB(iemOp_blendvpd_Vdq_Wdq);
99	/* Opcode 0x0f 0x38 0x16 - invalid */
100	/* Opcode 0x66 0x0f 0x38 0x16 - invalid (vex only). */
101	/* Opcode 0x0f 0x38 0x17 - invalid */
102	/** Opcode 0x66 0x0f 0x38 0x17 - invalid */
103	FNIEMOP_STUB(iemOp_ptest_Vx_Wx);
104	/* Opcode 0x0f 0x38 0x18 - invalid */
105	/* Opcode 0x66 0x0f 0x38 0x18 - invalid (vex only). */
106	/* Opcode 0x0f 0x38 0x19 - invalid */
107	/* Opcode 0x66 0x0f 0x38 0x19 - invalid (vex only). */
108	/* Opcode 0x0f 0x38 0x1a - invalid */
109	/* Opcode 0x66 0x0f 0x38 0x1a - invalid (vex only). */
110	/* Opcode 0x0f 0x38 0x1b - invalid */
111	/* Opcode 0x66 0x0f 0x38 0x1b - invalid */
112	/** Opcode 0x0f 0x38 0x1c. */
113	FNIEMOP_STUB(iemOp_pabsb_Pq_Qq);
114	/** Opcode 0x66 0x0f 0x38 0x1c. */
115	FNIEMOP_STUB(iemOp_pabsb_Vx_Wx);
116	/** Opcode 0x0f 0x38 0x1d. */
117	FNIEMOP_STUB(iemOp_pabsw_Pq_Qq);
118	/** Opcode 0x66 0x0f 0x38 0x1d. */
119	FNIEMOP_STUB(iemOp_pabsw_Vx_Wx);
120	/** Opcode 0x0f 0x38 0x1e. */
121	FNIEMOP_STUB(iemOp_pabsd_Pq_Qq);
122	/** Opcode 0x66 0x0f 0x38 0x1e. */
123	FNIEMOP_STUB(iemOp_pabsd_Vx_Wx);
124	/* Opcode 0x0f 0x38 0x1f - invalid */
125	/* Opcode 0x66 0x0f 0x38 0x1f - invalid */
126
127
128	/** Opcode 0x66 0x0f 0x38 0x20. */
129	FNIEMOP_STUB(iemOp_pmovsxbw_Vx_UxMq);
130	/** Opcode 0x66 0x0f 0x38 0x21. */
131	FNIEMOP_STUB(iemOp_pmovsxbd_Vx_UxMd);
132	/** Opcode 0x66 0x0f 0x38 0x22. */
133	FNIEMOP_STUB(iemOp_pmovsxbq_Vx_UxMw);
134	/** Opcode 0x66 0x0f 0x38 0x23. */
135	FNIEMOP_STUB(iemOp_pmovsxwd_Vx_UxMq);
136	/** Opcode 0x66 0x0f 0x38 0x24. */
137	FNIEMOP_STUB(iemOp_pmovsxwq_Vx_UxMd);
138	/** Opcode 0x66 0x0f 0x38 0x25. */
139	FNIEMOP_STUB(iemOp_pmovsxdq_Vx_UxMq);
140	/* Opcode 0x66 0x0f 0x38 0x26 - invalid */
141	/* Opcode 0x66 0x0f 0x38 0x27 - invalid */
142	/** Opcode 0x66 0x0f 0x38 0x28. */
143	FNIEMOP_STUB(iemOp_pmuldq_Vx_Wx);
144
145	/**
146	* Common worker for SSE4.1 instructions on the forms:
147	* pxxx xmm1, xmm2/mem128
148	*
149	* Proper alignment of the 128-bit operand is enforced.
150	* Exceptions type 4. SSE2 cpuid checks.
151	*
152	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSse2_FullFull_To_Full
153	*/
154	FNIEMOP_DEF_1(iemOpCommonSse41_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
155	{
156	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
157	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
158	{
159	/*
160	* Register, register.
161	*/
162	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
163	IEM_MC_BEGIN(2, 0);
164	IEM_MC_ARG(PRTUINT128U, pDst, 0);
165	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
166	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
167	IEM_MC_PREPARE_SSE_USAGE();
168	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
169	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
170	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
171	IEM_MC_ADVANCE_RIP();
172	IEM_MC_END();
173	}
174	else
175	{
176	/*
177	* Register, memory.
178	*/
179	IEM_MC_BEGIN(2, 2);
180	IEM_MC_ARG(PRTUINT128U, pDst, 0);
181	IEM_MC_LOCAL(RTUINT128U, uSrc);
182	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
183	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
184
185	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
186	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
187	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
188	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
189
190	IEM_MC_PREPARE_SSE_USAGE();
191	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
192	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
193
194	IEM_MC_ADVANCE_RIP();
195	IEM_MC_END();
196	}
197	return VINF_SUCCESS;
198	}
199
200
201	/**
202	* Common worker for SSE4.2 instructions on the forms:
203	* pxxx xmm1, xmm2/mem128
204	*
205	* Proper alignment of the 128-bit operand is enforced.
206	* Exceptions type 4. SSE2 cpuid checks.
207	*
208	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSse41_FullFull_To_Full
209	*/
210	FNIEMOP_DEF_1(iemOpCommonSse42_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
211	{
212	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
213	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
214	{
215	/*
216	* Register, register.
217	*/
218	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
219	IEM_MC_BEGIN(2, 0);
220	IEM_MC_ARG(PRTUINT128U, pDst, 0);
221	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
222	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
223	IEM_MC_PREPARE_SSE_USAGE();
224	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
225	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
226	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
227	IEM_MC_ADVANCE_RIP();
228	IEM_MC_END();
229	}
230	else
231	{
232	/*
233	* Register, memory.
234	*/
235	IEM_MC_BEGIN(2, 2);
236	IEM_MC_ARG(PRTUINT128U, pDst, 0);
237	IEM_MC_LOCAL(RTUINT128U, uSrc);
238	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
239	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
240
241	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
242	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
243	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
244	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
245
246	IEM_MC_PREPARE_SSE_USAGE();
247	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
248	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
249
250	IEM_MC_ADVANCE_RIP();
251	IEM_MC_END();
252	}
253	return VINF_SUCCESS;
254	}
255
256
257	/** Opcode 0x66 0x0f 0x38 0x29. */
258	FNIEMOP_DEF(iemOp_pcmpeqq_Vx_Wx)
259	{
260	IEMOP_MNEMONIC2(RM, PCMPEQQ, pcmpeqq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
261	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
262	IEM_SELECT_HOST_OR_FALLBACK(fSse41, &g_iemAImpl_pcmpeqq, &g_iemAImpl_pcmpeqq_fallback));
263	}
264
265
266	/**
267	* @opcode 0x2a
268	* @opcodesub !11 mr/reg
269	* @oppfx 0x66
270	* @opcpuid sse4.1
271	* @opgroup og_sse41_cachect
272	* @opxcpttype 1
273	* @optest op1=-1 op2=2 -> op1=2
274	* @optest op1=0 op2=-42 -> op1=-42
275	*/
276	FNIEMOP_DEF(iemOp_movntdqa_Vdq_Mdq)
277	{
278	IEMOP_MNEMONIC2(RM_MEM, MOVNTDQA, movntdqa, Vdq_WO, Mdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
279	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
280	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
281	{
282	/* Register, memory. */
283	IEM_MC_BEGIN(0, 2);
284	IEM_MC_LOCAL(RTUINT128U, uSrc);
285	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
286
287	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
288	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
289	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
290	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
291
292	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
293	IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
294
295	IEM_MC_ADVANCE_RIP();
296	IEM_MC_END();
297	return VINF_SUCCESS;
298	}
299
300	/**
301	* @opdone
302	* @opmnemonic ud660f382areg
303	* @opcode 0x2a
304	* @opcodesub 11 mr/reg
305	* @oppfx 0x66
306	* @opunused immediate
307	* @opcpuid sse
308	* @optest ->
309	*/
310	return IEMOP_RAISE_INVALID_OPCODE();
311	}
312
313	/** Opcode 0x66 0x0f 0x38 0x2b. */
314	FNIEMOP_STUB(iemOp_packusdw_Vx_Wx);
315	/* Opcode 0x66 0x0f 0x38 0x2c - invalid (vex only). */
316	/* Opcode 0x66 0x0f 0x38 0x2d - invalid (vex only). */
317	/* Opcode 0x66 0x0f 0x38 0x2e - invalid (vex only). */
318	/* Opcode 0x66 0x0f 0x38 0x2f - invalid (vex only). */
319
320	/** Opcode 0x66 0x0f 0x38 0x30. */
321	FNIEMOP_STUB(iemOp_pmovzxbw_Vx_UxMq);
322	/** Opcode 0x66 0x0f 0x38 0x31. */
323	FNIEMOP_STUB(iemOp_pmovzxbd_Vx_UxMd);
324	/** Opcode 0x66 0x0f 0x38 0x32. */
325	FNIEMOP_STUB(iemOp_pmovzxbq_Vx_UxMw);
326	/** Opcode 0x66 0x0f 0x38 0x33. */
327	FNIEMOP_STUB(iemOp_pmovzxwd_Vx_UxMq);
328	/** Opcode 0x66 0x0f 0x38 0x34. */
329	FNIEMOP_STUB(iemOp_pmovzxwq_Vx_UxMd);
330	/** Opcode 0x66 0x0f 0x38 0x35. */
331	FNIEMOP_STUB(iemOp_pmovzxdq_Vx_UxMq);
332	/* Opcode 0x66 0x0f 0x38 0x36 - invalid (vex only). */
333
334
335	/** Opcode 0x66 0x0f 0x38 0x37. */
336	FNIEMOP_DEF(iemOp_pcmpgtq_Vx_Wx)
337	{
338	IEMOP_MNEMONIC2(RM, PCMPGTQ, pcmpgtq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
339	return FNIEMOP_CALL_1(iemOpCommonSse42_FullFull_To_Full,
340	IEM_SELECT_HOST_OR_FALLBACK(fSse42, &g_iemAImpl_pcmpgtq, &g_iemAImpl_pcmpgtq_fallback));
341	}
342
343
344	/** Opcode 0x66 0x0f 0x38 0x38. */
345	FNIEMOP_STUB(iemOp_pminsb_Vx_Wx);
346	/** Opcode 0x66 0x0f 0x38 0x39. */
347	FNIEMOP_STUB(iemOp_pminsd_Vx_Wx);
348	/** Opcode 0x66 0x0f 0x38 0x3a. */
349	FNIEMOP_STUB(iemOp_pminuw_Vx_Wx);
350	/** Opcode 0x66 0x0f 0x38 0x3b. */
351	FNIEMOP_STUB(iemOp_pminud_Vx_Wx);
352	/** Opcode 0x66 0x0f 0x38 0x3c. */
353	FNIEMOP_STUB(iemOp_pmaxsb_Vx_Wx);
354	/** Opcode 0x66 0x0f 0x38 0x3d. */
355	FNIEMOP_STUB(iemOp_pmaxsd_Vx_Wx);
356	/** Opcode 0x66 0x0f 0x38 0x3e. */
357	FNIEMOP_STUB(iemOp_pmaxuw_Vx_Wx);
358	/** Opcode 0x66 0x0f 0x38 0x3f. */
359	FNIEMOP_STUB(iemOp_pmaxud_Vx_Wx);
360
361
362	/** Opcode 0x66 0x0f 0x38 0x40. */
363	FNIEMOP_STUB(iemOp_pmulld_Vx_Wx);
364	/** Opcode 0x66 0x0f 0x38 0x41. */
365	FNIEMOP_STUB(iemOp_phminposuw_Vdq_Wdq);
366	/* Opcode 0x66 0x0f 0x38 0x42 - invalid. */
367	/* Opcode 0x66 0x0f 0x38 0x43 - invalid. */
368	/* Opcode 0x66 0x0f 0x38 0x44 - invalid. */
369	/* Opcode 0x66 0x0f 0x38 0x45 - invalid (vex only). */
370	/* Opcode 0x66 0x0f 0x38 0x46 - invalid (vex only). */
371	/* Opcode 0x66 0x0f 0x38 0x47 - invalid (vex only). */
372	/* Opcode 0x66 0x0f 0x38 0x48 - invalid. */
373	/* Opcode 0x66 0x0f 0x38 0x49 - invalid. */
374	/* Opcode 0x66 0x0f 0x38 0x4a - invalid. */
375	/* Opcode 0x66 0x0f 0x38 0x4b - invalid. */
376	/* Opcode 0x66 0x0f 0x38 0x4c - invalid. */
377	/* Opcode 0x66 0x0f 0x38 0x4d - invalid. */
378	/* Opcode 0x66 0x0f 0x38 0x4e - invalid. */
379	/* Opcode 0x66 0x0f 0x38 0x4f - invalid. */
380
381	/* Opcode 0x66 0x0f 0x38 0x50 - invalid. */
382	/* Opcode 0x66 0x0f 0x38 0x51 - invalid. */
383	/* Opcode 0x66 0x0f 0x38 0x52 - invalid. */
384	/* Opcode 0x66 0x0f 0x38 0x53 - invalid. */
385	/* Opcode 0x66 0x0f 0x38 0x54 - invalid. */
386	/* Opcode 0x66 0x0f 0x38 0x55 - invalid. */
387	/* Opcode 0x66 0x0f 0x38 0x56 - invalid. */
388	/* Opcode 0x66 0x0f 0x38 0x57 - invalid. */
389	/* Opcode 0x66 0x0f 0x38 0x58 - invalid (vex only). */
390	/* Opcode 0x66 0x0f 0x38 0x59 - invalid (vex only). */
391	/* Opcode 0x66 0x0f 0x38 0x5a - invalid (vex only). */
392	/* Opcode 0x66 0x0f 0x38 0x5b - invalid. */
393	/* Opcode 0x66 0x0f 0x38 0x5c - invalid. */
394	/* Opcode 0x66 0x0f 0x38 0x5d - invalid. */
395	/* Opcode 0x66 0x0f 0x38 0x5e - invalid. */
396	/* Opcode 0x66 0x0f 0x38 0x5f - invalid. */
397
398	/* Opcode 0x66 0x0f 0x38 0x60 - invalid. */
399	/* Opcode 0x66 0x0f 0x38 0x61 - invalid. */
400	/* Opcode 0x66 0x0f 0x38 0x62 - invalid. */
401	/* Opcode 0x66 0x0f 0x38 0x63 - invalid. */
402	/* Opcode 0x66 0x0f 0x38 0x64 - invalid. */
403	/* Opcode 0x66 0x0f 0x38 0x65 - invalid. */
404	/* Opcode 0x66 0x0f 0x38 0x66 - invalid. */
405	/* Opcode 0x66 0x0f 0x38 0x67 - invalid. */
406	/* Opcode 0x66 0x0f 0x38 0x68 - invalid. */
407	/* Opcode 0x66 0x0f 0x38 0x69 - invalid. */
408	/* Opcode 0x66 0x0f 0x38 0x6a - invalid. */
409	/* Opcode 0x66 0x0f 0x38 0x6b - invalid. */
410	/* Opcode 0x66 0x0f 0x38 0x6c - invalid. */
411	/* Opcode 0x66 0x0f 0x38 0x6d - invalid. */
412	/* Opcode 0x66 0x0f 0x38 0x6e - invalid. */
413	/* Opcode 0x66 0x0f 0x38 0x6f - invalid. */
414
415	/* Opcode 0x66 0x0f 0x38 0x70 - invalid. */
416	/* Opcode 0x66 0x0f 0x38 0x71 - invalid. */
417	/* Opcode 0x66 0x0f 0x38 0x72 - invalid. */
418	/* Opcode 0x66 0x0f 0x38 0x73 - invalid. */
419	/* Opcode 0x66 0x0f 0x38 0x74 - invalid. */
420	/* Opcode 0x66 0x0f 0x38 0x75 - invalid. */
421	/* Opcode 0x66 0x0f 0x38 0x76 - invalid. */
422	/* Opcode 0x66 0x0f 0x38 0x77 - invalid. */
423	/* Opcode 0x66 0x0f 0x38 0x78 - invalid (vex only). */
424	/* Opcode 0x66 0x0f 0x38 0x79 - invalid (vex only). */
425	/* Opcode 0x66 0x0f 0x38 0x7a - invalid. */
426	/* Opcode 0x66 0x0f 0x38 0x7b - invalid. */
427	/* Opcode 0x66 0x0f 0x38 0x7c - invalid. */
428	/* Opcode 0x66 0x0f 0x38 0x7d - invalid. */
429	/* Opcode 0x66 0x0f 0x38 0x7e - invalid. */
430	/* Opcode 0x66 0x0f 0x38 0x7f - invalid. */
431
432	/** Opcode 0x66 0x0f 0x38 0x80. */
433	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
434	FNIEMOP_DEF(iemOp_invept_Gy_Mdq)
435	{
436	IEMOP_MNEMONIC(invept, "invept Gy,Mdq");
437	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
438	IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
439	IEMOP_HLP_VMX_INSTR("invept", kVmxVDiag_Invept);
440	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
441	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
442	{
443	/* Register, memory. */
444	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
445	{
446	IEM_MC_BEGIN(3, 0);
447	IEM_MC_ARG(uint8_t, iEffSeg, 0);
448	IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
449	IEM_MC_ARG(uint64_t, uInveptType, 2);
450	IEM_MC_FETCH_GREG_U64(uInveptType, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
451	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
452	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
453	IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
454	IEM_MC_END();
455	}
456	else
457	{
458	IEM_MC_BEGIN(3, 0);
459	IEM_MC_ARG(uint8_t, iEffSeg, 0);
460	IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
461	IEM_MC_ARG(uint32_t, uInveptType, 2);
462	IEM_MC_FETCH_GREG_U32(uInveptType, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
463	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
464	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
465	IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
466	IEM_MC_END();
467	}
468	}
469	Log(("iemOp_invept_Gy_Mdq: invalid encoding -> #UD\n"));
470	return IEMOP_RAISE_INVALID_OPCODE();
471	}
472	#else
473	FNIEMOP_STUB(iemOp_invept_Gy_Mdq);
474	#endif
475
476	/** Opcode 0x66 0x0f 0x38 0x81. */
477	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
478	FNIEMOP_DEF(iemOp_invvpid_Gy_Mdq)
479	{
480	IEMOP_MNEMONIC(invvpid, "invvpid Gy,Mdq");
481	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
482	IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
483	IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
484	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
485	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
486	{
487	/* Register, memory. */
488	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
489	{
490	IEM_MC_BEGIN(3, 0);
491	IEM_MC_ARG(uint8_t, iEffSeg, 0);
492	IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
493	IEM_MC_ARG(uint64_t, uInvvpidType, 2);
494	IEM_MC_FETCH_GREG_U64(uInvvpidType, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
495	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
496	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
497	IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
498	IEM_MC_END();
499	}
500	else
501	{
502	IEM_MC_BEGIN(3, 0);
503	IEM_MC_ARG(uint8_t, iEffSeg, 0);
504	IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
505	IEM_MC_ARG(uint32_t, uInvvpidType, 2);
506	IEM_MC_FETCH_GREG_U32(uInvvpidType, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
507	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
508	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
509	IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
510	IEM_MC_END();
511	}
512	}
513	Log(("iemOp_invvpid_Gy_Mdq: invalid encoding -> #UD\n"));
514	return IEMOP_RAISE_INVALID_OPCODE();
515	}
516	#else
517	FNIEMOP_STUB(iemOp_invvpid_Gy_Mdq);
518	#endif
519
520	/** Opcode 0x66 0x0f 0x38 0x82. */
521	FNIEMOP_DEF(iemOp_invpcid_Gy_Mdq)
522	{
523	IEMOP_MNEMONIC(invpcid, "invpcid Gy,Mdq");
524	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
525	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
526	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
527	{
528	/* Register, memory. */
529	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
530	{
531	IEM_MC_BEGIN(3, 0);
532	IEM_MC_ARG(uint8_t, iEffSeg, 0);
533	IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
534	IEM_MC_ARG(uint64_t, uInvpcidType, 2);
535	IEM_MC_FETCH_GREG_U64(uInvpcidType, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
536	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
537	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
538	IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
539	IEM_MC_END();
540	}
541	else
542	{
543	IEM_MC_BEGIN(3, 0);
544	IEM_MC_ARG(uint8_t, iEffSeg, 0);
545	IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
546	IEM_MC_ARG(uint32_t, uInvpcidType, 2);
547	IEM_MC_FETCH_GREG_U32(uInvpcidType, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
548	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
549	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
550	IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
551	IEM_MC_END();
552	}
553	}
554	Log(("iemOp_invpcid_Gy_Mdq: invalid encoding -> #UD\n"));
555	return IEMOP_RAISE_INVALID_OPCODE();
556	}
557
558
559	/* Opcode 0x66 0x0f 0x38 0x83 - invalid. */
560	/* Opcode 0x66 0x0f 0x38 0x84 - invalid. */
561	/* Opcode 0x66 0x0f 0x38 0x85 - invalid. */
562	/* Opcode 0x66 0x0f 0x38 0x86 - invalid. */
563	/* Opcode 0x66 0x0f 0x38 0x87 - invalid. */
564	/* Opcode 0x66 0x0f 0x38 0x88 - invalid. */
565	/* Opcode 0x66 0x0f 0x38 0x89 - invalid. */
566	/* Opcode 0x66 0x0f 0x38 0x8a - invalid. */
567	/* Opcode 0x66 0x0f 0x38 0x8b - invalid. */
568	/* Opcode 0x66 0x0f 0x38 0x8c - invalid (vex only). */
569	/* Opcode 0x66 0x0f 0x38 0x8d - invalid. */
570	/* Opcode 0x66 0x0f 0x38 0x8e - invalid (vex only). */
571	/* Opcode 0x66 0x0f 0x38 0x8f - invalid. */
572
573	/* Opcode 0x66 0x0f 0x38 0x90 - invalid (vex only). */
574	/* Opcode 0x66 0x0f 0x38 0x91 - invalid (vex only). */
575	/* Opcode 0x66 0x0f 0x38 0x92 - invalid (vex only). */
576	/* Opcode 0x66 0x0f 0x38 0x93 - invalid (vex only). */
577	/* Opcode 0x66 0x0f 0x38 0x94 - invalid. */
578	/* Opcode 0x66 0x0f 0x38 0x95 - invalid. */
579	/* Opcode 0x66 0x0f 0x38 0x96 - invalid (vex only). */
580	/* Opcode 0x66 0x0f 0x38 0x97 - invalid (vex only). */
581	/* Opcode 0x66 0x0f 0x38 0x98 - invalid (vex only). */
582	/* Opcode 0x66 0x0f 0x38 0x99 - invalid (vex only). */
583	/* Opcode 0x66 0x0f 0x38 0x9a - invalid (vex only). */
584	/* Opcode 0x66 0x0f 0x38 0x9b - invalid (vex only). */
585	/* Opcode 0x66 0x0f 0x38 0x9c - invalid (vex only). */
586	/* Opcode 0x66 0x0f 0x38 0x9d - invalid (vex only). */
587	/* Opcode 0x66 0x0f 0x38 0x9e - invalid (vex only). */
588	/* Opcode 0x66 0x0f 0x38 0x9f - invalid (vex only). */
589
590	/* Opcode 0x66 0x0f 0x38 0xa0 - invalid. */
591	/* Opcode 0x66 0x0f 0x38 0xa1 - invalid. */
592	/* Opcode 0x66 0x0f 0x38 0xa2 - invalid. */
593	/* Opcode 0x66 0x0f 0x38 0xa3 - invalid. */
594	/* Opcode 0x66 0x0f 0x38 0xa4 - invalid. */
595	/* Opcode 0x66 0x0f 0x38 0xa5 - invalid. */
596	/* Opcode 0x66 0x0f 0x38 0xa6 - invalid (vex only). */
597	/* Opcode 0x66 0x0f 0x38 0xa7 - invalid (vex only). */
598	/* Opcode 0x66 0x0f 0x38 0xa8 - invalid (vex only). */
599	/* Opcode 0x66 0x0f 0x38 0xa9 - invalid (vex only). */
600	/* Opcode 0x66 0x0f 0x38 0xaa - invalid (vex only). */
601	/* Opcode 0x66 0x0f 0x38 0xab - invalid (vex only). */
602	/* Opcode 0x66 0x0f 0x38 0xac - invalid (vex only). */
603	/* Opcode 0x66 0x0f 0x38 0xad - invalid (vex only). */
604	/* Opcode 0x66 0x0f 0x38 0xae - invalid (vex only). */
605	/* Opcode 0x66 0x0f 0x38 0xaf - invalid (vex only). */
606
607	/* Opcode 0x66 0x0f 0x38 0xb0 - invalid. */
608	/* Opcode 0x66 0x0f 0x38 0xb1 - invalid. */
609	/* Opcode 0x66 0x0f 0x38 0xb2 - invalid. */
610	/* Opcode 0x66 0x0f 0x38 0xb3 - invalid. */
611	/* Opcode 0x66 0x0f 0x38 0xb4 - invalid. */
612	/* Opcode 0x66 0x0f 0x38 0xb5 - invalid. */
613	/* Opcode 0x66 0x0f 0x38 0xb6 - invalid (vex only). */
614	/* Opcode 0x66 0x0f 0x38 0xb7 - invalid (vex only). */
615	/* Opcode 0x66 0x0f 0x38 0xb8 - invalid (vex only). */
616	/* Opcode 0x66 0x0f 0x38 0xb9 - invalid (vex only). */
617	/* Opcode 0x66 0x0f 0x38 0xba - invalid (vex only). */
618	/* Opcode 0x66 0x0f 0x38 0xbb - invalid (vex only). */
619	/* Opcode 0x66 0x0f 0x38 0xbc - invalid (vex only). */
620	/* Opcode 0x66 0x0f 0x38 0xbd - invalid (vex only). */
621	/* Opcode 0x66 0x0f 0x38 0xbe - invalid (vex only). */
622	/* Opcode 0x66 0x0f 0x38 0xbf - invalid (vex only). */
623
624	/* Opcode 0x0f 0x38 0xc0 - invalid. */
625	/* Opcode 0x66 0x0f 0x38 0xc0 - invalid. */
626	/* Opcode 0x0f 0x38 0xc1 - invalid. */
627	/* Opcode 0x66 0x0f 0x38 0xc1 - invalid. */
628	/* Opcode 0x0f 0x38 0xc2 - invalid. */
629	/* Opcode 0x66 0x0f 0x38 0xc2 - invalid. */
630	/* Opcode 0x0f 0x38 0xc3 - invalid. */
631	/* Opcode 0x66 0x0f 0x38 0xc3 - invalid. */
632	/* Opcode 0x0f 0x38 0xc4 - invalid. */
633	/* Opcode 0x66 0x0f 0x38 0xc4 - invalid. */
634	/* Opcode 0x0f 0x38 0xc5 - invalid. */
635	/* Opcode 0x66 0x0f 0x38 0xc5 - invalid. */
636	/* Opcode 0x0f 0x38 0xc6 - invalid. */
637	/* Opcode 0x66 0x0f 0x38 0xc6 - invalid. */
638	/* Opcode 0x0f 0x38 0xc7 - invalid. */
639	/* Opcode 0x66 0x0f 0x38 0xc7 - invalid. */
640	/** Opcode 0x0f 0x38 0xc8. */
641	FNIEMOP_STUB(iemOp_sha1nexte_Vdq_Wdq);
642	/* Opcode 0x66 0x0f 0x38 0xc8 - invalid. */
643	/** Opcode 0x0f 0x38 0xc9. */
644	FNIEMOP_STUB(iemOp_sha1msg1_Vdq_Wdq);
645	/* Opcode 0x66 0x0f 0x38 0xc9 - invalid. */
646	/** Opcode 0x0f 0x38 0xca. */
647	FNIEMOP_STUB(iemOp_sha1msg2_Vdq_Wdq);
648	/* Opcode 0x66 0x0f 0x38 0xca - invalid. */
649	/** Opcode 0x0f 0x38 0xcb. */
650	FNIEMOP_STUB(iemOp_sha256rnds2_Vdq_Wdq);
651	/* Opcode 0x66 0x0f 0x38 0xcb - invalid. */
652	/** Opcode 0x0f 0x38 0xcc. */
653	FNIEMOP_STUB(iemOp_sha256msg1_Vdq_Wdq);
654	/* Opcode 0x66 0x0f 0x38 0xcc - invalid. */
655	/** Opcode 0x0f 0x38 0xcd. */
656	FNIEMOP_STUB(iemOp_sha256msg2_Vdq_Wdq);
657	/* Opcode 0x66 0x0f 0x38 0xcd - invalid. */
658	/* Opcode 0x0f 0x38 0xce - invalid. */
659	/* Opcode 0x66 0x0f 0x38 0xce - invalid. */
660	/* Opcode 0x0f 0x38 0xcf - invalid. */
661	/* Opcode 0x66 0x0f 0x38 0xcf - invalid. */
662
663	/* Opcode 0x66 0x0f 0x38 0xd0 - invalid. */
664	/* Opcode 0x66 0x0f 0x38 0xd1 - invalid. */
665	/* Opcode 0x66 0x0f 0x38 0xd2 - invalid. */
666	/* Opcode 0x66 0x0f 0x38 0xd3 - invalid. */
667	/* Opcode 0x66 0x0f 0x38 0xd4 - invalid. */
668	/* Opcode 0x66 0x0f 0x38 0xd5 - invalid. */
669	/* Opcode 0x66 0x0f 0x38 0xd6 - invalid. */
670	/* Opcode 0x66 0x0f 0x38 0xd7 - invalid. */
671	/* Opcode 0x66 0x0f 0x38 0xd8 - invalid. */
672	/* Opcode 0x66 0x0f 0x38 0xd9 - invalid. */
673	/* Opcode 0x66 0x0f 0x38 0xda - invalid. */
674	/** Opcode 0x66 0x0f 0x38 0xdb. */
675	FNIEMOP_STUB(iemOp_aesimc_Vdq_Wdq);
676	/** Opcode 0x66 0x0f 0x38 0xdc. */
677	FNIEMOP_STUB(iemOp_aesenc_Vdq_Wdq);
678	/** Opcode 0x66 0x0f 0x38 0xdd. */
679	FNIEMOP_STUB(iemOp_aesenclast_Vdq_Wdq);
680	/** Opcode 0x66 0x0f 0x38 0xde. */
681	FNIEMOP_STUB(iemOp_aesdec_Vdq_Wdq);
682	/** Opcode 0x66 0x0f 0x38 0xdf. */
683	FNIEMOP_STUB(iemOp_aesdeclast_Vdq_Wdq);
684
685	/* Opcode 0x66 0x0f 0x38 0xe0 - invalid. */
686	/* Opcode 0x66 0x0f 0x38 0xe1 - invalid. */
687	/* Opcode 0x66 0x0f 0x38 0xe2 - invalid. */
688	/* Opcode 0x66 0x0f 0x38 0xe3 - invalid. */
689	/* Opcode 0x66 0x0f 0x38 0xe4 - invalid. */
690	/* Opcode 0x66 0x0f 0x38 0xe5 - invalid. */
691	/* Opcode 0x66 0x0f 0x38 0xe6 - invalid. */
692	/* Opcode 0x66 0x0f 0x38 0xe7 - invalid. */
693	/* Opcode 0x66 0x0f 0x38 0xe8 - invalid. */
694	/* Opcode 0x66 0x0f 0x38 0xe9 - invalid. */
695	/* Opcode 0x66 0x0f 0x38 0xea - invalid. */
696	/* Opcode 0x66 0x0f 0x38 0xeb - invalid. */
697	/* Opcode 0x66 0x0f 0x38 0xec - invalid. */
698	/* Opcode 0x66 0x0f 0x38 0xed - invalid. */
699	/* Opcode 0x66 0x0f 0x38 0xee - invalid. */
700	/* Opcode 0x66 0x0f 0x38 0xef - invalid. */
701
702
703	/** Opcode 0x0f 0x38 0xf0. */
704	FNIEMOP_STUB(iemOp_movbe_Gy_My);
705	/** Opcode 0x66 0x0f 0x38 0xf0. */
706	FNIEMOP_STUB(iemOp_movbe_Gw_Mw);
707	/* Opcode 0xf3 0x0f 0x38 0xf0 - invalid. */
708	/** Opcode 0xf2 0x0f 0x38 0xf0. */
709	FNIEMOP_STUB(iemOp_crc32_Gb_Eb);
710
711	/** Opcode 0x0f 0x38 0xf1. */
712	FNIEMOP_STUB(iemOp_movbe_My_Gy);
713	/** Opcode 0x66 0x0f 0x38 0xf1. */
714	FNIEMOP_STUB(iemOp_movbe_Mw_Gw);
715	/* Opcode 0xf3 0x0f 0x38 0xf1 - invalid. */
716	/** Opcode 0xf2 0x0f 0x38 0xf1. */
717	FNIEMOP_STUB(iemOp_crc32_Gv_Ev);
718
719	/* Opcode 0x0f 0x38 0xf2 - invalid (vex only). */
720	/* Opcode 0x66 0x0f 0x38 0xf2 - invalid. */
721	/* Opcode 0xf3 0x0f 0x38 0xf2 - invalid. */
722	/* Opcode 0xf2 0x0f 0x38 0xf2 - invalid. */
723
724	/* Opcode 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
725	/* Opcode 0x66 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
726	/* Opcode 0xf3 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
727	/* Opcode 0xf2 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
728
729	/* Opcode 0x0f 0x38 0xf4 - invalid. */
730	/* Opcode 0x66 0x0f 0x38 0xf4 - invalid. */
731	/* Opcode 0xf3 0x0f 0x38 0xf4 - invalid. */
732	/* Opcode 0xf2 0x0f 0x38 0xf4 - invalid. */
733
734	/* Opcode 0x0f 0x38 0xf5 - invalid (vex only). */
735	/* Opcode 0x66 0x0f 0x38 0xf5 - invalid. */
736	/* Opcode 0xf3 0x0f 0x38 0xf5 - invalid (vex only). */
737	/* Opcode 0xf2 0x0f 0x38 0xf5 - invalid (vex only). */
738
739	/* Opcode 0x0f 0x38 0xf6 - invalid. */
740	/** Opcode 0x66 0x0f 0x38 0xf6. */
741	FNIEMOP_STUB(iemOp_adcx_Gy_Ey);
742	/** Opcode 0xf3 0x0f 0x38 0xf6. */
743	FNIEMOP_STUB(iemOp_adox_Gy_Ey);
744	/* Opcode 0xf2 0x0f 0x38 0xf6 - invalid (vex only). */
745
746	/* Opcode 0x0f 0x38 0xf7 - invalid (vex only). */
747	/* Opcode 0x66 0x0f 0x38 0xf7 - invalid (vex only). */
748	/* Opcode 0xf3 0x0f 0x38 0xf7 - invalid (vex only). */
749	/* Opcode 0xf2 0x0f 0x38 0xf7 - invalid (vex only). */
750
751	/* Opcode 0x0f 0x38 0xf8 - invalid. */
752	/* Opcode 0x66 0x0f 0x38 0xf8 - invalid. */
753	/* Opcode 0xf3 0x0f 0x38 0xf8 - invalid. */
754	/* Opcode 0xf2 0x0f 0x38 0xf8 - invalid. */
755
756	/* Opcode 0x0f 0x38 0xf9 - invalid. */
757	/* Opcode 0x66 0x0f 0x38 0xf9 - invalid. */
758	/* Opcode 0xf3 0x0f 0x38 0xf9 - invalid. */
759	/* Opcode 0xf2 0x0f 0x38 0xf9 - invalid. */
760
761	/* Opcode 0x0f 0x38 0xfa - invalid. */
762	/* Opcode 0x66 0x0f 0x38 0xfa - invalid. */
763	/* Opcode 0xf3 0x0f 0x38 0xfa - invalid. */
764	/* Opcode 0xf2 0x0f 0x38 0xfa - invalid. */
765
766	/* Opcode 0x0f 0x38 0xfb - invalid. */
767	/* Opcode 0x66 0x0f 0x38 0xfb - invalid. */
768	/* Opcode 0xf3 0x0f 0x38 0xfb - invalid. */
769	/* Opcode 0xf2 0x0f 0x38 0xfb - invalid. */
770
771	/* Opcode 0x0f 0x38 0xfc - invalid. */
772	/* Opcode 0x66 0x0f 0x38 0xfc - invalid. */
773	/* Opcode 0xf3 0x0f 0x38 0xfc - invalid. */
774	/* Opcode 0xf2 0x0f 0x38 0xfc - invalid. */
775
776	/* Opcode 0x0f 0x38 0xfd - invalid. */
777	/* Opcode 0x66 0x0f 0x38 0xfd - invalid. */
778	/* Opcode 0xf3 0x0f 0x38 0xfd - invalid. */
779	/* Opcode 0xf2 0x0f 0x38 0xfd - invalid. */
780
781	/* Opcode 0x0f 0x38 0xfe - invalid. */
782	/* Opcode 0x66 0x0f 0x38 0xfe - invalid. */
783	/* Opcode 0xf3 0x0f 0x38 0xfe - invalid. */
784	/* Opcode 0xf2 0x0f 0x38 0xfe - invalid. */
785
786	/* Opcode 0x0f 0x38 0xff - invalid. */
787	/* Opcode 0x66 0x0f 0x38 0xff - invalid. */
788	/* Opcode 0xf3 0x0f 0x38 0xff - invalid. */
789	/* Opcode 0xf2 0x0f 0x38 0xff - invalid. */
790
791
792	/**
793	* Three byte opcode map, first two bytes are 0x0f 0x38.
794	* @sa g_apfnVexMap2
795	*/
796	IEM_STATIC const PFNIEMOP g_apfnThreeByte0f38[] =
797	{
798	/* no prefix, 066h prefix f3h prefix, f2h prefix */
799	/* 0x00 */ iemOp_pshufb_Pq_Qq, iemOp_pshufb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
800	/* 0x01 */ iemOp_phaddw_Pq_Qq, iemOp_phaddw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
801	/* 0x02 */ iemOp_phaddd_Pq_Qq, iemOp_phaddd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
802	/* 0x03 */ iemOp_phaddsw_Pq_Qq, iemOp_phaddsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
803	/* 0x04 */ iemOp_pmaddubsw_Pq_Qq, iemOp_pmaddubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
804	/* 0x05 */ iemOp_phsubw_Pq_Qq, iemOp_phsubw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
805	/* 0x06 */ iemOp_phsubd_Pq_Qq, iemOp_phsubdq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
806	/* 0x07 */ iemOp_phsubsw_Pq_Qq, iemOp_phsubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
807	/* 0x08 */ iemOp_psignb_Pq_Qq, iemOp_psignb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
808	/* 0x09 */ iemOp_psignw_Pq_Qq, iemOp_psignw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
809	/* 0x0a */ iemOp_psignd_Pq_Qq, iemOp_psignd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
810	/* 0x0b */ iemOp_pmulhrsw_Pq_Qq, iemOp_pmulhrsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
811	/* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
812	/* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
813	/* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
814	/* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
815
816	/* 0x10 */ iemOp_InvalidNeedRM, iemOp_pblendvb_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
817	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
818	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
819	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
820	/* 0x14 */ iemOp_InvalidNeedRM, iemOp_blendvps_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
821	/* 0x15 */ iemOp_InvalidNeedRM, iemOp_blendvpd_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
822	/* 0x16 */ IEMOP_X4(iemOp_InvalidNeedRM),
823	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_ptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
824	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
825	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
826	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
827	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
828	/* 0x1c */ iemOp_pabsb_Pq_Qq, iemOp_pabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
829	/* 0x1d */ iemOp_pabsw_Pq_Qq, iemOp_pabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
830	/* 0x1e */ iemOp_pabsd_Pq_Qq, iemOp_pabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
831	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
832
833	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_pmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
834	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_pmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
835	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_pmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
836	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_pmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
837	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_pmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
838	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_pmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
839	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
840	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
841	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_pmuldq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
842	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_pcmpeqq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
843	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_movntdqa_Vdq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
844	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_packusdw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
845	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRM),
846	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRM),
847	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRM),
848	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRM),
849
850	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_pmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
851	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_pmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
852	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_pmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
853	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_pmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
854	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_pmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
855	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_pmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
856	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
857	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_pcmpgtq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
858	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_pminsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
859	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_pminsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
860	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_pminuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
861	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_pminud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
862	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_pmaxsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
863	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_pmaxsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
864	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_pmaxuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
865	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_pmaxud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
866
867	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_pmulld_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
868	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_phminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
869	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
870	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
871	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
872	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
873	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
874	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
875	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
876	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
877	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
878	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
879	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
880	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
881	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
882	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
883
884	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
885	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
886	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
887	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
888	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
889	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
890	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
891	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
892	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRM),
893	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRM),
894	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRM),
895	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
896	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
897	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
898	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
899	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
900
901	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
902	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
903	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
904	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
905	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
906	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
907	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
908	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
909	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
910	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
911	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
912	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
913	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
914	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
915	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
916	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
917
918	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
919	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
920	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
921	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
922	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
923	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
924	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
925	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
926	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
927	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
928	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
929	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
930	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
931	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
932	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
933	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
934
935	/* 0x80 */ iemOp_InvalidNeedRM, iemOp_invept_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
936	/* 0x81 */ iemOp_InvalidNeedRM, iemOp_invvpid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
937	/* 0x82 */ iemOp_InvalidNeedRM, iemOp_invpcid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
938	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
939	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
940	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
941	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
942	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
943	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
944	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
945	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
946	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
947	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
948	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
949	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
950	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
951
952	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
953	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
954	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
955	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
956	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
957	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
958	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
959	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
960	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
961	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
962	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
963	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
964	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
965	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
966	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
967	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
968
969	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
970	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
971	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
972	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
973	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
974	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
975	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
976	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
977	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
978	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
979	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
980	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
981	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
982	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
983	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRM),
984	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
985
986	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
987	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
988	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
989	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
990	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
991	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
992	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
993	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
994	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
995	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
996	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
997	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
998	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
999	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
1000	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
1001	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
1002
1003	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1004	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1005	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1006	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1007	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1008	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1009	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1010	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1011	/* 0xc8 */ iemOp_sha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1012	/* 0xc9 */ iemOp_sha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1013	/* 0xca */ iemOp_sha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1014	/* 0xcb */ iemOp_sha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1015	/* 0xcc */ iemOp_sha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1016	/* 0xcd */ iemOp_sha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1017	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1018	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1019
1020	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1021	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1022	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1023	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1024	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1025	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1026	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1027	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1028	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1029	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1030	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1031	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_aesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1032	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_aesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1033	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_aesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1034	/* 0xde */ iemOp_InvalidNeedRM, iemOp_aesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1035	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_aesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1036
1037	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1038	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1039	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1040	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1041	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1042	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1043	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1044	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1045	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1046	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1047	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1048	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1049	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1050	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1051	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1052	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1053
1054	/* 0xf0 */ iemOp_movbe_Gy_My, iemOp_movbe_Gw_Mw, iemOp_InvalidNeedRM, iemOp_crc32_Gb_Eb,
1055	/* 0xf1 */ iemOp_movbe_My_Gy, iemOp_movbe_Mw_Gw, iemOp_InvalidNeedRM, iemOp_crc32_Gv_Ev,
1056	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1057	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1058	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1059	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1060	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_adcx_Gy_Ey, iemOp_adox_Gy_Ey, iemOp_InvalidNeedRM,
1061	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1062	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1063	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1064	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1065	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1066	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1067	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1068	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1069	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1070	};
1071	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f38) == 1024);
1072
1073	/** @} */
1074

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h@ 95453

Download in other formats: