1 | /* $Id: IEMAllInstructions.cpp.h 62478 2016-07-22 18:29:06Z vboxsync $ */
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2 | /** @file
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3 | * IEM - Instruction Decoding and Emulation.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2011-2016 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | /*******************************************************************************
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20 | * Global Variables *
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21 | *******************************************************************************/
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22 | extern const PFNIEMOP g_apfnOneByteMap[256]; /* not static since we need to forward declare it. */
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23 |
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24 | #ifdef _MSC_VER
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25 | # pragma warning(push)
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26 | # pragma warning(disable: 4702) /* Unreachable code like return in iemOp_Grp6_lldt. */
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27 | #endif
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28 |
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29 |
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30 | /**
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31 | * Common worker for instructions like ADD, AND, OR, ++ with a byte
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32 | * memory/register as the destination.
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33 | *
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34 | * @param pImpl Pointer to the instruction implementation (assembly).
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35 | */
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36 | FNIEMOP_DEF_1(iemOpHlpBinaryOperator_rm_r8, PCIEMOPBINSIZES, pImpl)
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37 | {
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38 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
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39 |
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40 | /*
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41 | * If rm is denoting a register, no more instruction bytes.
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42 | */
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43 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
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44 | {
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45 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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46 |
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47 | IEM_MC_BEGIN(3, 0);
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48 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
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49 | IEM_MC_ARG(uint8_t, u8Src, 1);
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50 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
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51 |
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52 | IEM_MC_FETCH_GREG_U8(u8Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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53 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
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54 | IEM_MC_REF_EFLAGS(pEFlags);
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55 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, u8Src, pEFlags);
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56 |
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57 | IEM_MC_ADVANCE_RIP();
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58 | IEM_MC_END();
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59 | }
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60 | else
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61 | {
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62 | /*
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63 | * We're accessing memory.
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64 | * Note! We're putting the eflags on the stack here so we can commit them
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65 | * after the memory.
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66 | */
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67 | uint32_t const fAccess = pImpl->pfnLockedU8 ? IEM_ACCESS_DATA_RW : IEM_ACCESS_DATA_R; /* CMP,TEST */
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68 | IEM_MC_BEGIN(3, 2);
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69 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
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70 | IEM_MC_ARG(uint8_t, u8Src, 1);
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71 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
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72 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
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73 |
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74 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
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75 | if (!pImpl->pfnLockedU8)
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76 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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77 | IEM_MC_MEM_MAP(pu8Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
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78 | IEM_MC_FETCH_GREG_U8(u8Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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79 | IEM_MC_FETCH_EFLAGS(EFlags);
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80 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
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81 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, u8Src, pEFlags);
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82 | else
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83 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU8, pu8Dst, u8Src, pEFlags);
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84 |
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85 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, fAccess);
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86 | IEM_MC_COMMIT_EFLAGS(EFlags);
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87 | IEM_MC_ADVANCE_RIP();
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88 | IEM_MC_END();
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89 | }
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90 | return VINF_SUCCESS;
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91 | }
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92 |
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93 |
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94 | /**
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95 | * Common worker for word/dword/qword instructions like ADD, AND, OR, ++ with
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96 | * memory/register as the destination.
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97 | *
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98 | * @param pImpl Pointer to the instruction implementation (assembly).
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99 | */
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100 | FNIEMOP_DEF_1(iemOpHlpBinaryOperator_rm_rv, PCIEMOPBINSIZES, pImpl)
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101 | {
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102 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
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103 |
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104 | /*
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105 | * If rm is denoting a register, no more instruction bytes.
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106 | */
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107 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
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108 | {
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109 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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110 |
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111 | switch (pVCpu->iem.s.enmEffOpSize)
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112 | {
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113 | case IEMMODE_16BIT:
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114 | IEM_MC_BEGIN(3, 0);
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115 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
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116 | IEM_MC_ARG(uint16_t, u16Src, 1);
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117 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
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118 |
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119 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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120 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
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121 | IEM_MC_REF_EFLAGS(pEFlags);
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122 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
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123 |
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124 | IEM_MC_ADVANCE_RIP();
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125 | IEM_MC_END();
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126 | break;
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127 |
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128 | case IEMMODE_32BIT:
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129 | IEM_MC_BEGIN(3, 0);
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130 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
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131 | IEM_MC_ARG(uint32_t, u32Src, 1);
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132 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
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133 |
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134 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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135 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
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136 | IEM_MC_REF_EFLAGS(pEFlags);
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137 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
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138 |
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139 | if (pImpl != &g_iemAImpl_test)
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140 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
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141 | IEM_MC_ADVANCE_RIP();
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142 | IEM_MC_END();
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143 | break;
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144 |
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145 | case IEMMODE_64BIT:
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146 | IEM_MC_BEGIN(3, 0);
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147 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
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148 | IEM_MC_ARG(uint64_t, u64Src, 1);
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149 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
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150 |
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151 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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152 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
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153 | IEM_MC_REF_EFLAGS(pEFlags);
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154 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
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155 |
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156 | IEM_MC_ADVANCE_RIP();
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157 | IEM_MC_END();
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158 | break;
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159 | }
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160 | }
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161 | else
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162 | {
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163 | /*
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164 | * We're accessing memory.
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165 | * Note! We're putting the eflags on the stack here so we can commit them
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166 | * after the memory.
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167 | */
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168 | uint32_t const fAccess = pImpl->pfnLockedU8 ? IEM_ACCESS_DATA_RW : IEM_ACCESS_DATA_R /* CMP,TEST */;
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169 | switch (pVCpu->iem.s.enmEffOpSize)
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170 | {
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171 | case IEMMODE_16BIT:
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172 | IEM_MC_BEGIN(3, 2);
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173 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
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174 | IEM_MC_ARG(uint16_t, u16Src, 1);
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175 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
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176 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
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177 |
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178 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
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179 | if (!pImpl->pfnLockedU16)
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180 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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181 | IEM_MC_MEM_MAP(pu16Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
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182 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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183 | IEM_MC_FETCH_EFLAGS(EFlags);
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184 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
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185 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
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186 | else
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187 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
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188 |
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189 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, fAccess);
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190 | IEM_MC_COMMIT_EFLAGS(EFlags);
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191 | IEM_MC_ADVANCE_RIP();
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192 | IEM_MC_END();
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193 | break;
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194 |
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195 | case IEMMODE_32BIT:
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196 | IEM_MC_BEGIN(3, 2);
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197 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
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198 | IEM_MC_ARG(uint32_t, u32Src, 1);
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199 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
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200 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
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201 |
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202 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
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203 | if (!pImpl->pfnLockedU32)
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204 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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205 | IEM_MC_MEM_MAP(pu32Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
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206 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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207 | IEM_MC_FETCH_EFLAGS(EFlags);
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208 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
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209 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
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210 | else
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211 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
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212 |
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213 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, fAccess);
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214 | IEM_MC_COMMIT_EFLAGS(EFlags);
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215 | IEM_MC_ADVANCE_RIP();
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216 | IEM_MC_END();
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217 | break;
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218 |
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219 | case IEMMODE_64BIT:
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220 | IEM_MC_BEGIN(3, 2);
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221 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
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222 | IEM_MC_ARG(uint64_t, u64Src, 1);
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223 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
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224 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
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225 |
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226 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
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227 | if (!pImpl->pfnLockedU64)
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228 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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229 | IEM_MC_MEM_MAP(pu64Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
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230 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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231 | IEM_MC_FETCH_EFLAGS(EFlags);
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232 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
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233 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
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234 | else
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235 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
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236 |
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237 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, fAccess);
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238 | IEM_MC_COMMIT_EFLAGS(EFlags);
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239 | IEM_MC_ADVANCE_RIP();
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240 | IEM_MC_END();
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241 | break;
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242 | }
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243 | }
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244 | return VINF_SUCCESS;
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245 | }
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246 |
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247 |
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248 | /**
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249 | * Common worker for byte instructions like ADD, AND, OR, ++ with a register as
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250 | * the destination.
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251 | *
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252 | * @param pImpl Pointer to the instruction implementation (assembly).
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253 | */
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254 | FNIEMOP_DEF_1(iemOpHlpBinaryOperator_r8_rm, PCIEMOPBINSIZES, pImpl)
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255 | {
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256 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
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257 |
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258 | /*
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259 | * If rm is denoting a register, no more instruction bytes.
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260 | */
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261 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
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262 | {
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263 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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264 | IEM_MC_BEGIN(3, 0);
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265 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
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266 | IEM_MC_ARG(uint8_t, u8Src, 1);
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267 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
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268 |
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269 | IEM_MC_FETCH_GREG_U8(u8Src, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
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270 | IEM_MC_REF_GREG_U8(pu8Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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271 | IEM_MC_REF_EFLAGS(pEFlags);
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272 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, u8Src, pEFlags);
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273 |
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274 | IEM_MC_ADVANCE_RIP();
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275 | IEM_MC_END();
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276 | }
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277 | else
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278 | {
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279 | /*
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280 | * We're accessing memory.
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281 | */
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282 | IEM_MC_BEGIN(3, 1);
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283 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
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284 | IEM_MC_ARG(uint8_t, u8Src, 1);
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285 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
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286 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
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287 |
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288 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
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289 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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290 | IEM_MC_FETCH_MEM_U8(u8Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
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291 | IEM_MC_REF_GREG_U8(pu8Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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292 | IEM_MC_REF_EFLAGS(pEFlags);
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293 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, u8Src, pEFlags);
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294 |
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295 | IEM_MC_ADVANCE_RIP();
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296 | IEM_MC_END();
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297 | }
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298 | return VINF_SUCCESS;
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299 | }
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300 |
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301 |
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302 | /**
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303 | * Common worker for word/dword/qword instructions like ADD, AND, OR, ++ with a
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304 | * register as the destination.
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305 | *
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306 | * @param pImpl Pointer to the instruction implementation (assembly).
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307 | */
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308 | FNIEMOP_DEF_1(iemOpHlpBinaryOperator_rv_rm, PCIEMOPBINSIZES, pImpl)
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309 | {
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310 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
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311 |
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312 | /*
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313 | * If rm is denoting a register, no more instruction bytes.
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314 | */
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315 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
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316 | {
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317 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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318 | switch (pVCpu->iem.s.enmEffOpSize)
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319 | {
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320 | case IEMMODE_16BIT:
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321 | IEM_MC_BEGIN(3, 0);
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322 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
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323 | IEM_MC_ARG(uint16_t, u16Src, 1);
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324 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
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325 |
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326 | IEM_MC_FETCH_GREG_U16(u16Src, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
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327 | IEM_MC_REF_GREG_U16(pu16Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
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328 | IEM_MC_REF_EFLAGS(pEFlags);
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329 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
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330 |
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331 | IEM_MC_ADVANCE_RIP();
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332 | IEM_MC_END();
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333 | break;
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334 |
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335 | case IEMMODE_32BIT:
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336 | IEM_MC_BEGIN(3, 0);
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337 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
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338 | IEM_MC_ARG(uint32_t, u32Src, 1);
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339 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
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340 |
|
---|
341 | IEM_MC_FETCH_GREG_U32(u32Src, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
342 | IEM_MC_REF_GREG_U32(pu32Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
343 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
344 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
345 |
|
---|
346 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
347 | IEM_MC_ADVANCE_RIP();
|
---|
348 | IEM_MC_END();
|
---|
349 | break;
|
---|
350 |
|
---|
351 | case IEMMODE_64BIT:
|
---|
352 | IEM_MC_BEGIN(3, 0);
|
---|
353 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
354 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
355 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
356 |
|
---|
357 | IEM_MC_FETCH_GREG_U64(u64Src, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
358 | IEM_MC_REF_GREG_U64(pu64Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
359 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
360 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
361 |
|
---|
362 | IEM_MC_ADVANCE_RIP();
|
---|
363 | IEM_MC_END();
|
---|
364 | break;
|
---|
365 | }
|
---|
366 | }
|
---|
367 | else
|
---|
368 | {
|
---|
369 | /*
|
---|
370 | * We're accessing memory.
|
---|
371 | */
|
---|
372 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
373 | {
|
---|
374 | case IEMMODE_16BIT:
|
---|
375 | IEM_MC_BEGIN(3, 1);
|
---|
376 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
377 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
378 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
379 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
380 |
|
---|
381 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
382 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
383 | IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
384 | IEM_MC_REF_GREG_U16(pu16Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
385 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
386 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
387 |
|
---|
388 | IEM_MC_ADVANCE_RIP();
|
---|
389 | IEM_MC_END();
|
---|
390 | break;
|
---|
391 |
|
---|
392 | case IEMMODE_32BIT:
|
---|
393 | IEM_MC_BEGIN(3, 1);
|
---|
394 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
395 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
396 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
397 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
398 |
|
---|
399 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
400 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
401 | IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
402 | IEM_MC_REF_GREG_U32(pu32Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
403 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
404 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
405 |
|
---|
406 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
407 | IEM_MC_ADVANCE_RIP();
|
---|
408 | IEM_MC_END();
|
---|
409 | break;
|
---|
410 |
|
---|
411 | case IEMMODE_64BIT:
|
---|
412 | IEM_MC_BEGIN(3, 1);
|
---|
413 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
414 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
415 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
416 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
417 |
|
---|
418 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
419 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
420 | IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
421 | IEM_MC_REF_GREG_U64(pu64Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
422 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
423 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
424 |
|
---|
425 | IEM_MC_ADVANCE_RIP();
|
---|
426 | IEM_MC_END();
|
---|
427 | break;
|
---|
428 | }
|
---|
429 | }
|
---|
430 | return VINF_SUCCESS;
|
---|
431 | }
|
---|
432 |
|
---|
433 |
|
---|
434 | /**
|
---|
435 | * Common worker for instructions like ADD, AND, OR, ++ with working on AL with
|
---|
436 | * a byte immediate.
|
---|
437 | *
|
---|
438 | * @param pImpl Pointer to the instruction implementation (assembly).
|
---|
439 | */
|
---|
440 | FNIEMOP_DEF_1(iemOpHlpBinaryOperator_AL_Ib, PCIEMOPBINSIZES, pImpl)
|
---|
441 | {
|
---|
442 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
443 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
444 |
|
---|
445 | IEM_MC_BEGIN(3, 0);
|
---|
446 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
447 | IEM_MC_ARG_CONST(uint8_t, u8Src,/*=*/ u8Imm, 1);
|
---|
448 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
449 |
|
---|
450 | IEM_MC_REF_GREG_U8(pu8Dst, X86_GREG_xAX);
|
---|
451 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
452 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, u8Src, pEFlags);
|
---|
453 |
|
---|
454 | IEM_MC_ADVANCE_RIP();
|
---|
455 | IEM_MC_END();
|
---|
456 | return VINF_SUCCESS;
|
---|
457 | }
|
---|
458 |
|
---|
459 |
|
---|
460 | /**
|
---|
461 | * Common worker for instructions like ADD, AND, OR, ++ with working on
|
---|
462 | * AX/EAX/RAX with a word/dword immediate.
|
---|
463 | *
|
---|
464 | * @param pImpl Pointer to the instruction implementation (assembly).
|
---|
465 | */
|
---|
466 | FNIEMOP_DEF_1(iemOpHlpBinaryOperator_rAX_Iz, PCIEMOPBINSIZES, pImpl)
|
---|
467 | {
|
---|
468 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
469 | {
|
---|
470 | case IEMMODE_16BIT:
|
---|
471 | {
|
---|
472 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
473 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
474 |
|
---|
475 | IEM_MC_BEGIN(3, 0);
|
---|
476 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
477 | IEM_MC_ARG_CONST(uint16_t, u16Src,/*=*/ u16Imm, 1);
|
---|
478 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
479 |
|
---|
480 | IEM_MC_REF_GREG_U16(pu16Dst, X86_GREG_xAX);
|
---|
481 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
482 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
483 |
|
---|
484 | IEM_MC_ADVANCE_RIP();
|
---|
485 | IEM_MC_END();
|
---|
486 | return VINF_SUCCESS;
|
---|
487 | }
|
---|
488 |
|
---|
489 | case IEMMODE_32BIT:
|
---|
490 | {
|
---|
491 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
492 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
493 |
|
---|
494 | IEM_MC_BEGIN(3, 0);
|
---|
495 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
496 | IEM_MC_ARG_CONST(uint32_t, u32Src,/*=*/ u32Imm, 1);
|
---|
497 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
498 |
|
---|
499 | IEM_MC_REF_GREG_U32(pu32Dst, X86_GREG_xAX);
|
---|
500 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
501 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
502 |
|
---|
503 | if (pImpl != &g_iemAImpl_test)
|
---|
504 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
505 | IEM_MC_ADVANCE_RIP();
|
---|
506 | IEM_MC_END();
|
---|
507 | return VINF_SUCCESS;
|
---|
508 | }
|
---|
509 |
|
---|
510 | case IEMMODE_64BIT:
|
---|
511 | {
|
---|
512 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
513 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
514 |
|
---|
515 | IEM_MC_BEGIN(3, 0);
|
---|
516 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
517 | IEM_MC_ARG_CONST(uint64_t, u64Src,/*=*/ u64Imm, 1);
|
---|
518 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
519 |
|
---|
520 | IEM_MC_REF_GREG_U64(pu64Dst, X86_GREG_xAX);
|
---|
521 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
522 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
523 |
|
---|
524 | IEM_MC_ADVANCE_RIP();
|
---|
525 | IEM_MC_END();
|
---|
526 | return VINF_SUCCESS;
|
---|
527 | }
|
---|
528 |
|
---|
529 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
530 | }
|
---|
531 | }
|
---|
532 |
|
---|
533 |
|
---|
534 | /** Opcodes 0xf1, 0xd6. */
|
---|
535 | FNIEMOP_DEF(iemOp_Invalid)
|
---|
536 | {
|
---|
537 | IEMOP_MNEMONIC("Invalid");
|
---|
538 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
539 | }
|
---|
540 |
|
---|
541 |
|
---|
542 | /** Invalid with RM byte . */
|
---|
543 | FNIEMOPRM_DEF(iemOp_InvalidWithRM)
|
---|
544 | {
|
---|
545 | IEMOP_MNEMONIC("InvalidWithRM");
|
---|
546 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
547 | }
|
---|
548 |
|
---|
549 |
|
---|
550 |
|
---|
551 | /** @name ..... opcodes.
|
---|
552 | *
|
---|
553 | * @{
|
---|
554 | */
|
---|
555 |
|
---|
556 | /** @} */
|
---|
557 |
|
---|
558 |
|
---|
559 | /** @name Two byte opcodes (first byte 0x0f).
|
---|
560 | *
|
---|
561 | * @{
|
---|
562 | */
|
---|
563 |
|
---|
564 | /** Opcode 0x0f 0x00 /0. */
|
---|
565 | FNIEMOPRM_DEF(iemOp_Grp6_sldt)
|
---|
566 | {
|
---|
567 | IEMOP_MNEMONIC("sldt Rv/Mw");
|
---|
568 | IEMOP_HLP_MIN_286();
|
---|
569 | IEMOP_HLP_NO_REAL_OR_V86_MODE();
|
---|
570 |
|
---|
571 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
572 | {
|
---|
573 | IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
574 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
575 | {
|
---|
576 | case IEMMODE_16BIT:
|
---|
577 | IEM_MC_BEGIN(0, 1);
|
---|
578 | IEM_MC_LOCAL(uint16_t, u16Ldtr);
|
---|
579 | IEM_MC_FETCH_LDTR_U16(u16Ldtr);
|
---|
580 | IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Ldtr);
|
---|
581 | IEM_MC_ADVANCE_RIP();
|
---|
582 | IEM_MC_END();
|
---|
583 | break;
|
---|
584 |
|
---|
585 | case IEMMODE_32BIT:
|
---|
586 | IEM_MC_BEGIN(0, 1);
|
---|
587 | IEM_MC_LOCAL(uint32_t, u32Ldtr);
|
---|
588 | IEM_MC_FETCH_LDTR_U32(u32Ldtr);
|
---|
589 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Ldtr);
|
---|
590 | IEM_MC_ADVANCE_RIP();
|
---|
591 | IEM_MC_END();
|
---|
592 | break;
|
---|
593 |
|
---|
594 | case IEMMODE_64BIT:
|
---|
595 | IEM_MC_BEGIN(0, 1);
|
---|
596 | IEM_MC_LOCAL(uint64_t, u64Ldtr);
|
---|
597 | IEM_MC_FETCH_LDTR_U64(u64Ldtr);
|
---|
598 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Ldtr);
|
---|
599 | IEM_MC_ADVANCE_RIP();
|
---|
600 | IEM_MC_END();
|
---|
601 | break;
|
---|
602 |
|
---|
603 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
604 | }
|
---|
605 | }
|
---|
606 | else
|
---|
607 | {
|
---|
608 | IEM_MC_BEGIN(0, 2);
|
---|
609 | IEM_MC_LOCAL(uint16_t, u16Ldtr);
|
---|
610 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
611 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
612 | IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
613 | IEM_MC_FETCH_LDTR_U16(u16Ldtr);
|
---|
614 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Ldtr);
|
---|
615 | IEM_MC_ADVANCE_RIP();
|
---|
616 | IEM_MC_END();
|
---|
617 | }
|
---|
618 | return VINF_SUCCESS;
|
---|
619 | }
|
---|
620 |
|
---|
621 |
|
---|
622 | /** Opcode 0x0f 0x00 /1. */
|
---|
623 | FNIEMOPRM_DEF(iemOp_Grp6_str)
|
---|
624 | {
|
---|
625 | IEMOP_MNEMONIC("str Rv/Mw");
|
---|
626 | IEMOP_HLP_MIN_286();
|
---|
627 | IEMOP_HLP_NO_REAL_OR_V86_MODE();
|
---|
628 |
|
---|
629 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
630 | {
|
---|
631 | IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
632 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
633 | {
|
---|
634 | case IEMMODE_16BIT:
|
---|
635 | IEM_MC_BEGIN(0, 1);
|
---|
636 | IEM_MC_LOCAL(uint16_t, u16Tr);
|
---|
637 | IEM_MC_FETCH_TR_U16(u16Tr);
|
---|
638 | IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Tr);
|
---|
639 | IEM_MC_ADVANCE_RIP();
|
---|
640 | IEM_MC_END();
|
---|
641 | break;
|
---|
642 |
|
---|
643 | case IEMMODE_32BIT:
|
---|
644 | IEM_MC_BEGIN(0, 1);
|
---|
645 | IEM_MC_LOCAL(uint32_t, u32Tr);
|
---|
646 | IEM_MC_FETCH_TR_U32(u32Tr);
|
---|
647 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tr);
|
---|
648 | IEM_MC_ADVANCE_RIP();
|
---|
649 | IEM_MC_END();
|
---|
650 | break;
|
---|
651 |
|
---|
652 | case IEMMODE_64BIT:
|
---|
653 | IEM_MC_BEGIN(0, 1);
|
---|
654 | IEM_MC_LOCAL(uint64_t, u64Tr);
|
---|
655 | IEM_MC_FETCH_TR_U64(u64Tr);
|
---|
656 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tr);
|
---|
657 | IEM_MC_ADVANCE_RIP();
|
---|
658 | IEM_MC_END();
|
---|
659 | break;
|
---|
660 |
|
---|
661 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
662 | }
|
---|
663 | }
|
---|
664 | else
|
---|
665 | {
|
---|
666 | IEM_MC_BEGIN(0, 2);
|
---|
667 | IEM_MC_LOCAL(uint16_t, u16Tr);
|
---|
668 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
669 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
670 | IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
671 | IEM_MC_FETCH_TR_U16(u16Tr);
|
---|
672 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tr);
|
---|
673 | IEM_MC_ADVANCE_RIP();
|
---|
674 | IEM_MC_END();
|
---|
675 | }
|
---|
676 | return VINF_SUCCESS;
|
---|
677 | }
|
---|
678 |
|
---|
679 |
|
---|
680 | /** Opcode 0x0f 0x00 /2. */
|
---|
681 | FNIEMOPRM_DEF(iemOp_Grp6_lldt)
|
---|
682 | {
|
---|
683 | IEMOP_MNEMONIC("lldt Ew");
|
---|
684 | IEMOP_HLP_MIN_286();
|
---|
685 | IEMOP_HLP_NO_REAL_OR_V86_MODE();
|
---|
686 |
|
---|
687 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
688 | {
|
---|
689 | IEMOP_HLP_DECODED_NL_1(OP_LLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS);
|
---|
690 | IEM_MC_BEGIN(1, 0);
|
---|
691 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
692 | IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
693 | IEM_MC_CALL_CIMPL_1(iemCImpl_lldt, u16Sel);
|
---|
694 | IEM_MC_END();
|
---|
695 | }
|
---|
696 | else
|
---|
697 | {
|
---|
698 | IEM_MC_BEGIN(1, 1);
|
---|
699 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
700 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
701 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
702 | IEMOP_HLP_DECODED_NL_1(OP_LLDT, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS);
|
---|
703 | IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO(); /** @todo test order */
|
---|
704 | IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
705 | IEM_MC_CALL_CIMPL_1(iemCImpl_lldt, u16Sel);
|
---|
706 | IEM_MC_END();
|
---|
707 | }
|
---|
708 | return VINF_SUCCESS;
|
---|
709 | }
|
---|
710 |
|
---|
711 |
|
---|
712 | /** Opcode 0x0f 0x00 /3. */
|
---|
713 | FNIEMOPRM_DEF(iemOp_Grp6_ltr)
|
---|
714 | {
|
---|
715 | IEMOP_MNEMONIC("ltr Ew");
|
---|
716 | IEMOP_HLP_MIN_286();
|
---|
717 | IEMOP_HLP_NO_REAL_OR_V86_MODE();
|
---|
718 |
|
---|
719 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
720 | {
|
---|
721 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
722 | IEM_MC_BEGIN(1, 0);
|
---|
723 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
724 | IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
725 | IEM_MC_CALL_CIMPL_1(iemCImpl_ltr, u16Sel);
|
---|
726 | IEM_MC_END();
|
---|
727 | }
|
---|
728 | else
|
---|
729 | {
|
---|
730 | IEM_MC_BEGIN(1, 1);
|
---|
731 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
732 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
733 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
734 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
735 | IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO(); /** @todo test ordre */
|
---|
736 | IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
737 | IEM_MC_CALL_CIMPL_1(iemCImpl_ltr, u16Sel);
|
---|
738 | IEM_MC_END();
|
---|
739 | }
|
---|
740 | return VINF_SUCCESS;
|
---|
741 | }
|
---|
742 |
|
---|
743 |
|
---|
744 | /** Opcode 0x0f 0x00 /3. */
|
---|
745 | FNIEMOP_DEF_2(iemOpCommonGrp6VerX, uint8_t, bRm, bool, fWrite)
|
---|
746 | {
|
---|
747 | IEMOP_HLP_MIN_286();
|
---|
748 | IEMOP_HLP_NO_REAL_OR_V86_MODE();
|
---|
749 |
|
---|
750 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
751 | {
|
---|
752 | IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
753 | IEM_MC_BEGIN(2, 0);
|
---|
754 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
755 | IEM_MC_ARG_CONST(bool, fWriteArg, fWrite, 1);
|
---|
756 | IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
757 | IEM_MC_CALL_CIMPL_2(iemCImpl_VerX, u16Sel, fWriteArg);
|
---|
758 | IEM_MC_END();
|
---|
759 | }
|
---|
760 | else
|
---|
761 | {
|
---|
762 | IEM_MC_BEGIN(2, 1);
|
---|
763 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
764 | IEM_MC_ARG_CONST(bool, fWriteArg, fWrite, 1);
|
---|
765 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
766 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
767 | IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
768 | IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
769 | IEM_MC_CALL_CIMPL_2(iemCImpl_VerX, u16Sel, fWriteArg);
|
---|
770 | IEM_MC_END();
|
---|
771 | }
|
---|
772 | return VINF_SUCCESS;
|
---|
773 | }
|
---|
774 |
|
---|
775 |
|
---|
776 | /** Opcode 0x0f 0x00 /4. */
|
---|
777 | FNIEMOPRM_DEF(iemOp_Grp6_verr)
|
---|
778 | {
|
---|
779 | IEMOP_MNEMONIC("verr Ew");
|
---|
780 | IEMOP_HLP_MIN_286();
|
---|
781 | return FNIEMOP_CALL_2(iemOpCommonGrp6VerX, bRm, false);
|
---|
782 | }
|
---|
783 |
|
---|
784 |
|
---|
785 | /** Opcode 0x0f 0x00 /5. */
|
---|
786 | FNIEMOPRM_DEF(iemOp_Grp6_verw)
|
---|
787 | {
|
---|
788 | IEMOP_MNEMONIC("verr Ew");
|
---|
789 | IEMOP_HLP_MIN_286();
|
---|
790 | return FNIEMOP_CALL_2(iemOpCommonGrp6VerX, bRm, true);
|
---|
791 | }
|
---|
792 |
|
---|
793 |
|
---|
794 | /**
|
---|
795 | * Group 6 jump table.
|
---|
796 | */
|
---|
797 | IEM_STATIC const PFNIEMOPRM g_apfnGroup6[8] =
|
---|
798 | {
|
---|
799 | iemOp_Grp6_sldt,
|
---|
800 | iemOp_Grp6_str,
|
---|
801 | iemOp_Grp6_lldt,
|
---|
802 | iemOp_Grp6_ltr,
|
---|
803 | iemOp_Grp6_verr,
|
---|
804 | iemOp_Grp6_verw,
|
---|
805 | iemOp_InvalidWithRM,
|
---|
806 | iemOp_InvalidWithRM
|
---|
807 | };
|
---|
808 |
|
---|
809 | /** Opcode 0x0f 0x00. */
|
---|
810 | FNIEMOP_DEF(iemOp_Grp6)
|
---|
811 | {
|
---|
812 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
813 | return FNIEMOP_CALL_1(g_apfnGroup6[(bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK], bRm);
|
---|
814 | }
|
---|
815 |
|
---|
816 |
|
---|
817 | /** Opcode 0x0f 0x01 /0. */
|
---|
818 | FNIEMOP_DEF_1(iemOp_Grp7_sgdt, uint8_t, bRm)
|
---|
819 | {
|
---|
820 | IEMOP_MNEMONIC("sgdt Ms");
|
---|
821 | IEMOP_HLP_MIN_286();
|
---|
822 | IEMOP_HLP_64BIT_OP_SIZE();
|
---|
823 | IEM_MC_BEGIN(2, 1);
|
---|
824 | IEM_MC_ARG(uint8_t, iEffSeg, 0);
|
---|
825 | IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
|
---|
826 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
827 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
828 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
829 | IEM_MC_CALL_CIMPL_2(iemCImpl_sgdt, iEffSeg, GCPtrEffSrc);
|
---|
830 | IEM_MC_END();
|
---|
831 | return VINF_SUCCESS;
|
---|
832 | }
|
---|
833 |
|
---|
834 |
|
---|
835 | /** Opcode 0x0f 0x01 /0. */
|
---|
836 | FNIEMOP_DEF(iemOp_Grp7_vmcall)
|
---|
837 | {
|
---|
838 | IEMOP_BITCH_ABOUT_STUB();
|
---|
839 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
840 | }
|
---|
841 |
|
---|
842 |
|
---|
843 | /** Opcode 0x0f 0x01 /0. */
|
---|
844 | FNIEMOP_DEF(iemOp_Grp7_vmlaunch)
|
---|
845 | {
|
---|
846 | IEMOP_BITCH_ABOUT_STUB();
|
---|
847 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
848 | }
|
---|
849 |
|
---|
850 |
|
---|
851 | /** Opcode 0x0f 0x01 /0. */
|
---|
852 | FNIEMOP_DEF(iemOp_Grp7_vmresume)
|
---|
853 | {
|
---|
854 | IEMOP_BITCH_ABOUT_STUB();
|
---|
855 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
856 | }
|
---|
857 |
|
---|
858 |
|
---|
859 | /** Opcode 0x0f 0x01 /0. */
|
---|
860 | FNIEMOP_DEF(iemOp_Grp7_vmxoff)
|
---|
861 | {
|
---|
862 | IEMOP_BITCH_ABOUT_STUB();
|
---|
863 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
864 | }
|
---|
865 |
|
---|
866 |
|
---|
867 | /** Opcode 0x0f 0x01 /1. */
|
---|
868 | FNIEMOP_DEF_1(iemOp_Grp7_sidt, uint8_t, bRm)
|
---|
869 | {
|
---|
870 | IEMOP_MNEMONIC("sidt Ms");
|
---|
871 | IEMOP_HLP_MIN_286();
|
---|
872 | IEMOP_HLP_64BIT_OP_SIZE();
|
---|
873 | IEM_MC_BEGIN(2, 1);
|
---|
874 | IEM_MC_ARG(uint8_t, iEffSeg, 0);
|
---|
875 | IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
|
---|
876 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
877 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
878 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
879 | IEM_MC_CALL_CIMPL_2(iemCImpl_sidt, iEffSeg, GCPtrEffSrc);
|
---|
880 | IEM_MC_END();
|
---|
881 | return VINF_SUCCESS;
|
---|
882 | }
|
---|
883 |
|
---|
884 |
|
---|
885 | /** Opcode 0x0f 0x01 /1. */
|
---|
886 | FNIEMOP_DEF(iemOp_Grp7_monitor)
|
---|
887 | {
|
---|
888 | IEMOP_MNEMONIC("monitor");
|
---|
889 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo Verify that monitor is allergic to lock prefixes. */
|
---|
890 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_monitor, pVCpu->iem.s.iEffSeg);
|
---|
891 | }
|
---|
892 |
|
---|
893 |
|
---|
894 | /** Opcode 0x0f 0x01 /1. */
|
---|
895 | FNIEMOP_DEF(iemOp_Grp7_mwait)
|
---|
896 | {
|
---|
897 | IEMOP_MNEMONIC("mwait"); /** @todo Verify that mwait is allergic to lock prefixes. */
|
---|
898 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
899 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_mwait);
|
---|
900 | }
|
---|
901 |
|
---|
902 |
|
---|
903 | /** Opcode 0x0f 0x01 /2. */
|
---|
904 | FNIEMOP_DEF_1(iemOp_Grp7_lgdt, uint8_t, bRm)
|
---|
905 | {
|
---|
906 | IEMOP_MNEMONIC("lgdt");
|
---|
907 | IEMOP_HLP_64BIT_OP_SIZE();
|
---|
908 | IEM_MC_BEGIN(3, 1);
|
---|
909 | IEM_MC_ARG(uint8_t, iEffSeg, 0);
|
---|
910 | IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
|
---|
911 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSizeArg,/*=*/pVCpu->iem.s.enmEffOpSize, 2);
|
---|
912 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
913 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
914 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
915 | IEM_MC_CALL_CIMPL_3(iemCImpl_lgdt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg);
|
---|
916 | IEM_MC_END();
|
---|
917 | return VINF_SUCCESS;
|
---|
918 | }
|
---|
919 |
|
---|
920 |
|
---|
921 | /** Opcode 0x0f 0x01 0xd0. */
|
---|
922 | FNIEMOP_DEF(iemOp_Grp7_xgetbv)
|
---|
923 | {
|
---|
924 | IEMOP_MNEMONIC("xgetbv");
|
---|
925 | if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
|
---|
926 | {
|
---|
927 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
|
---|
928 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_xgetbv);
|
---|
929 | }
|
---|
930 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
931 | }
|
---|
932 |
|
---|
933 |
|
---|
934 | /** Opcode 0x0f 0x01 0xd1. */
|
---|
935 | FNIEMOP_DEF(iemOp_Grp7_xsetbv)
|
---|
936 | {
|
---|
937 | IEMOP_MNEMONIC("xsetbv");
|
---|
938 | if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
|
---|
939 | {
|
---|
940 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
|
---|
941 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_xsetbv);
|
---|
942 | }
|
---|
943 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
944 | }
|
---|
945 |
|
---|
946 |
|
---|
947 | /** Opcode 0x0f 0x01 /3. */
|
---|
948 | FNIEMOP_DEF_1(iemOp_Grp7_lidt, uint8_t, bRm)
|
---|
949 | {
|
---|
950 | IEMMODE enmEffOpSize = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
|
---|
951 | ? IEMMODE_64BIT
|
---|
952 | : pVCpu->iem.s.enmEffOpSize;
|
---|
953 | IEM_MC_BEGIN(3, 1);
|
---|
954 | IEM_MC_ARG(uint8_t, iEffSeg, 0);
|
---|
955 | IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
|
---|
956 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSizeArg,/*=*/enmEffOpSize, 2);
|
---|
957 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
958 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
959 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
960 | IEM_MC_CALL_CIMPL_3(iemCImpl_lidt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg);
|
---|
961 | IEM_MC_END();
|
---|
962 | return VINF_SUCCESS;
|
---|
963 | }
|
---|
964 |
|
---|
965 |
|
---|
966 | /** Opcode 0x0f 0x01 0xd8. */
|
---|
967 | FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmrun);
|
---|
968 |
|
---|
969 | /** Opcode 0x0f 0x01 0xd9. */
|
---|
970 | FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmmcall);
|
---|
971 |
|
---|
972 | /** Opcode 0x0f 0x01 0xda. */
|
---|
973 | FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmload);
|
---|
974 |
|
---|
975 | /** Opcode 0x0f 0x01 0xdb. */
|
---|
976 | FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmsave);
|
---|
977 |
|
---|
978 | /** Opcode 0x0f 0x01 0xdc. */
|
---|
979 | FNIEMOP_UD_STUB(iemOp_Grp7_Amd_stgi);
|
---|
980 |
|
---|
981 | /** Opcode 0x0f 0x01 0xdd. */
|
---|
982 | FNIEMOP_UD_STUB(iemOp_Grp7_Amd_clgi);
|
---|
983 |
|
---|
984 | /** Opcode 0x0f 0x01 0xde. */
|
---|
985 | FNIEMOP_UD_STUB(iemOp_Grp7_Amd_skinit);
|
---|
986 |
|
---|
987 | /** Opcode 0x0f 0x01 0xdf. */
|
---|
988 | FNIEMOP_UD_STUB(iemOp_Grp7_Amd_invlpga);
|
---|
989 |
|
---|
990 | /** Opcode 0x0f 0x01 /4. */
|
---|
991 | FNIEMOP_DEF_1(iemOp_Grp7_smsw, uint8_t, bRm)
|
---|
992 | {
|
---|
993 | IEMOP_MNEMONIC("smsw");
|
---|
994 | IEMOP_HLP_MIN_286();
|
---|
995 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
996 | {
|
---|
997 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
998 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
999 | {
|
---|
1000 | case IEMMODE_16BIT:
|
---|
1001 | IEM_MC_BEGIN(0, 1);
|
---|
1002 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
1003 | IEM_MC_FETCH_CR0_U16(u16Tmp);
|
---|
1004 | if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
|
---|
1005 | { /* likely */ }
|
---|
1006 | else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
|
---|
1007 | IEM_MC_OR_LOCAL_U16(u16Tmp, 0xffe0);
|
---|
1008 | else
|
---|
1009 | IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0);
|
---|
1010 | IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Tmp);
|
---|
1011 | IEM_MC_ADVANCE_RIP();
|
---|
1012 | IEM_MC_END();
|
---|
1013 | return VINF_SUCCESS;
|
---|
1014 |
|
---|
1015 | case IEMMODE_32BIT:
|
---|
1016 | IEM_MC_BEGIN(0, 1);
|
---|
1017 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
1018 | IEM_MC_FETCH_CR0_U32(u32Tmp);
|
---|
1019 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
|
---|
1020 | IEM_MC_ADVANCE_RIP();
|
---|
1021 | IEM_MC_END();
|
---|
1022 | return VINF_SUCCESS;
|
---|
1023 |
|
---|
1024 | case IEMMODE_64BIT:
|
---|
1025 | IEM_MC_BEGIN(0, 1);
|
---|
1026 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
1027 | IEM_MC_FETCH_CR0_U64(u64Tmp);
|
---|
1028 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
|
---|
1029 | IEM_MC_ADVANCE_RIP();
|
---|
1030 | IEM_MC_END();
|
---|
1031 | return VINF_SUCCESS;
|
---|
1032 |
|
---|
1033 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
1034 | }
|
---|
1035 | }
|
---|
1036 | else
|
---|
1037 | {
|
---|
1038 | /* Ignore operand size here, memory refs are always 16-bit. */
|
---|
1039 | IEM_MC_BEGIN(0, 2);
|
---|
1040 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
1041 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
1042 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
1043 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1044 | IEM_MC_FETCH_CR0_U16(u16Tmp);
|
---|
1045 | if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
|
---|
1046 | { /* likely */ }
|
---|
1047 | else if (pVCpu->iem.s.uTargetCpu >= IEMTARGETCPU_386)
|
---|
1048 | IEM_MC_OR_LOCAL_U16(u16Tmp, 0xffe0);
|
---|
1049 | else
|
---|
1050 | IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0);
|
---|
1051 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tmp);
|
---|
1052 | IEM_MC_ADVANCE_RIP();
|
---|
1053 | IEM_MC_END();
|
---|
1054 | return VINF_SUCCESS;
|
---|
1055 | }
|
---|
1056 | }
|
---|
1057 |
|
---|
1058 |
|
---|
1059 | /** Opcode 0x0f 0x01 /6. */
|
---|
1060 | FNIEMOP_DEF_1(iemOp_Grp7_lmsw, uint8_t, bRm)
|
---|
1061 | {
|
---|
1062 | /* The operand size is effectively ignored, all is 16-bit and only the
|
---|
1063 | lower 3-bits are used. */
|
---|
1064 | IEMOP_MNEMONIC("lmsw");
|
---|
1065 | IEMOP_HLP_MIN_286();
|
---|
1066 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1067 | {
|
---|
1068 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1069 | IEM_MC_BEGIN(1, 0);
|
---|
1070 | IEM_MC_ARG(uint16_t, u16Tmp, 0);
|
---|
1071 | IEM_MC_FETCH_GREG_U16(u16Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
1072 | IEM_MC_CALL_CIMPL_1(iemCImpl_lmsw, u16Tmp);
|
---|
1073 | IEM_MC_END();
|
---|
1074 | }
|
---|
1075 | else
|
---|
1076 | {
|
---|
1077 | IEM_MC_BEGIN(1, 1);
|
---|
1078 | IEM_MC_ARG(uint16_t, u16Tmp, 0);
|
---|
1079 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
1080 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
1081 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1082 | IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
1083 | IEM_MC_CALL_CIMPL_1(iemCImpl_lmsw, u16Tmp);
|
---|
1084 | IEM_MC_END();
|
---|
1085 | }
|
---|
1086 | return VINF_SUCCESS;
|
---|
1087 | }
|
---|
1088 |
|
---|
1089 |
|
---|
1090 | /** Opcode 0x0f 0x01 /7. */
|
---|
1091 | FNIEMOP_DEF_1(iemOp_Grp7_invlpg, uint8_t, bRm)
|
---|
1092 | {
|
---|
1093 | IEMOP_MNEMONIC("invlpg");
|
---|
1094 | IEMOP_HLP_MIN_486();
|
---|
1095 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1096 | IEM_MC_BEGIN(1, 1);
|
---|
1097 | IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 0);
|
---|
1098 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
1099 | IEM_MC_CALL_CIMPL_1(iemCImpl_invlpg, GCPtrEffDst);
|
---|
1100 | IEM_MC_END();
|
---|
1101 | return VINF_SUCCESS;
|
---|
1102 | }
|
---|
1103 |
|
---|
1104 |
|
---|
1105 | /** Opcode 0x0f 0x01 /7. */
|
---|
1106 | FNIEMOP_DEF(iemOp_Grp7_swapgs)
|
---|
1107 | {
|
---|
1108 | IEMOP_MNEMONIC("swapgs");
|
---|
1109 | IEMOP_HLP_ONLY_64BIT();
|
---|
1110 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1111 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_swapgs);
|
---|
1112 | }
|
---|
1113 |
|
---|
1114 |
|
---|
1115 | /** Opcode 0x0f 0x01 /7. */
|
---|
1116 | FNIEMOP_DEF(iemOp_Grp7_rdtscp)
|
---|
1117 | {
|
---|
1118 | NOREF(pVCpu);
|
---|
1119 | IEMOP_BITCH_ABOUT_STUB();
|
---|
1120 | return VERR_IEM_INSTR_NOT_IMPLEMENTED;
|
---|
1121 | }
|
---|
1122 |
|
---|
1123 |
|
---|
1124 | /** Opcode 0x0f 0x01. */
|
---|
1125 | FNIEMOP_DEF(iemOp_Grp7)
|
---|
1126 | {
|
---|
1127 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1128 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
1129 | {
|
---|
1130 | case 0:
|
---|
1131 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
1132 | return FNIEMOP_CALL_1(iemOp_Grp7_sgdt, bRm);
|
---|
1133 | switch (bRm & X86_MODRM_RM_MASK)
|
---|
1134 | {
|
---|
1135 | case 1: return FNIEMOP_CALL(iemOp_Grp7_vmcall);
|
---|
1136 | case 2: return FNIEMOP_CALL(iemOp_Grp7_vmlaunch);
|
---|
1137 | case 3: return FNIEMOP_CALL(iemOp_Grp7_vmresume);
|
---|
1138 | case 4: return FNIEMOP_CALL(iemOp_Grp7_vmxoff);
|
---|
1139 | }
|
---|
1140 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1141 |
|
---|
1142 | case 1:
|
---|
1143 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
1144 | return FNIEMOP_CALL_1(iemOp_Grp7_sidt, bRm);
|
---|
1145 | switch (bRm & X86_MODRM_RM_MASK)
|
---|
1146 | {
|
---|
1147 | case 0: return FNIEMOP_CALL(iemOp_Grp7_monitor);
|
---|
1148 | case 1: return FNIEMOP_CALL(iemOp_Grp7_mwait);
|
---|
1149 | }
|
---|
1150 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1151 |
|
---|
1152 | case 2:
|
---|
1153 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
1154 | return FNIEMOP_CALL_1(iemOp_Grp7_lgdt, bRm);
|
---|
1155 | switch (bRm & X86_MODRM_RM_MASK)
|
---|
1156 | {
|
---|
1157 | case 0: return FNIEMOP_CALL(iemOp_Grp7_xgetbv);
|
---|
1158 | case 1: return FNIEMOP_CALL(iemOp_Grp7_xsetbv);
|
---|
1159 | }
|
---|
1160 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1161 |
|
---|
1162 | case 3:
|
---|
1163 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
1164 | return FNIEMOP_CALL_1(iemOp_Grp7_lidt, bRm);
|
---|
1165 | switch (bRm & X86_MODRM_RM_MASK)
|
---|
1166 | {
|
---|
1167 | case 0: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmrun);
|
---|
1168 | case 1: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmmcall);
|
---|
1169 | case 2: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmload);
|
---|
1170 | case 3: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmsave);
|
---|
1171 | case 4: return FNIEMOP_CALL(iemOp_Grp7_Amd_stgi);
|
---|
1172 | case 5: return FNIEMOP_CALL(iemOp_Grp7_Amd_clgi);
|
---|
1173 | case 6: return FNIEMOP_CALL(iemOp_Grp7_Amd_skinit);
|
---|
1174 | case 7: return FNIEMOP_CALL(iemOp_Grp7_Amd_invlpga);
|
---|
1175 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
1176 | }
|
---|
1177 |
|
---|
1178 | case 4:
|
---|
1179 | return FNIEMOP_CALL_1(iemOp_Grp7_smsw, bRm);
|
---|
1180 |
|
---|
1181 | case 5:
|
---|
1182 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1183 |
|
---|
1184 | case 6:
|
---|
1185 | return FNIEMOP_CALL_1(iemOp_Grp7_lmsw, bRm);
|
---|
1186 |
|
---|
1187 | case 7:
|
---|
1188 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
1189 | return FNIEMOP_CALL_1(iemOp_Grp7_invlpg, bRm);
|
---|
1190 | switch (bRm & X86_MODRM_RM_MASK)
|
---|
1191 | {
|
---|
1192 | case 0: return FNIEMOP_CALL(iemOp_Grp7_swapgs);
|
---|
1193 | case 1: return FNIEMOP_CALL(iemOp_Grp7_rdtscp);
|
---|
1194 | }
|
---|
1195 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1196 |
|
---|
1197 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
1198 | }
|
---|
1199 | }
|
---|
1200 |
|
---|
1201 | /** Opcode 0x0f 0x00 /3. */
|
---|
1202 | FNIEMOP_DEF_1(iemOpCommonLarLsl_Gv_Ew, bool, fIsLar)
|
---|
1203 | {
|
---|
1204 | IEMOP_HLP_NO_REAL_OR_V86_MODE();
|
---|
1205 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1206 |
|
---|
1207 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1208 | {
|
---|
1209 | IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_REG, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
1210 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
1211 | {
|
---|
1212 | case IEMMODE_16BIT:
|
---|
1213 | {
|
---|
1214 | IEM_MC_BEGIN(4, 0);
|
---|
1215 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
1216 | IEM_MC_ARG(uint16_t, u16Sel, 1);
|
---|
1217 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
1218 | IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 3);
|
---|
1219 |
|
---|
1220 | IEM_MC_REF_GREG_U16(pu16Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1221 | IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
1222 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
1223 | IEM_MC_CALL_CIMPL_4(iemCImpl_LarLsl_u16, pu16Dst, u16Sel, pEFlags, fIsLarArg);
|
---|
1224 |
|
---|
1225 | IEM_MC_END();
|
---|
1226 | return VINF_SUCCESS;
|
---|
1227 | }
|
---|
1228 |
|
---|
1229 | case IEMMODE_32BIT:
|
---|
1230 | case IEMMODE_64BIT:
|
---|
1231 | {
|
---|
1232 | IEM_MC_BEGIN(4, 0);
|
---|
1233 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
1234 | IEM_MC_ARG(uint16_t, u16Sel, 1);
|
---|
1235 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
1236 | IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 3);
|
---|
1237 |
|
---|
1238 | IEM_MC_REF_GREG_U64(pu64Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1239 | IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
1240 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
1241 | IEM_MC_CALL_CIMPL_4(iemCImpl_LarLsl_u64, pu64Dst, u16Sel, pEFlags, fIsLarArg);
|
---|
1242 |
|
---|
1243 | IEM_MC_END();
|
---|
1244 | return VINF_SUCCESS;
|
---|
1245 | }
|
---|
1246 |
|
---|
1247 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
1248 | }
|
---|
1249 | }
|
---|
1250 | else
|
---|
1251 | {
|
---|
1252 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
1253 | {
|
---|
1254 | case IEMMODE_16BIT:
|
---|
1255 | {
|
---|
1256 | IEM_MC_BEGIN(4, 1);
|
---|
1257 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
1258 | IEM_MC_ARG(uint16_t, u16Sel, 1);
|
---|
1259 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
1260 | IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 3);
|
---|
1261 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1262 |
|
---|
1263 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1264 | IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_MEM, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
1265 |
|
---|
1266 | IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
1267 | IEM_MC_REF_GREG_U16(pu16Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1268 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
1269 | IEM_MC_CALL_CIMPL_4(iemCImpl_LarLsl_u16, pu16Dst, u16Sel, pEFlags, fIsLarArg);
|
---|
1270 |
|
---|
1271 | IEM_MC_END();
|
---|
1272 | return VINF_SUCCESS;
|
---|
1273 | }
|
---|
1274 |
|
---|
1275 | case IEMMODE_32BIT:
|
---|
1276 | case IEMMODE_64BIT:
|
---|
1277 | {
|
---|
1278 | IEM_MC_BEGIN(4, 1);
|
---|
1279 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
1280 | IEM_MC_ARG(uint16_t, u16Sel, 1);
|
---|
1281 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
1282 | IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 3);
|
---|
1283 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1284 |
|
---|
1285 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1286 | IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_MEM, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED_NOTRAP);
|
---|
1287 | /** @todo testcase: make sure it's a 16-bit read. */
|
---|
1288 |
|
---|
1289 | IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
1290 | IEM_MC_REF_GREG_U64(pu64Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1291 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
1292 | IEM_MC_CALL_CIMPL_4(iemCImpl_LarLsl_u64, pu64Dst, u16Sel, pEFlags, fIsLarArg);
|
---|
1293 |
|
---|
1294 | IEM_MC_END();
|
---|
1295 | return VINF_SUCCESS;
|
---|
1296 | }
|
---|
1297 |
|
---|
1298 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
1299 | }
|
---|
1300 | }
|
---|
1301 | }
|
---|
1302 |
|
---|
1303 |
|
---|
1304 |
|
---|
1305 | /** Opcode 0x0f 0x02. */
|
---|
1306 | FNIEMOP_DEF(iemOp_lar_Gv_Ew)
|
---|
1307 | {
|
---|
1308 | IEMOP_MNEMONIC("lar Gv,Ew");
|
---|
1309 | return FNIEMOP_CALL_1(iemOpCommonLarLsl_Gv_Ew, true);
|
---|
1310 | }
|
---|
1311 |
|
---|
1312 |
|
---|
1313 | /** Opcode 0x0f 0x03. */
|
---|
1314 | FNIEMOP_DEF(iemOp_lsl_Gv_Ew)
|
---|
1315 | {
|
---|
1316 | IEMOP_MNEMONIC("lsl Gv,Ew");
|
---|
1317 | return FNIEMOP_CALL_1(iemOpCommonLarLsl_Gv_Ew, false);
|
---|
1318 | }
|
---|
1319 |
|
---|
1320 |
|
---|
1321 | /** Opcode 0x0f 0x05. */
|
---|
1322 | FNIEMOP_DEF(iemOp_syscall)
|
---|
1323 | {
|
---|
1324 | IEMOP_MNEMONIC("syscall"); /** @todo 286 LOADALL */
|
---|
1325 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1326 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_syscall);
|
---|
1327 | }
|
---|
1328 |
|
---|
1329 |
|
---|
1330 | /** Opcode 0x0f 0x06. */
|
---|
1331 | FNIEMOP_DEF(iemOp_clts)
|
---|
1332 | {
|
---|
1333 | IEMOP_MNEMONIC("clts");
|
---|
1334 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1335 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_clts);
|
---|
1336 | }
|
---|
1337 |
|
---|
1338 |
|
---|
1339 | /** Opcode 0x0f 0x07. */
|
---|
1340 | FNIEMOP_DEF(iemOp_sysret)
|
---|
1341 | {
|
---|
1342 | IEMOP_MNEMONIC("sysret"); /** @todo 386 LOADALL */
|
---|
1343 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1344 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_sysret);
|
---|
1345 | }
|
---|
1346 |
|
---|
1347 |
|
---|
1348 | /** Opcode 0x0f 0x08. */
|
---|
1349 | FNIEMOP_STUB(iemOp_invd);
|
---|
1350 | // IEMOP_HLP_MIN_486();
|
---|
1351 |
|
---|
1352 |
|
---|
1353 | /** Opcode 0x0f 0x09. */
|
---|
1354 | FNIEMOP_DEF(iemOp_wbinvd)
|
---|
1355 | {
|
---|
1356 | IEMOP_MNEMONIC("wbinvd");
|
---|
1357 | IEMOP_HLP_MIN_486();
|
---|
1358 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1359 | IEM_MC_BEGIN(0, 0);
|
---|
1360 | IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO();
|
---|
1361 | IEM_MC_ADVANCE_RIP();
|
---|
1362 | IEM_MC_END();
|
---|
1363 | return VINF_SUCCESS; /* ignore for now */
|
---|
1364 | }
|
---|
1365 |
|
---|
1366 |
|
---|
1367 | /** Opcode 0x0f 0x0b. */
|
---|
1368 | FNIEMOP_DEF(iemOp_ud2)
|
---|
1369 | {
|
---|
1370 | IEMOP_MNEMONIC("ud2");
|
---|
1371 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1372 | }
|
---|
1373 |
|
---|
1374 | /** Opcode 0x0f 0x0d. */
|
---|
1375 | FNIEMOP_DEF(iemOp_nop_Ev_GrpP)
|
---|
1376 | {
|
---|
1377 | /* AMD prefetch group, Intel implements this as NOP Ev (and so do we). */
|
---|
1378 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->f3DNowPrefetch)
|
---|
1379 | {
|
---|
1380 | IEMOP_MNEMONIC("GrpP");
|
---|
1381 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1382 | }
|
---|
1383 |
|
---|
1384 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1385 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1386 | {
|
---|
1387 | IEMOP_MNEMONIC("GrpP");
|
---|
1388 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1389 | }
|
---|
1390 |
|
---|
1391 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
1392 | {
|
---|
1393 | case 2: /* Aliased to /0 for the time being. */
|
---|
1394 | case 4: /* Aliased to /0 for the time being. */
|
---|
1395 | case 5: /* Aliased to /0 for the time being. */
|
---|
1396 | case 6: /* Aliased to /0 for the time being. */
|
---|
1397 | case 7: /* Aliased to /0 for the time being. */
|
---|
1398 | case 0: IEMOP_MNEMONIC("prefetch"); break;
|
---|
1399 | case 1: IEMOP_MNEMONIC("prefetchw"); break;
|
---|
1400 | case 3: IEMOP_MNEMONIC("prefetchw"); break;
|
---|
1401 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
1402 | }
|
---|
1403 |
|
---|
1404 | IEM_MC_BEGIN(0, 1);
|
---|
1405 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1406 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1407 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1408 | /* Currently a NOP. */
|
---|
1409 | NOREF(GCPtrEffSrc);
|
---|
1410 | IEM_MC_ADVANCE_RIP();
|
---|
1411 | IEM_MC_END();
|
---|
1412 | return VINF_SUCCESS;
|
---|
1413 | }
|
---|
1414 |
|
---|
1415 |
|
---|
1416 | /** Opcode 0x0f 0x0e. */
|
---|
1417 | FNIEMOP_STUB(iemOp_femms);
|
---|
1418 |
|
---|
1419 |
|
---|
1420 | /** Opcode 0x0f 0x0f 0x0c. */
|
---|
1421 | FNIEMOP_STUB(iemOp_3Dnow_pi2fw_Pq_Qq);
|
---|
1422 |
|
---|
1423 | /** Opcode 0x0f 0x0f 0x0d. */
|
---|
1424 | FNIEMOP_STUB(iemOp_3Dnow_pi2fd_Pq_Qq);
|
---|
1425 |
|
---|
1426 | /** Opcode 0x0f 0x0f 0x1c. */
|
---|
1427 | FNIEMOP_STUB(iemOp_3Dnow_pf2fw_Pq_Qq);
|
---|
1428 |
|
---|
1429 | /** Opcode 0x0f 0x0f 0x1d. */
|
---|
1430 | FNIEMOP_STUB(iemOp_3Dnow_pf2fd_Pq_Qq);
|
---|
1431 |
|
---|
1432 | /** Opcode 0x0f 0x0f 0x8a. */
|
---|
1433 | FNIEMOP_STUB(iemOp_3Dnow_pfnacc_Pq_Qq);
|
---|
1434 |
|
---|
1435 | /** Opcode 0x0f 0x0f 0x8e. */
|
---|
1436 | FNIEMOP_STUB(iemOp_3Dnow_pfpnacc_Pq_Qq);
|
---|
1437 |
|
---|
1438 | /** Opcode 0x0f 0x0f 0x90. */
|
---|
1439 | FNIEMOP_STUB(iemOp_3Dnow_pfcmpge_Pq_Qq);
|
---|
1440 |
|
---|
1441 | /** Opcode 0x0f 0x0f 0x94. */
|
---|
1442 | FNIEMOP_STUB(iemOp_3Dnow_pfmin_Pq_Qq);
|
---|
1443 |
|
---|
1444 | /** Opcode 0x0f 0x0f 0x96. */
|
---|
1445 | FNIEMOP_STUB(iemOp_3Dnow_pfrcp_Pq_Qq);
|
---|
1446 |
|
---|
1447 | /** Opcode 0x0f 0x0f 0x97. */
|
---|
1448 | FNIEMOP_STUB(iemOp_3Dnow_pfrsqrt_Pq_Qq);
|
---|
1449 |
|
---|
1450 | /** Opcode 0x0f 0x0f 0x9a. */
|
---|
1451 | FNIEMOP_STUB(iemOp_3Dnow_pfsub_Pq_Qq);
|
---|
1452 |
|
---|
1453 | /** Opcode 0x0f 0x0f 0x9e. */
|
---|
1454 | FNIEMOP_STUB(iemOp_3Dnow_pfadd_PQ_Qq);
|
---|
1455 |
|
---|
1456 | /** Opcode 0x0f 0x0f 0xa0. */
|
---|
1457 | FNIEMOP_STUB(iemOp_3Dnow_pfcmpgt_Pq_Qq);
|
---|
1458 |
|
---|
1459 | /** Opcode 0x0f 0x0f 0xa4. */
|
---|
1460 | FNIEMOP_STUB(iemOp_3Dnow_pfmax_Pq_Qq);
|
---|
1461 |
|
---|
1462 | /** Opcode 0x0f 0x0f 0xa6. */
|
---|
1463 | FNIEMOP_STUB(iemOp_3Dnow_pfrcpit1_Pq_Qq);
|
---|
1464 |
|
---|
1465 | /** Opcode 0x0f 0x0f 0xa7. */
|
---|
1466 | FNIEMOP_STUB(iemOp_3Dnow_pfrsqit1_Pq_Qq);
|
---|
1467 |
|
---|
1468 | /** Opcode 0x0f 0x0f 0xaa. */
|
---|
1469 | FNIEMOP_STUB(iemOp_3Dnow_pfsubr_Pq_Qq);
|
---|
1470 |
|
---|
1471 | /** Opcode 0x0f 0x0f 0xae. */
|
---|
1472 | FNIEMOP_STUB(iemOp_3Dnow_pfacc_PQ_Qq);
|
---|
1473 |
|
---|
1474 | /** Opcode 0x0f 0x0f 0xb0. */
|
---|
1475 | FNIEMOP_STUB(iemOp_3Dnow_pfcmpeq_Pq_Qq);
|
---|
1476 |
|
---|
1477 | /** Opcode 0x0f 0x0f 0xb4. */
|
---|
1478 | FNIEMOP_STUB(iemOp_3Dnow_pfmul_Pq_Qq);
|
---|
1479 |
|
---|
1480 | /** Opcode 0x0f 0x0f 0xb6. */
|
---|
1481 | FNIEMOP_STUB(iemOp_3Dnow_pfrcpit2_Pq_Qq);
|
---|
1482 |
|
---|
1483 | /** Opcode 0x0f 0x0f 0xb7. */
|
---|
1484 | FNIEMOP_STUB(iemOp_3Dnow_pmulhrw_Pq_Qq);
|
---|
1485 |
|
---|
1486 | /** Opcode 0x0f 0x0f 0xbb. */
|
---|
1487 | FNIEMOP_STUB(iemOp_3Dnow_pswapd_Pq_Qq);
|
---|
1488 |
|
---|
1489 | /** Opcode 0x0f 0x0f 0xbf. */
|
---|
1490 | FNIEMOP_STUB(iemOp_3Dnow_pavgusb_PQ_Qq);
|
---|
1491 |
|
---|
1492 |
|
---|
1493 | /** Opcode 0x0f 0x0f. */
|
---|
1494 | FNIEMOP_DEF(iemOp_3Dnow)
|
---|
1495 | {
|
---|
1496 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->f3DNow)
|
---|
1497 | {
|
---|
1498 | IEMOP_MNEMONIC("3Dnow");
|
---|
1499 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1500 | }
|
---|
1501 |
|
---|
1502 | /* This is pretty sparse, use switch instead of table. */
|
---|
1503 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
1504 | switch (b)
|
---|
1505 | {
|
---|
1506 | case 0x0c: return FNIEMOP_CALL(iemOp_3Dnow_pi2fw_Pq_Qq);
|
---|
1507 | case 0x0d: return FNIEMOP_CALL(iemOp_3Dnow_pi2fd_Pq_Qq);
|
---|
1508 | case 0x1c: return FNIEMOP_CALL(iemOp_3Dnow_pf2fw_Pq_Qq);
|
---|
1509 | case 0x1d: return FNIEMOP_CALL(iemOp_3Dnow_pf2fd_Pq_Qq);
|
---|
1510 | case 0x8a: return FNIEMOP_CALL(iemOp_3Dnow_pfnacc_Pq_Qq);
|
---|
1511 | case 0x8e: return FNIEMOP_CALL(iemOp_3Dnow_pfpnacc_Pq_Qq);
|
---|
1512 | case 0x90: return FNIEMOP_CALL(iemOp_3Dnow_pfcmpge_Pq_Qq);
|
---|
1513 | case 0x94: return FNIEMOP_CALL(iemOp_3Dnow_pfmin_Pq_Qq);
|
---|
1514 | case 0x96: return FNIEMOP_CALL(iemOp_3Dnow_pfrcp_Pq_Qq);
|
---|
1515 | case 0x97: return FNIEMOP_CALL(iemOp_3Dnow_pfrsqrt_Pq_Qq);
|
---|
1516 | case 0x9a: return FNIEMOP_CALL(iemOp_3Dnow_pfsub_Pq_Qq);
|
---|
1517 | case 0x9e: return FNIEMOP_CALL(iemOp_3Dnow_pfadd_PQ_Qq);
|
---|
1518 | case 0xa0: return FNIEMOP_CALL(iemOp_3Dnow_pfcmpgt_Pq_Qq);
|
---|
1519 | case 0xa4: return FNIEMOP_CALL(iemOp_3Dnow_pfmax_Pq_Qq);
|
---|
1520 | case 0xa6: return FNIEMOP_CALL(iemOp_3Dnow_pfrcpit1_Pq_Qq);
|
---|
1521 | case 0xa7: return FNIEMOP_CALL(iemOp_3Dnow_pfrsqit1_Pq_Qq);
|
---|
1522 | case 0xaa: return FNIEMOP_CALL(iemOp_3Dnow_pfsubr_Pq_Qq);
|
---|
1523 | case 0xae: return FNIEMOP_CALL(iemOp_3Dnow_pfacc_PQ_Qq);
|
---|
1524 | case 0xb0: return FNIEMOP_CALL(iemOp_3Dnow_pfcmpeq_Pq_Qq);
|
---|
1525 | case 0xb4: return FNIEMOP_CALL(iemOp_3Dnow_pfmul_Pq_Qq);
|
---|
1526 | case 0xb6: return FNIEMOP_CALL(iemOp_3Dnow_pfrcpit2_Pq_Qq);
|
---|
1527 | case 0xb7: return FNIEMOP_CALL(iemOp_3Dnow_pmulhrw_Pq_Qq);
|
---|
1528 | case 0xbb: return FNIEMOP_CALL(iemOp_3Dnow_pswapd_Pq_Qq);
|
---|
1529 | case 0xbf: return FNIEMOP_CALL(iemOp_3Dnow_pavgusb_PQ_Qq);
|
---|
1530 | default:
|
---|
1531 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1532 | }
|
---|
1533 | }
|
---|
1534 |
|
---|
1535 |
|
---|
1536 | /** Opcode 0x0f 0x10. */
|
---|
1537 | FNIEMOP_STUB(iemOp_movups_Vps_Wps__movupd_Vpd_Wpd__movss_Vss_Wss__movsd_Vsd_Wsd);
|
---|
1538 |
|
---|
1539 |
|
---|
1540 | /** Opcode 0x0f 0x11. */
|
---|
1541 | FNIEMOP_DEF(iemOp_movups_Wps_Vps__movupd_Wpd_Vpd__movss_Wss_Vss__movsd_Vsd_Wsd)
|
---|
1542 | {
|
---|
1543 | /* Quick hack. Need to restructure all of this later some time. */
|
---|
1544 | uint32_t const fRelevantPrefix = pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ);
|
---|
1545 | if (fRelevantPrefix == 0)
|
---|
1546 | {
|
---|
1547 | IEMOP_MNEMONIC("movups Wps,Vps");
|
---|
1548 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1549 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1550 | {
|
---|
1551 | /*
|
---|
1552 | * Register, register.
|
---|
1553 | */
|
---|
1554 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
|
---|
1555 | IEM_MC_BEGIN(0, 0);
|
---|
1556 | IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
|
---|
1557 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
1558 | IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
|
---|
1559 | ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1560 | IEM_MC_ADVANCE_RIP();
|
---|
1561 | IEM_MC_END();
|
---|
1562 | }
|
---|
1563 | else
|
---|
1564 | {
|
---|
1565 | /*
|
---|
1566 | * Memory, register.
|
---|
1567 | */
|
---|
1568 | IEM_MC_BEGIN(0, 2);
|
---|
1569 | IEM_MC_LOCAL(uint128_t, uSrc); /** @todo optimize this one day... */
|
---|
1570 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1571 |
|
---|
1572 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1573 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); /** @todo check if this is delayed this long for REPZ/NZ - yes it generally is! */
|
---|
1574 | IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
|
---|
1575 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
|
---|
1576 |
|
---|
1577 | IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1578 | IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
|
---|
1579 |
|
---|
1580 | IEM_MC_ADVANCE_RIP();
|
---|
1581 | IEM_MC_END();
|
---|
1582 | }
|
---|
1583 | }
|
---|
1584 | else if (fRelevantPrefix == IEM_OP_PRF_REPNZ)
|
---|
1585 | {
|
---|
1586 | IEMOP_MNEMONIC("movsd Wsd,Vsd");
|
---|
1587 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1588 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1589 | {
|
---|
1590 | /*
|
---|
1591 | * Register, register.
|
---|
1592 | */
|
---|
1593 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1594 | IEM_MC_BEGIN(0, 1);
|
---|
1595 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
1596 |
|
---|
1597 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
1598 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
1599 | IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1600 | IEM_MC_STORE_XREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
|
---|
1601 |
|
---|
1602 | IEM_MC_ADVANCE_RIP();
|
---|
1603 | IEM_MC_END();
|
---|
1604 | }
|
---|
1605 | else
|
---|
1606 | {
|
---|
1607 | /*
|
---|
1608 | * Memory, register.
|
---|
1609 | */
|
---|
1610 | IEM_MC_BEGIN(0, 2);
|
---|
1611 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
1612 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1613 |
|
---|
1614 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1615 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1616 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
1617 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
|
---|
1618 |
|
---|
1619 | IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1620 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
|
---|
1621 |
|
---|
1622 | IEM_MC_ADVANCE_RIP();
|
---|
1623 | IEM_MC_END();
|
---|
1624 | }
|
---|
1625 | }
|
---|
1626 | else
|
---|
1627 | {
|
---|
1628 | IEMOP_BITCH_ABOUT_STUB();
|
---|
1629 | return VERR_IEM_INSTR_NOT_IMPLEMENTED;
|
---|
1630 | }
|
---|
1631 | return VINF_SUCCESS;
|
---|
1632 | }
|
---|
1633 |
|
---|
1634 |
|
---|
1635 | /** Opcode 0x0f 0x12. */
|
---|
1636 | FNIEMOP_STUB(iemOp_movlps_Vq_Mq__movhlps_Vq_Uq__movlpd_Vq_Mq__movsldup_Vq_Wq__movddup_Vq_Wq); //NEXT
|
---|
1637 |
|
---|
1638 |
|
---|
1639 | /** Opcode 0x0f 0x13. */
|
---|
1640 | FNIEMOP_DEF(iemOp_movlps_Mq_Vq__movlpd_Mq_Vq)
|
---|
1641 | {
|
---|
1642 | /* Quick hack. Need to restructure all of this later some time. */
|
---|
1643 | if (pVCpu->iem.s.fPrefixes == IEM_OP_PRF_SIZE_OP)
|
---|
1644 | {
|
---|
1645 | IEMOP_MNEMONIC("movlpd Mq,Vq");
|
---|
1646 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1647 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1648 | {
|
---|
1649 | #if 0
|
---|
1650 | /*
|
---|
1651 | * Register, register.
|
---|
1652 | */
|
---|
1653 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
|
---|
1654 | IEM_MC_BEGIN(0, 1);
|
---|
1655 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
1656 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
1657 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
1658 | IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1659 | IEM_MC_STORE_XREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
|
---|
1660 | IEM_MC_ADVANCE_RIP();
|
---|
1661 | IEM_MC_END();
|
---|
1662 | #else
|
---|
1663 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1664 | #endif
|
---|
1665 | }
|
---|
1666 | else
|
---|
1667 | {
|
---|
1668 | /*
|
---|
1669 | * Memory, register.
|
---|
1670 | */
|
---|
1671 | IEM_MC_BEGIN(0, 2);
|
---|
1672 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
1673 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1674 |
|
---|
1675 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1676 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); /** @todo check if this is delayed this long for REPZ/NZ - yes it generally is! */
|
---|
1677 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
1678 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
|
---|
1679 |
|
---|
1680 | IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1681 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
|
---|
1682 |
|
---|
1683 | IEM_MC_ADVANCE_RIP();
|
---|
1684 | IEM_MC_END();
|
---|
1685 | }
|
---|
1686 | return VINF_SUCCESS;
|
---|
1687 | }
|
---|
1688 |
|
---|
1689 | IEMOP_BITCH_ABOUT_STUB();
|
---|
1690 | return VERR_IEM_INSTR_NOT_IMPLEMENTED;
|
---|
1691 | }
|
---|
1692 |
|
---|
1693 |
|
---|
1694 | /** Opcode 0x0f 0x14. */
|
---|
1695 | FNIEMOP_STUB(iemOp_unpckhlps_Vps_Wq__unpcklpd_Vpd_Wq);
|
---|
1696 | /** Opcode 0x0f 0x15. */
|
---|
1697 | FNIEMOP_STUB(iemOp_unpckhps_Vps_Wq__unpckhpd_Vpd_Wq);
|
---|
1698 | /** Opcode 0x0f 0x16. */
|
---|
1699 | FNIEMOP_STUB(iemOp_movhps_Vq_Mq__movlhps_Vq_Uq__movhpd_Vq_Mq__movshdup_Vq_Wq); //NEXT
|
---|
1700 | /** Opcode 0x0f 0x17. */
|
---|
1701 | FNIEMOP_STUB(iemOp_movhps_Mq_Vq__movhpd_Mq_Vq); //NEXT
|
---|
1702 |
|
---|
1703 |
|
---|
1704 | /** Opcode 0x0f 0x18. */
|
---|
1705 | FNIEMOP_DEF(iemOp_prefetch_Grp16)
|
---|
1706 | {
|
---|
1707 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1708 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
1709 | {
|
---|
1710 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
1711 | {
|
---|
1712 | case 4: /* Aliased to /0 for the time being according to AMD. */
|
---|
1713 | case 5: /* Aliased to /0 for the time being according to AMD. */
|
---|
1714 | case 6: /* Aliased to /0 for the time being according to AMD. */
|
---|
1715 | case 7: /* Aliased to /0 for the time being according to AMD. */
|
---|
1716 | case 0: IEMOP_MNEMONIC("prefetchNTA m8"); break;
|
---|
1717 | case 1: IEMOP_MNEMONIC("prefetchT0 m8"); break;
|
---|
1718 | case 2: IEMOP_MNEMONIC("prefetchT1 m8"); break;
|
---|
1719 | case 3: IEMOP_MNEMONIC("prefetchT2 m8"); break;
|
---|
1720 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
1721 | }
|
---|
1722 |
|
---|
1723 | IEM_MC_BEGIN(0, 1);
|
---|
1724 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1725 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1726 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1727 | /* Currently a NOP. */
|
---|
1728 | NOREF(GCPtrEffSrc);
|
---|
1729 | IEM_MC_ADVANCE_RIP();
|
---|
1730 | IEM_MC_END();
|
---|
1731 | return VINF_SUCCESS;
|
---|
1732 | }
|
---|
1733 |
|
---|
1734 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1735 | }
|
---|
1736 |
|
---|
1737 |
|
---|
1738 | /** Opcode 0x0f 0x19..0x1f. */
|
---|
1739 | FNIEMOP_DEF(iemOp_nop_Ev)
|
---|
1740 | {
|
---|
1741 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1742 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1743 | {
|
---|
1744 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1745 | IEM_MC_BEGIN(0, 0);
|
---|
1746 | IEM_MC_ADVANCE_RIP();
|
---|
1747 | IEM_MC_END();
|
---|
1748 | }
|
---|
1749 | else
|
---|
1750 | {
|
---|
1751 | IEM_MC_BEGIN(0, 1);
|
---|
1752 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1753 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1754 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1755 | /* Currently a NOP. */
|
---|
1756 | NOREF(GCPtrEffSrc);
|
---|
1757 | IEM_MC_ADVANCE_RIP();
|
---|
1758 | IEM_MC_END();
|
---|
1759 | }
|
---|
1760 | return VINF_SUCCESS;
|
---|
1761 | }
|
---|
1762 |
|
---|
1763 |
|
---|
1764 | /** Opcode 0x0f 0x20. */
|
---|
1765 | FNIEMOP_DEF(iemOp_mov_Rd_Cd)
|
---|
1766 | {
|
---|
1767 | /* mod is ignored, as is operand size overrides. */
|
---|
1768 | IEMOP_MNEMONIC("mov Rd,Cd");
|
---|
1769 | IEMOP_HLP_MIN_386();
|
---|
1770 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
1771 | pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
|
---|
1772 | else
|
---|
1773 | pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_32BIT;
|
---|
1774 |
|
---|
1775 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1776 | uint8_t iCrReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
|
---|
1777 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)
|
---|
1778 | {
|
---|
1779 | /* The lock prefix can be used to encode CR8 accesses on some CPUs. */
|
---|
1780 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCr8In32Bit)
|
---|
1781 | return IEMOP_RAISE_INVALID_OPCODE(); /* #UD takes precedence over #GP(), see test. */
|
---|
1782 | iCrReg |= 8;
|
---|
1783 | }
|
---|
1784 | switch (iCrReg)
|
---|
1785 | {
|
---|
1786 | case 0: case 2: case 3: case 4: case 8:
|
---|
1787 | break;
|
---|
1788 | default:
|
---|
1789 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1790 | }
|
---|
1791 | IEMOP_HLP_DONE_DECODING();
|
---|
1792 |
|
---|
1793 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Cd, (X86_MODRM_RM_MASK & bRm) | pVCpu->iem.s.uRexB, iCrReg);
|
---|
1794 | }
|
---|
1795 |
|
---|
1796 |
|
---|
1797 | /** Opcode 0x0f 0x21. */
|
---|
1798 | FNIEMOP_DEF(iemOp_mov_Rd_Dd)
|
---|
1799 | {
|
---|
1800 | IEMOP_MNEMONIC("mov Rd,Dd");
|
---|
1801 | IEMOP_HLP_MIN_386();
|
---|
1802 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1803 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1804 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R)
|
---|
1805 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1806 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Dd,
|
---|
1807 | (X86_MODRM_RM_MASK & bRm) | pVCpu->iem.s.uRexB,
|
---|
1808 | ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK));
|
---|
1809 | }
|
---|
1810 |
|
---|
1811 |
|
---|
1812 | /** Opcode 0x0f 0x22. */
|
---|
1813 | FNIEMOP_DEF(iemOp_mov_Cd_Rd)
|
---|
1814 | {
|
---|
1815 | /* mod is ignored, as is operand size overrides. */
|
---|
1816 | IEMOP_MNEMONIC("mov Cd,Rd");
|
---|
1817 | IEMOP_HLP_MIN_386();
|
---|
1818 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
1819 | pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
|
---|
1820 | else
|
---|
1821 | pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_32BIT;
|
---|
1822 |
|
---|
1823 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1824 | uint8_t iCrReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
|
---|
1825 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)
|
---|
1826 | {
|
---|
1827 | /* The lock prefix can be used to encode CR8 accesses on some CPUs. */
|
---|
1828 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCr8In32Bit)
|
---|
1829 | return IEMOP_RAISE_INVALID_OPCODE(); /* #UD takes precedence over #GP(), see test. */
|
---|
1830 | iCrReg |= 8;
|
---|
1831 | }
|
---|
1832 | switch (iCrReg)
|
---|
1833 | {
|
---|
1834 | case 0: case 2: case 3: case 4: case 8:
|
---|
1835 | break;
|
---|
1836 | default:
|
---|
1837 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1838 | }
|
---|
1839 | IEMOP_HLP_DONE_DECODING();
|
---|
1840 |
|
---|
1841 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Cd_Rd, iCrReg, (X86_MODRM_RM_MASK & bRm) | pVCpu->iem.s.uRexB);
|
---|
1842 | }
|
---|
1843 |
|
---|
1844 |
|
---|
1845 | /** Opcode 0x0f 0x23. */
|
---|
1846 | FNIEMOP_DEF(iemOp_mov_Dd_Rd)
|
---|
1847 | {
|
---|
1848 | IEMOP_MNEMONIC("mov Dd,Rd");
|
---|
1849 | IEMOP_HLP_MIN_386();
|
---|
1850 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1851 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
1852 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R)
|
---|
1853 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1854 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Dd_Rd,
|
---|
1855 | ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK),
|
---|
1856 | (X86_MODRM_RM_MASK & bRm) | pVCpu->iem.s.uRexB);
|
---|
1857 | }
|
---|
1858 |
|
---|
1859 |
|
---|
1860 | /** Opcode 0x0f 0x24. */
|
---|
1861 | FNIEMOP_DEF(iemOp_mov_Rd_Td)
|
---|
1862 | {
|
---|
1863 | IEMOP_MNEMONIC("mov Rd,Td");
|
---|
1864 | /** @todo works on 386 and 486. */
|
---|
1865 | /* The RM byte is not considered, see testcase. */
|
---|
1866 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1867 | }
|
---|
1868 |
|
---|
1869 |
|
---|
1870 | /** Opcode 0x0f 0x26. */
|
---|
1871 | FNIEMOP_DEF(iemOp_mov_Td_Rd)
|
---|
1872 | {
|
---|
1873 | IEMOP_MNEMONIC("mov Td,Rd");
|
---|
1874 | /** @todo works on 386 and 486. */
|
---|
1875 | /* The RM byte is not considered, see testcase. */
|
---|
1876 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
1877 | }
|
---|
1878 |
|
---|
1879 |
|
---|
1880 | /** Opcode 0x0f 0x28. */
|
---|
1881 | FNIEMOP_DEF(iemOp_movaps_Vps_Wps__movapd_Vpd_Wpd)
|
---|
1882 | {
|
---|
1883 | IEMOP_MNEMONIC(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP) ? "movaps r,mr" : "movapd r,mr");
|
---|
1884 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1885 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1886 | {
|
---|
1887 | /*
|
---|
1888 | * Register, register.
|
---|
1889 | */
|
---|
1890 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
|
---|
1891 | IEM_MC_BEGIN(0, 0);
|
---|
1892 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP))
|
---|
1893 | IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
|
---|
1894 | else
|
---|
1895 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
1896 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
1897 | IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
|
---|
1898 | (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
1899 | IEM_MC_ADVANCE_RIP();
|
---|
1900 | IEM_MC_END();
|
---|
1901 | }
|
---|
1902 | else
|
---|
1903 | {
|
---|
1904 | /*
|
---|
1905 | * Register, memory.
|
---|
1906 | */
|
---|
1907 | IEM_MC_BEGIN(0, 2);
|
---|
1908 | IEM_MC_LOCAL(uint128_t, uSrc); /** @todo optimize this one day... */
|
---|
1909 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1910 |
|
---|
1911 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1912 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); /** @todo check if this is delayed this long for REPZ/NZ */
|
---|
1913 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP))
|
---|
1914 | IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
|
---|
1915 | else
|
---|
1916 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
1917 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
1918 |
|
---|
1919 | IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
1920 | IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
|
---|
1921 |
|
---|
1922 | IEM_MC_ADVANCE_RIP();
|
---|
1923 | IEM_MC_END();
|
---|
1924 | }
|
---|
1925 | return VINF_SUCCESS;
|
---|
1926 | }
|
---|
1927 |
|
---|
1928 |
|
---|
1929 | /** Opcode 0x0f 0x29. */
|
---|
1930 | FNIEMOP_DEF(iemOp_movaps_Wps_Vps__movapd_Wpd_Vpd)
|
---|
1931 | {
|
---|
1932 | IEMOP_MNEMONIC(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP) ? "movaps mr,r" : "movapd mr,r");
|
---|
1933 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1934 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
1935 | {
|
---|
1936 | /*
|
---|
1937 | * Register, register.
|
---|
1938 | */
|
---|
1939 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
|
---|
1940 | IEM_MC_BEGIN(0, 0);
|
---|
1941 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP))
|
---|
1942 | IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
|
---|
1943 | else
|
---|
1944 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
1945 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
1946 | IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
|
---|
1947 | ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1948 | IEM_MC_ADVANCE_RIP();
|
---|
1949 | IEM_MC_END();
|
---|
1950 | }
|
---|
1951 | else
|
---|
1952 | {
|
---|
1953 | /*
|
---|
1954 | * Memory, register.
|
---|
1955 | */
|
---|
1956 | IEM_MC_BEGIN(0, 2);
|
---|
1957 | IEM_MC_LOCAL(uint128_t, uSrc); /** @todo optimize this one day... */
|
---|
1958 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1959 |
|
---|
1960 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1961 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); /** @todo check if this is delayed this long for REPZ/NZ */
|
---|
1962 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP))
|
---|
1963 | IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
|
---|
1964 | else
|
---|
1965 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
1966 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
|
---|
1967 |
|
---|
1968 | IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
1969 | IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
|
---|
1970 |
|
---|
1971 | IEM_MC_ADVANCE_RIP();
|
---|
1972 | IEM_MC_END();
|
---|
1973 | }
|
---|
1974 | return VINF_SUCCESS;
|
---|
1975 | }
|
---|
1976 |
|
---|
1977 |
|
---|
1978 | /** Opcode 0x0f 0x2a. */
|
---|
1979 | FNIEMOP_STUB(iemOp_cvtpi2ps_Vps_Qpi__cvtpi2pd_Vpd_Qpi__cvtsi2ss_Vss_Ey__cvtsi2sd_Vsd_Ey); //NEXT
|
---|
1980 |
|
---|
1981 |
|
---|
1982 | /** Opcode 0x0f 0x2b. */
|
---|
1983 | FNIEMOP_DEF(iemOp_movntps_Mps_Vps__movntpd_Mpd_Vpd)
|
---|
1984 | {
|
---|
1985 | IEMOP_MNEMONIC(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP) ? "movntps mr,r" : "movntpd mr,r");
|
---|
1986 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
1987 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
1988 | {
|
---|
1989 | /*
|
---|
1990 | * memory, register.
|
---|
1991 | */
|
---|
1992 | IEM_MC_BEGIN(0, 2);
|
---|
1993 | IEM_MC_LOCAL(uint128_t, uSrc); /** @todo optimize this one day... */
|
---|
1994 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
1995 |
|
---|
1996 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
1997 | IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES(); /** @todo check if this is delayed this long for REPZ/NZ */
|
---|
1998 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP))
|
---|
1999 | IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
|
---|
2000 | else
|
---|
2001 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2002 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
2003 |
|
---|
2004 | IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
2005 | IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
|
---|
2006 |
|
---|
2007 | IEM_MC_ADVANCE_RIP();
|
---|
2008 | IEM_MC_END();
|
---|
2009 | }
|
---|
2010 | /* The register, register encoding is invalid. */
|
---|
2011 | else
|
---|
2012 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2013 | return VINF_SUCCESS;
|
---|
2014 | }
|
---|
2015 |
|
---|
2016 |
|
---|
2017 | /** Opcode 0x0f 0x2c. */
|
---|
2018 | FNIEMOP_STUB(iemOp_cvttps2pi_Ppi_Wps__cvttpd2pi_Ppi_Wpd__cvttss2si_Gy_Wss__cvttsd2si_Yu_Wsd); //NEXT
|
---|
2019 | /** Opcode 0x0f 0x2d. */
|
---|
2020 | FNIEMOP_STUB(iemOp_cvtps2pi_Ppi_Wps__cvtpd2pi_QpiWpd__cvtss2si_Gy_Wss__cvtsd2si_Gy_Wsd);
|
---|
2021 | /** Opcode 0x0f 0x2e. */
|
---|
2022 | FNIEMOP_STUB(iemOp_ucomiss_Vss_Wss__ucomisd_Vsd_Wsd); //NEXT
|
---|
2023 | /** Opcode 0x0f 0x2f. */
|
---|
2024 | FNIEMOP_STUB(iemOp_comiss_Vss_Wss__comisd_Vsd_Wsd);
|
---|
2025 |
|
---|
2026 |
|
---|
2027 | /** Opcode 0x0f 0x30. */
|
---|
2028 | FNIEMOP_DEF(iemOp_wrmsr)
|
---|
2029 | {
|
---|
2030 | IEMOP_MNEMONIC("wrmsr");
|
---|
2031 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2032 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_wrmsr);
|
---|
2033 | }
|
---|
2034 |
|
---|
2035 |
|
---|
2036 | /** Opcode 0x0f 0x31. */
|
---|
2037 | FNIEMOP_DEF(iemOp_rdtsc)
|
---|
2038 | {
|
---|
2039 | IEMOP_MNEMONIC("rdtsc");
|
---|
2040 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2041 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdtsc);
|
---|
2042 | }
|
---|
2043 |
|
---|
2044 |
|
---|
2045 | /** Opcode 0x0f 0x33. */
|
---|
2046 | FNIEMOP_DEF(iemOp_rdmsr)
|
---|
2047 | {
|
---|
2048 | IEMOP_MNEMONIC("rdmsr");
|
---|
2049 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2050 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdmsr);
|
---|
2051 | }
|
---|
2052 |
|
---|
2053 |
|
---|
2054 | /** Opcode 0x0f 0x34. */
|
---|
2055 | FNIEMOP_STUB(iemOp_rdpmc);
|
---|
2056 | /** Opcode 0x0f 0x34. */
|
---|
2057 | FNIEMOP_STUB(iemOp_sysenter);
|
---|
2058 | /** Opcode 0x0f 0x35. */
|
---|
2059 | FNIEMOP_STUB(iemOp_sysexit);
|
---|
2060 | /** Opcode 0x0f 0x37. */
|
---|
2061 | FNIEMOP_STUB(iemOp_getsec);
|
---|
2062 | /** Opcode 0x0f 0x38. */
|
---|
2063 | FNIEMOP_UD_STUB(iemOp_3byte_Esc_A4); /* Here there be dragons... */
|
---|
2064 | /** Opcode 0x0f 0x3a. */
|
---|
2065 | FNIEMOP_UD_STUB(iemOp_3byte_Esc_A5); /* Here there be dragons... */
|
---|
2066 |
|
---|
2067 |
|
---|
2068 | /**
|
---|
2069 | * Implements a conditional move.
|
---|
2070 | *
|
---|
2071 | * Wish there was an obvious way to do this where we could share and reduce
|
---|
2072 | * code bloat.
|
---|
2073 | *
|
---|
2074 | * @param a_Cnd The conditional "microcode" operation.
|
---|
2075 | */
|
---|
2076 | #define CMOV_X(a_Cnd) \
|
---|
2077 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
|
---|
2078 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
|
---|
2079 | { \
|
---|
2080 | switch (pVCpu->iem.s.enmEffOpSize) \
|
---|
2081 | { \
|
---|
2082 | case IEMMODE_16BIT: \
|
---|
2083 | IEM_MC_BEGIN(0, 1); \
|
---|
2084 | IEM_MC_LOCAL(uint16_t, u16Tmp); \
|
---|
2085 | a_Cnd { \
|
---|
2086 | IEM_MC_FETCH_GREG_U16(u16Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); \
|
---|
2087 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Tmp); \
|
---|
2088 | } IEM_MC_ENDIF(); \
|
---|
2089 | IEM_MC_ADVANCE_RIP(); \
|
---|
2090 | IEM_MC_END(); \
|
---|
2091 | return VINF_SUCCESS; \
|
---|
2092 | \
|
---|
2093 | case IEMMODE_32BIT: \
|
---|
2094 | IEM_MC_BEGIN(0, 1); \
|
---|
2095 | IEM_MC_LOCAL(uint32_t, u32Tmp); \
|
---|
2096 | a_Cnd { \
|
---|
2097 | IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); \
|
---|
2098 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp); \
|
---|
2099 | } IEM_MC_ELSE() { \
|
---|
2100 | IEM_MC_CLEAR_HIGH_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg); \
|
---|
2101 | } IEM_MC_ENDIF(); \
|
---|
2102 | IEM_MC_ADVANCE_RIP(); \
|
---|
2103 | IEM_MC_END(); \
|
---|
2104 | return VINF_SUCCESS; \
|
---|
2105 | \
|
---|
2106 | case IEMMODE_64BIT: \
|
---|
2107 | IEM_MC_BEGIN(0, 1); \
|
---|
2108 | IEM_MC_LOCAL(uint64_t, u64Tmp); \
|
---|
2109 | a_Cnd { \
|
---|
2110 | IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); \
|
---|
2111 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp); \
|
---|
2112 | } IEM_MC_ENDIF(); \
|
---|
2113 | IEM_MC_ADVANCE_RIP(); \
|
---|
2114 | IEM_MC_END(); \
|
---|
2115 | return VINF_SUCCESS; \
|
---|
2116 | \
|
---|
2117 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
|
---|
2118 | } \
|
---|
2119 | } \
|
---|
2120 | else \
|
---|
2121 | { \
|
---|
2122 | switch (pVCpu->iem.s.enmEffOpSize) \
|
---|
2123 | { \
|
---|
2124 | case IEMMODE_16BIT: \
|
---|
2125 | IEM_MC_BEGIN(0, 2); \
|
---|
2126 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
|
---|
2127 | IEM_MC_LOCAL(uint16_t, u16Tmp); \
|
---|
2128 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
|
---|
2129 | IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
|
---|
2130 | a_Cnd { \
|
---|
2131 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Tmp); \
|
---|
2132 | } IEM_MC_ENDIF(); \
|
---|
2133 | IEM_MC_ADVANCE_RIP(); \
|
---|
2134 | IEM_MC_END(); \
|
---|
2135 | return VINF_SUCCESS; \
|
---|
2136 | \
|
---|
2137 | case IEMMODE_32BIT: \
|
---|
2138 | IEM_MC_BEGIN(0, 2); \
|
---|
2139 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
|
---|
2140 | IEM_MC_LOCAL(uint32_t, u32Tmp); \
|
---|
2141 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
|
---|
2142 | IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
|
---|
2143 | a_Cnd { \
|
---|
2144 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp); \
|
---|
2145 | } IEM_MC_ELSE() { \
|
---|
2146 | IEM_MC_CLEAR_HIGH_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg); \
|
---|
2147 | } IEM_MC_ENDIF(); \
|
---|
2148 | IEM_MC_ADVANCE_RIP(); \
|
---|
2149 | IEM_MC_END(); \
|
---|
2150 | return VINF_SUCCESS; \
|
---|
2151 | \
|
---|
2152 | case IEMMODE_64BIT: \
|
---|
2153 | IEM_MC_BEGIN(0, 2); \
|
---|
2154 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
|
---|
2155 | IEM_MC_LOCAL(uint64_t, u64Tmp); \
|
---|
2156 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
|
---|
2157 | IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
|
---|
2158 | a_Cnd { \
|
---|
2159 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp); \
|
---|
2160 | } IEM_MC_ENDIF(); \
|
---|
2161 | IEM_MC_ADVANCE_RIP(); \
|
---|
2162 | IEM_MC_END(); \
|
---|
2163 | return VINF_SUCCESS; \
|
---|
2164 | \
|
---|
2165 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
|
---|
2166 | } \
|
---|
2167 | } do {} while (0)
|
---|
2168 |
|
---|
2169 |
|
---|
2170 |
|
---|
2171 | /** Opcode 0x0f 0x40. */
|
---|
2172 | FNIEMOP_DEF(iemOp_cmovo_Gv_Ev)
|
---|
2173 | {
|
---|
2174 | IEMOP_MNEMONIC("cmovo Gv,Ev");
|
---|
2175 | CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF));
|
---|
2176 | }
|
---|
2177 |
|
---|
2178 |
|
---|
2179 | /** Opcode 0x0f 0x41. */
|
---|
2180 | FNIEMOP_DEF(iemOp_cmovno_Gv_Ev)
|
---|
2181 | {
|
---|
2182 | IEMOP_MNEMONIC("cmovno Gv,Ev");
|
---|
2183 | CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_OF));
|
---|
2184 | }
|
---|
2185 |
|
---|
2186 |
|
---|
2187 | /** Opcode 0x0f 0x42. */
|
---|
2188 | FNIEMOP_DEF(iemOp_cmovc_Gv_Ev)
|
---|
2189 | {
|
---|
2190 | IEMOP_MNEMONIC("cmovc Gv,Ev");
|
---|
2191 | CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF));
|
---|
2192 | }
|
---|
2193 |
|
---|
2194 |
|
---|
2195 | /** Opcode 0x0f 0x43. */
|
---|
2196 | FNIEMOP_DEF(iemOp_cmovnc_Gv_Ev)
|
---|
2197 | {
|
---|
2198 | IEMOP_MNEMONIC("cmovnc Gv,Ev");
|
---|
2199 | CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_CF));
|
---|
2200 | }
|
---|
2201 |
|
---|
2202 |
|
---|
2203 | /** Opcode 0x0f 0x44. */
|
---|
2204 | FNIEMOP_DEF(iemOp_cmove_Gv_Ev)
|
---|
2205 | {
|
---|
2206 | IEMOP_MNEMONIC("cmove Gv,Ev");
|
---|
2207 | CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF));
|
---|
2208 | }
|
---|
2209 |
|
---|
2210 |
|
---|
2211 | /** Opcode 0x0f 0x45. */
|
---|
2212 | FNIEMOP_DEF(iemOp_cmovne_Gv_Ev)
|
---|
2213 | {
|
---|
2214 | IEMOP_MNEMONIC("cmovne Gv,Ev");
|
---|
2215 | CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF));
|
---|
2216 | }
|
---|
2217 |
|
---|
2218 |
|
---|
2219 | /** Opcode 0x0f 0x46. */
|
---|
2220 | FNIEMOP_DEF(iemOp_cmovbe_Gv_Ev)
|
---|
2221 | {
|
---|
2222 | IEMOP_MNEMONIC("cmovbe Gv,Ev");
|
---|
2223 | CMOV_X(IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF));
|
---|
2224 | }
|
---|
2225 |
|
---|
2226 |
|
---|
2227 | /** Opcode 0x0f 0x47. */
|
---|
2228 | FNIEMOP_DEF(iemOp_cmovnbe_Gv_Ev)
|
---|
2229 | {
|
---|
2230 | IEMOP_MNEMONIC("cmovnbe Gv,Ev");
|
---|
2231 | CMOV_X(IEM_MC_IF_EFL_NO_BITS_SET(X86_EFL_CF | X86_EFL_ZF));
|
---|
2232 | }
|
---|
2233 |
|
---|
2234 |
|
---|
2235 | /** Opcode 0x0f 0x48. */
|
---|
2236 | FNIEMOP_DEF(iemOp_cmovs_Gv_Ev)
|
---|
2237 | {
|
---|
2238 | IEMOP_MNEMONIC("cmovs Gv,Ev");
|
---|
2239 | CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF));
|
---|
2240 | }
|
---|
2241 |
|
---|
2242 |
|
---|
2243 | /** Opcode 0x0f 0x49. */
|
---|
2244 | FNIEMOP_DEF(iemOp_cmovns_Gv_Ev)
|
---|
2245 | {
|
---|
2246 | IEMOP_MNEMONIC("cmovns Gv,Ev");
|
---|
2247 | CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_SF));
|
---|
2248 | }
|
---|
2249 |
|
---|
2250 |
|
---|
2251 | /** Opcode 0x0f 0x4a. */
|
---|
2252 | FNIEMOP_DEF(iemOp_cmovp_Gv_Ev)
|
---|
2253 | {
|
---|
2254 | IEMOP_MNEMONIC("cmovp Gv,Ev");
|
---|
2255 | CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF));
|
---|
2256 | }
|
---|
2257 |
|
---|
2258 |
|
---|
2259 | /** Opcode 0x0f 0x4b. */
|
---|
2260 | FNIEMOP_DEF(iemOp_cmovnp_Gv_Ev)
|
---|
2261 | {
|
---|
2262 | IEMOP_MNEMONIC("cmovnp Gv,Ev");
|
---|
2263 | CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_PF));
|
---|
2264 | }
|
---|
2265 |
|
---|
2266 |
|
---|
2267 | /** Opcode 0x0f 0x4c. */
|
---|
2268 | FNIEMOP_DEF(iemOp_cmovl_Gv_Ev)
|
---|
2269 | {
|
---|
2270 | IEMOP_MNEMONIC("cmovl Gv,Ev");
|
---|
2271 | CMOV_X(IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF));
|
---|
2272 | }
|
---|
2273 |
|
---|
2274 |
|
---|
2275 | /** Opcode 0x0f 0x4d. */
|
---|
2276 | FNIEMOP_DEF(iemOp_cmovnl_Gv_Ev)
|
---|
2277 | {
|
---|
2278 | IEMOP_MNEMONIC("cmovnl Gv,Ev");
|
---|
2279 | CMOV_X(IEM_MC_IF_EFL_BITS_EQ(X86_EFL_SF, X86_EFL_OF));
|
---|
2280 | }
|
---|
2281 |
|
---|
2282 |
|
---|
2283 | /** Opcode 0x0f 0x4e. */
|
---|
2284 | FNIEMOP_DEF(iemOp_cmovle_Gv_Ev)
|
---|
2285 | {
|
---|
2286 | IEMOP_MNEMONIC("cmovle Gv,Ev");
|
---|
2287 | CMOV_X(IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF));
|
---|
2288 | }
|
---|
2289 |
|
---|
2290 |
|
---|
2291 | /** Opcode 0x0f 0x4f. */
|
---|
2292 | FNIEMOP_DEF(iemOp_cmovnle_Gv_Ev)
|
---|
2293 | {
|
---|
2294 | IEMOP_MNEMONIC("cmovnle Gv,Ev");
|
---|
2295 | CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF));
|
---|
2296 | }
|
---|
2297 |
|
---|
2298 | #undef CMOV_X
|
---|
2299 |
|
---|
2300 | /** Opcode 0x0f 0x50. */
|
---|
2301 | FNIEMOP_STUB(iemOp_movmskps_Gy_Ups__movmskpd_Gy_Upd);
|
---|
2302 | /** Opcode 0x0f 0x51. */
|
---|
2303 | FNIEMOP_STUB(iemOp_sqrtps_Wps_Vps__sqrtpd_Wpd_Vpd__sqrtss_Vss_Wss__sqrtsd_Vsd_Wsd);
|
---|
2304 | /** Opcode 0x0f 0x52. */
|
---|
2305 | FNIEMOP_STUB(iemOp_rsqrtps_Wps_Vps__rsqrtss_Vss_Wss);
|
---|
2306 | /** Opcode 0x0f 0x53. */
|
---|
2307 | FNIEMOP_STUB(iemOp_rcpps_Wps_Vps__rcpss_Vs_Wss);
|
---|
2308 | /** Opcode 0x0f 0x54. */
|
---|
2309 | FNIEMOP_STUB(iemOp_andps_Vps_Wps__andpd_Wpd_Vpd);
|
---|
2310 | /** Opcode 0x0f 0x55. */
|
---|
2311 | FNIEMOP_STUB(iemOp_andnps_Vps_Wps__andnpd_Wpd_Vpd);
|
---|
2312 | /** Opcode 0x0f 0x56. */
|
---|
2313 | FNIEMOP_STUB(iemOp_orps_Wpd_Vpd__orpd_Wpd_Vpd);
|
---|
2314 | /** Opcode 0x0f 0x57. */
|
---|
2315 | FNIEMOP_STUB(iemOp_xorps_Vps_Wps__xorpd_Wpd_Vpd);
|
---|
2316 | /** Opcode 0x0f 0x58. */
|
---|
2317 | FNIEMOP_STUB(iemOp_addps_Vps_Wps__addpd_Vpd_Wpd__addss_Vss_Wss__addsd_Vsd_Wsd); //NEXT
|
---|
2318 | /** Opcode 0x0f 0x59. */
|
---|
2319 | FNIEMOP_STUB(iemOp_mulps_Vps_Wps__mulpd_Vpd_Wpd__mulss_Vss__Wss__mulsd_Vsd_Wsd);//NEXT
|
---|
2320 | /** Opcode 0x0f 0x5a. */
|
---|
2321 | FNIEMOP_STUB(iemOp_cvtps2pd_Vpd_Wps__cvtpd2ps_Vps_Wpd__cvtss2sd_Vsd_Wss__cvtsd2ss_Vss_Wsd);
|
---|
2322 | /** Opcode 0x0f 0x5b. */
|
---|
2323 | FNIEMOP_STUB(iemOp_cvtdq2ps_Vps_Wdq__cvtps2dq_Vdq_Wps__cvtps2dq_Vdq_Wps);
|
---|
2324 | /** Opcode 0x0f 0x5c. */
|
---|
2325 | FNIEMOP_STUB(iemOp_subps_Vps_Wps__subpd_Vps_Wdp__subss_Vss_Wss__subsd_Vsd_Wsd);
|
---|
2326 | /** Opcode 0x0f 0x5d. */
|
---|
2327 | FNIEMOP_STUB(iemOp_minps_Vps_Wps__minpd_Vpd_Wpd__minss_Vss_Wss__minsd_Vsd_Wsd);
|
---|
2328 | /** Opcode 0x0f 0x5e. */
|
---|
2329 | FNIEMOP_STUB(iemOp_divps_Vps_Wps__divpd_Vpd_Wpd__divss_Vss_Wss__divsd_Vsd_Wsd);
|
---|
2330 | /** Opcode 0x0f 0x5f. */
|
---|
2331 | FNIEMOP_STUB(iemOp_maxps_Vps_Wps__maxpd_Vpd_Wpd__maxss_Vss_Wss__maxsd_Vsd_Wsd);
|
---|
2332 |
|
---|
2333 |
|
---|
2334 | /**
|
---|
2335 | * Common worker for SSE2 and MMX instructions on the forms:
|
---|
2336 | * pxxxx xmm1, xmm2/mem128
|
---|
2337 | * pxxxx mm1, mm2/mem32
|
---|
2338 | *
|
---|
2339 | * The 2nd operand is the first half of a register, which in the memory case
|
---|
2340 | * means a 32-bit memory access for MMX and 128-bit aligned 64-bit or 128-bit
|
---|
2341 | * memory accessed for MMX.
|
---|
2342 | *
|
---|
2343 | * Exceptions type 4.
|
---|
2344 | */
|
---|
2345 | FNIEMOP_DEF_1(iemOpCommonMmxSse_LowLow_To_Full, PCIEMOPMEDIAF1L1, pImpl)
|
---|
2346 | {
|
---|
2347 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
2348 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
2349 | {
|
---|
2350 | case IEM_OP_PRF_SIZE_OP: /* SSE */
|
---|
2351 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2352 | {
|
---|
2353 | /*
|
---|
2354 | * Register, register.
|
---|
2355 | */
|
---|
2356 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2357 | IEM_MC_BEGIN(2, 0);
|
---|
2358 | IEM_MC_ARG(uint128_t *, pDst, 0);
|
---|
2359 | IEM_MC_ARG(uint64_t const *, pSrc, 1);
|
---|
2360 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2361 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
2362 | IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
2363 | IEM_MC_REF_XREG_U64_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
2364 | IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
|
---|
2365 | IEM_MC_ADVANCE_RIP();
|
---|
2366 | IEM_MC_END();
|
---|
2367 | }
|
---|
2368 | else
|
---|
2369 | {
|
---|
2370 | /*
|
---|
2371 | * Register, memory.
|
---|
2372 | */
|
---|
2373 | IEM_MC_BEGIN(2, 2);
|
---|
2374 | IEM_MC_ARG(uint128_t *, pDst, 0);
|
---|
2375 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
2376 | IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
|
---|
2377 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2378 |
|
---|
2379 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
2380 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2381 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2382 | IEM_MC_FETCH_MEM_U64_ALIGN_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2383 |
|
---|
2384 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
2385 | IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
2386 | IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
|
---|
2387 |
|
---|
2388 | IEM_MC_ADVANCE_RIP();
|
---|
2389 | IEM_MC_END();
|
---|
2390 | }
|
---|
2391 | return VINF_SUCCESS;
|
---|
2392 |
|
---|
2393 | case 0: /* MMX */
|
---|
2394 | if (!pImpl->pfnU64)
|
---|
2395 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2396 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2397 | {
|
---|
2398 | /*
|
---|
2399 | * Register, register.
|
---|
2400 | */
|
---|
2401 | /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
|
---|
2402 | /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
|
---|
2403 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2404 | IEM_MC_BEGIN(2, 0);
|
---|
2405 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
2406 | IEM_MC_ARG(uint32_t const *, pSrc, 1);
|
---|
2407 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
2408 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
2409 | IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
2410 | IEM_MC_REF_MREG_U32_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
|
---|
2411 | IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
|
---|
2412 | IEM_MC_ADVANCE_RIP();
|
---|
2413 | IEM_MC_END();
|
---|
2414 | }
|
---|
2415 | else
|
---|
2416 | {
|
---|
2417 | /*
|
---|
2418 | * Register, memory.
|
---|
2419 | */
|
---|
2420 | IEM_MC_BEGIN(2, 2);
|
---|
2421 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
2422 | IEM_MC_LOCAL(uint32_t, uSrc);
|
---|
2423 | IEM_MC_ARG_LOCAL_REF(uint32_t const *, pSrc, uSrc, 1);
|
---|
2424 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2425 |
|
---|
2426 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
2427 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2428 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
2429 | IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2430 |
|
---|
2431 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
2432 | IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
2433 | IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
|
---|
2434 |
|
---|
2435 | IEM_MC_ADVANCE_RIP();
|
---|
2436 | IEM_MC_END();
|
---|
2437 | }
|
---|
2438 | return VINF_SUCCESS;
|
---|
2439 |
|
---|
2440 | default:
|
---|
2441 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2442 | }
|
---|
2443 | }
|
---|
2444 |
|
---|
2445 |
|
---|
2446 | /** Opcode 0x0f 0x60. */
|
---|
2447 | FNIEMOP_DEF(iemOp_punpcklbw_Pq_Qd__punpcklbw_Vdq_Wdq)
|
---|
2448 | {
|
---|
2449 | IEMOP_MNEMONIC("punpcklbw");
|
---|
2450 | return FNIEMOP_CALL_1(iemOpCommonMmxSse_LowLow_To_Full, &g_iemAImpl_punpcklbw);
|
---|
2451 | }
|
---|
2452 |
|
---|
2453 |
|
---|
2454 | /** Opcode 0x0f 0x61. */
|
---|
2455 | FNIEMOP_DEF(iemOp_punpcklwd_Pq_Qd__punpcklwd_Vdq_Wdq)
|
---|
2456 | {
|
---|
2457 | IEMOP_MNEMONIC("punpcklwd"); /** @todo AMD mark the MMX version as 3DNow!. Intel says MMX CPUID req. */
|
---|
2458 | return FNIEMOP_CALL_1(iemOpCommonMmxSse_LowLow_To_Full, &g_iemAImpl_punpcklwd);
|
---|
2459 | }
|
---|
2460 |
|
---|
2461 |
|
---|
2462 | /** Opcode 0x0f 0x62. */
|
---|
2463 | FNIEMOP_DEF(iemOp_punpckldq_Pq_Qd__punpckldq_Vdq_Wdq)
|
---|
2464 | {
|
---|
2465 | IEMOP_MNEMONIC("punpckldq");
|
---|
2466 | return FNIEMOP_CALL_1(iemOpCommonMmxSse_LowLow_To_Full, &g_iemAImpl_punpckldq);
|
---|
2467 | }
|
---|
2468 |
|
---|
2469 |
|
---|
2470 | /** Opcode 0x0f 0x63. */
|
---|
2471 | FNIEMOP_STUB(iemOp_packsswb_Pq_Qq__packsswb_Vdq_Wdq);
|
---|
2472 | /** Opcode 0x0f 0x64. */
|
---|
2473 | FNIEMOP_STUB(iemOp_pcmpgtb_Pq_Qq__pcmpgtb_Vdq_Wdq);
|
---|
2474 | /** Opcode 0x0f 0x65. */
|
---|
2475 | FNIEMOP_STUB(iemOp_pcmpgtw_Pq_Qq__pcmpgtw_Vdq_Wdq);
|
---|
2476 | /** Opcode 0x0f 0x66. */
|
---|
2477 | FNIEMOP_STUB(iemOp_pcmpgtd_Pq_Qq__pcmpgtd_Vdq_Wdq);
|
---|
2478 | /** Opcode 0x0f 0x67. */
|
---|
2479 | FNIEMOP_STUB(iemOp_packuswb_Pq_Qq__packuswb_Vdq_Wdq);
|
---|
2480 |
|
---|
2481 |
|
---|
2482 | /**
|
---|
2483 | * Common worker for SSE2 and MMX instructions on the forms:
|
---|
2484 | * pxxxx xmm1, xmm2/mem128
|
---|
2485 | * pxxxx mm1, mm2/mem64
|
---|
2486 | *
|
---|
2487 | * The 2nd operand is the second half of a register, which in the memory case
|
---|
2488 | * means a 64-bit memory access for MMX, and for MMX a 128-bit aligned access
|
---|
2489 | * where it may read the full 128 bits or only the upper 64 bits.
|
---|
2490 | *
|
---|
2491 | * Exceptions type 4.
|
---|
2492 | */
|
---|
2493 | FNIEMOP_DEF_1(iemOpCommonMmxSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
|
---|
2494 | {
|
---|
2495 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
2496 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
2497 | {
|
---|
2498 | case IEM_OP_PRF_SIZE_OP: /* SSE */
|
---|
2499 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2500 | {
|
---|
2501 | /*
|
---|
2502 | * Register, register.
|
---|
2503 | */
|
---|
2504 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2505 | IEM_MC_BEGIN(2, 0);
|
---|
2506 | IEM_MC_ARG(uint128_t *, pDst, 0);
|
---|
2507 | IEM_MC_ARG(uint128_t const *, pSrc, 1);
|
---|
2508 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2509 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
2510 | IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
2511 | IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
2512 | IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
|
---|
2513 | IEM_MC_ADVANCE_RIP();
|
---|
2514 | IEM_MC_END();
|
---|
2515 | }
|
---|
2516 | else
|
---|
2517 | {
|
---|
2518 | /*
|
---|
2519 | * Register, memory.
|
---|
2520 | */
|
---|
2521 | IEM_MC_BEGIN(2, 2);
|
---|
2522 | IEM_MC_ARG(uint128_t *, pDst, 0);
|
---|
2523 | IEM_MC_LOCAL(uint128_t, uSrc);
|
---|
2524 | IEM_MC_ARG_LOCAL_REF(uint128_t const *, pSrc, uSrc, 1);
|
---|
2525 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2526 |
|
---|
2527 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
2528 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2529 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2530 | IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
|
---|
2531 |
|
---|
2532 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
2533 | IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
2534 | IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
|
---|
2535 |
|
---|
2536 | IEM_MC_ADVANCE_RIP();
|
---|
2537 | IEM_MC_END();
|
---|
2538 | }
|
---|
2539 | return VINF_SUCCESS;
|
---|
2540 |
|
---|
2541 | case 0: /* MMX */
|
---|
2542 | if (!pImpl->pfnU64)
|
---|
2543 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2544 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2545 | {
|
---|
2546 | /*
|
---|
2547 | * Register, register.
|
---|
2548 | */
|
---|
2549 | /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
|
---|
2550 | /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
|
---|
2551 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2552 | IEM_MC_BEGIN(2, 0);
|
---|
2553 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
2554 | IEM_MC_ARG(uint64_t const *, pSrc, 1);
|
---|
2555 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
2556 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
2557 | IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
2558 | IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
|
---|
2559 | IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
|
---|
2560 | IEM_MC_ADVANCE_RIP();
|
---|
2561 | IEM_MC_END();
|
---|
2562 | }
|
---|
2563 | else
|
---|
2564 | {
|
---|
2565 | /*
|
---|
2566 | * Register, memory.
|
---|
2567 | */
|
---|
2568 | IEM_MC_BEGIN(2, 2);
|
---|
2569 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
2570 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
2571 | IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
|
---|
2572 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2573 |
|
---|
2574 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
2575 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2576 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
2577 | IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2578 |
|
---|
2579 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
2580 | IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
2581 | IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
|
---|
2582 |
|
---|
2583 | IEM_MC_ADVANCE_RIP();
|
---|
2584 | IEM_MC_END();
|
---|
2585 | }
|
---|
2586 | return VINF_SUCCESS;
|
---|
2587 |
|
---|
2588 | default:
|
---|
2589 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2590 | }
|
---|
2591 | }
|
---|
2592 |
|
---|
2593 |
|
---|
2594 | /** Opcode 0x0f 0x68. */
|
---|
2595 | FNIEMOP_DEF(iemOp_punpckhbw_Pq_Qq__punpckhbw_Vdq_Wdq)
|
---|
2596 | {
|
---|
2597 | IEMOP_MNEMONIC("punpckhbw");
|
---|
2598 | return FNIEMOP_CALL_1(iemOpCommonMmxSse_HighHigh_To_Full, &g_iemAImpl_punpckhbw);
|
---|
2599 | }
|
---|
2600 |
|
---|
2601 |
|
---|
2602 | /** Opcode 0x0f 0x69. */
|
---|
2603 | FNIEMOP_DEF(iemOp_punpckhwd_Pq_Qd__punpckhwd_Vdq_Wdq)
|
---|
2604 | {
|
---|
2605 | IEMOP_MNEMONIC("punpckhwd");
|
---|
2606 | return FNIEMOP_CALL_1(iemOpCommonMmxSse_HighHigh_To_Full, &g_iemAImpl_punpckhwd);
|
---|
2607 | }
|
---|
2608 |
|
---|
2609 |
|
---|
2610 | /** Opcode 0x0f 0x6a. */
|
---|
2611 | FNIEMOP_DEF(iemOp_punpckhdq_Pq_Qd__punpckhdq_Vdq_Wdq)
|
---|
2612 | {
|
---|
2613 | IEMOP_MNEMONIC("punpckhdq");
|
---|
2614 | return FNIEMOP_CALL_1(iemOpCommonMmxSse_HighHigh_To_Full, &g_iemAImpl_punpckhdq);
|
---|
2615 | }
|
---|
2616 |
|
---|
2617 | /** Opcode 0x0f 0x6b. */
|
---|
2618 | FNIEMOP_STUB(iemOp_packssdw_Pq_Qd__packssdq_Vdq_Wdq);
|
---|
2619 |
|
---|
2620 |
|
---|
2621 | /** Opcode 0x0f 0x6c. */
|
---|
2622 | FNIEMOP_DEF(iemOp_punpcklqdq_Vdq_Wdq)
|
---|
2623 | {
|
---|
2624 | IEMOP_MNEMONIC("punpcklqdq");
|
---|
2625 | return FNIEMOP_CALL_1(iemOpCommonMmxSse_LowLow_To_Full, &g_iemAImpl_punpcklqdq);
|
---|
2626 | }
|
---|
2627 |
|
---|
2628 |
|
---|
2629 | /** Opcode 0x0f 0x6d. */
|
---|
2630 | FNIEMOP_DEF(iemOp_punpckhqdq_Vdq_Wdq)
|
---|
2631 | {
|
---|
2632 | IEMOP_MNEMONIC("punpckhqdq");
|
---|
2633 | return FNIEMOP_CALL_1(iemOpCommonMmxSse_HighHigh_To_Full, &g_iemAImpl_punpckhqdq);
|
---|
2634 | }
|
---|
2635 |
|
---|
2636 |
|
---|
2637 | /** Opcode 0x0f 0x6e. */
|
---|
2638 | FNIEMOP_DEF(iemOp_movd_q_Pd_Ey__movd_q_Vy_Ey)
|
---|
2639 | {
|
---|
2640 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
2641 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
2642 | {
|
---|
2643 | case IEM_OP_PRF_SIZE_OP: /* SSE */
|
---|
2644 | IEMOP_MNEMONIC("movd/q Wd/q,Ed/q");
|
---|
2645 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2646 | {
|
---|
2647 | /* XMM, greg*/
|
---|
2648 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2649 | IEM_MC_BEGIN(0, 1);
|
---|
2650 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2651 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
2652 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
|
---|
2653 | {
|
---|
2654 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
2655 | IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
2656 | IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
|
---|
2657 | }
|
---|
2658 | else
|
---|
2659 | {
|
---|
2660 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
2661 | IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
2662 | IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
|
---|
2663 | }
|
---|
2664 | IEM_MC_ADVANCE_RIP();
|
---|
2665 | IEM_MC_END();
|
---|
2666 | }
|
---|
2667 | else
|
---|
2668 | {
|
---|
2669 | /* XMM, [mem] */
|
---|
2670 | IEM_MC_BEGIN(0, 2);
|
---|
2671 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2672 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); /** @todo order */
|
---|
2673 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
|
---|
2674 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2675 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
2676 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
|
---|
2677 | {
|
---|
2678 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
2679 | IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2680 | IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
|
---|
2681 | }
|
---|
2682 | else
|
---|
2683 | {
|
---|
2684 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
2685 | IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2686 | IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
|
---|
2687 | }
|
---|
2688 | IEM_MC_ADVANCE_RIP();
|
---|
2689 | IEM_MC_END();
|
---|
2690 | }
|
---|
2691 | return VINF_SUCCESS;
|
---|
2692 |
|
---|
2693 | case 0: /* MMX */
|
---|
2694 | IEMOP_MNEMONIC("movq/d Pd/q,Ed/q");
|
---|
2695 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2696 | {
|
---|
2697 | /* MMX, greg */
|
---|
2698 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2699 | IEM_MC_BEGIN(0, 1);
|
---|
2700 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
2701 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
2702 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
2703 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
|
---|
2704 | IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
2705 | else
|
---|
2706 | IEM_MC_FETCH_GREG_U32_ZX_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
2707 | IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
|
---|
2708 | IEM_MC_ADVANCE_RIP();
|
---|
2709 | IEM_MC_END();
|
---|
2710 | }
|
---|
2711 | else
|
---|
2712 | {
|
---|
2713 | /* MMX, [mem] */
|
---|
2714 | IEM_MC_BEGIN(0, 2);
|
---|
2715 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2716 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
2717 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
|
---|
2718 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2719 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
2720 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
|
---|
2721 | {
|
---|
2722 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
2723 | IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2724 | IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
|
---|
2725 | }
|
---|
2726 | else
|
---|
2727 | {
|
---|
2728 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
2729 | IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2730 | IEM_MC_STORE_MREG_U32_ZX_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u32Tmp);
|
---|
2731 | }
|
---|
2732 | IEM_MC_ADVANCE_RIP();
|
---|
2733 | IEM_MC_END();
|
---|
2734 | }
|
---|
2735 | return VINF_SUCCESS;
|
---|
2736 |
|
---|
2737 | default:
|
---|
2738 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2739 | }
|
---|
2740 | }
|
---|
2741 |
|
---|
2742 |
|
---|
2743 | /** Opcode 0x0f 0x6f. */
|
---|
2744 | FNIEMOP_DEF(iemOp_movq_Pq_Qq__movdqa_Vdq_Wdq__movdqu_Vdq_Wdq)
|
---|
2745 | {
|
---|
2746 | bool fAligned = false;
|
---|
2747 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
2748 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
2749 | {
|
---|
2750 | case IEM_OP_PRF_SIZE_OP: /* SSE aligned */
|
---|
2751 | fAligned = true;
|
---|
2752 | case IEM_OP_PRF_REPZ: /* SSE unaligned */
|
---|
2753 | if (fAligned)
|
---|
2754 | IEMOP_MNEMONIC("movdqa Vdq,Wdq");
|
---|
2755 | else
|
---|
2756 | IEMOP_MNEMONIC("movdqu Vdq,Wdq");
|
---|
2757 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2758 | {
|
---|
2759 | /*
|
---|
2760 | * Register, register.
|
---|
2761 | */
|
---|
2762 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2763 | IEM_MC_BEGIN(0, 0);
|
---|
2764 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2765 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
2766 | IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
|
---|
2767 | (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
2768 | IEM_MC_ADVANCE_RIP();
|
---|
2769 | IEM_MC_END();
|
---|
2770 | }
|
---|
2771 | else
|
---|
2772 | {
|
---|
2773 | /*
|
---|
2774 | * Register, memory.
|
---|
2775 | */
|
---|
2776 | IEM_MC_BEGIN(0, 2);
|
---|
2777 | IEM_MC_LOCAL(uint128_t, u128Tmp);
|
---|
2778 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2779 |
|
---|
2780 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
2781 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2782 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2783 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
2784 | if (fAligned)
|
---|
2785 | IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2786 | else
|
---|
2787 | IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2788 | IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
|
---|
2789 |
|
---|
2790 | IEM_MC_ADVANCE_RIP();
|
---|
2791 | IEM_MC_END();
|
---|
2792 | }
|
---|
2793 | return VINF_SUCCESS;
|
---|
2794 |
|
---|
2795 | case 0: /* MMX */
|
---|
2796 | IEMOP_MNEMONIC("movq Pq,Qq");
|
---|
2797 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2798 | {
|
---|
2799 | /*
|
---|
2800 | * Register, register.
|
---|
2801 | */
|
---|
2802 | /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
|
---|
2803 | /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
|
---|
2804 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2805 | IEM_MC_BEGIN(0, 1);
|
---|
2806 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
2807 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
2808 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
2809 | IEM_MC_FETCH_MREG_U64(u64Tmp, bRm & X86_MODRM_RM_MASK);
|
---|
2810 | IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
|
---|
2811 | IEM_MC_ADVANCE_RIP();
|
---|
2812 | IEM_MC_END();
|
---|
2813 | }
|
---|
2814 | else
|
---|
2815 | {
|
---|
2816 | /*
|
---|
2817 | * Register, memory.
|
---|
2818 | */
|
---|
2819 | IEM_MC_BEGIN(0, 2);
|
---|
2820 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
2821 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2822 |
|
---|
2823 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
2824 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2825 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
2826 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
2827 | IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2828 | IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
|
---|
2829 |
|
---|
2830 | IEM_MC_ADVANCE_RIP();
|
---|
2831 | IEM_MC_END();
|
---|
2832 | }
|
---|
2833 | return VINF_SUCCESS;
|
---|
2834 |
|
---|
2835 | default:
|
---|
2836 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2837 | }
|
---|
2838 | }
|
---|
2839 |
|
---|
2840 |
|
---|
2841 | /** Opcode 0x0f 0x70. The immediate here is evil! */
|
---|
2842 | FNIEMOP_DEF(iemOp_pshufw_Pq_Qq_Ib__pshufd_Vdq_Wdq_Ib__pshufhw_Vdq_Wdq_Ib__pshuflq_Vdq_Wdq_Ib)
|
---|
2843 | {
|
---|
2844 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
2845 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
2846 | {
|
---|
2847 | case IEM_OP_PRF_SIZE_OP: /* SSE */
|
---|
2848 | case IEM_OP_PRF_REPNZ: /* SSE */
|
---|
2849 | case IEM_OP_PRF_REPZ: /* SSE */
|
---|
2850 | {
|
---|
2851 | PFNIEMAIMPLMEDIAPSHUF pfnAImpl;
|
---|
2852 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
2853 | {
|
---|
2854 | case IEM_OP_PRF_SIZE_OP:
|
---|
2855 | IEMOP_MNEMONIC("pshufd Vdq,Wdq,Ib");
|
---|
2856 | pfnAImpl = iemAImpl_pshufd;
|
---|
2857 | break;
|
---|
2858 | case IEM_OP_PRF_REPNZ:
|
---|
2859 | IEMOP_MNEMONIC("pshuflw Vdq,Wdq,Ib");
|
---|
2860 | pfnAImpl = iemAImpl_pshuflw;
|
---|
2861 | break;
|
---|
2862 | case IEM_OP_PRF_REPZ:
|
---|
2863 | IEMOP_MNEMONIC("pshufhw Vdq,Wdq,Ib");
|
---|
2864 | pfnAImpl = iemAImpl_pshufhw;
|
---|
2865 | break;
|
---|
2866 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
2867 | }
|
---|
2868 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2869 | {
|
---|
2870 | /*
|
---|
2871 | * Register, register.
|
---|
2872 | */
|
---|
2873 | uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
|
---|
2874 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2875 |
|
---|
2876 | IEM_MC_BEGIN(3, 0);
|
---|
2877 | IEM_MC_ARG(uint128_t *, pDst, 0);
|
---|
2878 | IEM_MC_ARG(uint128_t const *, pSrc, 1);
|
---|
2879 | IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
|
---|
2880 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2881 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
2882 | IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
2883 | IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
2884 | IEM_MC_CALL_SSE_AIMPL_3(pfnAImpl, pDst, pSrc, bEvilArg);
|
---|
2885 | IEM_MC_ADVANCE_RIP();
|
---|
2886 | IEM_MC_END();
|
---|
2887 | }
|
---|
2888 | else
|
---|
2889 | {
|
---|
2890 | /*
|
---|
2891 | * Register, memory.
|
---|
2892 | */
|
---|
2893 | IEM_MC_BEGIN(3, 2);
|
---|
2894 | IEM_MC_ARG(uint128_t *, pDst, 0);
|
---|
2895 | IEM_MC_LOCAL(uint128_t, uSrc);
|
---|
2896 | IEM_MC_ARG_LOCAL_REF(uint128_t const *, pSrc, uSrc, 1);
|
---|
2897 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2898 |
|
---|
2899 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
2900 | uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
|
---|
2901 | IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
|
---|
2902 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2903 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
2904 |
|
---|
2905 | IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2906 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
2907 | IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
2908 | IEM_MC_CALL_SSE_AIMPL_3(pfnAImpl, pDst, pSrc, bEvilArg);
|
---|
2909 |
|
---|
2910 | IEM_MC_ADVANCE_RIP();
|
---|
2911 | IEM_MC_END();
|
---|
2912 | }
|
---|
2913 | return VINF_SUCCESS;
|
---|
2914 | }
|
---|
2915 |
|
---|
2916 | case 0: /* MMX Extension */
|
---|
2917 | IEMOP_MNEMONIC("pshufw Pq,Qq,Ib");
|
---|
2918 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
2919 | {
|
---|
2920 | /*
|
---|
2921 | * Register, register.
|
---|
2922 | */
|
---|
2923 | uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
|
---|
2924 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2925 |
|
---|
2926 | IEM_MC_BEGIN(3, 0);
|
---|
2927 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
2928 | IEM_MC_ARG(uint64_t const *, pSrc, 1);
|
---|
2929 | IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
|
---|
2930 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
|
---|
2931 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
2932 | IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
2933 | IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
|
---|
2934 | IEM_MC_CALL_MMX_AIMPL_3(iemAImpl_pshufw, pDst, pSrc, bEvilArg);
|
---|
2935 | IEM_MC_ADVANCE_RIP();
|
---|
2936 | IEM_MC_END();
|
---|
2937 | }
|
---|
2938 | else
|
---|
2939 | {
|
---|
2940 | /*
|
---|
2941 | * Register, memory.
|
---|
2942 | */
|
---|
2943 | IEM_MC_BEGIN(3, 2);
|
---|
2944 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
2945 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
2946 | IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
|
---|
2947 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
2948 |
|
---|
2949 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
2950 | uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
|
---|
2951 | IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
|
---|
2952 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
2953 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
|
---|
2954 |
|
---|
2955 | IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
2956 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
2957 | IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
2958 | IEM_MC_CALL_MMX_AIMPL_3(iemAImpl_pshufw, pDst, pSrc, bEvilArg);
|
---|
2959 |
|
---|
2960 | IEM_MC_ADVANCE_RIP();
|
---|
2961 | IEM_MC_END();
|
---|
2962 | }
|
---|
2963 | return VINF_SUCCESS;
|
---|
2964 |
|
---|
2965 | default:
|
---|
2966 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2967 | }
|
---|
2968 | }
|
---|
2969 |
|
---|
2970 |
|
---|
2971 | /** Opcode 0x0f 0x71 11/2. */
|
---|
2972 | FNIEMOP_STUB_1(iemOp_Grp12_psrlw_Nq_Ib, uint8_t, bRm);
|
---|
2973 |
|
---|
2974 | /** Opcode 0x66 0x0f 0x71 11/2. */
|
---|
2975 | FNIEMOP_STUB_1(iemOp_Grp12_psrlw_Udq_Ib, uint8_t, bRm);
|
---|
2976 |
|
---|
2977 | /** Opcode 0x0f 0x71 11/4. */
|
---|
2978 | FNIEMOP_STUB_1(iemOp_Grp12_psraw_Nq_Ib, uint8_t, bRm);
|
---|
2979 |
|
---|
2980 | /** Opcode 0x66 0x0f 0x71 11/4. */
|
---|
2981 | FNIEMOP_STUB_1(iemOp_Grp12_psraw_Udq_Ib, uint8_t, bRm);
|
---|
2982 |
|
---|
2983 | /** Opcode 0x0f 0x71 11/6. */
|
---|
2984 | FNIEMOP_STUB_1(iemOp_Grp12_psllw_Nq_Ib, uint8_t, bRm);
|
---|
2985 |
|
---|
2986 | /** Opcode 0x66 0x0f 0x71 11/6. */
|
---|
2987 | FNIEMOP_STUB_1(iemOp_Grp12_psllw_Udq_Ib, uint8_t, bRm);
|
---|
2988 |
|
---|
2989 |
|
---|
2990 | /** Opcode 0x0f 0x71. */
|
---|
2991 | FNIEMOP_DEF(iemOp_Grp12)
|
---|
2992 | {
|
---|
2993 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
2994 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
2995 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
2996 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
2997 | {
|
---|
2998 | case 0: case 1: case 3: case 5: case 7:
|
---|
2999 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3000 | case 2:
|
---|
3001 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3002 | {
|
---|
3003 | case 0: return FNIEMOP_CALL_1(iemOp_Grp12_psrlw_Nq_Ib, bRm);
|
---|
3004 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp12_psrlw_Udq_Ib, bRm);
|
---|
3005 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3006 | }
|
---|
3007 | case 4:
|
---|
3008 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3009 | {
|
---|
3010 | case 0: return FNIEMOP_CALL_1(iemOp_Grp12_psraw_Nq_Ib, bRm);
|
---|
3011 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp12_psraw_Udq_Ib, bRm);
|
---|
3012 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3013 | }
|
---|
3014 | case 6:
|
---|
3015 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3016 | {
|
---|
3017 | case 0: return FNIEMOP_CALL_1(iemOp_Grp12_psllw_Nq_Ib, bRm);
|
---|
3018 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp12_psllw_Udq_Ib, bRm);
|
---|
3019 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3020 | }
|
---|
3021 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
3022 | }
|
---|
3023 | }
|
---|
3024 |
|
---|
3025 |
|
---|
3026 | /** Opcode 0x0f 0x72 11/2. */
|
---|
3027 | FNIEMOP_STUB_1(iemOp_Grp13_psrld_Nq_Ib, uint8_t, bRm);
|
---|
3028 |
|
---|
3029 | /** Opcode 0x66 0x0f 0x72 11/2. */
|
---|
3030 | FNIEMOP_STUB_1(iemOp_Grp13_psrld_Udq_Ib, uint8_t, bRm);
|
---|
3031 |
|
---|
3032 | /** Opcode 0x0f 0x72 11/4. */
|
---|
3033 | FNIEMOP_STUB_1(iemOp_Grp13_psrad_Nq_Ib, uint8_t, bRm);
|
---|
3034 |
|
---|
3035 | /** Opcode 0x66 0x0f 0x72 11/4. */
|
---|
3036 | FNIEMOP_STUB_1(iemOp_Grp13_psrad_Udq_Ib, uint8_t, bRm);
|
---|
3037 |
|
---|
3038 | /** Opcode 0x0f 0x72 11/6. */
|
---|
3039 | FNIEMOP_STUB_1(iemOp_Grp13_pslld_Nq_Ib, uint8_t, bRm);
|
---|
3040 |
|
---|
3041 | /** Opcode 0x66 0x0f 0x72 11/6. */
|
---|
3042 | FNIEMOP_STUB_1(iemOp_Grp13_pslld_Udq_Ib, uint8_t, bRm);
|
---|
3043 |
|
---|
3044 |
|
---|
3045 | /** Opcode 0x0f 0x72. */
|
---|
3046 | FNIEMOP_DEF(iemOp_Grp13)
|
---|
3047 | {
|
---|
3048 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
3049 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
3050 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3051 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
3052 | {
|
---|
3053 | case 0: case 1: case 3: case 5: case 7:
|
---|
3054 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3055 | case 2:
|
---|
3056 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3057 | {
|
---|
3058 | case 0: return FNIEMOP_CALL_1(iemOp_Grp13_psrld_Nq_Ib, bRm);
|
---|
3059 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp13_psrld_Udq_Ib, bRm);
|
---|
3060 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3061 | }
|
---|
3062 | case 4:
|
---|
3063 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3064 | {
|
---|
3065 | case 0: return FNIEMOP_CALL_1(iemOp_Grp13_psrad_Nq_Ib, bRm);
|
---|
3066 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp13_psrad_Udq_Ib, bRm);
|
---|
3067 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3068 | }
|
---|
3069 | case 6:
|
---|
3070 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3071 | {
|
---|
3072 | case 0: return FNIEMOP_CALL_1(iemOp_Grp13_pslld_Nq_Ib, bRm);
|
---|
3073 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp13_pslld_Udq_Ib, bRm);
|
---|
3074 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3075 | }
|
---|
3076 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
3077 | }
|
---|
3078 | }
|
---|
3079 |
|
---|
3080 |
|
---|
3081 | /** Opcode 0x0f 0x73 11/2. */
|
---|
3082 | FNIEMOP_STUB_1(iemOp_Grp14_psrlq_Nq_Ib, uint8_t, bRm);
|
---|
3083 |
|
---|
3084 | /** Opcode 0x66 0x0f 0x73 11/2. */
|
---|
3085 | FNIEMOP_STUB_1(iemOp_Grp14_psrlq_Udq_Ib, uint8_t, bRm);
|
---|
3086 |
|
---|
3087 | /** Opcode 0x66 0x0f 0x73 11/3. */
|
---|
3088 | FNIEMOP_STUB_1(iemOp_Grp14_psrldq_Udq_Ib, uint8_t, bRm); //NEXT
|
---|
3089 |
|
---|
3090 | /** Opcode 0x0f 0x73 11/6. */
|
---|
3091 | FNIEMOP_STUB_1(iemOp_Grp14_psllq_Nq_Ib, uint8_t, bRm);
|
---|
3092 |
|
---|
3093 | /** Opcode 0x66 0x0f 0x73 11/6. */
|
---|
3094 | FNIEMOP_STUB_1(iemOp_Grp14_psllq_Udq_Ib, uint8_t, bRm);
|
---|
3095 |
|
---|
3096 | /** Opcode 0x66 0x0f 0x73 11/7. */
|
---|
3097 | FNIEMOP_STUB_1(iemOp_Grp14_pslldq_Udq_Ib, uint8_t, bRm); //NEXT
|
---|
3098 |
|
---|
3099 |
|
---|
3100 | /** Opcode 0x0f 0x73. */
|
---|
3101 | FNIEMOP_DEF(iemOp_Grp14)
|
---|
3102 | {
|
---|
3103 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
3104 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
3105 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3106 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
3107 | {
|
---|
3108 | case 0: case 1: case 4: case 5:
|
---|
3109 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3110 | case 2:
|
---|
3111 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3112 | {
|
---|
3113 | case 0: return FNIEMOP_CALL_1(iemOp_Grp14_psrlq_Nq_Ib, bRm);
|
---|
3114 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp14_psrlq_Udq_Ib, bRm);
|
---|
3115 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3116 | }
|
---|
3117 | case 3:
|
---|
3118 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3119 | {
|
---|
3120 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp14_psrldq_Udq_Ib, bRm);
|
---|
3121 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3122 | }
|
---|
3123 | case 6:
|
---|
3124 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3125 | {
|
---|
3126 | case 0: return FNIEMOP_CALL_1(iemOp_Grp14_psllq_Nq_Ib, bRm);
|
---|
3127 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp14_psllq_Udq_Ib, bRm);
|
---|
3128 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3129 | }
|
---|
3130 | case 7:
|
---|
3131 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
3132 | {
|
---|
3133 | case IEM_OP_PRF_SIZE_OP: return FNIEMOP_CALL_1(iemOp_Grp14_pslldq_Udq_Ib, bRm);
|
---|
3134 | default: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3135 | }
|
---|
3136 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
3137 | }
|
---|
3138 | }
|
---|
3139 |
|
---|
3140 |
|
---|
3141 | /**
|
---|
3142 | * Common worker for SSE2 and MMX instructions on the forms:
|
---|
3143 | * pxxx mm1, mm2/mem64
|
---|
3144 | * pxxx xmm1, xmm2/mem128
|
---|
3145 | *
|
---|
3146 | * Proper alignment of the 128-bit operand is enforced.
|
---|
3147 | * Exceptions type 4. SSE2 and MMX cpuid checks.
|
---|
3148 | */
|
---|
3149 | FNIEMOP_DEF_1(iemOpCommonMmxSse2_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
|
---|
3150 | {
|
---|
3151 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
3152 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
3153 | {
|
---|
3154 | case IEM_OP_PRF_SIZE_OP: /* SSE */
|
---|
3155 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
3156 | {
|
---|
3157 | /*
|
---|
3158 | * Register, register.
|
---|
3159 | */
|
---|
3160 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3161 | IEM_MC_BEGIN(2, 0);
|
---|
3162 | IEM_MC_ARG(uint128_t *, pDst, 0);
|
---|
3163 | IEM_MC_ARG(uint128_t const *, pSrc, 1);
|
---|
3164 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
3165 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
3166 | IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
3167 | IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
3168 | IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
|
---|
3169 | IEM_MC_ADVANCE_RIP();
|
---|
3170 | IEM_MC_END();
|
---|
3171 | }
|
---|
3172 | else
|
---|
3173 | {
|
---|
3174 | /*
|
---|
3175 | * Register, memory.
|
---|
3176 | */
|
---|
3177 | IEM_MC_BEGIN(2, 2);
|
---|
3178 | IEM_MC_ARG(uint128_t *, pDst, 0);
|
---|
3179 | IEM_MC_LOCAL(uint128_t, uSrc);
|
---|
3180 | IEM_MC_ARG_LOCAL_REF(uint128_t const *, pSrc, uSrc, 1);
|
---|
3181 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
3182 |
|
---|
3183 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
3184 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3185 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
3186 | IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
3187 |
|
---|
3188 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
3189 | IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
3190 | IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
|
---|
3191 |
|
---|
3192 | IEM_MC_ADVANCE_RIP();
|
---|
3193 | IEM_MC_END();
|
---|
3194 | }
|
---|
3195 | return VINF_SUCCESS;
|
---|
3196 |
|
---|
3197 | case 0: /* MMX */
|
---|
3198 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
3199 | {
|
---|
3200 | /*
|
---|
3201 | * Register, register.
|
---|
3202 | */
|
---|
3203 | /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
|
---|
3204 | /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
|
---|
3205 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3206 | IEM_MC_BEGIN(2, 0);
|
---|
3207 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
3208 | IEM_MC_ARG(uint64_t const *, pSrc, 1);
|
---|
3209 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
3210 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
3211 | IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
3212 | IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
|
---|
3213 | IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
|
---|
3214 | IEM_MC_ADVANCE_RIP();
|
---|
3215 | IEM_MC_END();
|
---|
3216 | }
|
---|
3217 | else
|
---|
3218 | {
|
---|
3219 | /*
|
---|
3220 | * Register, memory.
|
---|
3221 | */
|
---|
3222 | IEM_MC_BEGIN(2, 2);
|
---|
3223 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
3224 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
3225 | IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
|
---|
3226 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
3227 |
|
---|
3228 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
3229 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3230 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
3231 | IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
3232 |
|
---|
3233 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
3234 | IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
3235 | IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
|
---|
3236 |
|
---|
3237 | IEM_MC_ADVANCE_RIP();
|
---|
3238 | IEM_MC_END();
|
---|
3239 | }
|
---|
3240 | return VINF_SUCCESS;
|
---|
3241 |
|
---|
3242 | default:
|
---|
3243 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3244 | }
|
---|
3245 | }
|
---|
3246 |
|
---|
3247 |
|
---|
3248 | /** Opcode 0x0f 0x74. */
|
---|
3249 | FNIEMOP_DEF(iemOp_pcmpeqb_Pq_Qq__pcmpeqb_Vdq_Wdq)
|
---|
3250 | {
|
---|
3251 | IEMOP_MNEMONIC("pcmpeqb");
|
---|
3252 | return FNIEMOP_CALL_1(iemOpCommonMmxSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqb);
|
---|
3253 | }
|
---|
3254 |
|
---|
3255 |
|
---|
3256 | /** Opcode 0x0f 0x75. */
|
---|
3257 | FNIEMOP_DEF(iemOp_pcmpeqw_Pq_Qq__pcmpeqw_Vdq_Wdq)
|
---|
3258 | {
|
---|
3259 | IEMOP_MNEMONIC("pcmpeqw");
|
---|
3260 | return FNIEMOP_CALL_1(iemOpCommonMmxSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqw);
|
---|
3261 | }
|
---|
3262 |
|
---|
3263 |
|
---|
3264 | /** Opcode 0x0f 0x76. */
|
---|
3265 | FNIEMOP_DEF(iemOp_pcmped_Pq_Qq__pcmpeqd_Vdq_Wdq)
|
---|
3266 | {
|
---|
3267 | IEMOP_MNEMONIC("pcmpeqd");
|
---|
3268 | return FNIEMOP_CALL_1(iemOpCommonMmxSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqd);
|
---|
3269 | }
|
---|
3270 |
|
---|
3271 |
|
---|
3272 | /** Opcode 0x0f 0x77. */
|
---|
3273 | FNIEMOP_STUB(iemOp_emms);
|
---|
3274 | /** Opcode 0x0f 0x78. */
|
---|
3275 | FNIEMOP_UD_STUB(iemOp_vmread_AmdGrp17);
|
---|
3276 | /** Opcode 0x0f 0x79. */
|
---|
3277 | FNIEMOP_UD_STUB(iemOp_vmwrite);
|
---|
3278 | /** Opcode 0x0f 0x7c. */
|
---|
3279 | FNIEMOP_STUB(iemOp_haddpd_Vdp_Wpd__haddps_Vps_Wps);
|
---|
3280 | /** Opcode 0x0f 0x7d. */
|
---|
3281 | FNIEMOP_STUB(iemOp_hsubpd_Vpd_Wpd__hsubps_Vps_Wps);
|
---|
3282 |
|
---|
3283 |
|
---|
3284 | /** Opcode 0x0f 0x7e. */
|
---|
3285 | FNIEMOP_DEF(iemOp_movd_q_Ey_Pd__movd_q_Ey_Vy__movq_Vq_Wq)
|
---|
3286 | {
|
---|
3287 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
3288 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
3289 | {
|
---|
3290 | case IEM_OP_PRF_SIZE_OP: /* SSE */
|
---|
3291 | IEMOP_MNEMONIC("movd/q Ed/q,Wd/q");
|
---|
3292 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
3293 | {
|
---|
3294 | /* greg, XMM */
|
---|
3295 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3296 | IEM_MC_BEGIN(0, 1);
|
---|
3297 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
3298 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
|
---|
3299 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
|
---|
3300 | {
|
---|
3301 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
3302 | IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
3303 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
|
---|
3304 | }
|
---|
3305 | else
|
---|
3306 | {
|
---|
3307 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
3308 | IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
3309 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
|
---|
3310 | }
|
---|
3311 | IEM_MC_ADVANCE_RIP();
|
---|
3312 | IEM_MC_END();
|
---|
3313 | }
|
---|
3314 | else
|
---|
3315 | {
|
---|
3316 | /* [mem], XMM */
|
---|
3317 | IEM_MC_BEGIN(0, 2);
|
---|
3318 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
3319 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
3320 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
|
---|
3321 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3322 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
|
---|
3323 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
|
---|
3324 | {
|
---|
3325 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
3326 | IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
3327 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
|
---|
3328 | }
|
---|
3329 | else
|
---|
3330 | {
|
---|
3331 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
3332 | IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
3333 | IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
|
---|
3334 | }
|
---|
3335 | IEM_MC_ADVANCE_RIP();
|
---|
3336 | IEM_MC_END();
|
---|
3337 | }
|
---|
3338 | return VINF_SUCCESS;
|
---|
3339 |
|
---|
3340 | case 0: /* MMX */
|
---|
3341 | IEMOP_MNEMONIC("movq/d Ed/q,Pd/q");
|
---|
3342 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
3343 | {
|
---|
3344 | /* greg, MMX */
|
---|
3345 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3346 | IEM_MC_BEGIN(0, 1);
|
---|
3347 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
3348 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
3349 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
|
---|
3350 | {
|
---|
3351 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
3352 | IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
3353 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
|
---|
3354 | }
|
---|
3355 | else
|
---|
3356 | {
|
---|
3357 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
3358 | IEM_MC_FETCH_MREG_U32(u32Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
3359 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
|
---|
3360 | }
|
---|
3361 | IEM_MC_ADVANCE_RIP();
|
---|
3362 | IEM_MC_END();
|
---|
3363 | }
|
---|
3364 | else
|
---|
3365 | {
|
---|
3366 | /* [mem], MMX */
|
---|
3367 | IEM_MC_BEGIN(0, 2);
|
---|
3368 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
3369 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
3370 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
|
---|
3371 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3372 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
3373 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
|
---|
3374 | {
|
---|
3375 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
3376 | IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
3377 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
|
---|
3378 | }
|
---|
3379 | else
|
---|
3380 | {
|
---|
3381 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
3382 | IEM_MC_FETCH_MREG_U32(u32Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
3383 | IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
|
---|
3384 | }
|
---|
3385 | IEM_MC_ADVANCE_RIP();
|
---|
3386 | IEM_MC_END();
|
---|
3387 | }
|
---|
3388 | return VINF_SUCCESS;
|
---|
3389 |
|
---|
3390 | default:
|
---|
3391 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3392 | }
|
---|
3393 | }
|
---|
3394 |
|
---|
3395 |
|
---|
3396 | /** Opcode 0x0f 0x7f. */
|
---|
3397 | FNIEMOP_DEF(iemOp_movq_Qq_Pq__movq_movdqa_Wdq_Vdq__movdqu_Wdq_Vdq)
|
---|
3398 | {
|
---|
3399 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
3400 | bool fAligned = false;
|
---|
3401 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
3402 | {
|
---|
3403 | case IEM_OP_PRF_SIZE_OP: /* SSE aligned */
|
---|
3404 | fAligned = true;
|
---|
3405 | case IEM_OP_PRF_REPZ: /* SSE unaligned */
|
---|
3406 | if (fAligned)
|
---|
3407 | IEMOP_MNEMONIC("movdqa Wdq,Vdq");
|
---|
3408 | else
|
---|
3409 | IEMOP_MNEMONIC("movdqu Wdq,Vdq");
|
---|
3410 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
3411 | {
|
---|
3412 | /*
|
---|
3413 | * Register, register.
|
---|
3414 | */
|
---|
3415 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3416 | IEM_MC_BEGIN(0, 0);
|
---|
3417 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
3418 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
|
---|
3419 | IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
|
---|
3420 | ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
3421 | IEM_MC_ADVANCE_RIP();
|
---|
3422 | IEM_MC_END();
|
---|
3423 | }
|
---|
3424 | else
|
---|
3425 | {
|
---|
3426 | /*
|
---|
3427 | * Register, memory.
|
---|
3428 | */
|
---|
3429 | IEM_MC_BEGIN(0, 2);
|
---|
3430 | IEM_MC_LOCAL(uint128_t, u128Tmp);
|
---|
3431 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
3432 |
|
---|
3433 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
3434 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3435 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
3436 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
|
---|
3437 |
|
---|
3438 | IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
3439 | if (fAligned)
|
---|
3440 | IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
|
---|
3441 | else
|
---|
3442 | IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
|
---|
3443 |
|
---|
3444 | IEM_MC_ADVANCE_RIP();
|
---|
3445 | IEM_MC_END();
|
---|
3446 | }
|
---|
3447 | return VINF_SUCCESS;
|
---|
3448 |
|
---|
3449 | case 0: /* MMX */
|
---|
3450 | IEMOP_MNEMONIC("movq Qq,Pq");
|
---|
3451 |
|
---|
3452 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
3453 | {
|
---|
3454 | /*
|
---|
3455 | * Register, register.
|
---|
3456 | */
|
---|
3457 | /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
|
---|
3458 | /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
|
---|
3459 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3460 | IEM_MC_BEGIN(0, 1);
|
---|
3461 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
3462 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
3463 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
3464 | IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
3465 | IEM_MC_STORE_MREG_U64(bRm & X86_MODRM_RM_MASK, u64Tmp);
|
---|
3466 | IEM_MC_ADVANCE_RIP();
|
---|
3467 | IEM_MC_END();
|
---|
3468 | }
|
---|
3469 | else
|
---|
3470 | {
|
---|
3471 | /*
|
---|
3472 | * Register, memory.
|
---|
3473 | */
|
---|
3474 | IEM_MC_BEGIN(0, 2);
|
---|
3475 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
3476 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
3477 |
|
---|
3478 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
3479 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3480 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
3481 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
3482 |
|
---|
3483 | IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
3484 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
|
---|
3485 |
|
---|
3486 | IEM_MC_ADVANCE_RIP();
|
---|
3487 | IEM_MC_END();
|
---|
3488 | }
|
---|
3489 | return VINF_SUCCESS;
|
---|
3490 |
|
---|
3491 | default:
|
---|
3492 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
3493 | }
|
---|
3494 | }
|
---|
3495 |
|
---|
3496 |
|
---|
3497 |
|
---|
3498 | /** Opcode 0x0f 0x80. */
|
---|
3499 | FNIEMOP_DEF(iemOp_jo_Jv)
|
---|
3500 | {
|
---|
3501 | IEMOP_MNEMONIC("jo Jv");
|
---|
3502 | IEMOP_HLP_MIN_386();
|
---|
3503 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3504 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3505 | {
|
---|
3506 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3507 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3508 |
|
---|
3509 | IEM_MC_BEGIN(0, 0);
|
---|
3510 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
3511 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3512 | } IEM_MC_ELSE() {
|
---|
3513 | IEM_MC_ADVANCE_RIP();
|
---|
3514 | } IEM_MC_ENDIF();
|
---|
3515 | IEM_MC_END();
|
---|
3516 | }
|
---|
3517 | else
|
---|
3518 | {
|
---|
3519 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3520 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3521 |
|
---|
3522 | IEM_MC_BEGIN(0, 0);
|
---|
3523 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
3524 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3525 | } IEM_MC_ELSE() {
|
---|
3526 | IEM_MC_ADVANCE_RIP();
|
---|
3527 | } IEM_MC_ENDIF();
|
---|
3528 | IEM_MC_END();
|
---|
3529 | }
|
---|
3530 | return VINF_SUCCESS;
|
---|
3531 | }
|
---|
3532 |
|
---|
3533 |
|
---|
3534 | /** Opcode 0x0f 0x81. */
|
---|
3535 | FNIEMOP_DEF(iemOp_jno_Jv)
|
---|
3536 | {
|
---|
3537 | IEMOP_MNEMONIC("jno Jv");
|
---|
3538 | IEMOP_HLP_MIN_386();
|
---|
3539 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3540 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3541 | {
|
---|
3542 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3543 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3544 |
|
---|
3545 | IEM_MC_BEGIN(0, 0);
|
---|
3546 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
3547 | IEM_MC_ADVANCE_RIP();
|
---|
3548 | } IEM_MC_ELSE() {
|
---|
3549 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3550 | } IEM_MC_ENDIF();
|
---|
3551 | IEM_MC_END();
|
---|
3552 | }
|
---|
3553 | else
|
---|
3554 | {
|
---|
3555 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3556 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3557 |
|
---|
3558 | IEM_MC_BEGIN(0, 0);
|
---|
3559 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
3560 | IEM_MC_ADVANCE_RIP();
|
---|
3561 | } IEM_MC_ELSE() {
|
---|
3562 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3563 | } IEM_MC_ENDIF();
|
---|
3564 | IEM_MC_END();
|
---|
3565 | }
|
---|
3566 | return VINF_SUCCESS;
|
---|
3567 | }
|
---|
3568 |
|
---|
3569 |
|
---|
3570 | /** Opcode 0x0f 0x82. */
|
---|
3571 | FNIEMOP_DEF(iemOp_jc_Jv)
|
---|
3572 | {
|
---|
3573 | IEMOP_MNEMONIC("jc/jb/jnae Jv");
|
---|
3574 | IEMOP_HLP_MIN_386();
|
---|
3575 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3576 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3577 | {
|
---|
3578 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3579 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3580 |
|
---|
3581 | IEM_MC_BEGIN(0, 0);
|
---|
3582 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
3583 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3584 | } IEM_MC_ELSE() {
|
---|
3585 | IEM_MC_ADVANCE_RIP();
|
---|
3586 | } IEM_MC_ENDIF();
|
---|
3587 | IEM_MC_END();
|
---|
3588 | }
|
---|
3589 | else
|
---|
3590 | {
|
---|
3591 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3592 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3593 |
|
---|
3594 | IEM_MC_BEGIN(0, 0);
|
---|
3595 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
3596 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3597 | } IEM_MC_ELSE() {
|
---|
3598 | IEM_MC_ADVANCE_RIP();
|
---|
3599 | } IEM_MC_ENDIF();
|
---|
3600 | IEM_MC_END();
|
---|
3601 | }
|
---|
3602 | return VINF_SUCCESS;
|
---|
3603 | }
|
---|
3604 |
|
---|
3605 |
|
---|
3606 | /** Opcode 0x0f 0x83. */
|
---|
3607 | FNIEMOP_DEF(iemOp_jnc_Jv)
|
---|
3608 | {
|
---|
3609 | IEMOP_MNEMONIC("jnc/jnb/jae Jv");
|
---|
3610 | IEMOP_HLP_MIN_386();
|
---|
3611 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3612 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3613 | {
|
---|
3614 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3615 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3616 |
|
---|
3617 | IEM_MC_BEGIN(0, 0);
|
---|
3618 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
3619 | IEM_MC_ADVANCE_RIP();
|
---|
3620 | } IEM_MC_ELSE() {
|
---|
3621 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3622 | } IEM_MC_ENDIF();
|
---|
3623 | IEM_MC_END();
|
---|
3624 | }
|
---|
3625 | else
|
---|
3626 | {
|
---|
3627 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3628 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3629 |
|
---|
3630 | IEM_MC_BEGIN(0, 0);
|
---|
3631 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
3632 | IEM_MC_ADVANCE_RIP();
|
---|
3633 | } IEM_MC_ELSE() {
|
---|
3634 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3635 | } IEM_MC_ENDIF();
|
---|
3636 | IEM_MC_END();
|
---|
3637 | }
|
---|
3638 | return VINF_SUCCESS;
|
---|
3639 | }
|
---|
3640 |
|
---|
3641 |
|
---|
3642 | /** Opcode 0x0f 0x84. */
|
---|
3643 | FNIEMOP_DEF(iemOp_je_Jv)
|
---|
3644 | {
|
---|
3645 | IEMOP_MNEMONIC("je/jz Jv");
|
---|
3646 | IEMOP_HLP_MIN_386();
|
---|
3647 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3648 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3649 | {
|
---|
3650 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3651 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3652 |
|
---|
3653 | IEM_MC_BEGIN(0, 0);
|
---|
3654 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
3655 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3656 | } IEM_MC_ELSE() {
|
---|
3657 | IEM_MC_ADVANCE_RIP();
|
---|
3658 | } IEM_MC_ENDIF();
|
---|
3659 | IEM_MC_END();
|
---|
3660 | }
|
---|
3661 | else
|
---|
3662 | {
|
---|
3663 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3664 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3665 |
|
---|
3666 | IEM_MC_BEGIN(0, 0);
|
---|
3667 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
3668 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3669 | } IEM_MC_ELSE() {
|
---|
3670 | IEM_MC_ADVANCE_RIP();
|
---|
3671 | } IEM_MC_ENDIF();
|
---|
3672 | IEM_MC_END();
|
---|
3673 | }
|
---|
3674 | return VINF_SUCCESS;
|
---|
3675 | }
|
---|
3676 |
|
---|
3677 |
|
---|
3678 | /** Opcode 0x0f 0x85. */
|
---|
3679 | FNIEMOP_DEF(iemOp_jne_Jv)
|
---|
3680 | {
|
---|
3681 | IEMOP_MNEMONIC("jne/jnz Jv");
|
---|
3682 | IEMOP_HLP_MIN_386();
|
---|
3683 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3684 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3685 | {
|
---|
3686 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3687 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3688 |
|
---|
3689 | IEM_MC_BEGIN(0, 0);
|
---|
3690 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
3691 | IEM_MC_ADVANCE_RIP();
|
---|
3692 | } IEM_MC_ELSE() {
|
---|
3693 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3694 | } IEM_MC_ENDIF();
|
---|
3695 | IEM_MC_END();
|
---|
3696 | }
|
---|
3697 | else
|
---|
3698 | {
|
---|
3699 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3700 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3701 |
|
---|
3702 | IEM_MC_BEGIN(0, 0);
|
---|
3703 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
3704 | IEM_MC_ADVANCE_RIP();
|
---|
3705 | } IEM_MC_ELSE() {
|
---|
3706 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3707 | } IEM_MC_ENDIF();
|
---|
3708 | IEM_MC_END();
|
---|
3709 | }
|
---|
3710 | return VINF_SUCCESS;
|
---|
3711 | }
|
---|
3712 |
|
---|
3713 |
|
---|
3714 | /** Opcode 0x0f 0x86. */
|
---|
3715 | FNIEMOP_DEF(iemOp_jbe_Jv)
|
---|
3716 | {
|
---|
3717 | IEMOP_MNEMONIC("jbe/jna Jv");
|
---|
3718 | IEMOP_HLP_MIN_386();
|
---|
3719 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3720 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3721 | {
|
---|
3722 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3723 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3724 |
|
---|
3725 | IEM_MC_BEGIN(0, 0);
|
---|
3726 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
3727 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3728 | } IEM_MC_ELSE() {
|
---|
3729 | IEM_MC_ADVANCE_RIP();
|
---|
3730 | } IEM_MC_ENDIF();
|
---|
3731 | IEM_MC_END();
|
---|
3732 | }
|
---|
3733 | else
|
---|
3734 | {
|
---|
3735 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3736 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3737 |
|
---|
3738 | IEM_MC_BEGIN(0, 0);
|
---|
3739 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
3740 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3741 | } IEM_MC_ELSE() {
|
---|
3742 | IEM_MC_ADVANCE_RIP();
|
---|
3743 | } IEM_MC_ENDIF();
|
---|
3744 | IEM_MC_END();
|
---|
3745 | }
|
---|
3746 | return VINF_SUCCESS;
|
---|
3747 | }
|
---|
3748 |
|
---|
3749 |
|
---|
3750 | /** Opcode 0x0f 0x87. */
|
---|
3751 | FNIEMOP_DEF(iemOp_jnbe_Jv)
|
---|
3752 | {
|
---|
3753 | IEMOP_MNEMONIC("jnbe/ja Jv");
|
---|
3754 | IEMOP_HLP_MIN_386();
|
---|
3755 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3756 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3757 | {
|
---|
3758 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3759 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3760 |
|
---|
3761 | IEM_MC_BEGIN(0, 0);
|
---|
3762 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
3763 | IEM_MC_ADVANCE_RIP();
|
---|
3764 | } IEM_MC_ELSE() {
|
---|
3765 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3766 | } IEM_MC_ENDIF();
|
---|
3767 | IEM_MC_END();
|
---|
3768 | }
|
---|
3769 | else
|
---|
3770 | {
|
---|
3771 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3772 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3773 |
|
---|
3774 | IEM_MC_BEGIN(0, 0);
|
---|
3775 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
3776 | IEM_MC_ADVANCE_RIP();
|
---|
3777 | } IEM_MC_ELSE() {
|
---|
3778 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3779 | } IEM_MC_ENDIF();
|
---|
3780 | IEM_MC_END();
|
---|
3781 | }
|
---|
3782 | return VINF_SUCCESS;
|
---|
3783 | }
|
---|
3784 |
|
---|
3785 |
|
---|
3786 | /** Opcode 0x0f 0x88. */
|
---|
3787 | FNIEMOP_DEF(iemOp_js_Jv)
|
---|
3788 | {
|
---|
3789 | IEMOP_MNEMONIC("js Jv");
|
---|
3790 | IEMOP_HLP_MIN_386();
|
---|
3791 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3792 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3793 | {
|
---|
3794 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3795 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3796 |
|
---|
3797 | IEM_MC_BEGIN(0, 0);
|
---|
3798 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
3799 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3800 | } IEM_MC_ELSE() {
|
---|
3801 | IEM_MC_ADVANCE_RIP();
|
---|
3802 | } IEM_MC_ENDIF();
|
---|
3803 | IEM_MC_END();
|
---|
3804 | }
|
---|
3805 | else
|
---|
3806 | {
|
---|
3807 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3808 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3809 |
|
---|
3810 | IEM_MC_BEGIN(0, 0);
|
---|
3811 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
3812 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3813 | } IEM_MC_ELSE() {
|
---|
3814 | IEM_MC_ADVANCE_RIP();
|
---|
3815 | } IEM_MC_ENDIF();
|
---|
3816 | IEM_MC_END();
|
---|
3817 | }
|
---|
3818 | return VINF_SUCCESS;
|
---|
3819 | }
|
---|
3820 |
|
---|
3821 |
|
---|
3822 | /** Opcode 0x0f 0x89. */
|
---|
3823 | FNIEMOP_DEF(iemOp_jns_Jv)
|
---|
3824 | {
|
---|
3825 | IEMOP_MNEMONIC("jns Jv");
|
---|
3826 | IEMOP_HLP_MIN_386();
|
---|
3827 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3828 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3829 | {
|
---|
3830 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3831 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3832 |
|
---|
3833 | IEM_MC_BEGIN(0, 0);
|
---|
3834 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
3835 | IEM_MC_ADVANCE_RIP();
|
---|
3836 | } IEM_MC_ELSE() {
|
---|
3837 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3838 | } IEM_MC_ENDIF();
|
---|
3839 | IEM_MC_END();
|
---|
3840 | }
|
---|
3841 | else
|
---|
3842 | {
|
---|
3843 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3844 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3845 |
|
---|
3846 | IEM_MC_BEGIN(0, 0);
|
---|
3847 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
3848 | IEM_MC_ADVANCE_RIP();
|
---|
3849 | } IEM_MC_ELSE() {
|
---|
3850 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3851 | } IEM_MC_ENDIF();
|
---|
3852 | IEM_MC_END();
|
---|
3853 | }
|
---|
3854 | return VINF_SUCCESS;
|
---|
3855 | }
|
---|
3856 |
|
---|
3857 |
|
---|
3858 | /** Opcode 0x0f 0x8a. */
|
---|
3859 | FNIEMOP_DEF(iemOp_jp_Jv)
|
---|
3860 | {
|
---|
3861 | IEMOP_MNEMONIC("jp Jv");
|
---|
3862 | IEMOP_HLP_MIN_386();
|
---|
3863 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3864 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3865 | {
|
---|
3866 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3867 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3868 |
|
---|
3869 | IEM_MC_BEGIN(0, 0);
|
---|
3870 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
3871 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3872 | } IEM_MC_ELSE() {
|
---|
3873 | IEM_MC_ADVANCE_RIP();
|
---|
3874 | } IEM_MC_ENDIF();
|
---|
3875 | IEM_MC_END();
|
---|
3876 | }
|
---|
3877 | else
|
---|
3878 | {
|
---|
3879 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3880 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3881 |
|
---|
3882 | IEM_MC_BEGIN(0, 0);
|
---|
3883 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
3884 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3885 | } IEM_MC_ELSE() {
|
---|
3886 | IEM_MC_ADVANCE_RIP();
|
---|
3887 | } IEM_MC_ENDIF();
|
---|
3888 | IEM_MC_END();
|
---|
3889 | }
|
---|
3890 | return VINF_SUCCESS;
|
---|
3891 | }
|
---|
3892 |
|
---|
3893 |
|
---|
3894 | /** Opcode 0x0f 0x8b. */
|
---|
3895 | FNIEMOP_DEF(iemOp_jnp_Jv)
|
---|
3896 | {
|
---|
3897 | IEMOP_MNEMONIC("jo Jv");
|
---|
3898 | IEMOP_HLP_MIN_386();
|
---|
3899 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3900 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3901 | {
|
---|
3902 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3903 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3904 |
|
---|
3905 | IEM_MC_BEGIN(0, 0);
|
---|
3906 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
3907 | IEM_MC_ADVANCE_RIP();
|
---|
3908 | } IEM_MC_ELSE() {
|
---|
3909 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3910 | } IEM_MC_ENDIF();
|
---|
3911 | IEM_MC_END();
|
---|
3912 | }
|
---|
3913 | else
|
---|
3914 | {
|
---|
3915 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3916 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3917 |
|
---|
3918 | IEM_MC_BEGIN(0, 0);
|
---|
3919 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
3920 | IEM_MC_ADVANCE_RIP();
|
---|
3921 | } IEM_MC_ELSE() {
|
---|
3922 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3923 | } IEM_MC_ENDIF();
|
---|
3924 | IEM_MC_END();
|
---|
3925 | }
|
---|
3926 | return VINF_SUCCESS;
|
---|
3927 | }
|
---|
3928 |
|
---|
3929 |
|
---|
3930 | /** Opcode 0x0f 0x8c. */
|
---|
3931 | FNIEMOP_DEF(iemOp_jl_Jv)
|
---|
3932 | {
|
---|
3933 | IEMOP_MNEMONIC("jl/jnge Jv");
|
---|
3934 | IEMOP_HLP_MIN_386();
|
---|
3935 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3936 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3937 | {
|
---|
3938 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3939 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3940 |
|
---|
3941 | IEM_MC_BEGIN(0, 0);
|
---|
3942 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
3943 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3944 | } IEM_MC_ELSE() {
|
---|
3945 | IEM_MC_ADVANCE_RIP();
|
---|
3946 | } IEM_MC_ENDIF();
|
---|
3947 | IEM_MC_END();
|
---|
3948 | }
|
---|
3949 | else
|
---|
3950 | {
|
---|
3951 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3952 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3953 |
|
---|
3954 | IEM_MC_BEGIN(0, 0);
|
---|
3955 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
3956 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3957 | } IEM_MC_ELSE() {
|
---|
3958 | IEM_MC_ADVANCE_RIP();
|
---|
3959 | } IEM_MC_ENDIF();
|
---|
3960 | IEM_MC_END();
|
---|
3961 | }
|
---|
3962 | return VINF_SUCCESS;
|
---|
3963 | }
|
---|
3964 |
|
---|
3965 |
|
---|
3966 | /** Opcode 0x0f 0x8d. */
|
---|
3967 | FNIEMOP_DEF(iemOp_jnl_Jv)
|
---|
3968 | {
|
---|
3969 | IEMOP_MNEMONIC("jnl/jge Jv");
|
---|
3970 | IEMOP_HLP_MIN_386();
|
---|
3971 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
3972 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
3973 | {
|
---|
3974 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
3975 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3976 |
|
---|
3977 | IEM_MC_BEGIN(0, 0);
|
---|
3978 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
3979 | IEM_MC_ADVANCE_RIP();
|
---|
3980 | } IEM_MC_ELSE() {
|
---|
3981 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
3982 | } IEM_MC_ENDIF();
|
---|
3983 | IEM_MC_END();
|
---|
3984 | }
|
---|
3985 | else
|
---|
3986 | {
|
---|
3987 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
3988 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
3989 |
|
---|
3990 | IEM_MC_BEGIN(0, 0);
|
---|
3991 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
3992 | IEM_MC_ADVANCE_RIP();
|
---|
3993 | } IEM_MC_ELSE() {
|
---|
3994 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
3995 | } IEM_MC_ENDIF();
|
---|
3996 | IEM_MC_END();
|
---|
3997 | }
|
---|
3998 | return VINF_SUCCESS;
|
---|
3999 | }
|
---|
4000 |
|
---|
4001 |
|
---|
4002 | /** Opcode 0x0f 0x8e. */
|
---|
4003 | FNIEMOP_DEF(iemOp_jle_Jv)
|
---|
4004 | {
|
---|
4005 | IEMOP_MNEMONIC("jle/jng Jv");
|
---|
4006 | IEMOP_HLP_MIN_386();
|
---|
4007 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
4008 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
4009 | {
|
---|
4010 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
4011 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4012 |
|
---|
4013 | IEM_MC_BEGIN(0, 0);
|
---|
4014 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
4015 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
4016 | } IEM_MC_ELSE() {
|
---|
4017 | IEM_MC_ADVANCE_RIP();
|
---|
4018 | } IEM_MC_ENDIF();
|
---|
4019 | IEM_MC_END();
|
---|
4020 | }
|
---|
4021 | else
|
---|
4022 | {
|
---|
4023 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
4024 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4025 |
|
---|
4026 | IEM_MC_BEGIN(0, 0);
|
---|
4027 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
4028 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
4029 | } IEM_MC_ELSE() {
|
---|
4030 | IEM_MC_ADVANCE_RIP();
|
---|
4031 | } IEM_MC_ENDIF();
|
---|
4032 | IEM_MC_END();
|
---|
4033 | }
|
---|
4034 | return VINF_SUCCESS;
|
---|
4035 | }
|
---|
4036 |
|
---|
4037 |
|
---|
4038 | /** Opcode 0x0f 0x8f. */
|
---|
4039 | FNIEMOP_DEF(iemOp_jnle_Jv)
|
---|
4040 | {
|
---|
4041 | IEMOP_MNEMONIC("jnle/jg Jv");
|
---|
4042 | IEMOP_HLP_MIN_386();
|
---|
4043 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
4044 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
4045 | {
|
---|
4046 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
4047 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4048 |
|
---|
4049 | IEM_MC_BEGIN(0, 0);
|
---|
4050 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
4051 | IEM_MC_ADVANCE_RIP();
|
---|
4052 | } IEM_MC_ELSE() {
|
---|
4053 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
4054 | } IEM_MC_ENDIF();
|
---|
4055 | IEM_MC_END();
|
---|
4056 | }
|
---|
4057 | else
|
---|
4058 | {
|
---|
4059 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
4060 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4061 |
|
---|
4062 | IEM_MC_BEGIN(0, 0);
|
---|
4063 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
4064 | IEM_MC_ADVANCE_RIP();
|
---|
4065 | } IEM_MC_ELSE() {
|
---|
4066 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
4067 | } IEM_MC_ENDIF();
|
---|
4068 | IEM_MC_END();
|
---|
4069 | }
|
---|
4070 | return VINF_SUCCESS;
|
---|
4071 | }
|
---|
4072 |
|
---|
4073 |
|
---|
4074 | /** Opcode 0x0f 0x90. */
|
---|
4075 | FNIEMOP_DEF(iemOp_seto_Eb)
|
---|
4076 | {
|
---|
4077 | IEMOP_MNEMONIC("seto Eb");
|
---|
4078 | IEMOP_HLP_MIN_386();
|
---|
4079 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4080 |
|
---|
4081 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4082 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4083 | * ignoring for now. */
|
---|
4084 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4085 | {
|
---|
4086 | /* register target */
|
---|
4087 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4088 | IEM_MC_BEGIN(0, 0);
|
---|
4089 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
4090 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4091 | } IEM_MC_ELSE() {
|
---|
4092 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4093 | } IEM_MC_ENDIF();
|
---|
4094 | IEM_MC_ADVANCE_RIP();
|
---|
4095 | IEM_MC_END();
|
---|
4096 | }
|
---|
4097 | else
|
---|
4098 | {
|
---|
4099 | /* memory target */
|
---|
4100 | IEM_MC_BEGIN(0, 1);
|
---|
4101 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4102 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4103 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4104 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
4105 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4106 | } IEM_MC_ELSE() {
|
---|
4107 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4108 | } IEM_MC_ENDIF();
|
---|
4109 | IEM_MC_ADVANCE_RIP();
|
---|
4110 | IEM_MC_END();
|
---|
4111 | }
|
---|
4112 | return VINF_SUCCESS;
|
---|
4113 | }
|
---|
4114 |
|
---|
4115 |
|
---|
4116 | /** Opcode 0x0f 0x91. */
|
---|
4117 | FNIEMOP_DEF(iemOp_setno_Eb)
|
---|
4118 | {
|
---|
4119 | IEMOP_MNEMONIC("setno Eb");
|
---|
4120 | IEMOP_HLP_MIN_386();
|
---|
4121 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4122 |
|
---|
4123 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4124 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4125 | * ignoring for now. */
|
---|
4126 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4127 | {
|
---|
4128 | /* register target */
|
---|
4129 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4130 | IEM_MC_BEGIN(0, 0);
|
---|
4131 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
4132 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4133 | } IEM_MC_ELSE() {
|
---|
4134 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4135 | } IEM_MC_ENDIF();
|
---|
4136 | IEM_MC_ADVANCE_RIP();
|
---|
4137 | IEM_MC_END();
|
---|
4138 | }
|
---|
4139 | else
|
---|
4140 | {
|
---|
4141 | /* memory target */
|
---|
4142 | IEM_MC_BEGIN(0, 1);
|
---|
4143 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4144 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4145 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4146 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
4147 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4148 | } IEM_MC_ELSE() {
|
---|
4149 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4150 | } IEM_MC_ENDIF();
|
---|
4151 | IEM_MC_ADVANCE_RIP();
|
---|
4152 | IEM_MC_END();
|
---|
4153 | }
|
---|
4154 | return VINF_SUCCESS;
|
---|
4155 | }
|
---|
4156 |
|
---|
4157 |
|
---|
4158 | /** Opcode 0x0f 0x92. */
|
---|
4159 | FNIEMOP_DEF(iemOp_setc_Eb)
|
---|
4160 | {
|
---|
4161 | IEMOP_MNEMONIC("setc Eb");
|
---|
4162 | IEMOP_HLP_MIN_386();
|
---|
4163 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4164 |
|
---|
4165 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4166 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4167 | * ignoring for now. */
|
---|
4168 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4169 | {
|
---|
4170 | /* register target */
|
---|
4171 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4172 | IEM_MC_BEGIN(0, 0);
|
---|
4173 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
4174 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4175 | } IEM_MC_ELSE() {
|
---|
4176 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4177 | } IEM_MC_ENDIF();
|
---|
4178 | IEM_MC_ADVANCE_RIP();
|
---|
4179 | IEM_MC_END();
|
---|
4180 | }
|
---|
4181 | else
|
---|
4182 | {
|
---|
4183 | /* memory target */
|
---|
4184 | IEM_MC_BEGIN(0, 1);
|
---|
4185 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4186 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4187 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4188 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
4189 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4190 | } IEM_MC_ELSE() {
|
---|
4191 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4192 | } IEM_MC_ENDIF();
|
---|
4193 | IEM_MC_ADVANCE_RIP();
|
---|
4194 | IEM_MC_END();
|
---|
4195 | }
|
---|
4196 | return VINF_SUCCESS;
|
---|
4197 | }
|
---|
4198 |
|
---|
4199 |
|
---|
4200 | /** Opcode 0x0f 0x93. */
|
---|
4201 | FNIEMOP_DEF(iemOp_setnc_Eb)
|
---|
4202 | {
|
---|
4203 | IEMOP_MNEMONIC("setnc Eb");
|
---|
4204 | IEMOP_HLP_MIN_386();
|
---|
4205 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4206 |
|
---|
4207 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4208 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4209 | * ignoring for now. */
|
---|
4210 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4211 | {
|
---|
4212 | /* register target */
|
---|
4213 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4214 | IEM_MC_BEGIN(0, 0);
|
---|
4215 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
4216 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4217 | } IEM_MC_ELSE() {
|
---|
4218 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4219 | } IEM_MC_ENDIF();
|
---|
4220 | IEM_MC_ADVANCE_RIP();
|
---|
4221 | IEM_MC_END();
|
---|
4222 | }
|
---|
4223 | else
|
---|
4224 | {
|
---|
4225 | /* memory target */
|
---|
4226 | IEM_MC_BEGIN(0, 1);
|
---|
4227 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4228 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4229 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4230 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
4231 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4232 | } IEM_MC_ELSE() {
|
---|
4233 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4234 | } IEM_MC_ENDIF();
|
---|
4235 | IEM_MC_ADVANCE_RIP();
|
---|
4236 | IEM_MC_END();
|
---|
4237 | }
|
---|
4238 | return VINF_SUCCESS;
|
---|
4239 | }
|
---|
4240 |
|
---|
4241 |
|
---|
4242 | /** Opcode 0x0f 0x94. */
|
---|
4243 | FNIEMOP_DEF(iemOp_sete_Eb)
|
---|
4244 | {
|
---|
4245 | IEMOP_MNEMONIC("sete Eb");
|
---|
4246 | IEMOP_HLP_MIN_386();
|
---|
4247 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4248 |
|
---|
4249 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4250 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4251 | * ignoring for now. */
|
---|
4252 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4253 | {
|
---|
4254 | /* register target */
|
---|
4255 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4256 | IEM_MC_BEGIN(0, 0);
|
---|
4257 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
4258 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4259 | } IEM_MC_ELSE() {
|
---|
4260 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4261 | } IEM_MC_ENDIF();
|
---|
4262 | IEM_MC_ADVANCE_RIP();
|
---|
4263 | IEM_MC_END();
|
---|
4264 | }
|
---|
4265 | else
|
---|
4266 | {
|
---|
4267 | /* memory target */
|
---|
4268 | IEM_MC_BEGIN(0, 1);
|
---|
4269 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4270 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4271 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4272 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
4273 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4274 | } IEM_MC_ELSE() {
|
---|
4275 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4276 | } IEM_MC_ENDIF();
|
---|
4277 | IEM_MC_ADVANCE_RIP();
|
---|
4278 | IEM_MC_END();
|
---|
4279 | }
|
---|
4280 | return VINF_SUCCESS;
|
---|
4281 | }
|
---|
4282 |
|
---|
4283 |
|
---|
4284 | /** Opcode 0x0f 0x95. */
|
---|
4285 | FNIEMOP_DEF(iemOp_setne_Eb)
|
---|
4286 | {
|
---|
4287 | IEMOP_MNEMONIC("setne Eb");
|
---|
4288 | IEMOP_HLP_MIN_386();
|
---|
4289 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4290 |
|
---|
4291 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4292 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4293 | * ignoring for now. */
|
---|
4294 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4295 | {
|
---|
4296 | /* register target */
|
---|
4297 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4298 | IEM_MC_BEGIN(0, 0);
|
---|
4299 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
4300 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4301 | } IEM_MC_ELSE() {
|
---|
4302 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4303 | } IEM_MC_ENDIF();
|
---|
4304 | IEM_MC_ADVANCE_RIP();
|
---|
4305 | IEM_MC_END();
|
---|
4306 | }
|
---|
4307 | else
|
---|
4308 | {
|
---|
4309 | /* memory target */
|
---|
4310 | IEM_MC_BEGIN(0, 1);
|
---|
4311 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4312 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4313 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4314 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
4315 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4316 | } IEM_MC_ELSE() {
|
---|
4317 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4318 | } IEM_MC_ENDIF();
|
---|
4319 | IEM_MC_ADVANCE_RIP();
|
---|
4320 | IEM_MC_END();
|
---|
4321 | }
|
---|
4322 | return VINF_SUCCESS;
|
---|
4323 | }
|
---|
4324 |
|
---|
4325 |
|
---|
4326 | /** Opcode 0x0f 0x96. */
|
---|
4327 | FNIEMOP_DEF(iemOp_setbe_Eb)
|
---|
4328 | {
|
---|
4329 | IEMOP_MNEMONIC("setbe Eb");
|
---|
4330 | IEMOP_HLP_MIN_386();
|
---|
4331 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4332 |
|
---|
4333 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4334 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4335 | * ignoring for now. */
|
---|
4336 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4337 | {
|
---|
4338 | /* register target */
|
---|
4339 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4340 | IEM_MC_BEGIN(0, 0);
|
---|
4341 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
4342 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4343 | } IEM_MC_ELSE() {
|
---|
4344 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4345 | } IEM_MC_ENDIF();
|
---|
4346 | IEM_MC_ADVANCE_RIP();
|
---|
4347 | IEM_MC_END();
|
---|
4348 | }
|
---|
4349 | else
|
---|
4350 | {
|
---|
4351 | /* memory target */
|
---|
4352 | IEM_MC_BEGIN(0, 1);
|
---|
4353 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4354 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4355 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4356 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
4357 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4358 | } IEM_MC_ELSE() {
|
---|
4359 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4360 | } IEM_MC_ENDIF();
|
---|
4361 | IEM_MC_ADVANCE_RIP();
|
---|
4362 | IEM_MC_END();
|
---|
4363 | }
|
---|
4364 | return VINF_SUCCESS;
|
---|
4365 | }
|
---|
4366 |
|
---|
4367 |
|
---|
4368 | /** Opcode 0x0f 0x97. */
|
---|
4369 | FNIEMOP_DEF(iemOp_setnbe_Eb)
|
---|
4370 | {
|
---|
4371 | IEMOP_MNEMONIC("setnbe Eb");
|
---|
4372 | IEMOP_HLP_MIN_386();
|
---|
4373 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4374 |
|
---|
4375 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4376 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4377 | * ignoring for now. */
|
---|
4378 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4379 | {
|
---|
4380 | /* register target */
|
---|
4381 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4382 | IEM_MC_BEGIN(0, 0);
|
---|
4383 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
4384 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4385 | } IEM_MC_ELSE() {
|
---|
4386 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4387 | } IEM_MC_ENDIF();
|
---|
4388 | IEM_MC_ADVANCE_RIP();
|
---|
4389 | IEM_MC_END();
|
---|
4390 | }
|
---|
4391 | else
|
---|
4392 | {
|
---|
4393 | /* memory target */
|
---|
4394 | IEM_MC_BEGIN(0, 1);
|
---|
4395 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4396 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4397 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4398 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
4399 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4400 | } IEM_MC_ELSE() {
|
---|
4401 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4402 | } IEM_MC_ENDIF();
|
---|
4403 | IEM_MC_ADVANCE_RIP();
|
---|
4404 | IEM_MC_END();
|
---|
4405 | }
|
---|
4406 | return VINF_SUCCESS;
|
---|
4407 | }
|
---|
4408 |
|
---|
4409 |
|
---|
4410 | /** Opcode 0x0f 0x98. */
|
---|
4411 | FNIEMOP_DEF(iemOp_sets_Eb)
|
---|
4412 | {
|
---|
4413 | IEMOP_MNEMONIC("sets Eb");
|
---|
4414 | IEMOP_HLP_MIN_386();
|
---|
4415 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4416 |
|
---|
4417 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4418 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4419 | * ignoring for now. */
|
---|
4420 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4421 | {
|
---|
4422 | /* register target */
|
---|
4423 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4424 | IEM_MC_BEGIN(0, 0);
|
---|
4425 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
4426 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4427 | } IEM_MC_ELSE() {
|
---|
4428 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4429 | } IEM_MC_ENDIF();
|
---|
4430 | IEM_MC_ADVANCE_RIP();
|
---|
4431 | IEM_MC_END();
|
---|
4432 | }
|
---|
4433 | else
|
---|
4434 | {
|
---|
4435 | /* memory target */
|
---|
4436 | IEM_MC_BEGIN(0, 1);
|
---|
4437 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4438 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4439 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4440 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
4441 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4442 | } IEM_MC_ELSE() {
|
---|
4443 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4444 | } IEM_MC_ENDIF();
|
---|
4445 | IEM_MC_ADVANCE_RIP();
|
---|
4446 | IEM_MC_END();
|
---|
4447 | }
|
---|
4448 | return VINF_SUCCESS;
|
---|
4449 | }
|
---|
4450 |
|
---|
4451 |
|
---|
4452 | /** Opcode 0x0f 0x99. */
|
---|
4453 | FNIEMOP_DEF(iemOp_setns_Eb)
|
---|
4454 | {
|
---|
4455 | IEMOP_MNEMONIC("setns Eb");
|
---|
4456 | IEMOP_HLP_MIN_386();
|
---|
4457 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4458 |
|
---|
4459 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4460 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4461 | * ignoring for now. */
|
---|
4462 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4463 | {
|
---|
4464 | /* register target */
|
---|
4465 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4466 | IEM_MC_BEGIN(0, 0);
|
---|
4467 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
4468 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4469 | } IEM_MC_ELSE() {
|
---|
4470 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4471 | } IEM_MC_ENDIF();
|
---|
4472 | IEM_MC_ADVANCE_RIP();
|
---|
4473 | IEM_MC_END();
|
---|
4474 | }
|
---|
4475 | else
|
---|
4476 | {
|
---|
4477 | /* memory target */
|
---|
4478 | IEM_MC_BEGIN(0, 1);
|
---|
4479 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4480 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4481 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4482 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
4483 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4484 | } IEM_MC_ELSE() {
|
---|
4485 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4486 | } IEM_MC_ENDIF();
|
---|
4487 | IEM_MC_ADVANCE_RIP();
|
---|
4488 | IEM_MC_END();
|
---|
4489 | }
|
---|
4490 | return VINF_SUCCESS;
|
---|
4491 | }
|
---|
4492 |
|
---|
4493 |
|
---|
4494 | /** Opcode 0x0f 0x9a. */
|
---|
4495 | FNIEMOP_DEF(iemOp_setp_Eb)
|
---|
4496 | {
|
---|
4497 | IEMOP_MNEMONIC("setnp Eb");
|
---|
4498 | IEMOP_HLP_MIN_386();
|
---|
4499 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4500 |
|
---|
4501 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4502 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4503 | * ignoring for now. */
|
---|
4504 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4505 | {
|
---|
4506 | /* register target */
|
---|
4507 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4508 | IEM_MC_BEGIN(0, 0);
|
---|
4509 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
4510 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4511 | } IEM_MC_ELSE() {
|
---|
4512 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4513 | } IEM_MC_ENDIF();
|
---|
4514 | IEM_MC_ADVANCE_RIP();
|
---|
4515 | IEM_MC_END();
|
---|
4516 | }
|
---|
4517 | else
|
---|
4518 | {
|
---|
4519 | /* memory target */
|
---|
4520 | IEM_MC_BEGIN(0, 1);
|
---|
4521 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4522 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4523 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4524 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
4525 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4526 | } IEM_MC_ELSE() {
|
---|
4527 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4528 | } IEM_MC_ENDIF();
|
---|
4529 | IEM_MC_ADVANCE_RIP();
|
---|
4530 | IEM_MC_END();
|
---|
4531 | }
|
---|
4532 | return VINF_SUCCESS;
|
---|
4533 | }
|
---|
4534 |
|
---|
4535 |
|
---|
4536 | /** Opcode 0x0f 0x9b. */
|
---|
4537 | FNIEMOP_DEF(iemOp_setnp_Eb)
|
---|
4538 | {
|
---|
4539 | IEMOP_MNEMONIC("setnp Eb");
|
---|
4540 | IEMOP_HLP_MIN_386();
|
---|
4541 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4542 |
|
---|
4543 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4544 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4545 | * ignoring for now. */
|
---|
4546 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4547 | {
|
---|
4548 | /* register target */
|
---|
4549 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4550 | IEM_MC_BEGIN(0, 0);
|
---|
4551 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
4552 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4553 | } IEM_MC_ELSE() {
|
---|
4554 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4555 | } IEM_MC_ENDIF();
|
---|
4556 | IEM_MC_ADVANCE_RIP();
|
---|
4557 | IEM_MC_END();
|
---|
4558 | }
|
---|
4559 | else
|
---|
4560 | {
|
---|
4561 | /* memory target */
|
---|
4562 | IEM_MC_BEGIN(0, 1);
|
---|
4563 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4564 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4565 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4566 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
4567 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4568 | } IEM_MC_ELSE() {
|
---|
4569 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4570 | } IEM_MC_ENDIF();
|
---|
4571 | IEM_MC_ADVANCE_RIP();
|
---|
4572 | IEM_MC_END();
|
---|
4573 | }
|
---|
4574 | return VINF_SUCCESS;
|
---|
4575 | }
|
---|
4576 |
|
---|
4577 |
|
---|
4578 | /** Opcode 0x0f 0x9c. */
|
---|
4579 | FNIEMOP_DEF(iemOp_setl_Eb)
|
---|
4580 | {
|
---|
4581 | IEMOP_MNEMONIC("setl Eb");
|
---|
4582 | IEMOP_HLP_MIN_386();
|
---|
4583 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4584 |
|
---|
4585 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4586 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4587 | * ignoring for now. */
|
---|
4588 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4589 | {
|
---|
4590 | /* register target */
|
---|
4591 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4592 | IEM_MC_BEGIN(0, 0);
|
---|
4593 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
4594 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4595 | } IEM_MC_ELSE() {
|
---|
4596 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4597 | } IEM_MC_ENDIF();
|
---|
4598 | IEM_MC_ADVANCE_RIP();
|
---|
4599 | IEM_MC_END();
|
---|
4600 | }
|
---|
4601 | else
|
---|
4602 | {
|
---|
4603 | /* memory target */
|
---|
4604 | IEM_MC_BEGIN(0, 1);
|
---|
4605 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4606 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4607 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4608 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
4609 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4610 | } IEM_MC_ELSE() {
|
---|
4611 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4612 | } IEM_MC_ENDIF();
|
---|
4613 | IEM_MC_ADVANCE_RIP();
|
---|
4614 | IEM_MC_END();
|
---|
4615 | }
|
---|
4616 | return VINF_SUCCESS;
|
---|
4617 | }
|
---|
4618 |
|
---|
4619 |
|
---|
4620 | /** Opcode 0x0f 0x9d. */
|
---|
4621 | FNIEMOP_DEF(iemOp_setnl_Eb)
|
---|
4622 | {
|
---|
4623 | IEMOP_MNEMONIC("setnl Eb");
|
---|
4624 | IEMOP_HLP_MIN_386();
|
---|
4625 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4626 |
|
---|
4627 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4628 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4629 | * ignoring for now. */
|
---|
4630 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4631 | {
|
---|
4632 | /* register target */
|
---|
4633 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4634 | IEM_MC_BEGIN(0, 0);
|
---|
4635 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
4636 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4637 | } IEM_MC_ELSE() {
|
---|
4638 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4639 | } IEM_MC_ENDIF();
|
---|
4640 | IEM_MC_ADVANCE_RIP();
|
---|
4641 | IEM_MC_END();
|
---|
4642 | }
|
---|
4643 | else
|
---|
4644 | {
|
---|
4645 | /* memory target */
|
---|
4646 | IEM_MC_BEGIN(0, 1);
|
---|
4647 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4648 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4649 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4650 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
4651 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4652 | } IEM_MC_ELSE() {
|
---|
4653 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4654 | } IEM_MC_ENDIF();
|
---|
4655 | IEM_MC_ADVANCE_RIP();
|
---|
4656 | IEM_MC_END();
|
---|
4657 | }
|
---|
4658 | return VINF_SUCCESS;
|
---|
4659 | }
|
---|
4660 |
|
---|
4661 |
|
---|
4662 | /** Opcode 0x0f 0x9e. */
|
---|
4663 | FNIEMOP_DEF(iemOp_setle_Eb)
|
---|
4664 | {
|
---|
4665 | IEMOP_MNEMONIC("setle Eb");
|
---|
4666 | IEMOP_HLP_MIN_386();
|
---|
4667 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4668 |
|
---|
4669 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4670 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4671 | * ignoring for now. */
|
---|
4672 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4673 | {
|
---|
4674 | /* register target */
|
---|
4675 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4676 | IEM_MC_BEGIN(0, 0);
|
---|
4677 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
4678 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4679 | } IEM_MC_ELSE() {
|
---|
4680 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4681 | } IEM_MC_ENDIF();
|
---|
4682 | IEM_MC_ADVANCE_RIP();
|
---|
4683 | IEM_MC_END();
|
---|
4684 | }
|
---|
4685 | else
|
---|
4686 | {
|
---|
4687 | /* memory target */
|
---|
4688 | IEM_MC_BEGIN(0, 1);
|
---|
4689 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4690 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4691 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4692 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
4693 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4694 | } IEM_MC_ELSE() {
|
---|
4695 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4696 | } IEM_MC_ENDIF();
|
---|
4697 | IEM_MC_ADVANCE_RIP();
|
---|
4698 | IEM_MC_END();
|
---|
4699 | }
|
---|
4700 | return VINF_SUCCESS;
|
---|
4701 | }
|
---|
4702 |
|
---|
4703 |
|
---|
4704 | /** Opcode 0x0f 0x9f. */
|
---|
4705 | FNIEMOP_DEF(iemOp_setnle_Eb)
|
---|
4706 | {
|
---|
4707 | IEMOP_MNEMONIC("setnle Eb");
|
---|
4708 | IEMOP_HLP_MIN_386();
|
---|
4709 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4710 |
|
---|
4711 | /** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
|
---|
4712 | * any way. AMD says it's "unused", whatever that means. We're
|
---|
4713 | * ignoring for now. */
|
---|
4714 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4715 | {
|
---|
4716 | /* register target */
|
---|
4717 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4718 | IEM_MC_BEGIN(0, 0);
|
---|
4719 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
4720 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 0);
|
---|
4721 | } IEM_MC_ELSE() {
|
---|
4722 | IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 1);
|
---|
4723 | } IEM_MC_ENDIF();
|
---|
4724 | IEM_MC_ADVANCE_RIP();
|
---|
4725 | IEM_MC_END();
|
---|
4726 | }
|
---|
4727 | else
|
---|
4728 | {
|
---|
4729 | /* memory target */
|
---|
4730 | IEM_MC_BEGIN(0, 1);
|
---|
4731 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4732 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4733 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4734 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
4735 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4736 | } IEM_MC_ELSE() {
|
---|
4737 | IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
|
---|
4738 | } IEM_MC_ENDIF();
|
---|
4739 | IEM_MC_ADVANCE_RIP();
|
---|
4740 | IEM_MC_END();
|
---|
4741 | }
|
---|
4742 | return VINF_SUCCESS;
|
---|
4743 | }
|
---|
4744 |
|
---|
4745 |
|
---|
4746 | /**
|
---|
4747 | * Common 'push segment-register' helper.
|
---|
4748 | */
|
---|
4749 | FNIEMOP_DEF_1(iemOpCommonPushSReg, uint8_t, iReg)
|
---|
4750 | {
|
---|
4751 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4752 | if (iReg < X86_SREG_FS)
|
---|
4753 | IEMOP_HLP_NO_64BIT();
|
---|
4754 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
4755 |
|
---|
4756 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
4757 | {
|
---|
4758 | case IEMMODE_16BIT:
|
---|
4759 | IEM_MC_BEGIN(0, 1);
|
---|
4760 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
4761 | IEM_MC_FETCH_SREG_U16(u16Value, iReg);
|
---|
4762 | IEM_MC_PUSH_U16(u16Value);
|
---|
4763 | IEM_MC_ADVANCE_RIP();
|
---|
4764 | IEM_MC_END();
|
---|
4765 | break;
|
---|
4766 |
|
---|
4767 | case IEMMODE_32BIT:
|
---|
4768 | IEM_MC_BEGIN(0, 1);
|
---|
4769 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
4770 | IEM_MC_FETCH_SREG_ZX_U32(u32Value, iReg);
|
---|
4771 | IEM_MC_PUSH_U32_SREG(u32Value);
|
---|
4772 | IEM_MC_ADVANCE_RIP();
|
---|
4773 | IEM_MC_END();
|
---|
4774 | break;
|
---|
4775 |
|
---|
4776 | case IEMMODE_64BIT:
|
---|
4777 | IEM_MC_BEGIN(0, 1);
|
---|
4778 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
4779 | IEM_MC_FETCH_SREG_ZX_U64(u64Value, iReg);
|
---|
4780 | IEM_MC_PUSH_U64(u64Value);
|
---|
4781 | IEM_MC_ADVANCE_RIP();
|
---|
4782 | IEM_MC_END();
|
---|
4783 | break;
|
---|
4784 | }
|
---|
4785 |
|
---|
4786 | return VINF_SUCCESS;
|
---|
4787 | }
|
---|
4788 |
|
---|
4789 |
|
---|
4790 | /** Opcode 0x0f 0xa0. */
|
---|
4791 | FNIEMOP_DEF(iemOp_push_fs)
|
---|
4792 | {
|
---|
4793 | IEMOP_MNEMONIC("push fs");
|
---|
4794 | IEMOP_HLP_MIN_386();
|
---|
4795 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4796 | return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_FS);
|
---|
4797 | }
|
---|
4798 |
|
---|
4799 |
|
---|
4800 | /** Opcode 0x0f 0xa1. */
|
---|
4801 | FNIEMOP_DEF(iemOp_pop_fs)
|
---|
4802 | {
|
---|
4803 | IEMOP_MNEMONIC("pop fs");
|
---|
4804 | IEMOP_HLP_MIN_386();
|
---|
4805 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4806 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_FS, pVCpu->iem.s.enmEffOpSize);
|
---|
4807 | }
|
---|
4808 |
|
---|
4809 |
|
---|
4810 | /** Opcode 0x0f 0xa2. */
|
---|
4811 | FNIEMOP_DEF(iemOp_cpuid)
|
---|
4812 | {
|
---|
4813 | IEMOP_MNEMONIC("cpuid");
|
---|
4814 | IEMOP_HLP_MIN_486(); /* not all 486es. */
|
---|
4815 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4816 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_cpuid);
|
---|
4817 | }
|
---|
4818 |
|
---|
4819 |
|
---|
4820 | /**
|
---|
4821 | * Common worker for iemOp_bt_Ev_Gv, iemOp_btc_Ev_Gv, iemOp_btr_Ev_Gv and
|
---|
4822 | * iemOp_bts_Ev_Gv.
|
---|
4823 | */
|
---|
4824 | FNIEMOP_DEF_1(iemOpCommonBit_Ev_Gv, PCIEMOPBINSIZES, pImpl)
|
---|
4825 | {
|
---|
4826 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
4827 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
4828 |
|
---|
4829 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
4830 | {
|
---|
4831 | /* register destination. */
|
---|
4832 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4833 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
4834 | {
|
---|
4835 | case IEMMODE_16BIT:
|
---|
4836 | IEM_MC_BEGIN(3, 0);
|
---|
4837 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
4838 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
4839 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
4840 |
|
---|
4841 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
4842 | IEM_MC_AND_LOCAL_U16(u16Src, 0xf);
|
---|
4843 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
4844 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
4845 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
4846 |
|
---|
4847 | IEM_MC_ADVANCE_RIP();
|
---|
4848 | IEM_MC_END();
|
---|
4849 | return VINF_SUCCESS;
|
---|
4850 |
|
---|
4851 | case IEMMODE_32BIT:
|
---|
4852 | IEM_MC_BEGIN(3, 0);
|
---|
4853 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
4854 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
4855 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
4856 |
|
---|
4857 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
4858 | IEM_MC_AND_LOCAL_U32(u32Src, 0x1f);
|
---|
4859 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
4860 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
4861 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
4862 |
|
---|
4863 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
4864 | IEM_MC_ADVANCE_RIP();
|
---|
4865 | IEM_MC_END();
|
---|
4866 | return VINF_SUCCESS;
|
---|
4867 |
|
---|
4868 | case IEMMODE_64BIT:
|
---|
4869 | IEM_MC_BEGIN(3, 0);
|
---|
4870 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
4871 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
4872 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
4873 |
|
---|
4874 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
4875 | IEM_MC_AND_LOCAL_U64(u64Src, 0x3f);
|
---|
4876 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
4877 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
4878 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
4879 |
|
---|
4880 | IEM_MC_ADVANCE_RIP();
|
---|
4881 | IEM_MC_END();
|
---|
4882 | return VINF_SUCCESS;
|
---|
4883 |
|
---|
4884 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
4885 | }
|
---|
4886 | }
|
---|
4887 | else
|
---|
4888 | {
|
---|
4889 | /* memory destination. */
|
---|
4890 |
|
---|
4891 | uint32_t fAccess;
|
---|
4892 | if (pImpl->pfnLockedU16)
|
---|
4893 | fAccess = IEM_ACCESS_DATA_RW;
|
---|
4894 | else /* BT */
|
---|
4895 | fAccess = IEM_ACCESS_DATA_R;
|
---|
4896 |
|
---|
4897 | NOREF(fAccess);
|
---|
4898 |
|
---|
4899 | /** @todo test negative bit offsets! */
|
---|
4900 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
4901 | {
|
---|
4902 | case IEMMODE_16BIT:
|
---|
4903 | IEM_MC_BEGIN(3, 2);
|
---|
4904 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
4905 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
4906 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
4907 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4908 | IEM_MC_LOCAL(int16_t, i16AddrAdj);
|
---|
4909 |
|
---|
4910 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4911 | if (pImpl->pfnLockedU16)
|
---|
4912 | IEMOP_HLP_DONE_DECODING();
|
---|
4913 | else
|
---|
4914 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4915 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
4916 | IEM_MC_ASSIGN(i16AddrAdj, u16Src);
|
---|
4917 | IEM_MC_AND_ARG_U16(u16Src, 0x0f);
|
---|
4918 | IEM_MC_SAR_LOCAL_S16(i16AddrAdj, 4);
|
---|
4919 | IEM_MC_SAR_LOCAL_S16(i16AddrAdj, 1);
|
---|
4920 | IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(GCPtrEffDst, i16AddrAdj);
|
---|
4921 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
4922 |
|
---|
4923 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4924 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
4925 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
4926 | else
|
---|
4927 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
|
---|
4928 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
4929 |
|
---|
4930 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
4931 | IEM_MC_ADVANCE_RIP();
|
---|
4932 | IEM_MC_END();
|
---|
4933 | return VINF_SUCCESS;
|
---|
4934 |
|
---|
4935 | case IEMMODE_32BIT:
|
---|
4936 | IEM_MC_BEGIN(3, 2);
|
---|
4937 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
4938 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
4939 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
4940 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4941 | IEM_MC_LOCAL(int32_t, i32AddrAdj);
|
---|
4942 |
|
---|
4943 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4944 | if (pImpl->pfnLockedU16)
|
---|
4945 | IEMOP_HLP_DONE_DECODING();
|
---|
4946 | else
|
---|
4947 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4948 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
4949 | IEM_MC_ASSIGN(i32AddrAdj, u32Src);
|
---|
4950 | IEM_MC_AND_ARG_U32(u32Src, 0x1f);
|
---|
4951 | IEM_MC_SAR_LOCAL_S32(i32AddrAdj, 5);
|
---|
4952 | IEM_MC_SHL_LOCAL_S32(i32AddrAdj, 2);
|
---|
4953 | IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(GCPtrEffDst, i32AddrAdj);
|
---|
4954 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
4955 |
|
---|
4956 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4957 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
4958 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
4959 | else
|
---|
4960 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
|
---|
4961 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
4962 |
|
---|
4963 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
4964 | IEM_MC_ADVANCE_RIP();
|
---|
4965 | IEM_MC_END();
|
---|
4966 | return VINF_SUCCESS;
|
---|
4967 |
|
---|
4968 | case IEMMODE_64BIT:
|
---|
4969 | IEM_MC_BEGIN(3, 2);
|
---|
4970 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
4971 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
4972 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
4973 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
4974 | IEM_MC_LOCAL(int64_t, i64AddrAdj);
|
---|
4975 |
|
---|
4976 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
4977 | if (pImpl->pfnLockedU16)
|
---|
4978 | IEMOP_HLP_DONE_DECODING();
|
---|
4979 | else
|
---|
4980 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
4981 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
4982 | IEM_MC_ASSIGN(i64AddrAdj, u64Src);
|
---|
4983 | IEM_MC_AND_ARG_U64(u64Src, 0x3f);
|
---|
4984 | IEM_MC_SAR_LOCAL_S64(i64AddrAdj, 6);
|
---|
4985 | IEM_MC_SHL_LOCAL_S64(i64AddrAdj, 3);
|
---|
4986 | IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(GCPtrEffDst, i64AddrAdj);
|
---|
4987 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
4988 |
|
---|
4989 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
4990 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
4991 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
4992 | else
|
---|
4993 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
|
---|
4994 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
4995 |
|
---|
4996 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
4997 | IEM_MC_ADVANCE_RIP();
|
---|
4998 | IEM_MC_END();
|
---|
4999 | return VINF_SUCCESS;
|
---|
5000 |
|
---|
5001 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5002 | }
|
---|
5003 | }
|
---|
5004 | }
|
---|
5005 |
|
---|
5006 |
|
---|
5007 | /** Opcode 0x0f 0xa3. */
|
---|
5008 | FNIEMOP_DEF(iemOp_bt_Ev_Gv)
|
---|
5009 | {
|
---|
5010 | IEMOP_MNEMONIC("bt Gv,Gv");
|
---|
5011 | IEMOP_HLP_MIN_386();
|
---|
5012 | return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_bt);
|
---|
5013 | }
|
---|
5014 |
|
---|
5015 |
|
---|
5016 | /**
|
---|
5017 | * Common worker for iemOp_shrd_Ev_Gv_Ib and iemOp_shld_Ev_Gv_Ib.
|
---|
5018 | */
|
---|
5019 | FNIEMOP_DEF_1(iemOpCommonShldShrd_Ib, PCIEMOPSHIFTDBLSIZES, pImpl)
|
---|
5020 | {
|
---|
5021 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5022 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_OF);
|
---|
5023 |
|
---|
5024 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
5025 | {
|
---|
5026 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
5027 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5028 |
|
---|
5029 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5030 | {
|
---|
5031 | case IEMMODE_16BIT:
|
---|
5032 | IEM_MC_BEGIN(4, 0);
|
---|
5033 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
5034 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
5035 | IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2);
|
---|
5036 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5037 |
|
---|
5038 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5039 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5040 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5041 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
|
---|
5042 |
|
---|
5043 | IEM_MC_ADVANCE_RIP();
|
---|
5044 | IEM_MC_END();
|
---|
5045 | return VINF_SUCCESS;
|
---|
5046 |
|
---|
5047 | case IEMMODE_32BIT:
|
---|
5048 | IEM_MC_BEGIN(4, 0);
|
---|
5049 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
5050 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
5051 | IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2);
|
---|
5052 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5053 |
|
---|
5054 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5055 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5056 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5057 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
|
---|
5058 |
|
---|
5059 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
5060 | IEM_MC_ADVANCE_RIP();
|
---|
5061 | IEM_MC_END();
|
---|
5062 | return VINF_SUCCESS;
|
---|
5063 |
|
---|
5064 | case IEMMODE_64BIT:
|
---|
5065 | IEM_MC_BEGIN(4, 0);
|
---|
5066 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
5067 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
5068 | IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2);
|
---|
5069 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5070 |
|
---|
5071 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5072 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5073 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5074 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
|
---|
5075 |
|
---|
5076 | IEM_MC_ADVANCE_RIP();
|
---|
5077 | IEM_MC_END();
|
---|
5078 | return VINF_SUCCESS;
|
---|
5079 |
|
---|
5080 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5081 | }
|
---|
5082 | }
|
---|
5083 | else
|
---|
5084 | {
|
---|
5085 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5086 | {
|
---|
5087 | case IEMMODE_16BIT:
|
---|
5088 | IEM_MC_BEGIN(4, 2);
|
---|
5089 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
5090 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
5091 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5092 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5093 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5094 |
|
---|
5095 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
5096 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
5097 | IEM_MC_ASSIGN(cShiftArg, cShift);
|
---|
5098 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5099 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5100 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5101 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5102 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
|
---|
5103 |
|
---|
5104 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
5105 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5106 | IEM_MC_ADVANCE_RIP();
|
---|
5107 | IEM_MC_END();
|
---|
5108 | return VINF_SUCCESS;
|
---|
5109 |
|
---|
5110 | case IEMMODE_32BIT:
|
---|
5111 | IEM_MC_BEGIN(4, 2);
|
---|
5112 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
5113 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
5114 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5115 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5116 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5117 |
|
---|
5118 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
5119 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
5120 | IEM_MC_ASSIGN(cShiftArg, cShift);
|
---|
5121 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5122 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5123 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5124 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5125 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
|
---|
5126 |
|
---|
5127 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
5128 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5129 | IEM_MC_ADVANCE_RIP();
|
---|
5130 | IEM_MC_END();
|
---|
5131 | return VINF_SUCCESS;
|
---|
5132 |
|
---|
5133 | case IEMMODE_64BIT:
|
---|
5134 | IEM_MC_BEGIN(4, 2);
|
---|
5135 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
5136 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
5137 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5138 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5139 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5140 |
|
---|
5141 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
5142 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
5143 | IEM_MC_ASSIGN(cShiftArg, cShift);
|
---|
5144 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5145 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5146 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5147 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5148 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
|
---|
5149 |
|
---|
5150 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
5151 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5152 | IEM_MC_ADVANCE_RIP();
|
---|
5153 | IEM_MC_END();
|
---|
5154 | return VINF_SUCCESS;
|
---|
5155 |
|
---|
5156 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5157 | }
|
---|
5158 | }
|
---|
5159 | }
|
---|
5160 |
|
---|
5161 |
|
---|
5162 | /**
|
---|
5163 | * Common worker for iemOp_shrd_Ev_Gv_CL and iemOp_shld_Ev_Gv_CL.
|
---|
5164 | */
|
---|
5165 | FNIEMOP_DEF_1(iemOpCommonShldShrd_CL, PCIEMOPSHIFTDBLSIZES, pImpl)
|
---|
5166 | {
|
---|
5167 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5168 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_OF);
|
---|
5169 |
|
---|
5170 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
5171 | {
|
---|
5172 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5173 |
|
---|
5174 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5175 | {
|
---|
5176 | case IEMMODE_16BIT:
|
---|
5177 | IEM_MC_BEGIN(4, 0);
|
---|
5178 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
5179 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
5180 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5181 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5182 |
|
---|
5183 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5184 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5185 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
5186 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5187 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
|
---|
5188 |
|
---|
5189 | IEM_MC_ADVANCE_RIP();
|
---|
5190 | IEM_MC_END();
|
---|
5191 | return VINF_SUCCESS;
|
---|
5192 |
|
---|
5193 | case IEMMODE_32BIT:
|
---|
5194 | IEM_MC_BEGIN(4, 0);
|
---|
5195 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
5196 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
5197 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5198 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5199 |
|
---|
5200 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5201 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5202 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
5203 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5204 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
|
---|
5205 |
|
---|
5206 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
5207 | IEM_MC_ADVANCE_RIP();
|
---|
5208 | IEM_MC_END();
|
---|
5209 | return VINF_SUCCESS;
|
---|
5210 |
|
---|
5211 | case IEMMODE_64BIT:
|
---|
5212 | IEM_MC_BEGIN(4, 0);
|
---|
5213 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
5214 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
5215 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5216 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5217 |
|
---|
5218 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5219 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5220 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
5221 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5222 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
|
---|
5223 |
|
---|
5224 | IEM_MC_ADVANCE_RIP();
|
---|
5225 | IEM_MC_END();
|
---|
5226 | return VINF_SUCCESS;
|
---|
5227 |
|
---|
5228 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5229 | }
|
---|
5230 | }
|
---|
5231 | else
|
---|
5232 | {
|
---|
5233 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5234 | {
|
---|
5235 | case IEMMODE_16BIT:
|
---|
5236 | IEM_MC_BEGIN(4, 2);
|
---|
5237 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
5238 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
5239 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5240 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5241 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5242 |
|
---|
5243 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
5244 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5245 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5246 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
5247 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5248 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5249 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
|
---|
5250 |
|
---|
5251 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
5252 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5253 | IEM_MC_ADVANCE_RIP();
|
---|
5254 | IEM_MC_END();
|
---|
5255 | return VINF_SUCCESS;
|
---|
5256 |
|
---|
5257 | case IEMMODE_32BIT:
|
---|
5258 | IEM_MC_BEGIN(4, 2);
|
---|
5259 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
5260 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
5261 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5262 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5263 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5264 |
|
---|
5265 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
5266 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5267 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5268 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
5269 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5270 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5271 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
|
---|
5272 |
|
---|
5273 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
5274 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5275 | IEM_MC_ADVANCE_RIP();
|
---|
5276 | IEM_MC_END();
|
---|
5277 | return VINF_SUCCESS;
|
---|
5278 |
|
---|
5279 | case IEMMODE_64BIT:
|
---|
5280 | IEM_MC_BEGIN(4, 2);
|
---|
5281 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
5282 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
5283 | IEM_MC_ARG(uint8_t, cShiftArg, 2);
|
---|
5284 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5285 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5286 |
|
---|
5287 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
5288 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5289 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5290 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
5291 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5292 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5293 | IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
|
---|
5294 |
|
---|
5295 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
5296 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5297 | IEM_MC_ADVANCE_RIP();
|
---|
5298 | IEM_MC_END();
|
---|
5299 | return VINF_SUCCESS;
|
---|
5300 |
|
---|
5301 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5302 | }
|
---|
5303 | }
|
---|
5304 | }
|
---|
5305 |
|
---|
5306 |
|
---|
5307 |
|
---|
5308 | /** Opcode 0x0f 0xa4. */
|
---|
5309 | FNIEMOP_DEF(iemOp_shld_Ev_Gv_Ib)
|
---|
5310 | {
|
---|
5311 | IEMOP_MNEMONIC("shld Ev,Gv,Ib");
|
---|
5312 | IEMOP_HLP_MIN_386();
|
---|
5313 | return FNIEMOP_CALL_1(iemOpCommonShldShrd_Ib, &g_iemAImpl_shld);
|
---|
5314 | }
|
---|
5315 |
|
---|
5316 |
|
---|
5317 | /** Opcode 0x0f 0xa5. */
|
---|
5318 | FNIEMOP_DEF(iemOp_shld_Ev_Gv_CL)
|
---|
5319 | {
|
---|
5320 | IEMOP_MNEMONIC("shld Ev,Gv,CL");
|
---|
5321 | IEMOP_HLP_MIN_386();
|
---|
5322 | return FNIEMOP_CALL_1(iemOpCommonShldShrd_CL, &g_iemAImpl_shld);
|
---|
5323 | }
|
---|
5324 |
|
---|
5325 |
|
---|
5326 | /** Opcode 0x0f 0xa8. */
|
---|
5327 | FNIEMOP_DEF(iemOp_push_gs)
|
---|
5328 | {
|
---|
5329 | IEMOP_MNEMONIC("push gs");
|
---|
5330 | IEMOP_HLP_MIN_386();
|
---|
5331 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5332 | return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_GS);
|
---|
5333 | }
|
---|
5334 |
|
---|
5335 |
|
---|
5336 | /** Opcode 0x0f 0xa9. */
|
---|
5337 | FNIEMOP_DEF(iemOp_pop_gs)
|
---|
5338 | {
|
---|
5339 | IEMOP_MNEMONIC("pop gs");
|
---|
5340 | IEMOP_HLP_MIN_386();
|
---|
5341 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5342 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_GS, pVCpu->iem.s.enmEffOpSize);
|
---|
5343 | }
|
---|
5344 |
|
---|
5345 |
|
---|
5346 | /** Opcode 0x0f 0xaa. */
|
---|
5347 | FNIEMOP_STUB(iemOp_rsm);
|
---|
5348 | //IEMOP_HLP_MIN_386();
|
---|
5349 |
|
---|
5350 |
|
---|
5351 | /** Opcode 0x0f 0xab. */
|
---|
5352 | FNIEMOP_DEF(iemOp_bts_Ev_Gv)
|
---|
5353 | {
|
---|
5354 | IEMOP_MNEMONIC("bts Ev,Gv");
|
---|
5355 | IEMOP_HLP_MIN_386();
|
---|
5356 | return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_bts);
|
---|
5357 | }
|
---|
5358 |
|
---|
5359 |
|
---|
5360 | /** Opcode 0x0f 0xac. */
|
---|
5361 | FNIEMOP_DEF(iemOp_shrd_Ev_Gv_Ib)
|
---|
5362 | {
|
---|
5363 | IEMOP_MNEMONIC("shrd Ev,Gv,Ib");
|
---|
5364 | IEMOP_HLP_MIN_386();
|
---|
5365 | return FNIEMOP_CALL_1(iemOpCommonShldShrd_Ib, &g_iemAImpl_shrd);
|
---|
5366 | }
|
---|
5367 |
|
---|
5368 |
|
---|
5369 | /** Opcode 0x0f 0xad. */
|
---|
5370 | FNIEMOP_DEF(iemOp_shrd_Ev_Gv_CL)
|
---|
5371 | {
|
---|
5372 | IEMOP_MNEMONIC("shrd Ev,Gv,CL");
|
---|
5373 | IEMOP_HLP_MIN_386();
|
---|
5374 | return FNIEMOP_CALL_1(iemOpCommonShldShrd_CL, &g_iemAImpl_shrd);
|
---|
5375 | }
|
---|
5376 |
|
---|
5377 |
|
---|
5378 | /** Opcode 0x0f 0xae mem/0. */
|
---|
5379 | FNIEMOP_DEF_1(iemOp_Grp15_fxsave, uint8_t, bRm)
|
---|
5380 | {
|
---|
5381 | IEMOP_MNEMONIC("fxsave m512");
|
---|
5382 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFxSaveRstor)
|
---|
5383 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5384 |
|
---|
5385 | IEM_MC_BEGIN(3, 1);
|
---|
5386 | IEM_MC_ARG(uint8_t, iEffSeg, 0);
|
---|
5387 | IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
|
---|
5388 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 2);
|
---|
5389 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
5390 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5391 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
5392 | IEM_MC_CALL_CIMPL_3(iemCImpl_fxsave, iEffSeg, GCPtrEff, enmEffOpSize);
|
---|
5393 | IEM_MC_END();
|
---|
5394 | return VINF_SUCCESS;
|
---|
5395 | }
|
---|
5396 |
|
---|
5397 |
|
---|
5398 | /** Opcode 0x0f 0xae mem/1. */
|
---|
5399 | FNIEMOP_DEF_1(iemOp_Grp15_fxrstor, uint8_t, bRm)
|
---|
5400 | {
|
---|
5401 | IEMOP_MNEMONIC("fxrstor m512");
|
---|
5402 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFxSaveRstor)
|
---|
5403 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5404 |
|
---|
5405 | IEM_MC_BEGIN(3, 1);
|
---|
5406 | IEM_MC_ARG(uint8_t, iEffSeg, 0);
|
---|
5407 | IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
|
---|
5408 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 2);
|
---|
5409 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
5410 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5411 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
5412 | IEM_MC_CALL_CIMPL_3(iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize);
|
---|
5413 | IEM_MC_END();
|
---|
5414 | return VINF_SUCCESS;
|
---|
5415 | }
|
---|
5416 |
|
---|
5417 |
|
---|
5418 | /** Opcode 0x0f 0xae mem/2. */
|
---|
5419 | FNIEMOP_STUB_1(iemOp_Grp15_ldmxcsr, uint8_t, bRm);
|
---|
5420 |
|
---|
5421 | /** Opcode 0x0f 0xae mem/3. */
|
---|
5422 | FNIEMOP_STUB_1(iemOp_Grp15_stmxcsr, uint8_t, bRm);
|
---|
5423 |
|
---|
5424 | /** Opcode 0x0f 0xae mem/4. */
|
---|
5425 | FNIEMOP_UD_STUB_1(iemOp_Grp15_xsave, uint8_t, bRm);
|
---|
5426 |
|
---|
5427 | /** Opcode 0x0f 0xae mem/5. */
|
---|
5428 | FNIEMOP_UD_STUB_1(iemOp_Grp15_xrstor, uint8_t, bRm);
|
---|
5429 |
|
---|
5430 | /** Opcode 0x0f 0xae mem/6. */
|
---|
5431 | FNIEMOP_UD_STUB_1(iemOp_Grp15_xsaveopt, uint8_t, bRm);
|
---|
5432 |
|
---|
5433 | /** Opcode 0x0f 0xae mem/7. */
|
---|
5434 | FNIEMOP_STUB_1(iemOp_Grp15_clflush, uint8_t, bRm);
|
---|
5435 |
|
---|
5436 |
|
---|
5437 | /** Opcode 0x0f 0xae 11b/5. */
|
---|
5438 | FNIEMOP_DEF_1(iemOp_Grp15_lfence, uint8_t, bRm)
|
---|
5439 | {
|
---|
5440 | IEMOP_MNEMONIC("lfence");
|
---|
5441 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5442 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
|
---|
5443 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5444 |
|
---|
5445 | IEM_MC_BEGIN(0, 0);
|
---|
5446 | if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
|
---|
5447 | IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_lfence);
|
---|
5448 | else
|
---|
5449 | IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
|
---|
5450 | IEM_MC_ADVANCE_RIP();
|
---|
5451 | IEM_MC_END();
|
---|
5452 | return VINF_SUCCESS;
|
---|
5453 | }
|
---|
5454 |
|
---|
5455 |
|
---|
5456 | /** Opcode 0x0f 0xae 11b/6. */
|
---|
5457 | FNIEMOP_DEF_1(iemOp_Grp15_mfence, uint8_t, bRm)
|
---|
5458 | {
|
---|
5459 | IEMOP_MNEMONIC("mfence");
|
---|
5460 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5461 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
|
---|
5462 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5463 |
|
---|
5464 | IEM_MC_BEGIN(0, 0);
|
---|
5465 | if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
|
---|
5466 | IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_mfence);
|
---|
5467 | else
|
---|
5468 | IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
|
---|
5469 | IEM_MC_ADVANCE_RIP();
|
---|
5470 | IEM_MC_END();
|
---|
5471 | return VINF_SUCCESS;
|
---|
5472 | }
|
---|
5473 |
|
---|
5474 |
|
---|
5475 | /** Opcode 0x0f 0xae 11b/7. */
|
---|
5476 | FNIEMOP_DEF_1(iemOp_Grp15_sfence, uint8_t, bRm)
|
---|
5477 | {
|
---|
5478 | IEMOP_MNEMONIC("sfence");
|
---|
5479 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5480 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
|
---|
5481 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5482 |
|
---|
5483 | IEM_MC_BEGIN(0, 0);
|
---|
5484 | if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
|
---|
5485 | IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_sfence);
|
---|
5486 | else
|
---|
5487 | IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
|
---|
5488 | IEM_MC_ADVANCE_RIP();
|
---|
5489 | IEM_MC_END();
|
---|
5490 | return VINF_SUCCESS;
|
---|
5491 | }
|
---|
5492 |
|
---|
5493 |
|
---|
5494 | /** Opcode 0xf3 0x0f 0xae 11b/0. */
|
---|
5495 | FNIEMOP_UD_STUB_1(iemOp_Grp15_rdfsbase, uint8_t, bRm);
|
---|
5496 |
|
---|
5497 | /** Opcode 0xf3 0x0f 0xae 11b/1. */
|
---|
5498 | FNIEMOP_UD_STUB_1(iemOp_Grp15_rdgsbase, uint8_t, bRm);
|
---|
5499 |
|
---|
5500 | /** Opcode 0xf3 0x0f 0xae 11b/2. */
|
---|
5501 | FNIEMOP_UD_STUB_1(iemOp_Grp15_wrfsbase, uint8_t, bRm);
|
---|
5502 |
|
---|
5503 | /** Opcode 0xf3 0x0f 0xae 11b/3. */
|
---|
5504 | FNIEMOP_UD_STUB_1(iemOp_Grp15_wrgsbase, uint8_t, bRm);
|
---|
5505 |
|
---|
5506 |
|
---|
5507 | /** Opcode 0x0f 0xae. */
|
---|
5508 | FNIEMOP_DEF(iemOp_Grp15)
|
---|
5509 | {
|
---|
5510 | IEMOP_HLP_MIN_586(); /* Not entirely accurate nor needed, but useful for debugging 286 code. */
|
---|
5511 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5512 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
5513 | {
|
---|
5514 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
5515 | {
|
---|
5516 | case 0: return FNIEMOP_CALL_1(iemOp_Grp15_fxsave, bRm);
|
---|
5517 | case 1: return FNIEMOP_CALL_1(iemOp_Grp15_fxrstor, bRm);
|
---|
5518 | case 2: return FNIEMOP_CALL_1(iemOp_Grp15_ldmxcsr, bRm);
|
---|
5519 | case 3: return FNIEMOP_CALL_1(iemOp_Grp15_stmxcsr, bRm);
|
---|
5520 | case 4: return FNIEMOP_CALL_1(iemOp_Grp15_xsave, bRm);
|
---|
5521 | case 5: return FNIEMOP_CALL_1(iemOp_Grp15_xrstor, bRm);
|
---|
5522 | case 6: return FNIEMOP_CALL_1(iemOp_Grp15_xsaveopt,bRm);
|
---|
5523 | case 7: return FNIEMOP_CALL_1(iemOp_Grp15_clflush, bRm);
|
---|
5524 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5525 | }
|
---|
5526 | }
|
---|
5527 | else
|
---|
5528 | {
|
---|
5529 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_LOCK))
|
---|
5530 | {
|
---|
5531 | case 0:
|
---|
5532 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
5533 | {
|
---|
5534 | case 0: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5535 | case 1: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5536 | case 2: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5537 | case 3: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5538 | case 4: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5539 | case 5: return FNIEMOP_CALL_1(iemOp_Grp15_lfence, bRm);
|
---|
5540 | case 6: return FNIEMOP_CALL_1(iemOp_Grp15_mfence, bRm);
|
---|
5541 | case 7: return FNIEMOP_CALL_1(iemOp_Grp15_sfence, bRm);
|
---|
5542 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5543 | }
|
---|
5544 | break;
|
---|
5545 |
|
---|
5546 | case IEM_OP_PRF_REPZ:
|
---|
5547 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
5548 | {
|
---|
5549 | case 0: return FNIEMOP_CALL_1(iemOp_Grp15_rdfsbase, bRm);
|
---|
5550 | case 1: return FNIEMOP_CALL_1(iemOp_Grp15_rdgsbase, bRm);
|
---|
5551 | case 2: return FNIEMOP_CALL_1(iemOp_Grp15_wrfsbase, bRm);
|
---|
5552 | case 3: return FNIEMOP_CALL_1(iemOp_Grp15_wrgsbase, bRm);
|
---|
5553 | case 4: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5554 | case 5: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5555 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5556 | case 7: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5557 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5558 | }
|
---|
5559 | break;
|
---|
5560 |
|
---|
5561 | default:
|
---|
5562 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5563 | }
|
---|
5564 | }
|
---|
5565 | }
|
---|
5566 |
|
---|
5567 |
|
---|
5568 | /** Opcode 0x0f 0xaf. */
|
---|
5569 | FNIEMOP_DEF(iemOp_imul_Gv_Ev)
|
---|
5570 | {
|
---|
5571 | IEMOP_MNEMONIC("imul Gv,Ev");
|
---|
5572 | IEMOP_HLP_MIN_386();
|
---|
5573 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
5574 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_imul_two);
|
---|
5575 | }
|
---|
5576 |
|
---|
5577 |
|
---|
5578 | /** Opcode 0x0f 0xb0. */
|
---|
5579 | FNIEMOP_DEF(iemOp_cmpxchg_Eb_Gb)
|
---|
5580 | {
|
---|
5581 | IEMOP_MNEMONIC("cmpxchg Eb,Gb");
|
---|
5582 | IEMOP_HLP_MIN_486();
|
---|
5583 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5584 |
|
---|
5585 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
5586 | {
|
---|
5587 | IEMOP_HLP_DONE_DECODING();
|
---|
5588 | IEM_MC_BEGIN(4, 0);
|
---|
5589 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
5590 | IEM_MC_ARG(uint8_t *, pu8Al, 1);
|
---|
5591 | IEM_MC_ARG(uint8_t, u8Src, 2);
|
---|
5592 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5593 |
|
---|
5594 | IEM_MC_FETCH_GREG_U8(u8Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5595 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5596 | IEM_MC_REF_GREG_U8(pu8Al, X86_GREG_xAX);
|
---|
5597 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5598 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5599 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8, pu8Dst, pu8Al, u8Src, pEFlags);
|
---|
5600 | else
|
---|
5601 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8_locked, pu8Dst, pu8Al, u8Src, pEFlags);
|
---|
5602 |
|
---|
5603 | IEM_MC_ADVANCE_RIP();
|
---|
5604 | IEM_MC_END();
|
---|
5605 | }
|
---|
5606 | else
|
---|
5607 | {
|
---|
5608 | IEM_MC_BEGIN(4, 3);
|
---|
5609 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
5610 | IEM_MC_ARG(uint8_t *, pu8Al, 1);
|
---|
5611 | IEM_MC_ARG(uint8_t, u8Src, 2);
|
---|
5612 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5613 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5614 | IEM_MC_LOCAL(uint8_t, u8Al);
|
---|
5615 |
|
---|
5616 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
5617 | IEMOP_HLP_DONE_DECODING();
|
---|
5618 | IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5619 | IEM_MC_FETCH_GREG_U8(u8Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5620 | IEM_MC_FETCH_GREG_U8(u8Al, X86_GREG_xAX);
|
---|
5621 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5622 | IEM_MC_REF_LOCAL(pu8Al, u8Al);
|
---|
5623 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5624 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8, pu8Dst, pu8Al, u8Src, pEFlags);
|
---|
5625 | else
|
---|
5626 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8_locked, pu8Dst, pu8Al, u8Src, pEFlags);
|
---|
5627 |
|
---|
5628 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
|
---|
5629 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5630 | IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Al);
|
---|
5631 | IEM_MC_ADVANCE_RIP();
|
---|
5632 | IEM_MC_END();
|
---|
5633 | }
|
---|
5634 | return VINF_SUCCESS;
|
---|
5635 | }
|
---|
5636 |
|
---|
5637 | /** Opcode 0x0f 0xb1. */
|
---|
5638 | FNIEMOP_DEF(iemOp_cmpxchg_Ev_Gv)
|
---|
5639 | {
|
---|
5640 | IEMOP_MNEMONIC("cmpxchg Ev,Gv");
|
---|
5641 | IEMOP_HLP_MIN_486();
|
---|
5642 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5643 |
|
---|
5644 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
5645 | {
|
---|
5646 | IEMOP_HLP_DONE_DECODING();
|
---|
5647 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5648 | {
|
---|
5649 | case IEMMODE_16BIT:
|
---|
5650 | IEM_MC_BEGIN(4, 0);
|
---|
5651 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
5652 | IEM_MC_ARG(uint16_t *, pu16Ax, 1);
|
---|
5653 | IEM_MC_ARG(uint16_t, u16Src, 2);
|
---|
5654 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5655 |
|
---|
5656 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5657 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5658 | IEM_MC_REF_GREG_U16(pu16Ax, X86_GREG_xAX);
|
---|
5659 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5660 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5661 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16, pu16Dst, pu16Ax, u16Src, pEFlags);
|
---|
5662 | else
|
---|
5663 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16_locked, pu16Dst, pu16Ax, u16Src, pEFlags);
|
---|
5664 |
|
---|
5665 | IEM_MC_ADVANCE_RIP();
|
---|
5666 | IEM_MC_END();
|
---|
5667 | return VINF_SUCCESS;
|
---|
5668 |
|
---|
5669 | case IEMMODE_32BIT:
|
---|
5670 | IEM_MC_BEGIN(4, 0);
|
---|
5671 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
5672 | IEM_MC_ARG(uint32_t *, pu32Eax, 1);
|
---|
5673 | IEM_MC_ARG(uint32_t, u32Src, 2);
|
---|
5674 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5675 |
|
---|
5676 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5677 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5678 | IEM_MC_REF_GREG_U32(pu32Eax, X86_GREG_xAX);
|
---|
5679 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5680 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5681 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32, pu32Dst, pu32Eax, u32Src, pEFlags);
|
---|
5682 | else
|
---|
5683 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32_locked, pu32Dst, pu32Eax, u32Src, pEFlags);
|
---|
5684 |
|
---|
5685 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Eax);
|
---|
5686 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
5687 | IEM_MC_ADVANCE_RIP();
|
---|
5688 | IEM_MC_END();
|
---|
5689 | return VINF_SUCCESS;
|
---|
5690 |
|
---|
5691 | case IEMMODE_64BIT:
|
---|
5692 | IEM_MC_BEGIN(4, 0);
|
---|
5693 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
5694 | IEM_MC_ARG(uint64_t *, pu64Rax, 1);
|
---|
5695 | #ifdef RT_ARCH_X86
|
---|
5696 | IEM_MC_ARG(uint64_t *, pu64Src, 2);
|
---|
5697 | #else
|
---|
5698 | IEM_MC_ARG(uint64_t, u64Src, 2);
|
---|
5699 | #endif
|
---|
5700 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
5701 |
|
---|
5702 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5703 | IEM_MC_REF_GREG_U64(pu64Rax, X86_GREG_xAX);
|
---|
5704 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
5705 | #ifdef RT_ARCH_X86
|
---|
5706 | IEM_MC_REF_GREG_U64(pu64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5707 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5708 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, pu64Src, pEFlags);
|
---|
5709 | else
|
---|
5710 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, pu64Src, pEFlags);
|
---|
5711 | #else
|
---|
5712 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5713 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5714 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, u64Src, pEFlags);
|
---|
5715 | else
|
---|
5716 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, u64Src, pEFlags);
|
---|
5717 | #endif
|
---|
5718 |
|
---|
5719 | IEM_MC_ADVANCE_RIP();
|
---|
5720 | IEM_MC_END();
|
---|
5721 | return VINF_SUCCESS;
|
---|
5722 |
|
---|
5723 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5724 | }
|
---|
5725 | }
|
---|
5726 | else
|
---|
5727 | {
|
---|
5728 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5729 | {
|
---|
5730 | case IEMMODE_16BIT:
|
---|
5731 | IEM_MC_BEGIN(4, 3);
|
---|
5732 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
5733 | IEM_MC_ARG(uint16_t *, pu16Ax, 1);
|
---|
5734 | IEM_MC_ARG(uint16_t, u16Src, 2);
|
---|
5735 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5736 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5737 | IEM_MC_LOCAL(uint16_t, u16Ax);
|
---|
5738 |
|
---|
5739 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
5740 | IEMOP_HLP_DONE_DECODING();
|
---|
5741 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5742 | IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5743 | IEM_MC_FETCH_GREG_U16(u16Ax, X86_GREG_xAX);
|
---|
5744 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5745 | IEM_MC_REF_LOCAL(pu16Ax, u16Ax);
|
---|
5746 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5747 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16, pu16Dst, pu16Ax, u16Src, pEFlags);
|
---|
5748 | else
|
---|
5749 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16_locked, pu16Dst, pu16Ax, u16Src, pEFlags);
|
---|
5750 |
|
---|
5751 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
5752 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5753 | IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Ax);
|
---|
5754 | IEM_MC_ADVANCE_RIP();
|
---|
5755 | IEM_MC_END();
|
---|
5756 | return VINF_SUCCESS;
|
---|
5757 |
|
---|
5758 | case IEMMODE_32BIT:
|
---|
5759 | IEM_MC_BEGIN(4, 3);
|
---|
5760 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
5761 | IEM_MC_ARG(uint32_t *, pu32Eax, 1);
|
---|
5762 | IEM_MC_ARG(uint32_t, u32Src, 2);
|
---|
5763 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5764 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5765 | IEM_MC_LOCAL(uint32_t, u32Eax);
|
---|
5766 |
|
---|
5767 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
5768 | IEMOP_HLP_DONE_DECODING();
|
---|
5769 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5770 | IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5771 | IEM_MC_FETCH_GREG_U32(u32Eax, X86_GREG_xAX);
|
---|
5772 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5773 | IEM_MC_REF_LOCAL(pu32Eax, u32Eax);
|
---|
5774 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5775 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32, pu32Dst, pu32Eax, u32Src, pEFlags);
|
---|
5776 | else
|
---|
5777 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32_locked, pu32Dst, pu32Eax, u32Src, pEFlags);
|
---|
5778 |
|
---|
5779 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
5780 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5781 | IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Eax);
|
---|
5782 | IEM_MC_ADVANCE_RIP();
|
---|
5783 | IEM_MC_END();
|
---|
5784 | return VINF_SUCCESS;
|
---|
5785 |
|
---|
5786 | case IEMMODE_64BIT:
|
---|
5787 | IEM_MC_BEGIN(4, 3);
|
---|
5788 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
5789 | IEM_MC_ARG(uint64_t *, pu64Rax, 1);
|
---|
5790 | #ifdef RT_ARCH_X86
|
---|
5791 | IEM_MC_ARG(uint64_t *, pu64Src, 2);
|
---|
5792 | #else
|
---|
5793 | IEM_MC_ARG(uint64_t, u64Src, 2);
|
---|
5794 | #endif
|
---|
5795 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
|
---|
5796 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5797 | IEM_MC_LOCAL(uint64_t, u64Rax);
|
---|
5798 |
|
---|
5799 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
5800 | IEMOP_HLP_DONE_DECODING();
|
---|
5801 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
5802 | IEM_MC_FETCH_GREG_U64(u64Rax, X86_GREG_xAX);
|
---|
5803 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
5804 | IEM_MC_REF_LOCAL(pu64Rax, u64Rax);
|
---|
5805 | #ifdef RT_ARCH_X86
|
---|
5806 | IEM_MC_REF_GREG_U64(pu64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5807 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5808 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, pu64Src, pEFlags);
|
---|
5809 | else
|
---|
5810 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, pu64Src, pEFlags);
|
---|
5811 | #else
|
---|
5812 | IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
5813 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
5814 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, u64Src, pEFlags);
|
---|
5815 | else
|
---|
5816 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, u64Src, pEFlags);
|
---|
5817 | #endif
|
---|
5818 |
|
---|
5819 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
5820 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
5821 | IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Rax);
|
---|
5822 | IEM_MC_ADVANCE_RIP();
|
---|
5823 | IEM_MC_END();
|
---|
5824 | return VINF_SUCCESS;
|
---|
5825 |
|
---|
5826 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5827 | }
|
---|
5828 | }
|
---|
5829 | }
|
---|
5830 |
|
---|
5831 |
|
---|
5832 | FNIEMOP_DEF_2(iemOpCommonLoadSRegAndGreg, uint8_t, iSegReg, uint8_t, bRm)
|
---|
5833 | {
|
---|
5834 | Assert((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)); /* Caller checks this */
|
---|
5835 | uint8_t const iGReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
|
---|
5836 |
|
---|
5837 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5838 | {
|
---|
5839 | case IEMMODE_16BIT:
|
---|
5840 | IEM_MC_BEGIN(5, 1);
|
---|
5841 | IEM_MC_ARG(uint16_t, uSel, 0);
|
---|
5842 | IEM_MC_ARG(uint16_t, offSeg, 1);
|
---|
5843 | IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
|
---|
5844 | IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
|
---|
5845 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
|
---|
5846 | IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
|
---|
5847 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
5848 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5849 | IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
|
---|
5850 | IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 2);
|
---|
5851 | IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
|
---|
5852 | IEM_MC_END();
|
---|
5853 | return VINF_SUCCESS;
|
---|
5854 |
|
---|
5855 | case IEMMODE_32BIT:
|
---|
5856 | IEM_MC_BEGIN(5, 1);
|
---|
5857 | IEM_MC_ARG(uint16_t, uSel, 0);
|
---|
5858 | IEM_MC_ARG(uint32_t, offSeg, 1);
|
---|
5859 | IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
|
---|
5860 | IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
|
---|
5861 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
|
---|
5862 | IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
|
---|
5863 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
5864 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5865 | IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
|
---|
5866 | IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 4);
|
---|
5867 | IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
|
---|
5868 | IEM_MC_END();
|
---|
5869 | return VINF_SUCCESS;
|
---|
5870 |
|
---|
5871 | case IEMMODE_64BIT:
|
---|
5872 | IEM_MC_BEGIN(5, 1);
|
---|
5873 | IEM_MC_ARG(uint16_t, uSel, 0);
|
---|
5874 | IEM_MC_ARG(uint64_t, offSeg, 1);
|
---|
5875 | IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
|
---|
5876 | IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
|
---|
5877 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
|
---|
5878 | IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
|
---|
5879 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
5880 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5881 | if (IEM_IS_GUEST_CPU_AMD(pVCpu)) /** @todo testcase: rev 3.15 of the amd manuals claims it only loads a 32-bit greg. */
|
---|
5882 | IEM_MC_FETCH_MEM_U32_SX_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
|
---|
5883 | else
|
---|
5884 | IEM_MC_FETCH_MEM_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
|
---|
5885 | IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 8);
|
---|
5886 | IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
|
---|
5887 | IEM_MC_END();
|
---|
5888 | return VINF_SUCCESS;
|
---|
5889 |
|
---|
5890 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5891 | }
|
---|
5892 | }
|
---|
5893 |
|
---|
5894 |
|
---|
5895 | /** Opcode 0x0f 0xb2. */
|
---|
5896 | FNIEMOP_DEF(iemOp_lss_Gv_Mp)
|
---|
5897 | {
|
---|
5898 | IEMOP_MNEMONIC("lss Gv,Mp");
|
---|
5899 | IEMOP_HLP_MIN_386();
|
---|
5900 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5901 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
5902 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5903 | return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_SS, bRm);
|
---|
5904 | }
|
---|
5905 |
|
---|
5906 |
|
---|
5907 | /** Opcode 0x0f 0xb3. */
|
---|
5908 | FNIEMOP_DEF(iemOp_btr_Ev_Gv)
|
---|
5909 | {
|
---|
5910 | IEMOP_MNEMONIC("btr Ev,Gv");
|
---|
5911 | return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_btr);
|
---|
5912 | }
|
---|
5913 |
|
---|
5914 |
|
---|
5915 | /** Opcode 0x0f 0xb4. */
|
---|
5916 | FNIEMOP_DEF(iemOp_lfs_Gv_Mp)
|
---|
5917 | {
|
---|
5918 | IEMOP_MNEMONIC("lfs Gv,Mp");
|
---|
5919 | IEMOP_HLP_MIN_386();
|
---|
5920 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5921 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
5922 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5923 | return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_FS, bRm);
|
---|
5924 | }
|
---|
5925 |
|
---|
5926 |
|
---|
5927 | /** Opcode 0x0f 0xb5. */
|
---|
5928 | FNIEMOP_DEF(iemOp_lgs_Gv_Mp)
|
---|
5929 | {
|
---|
5930 | IEMOP_MNEMONIC("lgs Gv,Mp");
|
---|
5931 | IEMOP_HLP_MIN_386();
|
---|
5932 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5933 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
5934 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
5935 | return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_GS, bRm);
|
---|
5936 | }
|
---|
5937 |
|
---|
5938 |
|
---|
5939 | /** Opcode 0x0f 0xb6. */
|
---|
5940 | FNIEMOP_DEF(iemOp_movzx_Gv_Eb)
|
---|
5941 | {
|
---|
5942 | IEMOP_MNEMONIC("movzx Gv,Eb");
|
---|
5943 | IEMOP_HLP_MIN_386();
|
---|
5944 |
|
---|
5945 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
5946 |
|
---|
5947 | /*
|
---|
5948 | * If rm is denoting a register, no more instruction bytes.
|
---|
5949 | */
|
---|
5950 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
5951 | {
|
---|
5952 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5953 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5954 | {
|
---|
5955 | case IEMMODE_16BIT:
|
---|
5956 | IEM_MC_BEGIN(0, 1);
|
---|
5957 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
5958 | IEM_MC_FETCH_GREG_U8_ZX_U16(u16Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5959 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
|
---|
5960 | IEM_MC_ADVANCE_RIP();
|
---|
5961 | IEM_MC_END();
|
---|
5962 | return VINF_SUCCESS;
|
---|
5963 |
|
---|
5964 | case IEMMODE_32BIT:
|
---|
5965 | IEM_MC_BEGIN(0, 1);
|
---|
5966 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
5967 | IEM_MC_FETCH_GREG_U8_ZX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5968 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
5969 | IEM_MC_ADVANCE_RIP();
|
---|
5970 | IEM_MC_END();
|
---|
5971 | return VINF_SUCCESS;
|
---|
5972 |
|
---|
5973 | case IEMMODE_64BIT:
|
---|
5974 | IEM_MC_BEGIN(0, 1);
|
---|
5975 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
5976 | IEM_MC_FETCH_GREG_U8_ZX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
5977 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
5978 | IEM_MC_ADVANCE_RIP();
|
---|
5979 | IEM_MC_END();
|
---|
5980 | return VINF_SUCCESS;
|
---|
5981 |
|
---|
5982 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
5983 | }
|
---|
5984 | }
|
---|
5985 | else
|
---|
5986 | {
|
---|
5987 | /*
|
---|
5988 | * We're loading a register from memory.
|
---|
5989 | */
|
---|
5990 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
5991 | {
|
---|
5992 | case IEMMODE_16BIT:
|
---|
5993 | IEM_MC_BEGIN(0, 2);
|
---|
5994 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
5995 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
5996 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
5997 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
5998 | IEM_MC_FETCH_MEM_U8_ZX_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
5999 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
|
---|
6000 | IEM_MC_ADVANCE_RIP();
|
---|
6001 | IEM_MC_END();
|
---|
6002 | return VINF_SUCCESS;
|
---|
6003 |
|
---|
6004 | case IEMMODE_32BIT:
|
---|
6005 | IEM_MC_BEGIN(0, 2);
|
---|
6006 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
6007 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6008 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6009 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6010 | IEM_MC_FETCH_MEM_U8_ZX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6011 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
6012 | IEM_MC_ADVANCE_RIP();
|
---|
6013 | IEM_MC_END();
|
---|
6014 | return VINF_SUCCESS;
|
---|
6015 |
|
---|
6016 | case IEMMODE_64BIT:
|
---|
6017 | IEM_MC_BEGIN(0, 2);
|
---|
6018 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
6019 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6020 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6021 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6022 | IEM_MC_FETCH_MEM_U8_ZX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6023 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
6024 | IEM_MC_ADVANCE_RIP();
|
---|
6025 | IEM_MC_END();
|
---|
6026 | return VINF_SUCCESS;
|
---|
6027 |
|
---|
6028 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6029 | }
|
---|
6030 | }
|
---|
6031 | }
|
---|
6032 |
|
---|
6033 |
|
---|
6034 | /** Opcode 0x0f 0xb7. */
|
---|
6035 | FNIEMOP_DEF(iemOp_movzx_Gv_Ew)
|
---|
6036 | {
|
---|
6037 | IEMOP_MNEMONIC("movzx Gv,Ew");
|
---|
6038 | IEMOP_HLP_MIN_386();
|
---|
6039 |
|
---|
6040 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
6041 |
|
---|
6042 | /** @todo Not entirely sure how the operand size prefix is handled here,
|
---|
6043 | * assuming that it will be ignored. Would be nice to have a few
|
---|
6044 | * test for this. */
|
---|
6045 | /*
|
---|
6046 | * If rm is denoting a register, no more instruction bytes.
|
---|
6047 | */
|
---|
6048 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
6049 | {
|
---|
6050 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6051 | if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
|
---|
6052 | {
|
---|
6053 | IEM_MC_BEGIN(0, 1);
|
---|
6054 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
6055 | IEM_MC_FETCH_GREG_U16_ZX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6056 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
6057 | IEM_MC_ADVANCE_RIP();
|
---|
6058 | IEM_MC_END();
|
---|
6059 | }
|
---|
6060 | else
|
---|
6061 | {
|
---|
6062 | IEM_MC_BEGIN(0, 1);
|
---|
6063 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
6064 | IEM_MC_FETCH_GREG_U16_ZX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6065 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
6066 | IEM_MC_ADVANCE_RIP();
|
---|
6067 | IEM_MC_END();
|
---|
6068 | }
|
---|
6069 | }
|
---|
6070 | else
|
---|
6071 | {
|
---|
6072 | /*
|
---|
6073 | * We're loading a register from memory.
|
---|
6074 | */
|
---|
6075 | if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
|
---|
6076 | {
|
---|
6077 | IEM_MC_BEGIN(0, 2);
|
---|
6078 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
6079 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6080 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6081 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6082 | IEM_MC_FETCH_MEM_U16_ZX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6083 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
6084 | IEM_MC_ADVANCE_RIP();
|
---|
6085 | IEM_MC_END();
|
---|
6086 | }
|
---|
6087 | else
|
---|
6088 | {
|
---|
6089 | IEM_MC_BEGIN(0, 2);
|
---|
6090 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
6091 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6092 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6093 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6094 | IEM_MC_FETCH_MEM_U16_ZX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6095 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
6096 | IEM_MC_ADVANCE_RIP();
|
---|
6097 | IEM_MC_END();
|
---|
6098 | }
|
---|
6099 | }
|
---|
6100 | return VINF_SUCCESS;
|
---|
6101 | }
|
---|
6102 |
|
---|
6103 |
|
---|
6104 | /** Opcode 0x0f 0xb8. */
|
---|
6105 | FNIEMOP_STUB(iemOp_popcnt_Gv_Ev_jmpe);
|
---|
6106 |
|
---|
6107 |
|
---|
6108 | /** Opcode 0x0f 0xb9. */
|
---|
6109 | FNIEMOP_DEF(iemOp_Grp10)
|
---|
6110 | {
|
---|
6111 | Log(("iemOp_Grp10 -> #UD\n"));
|
---|
6112 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6113 | }
|
---|
6114 |
|
---|
6115 |
|
---|
6116 | /** Opcode 0x0f 0xba. */
|
---|
6117 | FNIEMOP_DEF(iemOp_Grp8)
|
---|
6118 | {
|
---|
6119 | IEMOP_HLP_MIN_386();
|
---|
6120 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
6121 | PCIEMOPBINSIZES pImpl;
|
---|
6122 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
6123 | {
|
---|
6124 | case 0: case 1: case 2: case 3:
|
---|
6125 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6126 | case 4: pImpl = &g_iemAImpl_bt; IEMOP_MNEMONIC("bt Ev,Ib"); break;
|
---|
6127 | case 5: pImpl = &g_iemAImpl_bts; IEMOP_MNEMONIC("bts Ev,Ib"); break;
|
---|
6128 | case 6: pImpl = &g_iemAImpl_btr; IEMOP_MNEMONIC("btr Ev,Ib"); break;
|
---|
6129 | case 7: pImpl = &g_iemAImpl_btc; IEMOP_MNEMONIC("btc Ev,Ib"); break;
|
---|
6130 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6131 | }
|
---|
6132 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
6133 |
|
---|
6134 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
6135 | {
|
---|
6136 | /* register destination. */
|
---|
6137 | uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
|
---|
6138 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6139 |
|
---|
6140 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
6141 | {
|
---|
6142 | case IEMMODE_16BIT:
|
---|
6143 | IEM_MC_BEGIN(3, 0);
|
---|
6144 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
6145 | IEM_MC_ARG_CONST(uint16_t, u16Src, /*=*/ u8Bit & 0x0f, 1);
|
---|
6146 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
6147 |
|
---|
6148 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6149 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
6150 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
6151 |
|
---|
6152 | IEM_MC_ADVANCE_RIP();
|
---|
6153 | IEM_MC_END();
|
---|
6154 | return VINF_SUCCESS;
|
---|
6155 |
|
---|
6156 | case IEMMODE_32BIT:
|
---|
6157 | IEM_MC_BEGIN(3, 0);
|
---|
6158 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
6159 | IEM_MC_ARG_CONST(uint32_t, u32Src, /*=*/ u8Bit & 0x1f, 1);
|
---|
6160 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
6161 |
|
---|
6162 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6163 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
6164 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
6165 |
|
---|
6166 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
6167 | IEM_MC_ADVANCE_RIP();
|
---|
6168 | IEM_MC_END();
|
---|
6169 | return VINF_SUCCESS;
|
---|
6170 |
|
---|
6171 | case IEMMODE_64BIT:
|
---|
6172 | IEM_MC_BEGIN(3, 0);
|
---|
6173 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
6174 | IEM_MC_ARG_CONST(uint64_t, u64Src, /*=*/ u8Bit & 0x3f, 1);
|
---|
6175 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
6176 |
|
---|
6177 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6178 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
6179 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
6180 |
|
---|
6181 | IEM_MC_ADVANCE_RIP();
|
---|
6182 | IEM_MC_END();
|
---|
6183 | return VINF_SUCCESS;
|
---|
6184 |
|
---|
6185 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6186 | }
|
---|
6187 | }
|
---|
6188 | else
|
---|
6189 | {
|
---|
6190 | /* memory destination. */
|
---|
6191 |
|
---|
6192 | uint32_t fAccess;
|
---|
6193 | if (pImpl->pfnLockedU16)
|
---|
6194 | fAccess = IEM_ACCESS_DATA_RW;
|
---|
6195 | else /* BT */
|
---|
6196 | fAccess = IEM_ACCESS_DATA_R;
|
---|
6197 |
|
---|
6198 | /** @todo test negative bit offsets! */
|
---|
6199 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
6200 | {
|
---|
6201 | case IEMMODE_16BIT:
|
---|
6202 | IEM_MC_BEGIN(3, 1);
|
---|
6203 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
6204 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
6205 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
6206 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6207 |
|
---|
6208 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
6209 | uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
|
---|
6210 | IEM_MC_ASSIGN(u16Src, u8Bit & 0x0f);
|
---|
6211 | if (pImpl->pfnLockedU16)
|
---|
6212 | IEMOP_HLP_DONE_DECODING();
|
---|
6213 | else
|
---|
6214 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6215 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
6216 | IEM_MC_MEM_MAP(pu16Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
6217 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
6218 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
6219 | else
|
---|
6220 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
|
---|
6221 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, fAccess);
|
---|
6222 |
|
---|
6223 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
6224 | IEM_MC_ADVANCE_RIP();
|
---|
6225 | IEM_MC_END();
|
---|
6226 | return VINF_SUCCESS;
|
---|
6227 |
|
---|
6228 | case IEMMODE_32BIT:
|
---|
6229 | IEM_MC_BEGIN(3, 1);
|
---|
6230 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
6231 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
6232 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
6233 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6234 |
|
---|
6235 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
6236 | uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
|
---|
6237 | IEM_MC_ASSIGN(u32Src, u8Bit & 0x1f);
|
---|
6238 | if (pImpl->pfnLockedU16)
|
---|
6239 | IEMOP_HLP_DONE_DECODING();
|
---|
6240 | else
|
---|
6241 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6242 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
6243 | IEM_MC_MEM_MAP(pu32Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
6244 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
6245 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
6246 | else
|
---|
6247 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
|
---|
6248 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, fAccess);
|
---|
6249 |
|
---|
6250 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
6251 | IEM_MC_ADVANCE_RIP();
|
---|
6252 | IEM_MC_END();
|
---|
6253 | return VINF_SUCCESS;
|
---|
6254 |
|
---|
6255 | case IEMMODE_64BIT:
|
---|
6256 | IEM_MC_BEGIN(3, 1);
|
---|
6257 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
6258 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
6259 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
6260 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6261 |
|
---|
6262 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
6263 | uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
|
---|
6264 | IEM_MC_ASSIGN(u64Src, u8Bit & 0x3f);
|
---|
6265 | if (pImpl->pfnLockedU16)
|
---|
6266 | IEMOP_HLP_DONE_DECODING();
|
---|
6267 | else
|
---|
6268 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6269 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
6270 | IEM_MC_MEM_MAP(pu64Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
|
---|
6271 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
6272 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
6273 | else
|
---|
6274 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
|
---|
6275 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, fAccess);
|
---|
6276 |
|
---|
6277 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
6278 | IEM_MC_ADVANCE_RIP();
|
---|
6279 | IEM_MC_END();
|
---|
6280 | return VINF_SUCCESS;
|
---|
6281 |
|
---|
6282 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6283 | }
|
---|
6284 | }
|
---|
6285 |
|
---|
6286 | }
|
---|
6287 |
|
---|
6288 |
|
---|
6289 | /** Opcode 0x0f 0xbb. */
|
---|
6290 | FNIEMOP_DEF(iemOp_btc_Ev_Gv)
|
---|
6291 | {
|
---|
6292 | IEMOP_MNEMONIC("btc Ev,Gv");
|
---|
6293 | IEMOP_HLP_MIN_386();
|
---|
6294 | return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_btc);
|
---|
6295 | }
|
---|
6296 |
|
---|
6297 |
|
---|
6298 | /** Opcode 0x0f 0xbc. */
|
---|
6299 | FNIEMOP_DEF(iemOp_bsf_Gv_Ev)
|
---|
6300 | {
|
---|
6301 | IEMOP_MNEMONIC("bsf Gv,Ev");
|
---|
6302 | IEMOP_HLP_MIN_386();
|
---|
6303 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
|
---|
6304 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_bsf);
|
---|
6305 | }
|
---|
6306 |
|
---|
6307 |
|
---|
6308 | /** Opcode 0x0f 0xbd. */
|
---|
6309 | FNIEMOP_DEF(iemOp_bsr_Gv_Ev)
|
---|
6310 | {
|
---|
6311 | IEMOP_MNEMONIC("bsr Gv,Ev");
|
---|
6312 | IEMOP_HLP_MIN_386();
|
---|
6313 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
|
---|
6314 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_bsr);
|
---|
6315 | }
|
---|
6316 |
|
---|
6317 |
|
---|
6318 | /** Opcode 0x0f 0xbe. */
|
---|
6319 | FNIEMOP_DEF(iemOp_movsx_Gv_Eb)
|
---|
6320 | {
|
---|
6321 | IEMOP_MNEMONIC("movsx Gv,Eb");
|
---|
6322 | IEMOP_HLP_MIN_386();
|
---|
6323 |
|
---|
6324 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
6325 |
|
---|
6326 | /*
|
---|
6327 | * If rm is denoting a register, no more instruction bytes.
|
---|
6328 | */
|
---|
6329 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
6330 | {
|
---|
6331 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6332 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
6333 | {
|
---|
6334 | case IEMMODE_16BIT:
|
---|
6335 | IEM_MC_BEGIN(0, 1);
|
---|
6336 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
6337 | IEM_MC_FETCH_GREG_U8_SX_U16(u16Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6338 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
|
---|
6339 | IEM_MC_ADVANCE_RIP();
|
---|
6340 | IEM_MC_END();
|
---|
6341 | return VINF_SUCCESS;
|
---|
6342 |
|
---|
6343 | case IEMMODE_32BIT:
|
---|
6344 | IEM_MC_BEGIN(0, 1);
|
---|
6345 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
6346 | IEM_MC_FETCH_GREG_U8_SX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6347 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
6348 | IEM_MC_ADVANCE_RIP();
|
---|
6349 | IEM_MC_END();
|
---|
6350 | return VINF_SUCCESS;
|
---|
6351 |
|
---|
6352 | case IEMMODE_64BIT:
|
---|
6353 | IEM_MC_BEGIN(0, 1);
|
---|
6354 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
6355 | IEM_MC_FETCH_GREG_U8_SX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6356 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
6357 | IEM_MC_ADVANCE_RIP();
|
---|
6358 | IEM_MC_END();
|
---|
6359 | return VINF_SUCCESS;
|
---|
6360 |
|
---|
6361 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6362 | }
|
---|
6363 | }
|
---|
6364 | else
|
---|
6365 | {
|
---|
6366 | /*
|
---|
6367 | * We're loading a register from memory.
|
---|
6368 | */
|
---|
6369 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
6370 | {
|
---|
6371 | case IEMMODE_16BIT:
|
---|
6372 | IEM_MC_BEGIN(0, 2);
|
---|
6373 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
6374 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6375 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6376 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6377 | IEM_MC_FETCH_MEM_U8_SX_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6378 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
|
---|
6379 | IEM_MC_ADVANCE_RIP();
|
---|
6380 | IEM_MC_END();
|
---|
6381 | return VINF_SUCCESS;
|
---|
6382 |
|
---|
6383 | case IEMMODE_32BIT:
|
---|
6384 | IEM_MC_BEGIN(0, 2);
|
---|
6385 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
6386 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6387 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6388 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6389 | IEM_MC_FETCH_MEM_U8_SX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6390 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
6391 | IEM_MC_ADVANCE_RIP();
|
---|
6392 | IEM_MC_END();
|
---|
6393 | return VINF_SUCCESS;
|
---|
6394 |
|
---|
6395 | case IEMMODE_64BIT:
|
---|
6396 | IEM_MC_BEGIN(0, 2);
|
---|
6397 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
6398 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6399 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6400 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6401 | IEM_MC_FETCH_MEM_U8_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6402 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
6403 | IEM_MC_ADVANCE_RIP();
|
---|
6404 | IEM_MC_END();
|
---|
6405 | return VINF_SUCCESS;
|
---|
6406 |
|
---|
6407 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6408 | }
|
---|
6409 | }
|
---|
6410 | }
|
---|
6411 |
|
---|
6412 |
|
---|
6413 | /** Opcode 0x0f 0xbf. */
|
---|
6414 | FNIEMOP_DEF(iemOp_movsx_Gv_Ew)
|
---|
6415 | {
|
---|
6416 | IEMOP_MNEMONIC("movsx Gv,Ew");
|
---|
6417 | IEMOP_HLP_MIN_386();
|
---|
6418 |
|
---|
6419 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
6420 |
|
---|
6421 | /** @todo Not entirely sure how the operand size prefix is handled here,
|
---|
6422 | * assuming that it will be ignored. Would be nice to have a few
|
---|
6423 | * test for this. */
|
---|
6424 | /*
|
---|
6425 | * If rm is denoting a register, no more instruction bytes.
|
---|
6426 | */
|
---|
6427 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
6428 | {
|
---|
6429 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6430 | if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
|
---|
6431 | {
|
---|
6432 | IEM_MC_BEGIN(0, 1);
|
---|
6433 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
6434 | IEM_MC_FETCH_GREG_U16_SX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6435 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
6436 | IEM_MC_ADVANCE_RIP();
|
---|
6437 | IEM_MC_END();
|
---|
6438 | }
|
---|
6439 | else
|
---|
6440 | {
|
---|
6441 | IEM_MC_BEGIN(0, 1);
|
---|
6442 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
6443 | IEM_MC_FETCH_GREG_U16_SX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6444 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
6445 | IEM_MC_ADVANCE_RIP();
|
---|
6446 | IEM_MC_END();
|
---|
6447 | }
|
---|
6448 | }
|
---|
6449 | else
|
---|
6450 | {
|
---|
6451 | /*
|
---|
6452 | * We're loading a register from memory.
|
---|
6453 | */
|
---|
6454 | if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
|
---|
6455 | {
|
---|
6456 | IEM_MC_BEGIN(0, 2);
|
---|
6457 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
6458 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6459 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6460 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6461 | IEM_MC_FETCH_MEM_U16_SX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6462 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
6463 | IEM_MC_ADVANCE_RIP();
|
---|
6464 | IEM_MC_END();
|
---|
6465 | }
|
---|
6466 | else
|
---|
6467 | {
|
---|
6468 | IEM_MC_BEGIN(0, 2);
|
---|
6469 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
6470 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6471 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6472 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6473 | IEM_MC_FETCH_MEM_U16_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
6474 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
6475 | IEM_MC_ADVANCE_RIP();
|
---|
6476 | IEM_MC_END();
|
---|
6477 | }
|
---|
6478 | }
|
---|
6479 | return VINF_SUCCESS;
|
---|
6480 | }
|
---|
6481 |
|
---|
6482 |
|
---|
6483 | /** Opcode 0x0f 0xc0. */
|
---|
6484 | FNIEMOP_DEF(iemOp_xadd_Eb_Gb)
|
---|
6485 | {
|
---|
6486 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
6487 | IEMOP_HLP_MIN_486();
|
---|
6488 | IEMOP_MNEMONIC("xadd Eb,Gb");
|
---|
6489 |
|
---|
6490 | /*
|
---|
6491 | * If rm is denoting a register, no more instruction bytes.
|
---|
6492 | */
|
---|
6493 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
6494 | {
|
---|
6495 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6496 |
|
---|
6497 | IEM_MC_BEGIN(3, 0);
|
---|
6498 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
6499 | IEM_MC_ARG(uint8_t *, pu8Reg, 1);
|
---|
6500 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
6501 |
|
---|
6502 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6503 | IEM_MC_REF_GREG_U8(pu8Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6504 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
6505 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8, pu8Dst, pu8Reg, pEFlags);
|
---|
6506 |
|
---|
6507 | IEM_MC_ADVANCE_RIP();
|
---|
6508 | IEM_MC_END();
|
---|
6509 | }
|
---|
6510 | else
|
---|
6511 | {
|
---|
6512 | /*
|
---|
6513 | * We're accessing memory.
|
---|
6514 | */
|
---|
6515 | IEM_MC_BEGIN(3, 3);
|
---|
6516 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
6517 | IEM_MC_ARG(uint8_t *, pu8Reg, 1);
|
---|
6518 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
6519 | IEM_MC_LOCAL(uint8_t, u8RegCopy);
|
---|
6520 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6521 |
|
---|
6522 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6523 | IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
6524 | IEM_MC_FETCH_GREG_U8(u8RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6525 | IEM_MC_REF_LOCAL(pu8Reg, u8RegCopy);
|
---|
6526 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
6527 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
6528 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8, pu8Dst, pu8Reg, pEFlags);
|
---|
6529 | else
|
---|
6530 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8_locked, pu8Dst, pu8Reg, pEFlags);
|
---|
6531 |
|
---|
6532 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
|
---|
6533 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
6534 | IEM_MC_STORE_GREG_U8(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u8RegCopy);
|
---|
6535 | IEM_MC_ADVANCE_RIP();
|
---|
6536 | IEM_MC_END();
|
---|
6537 | return VINF_SUCCESS;
|
---|
6538 | }
|
---|
6539 | return VINF_SUCCESS;
|
---|
6540 | }
|
---|
6541 |
|
---|
6542 |
|
---|
6543 | /** Opcode 0x0f 0xc1. */
|
---|
6544 | FNIEMOP_DEF(iemOp_xadd_Ev_Gv)
|
---|
6545 | {
|
---|
6546 | IEMOP_MNEMONIC("xadd Ev,Gv");
|
---|
6547 | IEMOP_HLP_MIN_486();
|
---|
6548 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
6549 |
|
---|
6550 | /*
|
---|
6551 | * If rm is denoting a register, no more instruction bytes.
|
---|
6552 | */
|
---|
6553 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
6554 | {
|
---|
6555 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6556 |
|
---|
6557 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
6558 | {
|
---|
6559 | case IEMMODE_16BIT:
|
---|
6560 | IEM_MC_BEGIN(3, 0);
|
---|
6561 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
6562 | IEM_MC_ARG(uint16_t *, pu16Reg, 1);
|
---|
6563 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
6564 |
|
---|
6565 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6566 | IEM_MC_REF_GREG_U16(pu16Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6567 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
6568 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16, pu16Dst, pu16Reg, pEFlags);
|
---|
6569 |
|
---|
6570 | IEM_MC_ADVANCE_RIP();
|
---|
6571 | IEM_MC_END();
|
---|
6572 | return VINF_SUCCESS;
|
---|
6573 |
|
---|
6574 | case IEMMODE_32BIT:
|
---|
6575 | IEM_MC_BEGIN(3, 0);
|
---|
6576 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
6577 | IEM_MC_ARG(uint32_t *, pu32Reg, 1);
|
---|
6578 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
6579 |
|
---|
6580 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6581 | IEM_MC_REF_GREG_U32(pu32Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6582 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
6583 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32, pu32Dst, pu32Reg, pEFlags);
|
---|
6584 |
|
---|
6585 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
6586 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Reg);
|
---|
6587 | IEM_MC_ADVANCE_RIP();
|
---|
6588 | IEM_MC_END();
|
---|
6589 | return VINF_SUCCESS;
|
---|
6590 |
|
---|
6591 | case IEMMODE_64BIT:
|
---|
6592 | IEM_MC_BEGIN(3, 0);
|
---|
6593 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
6594 | IEM_MC_ARG(uint64_t *, pu64Reg, 1);
|
---|
6595 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
6596 |
|
---|
6597 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
6598 | IEM_MC_REF_GREG_U64(pu64Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6599 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
6600 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64, pu64Dst, pu64Reg, pEFlags);
|
---|
6601 |
|
---|
6602 | IEM_MC_ADVANCE_RIP();
|
---|
6603 | IEM_MC_END();
|
---|
6604 | return VINF_SUCCESS;
|
---|
6605 |
|
---|
6606 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6607 | }
|
---|
6608 | }
|
---|
6609 | else
|
---|
6610 | {
|
---|
6611 | /*
|
---|
6612 | * We're accessing memory.
|
---|
6613 | */
|
---|
6614 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
6615 | {
|
---|
6616 | case IEMMODE_16BIT:
|
---|
6617 | IEM_MC_BEGIN(3, 3);
|
---|
6618 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
6619 | IEM_MC_ARG(uint16_t *, pu16Reg, 1);
|
---|
6620 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
6621 | IEM_MC_LOCAL(uint16_t, u16RegCopy);
|
---|
6622 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6623 |
|
---|
6624 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6625 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
6626 | IEM_MC_FETCH_GREG_U16(u16RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6627 | IEM_MC_REF_LOCAL(pu16Reg, u16RegCopy);
|
---|
6628 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
6629 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
6630 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16, pu16Dst, pu16Reg, pEFlags);
|
---|
6631 | else
|
---|
6632 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16_locked, pu16Dst, pu16Reg, pEFlags);
|
---|
6633 |
|
---|
6634 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
6635 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
6636 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16RegCopy);
|
---|
6637 | IEM_MC_ADVANCE_RIP();
|
---|
6638 | IEM_MC_END();
|
---|
6639 | return VINF_SUCCESS;
|
---|
6640 |
|
---|
6641 | case IEMMODE_32BIT:
|
---|
6642 | IEM_MC_BEGIN(3, 3);
|
---|
6643 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
6644 | IEM_MC_ARG(uint32_t *, pu32Reg, 1);
|
---|
6645 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
6646 | IEM_MC_LOCAL(uint32_t, u32RegCopy);
|
---|
6647 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6648 |
|
---|
6649 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6650 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
6651 | IEM_MC_FETCH_GREG_U32(u32RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6652 | IEM_MC_REF_LOCAL(pu32Reg, u32RegCopy);
|
---|
6653 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
6654 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
6655 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32, pu32Dst, pu32Reg, pEFlags);
|
---|
6656 | else
|
---|
6657 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32_locked, pu32Dst, pu32Reg, pEFlags);
|
---|
6658 |
|
---|
6659 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
6660 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
6661 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32RegCopy);
|
---|
6662 | IEM_MC_ADVANCE_RIP();
|
---|
6663 | IEM_MC_END();
|
---|
6664 | return VINF_SUCCESS;
|
---|
6665 |
|
---|
6666 | case IEMMODE_64BIT:
|
---|
6667 | IEM_MC_BEGIN(3, 3);
|
---|
6668 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
6669 | IEM_MC_ARG(uint64_t *, pu64Reg, 1);
|
---|
6670 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
6671 | IEM_MC_LOCAL(uint64_t, u64RegCopy);
|
---|
6672 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6673 |
|
---|
6674 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6675 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
6676 | IEM_MC_FETCH_GREG_U64(u64RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6677 | IEM_MC_REF_LOCAL(pu64Reg, u64RegCopy);
|
---|
6678 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
6679 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
6680 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64, pu64Dst, pu64Reg, pEFlags);
|
---|
6681 | else
|
---|
6682 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64_locked, pu64Dst, pu64Reg, pEFlags);
|
---|
6683 |
|
---|
6684 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
6685 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
6686 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64RegCopy);
|
---|
6687 | IEM_MC_ADVANCE_RIP();
|
---|
6688 | IEM_MC_END();
|
---|
6689 | return VINF_SUCCESS;
|
---|
6690 |
|
---|
6691 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6692 | }
|
---|
6693 | }
|
---|
6694 | }
|
---|
6695 |
|
---|
6696 | /** Opcode 0x0f 0xc2. */
|
---|
6697 | FNIEMOP_STUB(iemOp_cmpps_Vps_Wps_Ib__cmppd_Vpd_Wpd_Ib__cmpss_Vss_Wss_Ib__cmpsd_Vsd_Wsd_Ib);
|
---|
6698 |
|
---|
6699 |
|
---|
6700 | /** Opcode 0x0f 0xc3. */
|
---|
6701 | FNIEMOP_DEF(iemOp_movnti_My_Gy)
|
---|
6702 | {
|
---|
6703 | IEMOP_MNEMONIC("movnti My,Gy");
|
---|
6704 |
|
---|
6705 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
6706 |
|
---|
6707 | /* Only the register -> memory form makes sense, assuming #UD for the other form. */
|
---|
6708 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
6709 | {
|
---|
6710 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
6711 | {
|
---|
6712 | case IEMMODE_32BIT:
|
---|
6713 | IEM_MC_BEGIN(0, 2);
|
---|
6714 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
6715 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6716 |
|
---|
6717 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6718 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6719 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
|
---|
6720 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6721 |
|
---|
6722 | IEM_MC_FETCH_GREG_U32(u32Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6723 | IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value);
|
---|
6724 | IEM_MC_ADVANCE_RIP();
|
---|
6725 | IEM_MC_END();
|
---|
6726 | break;
|
---|
6727 |
|
---|
6728 | case IEMMODE_64BIT:
|
---|
6729 | IEM_MC_BEGIN(0, 2);
|
---|
6730 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
6731 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6732 |
|
---|
6733 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6734 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6735 | if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
|
---|
6736 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6737 |
|
---|
6738 | IEM_MC_FETCH_GREG_U64(u64Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
6739 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value);
|
---|
6740 | IEM_MC_ADVANCE_RIP();
|
---|
6741 | IEM_MC_END();
|
---|
6742 | break;
|
---|
6743 |
|
---|
6744 | case IEMMODE_16BIT:
|
---|
6745 | /** @todo check this form. */
|
---|
6746 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6747 | }
|
---|
6748 | }
|
---|
6749 | else
|
---|
6750 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6751 | return VINF_SUCCESS;
|
---|
6752 | }
|
---|
6753 |
|
---|
6754 |
|
---|
6755 | /** Opcode 0x0f 0xc4. */
|
---|
6756 | FNIEMOP_STUB(iemOp_pinsrw_Pq_Ry_Mw_Ib__pinsrw_Vdq_Ry_Mw_Ib);
|
---|
6757 |
|
---|
6758 | /** Opcode 0x0f 0xc5. */
|
---|
6759 | FNIEMOP_STUB(iemOp_pextrw_Gd_Nq_Ib__pextrw_Gd_Udq_Ib);
|
---|
6760 |
|
---|
6761 | /** Opcode 0x0f 0xc6. */
|
---|
6762 | FNIEMOP_STUB(iemOp_shufps_Vps_Wps_Ib__shufdp_Vpd_Wpd_Ib);
|
---|
6763 |
|
---|
6764 |
|
---|
6765 | /** Opcode 0x0f 0xc7 !11/1. */
|
---|
6766 | FNIEMOP_DEF_1(iemOp_Grp9_cmpxchg8b_Mq, uint8_t, bRm)
|
---|
6767 | {
|
---|
6768 | IEMOP_MNEMONIC("cmpxchg8b Mq");
|
---|
6769 |
|
---|
6770 | IEM_MC_BEGIN(4, 3);
|
---|
6771 | IEM_MC_ARG(uint64_t *, pu64MemDst, 0);
|
---|
6772 | IEM_MC_ARG(PRTUINT64U, pu64EaxEdx, 1);
|
---|
6773 | IEM_MC_ARG(PRTUINT64U, pu64EbxEcx, 2);
|
---|
6774 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 3);
|
---|
6775 | IEM_MC_LOCAL(RTUINT64U, u64EaxEdx);
|
---|
6776 | IEM_MC_LOCAL(RTUINT64U, u64EbxEcx);
|
---|
6777 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
6778 |
|
---|
6779 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
6780 | IEMOP_HLP_DONE_DECODING();
|
---|
6781 | IEM_MC_MEM_MAP(pu64MemDst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
6782 |
|
---|
6783 | IEM_MC_FETCH_GREG_U32(u64EaxEdx.s.Lo, X86_GREG_xAX);
|
---|
6784 | IEM_MC_FETCH_GREG_U32(u64EaxEdx.s.Hi, X86_GREG_xDX);
|
---|
6785 | IEM_MC_REF_LOCAL(pu64EaxEdx, u64EaxEdx);
|
---|
6786 |
|
---|
6787 | IEM_MC_FETCH_GREG_U32(u64EbxEcx.s.Lo, X86_GREG_xBX);
|
---|
6788 | IEM_MC_FETCH_GREG_U32(u64EbxEcx.s.Hi, X86_GREG_xCX);
|
---|
6789 | IEM_MC_REF_LOCAL(pu64EbxEcx, u64EbxEcx);
|
---|
6790 |
|
---|
6791 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
6792 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
6793 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg8b, pu64MemDst, pu64EaxEdx, pu64EbxEcx, pEFlags);
|
---|
6794 | else
|
---|
6795 | IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg8b_locked, pu64MemDst, pu64EaxEdx, pu64EbxEcx, pEFlags);
|
---|
6796 |
|
---|
6797 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64MemDst, IEM_ACCESS_DATA_RW);
|
---|
6798 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
6799 | IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF)
|
---|
6800 | /** @todo Testcase: Check effect of cmpxchg8b on bits 63:32 in rax and rdx. */
|
---|
6801 | IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u64EaxEdx.s.Lo);
|
---|
6802 | IEM_MC_STORE_GREG_U32(X86_GREG_xDX, u64EaxEdx.s.Hi);
|
---|
6803 | IEM_MC_ENDIF();
|
---|
6804 | IEM_MC_ADVANCE_RIP();
|
---|
6805 |
|
---|
6806 | IEM_MC_END();
|
---|
6807 | return VINF_SUCCESS;
|
---|
6808 | }
|
---|
6809 |
|
---|
6810 |
|
---|
6811 | /** Opcode REX.W 0x0f 0xc7 !11/1. */
|
---|
6812 | FNIEMOP_UD_STUB_1(iemOp_Grp9_cmpxchg16b_Mdq, uint8_t, bRm);
|
---|
6813 |
|
---|
6814 | /** Opcode 0x0f 0xc7 11/6. */
|
---|
6815 | FNIEMOP_UD_STUB_1(iemOp_Grp9_rdrand_Rv, uint8_t, bRm);
|
---|
6816 |
|
---|
6817 | /** Opcode 0x0f 0xc7 !11/6. */
|
---|
6818 | FNIEMOP_UD_STUB_1(iemOp_Grp9_vmptrld_Mq, uint8_t, bRm);
|
---|
6819 |
|
---|
6820 | /** Opcode 0x66 0x0f 0xc7 !11/6. */
|
---|
6821 | FNIEMOP_UD_STUB_1(iemOp_Grp9_vmclear_Mq, uint8_t, bRm);
|
---|
6822 |
|
---|
6823 | /** Opcode 0xf3 0x0f 0xc7 !11/6. */
|
---|
6824 | FNIEMOP_UD_STUB_1(iemOp_Grp9_vmxon_Mq, uint8_t, bRm);
|
---|
6825 |
|
---|
6826 | /** Opcode [0xf3] 0x0f 0xc7 !11/7. */
|
---|
6827 | FNIEMOP_UD_STUB_1(iemOp_Grp9_vmptrst_Mq, uint8_t, bRm);
|
---|
6828 |
|
---|
6829 |
|
---|
6830 | /** Opcode 0x0f 0xc7. */
|
---|
6831 | FNIEMOP_DEF(iemOp_Grp9)
|
---|
6832 | {
|
---|
6833 | /** @todo Testcase: Check mixing 0x66 and 0xf3. Check the effect of 0xf2. */
|
---|
6834 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
6835 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
6836 | {
|
---|
6837 | case 0: case 2: case 3: case 4: case 5:
|
---|
6838 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6839 | case 1:
|
---|
6840 | /** @todo Testcase: Check prefix effects on cmpxchg8b/16b. */
|
---|
6841 | if ( (bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)
|
---|
6842 | || (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ))) /** @todo Testcase: AMD seems to express a different idea here wrt prefixes. */
|
---|
6843 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6844 | if (bRm & IEM_OP_PRF_SIZE_REX_W)
|
---|
6845 | return FNIEMOP_CALL_1(iemOp_Grp9_cmpxchg16b_Mdq, bRm);
|
---|
6846 | return FNIEMOP_CALL_1(iemOp_Grp9_cmpxchg8b_Mq, bRm);
|
---|
6847 | case 6:
|
---|
6848 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
6849 | return FNIEMOP_CALL_1(iemOp_Grp9_rdrand_Rv, bRm);
|
---|
6850 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ))
|
---|
6851 | {
|
---|
6852 | case 0:
|
---|
6853 | return FNIEMOP_CALL_1(iemOp_Grp9_vmptrld_Mq, bRm);
|
---|
6854 | case IEM_OP_PRF_SIZE_OP:
|
---|
6855 | return FNIEMOP_CALL_1(iemOp_Grp9_vmclear_Mq, bRm);
|
---|
6856 | case IEM_OP_PRF_REPZ:
|
---|
6857 | return FNIEMOP_CALL_1(iemOp_Grp9_vmxon_Mq, bRm);
|
---|
6858 | default:
|
---|
6859 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6860 | }
|
---|
6861 | case 7:
|
---|
6862 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ))
|
---|
6863 | {
|
---|
6864 | case 0:
|
---|
6865 | case IEM_OP_PRF_REPZ:
|
---|
6866 | return FNIEMOP_CALL_1(iemOp_Grp9_vmptrst_Mq, bRm);
|
---|
6867 | default:
|
---|
6868 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
6869 | }
|
---|
6870 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6871 | }
|
---|
6872 | }
|
---|
6873 |
|
---|
6874 |
|
---|
6875 | /**
|
---|
6876 | * Common 'bswap register' helper.
|
---|
6877 | */
|
---|
6878 | FNIEMOP_DEF_1(iemOpCommonBswapGReg, uint8_t, iReg)
|
---|
6879 | {
|
---|
6880 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
6881 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
6882 | {
|
---|
6883 | case IEMMODE_16BIT:
|
---|
6884 | IEM_MC_BEGIN(1, 0);
|
---|
6885 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
6886 | IEM_MC_REF_GREG_U32(pu32Dst, iReg); /* Don't clear the high dword! */
|
---|
6887 | IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u16, pu32Dst);
|
---|
6888 | IEM_MC_ADVANCE_RIP();
|
---|
6889 | IEM_MC_END();
|
---|
6890 | return VINF_SUCCESS;
|
---|
6891 |
|
---|
6892 | case IEMMODE_32BIT:
|
---|
6893 | IEM_MC_BEGIN(1, 0);
|
---|
6894 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
6895 | IEM_MC_REF_GREG_U32(pu32Dst, iReg);
|
---|
6896 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
6897 | IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u32, pu32Dst);
|
---|
6898 | IEM_MC_ADVANCE_RIP();
|
---|
6899 | IEM_MC_END();
|
---|
6900 | return VINF_SUCCESS;
|
---|
6901 |
|
---|
6902 | case IEMMODE_64BIT:
|
---|
6903 | IEM_MC_BEGIN(1, 0);
|
---|
6904 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
6905 | IEM_MC_REF_GREG_U64(pu64Dst, iReg);
|
---|
6906 | IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u64, pu64Dst);
|
---|
6907 | IEM_MC_ADVANCE_RIP();
|
---|
6908 | IEM_MC_END();
|
---|
6909 | return VINF_SUCCESS;
|
---|
6910 |
|
---|
6911 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
6912 | }
|
---|
6913 | }
|
---|
6914 |
|
---|
6915 |
|
---|
6916 | /** Opcode 0x0f 0xc8. */
|
---|
6917 | FNIEMOP_DEF(iemOp_bswap_rAX_r8)
|
---|
6918 | {
|
---|
6919 | IEMOP_MNEMONIC("bswap rAX/r8");
|
---|
6920 | /* Note! Intel manuals states that R8-R15 can be accessed by using a REX.X
|
---|
6921 | prefix. REX.B is the correct prefix it appears. For a parallel
|
---|
6922 | case, see iemOp_mov_AL_Ib and iemOp_mov_eAX_Iv. */
|
---|
6923 | IEMOP_HLP_MIN_486();
|
---|
6924 | return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xAX | pVCpu->iem.s.uRexB);
|
---|
6925 | }
|
---|
6926 |
|
---|
6927 |
|
---|
6928 | /** Opcode 0x0f 0xc9. */
|
---|
6929 | FNIEMOP_DEF(iemOp_bswap_rCX_r9)
|
---|
6930 | {
|
---|
6931 | IEMOP_MNEMONIC("bswap rCX/r9");
|
---|
6932 | IEMOP_HLP_MIN_486();
|
---|
6933 | return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xCX | pVCpu->iem.s.uRexB);
|
---|
6934 | }
|
---|
6935 |
|
---|
6936 |
|
---|
6937 | /** Opcode 0x0f 0xca. */
|
---|
6938 | FNIEMOP_DEF(iemOp_bswap_rDX_r10)
|
---|
6939 | {
|
---|
6940 | IEMOP_MNEMONIC("bswap rDX/r9");
|
---|
6941 | IEMOP_HLP_MIN_486();
|
---|
6942 | return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xDX | pVCpu->iem.s.uRexB);
|
---|
6943 | }
|
---|
6944 |
|
---|
6945 |
|
---|
6946 | /** Opcode 0x0f 0xcb. */
|
---|
6947 | FNIEMOP_DEF(iemOp_bswap_rBX_r11)
|
---|
6948 | {
|
---|
6949 | IEMOP_MNEMONIC("bswap rBX/r9");
|
---|
6950 | IEMOP_HLP_MIN_486();
|
---|
6951 | return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xBX | pVCpu->iem.s.uRexB);
|
---|
6952 | }
|
---|
6953 |
|
---|
6954 |
|
---|
6955 | /** Opcode 0x0f 0xcc. */
|
---|
6956 | FNIEMOP_DEF(iemOp_bswap_rSP_r12)
|
---|
6957 | {
|
---|
6958 | IEMOP_MNEMONIC("bswap rSP/r12");
|
---|
6959 | IEMOP_HLP_MIN_486();
|
---|
6960 | return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xSP | pVCpu->iem.s.uRexB);
|
---|
6961 | }
|
---|
6962 |
|
---|
6963 |
|
---|
6964 | /** Opcode 0x0f 0xcd. */
|
---|
6965 | FNIEMOP_DEF(iemOp_bswap_rBP_r13)
|
---|
6966 | {
|
---|
6967 | IEMOP_MNEMONIC("bswap rBP/r13");
|
---|
6968 | IEMOP_HLP_MIN_486();
|
---|
6969 | return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xBP | pVCpu->iem.s.uRexB);
|
---|
6970 | }
|
---|
6971 |
|
---|
6972 |
|
---|
6973 | /** Opcode 0x0f 0xce. */
|
---|
6974 | FNIEMOP_DEF(iemOp_bswap_rSI_r14)
|
---|
6975 | {
|
---|
6976 | IEMOP_MNEMONIC("bswap rSI/r14");
|
---|
6977 | IEMOP_HLP_MIN_486();
|
---|
6978 | return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xSI | pVCpu->iem.s.uRexB);
|
---|
6979 | }
|
---|
6980 |
|
---|
6981 |
|
---|
6982 | /** Opcode 0x0f 0xcf. */
|
---|
6983 | FNIEMOP_DEF(iemOp_bswap_rDI_r15)
|
---|
6984 | {
|
---|
6985 | IEMOP_MNEMONIC("bswap rDI/r15");
|
---|
6986 | IEMOP_HLP_MIN_486();
|
---|
6987 | return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xDI | pVCpu->iem.s.uRexB);
|
---|
6988 | }
|
---|
6989 |
|
---|
6990 |
|
---|
6991 |
|
---|
6992 | /** Opcode 0x0f 0xd0. */
|
---|
6993 | FNIEMOP_STUB(iemOp_addsubpd_Vpd_Wpd__addsubps_Vps_Wps);
|
---|
6994 | /** Opcode 0x0f 0xd1. */
|
---|
6995 | FNIEMOP_STUB(iemOp_psrlw_Pp_Qp__psrlw_Vdp_Wdq);
|
---|
6996 | /** Opcode 0x0f 0xd2. */
|
---|
6997 | FNIEMOP_STUB(iemOp_psrld_Pq_Qq__psrld_Vdq_Wdq);
|
---|
6998 | /** Opcode 0x0f 0xd3. */
|
---|
6999 | FNIEMOP_STUB(iemOp_psrlq_Pq_Qq__psrlq_Vdq_Wdq);
|
---|
7000 | /** Opcode 0x0f 0xd4. */
|
---|
7001 | FNIEMOP_STUB(iemOp_paddq_Pq_Qq__paddq_Vdq_Wdq);
|
---|
7002 | /** Opcode 0x0f 0xd5. */
|
---|
7003 | FNIEMOP_STUB(iemOp_pmulq_Pq_Qq__pmullw_Vdq_Wdq);
|
---|
7004 | /** Opcode 0x0f 0xd6. */
|
---|
7005 | FNIEMOP_STUB(iemOp_movq_Wq_Vq__movq2dq_Vdq_Nq__movdq2q_Pq_Uq);
|
---|
7006 |
|
---|
7007 |
|
---|
7008 | /** Opcode 0x0f 0xd7. */
|
---|
7009 | FNIEMOP_DEF(iemOp_pmovmskb_Gd_Nq__pmovmskb_Gd_Udq)
|
---|
7010 | {
|
---|
7011 | /* Docs says register only. */
|
---|
7012 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
7013 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)) /** @todo test that this is registers only. */
|
---|
7014 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
7015 |
|
---|
7016 | /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
|
---|
7017 | /** @todo testcase: Check that the instruction implicitly clears the high
|
---|
7018 | * bits in 64-bit mode. The REX.W is first necessary when VLMAX > 256
|
---|
7019 | * and opcode modifications are made to work with the whole width (not
|
---|
7020 | * just 128). */
|
---|
7021 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
7022 | {
|
---|
7023 | case IEM_OP_PRF_SIZE_OP: /* SSE */
|
---|
7024 | IEMOP_MNEMONIC("pmovmskb Gd,Nq");
|
---|
7025 | IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_SSE | DISOPTYPE_HARMLESS);
|
---|
7026 | IEM_MC_BEGIN(2, 0);
|
---|
7027 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
7028 | IEM_MC_ARG(uint128_t const *, pSrc, 1);
|
---|
7029 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
7030 | IEM_MC_PREPARE_SSE_USAGE();
|
---|
7031 | IEM_MC_REF_GREG_U64(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
7032 | IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
7033 | IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_pmovmskb_u128, pDst, pSrc);
|
---|
7034 | IEM_MC_ADVANCE_RIP();
|
---|
7035 | IEM_MC_END();
|
---|
7036 | return VINF_SUCCESS;
|
---|
7037 |
|
---|
7038 | case 0: /* MMX */
|
---|
7039 | IEMOP_MNEMONIC("pmovmskb Gd,Udq");
|
---|
7040 | IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_MMX | DISOPTYPE_HARMLESS);
|
---|
7041 | IEM_MC_BEGIN(2, 0);
|
---|
7042 | IEM_MC_ARG(uint64_t *, pDst, 0);
|
---|
7043 | IEM_MC_ARG(uint64_t const *, pSrc, 1);
|
---|
7044 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
|
---|
7045 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
7046 | IEM_MC_REF_GREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
7047 | IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
|
---|
7048 | IEM_MC_CALL_MMX_AIMPL_2(iemAImpl_pmovmskb_u64, pDst, pSrc);
|
---|
7049 | IEM_MC_ADVANCE_RIP();
|
---|
7050 | IEM_MC_END();
|
---|
7051 | return VINF_SUCCESS;
|
---|
7052 |
|
---|
7053 | default:
|
---|
7054 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
7055 | }
|
---|
7056 | }
|
---|
7057 |
|
---|
7058 |
|
---|
7059 | /** Opcode 0x0f 0xd8. */
|
---|
7060 | FNIEMOP_STUB(iemOp_psubusb_Pq_Qq__psubusb_Vdq_Wdq);
|
---|
7061 | /** Opcode 0x0f 0xd9. */
|
---|
7062 | FNIEMOP_STUB(iemOp_psubusw_Pq_Qq__psubusw_Vdq_Wdq);
|
---|
7063 | /** Opcode 0x0f 0xda. */
|
---|
7064 | FNIEMOP_STUB(iemOp_pminub_Pq_Qq__pminub_Vdq_Wdq);
|
---|
7065 | /** Opcode 0x0f 0xdb. */
|
---|
7066 | FNIEMOP_STUB(iemOp_pand_Pq_Qq__pand_Vdq_Wdq);
|
---|
7067 | /** Opcode 0x0f 0xdc. */
|
---|
7068 | FNIEMOP_STUB(iemOp_paddusb_Pq_Qq__paddusb_Vdq_Wdq);
|
---|
7069 | /** Opcode 0x0f 0xdd. */
|
---|
7070 | FNIEMOP_STUB(iemOp_paddusw_Pq_Qq__paddusw_Vdq_Wdq);
|
---|
7071 | /** Opcode 0x0f 0xde. */
|
---|
7072 | FNIEMOP_STUB(iemOp_pmaxub_Pq_Qq__pamxub_Vdq_Wdq);
|
---|
7073 | /** Opcode 0x0f 0xdf. */
|
---|
7074 | FNIEMOP_STUB(iemOp_pandn_Pq_Qq__pandn_Vdq_Wdq);
|
---|
7075 | /** Opcode 0x0f 0xe0. */
|
---|
7076 | FNIEMOP_STUB(iemOp_pavgb_Pq_Qq__pavgb_Vdq_Wdq);
|
---|
7077 | /** Opcode 0x0f 0xe1. */
|
---|
7078 | FNIEMOP_STUB(iemOp_psraw_Pq_Qq__psraw_Vdq_Wdq);
|
---|
7079 | /** Opcode 0x0f 0xe2. */
|
---|
7080 | FNIEMOP_STUB(iemOp_psrad_Pq_Qq__psrad_Vdq_Wdq);
|
---|
7081 | /** Opcode 0x0f 0xe3. */
|
---|
7082 | FNIEMOP_STUB(iemOp_pavgw_Pq_Qq__pavgw_Vdq_Wdq);
|
---|
7083 | /** Opcode 0x0f 0xe4. */
|
---|
7084 | FNIEMOP_STUB(iemOp_pmulhuw_Pq_Qq__pmulhuw_Vdq_Wdq);
|
---|
7085 | /** Opcode 0x0f 0xe5. */
|
---|
7086 | FNIEMOP_STUB(iemOp_pmulhw_Pq_Qq__pmulhw_Vdq_Wdq);
|
---|
7087 | /** Opcode 0x0f 0xe6. */
|
---|
7088 | FNIEMOP_STUB(iemOp_cvttpd2dq_Vdq_Wdp__cvtdq2pd_Vdq_Wpd__cvtpd2dq_Vdq_Wpd);
|
---|
7089 |
|
---|
7090 |
|
---|
7091 | /** Opcode 0x0f 0xe7. */
|
---|
7092 | FNIEMOP_DEF(iemOp_movntq_Mq_Pq__movntdq_Mdq_Vdq)
|
---|
7093 | {
|
---|
7094 | IEMOP_MNEMONIC(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP) ? "movntq mr,r" : "movntdq mr,r");
|
---|
7095 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
7096 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
7097 | {
|
---|
7098 | /*
|
---|
7099 | * Register, memory.
|
---|
7100 | */
|
---|
7101 | /** @todo check when the REPNZ/Z bits kick in. Same as lock, probably... */
|
---|
7102 | switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
7103 | {
|
---|
7104 |
|
---|
7105 | case IEM_OP_PRF_SIZE_OP: /* SSE */
|
---|
7106 | IEM_MC_BEGIN(0, 2);
|
---|
7107 | IEM_MC_LOCAL(uint128_t, uSrc);
|
---|
7108 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
7109 |
|
---|
7110 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
7111 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
7112 | IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
|
---|
7113 | IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
|
---|
7114 |
|
---|
7115 | IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
7116 | IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
|
---|
7117 |
|
---|
7118 | IEM_MC_ADVANCE_RIP();
|
---|
7119 | IEM_MC_END();
|
---|
7120 | break;
|
---|
7121 |
|
---|
7122 | case 0: /* MMX */
|
---|
7123 | IEM_MC_BEGIN(0, 2);
|
---|
7124 | IEM_MC_LOCAL(uint64_t, uSrc);
|
---|
7125 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
7126 |
|
---|
7127 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
7128 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
7129 | IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
|
---|
7130 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
7131 |
|
---|
7132 | IEM_MC_FETCH_MREG_U64(uSrc, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
7133 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
|
---|
7134 |
|
---|
7135 | IEM_MC_ADVANCE_RIP();
|
---|
7136 | IEM_MC_END();
|
---|
7137 | break;
|
---|
7138 |
|
---|
7139 | default:
|
---|
7140 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
7141 | }
|
---|
7142 | }
|
---|
7143 | /* The register, register encoding is invalid. */
|
---|
7144 | else
|
---|
7145 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
7146 | return VINF_SUCCESS;
|
---|
7147 | }
|
---|
7148 |
|
---|
7149 |
|
---|
7150 | /** Opcode 0x0f 0xe8. */
|
---|
7151 | FNIEMOP_STUB(iemOp_psubsb_Pq_Qq__psubsb_Vdq_Wdq);
|
---|
7152 | /** Opcode 0x0f 0xe9. */
|
---|
7153 | FNIEMOP_STUB(iemOp_psubsw_Pq_Qq__psubsw_Vdq_Wdq);
|
---|
7154 | /** Opcode 0x0f 0xea. */
|
---|
7155 | FNIEMOP_STUB(iemOp_pminsw_Pq_Qq__pminsw_Vdq_Wdq);
|
---|
7156 | /** Opcode 0x0f 0xeb. */
|
---|
7157 | FNIEMOP_STUB(iemOp_por_Pq_Qq__por_Vdq_Wdq);
|
---|
7158 | /** Opcode 0x0f 0xec. */
|
---|
7159 | FNIEMOP_STUB(iemOp_paddsb_Pq_Qq__paddsb_Vdq_Wdq);
|
---|
7160 | /** Opcode 0x0f 0xed. */
|
---|
7161 | FNIEMOP_STUB(iemOp_paddsw_Pq_Qq__paddsw_Vdq_Wdq);
|
---|
7162 | /** Opcode 0x0f 0xee. */
|
---|
7163 | FNIEMOP_STUB(iemOp_pmaxsw_Pq_Qq__pmaxsw_Vdq_Wdq);
|
---|
7164 |
|
---|
7165 |
|
---|
7166 | /** Opcode 0x0f 0xef. */
|
---|
7167 | FNIEMOP_DEF(iemOp_pxor_Pq_Qq__pxor_Vdq_Wdq)
|
---|
7168 | {
|
---|
7169 | IEMOP_MNEMONIC("pxor");
|
---|
7170 | return FNIEMOP_CALL_1(iemOpCommonMmxSse2_FullFull_To_Full, &g_iemAImpl_pxor);
|
---|
7171 | }
|
---|
7172 |
|
---|
7173 |
|
---|
7174 | /** Opcode 0x0f 0xf0. */
|
---|
7175 | FNIEMOP_STUB(iemOp_lddqu_Vdq_Mdq);
|
---|
7176 | /** Opcode 0x0f 0xf1. */
|
---|
7177 | FNIEMOP_STUB(iemOp_psllw_Pq_Qq__pslw_Vdq_Wdq);
|
---|
7178 | /** Opcode 0x0f 0xf2. */
|
---|
7179 | FNIEMOP_STUB(iemOp_psld_Pq_Qq__pslld_Vdq_Wdq);
|
---|
7180 | /** Opcode 0x0f 0xf3. */
|
---|
7181 | FNIEMOP_STUB(iemOp_psllq_Pq_Qq__pslq_Vdq_Wdq);
|
---|
7182 | /** Opcode 0x0f 0xf4. */
|
---|
7183 | FNIEMOP_STUB(iemOp_pmuludq_Pq_Qq__pmuludq_Vdq_Wdq);
|
---|
7184 | /** Opcode 0x0f 0xf5. */
|
---|
7185 | FNIEMOP_STUB(iemOp_pmaddwd_Pq_Qq__pmaddwd_Vdq_Wdq);
|
---|
7186 | /** Opcode 0x0f 0xf6. */
|
---|
7187 | FNIEMOP_STUB(iemOp_psadbw_Pq_Qq__psadbw_Vdq_Wdq);
|
---|
7188 | /** Opcode 0x0f 0xf7. */
|
---|
7189 | FNIEMOP_STUB(iemOp_maskmovq_Pq_Nq__maskmovdqu_Vdq_Udq);
|
---|
7190 | /** Opcode 0x0f 0xf8. */
|
---|
7191 | FNIEMOP_STUB(iemOp_psubb_Pq_Qq_psubb_Vdq_Wdq); //NEXT
|
---|
7192 | /** Opcode 0x0f 0xf9. */
|
---|
7193 | FNIEMOP_STUB(iemOp_psubw_Pq_Qq__psubw_Vdq_Wdq);
|
---|
7194 | /** Opcode 0x0f 0xfa. */
|
---|
7195 | FNIEMOP_STUB(iemOp_psubd_Pq_Qq__psubd_Vdq_Wdq);
|
---|
7196 | /** Opcode 0x0f 0xfb. */
|
---|
7197 | FNIEMOP_STUB(iemOp_psubq_Pq_Qq__psbuq_Vdq_Wdq);
|
---|
7198 | /** Opcode 0x0f 0xfc. */
|
---|
7199 | FNIEMOP_STUB(iemOp_paddb_Pq_Qq__paddb_Vdq_Wdq);
|
---|
7200 | /** Opcode 0x0f 0xfd. */
|
---|
7201 | FNIEMOP_STUB(iemOp_paddw_Pq_Qq__paddw_Vdq_Wdq);
|
---|
7202 | /** Opcode 0x0f 0xfe. */
|
---|
7203 | FNIEMOP_STUB(iemOp_paddd_Pq_Qq__paddd_Vdq_Wdq);
|
---|
7204 |
|
---|
7205 |
|
---|
7206 | IEM_STATIC const PFNIEMOP g_apfnTwoByteMap[256] =
|
---|
7207 | {
|
---|
7208 | /* 0x00 */ iemOp_Grp6,
|
---|
7209 | /* 0x01 */ iemOp_Grp7,
|
---|
7210 | /* 0x02 */ iemOp_lar_Gv_Ew,
|
---|
7211 | /* 0x03 */ iemOp_lsl_Gv_Ew,
|
---|
7212 | /* 0x04 */ iemOp_Invalid,
|
---|
7213 | /* 0x05 */ iemOp_syscall,
|
---|
7214 | /* 0x06 */ iemOp_clts,
|
---|
7215 | /* 0x07 */ iemOp_sysret,
|
---|
7216 | /* 0x08 */ iemOp_invd,
|
---|
7217 | /* 0x09 */ iemOp_wbinvd,
|
---|
7218 | /* 0x0a */ iemOp_Invalid,
|
---|
7219 | /* 0x0b */ iemOp_ud2,
|
---|
7220 | /* 0x0c */ iemOp_Invalid,
|
---|
7221 | /* 0x0d */ iemOp_nop_Ev_GrpP,
|
---|
7222 | /* 0x0e */ iemOp_femms,
|
---|
7223 | /* 0x0f */ iemOp_3Dnow,
|
---|
7224 | /* 0x10 */ iemOp_movups_Vps_Wps__movupd_Vpd_Wpd__movss_Vss_Wss__movsd_Vsd_Wsd,
|
---|
7225 | /* 0x11 */ iemOp_movups_Wps_Vps__movupd_Wpd_Vpd__movss_Wss_Vss__movsd_Vsd_Wsd,
|
---|
7226 | /* 0x12 */ iemOp_movlps_Vq_Mq__movhlps_Vq_Uq__movlpd_Vq_Mq__movsldup_Vq_Wq__movddup_Vq_Wq,
|
---|
7227 | /* 0x13 */ iemOp_movlps_Mq_Vq__movlpd_Mq_Vq,
|
---|
7228 | /* 0x14 */ iemOp_unpckhlps_Vps_Wq__unpcklpd_Vpd_Wq,
|
---|
7229 | /* 0x15 */ iemOp_unpckhps_Vps_Wq__unpckhpd_Vpd_Wq,
|
---|
7230 | /* 0x16 */ iemOp_movhps_Vq_Mq__movlhps_Vq_Uq__movhpd_Vq_Mq__movshdup_Vq_Wq,
|
---|
7231 | /* 0x17 */ iemOp_movhps_Mq_Vq__movhpd_Mq_Vq,
|
---|
7232 | /* 0x18 */ iemOp_prefetch_Grp16,
|
---|
7233 | /* 0x19 */ iemOp_nop_Ev,
|
---|
7234 | /* 0x1a */ iemOp_nop_Ev,
|
---|
7235 | /* 0x1b */ iemOp_nop_Ev,
|
---|
7236 | /* 0x1c */ iemOp_nop_Ev,
|
---|
7237 | /* 0x1d */ iemOp_nop_Ev,
|
---|
7238 | /* 0x1e */ iemOp_nop_Ev,
|
---|
7239 | /* 0x1f */ iemOp_nop_Ev,
|
---|
7240 | /* 0x20 */ iemOp_mov_Rd_Cd,
|
---|
7241 | /* 0x21 */ iemOp_mov_Rd_Dd,
|
---|
7242 | /* 0x22 */ iemOp_mov_Cd_Rd,
|
---|
7243 | /* 0x23 */ iemOp_mov_Dd_Rd,
|
---|
7244 | /* 0x24 */ iemOp_mov_Rd_Td,
|
---|
7245 | /* 0x25 */ iemOp_Invalid,
|
---|
7246 | /* 0x26 */ iemOp_mov_Td_Rd,
|
---|
7247 | /* 0x27 */ iemOp_Invalid,
|
---|
7248 | /* 0x28 */ iemOp_movaps_Vps_Wps__movapd_Vpd_Wpd,
|
---|
7249 | /* 0x29 */ iemOp_movaps_Wps_Vps__movapd_Wpd_Vpd,
|
---|
7250 | /* 0x2a */ iemOp_cvtpi2ps_Vps_Qpi__cvtpi2pd_Vpd_Qpi__cvtsi2ss_Vss_Ey__cvtsi2sd_Vsd_Ey,
|
---|
7251 | /* 0x2b */ iemOp_movntps_Mps_Vps__movntpd_Mpd_Vpd,
|
---|
7252 | /* 0x2c */ iemOp_cvttps2pi_Ppi_Wps__cvttpd2pi_Ppi_Wpd__cvttss2si_Gy_Wss__cvttsd2si_Yu_Wsd,
|
---|
7253 | /* 0x2d */ iemOp_cvtps2pi_Ppi_Wps__cvtpd2pi_QpiWpd__cvtss2si_Gy_Wss__cvtsd2si_Gy_Wsd,
|
---|
7254 | /* 0x2e */ iemOp_ucomiss_Vss_Wss__ucomisd_Vsd_Wsd,
|
---|
7255 | /* 0x2f */ iemOp_comiss_Vss_Wss__comisd_Vsd_Wsd,
|
---|
7256 | /* 0x30 */ iemOp_wrmsr,
|
---|
7257 | /* 0x31 */ iemOp_rdtsc,
|
---|
7258 | /* 0x32 */ iemOp_rdmsr,
|
---|
7259 | /* 0x33 */ iemOp_rdpmc,
|
---|
7260 | /* 0x34 */ iemOp_sysenter,
|
---|
7261 | /* 0x35 */ iemOp_sysexit,
|
---|
7262 | /* 0x36 */ iemOp_Invalid,
|
---|
7263 | /* 0x37 */ iemOp_getsec,
|
---|
7264 | /* 0x38 */ iemOp_3byte_Esc_A4,
|
---|
7265 | /* 0x39 */ iemOp_Invalid,
|
---|
7266 | /* 0x3a */ iemOp_3byte_Esc_A5,
|
---|
7267 | /* 0x3b */ iemOp_Invalid,
|
---|
7268 | /* 0x3c */ iemOp_Invalid,
|
---|
7269 | /* 0x3d */ iemOp_Invalid,
|
---|
7270 | /* 0x3e */ iemOp_Invalid,
|
---|
7271 | /* 0x3f */ iemOp_Invalid,
|
---|
7272 | /* 0x40 */ iemOp_cmovo_Gv_Ev,
|
---|
7273 | /* 0x41 */ iemOp_cmovno_Gv_Ev,
|
---|
7274 | /* 0x42 */ iemOp_cmovc_Gv_Ev,
|
---|
7275 | /* 0x43 */ iemOp_cmovnc_Gv_Ev,
|
---|
7276 | /* 0x44 */ iemOp_cmove_Gv_Ev,
|
---|
7277 | /* 0x45 */ iemOp_cmovne_Gv_Ev,
|
---|
7278 | /* 0x46 */ iemOp_cmovbe_Gv_Ev,
|
---|
7279 | /* 0x47 */ iemOp_cmovnbe_Gv_Ev,
|
---|
7280 | /* 0x48 */ iemOp_cmovs_Gv_Ev,
|
---|
7281 | /* 0x49 */ iemOp_cmovns_Gv_Ev,
|
---|
7282 | /* 0x4a */ iemOp_cmovp_Gv_Ev,
|
---|
7283 | /* 0x4b */ iemOp_cmovnp_Gv_Ev,
|
---|
7284 | /* 0x4c */ iemOp_cmovl_Gv_Ev,
|
---|
7285 | /* 0x4d */ iemOp_cmovnl_Gv_Ev,
|
---|
7286 | /* 0x4e */ iemOp_cmovle_Gv_Ev,
|
---|
7287 | /* 0x4f */ iemOp_cmovnle_Gv_Ev,
|
---|
7288 | /* 0x50 */ iemOp_movmskps_Gy_Ups__movmskpd_Gy_Upd,
|
---|
7289 | /* 0x51 */ iemOp_sqrtps_Wps_Vps__sqrtpd_Wpd_Vpd__sqrtss_Vss_Wss__sqrtsd_Vsd_Wsd,
|
---|
7290 | /* 0x52 */ iemOp_rsqrtps_Wps_Vps__rsqrtss_Vss_Wss,
|
---|
7291 | /* 0x53 */ iemOp_rcpps_Wps_Vps__rcpss_Vs_Wss,
|
---|
7292 | /* 0x54 */ iemOp_andps_Vps_Wps__andpd_Wpd_Vpd,
|
---|
7293 | /* 0x55 */ iemOp_andnps_Vps_Wps__andnpd_Wpd_Vpd,
|
---|
7294 | /* 0x56 */ iemOp_orps_Wpd_Vpd__orpd_Wpd_Vpd,
|
---|
7295 | /* 0x57 */ iemOp_xorps_Vps_Wps__xorpd_Wpd_Vpd,
|
---|
7296 | /* 0x58 */ iemOp_addps_Vps_Wps__addpd_Vpd_Wpd__addss_Vss_Wss__addsd_Vsd_Wsd,
|
---|
7297 | /* 0x59 */ iemOp_mulps_Vps_Wps__mulpd_Vpd_Wpd__mulss_Vss__Wss__mulsd_Vsd_Wsd,
|
---|
7298 | /* 0x5a */ iemOp_cvtps2pd_Vpd_Wps__cvtpd2ps_Vps_Wpd__cvtss2sd_Vsd_Wss__cvtsd2ss_Vss_Wsd,
|
---|
7299 | /* 0x5b */ iemOp_cvtdq2ps_Vps_Wdq__cvtps2dq_Vdq_Wps__cvtps2dq_Vdq_Wps,
|
---|
7300 | /* 0x5c */ iemOp_subps_Vps_Wps__subpd_Vps_Wdp__subss_Vss_Wss__subsd_Vsd_Wsd,
|
---|
7301 | /* 0x5d */ iemOp_minps_Vps_Wps__minpd_Vpd_Wpd__minss_Vss_Wss__minsd_Vsd_Wsd,
|
---|
7302 | /* 0x5e */ iemOp_divps_Vps_Wps__divpd_Vpd_Wpd__divss_Vss_Wss__divsd_Vsd_Wsd,
|
---|
7303 | /* 0x5f */ iemOp_maxps_Vps_Wps__maxpd_Vpd_Wpd__maxss_Vss_Wss__maxsd_Vsd_Wsd,
|
---|
7304 | /* 0x60 */ iemOp_punpcklbw_Pq_Qd__punpcklbw_Vdq_Wdq,
|
---|
7305 | /* 0x61 */ iemOp_punpcklwd_Pq_Qd__punpcklwd_Vdq_Wdq,
|
---|
7306 | /* 0x62 */ iemOp_punpckldq_Pq_Qd__punpckldq_Vdq_Wdq,
|
---|
7307 | /* 0x63 */ iemOp_packsswb_Pq_Qq__packsswb_Vdq_Wdq,
|
---|
7308 | /* 0x64 */ iemOp_pcmpgtb_Pq_Qq__pcmpgtb_Vdq_Wdq,
|
---|
7309 | /* 0x65 */ iemOp_pcmpgtw_Pq_Qq__pcmpgtw_Vdq_Wdq,
|
---|
7310 | /* 0x66 */ iemOp_pcmpgtd_Pq_Qq__pcmpgtd_Vdq_Wdq,
|
---|
7311 | /* 0x67 */ iemOp_packuswb_Pq_Qq__packuswb_Vdq_Wdq,
|
---|
7312 | /* 0x68 */ iemOp_punpckhbw_Pq_Qq__punpckhbw_Vdq_Wdq,
|
---|
7313 | /* 0x69 */ iemOp_punpckhwd_Pq_Qd__punpckhwd_Vdq_Wdq,
|
---|
7314 | /* 0x6a */ iemOp_punpckhdq_Pq_Qd__punpckhdq_Vdq_Wdq,
|
---|
7315 | /* 0x6b */ iemOp_packssdw_Pq_Qd__packssdq_Vdq_Wdq,
|
---|
7316 | /* 0x6c */ iemOp_punpcklqdq_Vdq_Wdq,
|
---|
7317 | /* 0x6d */ iemOp_punpckhqdq_Vdq_Wdq,
|
---|
7318 | /* 0x6e */ iemOp_movd_q_Pd_Ey__movd_q_Vy_Ey,
|
---|
7319 | /* 0x6f */ iemOp_movq_Pq_Qq__movdqa_Vdq_Wdq__movdqu_Vdq_Wdq,
|
---|
7320 | /* 0x70 */ iemOp_pshufw_Pq_Qq_Ib__pshufd_Vdq_Wdq_Ib__pshufhw_Vdq_Wdq_Ib__pshuflq_Vdq_Wdq_Ib,
|
---|
7321 | /* 0x71 */ iemOp_Grp12,
|
---|
7322 | /* 0x72 */ iemOp_Grp13,
|
---|
7323 | /* 0x73 */ iemOp_Grp14,
|
---|
7324 | /* 0x74 */ iemOp_pcmpeqb_Pq_Qq__pcmpeqb_Vdq_Wdq,
|
---|
7325 | /* 0x75 */ iemOp_pcmpeqw_Pq_Qq__pcmpeqw_Vdq_Wdq,
|
---|
7326 | /* 0x76 */ iemOp_pcmped_Pq_Qq__pcmpeqd_Vdq_Wdq,
|
---|
7327 | /* 0x77 */ iemOp_emms,
|
---|
7328 | /* 0x78 */ iemOp_vmread_AmdGrp17,
|
---|
7329 | /* 0x79 */ iemOp_vmwrite,
|
---|
7330 | /* 0x7a */ iemOp_Invalid,
|
---|
7331 | /* 0x7b */ iemOp_Invalid,
|
---|
7332 | /* 0x7c */ iemOp_haddpd_Vdp_Wpd__haddps_Vps_Wps,
|
---|
7333 | /* 0x7d */ iemOp_hsubpd_Vpd_Wpd__hsubps_Vps_Wps,
|
---|
7334 | /* 0x7e */ iemOp_movd_q_Ey_Pd__movd_q_Ey_Vy__movq_Vq_Wq,
|
---|
7335 | /* 0x7f */ iemOp_movq_Qq_Pq__movq_movdqa_Wdq_Vdq__movdqu_Wdq_Vdq,
|
---|
7336 | /* 0x80 */ iemOp_jo_Jv,
|
---|
7337 | /* 0x81 */ iemOp_jno_Jv,
|
---|
7338 | /* 0x82 */ iemOp_jc_Jv,
|
---|
7339 | /* 0x83 */ iemOp_jnc_Jv,
|
---|
7340 | /* 0x84 */ iemOp_je_Jv,
|
---|
7341 | /* 0x85 */ iemOp_jne_Jv,
|
---|
7342 | /* 0x86 */ iemOp_jbe_Jv,
|
---|
7343 | /* 0x87 */ iemOp_jnbe_Jv,
|
---|
7344 | /* 0x88 */ iemOp_js_Jv,
|
---|
7345 | /* 0x89 */ iemOp_jns_Jv,
|
---|
7346 | /* 0x8a */ iemOp_jp_Jv,
|
---|
7347 | /* 0x8b */ iemOp_jnp_Jv,
|
---|
7348 | /* 0x8c */ iemOp_jl_Jv,
|
---|
7349 | /* 0x8d */ iemOp_jnl_Jv,
|
---|
7350 | /* 0x8e */ iemOp_jle_Jv,
|
---|
7351 | /* 0x8f */ iemOp_jnle_Jv,
|
---|
7352 | /* 0x90 */ iemOp_seto_Eb,
|
---|
7353 | /* 0x91 */ iemOp_setno_Eb,
|
---|
7354 | /* 0x92 */ iemOp_setc_Eb,
|
---|
7355 | /* 0x93 */ iemOp_setnc_Eb,
|
---|
7356 | /* 0x94 */ iemOp_sete_Eb,
|
---|
7357 | /* 0x95 */ iemOp_setne_Eb,
|
---|
7358 | /* 0x96 */ iemOp_setbe_Eb,
|
---|
7359 | /* 0x97 */ iemOp_setnbe_Eb,
|
---|
7360 | /* 0x98 */ iemOp_sets_Eb,
|
---|
7361 | /* 0x99 */ iemOp_setns_Eb,
|
---|
7362 | /* 0x9a */ iemOp_setp_Eb,
|
---|
7363 | /* 0x9b */ iemOp_setnp_Eb,
|
---|
7364 | /* 0x9c */ iemOp_setl_Eb,
|
---|
7365 | /* 0x9d */ iemOp_setnl_Eb,
|
---|
7366 | /* 0x9e */ iemOp_setle_Eb,
|
---|
7367 | /* 0x9f */ iemOp_setnle_Eb,
|
---|
7368 | /* 0xa0 */ iemOp_push_fs,
|
---|
7369 | /* 0xa1 */ iemOp_pop_fs,
|
---|
7370 | /* 0xa2 */ iemOp_cpuid,
|
---|
7371 | /* 0xa3 */ iemOp_bt_Ev_Gv,
|
---|
7372 | /* 0xa4 */ iemOp_shld_Ev_Gv_Ib,
|
---|
7373 | /* 0xa5 */ iemOp_shld_Ev_Gv_CL,
|
---|
7374 | /* 0xa6 */ iemOp_Invalid,
|
---|
7375 | /* 0xa7 */ iemOp_Invalid,
|
---|
7376 | /* 0xa8 */ iemOp_push_gs,
|
---|
7377 | /* 0xa9 */ iemOp_pop_gs,
|
---|
7378 | /* 0xaa */ iemOp_rsm,
|
---|
7379 | /* 0xab */ iemOp_bts_Ev_Gv,
|
---|
7380 | /* 0xac */ iemOp_shrd_Ev_Gv_Ib,
|
---|
7381 | /* 0xad */ iemOp_shrd_Ev_Gv_CL,
|
---|
7382 | /* 0xae */ iemOp_Grp15,
|
---|
7383 | /* 0xaf */ iemOp_imul_Gv_Ev,
|
---|
7384 | /* 0xb0 */ iemOp_cmpxchg_Eb_Gb,
|
---|
7385 | /* 0xb1 */ iemOp_cmpxchg_Ev_Gv,
|
---|
7386 | /* 0xb2 */ iemOp_lss_Gv_Mp,
|
---|
7387 | /* 0xb3 */ iemOp_btr_Ev_Gv,
|
---|
7388 | /* 0xb4 */ iemOp_lfs_Gv_Mp,
|
---|
7389 | /* 0xb5 */ iemOp_lgs_Gv_Mp,
|
---|
7390 | /* 0xb6 */ iemOp_movzx_Gv_Eb,
|
---|
7391 | /* 0xb7 */ iemOp_movzx_Gv_Ew,
|
---|
7392 | /* 0xb8 */ iemOp_popcnt_Gv_Ev_jmpe,
|
---|
7393 | /* 0xb9 */ iemOp_Grp10,
|
---|
7394 | /* 0xba */ iemOp_Grp8,
|
---|
7395 | /* 0xbd */ iemOp_btc_Ev_Gv,
|
---|
7396 | /* 0xbc */ iemOp_bsf_Gv_Ev,
|
---|
7397 | /* 0xbd */ iemOp_bsr_Gv_Ev,
|
---|
7398 | /* 0xbe */ iemOp_movsx_Gv_Eb,
|
---|
7399 | /* 0xbf */ iemOp_movsx_Gv_Ew,
|
---|
7400 | /* 0xc0 */ iemOp_xadd_Eb_Gb,
|
---|
7401 | /* 0xc1 */ iemOp_xadd_Ev_Gv,
|
---|
7402 | /* 0xc2 */ iemOp_cmpps_Vps_Wps_Ib__cmppd_Vpd_Wpd_Ib__cmpss_Vss_Wss_Ib__cmpsd_Vsd_Wsd_Ib,
|
---|
7403 | /* 0xc3 */ iemOp_movnti_My_Gy,
|
---|
7404 | /* 0xc4 */ iemOp_pinsrw_Pq_Ry_Mw_Ib__pinsrw_Vdq_Ry_Mw_Ib,
|
---|
7405 | /* 0xc5 */ iemOp_pextrw_Gd_Nq_Ib__pextrw_Gd_Udq_Ib,
|
---|
7406 | /* 0xc6 */ iemOp_shufps_Vps_Wps_Ib__shufdp_Vpd_Wpd_Ib,
|
---|
7407 | /* 0xc7 */ iemOp_Grp9,
|
---|
7408 | /* 0xc8 */ iemOp_bswap_rAX_r8,
|
---|
7409 | /* 0xc9 */ iemOp_bswap_rCX_r9,
|
---|
7410 | /* 0xca */ iemOp_bswap_rDX_r10,
|
---|
7411 | /* 0xcb */ iemOp_bswap_rBX_r11,
|
---|
7412 | /* 0xcc */ iemOp_bswap_rSP_r12,
|
---|
7413 | /* 0xcd */ iemOp_bswap_rBP_r13,
|
---|
7414 | /* 0xce */ iemOp_bswap_rSI_r14,
|
---|
7415 | /* 0xcf */ iemOp_bswap_rDI_r15,
|
---|
7416 | /* 0xd0 */ iemOp_addsubpd_Vpd_Wpd__addsubps_Vps_Wps,
|
---|
7417 | /* 0xd1 */ iemOp_psrlw_Pp_Qp__psrlw_Vdp_Wdq,
|
---|
7418 | /* 0xd2 */ iemOp_psrld_Pq_Qq__psrld_Vdq_Wdq,
|
---|
7419 | /* 0xd3 */ iemOp_psrlq_Pq_Qq__psrlq_Vdq_Wdq,
|
---|
7420 | /* 0xd4 */ iemOp_paddq_Pq_Qq__paddq_Vdq_Wdq,
|
---|
7421 | /* 0xd5 */ iemOp_pmulq_Pq_Qq__pmullw_Vdq_Wdq,
|
---|
7422 | /* 0xd6 */ iemOp_movq_Wq_Vq__movq2dq_Vdq_Nq__movdq2q_Pq_Uq,
|
---|
7423 | /* 0xd7 */ iemOp_pmovmskb_Gd_Nq__pmovmskb_Gd_Udq,
|
---|
7424 | /* 0xd8 */ iemOp_psubusb_Pq_Qq__psubusb_Vdq_Wdq,
|
---|
7425 | /* 0xd9 */ iemOp_psubusw_Pq_Qq__psubusw_Vdq_Wdq,
|
---|
7426 | /* 0xda */ iemOp_pminub_Pq_Qq__pminub_Vdq_Wdq,
|
---|
7427 | /* 0xdb */ iemOp_pand_Pq_Qq__pand_Vdq_Wdq,
|
---|
7428 | /* 0xdc */ iemOp_paddusb_Pq_Qq__paddusb_Vdq_Wdq,
|
---|
7429 | /* 0xdd */ iemOp_paddusw_Pq_Qq__paddusw_Vdq_Wdq,
|
---|
7430 | /* 0xde */ iemOp_pmaxub_Pq_Qq__pamxub_Vdq_Wdq,
|
---|
7431 | /* 0xdf */ iemOp_pandn_Pq_Qq__pandn_Vdq_Wdq,
|
---|
7432 | /* 0xe0 */ iemOp_pavgb_Pq_Qq__pavgb_Vdq_Wdq,
|
---|
7433 | /* 0xe1 */ iemOp_psraw_Pq_Qq__psraw_Vdq_Wdq,
|
---|
7434 | /* 0xe2 */ iemOp_psrad_Pq_Qq__psrad_Vdq_Wdq,
|
---|
7435 | /* 0xe3 */ iemOp_pavgw_Pq_Qq__pavgw_Vdq_Wdq,
|
---|
7436 | /* 0xe4 */ iemOp_pmulhuw_Pq_Qq__pmulhuw_Vdq_Wdq,
|
---|
7437 | /* 0xe5 */ iemOp_pmulhw_Pq_Qq__pmulhw_Vdq_Wdq,
|
---|
7438 | /* 0xe6 */ iemOp_cvttpd2dq_Vdq_Wdp__cvtdq2pd_Vdq_Wpd__cvtpd2dq_Vdq_Wpd,
|
---|
7439 | /* 0xe7 */ iemOp_movntq_Mq_Pq__movntdq_Mdq_Vdq,
|
---|
7440 | /* 0xe8 */ iemOp_psubsb_Pq_Qq__psubsb_Vdq_Wdq,
|
---|
7441 | /* 0xe9 */ iemOp_psubsw_Pq_Qq__psubsw_Vdq_Wdq,
|
---|
7442 | /* 0xea */ iemOp_pminsw_Pq_Qq__pminsw_Vdq_Wdq,
|
---|
7443 | /* 0xeb */ iemOp_por_Pq_Qq__por_Vdq_Wdq,
|
---|
7444 | /* 0xec */ iemOp_paddsb_Pq_Qq__paddsb_Vdq_Wdq,
|
---|
7445 | /* 0xed */ iemOp_paddsw_Pq_Qq__paddsw_Vdq_Wdq,
|
---|
7446 | /* 0xee */ iemOp_pmaxsw_Pq_Qq__pmaxsw_Vdq_Wdq,
|
---|
7447 | /* 0xef */ iemOp_pxor_Pq_Qq__pxor_Vdq_Wdq,
|
---|
7448 | /* 0xf0 */ iemOp_lddqu_Vdq_Mdq,
|
---|
7449 | /* 0xf1 */ iemOp_psllw_Pq_Qq__pslw_Vdq_Wdq,
|
---|
7450 | /* 0xf2 */ iemOp_psld_Pq_Qq__pslld_Vdq_Wdq,
|
---|
7451 | /* 0xf3 */ iemOp_psllq_Pq_Qq__pslq_Vdq_Wdq,
|
---|
7452 | /* 0xf4 */ iemOp_pmuludq_Pq_Qq__pmuludq_Vdq_Wdq,
|
---|
7453 | /* 0xf5 */ iemOp_pmaddwd_Pq_Qq__pmaddwd_Vdq_Wdq,
|
---|
7454 | /* 0xf6 */ iemOp_psadbw_Pq_Qq__psadbw_Vdq_Wdq,
|
---|
7455 | /* 0xf7 */ iemOp_maskmovq_Pq_Nq__maskmovdqu_Vdq_Udq,
|
---|
7456 | /* 0xf8 */ iemOp_psubb_Pq_Qq_psubb_Vdq_Wdq,
|
---|
7457 | /* 0xf9 */ iemOp_psubw_Pq_Qq__psubw_Vdq_Wdq,
|
---|
7458 | /* 0xfa */ iemOp_psubd_Pq_Qq__psubd_Vdq_Wdq,
|
---|
7459 | /* 0xfb */ iemOp_psubq_Pq_Qq__psbuq_Vdq_Wdq,
|
---|
7460 | /* 0xfc */ iemOp_paddb_Pq_Qq__paddb_Vdq_Wdq,
|
---|
7461 | /* 0xfd */ iemOp_paddw_Pq_Qq__paddw_Vdq_Wdq,
|
---|
7462 | /* 0xfe */ iemOp_paddd_Pq_Qq__paddd_Vdq_Wdq,
|
---|
7463 | /* 0xff */ iemOp_Invalid
|
---|
7464 | };
|
---|
7465 |
|
---|
7466 | /** @} */
|
---|
7467 |
|
---|
7468 |
|
---|
7469 | /** @name One byte opcodes.
|
---|
7470 | *
|
---|
7471 | * @{
|
---|
7472 | */
|
---|
7473 |
|
---|
7474 | /** Opcode 0x00. */
|
---|
7475 | FNIEMOP_DEF(iemOp_add_Eb_Gb)
|
---|
7476 | {
|
---|
7477 | IEMOP_MNEMONIC("add Eb,Gb");
|
---|
7478 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_add);
|
---|
7479 | }
|
---|
7480 |
|
---|
7481 |
|
---|
7482 | /** Opcode 0x01. */
|
---|
7483 | FNIEMOP_DEF(iemOp_add_Ev_Gv)
|
---|
7484 | {
|
---|
7485 | IEMOP_MNEMONIC("add Ev,Gv");
|
---|
7486 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_add);
|
---|
7487 | }
|
---|
7488 |
|
---|
7489 |
|
---|
7490 | /** Opcode 0x02. */
|
---|
7491 | FNIEMOP_DEF(iemOp_add_Gb_Eb)
|
---|
7492 | {
|
---|
7493 | IEMOP_MNEMONIC("add Gb,Eb");
|
---|
7494 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_add);
|
---|
7495 | }
|
---|
7496 |
|
---|
7497 |
|
---|
7498 | /** Opcode 0x03. */
|
---|
7499 | FNIEMOP_DEF(iemOp_add_Gv_Ev)
|
---|
7500 | {
|
---|
7501 | IEMOP_MNEMONIC("add Gv,Ev");
|
---|
7502 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_add);
|
---|
7503 | }
|
---|
7504 |
|
---|
7505 |
|
---|
7506 | /** Opcode 0x04. */
|
---|
7507 | FNIEMOP_DEF(iemOp_add_Al_Ib)
|
---|
7508 | {
|
---|
7509 | IEMOP_MNEMONIC("add al,Ib");
|
---|
7510 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_add);
|
---|
7511 | }
|
---|
7512 |
|
---|
7513 |
|
---|
7514 | /** Opcode 0x05. */
|
---|
7515 | FNIEMOP_DEF(iemOp_add_eAX_Iz)
|
---|
7516 | {
|
---|
7517 | IEMOP_MNEMONIC("add rAX,Iz");
|
---|
7518 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_add);
|
---|
7519 | }
|
---|
7520 |
|
---|
7521 |
|
---|
7522 | /** Opcode 0x06. */
|
---|
7523 | FNIEMOP_DEF(iemOp_push_ES)
|
---|
7524 | {
|
---|
7525 | IEMOP_MNEMONIC("push es");
|
---|
7526 | return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_ES);
|
---|
7527 | }
|
---|
7528 |
|
---|
7529 |
|
---|
7530 | /** Opcode 0x07. */
|
---|
7531 | FNIEMOP_DEF(iemOp_pop_ES)
|
---|
7532 | {
|
---|
7533 | IEMOP_MNEMONIC("pop es");
|
---|
7534 | IEMOP_HLP_NO_64BIT();
|
---|
7535 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
7536 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_ES, pVCpu->iem.s.enmEffOpSize);
|
---|
7537 | }
|
---|
7538 |
|
---|
7539 |
|
---|
7540 | /** Opcode 0x08. */
|
---|
7541 | FNIEMOP_DEF(iemOp_or_Eb_Gb)
|
---|
7542 | {
|
---|
7543 | IEMOP_MNEMONIC("or Eb,Gb");
|
---|
7544 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7545 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_or);
|
---|
7546 | }
|
---|
7547 |
|
---|
7548 |
|
---|
7549 | /** Opcode 0x09. */
|
---|
7550 | FNIEMOP_DEF(iemOp_or_Ev_Gv)
|
---|
7551 | {
|
---|
7552 | IEMOP_MNEMONIC("or Ev,Gv ");
|
---|
7553 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7554 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_or);
|
---|
7555 | }
|
---|
7556 |
|
---|
7557 |
|
---|
7558 | /** Opcode 0x0a. */
|
---|
7559 | FNIEMOP_DEF(iemOp_or_Gb_Eb)
|
---|
7560 | {
|
---|
7561 | IEMOP_MNEMONIC("or Gb,Eb");
|
---|
7562 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7563 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_or);
|
---|
7564 | }
|
---|
7565 |
|
---|
7566 |
|
---|
7567 | /** Opcode 0x0b. */
|
---|
7568 | FNIEMOP_DEF(iemOp_or_Gv_Ev)
|
---|
7569 | {
|
---|
7570 | IEMOP_MNEMONIC("or Gv,Ev");
|
---|
7571 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7572 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_or);
|
---|
7573 | }
|
---|
7574 |
|
---|
7575 |
|
---|
7576 | /** Opcode 0x0c. */
|
---|
7577 | FNIEMOP_DEF(iemOp_or_Al_Ib)
|
---|
7578 | {
|
---|
7579 | IEMOP_MNEMONIC("or al,Ib");
|
---|
7580 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7581 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_or);
|
---|
7582 | }
|
---|
7583 |
|
---|
7584 |
|
---|
7585 | /** Opcode 0x0d. */
|
---|
7586 | FNIEMOP_DEF(iemOp_or_eAX_Iz)
|
---|
7587 | {
|
---|
7588 | IEMOP_MNEMONIC("or rAX,Iz");
|
---|
7589 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7590 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_or);
|
---|
7591 | }
|
---|
7592 |
|
---|
7593 |
|
---|
7594 | /** Opcode 0x0e. */
|
---|
7595 | FNIEMOP_DEF(iemOp_push_CS)
|
---|
7596 | {
|
---|
7597 | IEMOP_MNEMONIC("push cs");
|
---|
7598 | return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_CS);
|
---|
7599 | }
|
---|
7600 |
|
---|
7601 |
|
---|
7602 | /** Opcode 0x0f. */
|
---|
7603 | FNIEMOP_DEF(iemOp_2byteEscape)
|
---|
7604 | {
|
---|
7605 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
7606 | /** @todo PUSH CS on 8086, undefined on 80186. */
|
---|
7607 | IEMOP_HLP_MIN_286();
|
---|
7608 | return FNIEMOP_CALL(g_apfnTwoByteMap[b]);
|
---|
7609 | }
|
---|
7610 |
|
---|
7611 | /** Opcode 0x10. */
|
---|
7612 | FNIEMOP_DEF(iemOp_adc_Eb_Gb)
|
---|
7613 | {
|
---|
7614 | IEMOP_MNEMONIC("adc Eb,Gb");
|
---|
7615 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_adc);
|
---|
7616 | }
|
---|
7617 |
|
---|
7618 |
|
---|
7619 | /** Opcode 0x11. */
|
---|
7620 | FNIEMOP_DEF(iemOp_adc_Ev_Gv)
|
---|
7621 | {
|
---|
7622 | IEMOP_MNEMONIC("adc Ev,Gv");
|
---|
7623 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_adc);
|
---|
7624 | }
|
---|
7625 |
|
---|
7626 |
|
---|
7627 | /** Opcode 0x12. */
|
---|
7628 | FNIEMOP_DEF(iemOp_adc_Gb_Eb)
|
---|
7629 | {
|
---|
7630 | IEMOP_MNEMONIC("adc Gb,Eb");
|
---|
7631 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_adc);
|
---|
7632 | }
|
---|
7633 |
|
---|
7634 |
|
---|
7635 | /** Opcode 0x13. */
|
---|
7636 | FNIEMOP_DEF(iemOp_adc_Gv_Ev)
|
---|
7637 | {
|
---|
7638 | IEMOP_MNEMONIC("adc Gv,Ev");
|
---|
7639 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_adc);
|
---|
7640 | }
|
---|
7641 |
|
---|
7642 |
|
---|
7643 | /** Opcode 0x14. */
|
---|
7644 | FNIEMOP_DEF(iemOp_adc_Al_Ib)
|
---|
7645 | {
|
---|
7646 | IEMOP_MNEMONIC("adc al,Ib");
|
---|
7647 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_adc);
|
---|
7648 | }
|
---|
7649 |
|
---|
7650 |
|
---|
7651 | /** Opcode 0x15. */
|
---|
7652 | FNIEMOP_DEF(iemOp_adc_eAX_Iz)
|
---|
7653 | {
|
---|
7654 | IEMOP_MNEMONIC("adc rAX,Iz");
|
---|
7655 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_adc);
|
---|
7656 | }
|
---|
7657 |
|
---|
7658 |
|
---|
7659 | /** Opcode 0x16. */
|
---|
7660 | FNIEMOP_DEF(iemOp_push_SS)
|
---|
7661 | {
|
---|
7662 | IEMOP_MNEMONIC("push ss");
|
---|
7663 | return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_SS);
|
---|
7664 | }
|
---|
7665 |
|
---|
7666 |
|
---|
7667 | /** Opcode 0x17. */
|
---|
7668 | FNIEMOP_DEF(iemOp_pop_SS)
|
---|
7669 | {
|
---|
7670 | IEMOP_MNEMONIC("pop ss"); /** @todo implies instruction fusing? */
|
---|
7671 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
7672 | IEMOP_HLP_NO_64BIT();
|
---|
7673 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_SS, pVCpu->iem.s.enmEffOpSize);
|
---|
7674 | }
|
---|
7675 |
|
---|
7676 |
|
---|
7677 | /** Opcode 0x18. */
|
---|
7678 | FNIEMOP_DEF(iemOp_sbb_Eb_Gb)
|
---|
7679 | {
|
---|
7680 | IEMOP_MNEMONIC("sbb Eb,Gb");
|
---|
7681 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_sbb);
|
---|
7682 | }
|
---|
7683 |
|
---|
7684 |
|
---|
7685 | /** Opcode 0x19. */
|
---|
7686 | FNIEMOP_DEF(iemOp_sbb_Ev_Gv)
|
---|
7687 | {
|
---|
7688 | IEMOP_MNEMONIC("sbb Ev,Gv");
|
---|
7689 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_sbb);
|
---|
7690 | }
|
---|
7691 |
|
---|
7692 |
|
---|
7693 | /** Opcode 0x1a. */
|
---|
7694 | FNIEMOP_DEF(iemOp_sbb_Gb_Eb)
|
---|
7695 | {
|
---|
7696 | IEMOP_MNEMONIC("sbb Gb,Eb");
|
---|
7697 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_sbb);
|
---|
7698 | }
|
---|
7699 |
|
---|
7700 |
|
---|
7701 | /** Opcode 0x1b. */
|
---|
7702 | FNIEMOP_DEF(iemOp_sbb_Gv_Ev)
|
---|
7703 | {
|
---|
7704 | IEMOP_MNEMONIC("sbb Gv,Ev");
|
---|
7705 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_sbb);
|
---|
7706 | }
|
---|
7707 |
|
---|
7708 |
|
---|
7709 | /** Opcode 0x1c. */
|
---|
7710 | FNIEMOP_DEF(iemOp_sbb_Al_Ib)
|
---|
7711 | {
|
---|
7712 | IEMOP_MNEMONIC("sbb al,Ib");
|
---|
7713 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_sbb);
|
---|
7714 | }
|
---|
7715 |
|
---|
7716 |
|
---|
7717 | /** Opcode 0x1d. */
|
---|
7718 | FNIEMOP_DEF(iemOp_sbb_eAX_Iz)
|
---|
7719 | {
|
---|
7720 | IEMOP_MNEMONIC("sbb rAX,Iz");
|
---|
7721 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_sbb);
|
---|
7722 | }
|
---|
7723 |
|
---|
7724 |
|
---|
7725 | /** Opcode 0x1e. */
|
---|
7726 | FNIEMOP_DEF(iemOp_push_DS)
|
---|
7727 | {
|
---|
7728 | IEMOP_MNEMONIC("push ds");
|
---|
7729 | return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_DS);
|
---|
7730 | }
|
---|
7731 |
|
---|
7732 |
|
---|
7733 | /** Opcode 0x1f. */
|
---|
7734 | FNIEMOP_DEF(iemOp_pop_DS)
|
---|
7735 | {
|
---|
7736 | IEMOP_MNEMONIC("pop ds");
|
---|
7737 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
7738 | IEMOP_HLP_NO_64BIT();
|
---|
7739 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_DS, pVCpu->iem.s.enmEffOpSize);
|
---|
7740 | }
|
---|
7741 |
|
---|
7742 |
|
---|
7743 | /** Opcode 0x20. */
|
---|
7744 | FNIEMOP_DEF(iemOp_and_Eb_Gb)
|
---|
7745 | {
|
---|
7746 | IEMOP_MNEMONIC("and Eb,Gb");
|
---|
7747 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7748 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_and);
|
---|
7749 | }
|
---|
7750 |
|
---|
7751 |
|
---|
7752 | /** Opcode 0x21. */
|
---|
7753 | FNIEMOP_DEF(iemOp_and_Ev_Gv)
|
---|
7754 | {
|
---|
7755 | IEMOP_MNEMONIC("and Ev,Gv");
|
---|
7756 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7757 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_and);
|
---|
7758 | }
|
---|
7759 |
|
---|
7760 |
|
---|
7761 | /** Opcode 0x22. */
|
---|
7762 | FNIEMOP_DEF(iemOp_and_Gb_Eb)
|
---|
7763 | {
|
---|
7764 | IEMOP_MNEMONIC("and Gb,Eb");
|
---|
7765 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7766 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_and);
|
---|
7767 | }
|
---|
7768 |
|
---|
7769 |
|
---|
7770 | /** Opcode 0x23. */
|
---|
7771 | FNIEMOP_DEF(iemOp_and_Gv_Ev)
|
---|
7772 | {
|
---|
7773 | IEMOP_MNEMONIC("and Gv,Ev");
|
---|
7774 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7775 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_and);
|
---|
7776 | }
|
---|
7777 |
|
---|
7778 |
|
---|
7779 | /** Opcode 0x24. */
|
---|
7780 | FNIEMOP_DEF(iemOp_and_Al_Ib)
|
---|
7781 | {
|
---|
7782 | IEMOP_MNEMONIC("and al,Ib");
|
---|
7783 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7784 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_and);
|
---|
7785 | }
|
---|
7786 |
|
---|
7787 |
|
---|
7788 | /** Opcode 0x25. */
|
---|
7789 | FNIEMOP_DEF(iemOp_and_eAX_Iz)
|
---|
7790 | {
|
---|
7791 | IEMOP_MNEMONIC("and rAX,Iz");
|
---|
7792 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7793 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_and);
|
---|
7794 | }
|
---|
7795 |
|
---|
7796 |
|
---|
7797 | /** Opcode 0x26. */
|
---|
7798 | FNIEMOP_DEF(iemOp_seg_ES)
|
---|
7799 | {
|
---|
7800 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("seg es");
|
---|
7801 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SEG_ES;
|
---|
7802 | pVCpu->iem.s.iEffSeg = X86_SREG_ES;
|
---|
7803 |
|
---|
7804 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
7805 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
7806 | }
|
---|
7807 |
|
---|
7808 |
|
---|
7809 | /** Opcode 0x27. */
|
---|
7810 | FNIEMOP_DEF(iemOp_daa)
|
---|
7811 | {
|
---|
7812 | IEMOP_MNEMONIC("daa AL");
|
---|
7813 | IEMOP_HLP_NO_64BIT();
|
---|
7814 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
7815 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF);
|
---|
7816 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_daa);
|
---|
7817 | }
|
---|
7818 |
|
---|
7819 |
|
---|
7820 | /** Opcode 0x28. */
|
---|
7821 | FNIEMOP_DEF(iemOp_sub_Eb_Gb)
|
---|
7822 | {
|
---|
7823 | IEMOP_MNEMONIC("sub Eb,Gb");
|
---|
7824 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_sub);
|
---|
7825 | }
|
---|
7826 |
|
---|
7827 |
|
---|
7828 | /** Opcode 0x29. */
|
---|
7829 | FNIEMOP_DEF(iemOp_sub_Ev_Gv)
|
---|
7830 | {
|
---|
7831 | IEMOP_MNEMONIC("sub Ev,Gv");
|
---|
7832 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_sub);
|
---|
7833 | }
|
---|
7834 |
|
---|
7835 |
|
---|
7836 | /** Opcode 0x2a. */
|
---|
7837 | FNIEMOP_DEF(iemOp_sub_Gb_Eb)
|
---|
7838 | {
|
---|
7839 | IEMOP_MNEMONIC("sub Gb,Eb");
|
---|
7840 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_sub);
|
---|
7841 | }
|
---|
7842 |
|
---|
7843 |
|
---|
7844 | /** Opcode 0x2b. */
|
---|
7845 | FNIEMOP_DEF(iemOp_sub_Gv_Ev)
|
---|
7846 | {
|
---|
7847 | IEMOP_MNEMONIC("sub Gv,Ev");
|
---|
7848 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_sub);
|
---|
7849 | }
|
---|
7850 |
|
---|
7851 |
|
---|
7852 | /** Opcode 0x2c. */
|
---|
7853 | FNIEMOP_DEF(iemOp_sub_Al_Ib)
|
---|
7854 | {
|
---|
7855 | IEMOP_MNEMONIC("sub al,Ib");
|
---|
7856 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_sub);
|
---|
7857 | }
|
---|
7858 |
|
---|
7859 |
|
---|
7860 | /** Opcode 0x2d. */
|
---|
7861 | FNIEMOP_DEF(iemOp_sub_eAX_Iz)
|
---|
7862 | {
|
---|
7863 | IEMOP_MNEMONIC("sub rAX,Iz");
|
---|
7864 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_sub);
|
---|
7865 | }
|
---|
7866 |
|
---|
7867 |
|
---|
7868 | /** Opcode 0x2e. */
|
---|
7869 | FNIEMOP_DEF(iemOp_seg_CS)
|
---|
7870 | {
|
---|
7871 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("seg cs");
|
---|
7872 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SEG_CS;
|
---|
7873 | pVCpu->iem.s.iEffSeg = X86_SREG_CS;
|
---|
7874 |
|
---|
7875 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
7876 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
7877 | }
|
---|
7878 |
|
---|
7879 |
|
---|
7880 | /** Opcode 0x2f. */
|
---|
7881 | FNIEMOP_DEF(iemOp_das)
|
---|
7882 | {
|
---|
7883 | IEMOP_MNEMONIC("das AL");
|
---|
7884 | IEMOP_HLP_NO_64BIT();
|
---|
7885 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
7886 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF);
|
---|
7887 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_das);
|
---|
7888 | }
|
---|
7889 |
|
---|
7890 |
|
---|
7891 | /** Opcode 0x30. */
|
---|
7892 | FNIEMOP_DEF(iemOp_xor_Eb_Gb)
|
---|
7893 | {
|
---|
7894 | IEMOP_MNEMONIC("xor Eb,Gb");
|
---|
7895 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7896 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_xor);
|
---|
7897 | }
|
---|
7898 |
|
---|
7899 |
|
---|
7900 | /** Opcode 0x31. */
|
---|
7901 | FNIEMOP_DEF(iemOp_xor_Ev_Gv)
|
---|
7902 | {
|
---|
7903 | IEMOP_MNEMONIC("xor Ev,Gv");
|
---|
7904 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7905 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_xor);
|
---|
7906 | }
|
---|
7907 |
|
---|
7908 |
|
---|
7909 | /** Opcode 0x32. */
|
---|
7910 | FNIEMOP_DEF(iemOp_xor_Gb_Eb)
|
---|
7911 | {
|
---|
7912 | IEMOP_MNEMONIC("xor Gb,Eb");
|
---|
7913 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7914 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_xor);
|
---|
7915 | }
|
---|
7916 |
|
---|
7917 |
|
---|
7918 | /** Opcode 0x33. */
|
---|
7919 | FNIEMOP_DEF(iemOp_xor_Gv_Ev)
|
---|
7920 | {
|
---|
7921 | IEMOP_MNEMONIC("xor Gv,Ev");
|
---|
7922 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7923 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_xor);
|
---|
7924 | }
|
---|
7925 |
|
---|
7926 |
|
---|
7927 | /** Opcode 0x34. */
|
---|
7928 | FNIEMOP_DEF(iemOp_xor_Al_Ib)
|
---|
7929 | {
|
---|
7930 | IEMOP_MNEMONIC("xor al,Ib");
|
---|
7931 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7932 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_xor);
|
---|
7933 | }
|
---|
7934 |
|
---|
7935 |
|
---|
7936 | /** Opcode 0x35. */
|
---|
7937 | FNIEMOP_DEF(iemOp_xor_eAX_Iz)
|
---|
7938 | {
|
---|
7939 | IEMOP_MNEMONIC("xor rAX,Iz");
|
---|
7940 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
7941 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_xor);
|
---|
7942 | }
|
---|
7943 |
|
---|
7944 |
|
---|
7945 | /** Opcode 0x36. */
|
---|
7946 | FNIEMOP_DEF(iemOp_seg_SS)
|
---|
7947 | {
|
---|
7948 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("seg ss");
|
---|
7949 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SEG_SS;
|
---|
7950 | pVCpu->iem.s.iEffSeg = X86_SREG_SS;
|
---|
7951 |
|
---|
7952 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
7953 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
7954 | }
|
---|
7955 |
|
---|
7956 |
|
---|
7957 | /** Opcode 0x37. */
|
---|
7958 | FNIEMOP_STUB(iemOp_aaa);
|
---|
7959 |
|
---|
7960 |
|
---|
7961 | /** Opcode 0x38. */
|
---|
7962 | FNIEMOP_DEF(iemOp_cmp_Eb_Gb)
|
---|
7963 | {
|
---|
7964 | IEMOP_MNEMONIC("cmp Eb,Gb");
|
---|
7965 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_cmp);
|
---|
7966 | }
|
---|
7967 |
|
---|
7968 |
|
---|
7969 | /** Opcode 0x39. */
|
---|
7970 | FNIEMOP_DEF(iemOp_cmp_Ev_Gv)
|
---|
7971 | {
|
---|
7972 | IEMOP_MNEMONIC("cmp Ev,Gv");
|
---|
7973 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_cmp);
|
---|
7974 | }
|
---|
7975 |
|
---|
7976 |
|
---|
7977 | /** Opcode 0x3a. */
|
---|
7978 | FNIEMOP_DEF(iemOp_cmp_Gb_Eb)
|
---|
7979 | {
|
---|
7980 | IEMOP_MNEMONIC("cmp Gb,Eb");
|
---|
7981 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_cmp);
|
---|
7982 | }
|
---|
7983 |
|
---|
7984 |
|
---|
7985 | /** Opcode 0x3b. */
|
---|
7986 | FNIEMOP_DEF(iemOp_cmp_Gv_Ev)
|
---|
7987 | {
|
---|
7988 | IEMOP_MNEMONIC("cmp Gv,Ev");
|
---|
7989 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_cmp);
|
---|
7990 | }
|
---|
7991 |
|
---|
7992 |
|
---|
7993 | /** Opcode 0x3c. */
|
---|
7994 | FNIEMOP_DEF(iemOp_cmp_Al_Ib)
|
---|
7995 | {
|
---|
7996 | IEMOP_MNEMONIC("cmp al,Ib");
|
---|
7997 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_cmp);
|
---|
7998 | }
|
---|
7999 |
|
---|
8000 |
|
---|
8001 | /** Opcode 0x3d. */
|
---|
8002 | FNIEMOP_DEF(iemOp_cmp_eAX_Iz)
|
---|
8003 | {
|
---|
8004 | IEMOP_MNEMONIC("cmp rAX,Iz");
|
---|
8005 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_cmp);
|
---|
8006 | }
|
---|
8007 |
|
---|
8008 |
|
---|
8009 | /** Opcode 0x3e. */
|
---|
8010 | FNIEMOP_DEF(iemOp_seg_DS)
|
---|
8011 | {
|
---|
8012 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("seg ds");
|
---|
8013 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SEG_DS;
|
---|
8014 | pVCpu->iem.s.iEffSeg = X86_SREG_DS;
|
---|
8015 |
|
---|
8016 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8017 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8018 | }
|
---|
8019 |
|
---|
8020 |
|
---|
8021 | /** Opcode 0x3f. */
|
---|
8022 | FNIEMOP_STUB(iemOp_aas);
|
---|
8023 |
|
---|
8024 | /**
|
---|
8025 | * Common 'inc/dec/not/neg register' helper.
|
---|
8026 | */
|
---|
8027 | FNIEMOP_DEF_2(iemOpCommonUnaryGReg, PCIEMOPUNARYSIZES, pImpl, uint8_t, iReg)
|
---|
8028 | {
|
---|
8029 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8030 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
8031 | {
|
---|
8032 | case IEMMODE_16BIT:
|
---|
8033 | IEM_MC_BEGIN(2, 0);
|
---|
8034 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
8035 | IEM_MC_ARG(uint32_t *, pEFlags, 1);
|
---|
8036 | IEM_MC_REF_GREG_U16(pu16Dst, iReg);
|
---|
8037 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
8038 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU16, pu16Dst, pEFlags);
|
---|
8039 | IEM_MC_ADVANCE_RIP();
|
---|
8040 | IEM_MC_END();
|
---|
8041 | return VINF_SUCCESS;
|
---|
8042 |
|
---|
8043 | case IEMMODE_32BIT:
|
---|
8044 | IEM_MC_BEGIN(2, 0);
|
---|
8045 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
8046 | IEM_MC_ARG(uint32_t *, pEFlags, 1);
|
---|
8047 | IEM_MC_REF_GREG_U32(pu32Dst, iReg);
|
---|
8048 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
8049 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU32, pu32Dst, pEFlags);
|
---|
8050 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
8051 | IEM_MC_ADVANCE_RIP();
|
---|
8052 | IEM_MC_END();
|
---|
8053 | return VINF_SUCCESS;
|
---|
8054 |
|
---|
8055 | case IEMMODE_64BIT:
|
---|
8056 | IEM_MC_BEGIN(2, 0);
|
---|
8057 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
8058 | IEM_MC_ARG(uint32_t *, pEFlags, 1);
|
---|
8059 | IEM_MC_REF_GREG_U64(pu64Dst, iReg);
|
---|
8060 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
8061 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU64, pu64Dst, pEFlags);
|
---|
8062 | IEM_MC_ADVANCE_RIP();
|
---|
8063 | IEM_MC_END();
|
---|
8064 | return VINF_SUCCESS;
|
---|
8065 | }
|
---|
8066 | return VINF_SUCCESS;
|
---|
8067 | }
|
---|
8068 |
|
---|
8069 |
|
---|
8070 | /** Opcode 0x40. */
|
---|
8071 | FNIEMOP_DEF(iemOp_inc_eAX)
|
---|
8072 | {
|
---|
8073 | /*
|
---|
8074 | * This is a REX prefix in 64-bit mode.
|
---|
8075 | */
|
---|
8076 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8077 | {
|
---|
8078 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex");
|
---|
8079 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX;
|
---|
8080 |
|
---|
8081 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8082 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8083 | }
|
---|
8084 |
|
---|
8085 | IEMOP_MNEMONIC("inc eAX");
|
---|
8086 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xAX);
|
---|
8087 | }
|
---|
8088 |
|
---|
8089 |
|
---|
8090 | /** Opcode 0x41. */
|
---|
8091 | FNIEMOP_DEF(iemOp_inc_eCX)
|
---|
8092 | {
|
---|
8093 | /*
|
---|
8094 | * This is a REX prefix in 64-bit mode.
|
---|
8095 | */
|
---|
8096 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8097 | {
|
---|
8098 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.b");
|
---|
8099 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_B;
|
---|
8100 | pVCpu->iem.s.uRexB = 1 << 3;
|
---|
8101 |
|
---|
8102 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8103 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8104 | }
|
---|
8105 |
|
---|
8106 | IEMOP_MNEMONIC("inc eCX");
|
---|
8107 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xCX);
|
---|
8108 | }
|
---|
8109 |
|
---|
8110 |
|
---|
8111 | /** Opcode 0x42. */
|
---|
8112 | FNIEMOP_DEF(iemOp_inc_eDX)
|
---|
8113 | {
|
---|
8114 | /*
|
---|
8115 | * This is a REX prefix in 64-bit mode.
|
---|
8116 | */
|
---|
8117 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8118 | {
|
---|
8119 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.x");
|
---|
8120 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_X;
|
---|
8121 | pVCpu->iem.s.uRexIndex = 1 << 3;
|
---|
8122 |
|
---|
8123 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8124 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8125 | }
|
---|
8126 |
|
---|
8127 | IEMOP_MNEMONIC("inc eDX");
|
---|
8128 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xDX);
|
---|
8129 | }
|
---|
8130 |
|
---|
8131 |
|
---|
8132 |
|
---|
8133 | /** Opcode 0x43. */
|
---|
8134 | FNIEMOP_DEF(iemOp_inc_eBX)
|
---|
8135 | {
|
---|
8136 | /*
|
---|
8137 | * This is a REX prefix in 64-bit mode.
|
---|
8138 | */
|
---|
8139 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8140 | {
|
---|
8141 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.bx");
|
---|
8142 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X;
|
---|
8143 | pVCpu->iem.s.uRexB = 1 << 3;
|
---|
8144 | pVCpu->iem.s.uRexIndex = 1 << 3;
|
---|
8145 |
|
---|
8146 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8147 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8148 | }
|
---|
8149 |
|
---|
8150 | IEMOP_MNEMONIC("inc eBX");
|
---|
8151 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xBX);
|
---|
8152 | }
|
---|
8153 |
|
---|
8154 |
|
---|
8155 | /** Opcode 0x44. */
|
---|
8156 | FNIEMOP_DEF(iemOp_inc_eSP)
|
---|
8157 | {
|
---|
8158 | /*
|
---|
8159 | * This is a REX prefix in 64-bit mode.
|
---|
8160 | */
|
---|
8161 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8162 | {
|
---|
8163 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.r");
|
---|
8164 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_R;
|
---|
8165 | pVCpu->iem.s.uRexReg = 1 << 3;
|
---|
8166 |
|
---|
8167 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8168 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8169 | }
|
---|
8170 |
|
---|
8171 | IEMOP_MNEMONIC("inc eSP");
|
---|
8172 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xSP);
|
---|
8173 | }
|
---|
8174 |
|
---|
8175 |
|
---|
8176 | /** Opcode 0x45. */
|
---|
8177 | FNIEMOP_DEF(iemOp_inc_eBP)
|
---|
8178 | {
|
---|
8179 | /*
|
---|
8180 | * This is a REX prefix in 64-bit mode.
|
---|
8181 | */
|
---|
8182 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8183 | {
|
---|
8184 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.rb");
|
---|
8185 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B;
|
---|
8186 | pVCpu->iem.s.uRexReg = 1 << 3;
|
---|
8187 | pVCpu->iem.s.uRexB = 1 << 3;
|
---|
8188 |
|
---|
8189 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8190 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8191 | }
|
---|
8192 |
|
---|
8193 | IEMOP_MNEMONIC("inc eBP");
|
---|
8194 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xBP);
|
---|
8195 | }
|
---|
8196 |
|
---|
8197 |
|
---|
8198 | /** Opcode 0x46. */
|
---|
8199 | FNIEMOP_DEF(iemOp_inc_eSI)
|
---|
8200 | {
|
---|
8201 | /*
|
---|
8202 | * This is a REX prefix in 64-bit mode.
|
---|
8203 | */
|
---|
8204 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8205 | {
|
---|
8206 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.rx");
|
---|
8207 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_X;
|
---|
8208 | pVCpu->iem.s.uRexReg = 1 << 3;
|
---|
8209 | pVCpu->iem.s.uRexIndex = 1 << 3;
|
---|
8210 |
|
---|
8211 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8212 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8213 | }
|
---|
8214 |
|
---|
8215 | IEMOP_MNEMONIC("inc eSI");
|
---|
8216 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xSI);
|
---|
8217 | }
|
---|
8218 |
|
---|
8219 |
|
---|
8220 | /** Opcode 0x47. */
|
---|
8221 | FNIEMOP_DEF(iemOp_inc_eDI)
|
---|
8222 | {
|
---|
8223 | /*
|
---|
8224 | * This is a REX prefix in 64-bit mode.
|
---|
8225 | */
|
---|
8226 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8227 | {
|
---|
8228 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.rbx");
|
---|
8229 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X;
|
---|
8230 | pVCpu->iem.s.uRexReg = 1 << 3;
|
---|
8231 | pVCpu->iem.s.uRexB = 1 << 3;
|
---|
8232 | pVCpu->iem.s.uRexIndex = 1 << 3;
|
---|
8233 |
|
---|
8234 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8235 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8236 | }
|
---|
8237 |
|
---|
8238 | IEMOP_MNEMONIC("inc eDI");
|
---|
8239 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xDI);
|
---|
8240 | }
|
---|
8241 |
|
---|
8242 |
|
---|
8243 | /** Opcode 0x48. */
|
---|
8244 | FNIEMOP_DEF(iemOp_dec_eAX)
|
---|
8245 | {
|
---|
8246 | /*
|
---|
8247 | * This is a REX prefix in 64-bit mode.
|
---|
8248 | */
|
---|
8249 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8250 | {
|
---|
8251 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.w");
|
---|
8252 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_SIZE_REX_W;
|
---|
8253 | iemRecalEffOpSize(pVCpu);
|
---|
8254 |
|
---|
8255 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8256 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8257 | }
|
---|
8258 |
|
---|
8259 | IEMOP_MNEMONIC("dec eAX");
|
---|
8260 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xAX);
|
---|
8261 | }
|
---|
8262 |
|
---|
8263 |
|
---|
8264 | /** Opcode 0x49. */
|
---|
8265 | FNIEMOP_DEF(iemOp_dec_eCX)
|
---|
8266 | {
|
---|
8267 | /*
|
---|
8268 | * This is a REX prefix in 64-bit mode.
|
---|
8269 | */
|
---|
8270 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8271 | {
|
---|
8272 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.bw");
|
---|
8273 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_B | IEM_OP_PRF_SIZE_REX_W;
|
---|
8274 | pVCpu->iem.s.uRexB = 1 << 3;
|
---|
8275 | iemRecalEffOpSize(pVCpu);
|
---|
8276 |
|
---|
8277 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8278 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8279 | }
|
---|
8280 |
|
---|
8281 | IEMOP_MNEMONIC("dec eCX");
|
---|
8282 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xCX);
|
---|
8283 | }
|
---|
8284 |
|
---|
8285 |
|
---|
8286 | /** Opcode 0x4a. */
|
---|
8287 | FNIEMOP_DEF(iemOp_dec_eDX)
|
---|
8288 | {
|
---|
8289 | /*
|
---|
8290 | * This is a REX prefix in 64-bit mode.
|
---|
8291 | */
|
---|
8292 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8293 | {
|
---|
8294 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.xw");
|
---|
8295 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W;
|
---|
8296 | pVCpu->iem.s.uRexIndex = 1 << 3;
|
---|
8297 | iemRecalEffOpSize(pVCpu);
|
---|
8298 |
|
---|
8299 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8300 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8301 | }
|
---|
8302 |
|
---|
8303 | IEMOP_MNEMONIC("dec eDX");
|
---|
8304 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xDX);
|
---|
8305 | }
|
---|
8306 |
|
---|
8307 |
|
---|
8308 | /** Opcode 0x4b. */
|
---|
8309 | FNIEMOP_DEF(iemOp_dec_eBX)
|
---|
8310 | {
|
---|
8311 | /*
|
---|
8312 | * This is a REX prefix in 64-bit mode.
|
---|
8313 | */
|
---|
8314 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8315 | {
|
---|
8316 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.bxw");
|
---|
8317 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W;
|
---|
8318 | pVCpu->iem.s.uRexB = 1 << 3;
|
---|
8319 | pVCpu->iem.s.uRexIndex = 1 << 3;
|
---|
8320 | iemRecalEffOpSize(pVCpu);
|
---|
8321 |
|
---|
8322 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8323 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8324 | }
|
---|
8325 |
|
---|
8326 | IEMOP_MNEMONIC("dec eBX");
|
---|
8327 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xBX);
|
---|
8328 | }
|
---|
8329 |
|
---|
8330 |
|
---|
8331 | /** Opcode 0x4c. */
|
---|
8332 | FNIEMOP_DEF(iemOp_dec_eSP)
|
---|
8333 | {
|
---|
8334 | /*
|
---|
8335 | * This is a REX prefix in 64-bit mode.
|
---|
8336 | */
|
---|
8337 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8338 | {
|
---|
8339 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.rw");
|
---|
8340 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_SIZE_REX_W;
|
---|
8341 | pVCpu->iem.s.uRexReg = 1 << 3;
|
---|
8342 | iemRecalEffOpSize(pVCpu);
|
---|
8343 |
|
---|
8344 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8345 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8346 | }
|
---|
8347 |
|
---|
8348 | IEMOP_MNEMONIC("dec eSP");
|
---|
8349 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xSP);
|
---|
8350 | }
|
---|
8351 |
|
---|
8352 |
|
---|
8353 | /** Opcode 0x4d. */
|
---|
8354 | FNIEMOP_DEF(iemOp_dec_eBP)
|
---|
8355 | {
|
---|
8356 | /*
|
---|
8357 | * This is a REX prefix in 64-bit mode.
|
---|
8358 | */
|
---|
8359 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8360 | {
|
---|
8361 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.rbw");
|
---|
8362 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B | IEM_OP_PRF_SIZE_REX_W;
|
---|
8363 | pVCpu->iem.s.uRexReg = 1 << 3;
|
---|
8364 | pVCpu->iem.s.uRexB = 1 << 3;
|
---|
8365 | iemRecalEffOpSize(pVCpu);
|
---|
8366 |
|
---|
8367 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8368 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8369 | }
|
---|
8370 |
|
---|
8371 | IEMOP_MNEMONIC("dec eBP");
|
---|
8372 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xBP);
|
---|
8373 | }
|
---|
8374 |
|
---|
8375 |
|
---|
8376 | /** Opcode 0x4e. */
|
---|
8377 | FNIEMOP_DEF(iemOp_dec_eSI)
|
---|
8378 | {
|
---|
8379 | /*
|
---|
8380 | * This is a REX prefix in 64-bit mode.
|
---|
8381 | */
|
---|
8382 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8383 | {
|
---|
8384 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.rxw");
|
---|
8385 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W;
|
---|
8386 | pVCpu->iem.s.uRexReg = 1 << 3;
|
---|
8387 | pVCpu->iem.s.uRexIndex = 1 << 3;
|
---|
8388 | iemRecalEffOpSize(pVCpu);
|
---|
8389 |
|
---|
8390 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8391 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8392 | }
|
---|
8393 |
|
---|
8394 | IEMOP_MNEMONIC("dec eSI");
|
---|
8395 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xSI);
|
---|
8396 | }
|
---|
8397 |
|
---|
8398 |
|
---|
8399 | /** Opcode 0x4f. */
|
---|
8400 | FNIEMOP_DEF(iemOp_dec_eDI)
|
---|
8401 | {
|
---|
8402 | /*
|
---|
8403 | * This is a REX prefix in 64-bit mode.
|
---|
8404 | */
|
---|
8405 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8406 | {
|
---|
8407 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("rex.rbxw");
|
---|
8408 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W;
|
---|
8409 | pVCpu->iem.s.uRexReg = 1 << 3;
|
---|
8410 | pVCpu->iem.s.uRexB = 1 << 3;
|
---|
8411 | pVCpu->iem.s.uRexIndex = 1 << 3;
|
---|
8412 | iemRecalEffOpSize(pVCpu);
|
---|
8413 |
|
---|
8414 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8415 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8416 | }
|
---|
8417 |
|
---|
8418 | IEMOP_MNEMONIC("dec eDI");
|
---|
8419 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xDI);
|
---|
8420 | }
|
---|
8421 |
|
---|
8422 |
|
---|
8423 | /**
|
---|
8424 | * Common 'push register' helper.
|
---|
8425 | */
|
---|
8426 | FNIEMOP_DEF_1(iemOpCommonPushGReg, uint8_t, iReg)
|
---|
8427 | {
|
---|
8428 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8429 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8430 | {
|
---|
8431 | iReg |= pVCpu->iem.s.uRexB;
|
---|
8432 | pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
|
---|
8433 | pVCpu->iem.s.enmEffOpSize = !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP) ? IEMMODE_64BIT : IEMMODE_16BIT;
|
---|
8434 | }
|
---|
8435 |
|
---|
8436 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
8437 | {
|
---|
8438 | case IEMMODE_16BIT:
|
---|
8439 | IEM_MC_BEGIN(0, 1);
|
---|
8440 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
8441 | IEM_MC_FETCH_GREG_U16(u16Value, iReg);
|
---|
8442 | IEM_MC_PUSH_U16(u16Value);
|
---|
8443 | IEM_MC_ADVANCE_RIP();
|
---|
8444 | IEM_MC_END();
|
---|
8445 | break;
|
---|
8446 |
|
---|
8447 | case IEMMODE_32BIT:
|
---|
8448 | IEM_MC_BEGIN(0, 1);
|
---|
8449 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
8450 | IEM_MC_FETCH_GREG_U32(u32Value, iReg);
|
---|
8451 | IEM_MC_PUSH_U32(u32Value);
|
---|
8452 | IEM_MC_ADVANCE_RIP();
|
---|
8453 | IEM_MC_END();
|
---|
8454 | break;
|
---|
8455 |
|
---|
8456 | case IEMMODE_64BIT:
|
---|
8457 | IEM_MC_BEGIN(0, 1);
|
---|
8458 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
8459 | IEM_MC_FETCH_GREG_U64(u64Value, iReg);
|
---|
8460 | IEM_MC_PUSH_U64(u64Value);
|
---|
8461 | IEM_MC_ADVANCE_RIP();
|
---|
8462 | IEM_MC_END();
|
---|
8463 | break;
|
---|
8464 | }
|
---|
8465 |
|
---|
8466 | return VINF_SUCCESS;
|
---|
8467 | }
|
---|
8468 |
|
---|
8469 |
|
---|
8470 | /** Opcode 0x50. */
|
---|
8471 | FNIEMOP_DEF(iemOp_push_eAX)
|
---|
8472 | {
|
---|
8473 | IEMOP_MNEMONIC("push rAX");
|
---|
8474 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, X86_GREG_xAX);
|
---|
8475 | }
|
---|
8476 |
|
---|
8477 |
|
---|
8478 | /** Opcode 0x51. */
|
---|
8479 | FNIEMOP_DEF(iemOp_push_eCX)
|
---|
8480 | {
|
---|
8481 | IEMOP_MNEMONIC("push rCX");
|
---|
8482 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, X86_GREG_xCX);
|
---|
8483 | }
|
---|
8484 |
|
---|
8485 |
|
---|
8486 | /** Opcode 0x52. */
|
---|
8487 | FNIEMOP_DEF(iemOp_push_eDX)
|
---|
8488 | {
|
---|
8489 | IEMOP_MNEMONIC("push rDX");
|
---|
8490 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, X86_GREG_xDX);
|
---|
8491 | }
|
---|
8492 |
|
---|
8493 |
|
---|
8494 | /** Opcode 0x53. */
|
---|
8495 | FNIEMOP_DEF(iemOp_push_eBX)
|
---|
8496 | {
|
---|
8497 | IEMOP_MNEMONIC("push rBX");
|
---|
8498 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, X86_GREG_xBX);
|
---|
8499 | }
|
---|
8500 |
|
---|
8501 |
|
---|
8502 | /** Opcode 0x54. */
|
---|
8503 | FNIEMOP_DEF(iemOp_push_eSP)
|
---|
8504 | {
|
---|
8505 | IEMOP_MNEMONIC("push rSP");
|
---|
8506 | if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_8086)
|
---|
8507 | {
|
---|
8508 | IEM_MC_BEGIN(0, 1);
|
---|
8509 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
8510 | IEM_MC_FETCH_GREG_U16(u16Value, X86_GREG_xSP);
|
---|
8511 | IEM_MC_SUB_LOCAL_U16(u16Value, 2);
|
---|
8512 | IEM_MC_PUSH_U16(u16Value);
|
---|
8513 | IEM_MC_ADVANCE_RIP();
|
---|
8514 | IEM_MC_END();
|
---|
8515 | }
|
---|
8516 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, X86_GREG_xSP);
|
---|
8517 | }
|
---|
8518 |
|
---|
8519 |
|
---|
8520 | /** Opcode 0x55. */
|
---|
8521 | FNIEMOP_DEF(iemOp_push_eBP)
|
---|
8522 | {
|
---|
8523 | IEMOP_MNEMONIC("push rBP");
|
---|
8524 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, X86_GREG_xBP);
|
---|
8525 | }
|
---|
8526 |
|
---|
8527 |
|
---|
8528 | /** Opcode 0x56. */
|
---|
8529 | FNIEMOP_DEF(iemOp_push_eSI)
|
---|
8530 | {
|
---|
8531 | IEMOP_MNEMONIC("push rSI");
|
---|
8532 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, X86_GREG_xSI);
|
---|
8533 | }
|
---|
8534 |
|
---|
8535 |
|
---|
8536 | /** Opcode 0x57. */
|
---|
8537 | FNIEMOP_DEF(iemOp_push_eDI)
|
---|
8538 | {
|
---|
8539 | IEMOP_MNEMONIC("push rDI");
|
---|
8540 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, X86_GREG_xDI);
|
---|
8541 | }
|
---|
8542 |
|
---|
8543 |
|
---|
8544 | /**
|
---|
8545 | * Common 'pop register' helper.
|
---|
8546 | */
|
---|
8547 | FNIEMOP_DEF_1(iemOpCommonPopGReg, uint8_t, iReg)
|
---|
8548 | {
|
---|
8549 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8550 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8551 | {
|
---|
8552 | iReg |= pVCpu->iem.s.uRexB;
|
---|
8553 | pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
|
---|
8554 | pVCpu->iem.s.enmEffOpSize = !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP) ? IEMMODE_64BIT : IEMMODE_16BIT;
|
---|
8555 | }
|
---|
8556 |
|
---|
8557 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
8558 | {
|
---|
8559 | case IEMMODE_16BIT:
|
---|
8560 | IEM_MC_BEGIN(0, 1);
|
---|
8561 | IEM_MC_LOCAL(uint16_t *, pu16Dst);
|
---|
8562 | IEM_MC_REF_GREG_U16(pu16Dst, iReg);
|
---|
8563 | IEM_MC_POP_U16(pu16Dst);
|
---|
8564 | IEM_MC_ADVANCE_RIP();
|
---|
8565 | IEM_MC_END();
|
---|
8566 | break;
|
---|
8567 |
|
---|
8568 | case IEMMODE_32BIT:
|
---|
8569 | IEM_MC_BEGIN(0, 1);
|
---|
8570 | IEM_MC_LOCAL(uint32_t *, pu32Dst);
|
---|
8571 | IEM_MC_REF_GREG_U32(pu32Dst, iReg);
|
---|
8572 | IEM_MC_POP_U32(pu32Dst);
|
---|
8573 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst); /** @todo testcase*/
|
---|
8574 | IEM_MC_ADVANCE_RIP();
|
---|
8575 | IEM_MC_END();
|
---|
8576 | break;
|
---|
8577 |
|
---|
8578 | case IEMMODE_64BIT:
|
---|
8579 | IEM_MC_BEGIN(0, 1);
|
---|
8580 | IEM_MC_LOCAL(uint64_t *, pu64Dst);
|
---|
8581 | IEM_MC_REF_GREG_U64(pu64Dst, iReg);
|
---|
8582 | IEM_MC_POP_U64(pu64Dst);
|
---|
8583 | IEM_MC_ADVANCE_RIP();
|
---|
8584 | IEM_MC_END();
|
---|
8585 | break;
|
---|
8586 | }
|
---|
8587 |
|
---|
8588 | return VINF_SUCCESS;
|
---|
8589 | }
|
---|
8590 |
|
---|
8591 |
|
---|
8592 | /** Opcode 0x58. */
|
---|
8593 | FNIEMOP_DEF(iemOp_pop_eAX)
|
---|
8594 | {
|
---|
8595 | IEMOP_MNEMONIC("pop rAX");
|
---|
8596 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, X86_GREG_xAX);
|
---|
8597 | }
|
---|
8598 |
|
---|
8599 |
|
---|
8600 | /** Opcode 0x59. */
|
---|
8601 | FNIEMOP_DEF(iemOp_pop_eCX)
|
---|
8602 | {
|
---|
8603 | IEMOP_MNEMONIC("pop rCX");
|
---|
8604 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, X86_GREG_xCX);
|
---|
8605 | }
|
---|
8606 |
|
---|
8607 |
|
---|
8608 | /** Opcode 0x5a. */
|
---|
8609 | FNIEMOP_DEF(iemOp_pop_eDX)
|
---|
8610 | {
|
---|
8611 | IEMOP_MNEMONIC("pop rDX");
|
---|
8612 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, X86_GREG_xDX);
|
---|
8613 | }
|
---|
8614 |
|
---|
8615 |
|
---|
8616 | /** Opcode 0x5b. */
|
---|
8617 | FNIEMOP_DEF(iemOp_pop_eBX)
|
---|
8618 | {
|
---|
8619 | IEMOP_MNEMONIC("pop rBX");
|
---|
8620 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, X86_GREG_xBX);
|
---|
8621 | }
|
---|
8622 |
|
---|
8623 |
|
---|
8624 | /** Opcode 0x5c. */
|
---|
8625 | FNIEMOP_DEF(iemOp_pop_eSP)
|
---|
8626 | {
|
---|
8627 | IEMOP_MNEMONIC("pop rSP");
|
---|
8628 | if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
|
---|
8629 | {
|
---|
8630 | if (pVCpu->iem.s.uRexB)
|
---|
8631 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, X86_GREG_xSP);
|
---|
8632 | pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
|
---|
8633 | pVCpu->iem.s.enmEffOpSize = !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP) ? IEMMODE_64BIT : IEMMODE_16BIT;
|
---|
8634 | }
|
---|
8635 |
|
---|
8636 | IEMOP_HLP_DECODED_NL_1(OP_POP, IEMOPFORM_FIXED, OP_PARM_REG_ESP,
|
---|
8637 | DISOPTYPE_HARMLESS | DISOPTYPE_DEFAULT_64_OP_SIZE | DISOPTYPE_REXB_EXTENDS_OPREG);
|
---|
8638 | /** @todo add testcase for this instruction. */
|
---|
8639 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
8640 | {
|
---|
8641 | case IEMMODE_16BIT:
|
---|
8642 | IEM_MC_BEGIN(0, 1);
|
---|
8643 | IEM_MC_LOCAL(uint16_t, u16Dst);
|
---|
8644 | IEM_MC_POP_U16(&u16Dst); /** @todo not correct MC, fix later. */
|
---|
8645 | IEM_MC_STORE_GREG_U16(X86_GREG_xSP, u16Dst);
|
---|
8646 | IEM_MC_ADVANCE_RIP();
|
---|
8647 | IEM_MC_END();
|
---|
8648 | break;
|
---|
8649 |
|
---|
8650 | case IEMMODE_32BIT:
|
---|
8651 | IEM_MC_BEGIN(0, 1);
|
---|
8652 | IEM_MC_LOCAL(uint32_t, u32Dst);
|
---|
8653 | IEM_MC_POP_U32(&u32Dst);
|
---|
8654 | IEM_MC_STORE_GREG_U32(X86_GREG_xSP, u32Dst);
|
---|
8655 | IEM_MC_ADVANCE_RIP();
|
---|
8656 | IEM_MC_END();
|
---|
8657 | break;
|
---|
8658 |
|
---|
8659 | case IEMMODE_64BIT:
|
---|
8660 | IEM_MC_BEGIN(0, 1);
|
---|
8661 | IEM_MC_LOCAL(uint64_t, u64Dst);
|
---|
8662 | IEM_MC_POP_U64(&u64Dst);
|
---|
8663 | IEM_MC_STORE_GREG_U64(X86_GREG_xSP, u64Dst);
|
---|
8664 | IEM_MC_ADVANCE_RIP();
|
---|
8665 | IEM_MC_END();
|
---|
8666 | break;
|
---|
8667 | }
|
---|
8668 |
|
---|
8669 | return VINF_SUCCESS;
|
---|
8670 | }
|
---|
8671 |
|
---|
8672 |
|
---|
8673 | /** Opcode 0x5d. */
|
---|
8674 | FNIEMOP_DEF(iemOp_pop_eBP)
|
---|
8675 | {
|
---|
8676 | IEMOP_MNEMONIC("pop rBP");
|
---|
8677 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, X86_GREG_xBP);
|
---|
8678 | }
|
---|
8679 |
|
---|
8680 |
|
---|
8681 | /** Opcode 0x5e. */
|
---|
8682 | FNIEMOP_DEF(iemOp_pop_eSI)
|
---|
8683 | {
|
---|
8684 | IEMOP_MNEMONIC("pop rSI");
|
---|
8685 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, X86_GREG_xSI);
|
---|
8686 | }
|
---|
8687 |
|
---|
8688 |
|
---|
8689 | /** Opcode 0x5f. */
|
---|
8690 | FNIEMOP_DEF(iemOp_pop_eDI)
|
---|
8691 | {
|
---|
8692 | IEMOP_MNEMONIC("pop rDI");
|
---|
8693 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, X86_GREG_xDI);
|
---|
8694 | }
|
---|
8695 |
|
---|
8696 |
|
---|
8697 | /** Opcode 0x60. */
|
---|
8698 | FNIEMOP_DEF(iemOp_pusha)
|
---|
8699 | {
|
---|
8700 | IEMOP_MNEMONIC("pusha");
|
---|
8701 | IEMOP_HLP_MIN_186();
|
---|
8702 | IEMOP_HLP_NO_64BIT();
|
---|
8703 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
8704 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_pusha_16);
|
---|
8705 | Assert(pVCpu->iem.s.enmEffOpSize == IEMMODE_32BIT);
|
---|
8706 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_pusha_32);
|
---|
8707 | }
|
---|
8708 |
|
---|
8709 |
|
---|
8710 | /** Opcode 0x61. */
|
---|
8711 | FNIEMOP_DEF(iemOp_popa)
|
---|
8712 | {
|
---|
8713 | IEMOP_MNEMONIC("popa");
|
---|
8714 | IEMOP_HLP_MIN_186();
|
---|
8715 | IEMOP_HLP_NO_64BIT();
|
---|
8716 | if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
|
---|
8717 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_popa_16);
|
---|
8718 | Assert(pVCpu->iem.s.enmEffOpSize == IEMMODE_32BIT);
|
---|
8719 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_popa_32);
|
---|
8720 | }
|
---|
8721 |
|
---|
8722 |
|
---|
8723 | /** Opcode 0x62. */
|
---|
8724 | FNIEMOP_STUB(iemOp_bound_Gv_Ma_evex);
|
---|
8725 | // IEMOP_HLP_MIN_186();
|
---|
8726 |
|
---|
8727 |
|
---|
8728 | /** Opcode 0x63 - non-64-bit modes. */
|
---|
8729 | FNIEMOP_DEF(iemOp_arpl_Ew_Gw)
|
---|
8730 | {
|
---|
8731 | IEMOP_MNEMONIC("arpl Ew,Gw");
|
---|
8732 | IEMOP_HLP_MIN_286();
|
---|
8733 | IEMOP_HLP_NO_REAL_OR_V86_MODE();
|
---|
8734 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
8735 |
|
---|
8736 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
8737 | {
|
---|
8738 | /* Register */
|
---|
8739 | IEMOP_HLP_DECODED_NL_2(OP_ARPL, IEMOPFORM_MR_REG, OP_PARM_Ew, OP_PARM_Gw, DISOPTYPE_HARMLESS);
|
---|
8740 | IEM_MC_BEGIN(3, 0);
|
---|
8741 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
8742 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
8743 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
8744 |
|
---|
8745 | IEM_MC_FETCH_GREG_U16(u16Src, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
8746 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK));
|
---|
8747 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
8748 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_arpl, pu16Dst, u16Src, pEFlags);
|
---|
8749 |
|
---|
8750 | IEM_MC_ADVANCE_RIP();
|
---|
8751 | IEM_MC_END();
|
---|
8752 | }
|
---|
8753 | else
|
---|
8754 | {
|
---|
8755 | /* Memory */
|
---|
8756 | IEM_MC_BEGIN(3, 2);
|
---|
8757 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
8758 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
8759 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
8760 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
8761 |
|
---|
8762 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
8763 | IEMOP_HLP_DECODED_NL_2(OP_ARPL, IEMOPFORM_MR_REG, OP_PARM_Ew, OP_PARM_Gw, DISOPTYPE_HARMLESS);
|
---|
8764 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
8765 | IEM_MC_FETCH_GREG_U16(u16Src, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
8766 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
8767 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_arpl, pu16Dst, u16Src, pEFlags);
|
---|
8768 |
|
---|
8769 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
8770 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
8771 | IEM_MC_ADVANCE_RIP();
|
---|
8772 | IEM_MC_END();
|
---|
8773 | }
|
---|
8774 | return VINF_SUCCESS;
|
---|
8775 |
|
---|
8776 | }
|
---|
8777 |
|
---|
8778 |
|
---|
8779 | /** Opcode 0x63.
|
---|
8780 | * @note This is a weird one. It works like a regular move instruction if
|
---|
8781 | * REX.W isn't set, at least according to AMD docs (rev 3.15, 2009-11).
|
---|
8782 | * @todo This definitely needs a testcase to verify the odd cases. */
|
---|
8783 | FNIEMOP_DEF(iemOp_movsxd_Gv_Ev)
|
---|
8784 | {
|
---|
8785 | Assert(pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT); /* Caller branched already . */
|
---|
8786 |
|
---|
8787 | IEMOP_MNEMONIC("movsxd Gv,Ev");
|
---|
8788 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
8789 |
|
---|
8790 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
8791 | {
|
---|
8792 | /*
|
---|
8793 | * Register to register.
|
---|
8794 | */
|
---|
8795 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8796 | IEM_MC_BEGIN(0, 1);
|
---|
8797 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
8798 | IEM_MC_FETCH_GREG_U32_SX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
8799 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
8800 | IEM_MC_ADVANCE_RIP();
|
---|
8801 | IEM_MC_END();
|
---|
8802 | }
|
---|
8803 | else
|
---|
8804 | {
|
---|
8805 | /*
|
---|
8806 | * We're loading a register from memory.
|
---|
8807 | */
|
---|
8808 | IEM_MC_BEGIN(0, 2);
|
---|
8809 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
8810 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
8811 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
8812 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8813 | IEM_MC_FETCH_MEM_U32_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
8814 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
8815 | IEM_MC_ADVANCE_RIP();
|
---|
8816 | IEM_MC_END();
|
---|
8817 | }
|
---|
8818 | return VINF_SUCCESS;
|
---|
8819 | }
|
---|
8820 |
|
---|
8821 |
|
---|
8822 | /** Opcode 0x64. */
|
---|
8823 | FNIEMOP_DEF(iemOp_seg_FS)
|
---|
8824 | {
|
---|
8825 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("seg fs");
|
---|
8826 | IEMOP_HLP_MIN_386();
|
---|
8827 |
|
---|
8828 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SEG_FS;
|
---|
8829 | pVCpu->iem.s.iEffSeg = X86_SREG_FS;
|
---|
8830 |
|
---|
8831 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8832 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8833 | }
|
---|
8834 |
|
---|
8835 |
|
---|
8836 | /** Opcode 0x65. */
|
---|
8837 | FNIEMOP_DEF(iemOp_seg_GS)
|
---|
8838 | {
|
---|
8839 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("seg gs");
|
---|
8840 | IEMOP_HLP_MIN_386();
|
---|
8841 |
|
---|
8842 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SEG_GS;
|
---|
8843 | pVCpu->iem.s.iEffSeg = X86_SREG_GS;
|
---|
8844 |
|
---|
8845 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8846 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8847 | }
|
---|
8848 |
|
---|
8849 |
|
---|
8850 | /** Opcode 0x66. */
|
---|
8851 | FNIEMOP_DEF(iemOp_op_size)
|
---|
8852 | {
|
---|
8853 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("op size");
|
---|
8854 | IEMOP_HLP_MIN_386();
|
---|
8855 |
|
---|
8856 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SIZE_OP;
|
---|
8857 | iemRecalEffOpSize(pVCpu);
|
---|
8858 |
|
---|
8859 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8860 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8861 | }
|
---|
8862 |
|
---|
8863 |
|
---|
8864 | /** Opcode 0x67. */
|
---|
8865 | FNIEMOP_DEF(iemOp_addr_size)
|
---|
8866 | {
|
---|
8867 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("addr size");
|
---|
8868 | IEMOP_HLP_MIN_386();
|
---|
8869 |
|
---|
8870 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SIZE_ADDR;
|
---|
8871 | switch (pVCpu->iem.s.enmDefAddrMode)
|
---|
8872 | {
|
---|
8873 | case IEMMODE_16BIT: pVCpu->iem.s.enmEffAddrMode = IEMMODE_32BIT; break;
|
---|
8874 | case IEMMODE_32BIT: pVCpu->iem.s.enmEffAddrMode = IEMMODE_16BIT; break;
|
---|
8875 | case IEMMODE_64BIT: pVCpu->iem.s.enmEffAddrMode = IEMMODE_32BIT; break;
|
---|
8876 | default: AssertFailed();
|
---|
8877 | }
|
---|
8878 |
|
---|
8879 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
8880 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
8881 | }
|
---|
8882 |
|
---|
8883 |
|
---|
8884 | /** Opcode 0x68. */
|
---|
8885 | FNIEMOP_DEF(iemOp_push_Iz)
|
---|
8886 | {
|
---|
8887 | IEMOP_MNEMONIC("push Iz");
|
---|
8888 | IEMOP_HLP_MIN_186();
|
---|
8889 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
8890 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
8891 | {
|
---|
8892 | case IEMMODE_16BIT:
|
---|
8893 | {
|
---|
8894 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
8895 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8896 | IEM_MC_BEGIN(0,0);
|
---|
8897 | IEM_MC_PUSH_U16(u16Imm);
|
---|
8898 | IEM_MC_ADVANCE_RIP();
|
---|
8899 | IEM_MC_END();
|
---|
8900 | return VINF_SUCCESS;
|
---|
8901 | }
|
---|
8902 |
|
---|
8903 | case IEMMODE_32BIT:
|
---|
8904 | {
|
---|
8905 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
8906 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8907 | IEM_MC_BEGIN(0,0);
|
---|
8908 | IEM_MC_PUSH_U32(u32Imm);
|
---|
8909 | IEM_MC_ADVANCE_RIP();
|
---|
8910 | IEM_MC_END();
|
---|
8911 | return VINF_SUCCESS;
|
---|
8912 | }
|
---|
8913 |
|
---|
8914 | case IEMMODE_64BIT:
|
---|
8915 | {
|
---|
8916 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
8917 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8918 | IEM_MC_BEGIN(0,0);
|
---|
8919 | IEM_MC_PUSH_U64(u64Imm);
|
---|
8920 | IEM_MC_ADVANCE_RIP();
|
---|
8921 | IEM_MC_END();
|
---|
8922 | return VINF_SUCCESS;
|
---|
8923 | }
|
---|
8924 |
|
---|
8925 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
8926 | }
|
---|
8927 | }
|
---|
8928 |
|
---|
8929 |
|
---|
8930 | /** Opcode 0x69. */
|
---|
8931 | FNIEMOP_DEF(iemOp_imul_Gv_Ev_Iz)
|
---|
8932 | {
|
---|
8933 | IEMOP_MNEMONIC("imul Gv,Ev,Iz"); /* Gv = Ev * Iz; */
|
---|
8934 | IEMOP_HLP_MIN_186();
|
---|
8935 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
8936 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
8937 |
|
---|
8938 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
8939 | {
|
---|
8940 | case IEMMODE_16BIT:
|
---|
8941 | {
|
---|
8942 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
8943 | {
|
---|
8944 | /* register operand */
|
---|
8945 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
8946 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8947 |
|
---|
8948 | IEM_MC_BEGIN(3, 1);
|
---|
8949 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
8950 | IEM_MC_ARG_CONST(uint16_t, u16Src,/*=*/ u16Imm,1);
|
---|
8951 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
8952 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
8953 |
|
---|
8954 | IEM_MC_FETCH_GREG_U16(u16Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
8955 | IEM_MC_REF_LOCAL(pu16Dst, u16Tmp);
|
---|
8956 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
8957 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u16, pu16Dst, u16Src, pEFlags);
|
---|
8958 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Tmp);
|
---|
8959 |
|
---|
8960 | IEM_MC_ADVANCE_RIP();
|
---|
8961 | IEM_MC_END();
|
---|
8962 | }
|
---|
8963 | else
|
---|
8964 | {
|
---|
8965 | /* memory operand */
|
---|
8966 | IEM_MC_BEGIN(3, 2);
|
---|
8967 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
8968 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
8969 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
8970 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
8971 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
8972 |
|
---|
8973 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 2);
|
---|
8974 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
8975 | IEM_MC_ASSIGN(u16Src, u16Imm);
|
---|
8976 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8977 | IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
8978 | IEM_MC_REF_LOCAL(pu16Dst, u16Tmp);
|
---|
8979 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
8980 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u16, pu16Dst, u16Src, pEFlags);
|
---|
8981 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Tmp);
|
---|
8982 |
|
---|
8983 | IEM_MC_ADVANCE_RIP();
|
---|
8984 | IEM_MC_END();
|
---|
8985 | }
|
---|
8986 | return VINF_SUCCESS;
|
---|
8987 | }
|
---|
8988 |
|
---|
8989 | case IEMMODE_32BIT:
|
---|
8990 | {
|
---|
8991 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
8992 | {
|
---|
8993 | /* register operand */
|
---|
8994 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
8995 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
8996 |
|
---|
8997 | IEM_MC_BEGIN(3, 1);
|
---|
8998 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
8999 | IEM_MC_ARG_CONST(uint32_t, u32Src,/*=*/ u32Imm,1);
|
---|
9000 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9001 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
9002 |
|
---|
9003 | IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9004 | IEM_MC_REF_LOCAL(pu32Dst, u32Tmp);
|
---|
9005 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9006 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u32, pu32Dst, u32Src, pEFlags);
|
---|
9007 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
|
---|
9008 |
|
---|
9009 | IEM_MC_ADVANCE_RIP();
|
---|
9010 | IEM_MC_END();
|
---|
9011 | }
|
---|
9012 | else
|
---|
9013 | {
|
---|
9014 | /* memory operand */
|
---|
9015 | IEM_MC_BEGIN(3, 2);
|
---|
9016 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
9017 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
9018 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9019 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
9020 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9021 |
|
---|
9022 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
|
---|
9023 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
9024 | IEM_MC_ASSIGN(u32Src, u32Imm);
|
---|
9025 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9026 | IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
9027 | IEM_MC_REF_LOCAL(pu32Dst, u32Tmp);
|
---|
9028 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9029 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u32, pu32Dst, u32Src, pEFlags);
|
---|
9030 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
|
---|
9031 |
|
---|
9032 | IEM_MC_ADVANCE_RIP();
|
---|
9033 | IEM_MC_END();
|
---|
9034 | }
|
---|
9035 | return VINF_SUCCESS;
|
---|
9036 | }
|
---|
9037 |
|
---|
9038 | case IEMMODE_64BIT:
|
---|
9039 | {
|
---|
9040 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
9041 | {
|
---|
9042 | /* register operand */
|
---|
9043 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
9044 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9045 |
|
---|
9046 | IEM_MC_BEGIN(3, 1);
|
---|
9047 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
9048 | IEM_MC_ARG_CONST(uint64_t, u64Src,/*=*/ u64Imm,1);
|
---|
9049 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9050 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
9051 |
|
---|
9052 | IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9053 | IEM_MC_REF_LOCAL(pu64Dst, u64Tmp);
|
---|
9054 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9055 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u64, pu64Dst, u64Src, pEFlags);
|
---|
9056 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
|
---|
9057 |
|
---|
9058 | IEM_MC_ADVANCE_RIP();
|
---|
9059 | IEM_MC_END();
|
---|
9060 | }
|
---|
9061 | else
|
---|
9062 | {
|
---|
9063 | /* memory operand */
|
---|
9064 | IEM_MC_BEGIN(3, 2);
|
---|
9065 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
9066 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
9067 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9068 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
9069 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9070 |
|
---|
9071 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
|
---|
9072 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
9073 | IEM_MC_ASSIGN(u64Src, u64Imm);
|
---|
9074 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9075 | IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
9076 | IEM_MC_REF_LOCAL(pu64Dst, u64Tmp);
|
---|
9077 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9078 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u64, pu64Dst, u64Src, pEFlags);
|
---|
9079 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
|
---|
9080 |
|
---|
9081 | IEM_MC_ADVANCE_RIP();
|
---|
9082 | IEM_MC_END();
|
---|
9083 | }
|
---|
9084 | return VINF_SUCCESS;
|
---|
9085 | }
|
---|
9086 | }
|
---|
9087 | AssertFailedReturn(VERR_IEM_IPE_9);
|
---|
9088 | }
|
---|
9089 |
|
---|
9090 |
|
---|
9091 | /** Opcode 0x6a. */
|
---|
9092 | FNIEMOP_DEF(iemOp_push_Ib)
|
---|
9093 | {
|
---|
9094 | IEMOP_MNEMONIC("push Ib");
|
---|
9095 | IEMOP_HLP_MIN_186();
|
---|
9096 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9097 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9098 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9099 |
|
---|
9100 | IEM_MC_BEGIN(0,0);
|
---|
9101 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
9102 | {
|
---|
9103 | case IEMMODE_16BIT:
|
---|
9104 | IEM_MC_PUSH_U16(i8Imm);
|
---|
9105 | break;
|
---|
9106 | case IEMMODE_32BIT:
|
---|
9107 | IEM_MC_PUSH_U32(i8Imm);
|
---|
9108 | break;
|
---|
9109 | case IEMMODE_64BIT:
|
---|
9110 | IEM_MC_PUSH_U64(i8Imm);
|
---|
9111 | break;
|
---|
9112 | }
|
---|
9113 | IEM_MC_ADVANCE_RIP();
|
---|
9114 | IEM_MC_END();
|
---|
9115 | return VINF_SUCCESS;
|
---|
9116 | }
|
---|
9117 |
|
---|
9118 |
|
---|
9119 | /** Opcode 0x6b. */
|
---|
9120 | FNIEMOP_DEF(iemOp_imul_Gv_Ev_Ib)
|
---|
9121 | {
|
---|
9122 | IEMOP_MNEMONIC("imul Gv,Ev,Ib"); /* Gv = Ev * Iz; */
|
---|
9123 | IEMOP_HLP_MIN_186();
|
---|
9124 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
9125 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
9126 |
|
---|
9127 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
9128 | {
|
---|
9129 | case IEMMODE_16BIT:
|
---|
9130 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
9131 | {
|
---|
9132 | /* register operand */
|
---|
9133 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
9134 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9135 |
|
---|
9136 | IEM_MC_BEGIN(3, 1);
|
---|
9137 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
9138 | IEM_MC_ARG_CONST(uint16_t, u16Src,/*=*/ (int8_t)u8Imm, 1);
|
---|
9139 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9140 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
9141 |
|
---|
9142 | IEM_MC_FETCH_GREG_U16(u16Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9143 | IEM_MC_REF_LOCAL(pu16Dst, u16Tmp);
|
---|
9144 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9145 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u16, pu16Dst, u16Src, pEFlags);
|
---|
9146 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Tmp);
|
---|
9147 |
|
---|
9148 | IEM_MC_ADVANCE_RIP();
|
---|
9149 | IEM_MC_END();
|
---|
9150 | }
|
---|
9151 | else
|
---|
9152 | {
|
---|
9153 | /* memory operand */
|
---|
9154 | IEM_MC_BEGIN(3, 2);
|
---|
9155 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
9156 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
9157 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9158 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
9159 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9160 |
|
---|
9161 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
9162 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_S8_SX_U16(&u16Imm);
|
---|
9163 | IEM_MC_ASSIGN(u16Src, u16Imm);
|
---|
9164 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9165 | IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
9166 | IEM_MC_REF_LOCAL(pu16Dst, u16Tmp);
|
---|
9167 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9168 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u16, pu16Dst, u16Src, pEFlags);
|
---|
9169 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Tmp);
|
---|
9170 |
|
---|
9171 | IEM_MC_ADVANCE_RIP();
|
---|
9172 | IEM_MC_END();
|
---|
9173 | }
|
---|
9174 | return VINF_SUCCESS;
|
---|
9175 |
|
---|
9176 | case IEMMODE_32BIT:
|
---|
9177 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
9178 | {
|
---|
9179 | /* register operand */
|
---|
9180 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
9181 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9182 |
|
---|
9183 | IEM_MC_BEGIN(3, 1);
|
---|
9184 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
9185 | IEM_MC_ARG_CONST(uint32_t, u32Src,/*=*/ (int8_t)u8Imm, 1);
|
---|
9186 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9187 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
9188 |
|
---|
9189 | IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9190 | IEM_MC_REF_LOCAL(pu32Dst, u32Tmp);
|
---|
9191 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9192 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u32, pu32Dst, u32Src, pEFlags);
|
---|
9193 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
|
---|
9194 |
|
---|
9195 | IEM_MC_ADVANCE_RIP();
|
---|
9196 | IEM_MC_END();
|
---|
9197 | }
|
---|
9198 | else
|
---|
9199 | {
|
---|
9200 | /* memory operand */
|
---|
9201 | IEM_MC_BEGIN(3, 2);
|
---|
9202 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
9203 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
9204 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9205 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
9206 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9207 |
|
---|
9208 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
9209 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_S8_SX_U32(&u32Imm);
|
---|
9210 | IEM_MC_ASSIGN(u32Src, u32Imm);
|
---|
9211 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9212 | IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
9213 | IEM_MC_REF_LOCAL(pu32Dst, u32Tmp);
|
---|
9214 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9215 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u32, pu32Dst, u32Src, pEFlags);
|
---|
9216 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
|
---|
9217 |
|
---|
9218 | IEM_MC_ADVANCE_RIP();
|
---|
9219 | IEM_MC_END();
|
---|
9220 | }
|
---|
9221 | return VINF_SUCCESS;
|
---|
9222 |
|
---|
9223 | case IEMMODE_64BIT:
|
---|
9224 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
9225 | {
|
---|
9226 | /* register operand */
|
---|
9227 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
9228 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9229 |
|
---|
9230 | IEM_MC_BEGIN(3, 1);
|
---|
9231 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
9232 | IEM_MC_ARG_CONST(uint64_t, u64Src,/*=*/ (int8_t)u8Imm, 1);
|
---|
9233 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9234 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
9235 |
|
---|
9236 | IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9237 | IEM_MC_REF_LOCAL(pu64Dst, u64Tmp);
|
---|
9238 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9239 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u64, pu64Dst, u64Src, pEFlags);
|
---|
9240 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
|
---|
9241 |
|
---|
9242 | IEM_MC_ADVANCE_RIP();
|
---|
9243 | IEM_MC_END();
|
---|
9244 | }
|
---|
9245 | else
|
---|
9246 | {
|
---|
9247 | /* memory operand */
|
---|
9248 | IEM_MC_BEGIN(3, 2);
|
---|
9249 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
9250 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
9251 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9252 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
9253 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9254 |
|
---|
9255 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
9256 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S8_SX_U64(&u64Imm);
|
---|
9257 | IEM_MC_ASSIGN(u64Src, u64Imm);
|
---|
9258 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9259 | IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
9260 | IEM_MC_REF_LOCAL(pu64Dst, u64Tmp);
|
---|
9261 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9262 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_imul_two_u64, pu64Dst, u64Src, pEFlags);
|
---|
9263 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
|
---|
9264 |
|
---|
9265 | IEM_MC_ADVANCE_RIP();
|
---|
9266 | IEM_MC_END();
|
---|
9267 | }
|
---|
9268 | return VINF_SUCCESS;
|
---|
9269 | }
|
---|
9270 | AssertFailedReturn(VERR_IEM_IPE_8);
|
---|
9271 | }
|
---|
9272 |
|
---|
9273 |
|
---|
9274 | /** Opcode 0x6c. */
|
---|
9275 | FNIEMOP_DEF(iemOp_insb_Yb_DX)
|
---|
9276 | {
|
---|
9277 | IEMOP_HLP_MIN_186();
|
---|
9278 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9279 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
9280 | {
|
---|
9281 | IEMOP_MNEMONIC("rep ins Yb,DX");
|
---|
9282 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9283 | {
|
---|
9284 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op8_addr16, false);
|
---|
9285 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op8_addr32, false);
|
---|
9286 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op8_addr64, false);
|
---|
9287 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9288 | }
|
---|
9289 | }
|
---|
9290 | else
|
---|
9291 | {
|
---|
9292 | IEMOP_MNEMONIC("ins Yb,DX");
|
---|
9293 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9294 | {
|
---|
9295 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op8_addr16, false);
|
---|
9296 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op8_addr32, false);
|
---|
9297 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op8_addr64, false);
|
---|
9298 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9299 | }
|
---|
9300 | }
|
---|
9301 | }
|
---|
9302 |
|
---|
9303 |
|
---|
9304 | /** Opcode 0x6d. */
|
---|
9305 | FNIEMOP_DEF(iemOp_inswd_Yv_DX)
|
---|
9306 | {
|
---|
9307 | IEMOP_HLP_MIN_186();
|
---|
9308 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9309 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
9310 | {
|
---|
9311 | IEMOP_MNEMONIC("rep ins Yv,DX");
|
---|
9312 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
9313 | {
|
---|
9314 | case IEMMODE_16BIT:
|
---|
9315 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9316 | {
|
---|
9317 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op16_addr16, false);
|
---|
9318 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op16_addr32, false);
|
---|
9319 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op16_addr64, false);
|
---|
9320 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9321 | }
|
---|
9322 | break;
|
---|
9323 | case IEMMODE_64BIT:
|
---|
9324 | case IEMMODE_32BIT:
|
---|
9325 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9326 | {
|
---|
9327 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op32_addr16, false);
|
---|
9328 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op32_addr32, false);
|
---|
9329 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_ins_op32_addr64, false);
|
---|
9330 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9331 | }
|
---|
9332 | break;
|
---|
9333 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9334 | }
|
---|
9335 | }
|
---|
9336 | else
|
---|
9337 | {
|
---|
9338 | IEMOP_MNEMONIC("ins Yv,DX");
|
---|
9339 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
9340 | {
|
---|
9341 | case IEMMODE_16BIT:
|
---|
9342 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9343 | {
|
---|
9344 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op16_addr16, false);
|
---|
9345 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op16_addr32, false);
|
---|
9346 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op16_addr64, false);
|
---|
9347 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9348 | }
|
---|
9349 | break;
|
---|
9350 | case IEMMODE_64BIT:
|
---|
9351 | case IEMMODE_32BIT:
|
---|
9352 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9353 | {
|
---|
9354 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op32_addr16, false);
|
---|
9355 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op32_addr32, false);
|
---|
9356 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_ins_op32_addr64, false);
|
---|
9357 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9358 | }
|
---|
9359 | break;
|
---|
9360 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9361 | }
|
---|
9362 | }
|
---|
9363 | }
|
---|
9364 |
|
---|
9365 |
|
---|
9366 | /** Opcode 0x6e. */
|
---|
9367 | FNIEMOP_DEF(iemOp_outsb_Yb_DX)
|
---|
9368 | {
|
---|
9369 | IEMOP_HLP_MIN_186();
|
---|
9370 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9371 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
9372 | {
|
---|
9373 | IEMOP_MNEMONIC("rep outs DX,Yb");
|
---|
9374 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9375 | {
|
---|
9376 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false);
|
---|
9377 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false);
|
---|
9378 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false);
|
---|
9379 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9380 | }
|
---|
9381 | }
|
---|
9382 | else
|
---|
9383 | {
|
---|
9384 | IEMOP_MNEMONIC("outs DX,Yb");
|
---|
9385 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9386 | {
|
---|
9387 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op8_addr16, pVCpu->iem.s.iEffSeg, false);
|
---|
9388 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op8_addr32, pVCpu->iem.s.iEffSeg, false);
|
---|
9389 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op8_addr64, pVCpu->iem.s.iEffSeg, false);
|
---|
9390 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9391 | }
|
---|
9392 | }
|
---|
9393 | }
|
---|
9394 |
|
---|
9395 |
|
---|
9396 | /** Opcode 0x6f. */
|
---|
9397 | FNIEMOP_DEF(iemOp_outswd_Yv_DX)
|
---|
9398 | {
|
---|
9399 | IEMOP_HLP_MIN_186();
|
---|
9400 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9401 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ))
|
---|
9402 | {
|
---|
9403 | IEMOP_MNEMONIC("rep outs DX,Yv");
|
---|
9404 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
9405 | {
|
---|
9406 | case IEMMODE_16BIT:
|
---|
9407 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9408 | {
|
---|
9409 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false);
|
---|
9410 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false);
|
---|
9411 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false);
|
---|
9412 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9413 | }
|
---|
9414 | break;
|
---|
9415 | case IEMMODE_64BIT:
|
---|
9416 | case IEMMODE_32BIT:
|
---|
9417 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9418 | {
|
---|
9419 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false);
|
---|
9420 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false);
|
---|
9421 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_rep_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false);
|
---|
9422 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9423 | }
|
---|
9424 | break;
|
---|
9425 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9426 | }
|
---|
9427 | }
|
---|
9428 | else
|
---|
9429 | {
|
---|
9430 | IEMOP_MNEMONIC("outs DX,Yv");
|
---|
9431 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
9432 | {
|
---|
9433 | case IEMMODE_16BIT:
|
---|
9434 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9435 | {
|
---|
9436 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op16_addr16, pVCpu->iem.s.iEffSeg, false);
|
---|
9437 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op16_addr32, pVCpu->iem.s.iEffSeg, false);
|
---|
9438 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op16_addr64, pVCpu->iem.s.iEffSeg, false);
|
---|
9439 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9440 | }
|
---|
9441 | break;
|
---|
9442 | case IEMMODE_64BIT:
|
---|
9443 | case IEMMODE_32BIT:
|
---|
9444 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
9445 | {
|
---|
9446 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op32_addr16, pVCpu->iem.s.iEffSeg, false);
|
---|
9447 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op32_addr32, pVCpu->iem.s.iEffSeg, false);
|
---|
9448 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_outs_op32_addr64, pVCpu->iem.s.iEffSeg, false);
|
---|
9449 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9450 | }
|
---|
9451 | break;
|
---|
9452 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
9453 | }
|
---|
9454 | }
|
---|
9455 | }
|
---|
9456 |
|
---|
9457 |
|
---|
9458 | /** Opcode 0x70. */
|
---|
9459 | FNIEMOP_DEF(iemOp_jo_Jb)
|
---|
9460 | {
|
---|
9461 | IEMOP_MNEMONIC("jo Jb");
|
---|
9462 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9463 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9464 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9465 |
|
---|
9466 | IEM_MC_BEGIN(0, 0);
|
---|
9467 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
9468 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9469 | } IEM_MC_ELSE() {
|
---|
9470 | IEM_MC_ADVANCE_RIP();
|
---|
9471 | } IEM_MC_ENDIF();
|
---|
9472 | IEM_MC_END();
|
---|
9473 | return VINF_SUCCESS;
|
---|
9474 | }
|
---|
9475 |
|
---|
9476 |
|
---|
9477 | /** Opcode 0x71. */
|
---|
9478 | FNIEMOP_DEF(iemOp_jno_Jb)
|
---|
9479 | {
|
---|
9480 | IEMOP_MNEMONIC("jno Jb");
|
---|
9481 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9482 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9483 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9484 |
|
---|
9485 | IEM_MC_BEGIN(0, 0);
|
---|
9486 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
|
---|
9487 | IEM_MC_ADVANCE_RIP();
|
---|
9488 | } IEM_MC_ELSE() {
|
---|
9489 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9490 | } IEM_MC_ENDIF();
|
---|
9491 | IEM_MC_END();
|
---|
9492 | return VINF_SUCCESS;
|
---|
9493 | }
|
---|
9494 |
|
---|
9495 | /** Opcode 0x72. */
|
---|
9496 | FNIEMOP_DEF(iemOp_jc_Jb)
|
---|
9497 | {
|
---|
9498 | IEMOP_MNEMONIC("jc/jnae Jb");
|
---|
9499 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9500 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9501 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9502 |
|
---|
9503 | IEM_MC_BEGIN(0, 0);
|
---|
9504 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
9505 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9506 | } IEM_MC_ELSE() {
|
---|
9507 | IEM_MC_ADVANCE_RIP();
|
---|
9508 | } IEM_MC_ENDIF();
|
---|
9509 | IEM_MC_END();
|
---|
9510 | return VINF_SUCCESS;
|
---|
9511 | }
|
---|
9512 |
|
---|
9513 |
|
---|
9514 | /** Opcode 0x73. */
|
---|
9515 | FNIEMOP_DEF(iemOp_jnc_Jb)
|
---|
9516 | {
|
---|
9517 | IEMOP_MNEMONIC("jnc/jnb Jb");
|
---|
9518 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9519 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9520 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9521 |
|
---|
9522 | IEM_MC_BEGIN(0, 0);
|
---|
9523 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
9524 | IEM_MC_ADVANCE_RIP();
|
---|
9525 | } IEM_MC_ELSE() {
|
---|
9526 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9527 | } IEM_MC_ENDIF();
|
---|
9528 | IEM_MC_END();
|
---|
9529 | return VINF_SUCCESS;
|
---|
9530 | }
|
---|
9531 |
|
---|
9532 |
|
---|
9533 | /** Opcode 0x74. */
|
---|
9534 | FNIEMOP_DEF(iemOp_je_Jb)
|
---|
9535 | {
|
---|
9536 | IEMOP_MNEMONIC("je/jz Jb");
|
---|
9537 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9538 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9539 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9540 |
|
---|
9541 | IEM_MC_BEGIN(0, 0);
|
---|
9542 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
9543 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9544 | } IEM_MC_ELSE() {
|
---|
9545 | IEM_MC_ADVANCE_RIP();
|
---|
9546 | } IEM_MC_ENDIF();
|
---|
9547 | IEM_MC_END();
|
---|
9548 | return VINF_SUCCESS;
|
---|
9549 | }
|
---|
9550 |
|
---|
9551 |
|
---|
9552 | /** Opcode 0x75. */
|
---|
9553 | FNIEMOP_DEF(iemOp_jne_Jb)
|
---|
9554 | {
|
---|
9555 | IEMOP_MNEMONIC("jne/jnz Jb");
|
---|
9556 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9557 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9558 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9559 |
|
---|
9560 | IEM_MC_BEGIN(0, 0);
|
---|
9561 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
9562 | IEM_MC_ADVANCE_RIP();
|
---|
9563 | } IEM_MC_ELSE() {
|
---|
9564 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9565 | } IEM_MC_ENDIF();
|
---|
9566 | IEM_MC_END();
|
---|
9567 | return VINF_SUCCESS;
|
---|
9568 | }
|
---|
9569 |
|
---|
9570 |
|
---|
9571 | /** Opcode 0x76. */
|
---|
9572 | FNIEMOP_DEF(iemOp_jbe_Jb)
|
---|
9573 | {
|
---|
9574 | IEMOP_MNEMONIC("jbe/jna Jb");
|
---|
9575 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9576 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9577 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9578 |
|
---|
9579 | IEM_MC_BEGIN(0, 0);
|
---|
9580 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
9581 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9582 | } IEM_MC_ELSE() {
|
---|
9583 | IEM_MC_ADVANCE_RIP();
|
---|
9584 | } IEM_MC_ENDIF();
|
---|
9585 | IEM_MC_END();
|
---|
9586 | return VINF_SUCCESS;
|
---|
9587 | }
|
---|
9588 |
|
---|
9589 |
|
---|
9590 | /** Opcode 0x77. */
|
---|
9591 | FNIEMOP_DEF(iemOp_jnbe_Jb)
|
---|
9592 | {
|
---|
9593 | IEMOP_MNEMONIC("jnbe/ja Jb");
|
---|
9594 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9595 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9596 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9597 |
|
---|
9598 | IEM_MC_BEGIN(0, 0);
|
---|
9599 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
|
---|
9600 | IEM_MC_ADVANCE_RIP();
|
---|
9601 | } IEM_MC_ELSE() {
|
---|
9602 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9603 | } IEM_MC_ENDIF();
|
---|
9604 | IEM_MC_END();
|
---|
9605 | return VINF_SUCCESS;
|
---|
9606 | }
|
---|
9607 |
|
---|
9608 |
|
---|
9609 | /** Opcode 0x78. */
|
---|
9610 | FNIEMOP_DEF(iemOp_js_Jb)
|
---|
9611 | {
|
---|
9612 | IEMOP_MNEMONIC("js Jb");
|
---|
9613 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9614 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9615 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9616 |
|
---|
9617 | IEM_MC_BEGIN(0, 0);
|
---|
9618 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
9619 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9620 | } IEM_MC_ELSE() {
|
---|
9621 | IEM_MC_ADVANCE_RIP();
|
---|
9622 | } IEM_MC_ENDIF();
|
---|
9623 | IEM_MC_END();
|
---|
9624 | return VINF_SUCCESS;
|
---|
9625 | }
|
---|
9626 |
|
---|
9627 |
|
---|
9628 | /** Opcode 0x79. */
|
---|
9629 | FNIEMOP_DEF(iemOp_jns_Jb)
|
---|
9630 | {
|
---|
9631 | IEMOP_MNEMONIC("jns Jb");
|
---|
9632 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9633 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9634 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9635 |
|
---|
9636 | IEM_MC_BEGIN(0, 0);
|
---|
9637 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
|
---|
9638 | IEM_MC_ADVANCE_RIP();
|
---|
9639 | } IEM_MC_ELSE() {
|
---|
9640 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9641 | } IEM_MC_ENDIF();
|
---|
9642 | IEM_MC_END();
|
---|
9643 | return VINF_SUCCESS;
|
---|
9644 | }
|
---|
9645 |
|
---|
9646 |
|
---|
9647 | /** Opcode 0x7a. */
|
---|
9648 | FNIEMOP_DEF(iemOp_jp_Jb)
|
---|
9649 | {
|
---|
9650 | IEMOP_MNEMONIC("jp Jb");
|
---|
9651 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9652 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9653 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9654 |
|
---|
9655 | IEM_MC_BEGIN(0, 0);
|
---|
9656 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
9657 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9658 | } IEM_MC_ELSE() {
|
---|
9659 | IEM_MC_ADVANCE_RIP();
|
---|
9660 | } IEM_MC_ENDIF();
|
---|
9661 | IEM_MC_END();
|
---|
9662 | return VINF_SUCCESS;
|
---|
9663 | }
|
---|
9664 |
|
---|
9665 |
|
---|
9666 | /** Opcode 0x7b. */
|
---|
9667 | FNIEMOP_DEF(iemOp_jnp_Jb)
|
---|
9668 | {
|
---|
9669 | IEMOP_MNEMONIC("jnp Jb");
|
---|
9670 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9671 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9672 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9673 |
|
---|
9674 | IEM_MC_BEGIN(0, 0);
|
---|
9675 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
|
---|
9676 | IEM_MC_ADVANCE_RIP();
|
---|
9677 | } IEM_MC_ELSE() {
|
---|
9678 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9679 | } IEM_MC_ENDIF();
|
---|
9680 | IEM_MC_END();
|
---|
9681 | return VINF_SUCCESS;
|
---|
9682 | }
|
---|
9683 |
|
---|
9684 |
|
---|
9685 | /** Opcode 0x7c. */
|
---|
9686 | FNIEMOP_DEF(iemOp_jl_Jb)
|
---|
9687 | {
|
---|
9688 | IEMOP_MNEMONIC("jl/jnge Jb");
|
---|
9689 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9690 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9691 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9692 |
|
---|
9693 | IEM_MC_BEGIN(0, 0);
|
---|
9694 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
9695 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9696 | } IEM_MC_ELSE() {
|
---|
9697 | IEM_MC_ADVANCE_RIP();
|
---|
9698 | } IEM_MC_ENDIF();
|
---|
9699 | IEM_MC_END();
|
---|
9700 | return VINF_SUCCESS;
|
---|
9701 | }
|
---|
9702 |
|
---|
9703 |
|
---|
9704 | /** Opcode 0x7d. */
|
---|
9705 | FNIEMOP_DEF(iemOp_jnl_Jb)
|
---|
9706 | {
|
---|
9707 | IEMOP_MNEMONIC("jnl/jge Jb");
|
---|
9708 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9709 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9710 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9711 |
|
---|
9712 | IEM_MC_BEGIN(0, 0);
|
---|
9713 | IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
|
---|
9714 | IEM_MC_ADVANCE_RIP();
|
---|
9715 | } IEM_MC_ELSE() {
|
---|
9716 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9717 | } IEM_MC_ENDIF();
|
---|
9718 | IEM_MC_END();
|
---|
9719 | return VINF_SUCCESS;
|
---|
9720 | }
|
---|
9721 |
|
---|
9722 |
|
---|
9723 | /** Opcode 0x7e. */
|
---|
9724 | FNIEMOP_DEF(iemOp_jle_Jb)
|
---|
9725 | {
|
---|
9726 | IEMOP_MNEMONIC("jle/jng Jb");
|
---|
9727 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9728 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9729 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9730 |
|
---|
9731 | IEM_MC_BEGIN(0, 0);
|
---|
9732 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
9733 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9734 | } IEM_MC_ELSE() {
|
---|
9735 | IEM_MC_ADVANCE_RIP();
|
---|
9736 | } IEM_MC_ENDIF();
|
---|
9737 | IEM_MC_END();
|
---|
9738 | return VINF_SUCCESS;
|
---|
9739 | }
|
---|
9740 |
|
---|
9741 |
|
---|
9742 | /** Opcode 0x7f. */
|
---|
9743 | FNIEMOP_DEF(iemOp_jnle_Jb)
|
---|
9744 | {
|
---|
9745 | IEMOP_MNEMONIC("jnle/jg Jb");
|
---|
9746 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
9747 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9748 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
9749 |
|
---|
9750 | IEM_MC_BEGIN(0, 0);
|
---|
9751 | IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
|
---|
9752 | IEM_MC_ADVANCE_RIP();
|
---|
9753 | } IEM_MC_ELSE() {
|
---|
9754 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
9755 | } IEM_MC_ENDIF();
|
---|
9756 | IEM_MC_END();
|
---|
9757 | return VINF_SUCCESS;
|
---|
9758 | }
|
---|
9759 |
|
---|
9760 |
|
---|
9761 | /** Opcode 0x80. */
|
---|
9762 | FNIEMOP_DEF(iemOp_Grp1_Eb_Ib_80)
|
---|
9763 | {
|
---|
9764 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
9765 | IEMOP_MNEMONIC2("add\0or\0\0adc\0sbb\0and\0sub\0xor\0cmp" + ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)*4, "Eb,Ib");
|
---|
9766 | PCIEMOPBINSIZES pImpl = g_apIemImplGrp1[(bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK];
|
---|
9767 |
|
---|
9768 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
9769 | {
|
---|
9770 | /* register target */
|
---|
9771 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
9772 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9773 | IEM_MC_BEGIN(3, 0);
|
---|
9774 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
9775 | IEM_MC_ARG_CONST(uint8_t, u8Src, /*=*/ u8Imm, 1);
|
---|
9776 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9777 |
|
---|
9778 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9779 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9780 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, u8Src, pEFlags);
|
---|
9781 |
|
---|
9782 | IEM_MC_ADVANCE_RIP();
|
---|
9783 | IEM_MC_END();
|
---|
9784 | }
|
---|
9785 | else
|
---|
9786 | {
|
---|
9787 | /* memory target */
|
---|
9788 | uint32_t fAccess;
|
---|
9789 | if (pImpl->pfnLockedU8)
|
---|
9790 | fAccess = IEM_ACCESS_DATA_RW;
|
---|
9791 | else /* CMP */
|
---|
9792 | fAccess = IEM_ACCESS_DATA_R;
|
---|
9793 | IEM_MC_BEGIN(3, 2);
|
---|
9794 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
9795 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
9796 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9797 |
|
---|
9798 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
9799 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
9800 | IEM_MC_ARG_CONST(uint8_t, u8Src, /*=*/ u8Imm, 1);
|
---|
9801 | if (pImpl->pfnLockedU8)
|
---|
9802 | IEMOP_HLP_DONE_DECODING();
|
---|
9803 | else
|
---|
9804 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9805 |
|
---|
9806 | IEM_MC_MEM_MAP(pu8Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
9807 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
9808 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
9809 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, u8Src, pEFlags);
|
---|
9810 | else
|
---|
9811 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU8, pu8Dst, u8Src, pEFlags);
|
---|
9812 |
|
---|
9813 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, fAccess);
|
---|
9814 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
9815 | IEM_MC_ADVANCE_RIP();
|
---|
9816 | IEM_MC_END();
|
---|
9817 | }
|
---|
9818 | return VINF_SUCCESS;
|
---|
9819 | }
|
---|
9820 |
|
---|
9821 |
|
---|
9822 | /** Opcode 0x81. */
|
---|
9823 | FNIEMOP_DEF(iemOp_Grp1_Ev_Iz)
|
---|
9824 | {
|
---|
9825 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
9826 | IEMOP_MNEMONIC2("add\0or\0\0adc\0sbb\0and\0sub\0xor\0cmp" + ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)*4, "Ev,Iz");
|
---|
9827 | PCIEMOPBINSIZES pImpl = g_apIemImplGrp1[(bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK];
|
---|
9828 |
|
---|
9829 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
9830 | {
|
---|
9831 | case IEMMODE_16BIT:
|
---|
9832 | {
|
---|
9833 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
9834 | {
|
---|
9835 | /* register target */
|
---|
9836 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
9837 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9838 | IEM_MC_BEGIN(3, 0);
|
---|
9839 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
9840 | IEM_MC_ARG_CONST(uint16_t, u16Src, /*=*/ u16Imm, 1);
|
---|
9841 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9842 |
|
---|
9843 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9844 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9845 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
9846 |
|
---|
9847 | IEM_MC_ADVANCE_RIP();
|
---|
9848 | IEM_MC_END();
|
---|
9849 | }
|
---|
9850 | else
|
---|
9851 | {
|
---|
9852 | /* memory target */
|
---|
9853 | uint32_t fAccess;
|
---|
9854 | if (pImpl->pfnLockedU16)
|
---|
9855 | fAccess = IEM_ACCESS_DATA_RW;
|
---|
9856 | else /* CMP, TEST */
|
---|
9857 | fAccess = IEM_ACCESS_DATA_R;
|
---|
9858 | IEM_MC_BEGIN(3, 2);
|
---|
9859 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
9860 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
9861 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
9862 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9863 |
|
---|
9864 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 2);
|
---|
9865 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
9866 | IEM_MC_ASSIGN(u16Src, u16Imm);
|
---|
9867 | if (pImpl->pfnLockedU16)
|
---|
9868 | IEMOP_HLP_DONE_DECODING();
|
---|
9869 | else
|
---|
9870 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9871 | IEM_MC_MEM_MAP(pu16Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
9872 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
9873 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
9874 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
9875 | else
|
---|
9876 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
|
---|
9877 |
|
---|
9878 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, fAccess);
|
---|
9879 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
9880 | IEM_MC_ADVANCE_RIP();
|
---|
9881 | IEM_MC_END();
|
---|
9882 | }
|
---|
9883 | break;
|
---|
9884 | }
|
---|
9885 |
|
---|
9886 | case IEMMODE_32BIT:
|
---|
9887 | {
|
---|
9888 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
9889 | {
|
---|
9890 | /* register target */
|
---|
9891 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
9892 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9893 | IEM_MC_BEGIN(3, 0);
|
---|
9894 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
9895 | IEM_MC_ARG_CONST(uint32_t, u32Src, /*=*/ u32Imm, 1);
|
---|
9896 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9897 |
|
---|
9898 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9899 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9900 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
9901 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
9902 |
|
---|
9903 | IEM_MC_ADVANCE_RIP();
|
---|
9904 | IEM_MC_END();
|
---|
9905 | }
|
---|
9906 | else
|
---|
9907 | {
|
---|
9908 | /* memory target */
|
---|
9909 | uint32_t fAccess;
|
---|
9910 | if (pImpl->pfnLockedU32)
|
---|
9911 | fAccess = IEM_ACCESS_DATA_RW;
|
---|
9912 | else /* CMP, TEST */
|
---|
9913 | fAccess = IEM_ACCESS_DATA_R;
|
---|
9914 | IEM_MC_BEGIN(3, 2);
|
---|
9915 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
9916 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
9917 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
9918 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9919 |
|
---|
9920 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
|
---|
9921 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
9922 | IEM_MC_ASSIGN(u32Src, u32Imm);
|
---|
9923 | if (pImpl->pfnLockedU32)
|
---|
9924 | IEMOP_HLP_DONE_DECODING();
|
---|
9925 | else
|
---|
9926 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9927 | IEM_MC_MEM_MAP(pu32Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
9928 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
9929 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
9930 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
9931 | else
|
---|
9932 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
|
---|
9933 |
|
---|
9934 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, fAccess);
|
---|
9935 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
9936 | IEM_MC_ADVANCE_RIP();
|
---|
9937 | IEM_MC_END();
|
---|
9938 | }
|
---|
9939 | break;
|
---|
9940 | }
|
---|
9941 |
|
---|
9942 | case IEMMODE_64BIT:
|
---|
9943 | {
|
---|
9944 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
9945 | {
|
---|
9946 | /* register target */
|
---|
9947 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
9948 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9949 | IEM_MC_BEGIN(3, 0);
|
---|
9950 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
9951 | IEM_MC_ARG_CONST(uint64_t, u64Src, /*=*/ u64Imm, 1);
|
---|
9952 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
9953 |
|
---|
9954 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
9955 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
9956 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
9957 |
|
---|
9958 | IEM_MC_ADVANCE_RIP();
|
---|
9959 | IEM_MC_END();
|
---|
9960 | }
|
---|
9961 | else
|
---|
9962 | {
|
---|
9963 | /* memory target */
|
---|
9964 | uint32_t fAccess;
|
---|
9965 | if (pImpl->pfnLockedU64)
|
---|
9966 | fAccess = IEM_ACCESS_DATA_RW;
|
---|
9967 | else /* CMP */
|
---|
9968 | fAccess = IEM_ACCESS_DATA_R;
|
---|
9969 | IEM_MC_BEGIN(3, 2);
|
---|
9970 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
9971 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
9972 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
9973 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
9974 |
|
---|
9975 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
|
---|
9976 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
9977 | if (pImpl->pfnLockedU64)
|
---|
9978 | IEMOP_HLP_DONE_DECODING();
|
---|
9979 | else
|
---|
9980 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
9981 | IEM_MC_ASSIGN(u64Src, u64Imm);
|
---|
9982 | IEM_MC_MEM_MAP(pu64Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
9983 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
9984 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
9985 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
9986 | else
|
---|
9987 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
|
---|
9988 |
|
---|
9989 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, fAccess);
|
---|
9990 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
9991 | IEM_MC_ADVANCE_RIP();
|
---|
9992 | IEM_MC_END();
|
---|
9993 | }
|
---|
9994 | break;
|
---|
9995 | }
|
---|
9996 | }
|
---|
9997 | return VINF_SUCCESS;
|
---|
9998 | }
|
---|
9999 |
|
---|
10000 |
|
---|
10001 | /** Opcode 0x82. */
|
---|
10002 | FNIEMOP_DEF(iemOp_Grp1_Eb_Ib_82)
|
---|
10003 | {
|
---|
10004 | IEMOP_HLP_NO_64BIT(); /** @todo do we need to decode the whole instruction or is this ok? */
|
---|
10005 | return FNIEMOP_CALL(iemOp_Grp1_Eb_Ib_80);
|
---|
10006 | }
|
---|
10007 |
|
---|
10008 |
|
---|
10009 | /** Opcode 0x83. */
|
---|
10010 | FNIEMOP_DEF(iemOp_Grp1_Ev_Ib)
|
---|
10011 | {
|
---|
10012 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10013 | IEMOP_MNEMONIC2("add\0or\0\0adc\0sbb\0and\0sub\0xor\0cmp" + ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)*4, "Ev,Ib");
|
---|
10014 | /* Note! Seems the OR, AND, and XOR instructions are present on CPUs prior
|
---|
10015 | to the 386 even if absent in the intel reference manuals and some
|
---|
10016 | 3rd party opcode listings. */
|
---|
10017 | PCIEMOPBINSIZES pImpl = g_apIemImplGrp1[(bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK];
|
---|
10018 |
|
---|
10019 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10020 | {
|
---|
10021 | /*
|
---|
10022 | * Register target
|
---|
10023 | */
|
---|
10024 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10025 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
10026 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10027 | {
|
---|
10028 | case IEMMODE_16BIT:
|
---|
10029 | {
|
---|
10030 | IEM_MC_BEGIN(3, 0);
|
---|
10031 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
10032 | IEM_MC_ARG_CONST(uint16_t, u16Src, /*=*/ (int8_t)u8Imm,1);
|
---|
10033 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
10034 |
|
---|
10035 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10036 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
10037 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
10038 |
|
---|
10039 | IEM_MC_ADVANCE_RIP();
|
---|
10040 | IEM_MC_END();
|
---|
10041 | break;
|
---|
10042 | }
|
---|
10043 |
|
---|
10044 | case IEMMODE_32BIT:
|
---|
10045 | {
|
---|
10046 | IEM_MC_BEGIN(3, 0);
|
---|
10047 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
10048 | IEM_MC_ARG_CONST(uint32_t, u32Src, /*=*/ (int8_t)u8Imm,1);
|
---|
10049 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
10050 |
|
---|
10051 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10052 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
10053 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
10054 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
10055 |
|
---|
10056 | IEM_MC_ADVANCE_RIP();
|
---|
10057 | IEM_MC_END();
|
---|
10058 | break;
|
---|
10059 | }
|
---|
10060 |
|
---|
10061 | case IEMMODE_64BIT:
|
---|
10062 | {
|
---|
10063 | IEM_MC_BEGIN(3, 0);
|
---|
10064 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
10065 | IEM_MC_ARG_CONST(uint64_t, u64Src, /*=*/ (int8_t)u8Imm,1);
|
---|
10066 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
10067 |
|
---|
10068 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10069 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
10070 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
10071 |
|
---|
10072 | IEM_MC_ADVANCE_RIP();
|
---|
10073 | IEM_MC_END();
|
---|
10074 | break;
|
---|
10075 | }
|
---|
10076 | }
|
---|
10077 | }
|
---|
10078 | else
|
---|
10079 | {
|
---|
10080 | /*
|
---|
10081 | * Memory target.
|
---|
10082 | */
|
---|
10083 | uint32_t fAccess;
|
---|
10084 | if (pImpl->pfnLockedU16)
|
---|
10085 | fAccess = IEM_ACCESS_DATA_RW;
|
---|
10086 | else /* CMP */
|
---|
10087 | fAccess = IEM_ACCESS_DATA_R;
|
---|
10088 |
|
---|
10089 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10090 | {
|
---|
10091 | case IEMMODE_16BIT:
|
---|
10092 | {
|
---|
10093 | IEM_MC_BEGIN(3, 2);
|
---|
10094 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
10095 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
10096 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
10097 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10098 |
|
---|
10099 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
10100 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
10101 | IEM_MC_ASSIGN(u16Src, (int8_t)u8Imm);
|
---|
10102 | if (pImpl->pfnLockedU16)
|
---|
10103 | IEMOP_HLP_DONE_DECODING();
|
---|
10104 | else
|
---|
10105 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10106 | IEM_MC_MEM_MAP(pu16Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
10107 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
10108 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
10109 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
|
---|
10110 | else
|
---|
10111 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
|
---|
10112 |
|
---|
10113 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, fAccess);
|
---|
10114 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
10115 | IEM_MC_ADVANCE_RIP();
|
---|
10116 | IEM_MC_END();
|
---|
10117 | break;
|
---|
10118 | }
|
---|
10119 |
|
---|
10120 | case IEMMODE_32BIT:
|
---|
10121 | {
|
---|
10122 | IEM_MC_BEGIN(3, 2);
|
---|
10123 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
10124 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
10125 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
10126 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10127 |
|
---|
10128 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
10129 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
10130 | IEM_MC_ASSIGN(u32Src, (int8_t)u8Imm);
|
---|
10131 | if (pImpl->pfnLockedU32)
|
---|
10132 | IEMOP_HLP_DONE_DECODING();
|
---|
10133 | else
|
---|
10134 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10135 | IEM_MC_MEM_MAP(pu32Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
10136 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
10137 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
10138 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
|
---|
10139 | else
|
---|
10140 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
|
---|
10141 |
|
---|
10142 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, fAccess);
|
---|
10143 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
10144 | IEM_MC_ADVANCE_RIP();
|
---|
10145 | IEM_MC_END();
|
---|
10146 | break;
|
---|
10147 | }
|
---|
10148 |
|
---|
10149 | case IEMMODE_64BIT:
|
---|
10150 | {
|
---|
10151 | IEM_MC_BEGIN(3, 2);
|
---|
10152 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
10153 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
10154 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
10155 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10156 |
|
---|
10157 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
10158 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
10159 | IEM_MC_ASSIGN(u64Src, (int8_t)u8Imm);
|
---|
10160 | if (pImpl->pfnLockedU64)
|
---|
10161 | IEMOP_HLP_DONE_DECODING();
|
---|
10162 | else
|
---|
10163 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10164 | IEM_MC_MEM_MAP(pu64Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
10165 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
10166 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
10167 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
|
---|
10168 | else
|
---|
10169 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
|
---|
10170 |
|
---|
10171 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, fAccess);
|
---|
10172 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
10173 | IEM_MC_ADVANCE_RIP();
|
---|
10174 | IEM_MC_END();
|
---|
10175 | break;
|
---|
10176 | }
|
---|
10177 | }
|
---|
10178 | }
|
---|
10179 | return VINF_SUCCESS;
|
---|
10180 | }
|
---|
10181 |
|
---|
10182 |
|
---|
10183 | /** Opcode 0x84. */
|
---|
10184 | FNIEMOP_DEF(iemOp_test_Eb_Gb)
|
---|
10185 | {
|
---|
10186 | IEMOP_MNEMONIC("test Eb,Gb");
|
---|
10187 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
10188 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_test);
|
---|
10189 | }
|
---|
10190 |
|
---|
10191 |
|
---|
10192 | /** Opcode 0x85. */
|
---|
10193 | FNIEMOP_DEF(iemOp_test_Ev_Gv)
|
---|
10194 | {
|
---|
10195 | IEMOP_MNEMONIC("test Ev,Gv");
|
---|
10196 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
10197 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_test);
|
---|
10198 | }
|
---|
10199 |
|
---|
10200 |
|
---|
10201 | /** Opcode 0x86. */
|
---|
10202 | FNIEMOP_DEF(iemOp_xchg_Eb_Gb)
|
---|
10203 | {
|
---|
10204 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10205 | IEMOP_MNEMONIC("xchg Eb,Gb");
|
---|
10206 |
|
---|
10207 | /*
|
---|
10208 | * If rm is denoting a register, no more instruction bytes.
|
---|
10209 | */
|
---|
10210 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10211 | {
|
---|
10212 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10213 |
|
---|
10214 | IEM_MC_BEGIN(0, 2);
|
---|
10215 | IEM_MC_LOCAL(uint8_t, uTmp1);
|
---|
10216 | IEM_MC_LOCAL(uint8_t, uTmp2);
|
---|
10217 |
|
---|
10218 | IEM_MC_FETCH_GREG_U8(uTmp1, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10219 | IEM_MC_FETCH_GREG_U8(uTmp2, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10220 | IEM_MC_STORE_GREG_U8((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uTmp1);
|
---|
10221 | IEM_MC_STORE_GREG_U8(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uTmp2);
|
---|
10222 |
|
---|
10223 | IEM_MC_ADVANCE_RIP();
|
---|
10224 | IEM_MC_END();
|
---|
10225 | }
|
---|
10226 | else
|
---|
10227 | {
|
---|
10228 | /*
|
---|
10229 | * We're accessing memory.
|
---|
10230 | */
|
---|
10231 | /** @todo the register must be committed separately! */
|
---|
10232 | IEM_MC_BEGIN(2, 2);
|
---|
10233 | IEM_MC_ARG(uint8_t *, pu8Mem, 0);
|
---|
10234 | IEM_MC_ARG(uint8_t *, pu8Reg, 1);
|
---|
10235 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10236 |
|
---|
10237 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10238 | IEM_MC_MEM_MAP(pu8Mem, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
10239 | IEM_MC_REF_GREG_U8(pu8Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10240 | IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_xchg_u8, pu8Mem, pu8Reg);
|
---|
10241 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Mem, IEM_ACCESS_DATA_RW);
|
---|
10242 |
|
---|
10243 | IEM_MC_ADVANCE_RIP();
|
---|
10244 | IEM_MC_END();
|
---|
10245 | }
|
---|
10246 | return VINF_SUCCESS;
|
---|
10247 | }
|
---|
10248 |
|
---|
10249 |
|
---|
10250 | /** Opcode 0x87. */
|
---|
10251 | FNIEMOP_DEF(iemOp_xchg_Ev_Gv)
|
---|
10252 | {
|
---|
10253 | IEMOP_MNEMONIC("xchg Ev,Gv");
|
---|
10254 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10255 |
|
---|
10256 | /*
|
---|
10257 | * If rm is denoting a register, no more instruction bytes.
|
---|
10258 | */
|
---|
10259 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10260 | {
|
---|
10261 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10262 |
|
---|
10263 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10264 | {
|
---|
10265 | case IEMMODE_16BIT:
|
---|
10266 | IEM_MC_BEGIN(0, 2);
|
---|
10267 | IEM_MC_LOCAL(uint16_t, uTmp1);
|
---|
10268 | IEM_MC_LOCAL(uint16_t, uTmp2);
|
---|
10269 |
|
---|
10270 | IEM_MC_FETCH_GREG_U16(uTmp1, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10271 | IEM_MC_FETCH_GREG_U16(uTmp2, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10272 | IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uTmp1);
|
---|
10273 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uTmp2);
|
---|
10274 |
|
---|
10275 | IEM_MC_ADVANCE_RIP();
|
---|
10276 | IEM_MC_END();
|
---|
10277 | return VINF_SUCCESS;
|
---|
10278 |
|
---|
10279 | case IEMMODE_32BIT:
|
---|
10280 | IEM_MC_BEGIN(0, 2);
|
---|
10281 | IEM_MC_LOCAL(uint32_t, uTmp1);
|
---|
10282 | IEM_MC_LOCAL(uint32_t, uTmp2);
|
---|
10283 |
|
---|
10284 | IEM_MC_FETCH_GREG_U32(uTmp1, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10285 | IEM_MC_FETCH_GREG_U32(uTmp2, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10286 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uTmp1);
|
---|
10287 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uTmp2);
|
---|
10288 |
|
---|
10289 | IEM_MC_ADVANCE_RIP();
|
---|
10290 | IEM_MC_END();
|
---|
10291 | return VINF_SUCCESS;
|
---|
10292 |
|
---|
10293 | case IEMMODE_64BIT:
|
---|
10294 | IEM_MC_BEGIN(0, 2);
|
---|
10295 | IEM_MC_LOCAL(uint64_t, uTmp1);
|
---|
10296 | IEM_MC_LOCAL(uint64_t, uTmp2);
|
---|
10297 |
|
---|
10298 | IEM_MC_FETCH_GREG_U64(uTmp1, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10299 | IEM_MC_FETCH_GREG_U64(uTmp2, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10300 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uTmp1);
|
---|
10301 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uTmp2);
|
---|
10302 |
|
---|
10303 | IEM_MC_ADVANCE_RIP();
|
---|
10304 | IEM_MC_END();
|
---|
10305 | return VINF_SUCCESS;
|
---|
10306 |
|
---|
10307 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
10308 | }
|
---|
10309 | }
|
---|
10310 | else
|
---|
10311 | {
|
---|
10312 | /*
|
---|
10313 | * We're accessing memory.
|
---|
10314 | */
|
---|
10315 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10316 | {
|
---|
10317 | /** @todo the register must be committed separately! */
|
---|
10318 | case IEMMODE_16BIT:
|
---|
10319 | IEM_MC_BEGIN(2, 2);
|
---|
10320 | IEM_MC_ARG(uint16_t *, pu16Mem, 0);
|
---|
10321 | IEM_MC_ARG(uint16_t *, pu16Reg, 1);
|
---|
10322 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10323 |
|
---|
10324 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10325 | IEM_MC_MEM_MAP(pu16Mem, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
10326 | IEM_MC_REF_GREG_U16(pu16Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10327 | IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_xchg_u16, pu16Mem, pu16Reg);
|
---|
10328 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Mem, IEM_ACCESS_DATA_RW);
|
---|
10329 |
|
---|
10330 | IEM_MC_ADVANCE_RIP();
|
---|
10331 | IEM_MC_END();
|
---|
10332 | return VINF_SUCCESS;
|
---|
10333 |
|
---|
10334 | case IEMMODE_32BIT:
|
---|
10335 | IEM_MC_BEGIN(2, 2);
|
---|
10336 | IEM_MC_ARG(uint32_t *, pu32Mem, 0);
|
---|
10337 | IEM_MC_ARG(uint32_t *, pu32Reg, 1);
|
---|
10338 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10339 |
|
---|
10340 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10341 | IEM_MC_MEM_MAP(pu32Mem, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
10342 | IEM_MC_REF_GREG_U32(pu32Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10343 | IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_xchg_u32, pu32Mem, pu32Reg);
|
---|
10344 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Mem, IEM_ACCESS_DATA_RW);
|
---|
10345 |
|
---|
10346 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Reg);
|
---|
10347 | IEM_MC_ADVANCE_RIP();
|
---|
10348 | IEM_MC_END();
|
---|
10349 | return VINF_SUCCESS;
|
---|
10350 |
|
---|
10351 | case IEMMODE_64BIT:
|
---|
10352 | IEM_MC_BEGIN(2, 2);
|
---|
10353 | IEM_MC_ARG(uint64_t *, pu64Mem, 0);
|
---|
10354 | IEM_MC_ARG(uint64_t *, pu64Reg, 1);
|
---|
10355 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10356 |
|
---|
10357 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10358 | IEM_MC_MEM_MAP(pu64Mem, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
10359 | IEM_MC_REF_GREG_U64(pu64Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10360 | IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_xchg_u64, pu64Mem, pu64Reg);
|
---|
10361 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Mem, IEM_ACCESS_DATA_RW);
|
---|
10362 |
|
---|
10363 | IEM_MC_ADVANCE_RIP();
|
---|
10364 | IEM_MC_END();
|
---|
10365 | return VINF_SUCCESS;
|
---|
10366 |
|
---|
10367 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
10368 | }
|
---|
10369 | }
|
---|
10370 | }
|
---|
10371 |
|
---|
10372 |
|
---|
10373 | /** Opcode 0x88. */
|
---|
10374 | FNIEMOP_DEF(iemOp_mov_Eb_Gb)
|
---|
10375 | {
|
---|
10376 | IEMOP_MNEMONIC("mov Eb,Gb");
|
---|
10377 |
|
---|
10378 | uint8_t bRm;
|
---|
10379 | IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10380 |
|
---|
10381 | /*
|
---|
10382 | * If rm is denoting a register, no more instruction bytes.
|
---|
10383 | */
|
---|
10384 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10385 | {
|
---|
10386 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10387 | IEM_MC_BEGIN(0, 1);
|
---|
10388 | IEM_MC_LOCAL(uint8_t, u8Value);
|
---|
10389 | IEM_MC_FETCH_GREG_U8(u8Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10390 | IEM_MC_STORE_GREG_U8((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u8Value);
|
---|
10391 | IEM_MC_ADVANCE_RIP();
|
---|
10392 | IEM_MC_END();
|
---|
10393 | }
|
---|
10394 | else
|
---|
10395 | {
|
---|
10396 | /*
|
---|
10397 | * We're writing a register to memory.
|
---|
10398 | */
|
---|
10399 | IEM_MC_BEGIN(0, 2);
|
---|
10400 | IEM_MC_LOCAL(uint8_t, u8Value);
|
---|
10401 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10402 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10403 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10404 | IEM_MC_FETCH_GREG_U8(u8Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10405 | IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u8Value);
|
---|
10406 | IEM_MC_ADVANCE_RIP();
|
---|
10407 | IEM_MC_END();
|
---|
10408 | }
|
---|
10409 | return VINF_SUCCESS;
|
---|
10410 |
|
---|
10411 | }
|
---|
10412 |
|
---|
10413 |
|
---|
10414 | /** Opcode 0x89. */
|
---|
10415 | FNIEMOP_DEF(iemOp_mov_Ev_Gv)
|
---|
10416 | {
|
---|
10417 | IEMOP_MNEMONIC("mov Ev,Gv");
|
---|
10418 |
|
---|
10419 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10420 |
|
---|
10421 | /*
|
---|
10422 | * If rm is denoting a register, no more instruction bytes.
|
---|
10423 | */
|
---|
10424 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10425 | {
|
---|
10426 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10427 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10428 | {
|
---|
10429 | case IEMMODE_16BIT:
|
---|
10430 | IEM_MC_BEGIN(0, 1);
|
---|
10431 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
10432 | IEM_MC_FETCH_GREG_U16(u16Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10433 | IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Value);
|
---|
10434 | IEM_MC_ADVANCE_RIP();
|
---|
10435 | IEM_MC_END();
|
---|
10436 | break;
|
---|
10437 |
|
---|
10438 | case IEMMODE_32BIT:
|
---|
10439 | IEM_MC_BEGIN(0, 1);
|
---|
10440 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
10441 | IEM_MC_FETCH_GREG_U32(u32Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10442 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Value);
|
---|
10443 | IEM_MC_ADVANCE_RIP();
|
---|
10444 | IEM_MC_END();
|
---|
10445 | break;
|
---|
10446 |
|
---|
10447 | case IEMMODE_64BIT:
|
---|
10448 | IEM_MC_BEGIN(0, 1);
|
---|
10449 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
10450 | IEM_MC_FETCH_GREG_U64(u64Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10451 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Value);
|
---|
10452 | IEM_MC_ADVANCE_RIP();
|
---|
10453 | IEM_MC_END();
|
---|
10454 | break;
|
---|
10455 | }
|
---|
10456 | }
|
---|
10457 | else
|
---|
10458 | {
|
---|
10459 | /*
|
---|
10460 | * We're writing a register to memory.
|
---|
10461 | */
|
---|
10462 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10463 | {
|
---|
10464 | case IEMMODE_16BIT:
|
---|
10465 | IEM_MC_BEGIN(0, 2);
|
---|
10466 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
10467 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10468 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10469 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10470 | IEM_MC_FETCH_GREG_U16(u16Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10471 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value);
|
---|
10472 | IEM_MC_ADVANCE_RIP();
|
---|
10473 | IEM_MC_END();
|
---|
10474 | break;
|
---|
10475 |
|
---|
10476 | case IEMMODE_32BIT:
|
---|
10477 | IEM_MC_BEGIN(0, 2);
|
---|
10478 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
10479 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10480 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10481 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10482 | IEM_MC_FETCH_GREG_U32(u32Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10483 | IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value);
|
---|
10484 | IEM_MC_ADVANCE_RIP();
|
---|
10485 | IEM_MC_END();
|
---|
10486 | break;
|
---|
10487 |
|
---|
10488 | case IEMMODE_64BIT:
|
---|
10489 | IEM_MC_BEGIN(0, 2);
|
---|
10490 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
10491 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10492 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10493 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10494 | IEM_MC_FETCH_GREG_U64(u64Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
|
---|
10495 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value);
|
---|
10496 | IEM_MC_ADVANCE_RIP();
|
---|
10497 | IEM_MC_END();
|
---|
10498 | break;
|
---|
10499 | }
|
---|
10500 | }
|
---|
10501 | return VINF_SUCCESS;
|
---|
10502 | }
|
---|
10503 |
|
---|
10504 |
|
---|
10505 | /** Opcode 0x8a. */
|
---|
10506 | FNIEMOP_DEF(iemOp_mov_Gb_Eb)
|
---|
10507 | {
|
---|
10508 | IEMOP_MNEMONIC("mov Gb,Eb");
|
---|
10509 |
|
---|
10510 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10511 |
|
---|
10512 | /*
|
---|
10513 | * If rm is denoting a register, no more instruction bytes.
|
---|
10514 | */
|
---|
10515 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10516 | {
|
---|
10517 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10518 | IEM_MC_BEGIN(0, 1);
|
---|
10519 | IEM_MC_LOCAL(uint8_t, u8Value);
|
---|
10520 | IEM_MC_FETCH_GREG_U8(u8Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10521 | IEM_MC_STORE_GREG_U8(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u8Value);
|
---|
10522 | IEM_MC_ADVANCE_RIP();
|
---|
10523 | IEM_MC_END();
|
---|
10524 | }
|
---|
10525 | else
|
---|
10526 | {
|
---|
10527 | /*
|
---|
10528 | * We're loading a register from memory.
|
---|
10529 | */
|
---|
10530 | IEM_MC_BEGIN(0, 2);
|
---|
10531 | IEM_MC_LOCAL(uint8_t, u8Value);
|
---|
10532 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10533 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10534 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10535 | IEM_MC_FETCH_MEM_U8(u8Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
10536 | IEM_MC_STORE_GREG_U8(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u8Value);
|
---|
10537 | IEM_MC_ADVANCE_RIP();
|
---|
10538 | IEM_MC_END();
|
---|
10539 | }
|
---|
10540 | return VINF_SUCCESS;
|
---|
10541 | }
|
---|
10542 |
|
---|
10543 |
|
---|
10544 | /** Opcode 0x8b. */
|
---|
10545 | FNIEMOP_DEF(iemOp_mov_Gv_Ev)
|
---|
10546 | {
|
---|
10547 | IEMOP_MNEMONIC("mov Gv,Ev");
|
---|
10548 |
|
---|
10549 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10550 |
|
---|
10551 | /*
|
---|
10552 | * If rm is denoting a register, no more instruction bytes.
|
---|
10553 | */
|
---|
10554 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10555 | {
|
---|
10556 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10557 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10558 | {
|
---|
10559 | case IEMMODE_16BIT:
|
---|
10560 | IEM_MC_BEGIN(0, 1);
|
---|
10561 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
10562 | IEM_MC_FETCH_GREG_U16(u16Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10563 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
|
---|
10564 | IEM_MC_ADVANCE_RIP();
|
---|
10565 | IEM_MC_END();
|
---|
10566 | break;
|
---|
10567 |
|
---|
10568 | case IEMMODE_32BIT:
|
---|
10569 | IEM_MC_BEGIN(0, 1);
|
---|
10570 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
10571 | IEM_MC_FETCH_GREG_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10572 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
10573 | IEM_MC_ADVANCE_RIP();
|
---|
10574 | IEM_MC_END();
|
---|
10575 | break;
|
---|
10576 |
|
---|
10577 | case IEMMODE_64BIT:
|
---|
10578 | IEM_MC_BEGIN(0, 1);
|
---|
10579 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
10580 | IEM_MC_FETCH_GREG_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10581 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
10582 | IEM_MC_ADVANCE_RIP();
|
---|
10583 | IEM_MC_END();
|
---|
10584 | break;
|
---|
10585 | }
|
---|
10586 | }
|
---|
10587 | else
|
---|
10588 | {
|
---|
10589 | /*
|
---|
10590 | * We're loading a register from memory.
|
---|
10591 | */
|
---|
10592 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10593 | {
|
---|
10594 | case IEMMODE_16BIT:
|
---|
10595 | IEM_MC_BEGIN(0, 2);
|
---|
10596 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
10597 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10598 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10599 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10600 | IEM_MC_FETCH_MEM_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
10601 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Value);
|
---|
10602 | IEM_MC_ADVANCE_RIP();
|
---|
10603 | IEM_MC_END();
|
---|
10604 | break;
|
---|
10605 |
|
---|
10606 | case IEMMODE_32BIT:
|
---|
10607 | IEM_MC_BEGIN(0, 2);
|
---|
10608 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
10609 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10610 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10611 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10612 | IEM_MC_FETCH_MEM_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
10613 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Value);
|
---|
10614 | IEM_MC_ADVANCE_RIP();
|
---|
10615 | IEM_MC_END();
|
---|
10616 | break;
|
---|
10617 |
|
---|
10618 | case IEMMODE_64BIT:
|
---|
10619 | IEM_MC_BEGIN(0, 2);
|
---|
10620 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
10621 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10622 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10623 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10624 | IEM_MC_FETCH_MEM_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
10625 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Value);
|
---|
10626 | IEM_MC_ADVANCE_RIP();
|
---|
10627 | IEM_MC_END();
|
---|
10628 | break;
|
---|
10629 | }
|
---|
10630 | }
|
---|
10631 | return VINF_SUCCESS;
|
---|
10632 | }
|
---|
10633 |
|
---|
10634 |
|
---|
10635 | /** Opcode 0x63. */
|
---|
10636 | FNIEMOP_DEF(iemOp_arpl_Ew_Gw_movsx_Gv_Ev)
|
---|
10637 | {
|
---|
10638 | if (pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT)
|
---|
10639 | return FNIEMOP_CALL(iemOp_arpl_Ew_Gw);
|
---|
10640 | if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
|
---|
10641 | return FNIEMOP_CALL(iemOp_mov_Gv_Ev);
|
---|
10642 | return FNIEMOP_CALL(iemOp_movsxd_Gv_Ev);
|
---|
10643 | }
|
---|
10644 |
|
---|
10645 |
|
---|
10646 | /** Opcode 0x8c. */
|
---|
10647 | FNIEMOP_DEF(iemOp_mov_Ev_Sw)
|
---|
10648 | {
|
---|
10649 | IEMOP_MNEMONIC("mov Ev,Sw");
|
---|
10650 |
|
---|
10651 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10652 |
|
---|
10653 | /*
|
---|
10654 | * Check that the destination register exists. The REX.R prefix is ignored.
|
---|
10655 | */
|
---|
10656 | uint8_t const iSegReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
10657 | if ( iSegReg > X86_SREG_GS)
|
---|
10658 | return IEMOP_RAISE_INVALID_OPCODE(); /** @todo should probably not be raised until we've fetched all the opcode bytes? */
|
---|
10659 |
|
---|
10660 | /*
|
---|
10661 | * If rm is denoting a register, no more instruction bytes.
|
---|
10662 | * In that case, the operand size is respected and the upper bits are
|
---|
10663 | * cleared (starting with some pentium).
|
---|
10664 | */
|
---|
10665 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10666 | {
|
---|
10667 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10668 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10669 | {
|
---|
10670 | case IEMMODE_16BIT:
|
---|
10671 | IEM_MC_BEGIN(0, 1);
|
---|
10672 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
10673 | IEM_MC_FETCH_SREG_U16(u16Value, iSegReg);
|
---|
10674 | IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Value);
|
---|
10675 | IEM_MC_ADVANCE_RIP();
|
---|
10676 | IEM_MC_END();
|
---|
10677 | break;
|
---|
10678 |
|
---|
10679 | case IEMMODE_32BIT:
|
---|
10680 | IEM_MC_BEGIN(0, 1);
|
---|
10681 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
10682 | IEM_MC_FETCH_SREG_ZX_U32(u32Value, iSegReg);
|
---|
10683 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Value);
|
---|
10684 | IEM_MC_ADVANCE_RIP();
|
---|
10685 | IEM_MC_END();
|
---|
10686 | break;
|
---|
10687 |
|
---|
10688 | case IEMMODE_64BIT:
|
---|
10689 | IEM_MC_BEGIN(0, 1);
|
---|
10690 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
10691 | IEM_MC_FETCH_SREG_ZX_U64(u64Value, iSegReg);
|
---|
10692 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Value);
|
---|
10693 | IEM_MC_ADVANCE_RIP();
|
---|
10694 | IEM_MC_END();
|
---|
10695 | break;
|
---|
10696 | }
|
---|
10697 | }
|
---|
10698 | else
|
---|
10699 | {
|
---|
10700 | /*
|
---|
10701 | * We're saving the register to memory. The access is word sized
|
---|
10702 | * regardless of operand size prefixes.
|
---|
10703 | */
|
---|
10704 | #if 0 /* not necessary */
|
---|
10705 | pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_16BIT;
|
---|
10706 | #endif
|
---|
10707 | IEM_MC_BEGIN(0, 2);
|
---|
10708 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
10709 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10710 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10711 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10712 | IEM_MC_FETCH_SREG_U16(u16Value, iSegReg);
|
---|
10713 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value);
|
---|
10714 | IEM_MC_ADVANCE_RIP();
|
---|
10715 | IEM_MC_END();
|
---|
10716 | }
|
---|
10717 | return VINF_SUCCESS;
|
---|
10718 | }
|
---|
10719 |
|
---|
10720 |
|
---|
10721 |
|
---|
10722 |
|
---|
10723 | /** Opcode 0x8d. */
|
---|
10724 | FNIEMOP_DEF(iemOp_lea_Gv_M)
|
---|
10725 | {
|
---|
10726 | IEMOP_MNEMONIC("lea Gv,M");
|
---|
10727 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10728 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10729 | return IEMOP_RAISE_INVALID_OPCODE(); /* no register form */
|
---|
10730 |
|
---|
10731 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10732 | {
|
---|
10733 | case IEMMODE_16BIT:
|
---|
10734 | IEM_MC_BEGIN(0, 2);
|
---|
10735 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
10736 | IEM_MC_LOCAL(uint16_t, u16Cast);
|
---|
10737 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
10738 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10739 | IEM_MC_ASSIGN_TO_SMALLER(u16Cast, GCPtrEffSrc);
|
---|
10740 | IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u16Cast);
|
---|
10741 | IEM_MC_ADVANCE_RIP();
|
---|
10742 | IEM_MC_END();
|
---|
10743 | return VINF_SUCCESS;
|
---|
10744 |
|
---|
10745 | case IEMMODE_32BIT:
|
---|
10746 | IEM_MC_BEGIN(0, 2);
|
---|
10747 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
10748 | IEM_MC_LOCAL(uint32_t, u32Cast);
|
---|
10749 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
10750 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10751 | IEM_MC_ASSIGN_TO_SMALLER(u32Cast, GCPtrEffSrc);
|
---|
10752 | IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Cast);
|
---|
10753 | IEM_MC_ADVANCE_RIP();
|
---|
10754 | IEM_MC_END();
|
---|
10755 | return VINF_SUCCESS;
|
---|
10756 |
|
---|
10757 | case IEMMODE_64BIT:
|
---|
10758 | IEM_MC_BEGIN(0, 1);
|
---|
10759 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
10760 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
10761 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10762 | IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, GCPtrEffSrc);
|
---|
10763 | IEM_MC_ADVANCE_RIP();
|
---|
10764 | IEM_MC_END();
|
---|
10765 | return VINF_SUCCESS;
|
---|
10766 | }
|
---|
10767 | AssertFailedReturn(VERR_IEM_IPE_7);
|
---|
10768 | }
|
---|
10769 |
|
---|
10770 |
|
---|
10771 | /** Opcode 0x8e. */
|
---|
10772 | FNIEMOP_DEF(iemOp_mov_Sw_Ev)
|
---|
10773 | {
|
---|
10774 | IEMOP_MNEMONIC("mov Sw,Ev");
|
---|
10775 |
|
---|
10776 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10777 |
|
---|
10778 | /*
|
---|
10779 | * The practical operand size is 16-bit.
|
---|
10780 | */
|
---|
10781 | #if 0 /* not necessary */
|
---|
10782 | pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_16BIT;
|
---|
10783 | #endif
|
---|
10784 |
|
---|
10785 | /*
|
---|
10786 | * Check that the destination register exists and can be used with this
|
---|
10787 | * instruction. The REX.R prefix is ignored.
|
---|
10788 | */
|
---|
10789 | uint8_t const iSegReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
|
---|
10790 | if ( iSegReg == X86_SREG_CS
|
---|
10791 | || iSegReg > X86_SREG_GS)
|
---|
10792 | return IEMOP_RAISE_INVALID_OPCODE(); /** @todo should probably not be raised until we've fetched all the opcode bytes? */
|
---|
10793 |
|
---|
10794 | /*
|
---|
10795 | * If rm is denoting a register, no more instruction bytes.
|
---|
10796 | */
|
---|
10797 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10798 | {
|
---|
10799 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10800 | IEM_MC_BEGIN(2, 0);
|
---|
10801 | IEM_MC_ARG_CONST(uint8_t, iSRegArg, iSegReg, 0);
|
---|
10802 | IEM_MC_ARG(uint16_t, u16Value, 1);
|
---|
10803 | IEM_MC_FETCH_GREG_U16(u16Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10804 | IEM_MC_CALL_CIMPL_2(iemCImpl_load_SReg, iSRegArg, u16Value);
|
---|
10805 | IEM_MC_END();
|
---|
10806 | }
|
---|
10807 | else
|
---|
10808 | {
|
---|
10809 | /*
|
---|
10810 | * We're loading the register from memory. The access is word sized
|
---|
10811 | * regardless of operand size prefixes.
|
---|
10812 | */
|
---|
10813 | IEM_MC_BEGIN(2, 1);
|
---|
10814 | IEM_MC_ARG_CONST(uint8_t, iSRegArg, iSegReg, 0);
|
---|
10815 | IEM_MC_ARG(uint16_t, u16Value, 1);
|
---|
10816 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
10817 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
10818 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10819 | IEM_MC_FETCH_MEM_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
10820 | IEM_MC_CALL_CIMPL_2(iemCImpl_load_SReg, iSRegArg, u16Value);
|
---|
10821 | IEM_MC_END();
|
---|
10822 | }
|
---|
10823 | return VINF_SUCCESS;
|
---|
10824 | }
|
---|
10825 |
|
---|
10826 |
|
---|
10827 | /** Opcode 0x8f /0. */
|
---|
10828 | FNIEMOP_DEF_1(iemOp_pop_Ev, uint8_t, bRm)
|
---|
10829 | {
|
---|
10830 | /* This bugger is rather annoying as it requires rSP to be updated before
|
---|
10831 | doing the effective address calculations. Will eventually require a
|
---|
10832 | split between the R/M+SIB decoding and the effective address
|
---|
10833 | calculation - which is something that is required for any attempt at
|
---|
10834 | reusing this code for a recompiler. It may also be good to have if we
|
---|
10835 | need to delay #UD exception caused by invalid lock prefixes.
|
---|
10836 |
|
---|
10837 | For now, we'll do a mostly safe interpreter-only implementation here. */
|
---|
10838 | /** @todo What's the deal with the 'reg' field and pop Ev? Ignorning it for
|
---|
10839 | * now until tests show it's checked.. */
|
---|
10840 | IEMOP_MNEMONIC("pop Ev");
|
---|
10841 |
|
---|
10842 | /* Register access is relatively easy and can share code. */
|
---|
10843 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
10844 | return FNIEMOP_CALL_1(iemOpCommonPopGReg, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
10845 |
|
---|
10846 | /*
|
---|
10847 | * Memory target.
|
---|
10848 | *
|
---|
10849 | * Intel says that RSP is incremented before it's used in any effective
|
---|
10850 | * address calcuations. This means some serious extra annoyance here since
|
---|
10851 | * we decode and calculate the effective address in one step and like to
|
---|
10852 | * delay committing registers till everything is done.
|
---|
10853 | *
|
---|
10854 | * So, we'll decode and calculate the effective address twice. This will
|
---|
10855 | * require some recoding if turned into a recompiler.
|
---|
10856 | */
|
---|
10857 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE(); /* The common code does this differently. */
|
---|
10858 |
|
---|
10859 | #ifndef TST_IEM_CHECK_MC
|
---|
10860 | /* Calc effective address with modified ESP. */
|
---|
10861 | /** @todo testcase */
|
---|
10862 | PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
|
---|
10863 | RTGCPTR GCPtrEff;
|
---|
10864 | VBOXSTRICTRC rcStrict;
|
---|
10865 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10866 | {
|
---|
10867 | case IEMMODE_16BIT: rcStrict = iemOpHlpCalcRmEffAddrEx(pVCpu, bRm, 0, &GCPtrEff, 2); break;
|
---|
10868 | case IEMMODE_32BIT: rcStrict = iemOpHlpCalcRmEffAddrEx(pVCpu, bRm, 0, &GCPtrEff, 4); break;
|
---|
10869 | case IEMMODE_64BIT: rcStrict = iemOpHlpCalcRmEffAddrEx(pVCpu, bRm, 0, &GCPtrEff, 8); break;
|
---|
10870 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
10871 | }
|
---|
10872 | if (rcStrict != VINF_SUCCESS)
|
---|
10873 | return rcStrict;
|
---|
10874 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10875 |
|
---|
10876 | /* Perform the operation - this should be CImpl. */
|
---|
10877 | RTUINT64U TmpRsp;
|
---|
10878 | TmpRsp.u = pCtx->rsp;
|
---|
10879 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10880 | {
|
---|
10881 | case IEMMODE_16BIT:
|
---|
10882 | {
|
---|
10883 | uint16_t u16Value;
|
---|
10884 | rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Value, &TmpRsp);
|
---|
10885 | if (rcStrict == VINF_SUCCESS)
|
---|
10886 | rcStrict = iemMemStoreDataU16(pVCpu, pVCpu->iem.s.iEffSeg, GCPtrEff, u16Value);
|
---|
10887 | break;
|
---|
10888 | }
|
---|
10889 |
|
---|
10890 | case IEMMODE_32BIT:
|
---|
10891 | {
|
---|
10892 | uint32_t u32Value;
|
---|
10893 | rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Value, &TmpRsp);
|
---|
10894 | if (rcStrict == VINF_SUCCESS)
|
---|
10895 | rcStrict = iemMemStoreDataU32(pVCpu, pVCpu->iem.s.iEffSeg, GCPtrEff, u32Value);
|
---|
10896 | break;
|
---|
10897 | }
|
---|
10898 |
|
---|
10899 | case IEMMODE_64BIT:
|
---|
10900 | {
|
---|
10901 | uint64_t u64Value;
|
---|
10902 | rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Value, &TmpRsp);
|
---|
10903 | if (rcStrict == VINF_SUCCESS)
|
---|
10904 | rcStrict = iemMemStoreDataU64(pVCpu, pVCpu->iem.s.iEffSeg, GCPtrEff, u64Value);
|
---|
10905 | break;
|
---|
10906 | }
|
---|
10907 |
|
---|
10908 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
10909 | }
|
---|
10910 | if (rcStrict == VINF_SUCCESS)
|
---|
10911 | {
|
---|
10912 | pCtx->rsp = TmpRsp.u;
|
---|
10913 | iemRegUpdateRipAndClearRF(pVCpu);
|
---|
10914 | }
|
---|
10915 | return rcStrict;
|
---|
10916 |
|
---|
10917 | #else
|
---|
10918 | return VERR_IEM_IPE_2;
|
---|
10919 | #endif
|
---|
10920 | }
|
---|
10921 |
|
---|
10922 |
|
---|
10923 | /** Opcode 0x8f. */
|
---|
10924 | FNIEMOP_DEF(iemOp_Grp1A)
|
---|
10925 | {
|
---|
10926 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
10927 | if ((bRm & X86_MODRM_REG_MASK) == (0 << X86_MODRM_REG_SHIFT)) /* /0 */
|
---|
10928 | return FNIEMOP_CALL_1(iemOp_pop_Ev, bRm);
|
---|
10929 |
|
---|
10930 | /* AMD has defined /1 thru /7 as XOP prefix (similar to three byte VEX). */
|
---|
10931 | /** @todo XOP decoding. */
|
---|
10932 | IEMOP_MNEMONIC("3-byte-xop");
|
---|
10933 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
10934 | }
|
---|
10935 |
|
---|
10936 |
|
---|
10937 | /**
|
---|
10938 | * Common 'xchg reg,rAX' helper.
|
---|
10939 | */
|
---|
10940 | FNIEMOP_DEF_1(iemOpCommonXchgGRegRax, uint8_t, iReg)
|
---|
10941 | {
|
---|
10942 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
10943 |
|
---|
10944 | iReg |= pVCpu->iem.s.uRexB;
|
---|
10945 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
10946 | {
|
---|
10947 | case IEMMODE_16BIT:
|
---|
10948 | IEM_MC_BEGIN(0, 2);
|
---|
10949 | IEM_MC_LOCAL(uint16_t, u16Tmp1);
|
---|
10950 | IEM_MC_LOCAL(uint16_t, u16Tmp2);
|
---|
10951 | IEM_MC_FETCH_GREG_U16(u16Tmp1, iReg);
|
---|
10952 | IEM_MC_FETCH_GREG_U16(u16Tmp2, X86_GREG_xAX);
|
---|
10953 | IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp1);
|
---|
10954 | IEM_MC_STORE_GREG_U16(iReg, u16Tmp2);
|
---|
10955 | IEM_MC_ADVANCE_RIP();
|
---|
10956 | IEM_MC_END();
|
---|
10957 | return VINF_SUCCESS;
|
---|
10958 |
|
---|
10959 | case IEMMODE_32BIT:
|
---|
10960 | IEM_MC_BEGIN(0, 2);
|
---|
10961 | IEM_MC_LOCAL(uint32_t, u32Tmp1);
|
---|
10962 | IEM_MC_LOCAL(uint32_t, u32Tmp2);
|
---|
10963 | IEM_MC_FETCH_GREG_U32(u32Tmp1, iReg);
|
---|
10964 | IEM_MC_FETCH_GREG_U32(u32Tmp2, X86_GREG_xAX);
|
---|
10965 | IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Tmp1);
|
---|
10966 | IEM_MC_STORE_GREG_U32(iReg, u32Tmp2);
|
---|
10967 | IEM_MC_ADVANCE_RIP();
|
---|
10968 | IEM_MC_END();
|
---|
10969 | return VINF_SUCCESS;
|
---|
10970 |
|
---|
10971 | case IEMMODE_64BIT:
|
---|
10972 | IEM_MC_BEGIN(0, 2);
|
---|
10973 | IEM_MC_LOCAL(uint64_t, u64Tmp1);
|
---|
10974 | IEM_MC_LOCAL(uint64_t, u64Tmp2);
|
---|
10975 | IEM_MC_FETCH_GREG_U64(u64Tmp1, iReg);
|
---|
10976 | IEM_MC_FETCH_GREG_U64(u64Tmp2, X86_GREG_xAX);
|
---|
10977 | IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Tmp1);
|
---|
10978 | IEM_MC_STORE_GREG_U64(iReg, u64Tmp2);
|
---|
10979 | IEM_MC_ADVANCE_RIP();
|
---|
10980 | IEM_MC_END();
|
---|
10981 | return VINF_SUCCESS;
|
---|
10982 |
|
---|
10983 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
10984 | }
|
---|
10985 | }
|
---|
10986 |
|
---|
10987 |
|
---|
10988 | /** Opcode 0x90. */
|
---|
10989 | FNIEMOP_DEF(iemOp_nop)
|
---|
10990 | {
|
---|
10991 | /* R8/R8D and RAX/EAX can be exchanged. */
|
---|
10992 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_B)
|
---|
10993 | {
|
---|
10994 | IEMOP_MNEMONIC("xchg r8,rAX");
|
---|
10995 | return FNIEMOP_CALL_1(iemOpCommonXchgGRegRax, X86_GREG_xAX);
|
---|
10996 | }
|
---|
10997 |
|
---|
10998 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)
|
---|
10999 | IEMOP_MNEMONIC("pause");
|
---|
11000 | else
|
---|
11001 | IEMOP_MNEMONIC("nop");
|
---|
11002 | IEM_MC_BEGIN(0, 0);
|
---|
11003 | IEM_MC_ADVANCE_RIP();
|
---|
11004 | IEM_MC_END();
|
---|
11005 | return VINF_SUCCESS;
|
---|
11006 | }
|
---|
11007 |
|
---|
11008 |
|
---|
11009 | /** Opcode 0x91. */
|
---|
11010 | FNIEMOP_DEF(iemOp_xchg_eCX_eAX)
|
---|
11011 | {
|
---|
11012 | IEMOP_MNEMONIC("xchg rCX,rAX");
|
---|
11013 | return FNIEMOP_CALL_1(iemOpCommonXchgGRegRax, X86_GREG_xCX);
|
---|
11014 | }
|
---|
11015 |
|
---|
11016 |
|
---|
11017 | /** Opcode 0x92. */
|
---|
11018 | FNIEMOP_DEF(iemOp_xchg_eDX_eAX)
|
---|
11019 | {
|
---|
11020 | IEMOP_MNEMONIC("xchg rDX,rAX");
|
---|
11021 | return FNIEMOP_CALL_1(iemOpCommonXchgGRegRax, X86_GREG_xDX);
|
---|
11022 | }
|
---|
11023 |
|
---|
11024 |
|
---|
11025 | /** Opcode 0x93. */
|
---|
11026 | FNIEMOP_DEF(iemOp_xchg_eBX_eAX)
|
---|
11027 | {
|
---|
11028 | IEMOP_MNEMONIC("xchg rBX,rAX");
|
---|
11029 | return FNIEMOP_CALL_1(iemOpCommonXchgGRegRax, X86_GREG_xBX);
|
---|
11030 | }
|
---|
11031 |
|
---|
11032 |
|
---|
11033 | /** Opcode 0x94. */
|
---|
11034 | FNIEMOP_DEF(iemOp_xchg_eSP_eAX)
|
---|
11035 | {
|
---|
11036 | IEMOP_MNEMONIC("xchg rSX,rAX");
|
---|
11037 | return FNIEMOP_CALL_1(iemOpCommonXchgGRegRax, X86_GREG_xSP);
|
---|
11038 | }
|
---|
11039 |
|
---|
11040 |
|
---|
11041 | /** Opcode 0x95. */
|
---|
11042 | FNIEMOP_DEF(iemOp_xchg_eBP_eAX)
|
---|
11043 | {
|
---|
11044 | IEMOP_MNEMONIC("xchg rBP,rAX");
|
---|
11045 | return FNIEMOP_CALL_1(iemOpCommonXchgGRegRax, X86_GREG_xBP);
|
---|
11046 | }
|
---|
11047 |
|
---|
11048 |
|
---|
11049 | /** Opcode 0x96. */
|
---|
11050 | FNIEMOP_DEF(iemOp_xchg_eSI_eAX)
|
---|
11051 | {
|
---|
11052 | IEMOP_MNEMONIC("xchg rSI,rAX");
|
---|
11053 | return FNIEMOP_CALL_1(iemOpCommonXchgGRegRax, X86_GREG_xSI);
|
---|
11054 | }
|
---|
11055 |
|
---|
11056 |
|
---|
11057 | /** Opcode 0x97. */
|
---|
11058 | FNIEMOP_DEF(iemOp_xchg_eDI_eAX)
|
---|
11059 | {
|
---|
11060 | IEMOP_MNEMONIC("xchg rDI,rAX");
|
---|
11061 | return FNIEMOP_CALL_1(iemOpCommonXchgGRegRax, X86_GREG_xDI);
|
---|
11062 | }
|
---|
11063 |
|
---|
11064 |
|
---|
11065 | /** Opcode 0x98. */
|
---|
11066 | FNIEMOP_DEF(iemOp_cbw)
|
---|
11067 | {
|
---|
11068 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11069 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11070 | {
|
---|
11071 | case IEMMODE_16BIT:
|
---|
11072 | IEMOP_MNEMONIC("cbw");
|
---|
11073 | IEM_MC_BEGIN(0, 1);
|
---|
11074 | IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 7) {
|
---|
11075 | IEM_MC_OR_GREG_U16(X86_GREG_xAX, UINT16_C(0xff00));
|
---|
11076 | } IEM_MC_ELSE() {
|
---|
11077 | IEM_MC_AND_GREG_U16(X86_GREG_xAX, UINT16_C(0x00ff));
|
---|
11078 | } IEM_MC_ENDIF();
|
---|
11079 | IEM_MC_ADVANCE_RIP();
|
---|
11080 | IEM_MC_END();
|
---|
11081 | return VINF_SUCCESS;
|
---|
11082 |
|
---|
11083 | case IEMMODE_32BIT:
|
---|
11084 | IEMOP_MNEMONIC("cwde");
|
---|
11085 | IEM_MC_BEGIN(0, 1);
|
---|
11086 | IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 15) {
|
---|
11087 | IEM_MC_OR_GREG_U32(X86_GREG_xAX, UINT32_C(0xffff0000));
|
---|
11088 | } IEM_MC_ELSE() {
|
---|
11089 | IEM_MC_AND_GREG_U32(X86_GREG_xAX, UINT32_C(0x0000ffff));
|
---|
11090 | } IEM_MC_ENDIF();
|
---|
11091 | IEM_MC_ADVANCE_RIP();
|
---|
11092 | IEM_MC_END();
|
---|
11093 | return VINF_SUCCESS;
|
---|
11094 |
|
---|
11095 | case IEMMODE_64BIT:
|
---|
11096 | IEMOP_MNEMONIC("cdqe");
|
---|
11097 | IEM_MC_BEGIN(0, 1);
|
---|
11098 | IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 31) {
|
---|
11099 | IEM_MC_OR_GREG_U64(X86_GREG_xAX, UINT64_C(0xffffffff00000000));
|
---|
11100 | } IEM_MC_ELSE() {
|
---|
11101 | IEM_MC_AND_GREG_U64(X86_GREG_xAX, UINT64_C(0x00000000ffffffff));
|
---|
11102 | } IEM_MC_ENDIF();
|
---|
11103 | IEM_MC_ADVANCE_RIP();
|
---|
11104 | IEM_MC_END();
|
---|
11105 | return VINF_SUCCESS;
|
---|
11106 |
|
---|
11107 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11108 | }
|
---|
11109 | }
|
---|
11110 |
|
---|
11111 |
|
---|
11112 | /** Opcode 0x99. */
|
---|
11113 | FNIEMOP_DEF(iemOp_cwd)
|
---|
11114 | {
|
---|
11115 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11116 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11117 | {
|
---|
11118 | case IEMMODE_16BIT:
|
---|
11119 | IEMOP_MNEMONIC("cwd");
|
---|
11120 | IEM_MC_BEGIN(0, 1);
|
---|
11121 | IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 15) {
|
---|
11122 | IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xDX, UINT16_C(0xffff));
|
---|
11123 | } IEM_MC_ELSE() {
|
---|
11124 | IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xDX, 0);
|
---|
11125 | } IEM_MC_ENDIF();
|
---|
11126 | IEM_MC_ADVANCE_RIP();
|
---|
11127 | IEM_MC_END();
|
---|
11128 | return VINF_SUCCESS;
|
---|
11129 |
|
---|
11130 | case IEMMODE_32BIT:
|
---|
11131 | IEMOP_MNEMONIC("cdq");
|
---|
11132 | IEM_MC_BEGIN(0, 1);
|
---|
11133 | IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 31) {
|
---|
11134 | IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xDX, UINT32_C(0xffffffff));
|
---|
11135 | } IEM_MC_ELSE() {
|
---|
11136 | IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xDX, 0);
|
---|
11137 | } IEM_MC_ENDIF();
|
---|
11138 | IEM_MC_ADVANCE_RIP();
|
---|
11139 | IEM_MC_END();
|
---|
11140 | return VINF_SUCCESS;
|
---|
11141 |
|
---|
11142 | case IEMMODE_64BIT:
|
---|
11143 | IEMOP_MNEMONIC("cqo");
|
---|
11144 | IEM_MC_BEGIN(0, 1);
|
---|
11145 | IEM_MC_IF_GREG_BIT_SET(X86_GREG_xAX, 63) {
|
---|
11146 | IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xDX, UINT64_C(0xffffffffffffffff));
|
---|
11147 | } IEM_MC_ELSE() {
|
---|
11148 | IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xDX, 0);
|
---|
11149 | } IEM_MC_ENDIF();
|
---|
11150 | IEM_MC_ADVANCE_RIP();
|
---|
11151 | IEM_MC_END();
|
---|
11152 | return VINF_SUCCESS;
|
---|
11153 |
|
---|
11154 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11155 | }
|
---|
11156 | }
|
---|
11157 |
|
---|
11158 |
|
---|
11159 | /** Opcode 0x9a. */
|
---|
11160 | FNIEMOP_DEF(iemOp_call_Ap)
|
---|
11161 | {
|
---|
11162 | IEMOP_MNEMONIC("call Ap");
|
---|
11163 | IEMOP_HLP_NO_64BIT();
|
---|
11164 |
|
---|
11165 | /* Decode the far pointer address and pass it on to the far call C implementation. */
|
---|
11166 | uint32_t offSeg;
|
---|
11167 | if (pVCpu->iem.s.enmEffOpSize != IEMMODE_16BIT)
|
---|
11168 | IEM_OPCODE_GET_NEXT_U32(&offSeg);
|
---|
11169 | else
|
---|
11170 | IEM_OPCODE_GET_NEXT_U16_ZX_U32(&offSeg);
|
---|
11171 | uint16_t uSel; IEM_OPCODE_GET_NEXT_U16(&uSel);
|
---|
11172 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11173 | return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_callf, uSel, offSeg, pVCpu->iem.s.enmEffOpSize);
|
---|
11174 | }
|
---|
11175 |
|
---|
11176 |
|
---|
11177 | /** Opcode 0x9b. (aka fwait) */
|
---|
11178 | FNIEMOP_DEF(iemOp_wait)
|
---|
11179 | {
|
---|
11180 | IEMOP_MNEMONIC("wait");
|
---|
11181 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11182 |
|
---|
11183 | IEM_MC_BEGIN(0, 0);
|
---|
11184 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
11185 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
11186 | IEM_MC_ADVANCE_RIP();
|
---|
11187 | IEM_MC_END();
|
---|
11188 | return VINF_SUCCESS;
|
---|
11189 | }
|
---|
11190 |
|
---|
11191 |
|
---|
11192 | /** Opcode 0x9c. */
|
---|
11193 | FNIEMOP_DEF(iemOp_pushf_Fv)
|
---|
11194 | {
|
---|
11195 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11196 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
11197 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_pushf, pVCpu->iem.s.enmEffOpSize);
|
---|
11198 | }
|
---|
11199 |
|
---|
11200 |
|
---|
11201 | /** Opcode 0x9d. */
|
---|
11202 | FNIEMOP_DEF(iemOp_popf_Fv)
|
---|
11203 | {
|
---|
11204 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11205 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
11206 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_popf, pVCpu->iem.s.enmEffOpSize);
|
---|
11207 | }
|
---|
11208 |
|
---|
11209 |
|
---|
11210 | /** Opcode 0x9e. */
|
---|
11211 | FNIEMOP_DEF(iemOp_sahf)
|
---|
11212 | {
|
---|
11213 | IEMOP_MNEMONIC("sahf");
|
---|
11214 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11215 | if ( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
|
---|
11216 | && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLahfSahf)
|
---|
11217 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
11218 | IEM_MC_BEGIN(0, 2);
|
---|
11219 | IEM_MC_LOCAL(uint32_t, u32Flags);
|
---|
11220 | IEM_MC_LOCAL(uint32_t, EFlags);
|
---|
11221 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
11222 | IEM_MC_FETCH_GREG_U8_ZX_U32(u32Flags, X86_GREG_xSP/*=AH*/);
|
---|
11223 | IEM_MC_AND_LOCAL_U32(u32Flags, X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
|
---|
11224 | IEM_MC_AND_LOCAL_U32(EFlags, UINT32_C(0xffffff00));
|
---|
11225 | IEM_MC_OR_LOCAL_U32(u32Flags, X86_EFL_1);
|
---|
11226 | IEM_MC_OR_2LOCS_U32(EFlags, u32Flags);
|
---|
11227 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
11228 | IEM_MC_ADVANCE_RIP();
|
---|
11229 | IEM_MC_END();
|
---|
11230 | return VINF_SUCCESS;
|
---|
11231 | }
|
---|
11232 |
|
---|
11233 |
|
---|
11234 | /** Opcode 0x9f. */
|
---|
11235 | FNIEMOP_DEF(iemOp_lahf)
|
---|
11236 | {
|
---|
11237 | IEMOP_MNEMONIC("lahf");
|
---|
11238 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11239 | if ( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
|
---|
11240 | && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLahfSahf)
|
---|
11241 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
11242 | IEM_MC_BEGIN(0, 1);
|
---|
11243 | IEM_MC_LOCAL(uint8_t, u8Flags);
|
---|
11244 | IEM_MC_FETCH_EFLAGS_U8(u8Flags);
|
---|
11245 | IEM_MC_STORE_GREG_U8(X86_GREG_xSP/*=AH*/, u8Flags);
|
---|
11246 | IEM_MC_ADVANCE_RIP();
|
---|
11247 | IEM_MC_END();
|
---|
11248 | return VINF_SUCCESS;
|
---|
11249 | }
|
---|
11250 |
|
---|
11251 |
|
---|
11252 | /**
|
---|
11253 | * Macro used by iemOp_mov_Al_Ob, iemOp_mov_rAX_Ov, iemOp_mov_Ob_AL and
|
---|
11254 | * iemOp_mov_Ov_rAX to fetch the moffsXX bit of the opcode and fend of lock
|
---|
11255 | * prefixes. Will return on failures.
|
---|
11256 | * @param a_GCPtrMemOff The variable to store the offset in.
|
---|
11257 | */
|
---|
11258 | #define IEMOP_FETCH_MOFFS_XX(a_GCPtrMemOff) \
|
---|
11259 | do \
|
---|
11260 | { \
|
---|
11261 | switch (pVCpu->iem.s.enmEffAddrMode) \
|
---|
11262 | { \
|
---|
11263 | case IEMMODE_16BIT: \
|
---|
11264 | IEM_OPCODE_GET_NEXT_U16_ZX_U64(&(a_GCPtrMemOff)); \
|
---|
11265 | break; \
|
---|
11266 | case IEMMODE_32BIT: \
|
---|
11267 | IEM_OPCODE_GET_NEXT_U32_ZX_U64(&(a_GCPtrMemOff)); \
|
---|
11268 | break; \
|
---|
11269 | case IEMMODE_64BIT: \
|
---|
11270 | IEM_OPCODE_GET_NEXT_U64(&(a_GCPtrMemOff)); \
|
---|
11271 | break; \
|
---|
11272 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
|
---|
11273 | } \
|
---|
11274 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
|
---|
11275 | } while (0)
|
---|
11276 |
|
---|
11277 | /** Opcode 0xa0. */
|
---|
11278 | FNIEMOP_DEF(iemOp_mov_Al_Ob)
|
---|
11279 | {
|
---|
11280 | /*
|
---|
11281 | * Get the offset and fend of lock prefixes.
|
---|
11282 | */
|
---|
11283 | RTGCPTR GCPtrMemOff;
|
---|
11284 | IEMOP_FETCH_MOFFS_XX(GCPtrMemOff);
|
---|
11285 |
|
---|
11286 | /*
|
---|
11287 | * Fetch AL.
|
---|
11288 | */
|
---|
11289 | IEM_MC_BEGIN(0,1);
|
---|
11290 | IEM_MC_LOCAL(uint8_t, u8Tmp);
|
---|
11291 | IEM_MC_FETCH_MEM_U8(u8Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff);
|
---|
11292 | IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp);
|
---|
11293 | IEM_MC_ADVANCE_RIP();
|
---|
11294 | IEM_MC_END();
|
---|
11295 | return VINF_SUCCESS;
|
---|
11296 | }
|
---|
11297 |
|
---|
11298 |
|
---|
11299 | /** Opcode 0xa1. */
|
---|
11300 | FNIEMOP_DEF(iemOp_mov_rAX_Ov)
|
---|
11301 | {
|
---|
11302 | /*
|
---|
11303 | * Get the offset and fend of lock prefixes.
|
---|
11304 | */
|
---|
11305 | IEMOP_MNEMONIC("mov rAX,Ov");
|
---|
11306 | RTGCPTR GCPtrMemOff;
|
---|
11307 | IEMOP_FETCH_MOFFS_XX(GCPtrMemOff);
|
---|
11308 |
|
---|
11309 | /*
|
---|
11310 | * Fetch rAX.
|
---|
11311 | */
|
---|
11312 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11313 | {
|
---|
11314 | case IEMMODE_16BIT:
|
---|
11315 | IEM_MC_BEGIN(0,1);
|
---|
11316 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
11317 | IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff);
|
---|
11318 | IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp);
|
---|
11319 | IEM_MC_ADVANCE_RIP();
|
---|
11320 | IEM_MC_END();
|
---|
11321 | return VINF_SUCCESS;
|
---|
11322 |
|
---|
11323 | case IEMMODE_32BIT:
|
---|
11324 | IEM_MC_BEGIN(0,1);
|
---|
11325 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
11326 | IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff);
|
---|
11327 | IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Tmp);
|
---|
11328 | IEM_MC_ADVANCE_RIP();
|
---|
11329 | IEM_MC_END();
|
---|
11330 | return VINF_SUCCESS;
|
---|
11331 |
|
---|
11332 | case IEMMODE_64BIT:
|
---|
11333 | IEM_MC_BEGIN(0,1);
|
---|
11334 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
11335 | IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff);
|
---|
11336 | IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Tmp);
|
---|
11337 | IEM_MC_ADVANCE_RIP();
|
---|
11338 | IEM_MC_END();
|
---|
11339 | return VINF_SUCCESS;
|
---|
11340 |
|
---|
11341 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11342 | }
|
---|
11343 | }
|
---|
11344 |
|
---|
11345 |
|
---|
11346 | /** Opcode 0xa2. */
|
---|
11347 | FNIEMOP_DEF(iemOp_mov_Ob_AL)
|
---|
11348 | {
|
---|
11349 | /*
|
---|
11350 | * Get the offset and fend of lock prefixes.
|
---|
11351 | */
|
---|
11352 | RTGCPTR GCPtrMemOff;
|
---|
11353 | IEMOP_FETCH_MOFFS_XX(GCPtrMemOff);
|
---|
11354 |
|
---|
11355 | /*
|
---|
11356 | * Store AL.
|
---|
11357 | */
|
---|
11358 | IEM_MC_BEGIN(0,1);
|
---|
11359 | IEM_MC_LOCAL(uint8_t, u8Tmp);
|
---|
11360 | IEM_MC_FETCH_GREG_U8(u8Tmp, X86_GREG_xAX);
|
---|
11361 | IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u8Tmp);
|
---|
11362 | IEM_MC_ADVANCE_RIP();
|
---|
11363 | IEM_MC_END();
|
---|
11364 | return VINF_SUCCESS;
|
---|
11365 | }
|
---|
11366 |
|
---|
11367 |
|
---|
11368 | /** Opcode 0xa3. */
|
---|
11369 | FNIEMOP_DEF(iemOp_mov_Ov_rAX)
|
---|
11370 | {
|
---|
11371 | /*
|
---|
11372 | * Get the offset and fend of lock prefixes.
|
---|
11373 | */
|
---|
11374 | RTGCPTR GCPtrMemOff;
|
---|
11375 | IEMOP_FETCH_MOFFS_XX(GCPtrMemOff);
|
---|
11376 |
|
---|
11377 | /*
|
---|
11378 | * Store rAX.
|
---|
11379 | */
|
---|
11380 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11381 | {
|
---|
11382 | case IEMMODE_16BIT:
|
---|
11383 | IEM_MC_BEGIN(0,1);
|
---|
11384 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
11385 | IEM_MC_FETCH_GREG_U16(u16Tmp, X86_GREG_xAX);
|
---|
11386 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u16Tmp);
|
---|
11387 | IEM_MC_ADVANCE_RIP();
|
---|
11388 | IEM_MC_END();
|
---|
11389 | return VINF_SUCCESS;
|
---|
11390 |
|
---|
11391 | case IEMMODE_32BIT:
|
---|
11392 | IEM_MC_BEGIN(0,1);
|
---|
11393 | IEM_MC_LOCAL(uint32_t, u32Tmp);
|
---|
11394 | IEM_MC_FETCH_GREG_U32(u32Tmp, X86_GREG_xAX);
|
---|
11395 | IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u32Tmp);
|
---|
11396 | IEM_MC_ADVANCE_RIP();
|
---|
11397 | IEM_MC_END();
|
---|
11398 | return VINF_SUCCESS;
|
---|
11399 |
|
---|
11400 | case IEMMODE_64BIT:
|
---|
11401 | IEM_MC_BEGIN(0,1);
|
---|
11402 | IEM_MC_LOCAL(uint64_t, u64Tmp);
|
---|
11403 | IEM_MC_FETCH_GREG_U64(u64Tmp, X86_GREG_xAX);
|
---|
11404 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u64Tmp);
|
---|
11405 | IEM_MC_ADVANCE_RIP();
|
---|
11406 | IEM_MC_END();
|
---|
11407 | return VINF_SUCCESS;
|
---|
11408 |
|
---|
11409 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11410 | }
|
---|
11411 | }
|
---|
11412 |
|
---|
11413 | /** Macro used by iemOp_movsb_Xb_Yb and iemOp_movswd_Xv_Yv */
|
---|
11414 | #define IEM_MOVS_CASE(ValBits, AddrBits) \
|
---|
11415 | IEM_MC_BEGIN(0, 2); \
|
---|
11416 | IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
|
---|
11417 | IEM_MC_LOCAL(RTGCPTR, uAddr); \
|
---|
11418 | IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xSI); \
|
---|
11419 | IEM_MC_FETCH_MEM_U##ValBits(uValue, pVCpu->iem.s.iEffSeg, uAddr); \
|
---|
11420 | IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xDI); \
|
---|
11421 | IEM_MC_STORE_MEM_U##ValBits(X86_SREG_ES, uAddr, uValue); \
|
---|
11422 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_DF) { \
|
---|
11423 | IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
|
---|
11424 | IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \
|
---|
11425 | } IEM_MC_ELSE() { \
|
---|
11426 | IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
|
---|
11427 | IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \
|
---|
11428 | } IEM_MC_ENDIF(); \
|
---|
11429 | IEM_MC_ADVANCE_RIP(); \
|
---|
11430 | IEM_MC_END();
|
---|
11431 |
|
---|
11432 | /** Opcode 0xa4. */
|
---|
11433 | FNIEMOP_DEF(iemOp_movsb_Xb_Yb)
|
---|
11434 | {
|
---|
11435 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11436 |
|
---|
11437 | /*
|
---|
11438 | * Use the C implementation if a repeat prefix is encountered.
|
---|
11439 | */
|
---|
11440 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
11441 | {
|
---|
11442 | IEMOP_MNEMONIC("rep movsb Xb,Yb");
|
---|
11443 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11444 | {
|
---|
11445 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op8_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11446 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op8_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11447 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op8_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11448 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11449 | }
|
---|
11450 | }
|
---|
11451 | IEMOP_MNEMONIC("movsb Xb,Yb");
|
---|
11452 |
|
---|
11453 | /*
|
---|
11454 | * Sharing case implementation with movs[wdq] below.
|
---|
11455 | */
|
---|
11456 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11457 | {
|
---|
11458 | case IEMMODE_16BIT: IEM_MOVS_CASE(8, 16); break;
|
---|
11459 | case IEMMODE_32BIT: IEM_MOVS_CASE(8, 32); break;
|
---|
11460 | case IEMMODE_64BIT: IEM_MOVS_CASE(8, 64); break;
|
---|
11461 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11462 | }
|
---|
11463 | return VINF_SUCCESS;
|
---|
11464 | }
|
---|
11465 |
|
---|
11466 |
|
---|
11467 | /** Opcode 0xa5. */
|
---|
11468 | FNIEMOP_DEF(iemOp_movswd_Xv_Yv)
|
---|
11469 | {
|
---|
11470 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11471 |
|
---|
11472 | /*
|
---|
11473 | * Use the C implementation if a repeat prefix is encountered.
|
---|
11474 | */
|
---|
11475 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
11476 | {
|
---|
11477 | IEMOP_MNEMONIC("rep movs Xv,Yv");
|
---|
11478 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11479 | {
|
---|
11480 | case IEMMODE_16BIT:
|
---|
11481 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11482 | {
|
---|
11483 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op16_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11484 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op16_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11485 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op16_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11486 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11487 | }
|
---|
11488 | break;
|
---|
11489 | case IEMMODE_32BIT:
|
---|
11490 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11491 | {
|
---|
11492 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op32_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11493 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op32_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11494 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op32_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11495 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11496 | }
|
---|
11497 | case IEMMODE_64BIT:
|
---|
11498 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11499 | {
|
---|
11500 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_6);
|
---|
11501 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op64_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11502 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_rep_movs_op64_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11503 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11504 | }
|
---|
11505 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11506 | }
|
---|
11507 | }
|
---|
11508 | IEMOP_MNEMONIC("movs Xv,Yv");
|
---|
11509 |
|
---|
11510 | /*
|
---|
11511 | * Annoying double switch here.
|
---|
11512 | * Using ugly macro for implementing the cases, sharing it with movsb.
|
---|
11513 | */
|
---|
11514 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11515 | {
|
---|
11516 | case IEMMODE_16BIT:
|
---|
11517 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11518 | {
|
---|
11519 | case IEMMODE_16BIT: IEM_MOVS_CASE(16, 16); break;
|
---|
11520 | case IEMMODE_32BIT: IEM_MOVS_CASE(16, 32); break;
|
---|
11521 | case IEMMODE_64BIT: IEM_MOVS_CASE(16, 64); break;
|
---|
11522 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11523 | }
|
---|
11524 | break;
|
---|
11525 |
|
---|
11526 | case IEMMODE_32BIT:
|
---|
11527 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11528 | {
|
---|
11529 | case IEMMODE_16BIT: IEM_MOVS_CASE(32, 16); break;
|
---|
11530 | case IEMMODE_32BIT: IEM_MOVS_CASE(32, 32); break;
|
---|
11531 | case IEMMODE_64BIT: IEM_MOVS_CASE(32, 64); break;
|
---|
11532 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11533 | }
|
---|
11534 | break;
|
---|
11535 |
|
---|
11536 | case IEMMODE_64BIT:
|
---|
11537 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11538 | {
|
---|
11539 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_1); /* cannot be encoded */ break;
|
---|
11540 | case IEMMODE_32BIT: IEM_MOVS_CASE(64, 32); break;
|
---|
11541 | case IEMMODE_64BIT: IEM_MOVS_CASE(64, 64); break;
|
---|
11542 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11543 | }
|
---|
11544 | break;
|
---|
11545 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11546 | }
|
---|
11547 | return VINF_SUCCESS;
|
---|
11548 | }
|
---|
11549 |
|
---|
11550 | #undef IEM_MOVS_CASE
|
---|
11551 |
|
---|
11552 | /** Macro used by iemOp_cmpsb_Xb_Yb and iemOp_cmpswd_Xv_Yv */
|
---|
11553 | #define IEM_CMPS_CASE(ValBits, AddrBits) \
|
---|
11554 | IEM_MC_BEGIN(3, 3); \
|
---|
11555 | IEM_MC_ARG(uint##ValBits##_t *, puValue1, 0); \
|
---|
11556 | IEM_MC_ARG(uint##ValBits##_t, uValue2, 1); \
|
---|
11557 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
|
---|
11558 | IEM_MC_LOCAL(uint##ValBits##_t, uValue1); \
|
---|
11559 | IEM_MC_LOCAL(RTGCPTR, uAddr); \
|
---|
11560 | \
|
---|
11561 | IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xSI); \
|
---|
11562 | IEM_MC_FETCH_MEM_U##ValBits(uValue1, pVCpu->iem.s.iEffSeg, uAddr); \
|
---|
11563 | IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xDI); \
|
---|
11564 | IEM_MC_FETCH_MEM_U##ValBits(uValue2, X86_SREG_ES, uAddr); \
|
---|
11565 | IEM_MC_REF_LOCAL(puValue1, uValue1); \
|
---|
11566 | IEM_MC_REF_EFLAGS(pEFlags); \
|
---|
11567 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_cmp_u##ValBits, puValue1, uValue2, pEFlags); \
|
---|
11568 | \
|
---|
11569 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_DF) { \
|
---|
11570 | IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
|
---|
11571 | IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \
|
---|
11572 | } IEM_MC_ELSE() { \
|
---|
11573 | IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
|
---|
11574 | IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \
|
---|
11575 | } IEM_MC_ENDIF(); \
|
---|
11576 | IEM_MC_ADVANCE_RIP(); \
|
---|
11577 | IEM_MC_END(); \
|
---|
11578 |
|
---|
11579 | /** Opcode 0xa6. */
|
---|
11580 | FNIEMOP_DEF(iemOp_cmpsb_Xb_Yb)
|
---|
11581 | {
|
---|
11582 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11583 |
|
---|
11584 | /*
|
---|
11585 | * Use the C implementation if a repeat prefix is encountered.
|
---|
11586 | */
|
---|
11587 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REPZ)
|
---|
11588 | {
|
---|
11589 | IEMOP_MNEMONIC("repe cmps Xb,Yb");
|
---|
11590 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11591 | {
|
---|
11592 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op8_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11593 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op8_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11594 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op8_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11595 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11596 | }
|
---|
11597 | }
|
---|
11598 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REPNZ)
|
---|
11599 | {
|
---|
11600 | IEMOP_MNEMONIC("repe cmps Xb,Yb");
|
---|
11601 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11602 | {
|
---|
11603 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op8_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11604 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op8_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11605 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op8_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11606 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11607 | }
|
---|
11608 | }
|
---|
11609 | IEMOP_MNEMONIC("cmps Xb,Yb");
|
---|
11610 |
|
---|
11611 | /*
|
---|
11612 | * Sharing case implementation with cmps[wdq] below.
|
---|
11613 | */
|
---|
11614 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11615 | {
|
---|
11616 | case IEMMODE_16BIT: IEM_CMPS_CASE(8, 16); break;
|
---|
11617 | case IEMMODE_32BIT: IEM_CMPS_CASE(8, 32); break;
|
---|
11618 | case IEMMODE_64BIT: IEM_CMPS_CASE(8, 64); break;
|
---|
11619 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11620 | }
|
---|
11621 | return VINF_SUCCESS;
|
---|
11622 |
|
---|
11623 | }
|
---|
11624 |
|
---|
11625 |
|
---|
11626 | /** Opcode 0xa7. */
|
---|
11627 | FNIEMOP_DEF(iemOp_cmpswd_Xv_Yv)
|
---|
11628 | {
|
---|
11629 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11630 |
|
---|
11631 | /*
|
---|
11632 | * Use the C implementation if a repeat prefix is encountered.
|
---|
11633 | */
|
---|
11634 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REPZ)
|
---|
11635 | {
|
---|
11636 | IEMOP_MNEMONIC("repe cmps Xv,Yv");
|
---|
11637 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11638 | {
|
---|
11639 | case IEMMODE_16BIT:
|
---|
11640 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11641 | {
|
---|
11642 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op16_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11643 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op16_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11644 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op16_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11645 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11646 | }
|
---|
11647 | break;
|
---|
11648 | case IEMMODE_32BIT:
|
---|
11649 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11650 | {
|
---|
11651 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op32_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11652 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op32_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11653 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op32_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11654 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11655 | }
|
---|
11656 | case IEMMODE_64BIT:
|
---|
11657 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11658 | {
|
---|
11659 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_4);
|
---|
11660 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op64_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11661 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repe_cmps_op64_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11662 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11663 | }
|
---|
11664 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11665 | }
|
---|
11666 | }
|
---|
11667 |
|
---|
11668 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REPNZ)
|
---|
11669 | {
|
---|
11670 | IEMOP_MNEMONIC("repne cmps Xv,Yv");
|
---|
11671 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11672 | {
|
---|
11673 | case IEMMODE_16BIT:
|
---|
11674 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11675 | {
|
---|
11676 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op16_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11677 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op16_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11678 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op16_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11679 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11680 | }
|
---|
11681 | break;
|
---|
11682 | case IEMMODE_32BIT:
|
---|
11683 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11684 | {
|
---|
11685 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op32_addr16, pVCpu->iem.s.iEffSeg);
|
---|
11686 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op32_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11687 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op32_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11688 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11689 | }
|
---|
11690 | case IEMMODE_64BIT:
|
---|
11691 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11692 | {
|
---|
11693 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_2);
|
---|
11694 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op64_addr32, pVCpu->iem.s.iEffSeg);
|
---|
11695 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_repne_cmps_op64_addr64, pVCpu->iem.s.iEffSeg);
|
---|
11696 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11697 | }
|
---|
11698 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11699 | }
|
---|
11700 | }
|
---|
11701 |
|
---|
11702 | IEMOP_MNEMONIC("cmps Xv,Yv");
|
---|
11703 |
|
---|
11704 | /*
|
---|
11705 | * Annoying double switch here.
|
---|
11706 | * Using ugly macro for implementing the cases, sharing it with cmpsb.
|
---|
11707 | */
|
---|
11708 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11709 | {
|
---|
11710 | case IEMMODE_16BIT:
|
---|
11711 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11712 | {
|
---|
11713 | case IEMMODE_16BIT: IEM_CMPS_CASE(16, 16); break;
|
---|
11714 | case IEMMODE_32BIT: IEM_CMPS_CASE(16, 32); break;
|
---|
11715 | case IEMMODE_64BIT: IEM_CMPS_CASE(16, 64); break;
|
---|
11716 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11717 | }
|
---|
11718 | break;
|
---|
11719 |
|
---|
11720 | case IEMMODE_32BIT:
|
---|
11721 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11722 | {
|
---|
11723 | case IEMMODE_16BIT: IEM_CMPS_CASE(32, 16); break;
|
---|
11724 | case IEMMODE_32BIT: IEM_CMPS_CASE(32, 32); break;
|
---|
11725 | case IEMMODE_64BIT: IEM_CMPS_CASE(32, 64); break;
|
---|
11726 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11727 | }
|
---|
11728 | break;
|
---|
11729 |
|
---|
11730 | case IEMMODE_64BIT:
|
---|
11731 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11732 | {
|
---|
11733 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_1); /* cannot be encoded */ break;
|
---|
11734 | case IEMMODE_32BIT: IEM_CMPS_CASE(64, 32); break;
|
---|
11735 | case IEMMODE_64BIT: IEM_CMPS_CASE(64, 64); break;
|
---|
11736 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11737 | }
|
---|
11738 | break;
|
---|
11739 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11740 | }
|
---|
11741 | return VINF_SUCCESS;
|
---|
11742 |
|
---|
11743 | }
|
---|
11744 |
|
---|
11745 | #undef IEM_CMPS_CASE
|
---|
11746 |
|
---|
11747 | /** Opcode 0xa8. */
|
---|
11748 | FNIEMOP_DEF(iemOp_test_AL_Ib)
|
---|
11749 | {
|
---|
11750 | IEMOP_MNEMONIC("test al,Ib");
|
---|
11751 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
11752 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_test);
|
---|
11753 | }
|
---|
11754 |
|
---|
11755 |
|
---|
11756 | /** Opcode 0xa9. */
|
---|
11757 | FNIEMOP_DEF(iemOp_test_eAX_Iz)
|
---|
11758 | {
|
---|
11759 | IEMOP_MNEMONIC("test rAX,Iz");
|
---|
11760 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
11761 | return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_test);
|
---|
11762 | }
|
---|
11763 |
|
---|
11764 |
|
---|
11765 | /** Macro used by iemOp_stosb_Yb_AL and iemOp_stoswd_Yv_eAX */
|
---|
11766 | #define IEM_STOS_CASE(ValBits, AddrBits) \
|
---|
11767 | IEM_MC_BEGIN(0, 2); \
|
---|
11768 | IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
|
---|
11769 | IEM_MC_LOCAL(RTGCPTR, uAddr); \
|
---|
11770 | IEM_MC_FETCH_GREG_U##ValBits(uValue, X86_GREG_xAX); \
|
---|
11771 | IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xDI); \
|
---|
11772 | IEM_MC_STORE_MEM_U##ValBits(X86_SREG_ES, uAddr, uValue); \
|
---|
11773 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_DF) { \
|
---|
11774 | IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
|
---|
11775 | } IEM_MC_ELSE() { \
|
---|
11776 | IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
|
---|
11777 | } IEM_MC_ENDIF(); \
|
---|
11778 | IEM_MC_ADVANCE_RIP(); \
|
---|
11779 | IEM_MC_END(); \
|
---|
11780 |
|
---|
11781 | /** Opcode 0xaa. */
|
---|
11782 | FNIEMOP_DEF(iemOp_stosb_Yb_AL)
|
---|
11783 | {
|
---|
11784 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11785 |
|
---|
11786 | /*
|
---|
11787 | * Use the C implementation if a repeat prefix is encountered.
|
---|
11788 | */
|
---|
11789 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
11790 | {
|
---|
11791 | IEMOP_MNEMONIC("rep stos Yb,al");
|
---|
11792 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11793 | {
|
---|
11794 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_al_m16);
|
---|
11795 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_al_m32);
|
---|
11796 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_al_m64);
|
---|
11797 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11798 | }
|
---|
11799 | }
|
---|
11800 | IEMOP_MNEMONIC("stos Yb,al");
|
---|
11801 |
|
---|
11802 | /*
|
---|
11803 | * Sharing case implementation with stos[wdq] below.
|
---|
11804 | */
|
---|
11805 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11806 | {
|
---|
11807 | case IEMMODE_16BIT: IEM_STOS_CASE(8, 16); break;
|
---|
11808 | case IEMMODE_32BIT: IEM_STOS_CASE(8, 32); break;
|
---|
11809 | case IEMMODE_64BIT: IEM_STOS_CASE(8, 64); break;
|
---|
11810 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11811 | }
|
---|
11812 | return VINF_SUCCESS;
|
---|
11813 | }
|
---|
11814 |
|
---|
11815 |
|
---|
11816 | /** Opcode 0xab. */
|
---|
11817 | FNIEMOP_DEF(iemOp_stoswd_Yv_eAX)
|
---|
11818 | {
|
---|
11819 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11820 |
|
---|
11821 | /*
|
---|
11822 | * Use the C implementation if a repeat prefix is encountered.
|
---|
11823 | */
|
---|
11824 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
11825 | {
|
---|
11826 | IEMOP_MNEMONIC("rep stos Yv,rAX");
|
---|
11827 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11828 | {
|
---|
11829 | case IEMMODE_16BIT:
|
---|
11830 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11831 | {
|
---|
11832 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_ax_m16);
|
---|
11833 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_ax_m32);
|
---|
11834 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_ax_m64);
|
---|
11835 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11836 | }
|
---|
11837 | break;
|
---|
11838 | case IEMMODE_32BIT:
|
---|
11839 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11840 | {
|
---|
11841 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_eax_m16);
|
---|
11842 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_eax_m32);
|
---|
11843 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_eax_m64);
|
---|
11844 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11845 | }
|
---|
11846 | case IEMMODE_64BIT:
|
---|
11847 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11848 | {
|
---|
11849 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_9);
|
---|
11850 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_rax_m32);
|
---|
11851 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stos_rax_m64);
|
---|
11852 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11853 | }
|
---|
11854 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11855 | }
|
---|
11856 | }
|
---|
11857 | IEMOP_MNEMONIC("stos Yv,rAX");
|
---|
11858 |
|
---|
11859 | /*
|
---|
11860 | * Annoying double switch here.
|
---|
11861 | * Using ugly macro for implementing the cases, sharing it with stosb.
|
---|
11862 | */
|
---|
11863 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11864 | {
|
---|
11865 | case IEMMODE_16BIT:
|
---|
11866 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11867 | {
|
---|
11868 | case IEMMODE_16BIT: IEM_STOS_CASE(16, 16); break;
|
---|
11869 | case IEMMODE_32BIT: IEM_STOS_CASE(16, 32); break;
|
---|
11870 | case IEMMODE_64BIT: IEM_STOS_CASE(16, 64); break;
|
---|
11871 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11872 | }
|
---|
11873 | break;
|
---|
11874 |
|
---|
11875 | case IEMMODE_32BIT:
|
---|
11876 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11877 | {
|
---|
11878 | case IEMMODE_16BIT: IEM_STOS_CASE(32, 16); break;
|
---|
11879 | case IEMMODE_32BIT: IEM_STOS_CASE(32, 32); break;
|
---|
11880 | case IEMMODE_64BIT: IEM_STOS_CASE(32, 64); break;
|
---|
11881 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11882 | }
|
---|
11883 | break;
|
---|
11884 |
|
---|
11885 | case IEMMODE_64BIT:
|
---|
11886 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11887 | {
|
---|
11888 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_1); /* cannot be encoded */ break;
|
---|
11889 | case IEMMODE_32BIT: IEM_STOS_CASE(64, 32); break;
|
---|
11890 | case IEMMODE_64BIT: IEM_STOS_CASE(64, 64); break;
|
---|
11891 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11892 | }
|
---|
11893 | break;
|
---|
11894 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11895 | }
|
---|
11896 | return VINF_SUCCESS;
|
---|
11897 | }
|
---|
11898 |
|
---|
11899 | #undef IEM_STOS_CASE
|
---|
11900 |
|
---|
11901 | /** Macro used by iemOp_lodsb_AL_Xb and iemOp_lodswd_eAX_Xv */
|
---|
11902 | #define IEM_LODS_CASE(ValBits, AddrBits) \
|
---|
11903 | IEM_MC_BEGIN(0, 2); \
|
---|
11904 | IEM_MC_LOCAL(uint##ValBits##_t, uValue); \
|
---|
11905 | IEM_MC_LOCAL(RTGCPTR, uAddr); \
|
---|
11906 | IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xSI); \
|
---|
11907 | IEM_MC_FETCH_MEM_U##ValBits(uValue, pVCpu->iem.s.iEffSeg, uAddr); \
|
---|
11908 | IEM_MC_STORE_GREG_U##ValBits(X86_GREG_xAX, uValue); \
|
---|
11909 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_DF) { \
|
---|
11910 | IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \
|
---|
11911 | } IEM_MC_ELSE() { \
|
---|
11912 | IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \
|
---|
11913 | } IEM_MC_ENDIF(); \
|
---|
11914 | IEM_MC_ADVANCE_RIP(); \
|
---|
11915 | IEM_MC_END();
|
---|
11916 |
|
---|
11917 | /** Opcode 0xac. */
|
---|
11918 | FNIEMOP_DEF(iemOp_lodsb_AL_Xb)
|
---|
11919 | {
|
---|
11920 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11921 |
|
---|
11922 | /*
|
---|
11923 | * Use the C implementation if a repeat prefix is encountered.
|
---|
11924 | */
|
---|
11925 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
11926 | {
|
---|
11927 | IEMOP_MNEMONIC("rep lodsb al,Xb");
|
---|
11928 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11929 | {
|
---|
11930 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_al_m16, pVCpu->iem.s.iEffSeg);
|
---|
11931 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_al_m32, pVCpu->iem.s.iEffSeg);
|
---|
11932 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_al_m64, pVCpu->iem.s.iEffSeg);
|
---|
11933 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11934 | }
|
---|
11935 | }
|
---|
11936 | IEMOP_MNEMONIC("lodsb al,Xb");
|
---|
11937 |
|
---|
11938 | /*
|
---|
11939 | * Sharing case implementation with stos[wdq] below.
|
---|
11940 | */
|
---|
11941 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11942 | {
|
---|
11943 | case IEMMODE_16BIT: IEM_LODS_CASE(8, 16); break;
|
---|
11944 | case IEMMODE_32BIT: IEM_LODS_CASE(8, 32); break;
|
---|
11945 | case IEMMODE_64BIT: IEM_LODS_CASE(8, 64); break;
|
---|
11946 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11947 | }
|
---|
11948 | return VINF_SUCCESS;
|
---|
11949 | }
|
---|
11950 |
|
---|
11951 |
|
---|
11952 | /** Opcode 0xad. */
|
---|
11953 | FNIEMOP_DEF(iemOp_lodswd_eAX_Xv)
|
---|
11954 | {
|
---|
11955 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
11956 |
|
---|
11957 | /*
|
---|
11958 | * Use the C implementation if a repeat prefix is encountered.
|
---|
11959 | */
|
---|
11960 | if (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ))
|
---|
11961 | {
|
---|
11962 | IEMOP_MNEMONIC("rep lods rAX,Xv");
|
---|
11963 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
11964 | {
|
---|
11965 | case IEMMODE_16BIT:
|
---|
11966 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11967 | {
|
---|
11968 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_ax_m16, pVCpu->iem.s.iEffSeg);
|
---|
11969 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_ax_m32, pVCpu->iem.s.iEffSeg);
|
---|
11970 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_ax_m64, pVCpu->iem.s.iEffSeg);
|
---|
11971 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11972 | }
|
---|
11973 | break;
|
---|
11974 | case IEMMODE_32BIT:
|
---|
11975 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11976 | {
|
---|
11977 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_eax_m16, pVCpu->iem.s.iEffSeg);
|
---|
11978 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_eax_m32, pVCpu->iem.s.iEffSeg);
|
---|
11979 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_eax_m64, pVCpu->iem.s.iEffSeg);
|
---|
11980 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11981 | }
|
---|
11982 | case IEMMODE_64BIT:
|
---|
11983 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
11984 | {
|
---|
11985 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_7);
|
---|
11986 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_rax_m32, pVCpu->iem.s.iEffSeg);
|
---|
11987 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_lods_rax_m64, pVCpu->iem.s.iEffSeg);
|
---|
11988 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11989 | }
|
---|
11990 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
11991 | }
|
---|
11992 | }
|
---|
11993 | IEMOP_MNEMONIC("lods rAX,Xv");
|
---|
11994 |
|
---|
11995 | /*
|
---|
11996 | * Annoying double switch here.
|
---|
11997 | * Using ugly macro for implementing the cases, sharing it with lodsb.
|
---|
11998 | */
|
---|
11999 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12000 | {
|
---|
12001 | case IEMMODE_16BIT:
|
---|
12002 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12003 | {
|
---|
12004 | case IEMMODE_16BIT: IEM_LODS_CASE(16, 16); break;
|
---|
12005 | case IEMMODE_32BIT: IEM_LODS_CASE(16, 32); break;
|
---|
12006 | case IEMMODE_64BIT: IEM_LODS_CASE(16, 64); break;
|
---|
12007 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12008 | }
|
---|
12009 | break;
|
---|
12010 |
|
---|
12011 | case IEMMODE_32BIT:
|
---|
12012 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12013 | {
|
---|
12014 | case IEMMODE_16BIT: IEM_LODS_CASE(32, 16); break;
|
---|
12015 | case IEMMODE_32BIT: IEM_LODS_CASE(32, 32); break;
|
---|
12016 | case IEMMODE_64BIT: IEM_LODS_CASE(32, 64); break;
|
---|
12017 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12018 | }
|
---|
12019 | break;
|
---|
12020 |
|
---|
12021 | case IEMMODE_64BIT:
|
---|
12022 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12023 | {
|
---|
12024 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_1); /* cannot be encoded */ break;
|
---|
12025 | case IEMMODE_32BIT: IEM_LODS_CASE(64, 32); break;
|
---|
12026 | case IEMMODE_64BIT: IEM_LODS_CASE(64, 64); break;
|
---|
12027 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12028 | }
|
---|
12029 | break;
|
---|
12030 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12031 | }
|
---|
12032 | return VINF_SUCCESS;
|
---|
12033 | }
|
---|
12034 |
|
---|
12035 | #undef IEM_LODS_CASE
|
---|
12036 |
|
---|
12037 | /** Macro used by iemOp_scasb_AL_Xb and iemOp_scaswd_eAX_Xv */
|
---|
12038 | #define IEM_SCAS_CASE(ValBits, AddrBits) \
|
---|
12039 | IEM_MC_BEGIN(3, 2); \
|
---|
12040 | IEM_MC_ARG(uint##ValBits##_t *, puRax, 0); \
|
---|
12041 | IEM_MC_ARG(uint##ValBits##_t, uValue, 1); \
|
---|
12042 | IEM_MC_ARG(uint32_t *, pEFlags, 2); \
|
---|
12043 | IEM_MC_LOCAL(RTGCPTR, uAddr); \
|
---|
12044 | \
|
---|
12045 | IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xDI); \
|
---|
12046 | IEM_MC_FETCH_MEM_U##ValBits(uValue, X86_SREG_ES, uAddr); \
|
---|
12047 | IEM_MC_REF_GREG_U##ValBits(puRax, X86_GREG_xAX); \
|
---|
12048 | IEM_MC_REF_EFLAGS(pEFlags); \
|
---|
12049 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_cmp_u##ValBits, puRax, uValue, pEFlags); \
|
---|
12050 | \
|
---|
12051 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_DF) { \
|
---|
12052 | IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
|
---|
12053 | } IEM_MC_ELSE() { \
|
---|
12054 | IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
|
---|
12055 | } IEM_MC_ENDIF(); \
|
---|
12056 | IEM_MC_ADVANCE_RIP(); \
|
---|
12057 | IEM_MC_END();
|
---|
12058 |
|
---|
12059 | /** Opcode 0xae. */
|
---|
12060 | FNIEMOP_DEF(iemOp_scasb_AL_Xb)
|
---|
12061 | {
|
---|
12062 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12063 |
|
---|
12064 | /*
|
---|
12065 | * Use the C implementation if a repeat prefix is encountered.
|
---|
12066 | */
|
---|
12067 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REPZ)
|
---|
12068 | {
|
---|
12069 | IEMOP_MNEMONIC("repe scasb al,Xb");
|
---|
12070 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12071 | {
|
---|
12072 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_al_m16);
|
---|
12073 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_al_m32);
|
---|
12074 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_al_m64);
|
---|
12075 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12076 | }
|
---|
12077 | }
|
---|
12078 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REPNZ)
|
---|
12079 | {
|
---|
12080 | IEMOP_MNEMONIC("repne scasb al,Xb");
|
---|
12081 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12082 | {
|
---|
12083 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_al_m16);
|
---|
12084 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_al_m32);
|
---|
12085 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_al_m64);
|
---|
12086 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12087 | }
|
---|
12088 | }
|
---|
12089 | IEMOP_MNEMONIC("scasb al,Xb");
|
---|
12090 |
|
---|
12091 | /*
|
---|
12092 | * Sharing case implementation with stos[wdq] below.
|
---|
12093 | */
|
---|
12094 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12095 | {
|
---|
12096 | case IEMMODE_16BIT: IEM_SCAS_CASE(8, 16); break;
|
---|
12097 | case IEMMODE_32BIT: IEM_SCAS_CASE(8, 32); break;
|
---|
12098 | case IEMMODE_64BIT: IEM_SCAS_CASE(8, 64); break;
|
---|
12099 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12100 | }
|
---|
12101 | return VINF_SUCCESS;
|
---|
12102 | }
|
---|
12103 |
|
---|
12104 |
|
---|
12105 | /** Opcode 0xaf. */
|
---|
12106 | FNIEMOP_DEF(iemOp_scaswd_eAX_Xv)
|
---|
12107 | {
|
---|
12108 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12109 |
|
---|
12110 | /*
|
---|
12111 | * Use the C implementation if a repeat prefix is encountered.
|
---|
12112 | */
|
---|
12113 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REPZ)
|
---|
12114 | {
|
---|
12115 | IEMOP_MNEMONIC("repe scas rAX,Xv");
|
---|
12116 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12117 | {
|
---|
12118 | case IEMMODE_16BIT:
|
---|
12119 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12120 | {
|
---|
12121 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_ax_m16);
|
---|
12122 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_ax_m32);
|
---|
12123 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_ax_m64);
|
---|
12124 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12125 | }
|
---|
12126 | break;
|
---|
12127 | case IEMMODE_32BIT:
|
---|
12128 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12129 | {
|
---|
12130 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_eax_m16);
|
---|
12131 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_eax_m32);
|
---|
12132 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_eax_m64);
|
---|
12133 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12134 | }
|
---|
12135 | case IEMMODE_64BIT:
|
---|
12136 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12137 | {
|
---|
12138 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_6); /** @todo It's this wrong, we can do 16-bit addressing in 64-bit mode, but not 32-bit. right? */
|
---|
12139 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_rax_m32);
|
---|
12140 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repe_scas_rax_m64);
|
---|
12141 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12142 | }
|
---|
12143 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12144 | }
|
---|
12145 | }
|
---|
12146 | if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REPNZ)
|
---|
12147 | {
|
---|
12148 | IEMOP_MNEMONIC("repne scas rAX,Xv");
|
---|
12149 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12150 | {
|
---|
12151 | case IEMMODE_16BIT:
|
---|
12152 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12153 | {
|
---|
12154 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_ax_m16);
|
---|
12155 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_ax_m32);
|
---|
12156 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_ax_m64);
|
---|
12157 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12158 | }
|
---|
12159 | break;
|
---|
12160 | case IEMMODE_32BIT:
|
---|
12161 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12162 | {
|
---|
12163 | case IEMMODE_16BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_eax_m16);
|
---|
12164 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_eax_m32);
|
---|
12165 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_eax_m64);
|
---|
12166 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12167 | }
|
---|
12168 | case IEMMODE_64BIT:
|
---|
12169 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12170 | {
|
---|
12171 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_5);
|
---|
12172 | case IEMMODE_32BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_rax_m32);
|
---|
12173 | case IEMMODE_64BIT: return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_repne_scas_rax_m64);
|
---|
12174 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12175 | }
|
---|
12176 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12177 | }
|
---|
12178 | }
|
---|
12179 | IEMOP_MNEMONIC("scas rAX,Xv");
|
---|
12180 |
|
---|
12181 | /*
|
---|
12182 | * Annoying double switch here.
|
---|
12183 | * Using ugly macro for implementing the cases, sharing it with scasb.
|
---|
12184 | */
|
---|
12185 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12186 | {
|
---|
12187 | case IEMMODE_16BIT:
|
---|
12188 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12189 | {
|
---|
12190 | case IEMMODE_16BIT: IEM_SCAS_CASE(16, 16); break;
|
---|
12191 | case IEMMODE_32BIT: IEM_SCAS_CASE(16, 32); break;
|
---|
12192 | case IEMMODE_64BIT: IEM_SCAS_CASE(16, 64); break;
|
---|
12193 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12194 | }
|
---|
12195 | break;
|
---|
12196 |
|
---|
12197 | case IEMMODE_32BIT:
|
---|
12198 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12199 | {
|
---|
12200 | case IEMMODE_16BIT: IEM_SCAS_CASE(32, 16); break;
|
---|
12201 | case IEMMODE_32BIT: IEM_SCAS_CASE(32, 32); break;
|
---|
12202 | case IEMMODE_64BIT: IEM_SCAS_CASE(32, 64); break;
|
---|
12203 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12204 | }
|
---|
12205 | break;
|
---|
12206 |
|
---|
12207 | case IEMMODE_64BIT:
|
---|
12208 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
12209 | {
|
---|
12210 | case IEMMODE_16BIT: AssertFailedReturn(VERR_IEM_IPE_1); /* cannot be encoded */ break;
|
---|
12211 | case IEMMODE_32BIT: IEM_SCAS_CASE(64, 32); break;
|
---|
12212 | case IEMMODE_64BIT: IEM_SCAS_CASE(64, 64); break;
|
---|
12213 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12214 | }
|
---|
12215 | break;
|
---|
12216 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12217 | }
|
---|
12218 | return VINF_SUCCESS;
|
---|
12219 | }
|
---|
12220 |
|
---|
12221 | #undef IEM_SCAS_CASE
|
---|
12222 |
|
---|
12223 | /**
|
---|
12224 | * Common 'mov r8, imm8' helper.
|
---|
12225 | */
|
---|
12226 | FNIEMOP_DEF_1(iemOpCommonMov_r8_Ib, uint8_t, iReg)
|
---|
12227 | {
|
---|
12228 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
12229 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12230 |
|
---|
12231 | IEM_MC_BEGIN(0, 1);
|
---|
12232 | IEM_MC_LOCAL_CONST(uint8_t, u8Value,/*=*/ u8Imm);
|
---|
12233 | IEM_MC_STORE_GREG_U8(iReg, u8Value);
|
---|
12234 | IEM_MC_ADVANCE_RIP();
|
---|
12235 | IEM_MC_END();
|
---|
12236 |
|
---|
12237 | return VINF_SUCCESS;
|
---|
12238 | }
|
---|
12239 |
|
---|
12240 |
|
---|
12241 | /** Opcode 0xb0. */
|
---|
12242 | FNIEMOP_DEF(iemOp_mov_AL_Ib)
|
---|
12243 | {
|
---|
12244 | IEMOP_MNEMONIC("mov AL,Ib");
|
---|
12245 | return FNIEMOP_CALL_1(iemOpCommonMov_r8_Ib, X86_GREG_xAX | pVCpu->iem.s.uRexB);
|
---|
12246 | }
|
---|
12247 |
|
---|
12248 |
|
---|
12249 | /** Opcode 0xb1. */
|
---|
12250 | FNIEMOP_DEF(iemOp_CL_Ib)
|
---|
12251 | {
|
---|
12252 | IEMOP_MNEMONIC("mov CL,Ib");
|
---|
12253 | return FNIEMOP_CALL_1(iemOpCommonMov_r8_Ib, X86_GREG_xCX | pVCpu->iem.s.uRexB);
|
---|
12254 | }
|
---|
12255 |
|
---|
12256 |
|
---|
12257 | /** Opcode 0xb2. */
|
---|
12258 | FNIEMOP_DEF(iemOp_DL_Ib)
|
---|
12259 | {
|
---|
12260 | IEMOP_MNEMONIC("mov DL,Ib");
|
---|
12261 | return FNIEMOP_CALL_1(iemOpCommonMov_r8_Ib, X86_GREG_xDX | pVCpu->iem.s.uRexB);
|
---|
12262 | }
|
---|
12263 |
|
---|
12264 |
|
---|
12265 | /** Opcode 0xb3. */
|
---|
12266 | FNIEMOP_DEF(iemOp_BL_Ib)
|
---|
12267 | {
|
---|
12268 | IEMOP_MNEMONIC("mov BL,Ib");
|
---|
12269 | return FNIEMOP_CALL_1(iemOpCommonMov_r8_Ib, X86_GREG_xBX | pVCpu->iem.s.uRexB);
|
---|
12270 | }
|
---|
12271 |
|
---|
12272 |
|
---|
12273 | /** Opcode 0xb4. */
|
---|
12274 | FNIEMOP_DEF(iemOp_mov_AH_Ib)
|
---|
12275 | {
|
---|
12276 | IEMOP_MNEMONIC("mov AH,Ib");
|
---|
12277 | return FNIEMOP_CALL_1(iemOpCommonMov_r8_Ib, X86_GREG_xSP | pVCpu->iem.s.uRexB);
|
---|
12278 | }
|
---|
12279 |
|
---|
12280 |
|
---|
12281 | /** Opcode 0xb5. */
|
---|
12282 | FNIEMOP_DEF(iemOp_CH_Ib)
|
---|
12283 | {
|
---|
12284 | IEMOP_MNEMONIC("mov CH,Ib");
|
---|
12285 | return FNIEMOP_CALL_1(iemOpCommonMov_r8_Ib, X86_GREG_xBP | pVCpu->iem.s.uRexB);
|
---|
12286 | }
|
---|
12287 |
|
---|
12288 |
|
---|
12289 | /** Opcode 0xb6. */
|
---|
12290 | FNIEMOP_DEF(iemOp_DH_Ib)
|
---|
12291 | {
|
---|
12292 | IEMOP_MNEMONIC("mov DH,Ib");
|
---|
12293 | return FNIEMOP_CALL_1(iemOpCommonMov_r8_Ib, X86_GREG_xSI | pVCpu->iem.s.uRexB);
|
---|
12294 | }
|
---|
12295 |
|
---|
12296 |
|
---|
12297 | /** Opcode 0xb7. */
|
---|
12298 | FNIEMOP_DEF(iemOp_BH_Ib)
|
---|
12299 | {
|
---|
12300 | IEMOP_MNEMONIC("mov BH,Ib");
|
---|
12301 | return FNIEMOP_CALL_1(iemOpCommonMov_r8_Ib, X86_GREG_xDI | pVCpu->iem.s.uRexB);
|
---|
12302 | }
|
---|
12303 |
|
---|
12304 |
|
---|
12305 | /**
|
---|
12306 | * Common 'mov regX,immX' helper.
|
---|
12307 | */
|
---|
12308 | FNIEMOP_DEF_1(iemOpCommonMov_Rv_Iv, uint8_t, iReg)
|
---|
12309 | {
|
---|
12310 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12311 | {
|
---|
12312 | case IEMMODE_16BIT:
|
---|
12313 | {
|
---|
12314 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
12315 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12316 |
|
---|
12317 | IEM_MC_BEGIN(0, 1);
|
---|
12318 | IEM_MC_LOCAL_CONST(uint16_t, u16Value,/*=*/ u16Imm);
|
---|
12319 | IEM_MC_STORE_GREG_U16(iReg, u16Value);
|
---|
12320 | IEM_MC_ADVANCE_RIP();
|
---|
12321 | IEM_MC_END();
|
---|
12322 | break;
|
---|
12323 | }
|
---|
12324 |
|
---|
12325 | case IEMMODE_32BIT:
|
---|
12326 | {
|
---|
12327 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
12328 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12329 |
|
---|
12330 | IEM_MC_BEGIN(0, 1);
|
---|
12331 | IEM_MC_LOCAL_CONST(uint32_t, u32Value,/*=*/ u32Imm);
|
---|
12332 | IEM_MC_STORE_GREG_U32(iReg, u32Value);
|
---|
12333 | IEM_MC_ADVANCE_RIP();
|
---|
12334 | IEM_MC_END();
|
---|
12335 | break;
|
---|
12336 | }
|
---|
12337 | case IEMMODE_64BIT:
|
---|
12338 | {
|
---|
12339 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_U64(&u64Imm); /* 64-bit immediate! */
|
---|
12340 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12341 |
|
---|
12342 | IEM_MC_BEGIN(0, 1);
|
---|
12343 | IEM_MC_LOCAL_CONST(uint64_t, u64Value,/*=*/ u64Imm);
|
---|
12344 | IEM_MC_STORE_GREG_U64(iReg, u64Value);
|
---|
12345 | IEM_MC_ADVANCE_RIP();
|
---|
12346 | IEM_MC_END();
|
---|
12347 | break;
|
---|
12348 | }
|
---|
12349 | }
|
---|
12350 |
|
---|
12351 | return VINF_SUCCESS;
|
---|
12352 | }
|
---|
12353 |
|
---|
12354 |
|
---|
12355 | /** Opcode 0xb8. */
|
---|
12356 | FNIEMOP_DEF(iemOp_eAX_Iv)
|
---|
12357 | {
|
---|
12358 | IEMOP_MNEMONIC("mov rAX,IV");
|
---|
12359 | return FNIEMOP_CALL_1(iemOpCommonMov_Rv_Iv, X86_GREG_xAX | pVCpu->iem.s.uRexB);
|
---|
12360 | }
|
---|
12361 |
|
---|
12362 |
|
---|
12363 | /** Opcode 0xb9. */
|
---|
12364 | FNIEMOP_DEF(iemOp_eCX_Iv)
|
---|
12365 | {
|
---|
12366 | IEMOP_MNEMONIC("mov rCX,IV");
|
---|
12367 | return FNIEMOP_CALL_1(iemOpCommonMov_Rv_Iv, X86_GREG_xCX | pVCpu->iem.s.uRexB);
|
---|
12368 | }
|
---|
12369 |
|
---|
12370 |
|
---|
12371 | /** Opcode 0xba. */
|
---|
12372 | FNIEMOP_DEF(iemOp_eDX_Iv)
|
---|
12373 | {
|
---|
12374 | IEMOP_MNEMONIC("mov rDX,IV");
|
---|
12375 | return FNIEMOP_CALL_1(iemOpCommonMov_Rv_Iv, X86_GREG_xDX | pVCpu->iem.s.uRexB);
|
---|
12376 | }
|
---|
12377 |
|
---|
12378 |
|
---|
12379 | /** Opcode 0xbb. */
|
---|
12380 | FNIEMOP_DEF(iemOp_eBX_Iv)
|
---|
12381 | {
|
---|
12382 | IEMOP_MNEMONIC("mov rBX,IV");
|
---|
12383 | return FNIEMOP_CALL_1(iemOpCommonMov_Rv_Iv, X86_GREG_xBX | pVCpu->iem.s.uRexB);
|
---|
12384 | }
|
---|
12385 |
|
---|
12386 |
|
---|
12387 | /** Opcode 0xbc. */
|
---|
12388 | FNIEMOP_DEF(iemOp_eSP_Iv)
|
---|
12389 | {
|
---|
12390 | IEMOP_MNEMONIC("mov rSP,IV");
|
---|
12391 | return FNIEMOP_CALL_1(iemOpCommonMov_Rv_Iv, X86_GREG_xSP | pVCpu->iem.s.uRexB);
|
---|
12392 | }
|
---|
12393 |
|
---|
12394 |
|
---|
12395 | /** Opcode 0xbd. */
|
---|
12396 | FNIEMOP_DEF(iemOp_eBP_Iv)
|
---|
12397 | {
|
---|
12398 | IEMOP_MNEMONIC("mov rBP,IV");
|
---|
12399 | return FNIEMOP_CALL_1(iemOpCommonMov_Rv_Iv, X86_GREG_xBP | pVCpu->iem.s.uRexB);
|
---|
12400 | }
|
---|
12401 |
|
---|
12402 |
|
---|
12403 | /** Opcode 0xbe. */
|
---|
12404 | FNIEMOP_DEF(iemOp_eSI_Iv)
|
---|
12405 | {
|
---|
12406 | IEMOP_MNEMONIC("mov rSI,IV");
|
---|
12407 | return FNIEMOP_CALL_1(iemOpCommonMov_Rv_Iv, X86_GREG_xSI | pVCpu->iem.s.uRexB);
|
---|
12408 | }
|
---|
12409 |
|
---|
12410 |
|
---|
12411 | /** Opcode 0xbf. */
|
---|
12412 | FNIEMOP_DEF(iemOp_eDI_Iv)
|
---|
12413 | {
|
---|
12414 | IEMOP_MNEMONIC("mov rDI,IV");
|
---|
12415 | return FNIEMOP_CALL_1(iemOpCommonMov_Rv_Iv, X86_GREG_xDI | pVCpu->iem.s.uRexB);
|
---|
12416 | }
|
---|
12417 |
|
---|
12418 |
|
---|
12419 | /** Opcode 0xc0. */
|
---|
12420 | FNIEMOP_DEF(iemOp_Grp2_Eb_Ib)
|
---|
12421 | {
|
---|
12422 | IEMOP_HLP_MIN_186();
|
---|
12423 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
12424 | PCIEMOPSHIFTSIZES pImpl;
|
---|
12425 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
12426 | {
|
---|
12427 | case 0: pImpl = &g_iemAImpl_rol; IEMOP_MNEMONIC("rol Eb,Ib"); break;
|
---|
12428 | case 1: pImpl = &g_iemAImpl_ror; IEMOP_MNEMONIC("ror Eb,Ib"); break;
|
---|
12429 | case 2: pImpl = &g_iemAImpl_rcl; IEMOP_MNEMONIC("rcl Eb,Ib"); break;
|
---|
12430 | case 3: pImpl = &g_iemAImpl_rcr; IEMOP_MNEMONIC("rcr Eb,Ib"); break;
|
---|
12431 | case 4: pImpl = &g_iemAImpl_shl; IEMOP_MNEMONIC("shl Eb,Ib"); break;
|
---|
12432 | case 5: pImpl = &g_iemAImpl_shr; IEMOP_MNEMONIC("shr Eb,Ib"); break;
|
---|
12433 | case 7: pImpl = &g_iemAImpl_sar; IEMOP_MNEMONIC("sar Eb,Ib"); break;
|
---|
12434 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
12435 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe stupid */
|
---|
12436 | }
|
---|
12437 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_AF);
|
---|
12438 |
|
---|
12439 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
12440 | {
|
---|
12441 | /* register */
|
---|
12442 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
12443 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12444 | IEM_MC_BEGIN(3, 0);
|
---|
12445 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
12446 | IEM_MC_ARG_CONST(uint8_t, cShiftArg, cShift, 1);
|
---|
12447 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
12448 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
12449 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
12450 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, cShiftArg, pEFlags);
|
---|
12451 | IEM_MC_ADVANCE_RIP();
|
---|
12452 | IEM_MC_END();
|
---|
12453 | }
|
---|
12454 | else
|
---|
12455 | {
|
---|
12456 | /* memory */
|
---|
12457 | IEM_MC_BEGIN(3, 2);
|
---|
12458 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
12459 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
12460 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
12461 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12462 |
|
---|
12463 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
12464 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
12465 | IEM_MC_ASSIGN(cShiftArg, cShift);
|
---|
12466 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12467 | IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
12468 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
12469 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, cShiftArg, pEFlags);
|
---|
12470 |
|
---|
12471 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
|
---|
12472 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
12473 | IEM_MC_ADVANCE_RIP();
|
---|
12474 | IEM_MC_END();
|
---|
12475 | }
|
---|
12476 | return VINF_SUCCESS;
|
---|
12477 | }
|
---|
12478 |
|
---|
12479 |
|
---|
12480 | /** Opcode 0xc1. */
|
---|
12481 | FNIEMOP_DEF(iemOp_Grp2_Ev_Ib)
|
---|
12482 | {
|
---|
12483 | IEMOP_HLP_MIN_186();
|
---|
12484 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
12485 | PCIEMOPSHIFTSIZES pImpl;
|
---|
12486 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
12487 | {
|
---|
12488 | case 0: pImpl = &g_iemAImpl_rol; IEMOP_MNEMONIC("rol Ev,Ib"); break;
|
---|
12489 | case 1: pImpl = &g_iemAImpl_ror; IEMOP_MNEMONIC("ror Ev,Ib"); break;
|
---|
12490 | case 2: pImpl = &g_iemAImpl_rcl; IEMOP_MNEMONIC("rcl Ev,Ib"); break;
|
---|
12491 | case 3: pImpl = &g_iemAImpl_rcr; IEMOP_MNEMONIC("rcr Ev,Ib"); break;
|
---|
12492 | case 4: pImpl = &g_iemAImpl_shl; IEMOP_MNEMONIC("shl Ev,Ib"); break;
|
---|
12493 | case 5: pImpl = &g_iemAImpl_shr; IEMOP_MNEMONIC("shr Ev,Ib"); break;
|
---|
12494 | case 7: pImpl = &g_iemAImpl_sar; IEMOP_MNEMONIC("sar Ev,Ib"); break;
|
---|
12495 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
12496 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe stupid */
|
---|
12497 | }
|
---|
12498 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_AF);
|
---|
12499 |
|
---|
12500 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
12501 | {
|
---|
12502 | /* register */
|
---|
12503 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
12504 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12505 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12506 | {
|
---|
12507 | case IEMMODE_16BIT:
|
---|
12508 | IEM_MC_BEGIN(3, 0);
|
---|
12509 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
12510 | IEM_MC_ARG_CONST(uint8_t, cShiftArg, cShift, 1);
|
---|
12511 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
12512 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
12513 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
12514 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, cShiftArg, pEFlags);
|
---|
12515 | IEM_MC_ADVANCE_RIP();
|
---|
12516 | IEM_MC_END();
|
---|
12517 | return VINF_SUCCESS;
|
---|
12518 |
|
---|
12519 | case IEMMODE_32BIT:
|
---|
12520 | IEM_MC_BEGIN(3, 0);
|
---|
12521 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
12522 | IEM_MC_ARG_CONST(uint8_t, cShiftArg, cShift, 1);
|
---|
12523 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
12524 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
12525 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
12526 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, cShiftArg, pEFlags);
|
---|
12527 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
12528 | IEM_MC_ADVANCE_RIP();
|
---|
12529 | IEM_MC_END();
|
---|
12530 | return VINF_SUCCESS;
|
---|
12531 |
|
---|
12532 | case IEMMODE_64BIT:
|
---|
12533 | IEM_MC_BEGIN(3, 0);
|
---|
12534 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
12535 | IEM_MC_ARG_CONST(uint8_t, cShiftArg, cShift, 1);
|
---|
12536 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
12537 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
12538 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
12539 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, cShiftArg, pEFlags);
|
---|
12540 | IEM_MC_ADVANCE_RIP();
|
---|
12541 | IEM_MC_END();
|
---|
12542 | return VINF_SUCCESS;
|
---|
12543 |
|
---|
12544 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12545 | }
|
---|
12546 | }
|
---|
12547 | else
|
---|
12548 | {
|
---|
12549 | /* memory */
|
---|
12550 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12551 | {
|
---|
12552 | case IEMMODE_16BIT:
|
---|
12553 | IEM_MC_BEGIN(3, 2);
|
---|
12554 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
12555 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
12556 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
12557 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12558 |
|
---|
12559 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
12560 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
12561 | IEM_MC_ASSIGN(cShiftArg, cShift);
|
---|
12562 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12563 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
12564 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
12565 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, cShiftArg, pEFlags);
|
---|
12566 |
|
---|
12567 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
12568 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
12569 | IEM_MC_ADVANCE_RIP();
|
---|
12570 | IEM_MC_END();
|
---|
12571 | return VINF_SUCCESS;
|
---|
12572 |
|
---|
12573 | case IEMMODE_32BIT:
|
---|
12574 | IEM_MC_BEGIN(3, 2);
|
---|
12575 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
12576 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
12577 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
12578 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12579 |
|
---|
12580 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
12581 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
12582 | IEM_MC_ASSIGN(cShiftArg, cShift);
|
---|
12583 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12584 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
12585 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
12586 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, cShiftArg, pEFlags);
|
---|
12587 |
|
---|
12588 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
12589 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
12590 | IEM_MC_ADVANCE_RIP();
|
---|
12591 | IEM_MC_END();
|
---|
12592 | return VINF_SUCCESS;
|
---|
12593 |
|
---|
12594 | case IEMMODE_64BIT:
|
---|
12595 | IEM_MC_BEGIN(3, 2);
|
---|
12596 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
12597 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
12598 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
12599 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12600 |
|
---|
12601 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
12602 | uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
|
---|
12603 | IEM_MC_ASSIGN(cShiftArg, cShift);
|
---|
12604 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12605 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
12606 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
12607 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, cShiftArg, pEFlags);
|
---|
12608 |
|
---|
12609 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
12610 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
12611 | IEM_MC_ADVANCE_RIP();
|
---|
12612 | IEM_MC_END();
|
---|
12613 | return VINF_SUCCESS;
|
---|
12614 |
|
---|
12615 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12616 | }
|
---|
12617 | }
|
---|
12618 | }
|
---|
12619 |
|
---|
12620 |
|
---|
12621 | /** Opcode 0xc2. */
|
---|
12622 | FNIEMOP_DEF(iemOp_retn_Iw)
|
---|
12623 | {
|
---|
12624 | IEMOP_MNEMONIC("retn Iw");
|
---|
12625 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
12626 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12627 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
12628 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_retn, pVCpu->iem.s.enmEffOpSize, u16Imm);
|
---|
12629 | }
|
---|
12630 |
|
---|
12631 |
|
---|
12632 | /** Opcode 0xc3. */
|
---|
12633 | FNIEMOP_DEF(iemOp_retn)
|
---|
12634 | {
|
---|
12635 | IEMOP_MNEMONIC("retn");
|
---|
12636 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
12637 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12638 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_retn, pVCpu->iem.s.enmEffOpSize, 0);
|
---|
12639 | }
|
---|
12640 |
|
---|
12641 |
|
---|
12642 | /** Opcode 0xc4. */
|
---|
12643 | FNIEMOP_DEF(iemOp_les_Gv_Mp_vex2)
|
---|
12644 | {
|
---|
12645 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
12646 | if ( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
|
---|
12647 | || (bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
12648 | {
|
---|
12649 | IEMOP_MNEMONIC("2-byte-vex");
|
---|
12650 | /* The LES instruction is invalid 64-bit mode. In legacy and
|
---|
12651 | compatability mode it is invalid with MOD=3.
|
---|
12652 | The use as a VEX prefix is made possible by assigning the inverted
|
---|
12653 | REX.R to the top MOD bit, and the top bit in the inverted register
|
---|
12654 | specifier to the bottom MOD bit, thereby effectively limiting 32-bit
|
---|
12655 | to accessing registers 0..7 in this VEX form. */
|
---|
12656 | /** @todo VEX: Just use new tables for it. */
|
---|
12657 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
12658 | }
|
---|
12659 | IEMOP_MNEMONIC("les Gv,Mp");
|
---|
12660 | return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_ES, bRm);
|
---|
12661 | }
|
---|
12662 |
|
---|
12663 |
|
---|
12664 | /** Opcode 0xc5. */
|
---|
12665 | FNIEMOP_DEF(iemOp_lds_Gv_Mp_vex3)
|
---|
12666 | {
|
---|
12667 | /* The LDS instruction is invalid 64-bit mode. In legacy and
|
---|
12668 | compatability mode it is invalid with MOD=3.
|
---|
12669 | The use as a VEX prefix is made possible by assigning the inverted
|
---|
12670 | REX.R and REX.X to the two MOD bits, since the REX bits are ignored
|
---|
12671 | outside of 64-bit mode. VEX is not available in real or v86 mode. */
|
---|
12672 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
12673 | if (pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT)
|
---|
12674 | {
|
---|
12675 | if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
|
---|
12676 | {
|
---|
12677 | IEMOP_MNEMONIC("lds Gv,Mp");
|
---|
12678 | return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_DS, bRm);
|
---|
12679 | }
|
---|
12680 | IEMOP_HLP_NO_REAL_OR_V86_MODE();
|
---|
12681 | }
|
---|
12682 |
|
---|
12683 | IEMOP_MNEMONIC("3-byte-vex");
|
---|
12684 | /** @todo Test when exctly the VEX conformance checks kick in during
|
---|
12685 | * instruction decoding and fetching (using \#PF). */
|
---|
12686 | uint8_t bVex1; IEM_OPCODE_GET_NEXT_U8(&bVex1);
|
---|
12687 | uint8_t bVex2; IEM_OPCODE_GET_NEXT_U8(&bVex2);
|
---|
12688 | uint8_t bOpcode; IEM_OPCODE_GET_NEXT_U8(&bOpcode);
|
---|
12689 | #if 0 /* will make sense of this next week... */
|
---|
12690 | if ( !(pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX))
|
---|
12691 | &&
|
---|
12692 | )
|
---|
12693 | {
|
---|
12694 |
|
---|
12695 | }
|
---|
12696 | #endif
|
---|
12697 |
|
---|
12698 | /** @todo VEX: Just use new tables for it. */
|
---|
12699 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
12700 | }
|
---|
12701 |
|
---|
12702 |
|
---|
12703 | /** Opcode 0xc6. */
|
---|
12704 | FNIEMOP_DEF(iemOp_Grp11_Eb_Ib)
|
---|
12705 | {
|
---|
12706 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
12707 | if ((bRm & X86_MODRM_REG_MASK) != (0 << X86_MODRM_REG_SHIFT)) /* only mov Eb,Ib in this group. */
|
---|
12708 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
12709 | IEMOP_MNEMONIC("mov Eb,Ib");
|
---|
12710 |
|
---|
12711 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
12712 | {
|
---|
12713 | /* register access */
|
---|
12714 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
12715 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12716 | IEM_MC_BEGIN(0, 0);
|
---|
12717 | IEM_MC_STORE_GREG_U8((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u8Imm);
|
---|
12718 | IEM_MC_ADVANCE_RIP();
|
---|
12719 | IEM_MC_END();
|
---|
12720 | }
|
---|
12721 | else
|
---|
12722 | {
|
---|
12723 | /* memory access. */
|
---|
12724 | IEM_MC_BEGIN(0, 1);
|
---|
12725 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12726 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
12727 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
12728 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12729 | IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u8Imm);
|
---|
12730 | IEM_MC_ADVANCE_RIP();
|
---|
12731 | IEM_MC_END();
|
---|
12732 | }
|
---|
12733 | return VINF_SUCCESS;
|
---|
12734 | }
|
---|
12735 |
|
---|
12736 |
|
---|
12737 | /** Opcode 0xc7. */
|
---|
12738 | FNIEMOP_DEF(iemOp_Grp11_Ev_Iz)
|
---|
12739 | {
|
---|
12740 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
12741 | if ((bRm & X86_MODRM_REG_MASK) != (0 << X86_MODRM_REG_SHIFT)) /* only mov Eb,Ib in this group. */
|
---|
12742 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
12743 | IEMOP_MNEMONIC("mov Ev,Iz");
|
---|
12744 |
|
---|
12745 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
12746 | {
|
---|
12747 | /* register access */
|
---|
12748 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12749 | {
|
---|
12750 | case IEMMODE_16BIT:
|
---|
12751 | IEM_MC_BEGIN(0, 0);
|
---|
12752 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
12753 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12754 | IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u16Imm);
|
---|
12755 | IEM_MC_ADVANCE_RIP();
|
---|
12756 | IEM_MC_END();
|
---|
12757 | return VINF_SUCCESS;
|
---|
12758 |
|
---|
12759 | case IEMMODE_32BIT:
|
---|
12760 | IEM_MC_BEGIN(0, 0);
|
---|
12761 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
12762 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12763 | IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Imm);
|
---|
12764 | IEM_MC_ADVANCE_RIP();
|
---|
12765 | IEM_MC_END();
|
---|
12766 | return VINF_SUCCESS;
|
---|
12767 |
|
---|
12768 | case IEMMODE_64BIT:
|
---|
12769 | IEM_MC_BEGIN(0, 0);
|
---|
12770 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
12771 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12772 | IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Imm);
|
---|
12773 | IEM_MC_ADVANCE_RIP();
|
---|
12774 | IEM_MC_END();
|
---|
12775 | return VINF_SUCCESS;
|
---|
12776 |
|
---|
12777 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12778 | }
|
---|
12779 | }
|
---|
12780 | else
|
---|
12781 | {
|
---|
12782 | /* memory access. */
|
---|
12783 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12784 | {
|
---|
12785 | case IEMMODE_16BIT:
|
---|
12786 | IEM_MC_BEGIN(0, 1);
|
---|
12787 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12788 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 2);
|
---|
12789 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
12790 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12791 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Imm);
|
---|
12792 | IEM_MC_ADVANCE_RIP();
|
---|
12793 | IEM_MC_END();
|
---|
12794 | return VINF_SUCCESS;
|
---|
12795 |
|
---|
12796 | case IEMMODE_32BIT:
|
---|
12797 | IEM_MC_BEGIN(0, 1);
|
---|
12798 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12799 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
|
---|
12800 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
12801 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12802 | IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Imm);
|
---|
12803 | IEM_MC_ADVANCE_RIP();
|
---|
12804 | IEM_MC_END();
|
---|
12805 | return VINF_SUCCESS;
|
---|
12806 |
|
---|
12807 | case IEMMODE_64BIT:
|
---|
12808 | IEM_MC_BEGIN(0, 1);
|
---|
12809 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12810 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
|
---|
12811 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
12812 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12813 | IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Imm);
|
---|
12814 | IEM_MC_ADVANCE_RIP();
|
---|
12815 | IEM_MC_END();
|
---|
12816 | return VINF_SUCCESS;
|
---|
12817 |
|
---|
12818 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
12819 | }
|
---|
12820 | }
|
---|
12821 | }
|
---|
12822 |
|
---|
12823 |
|
---|
12824 |
|
---|
12825 |
|
---|
12826 | /** Opcode 0xc8. */
|
---|
12827 | FNIEMOP_DEF(iemOp_enter_Iw_Ib)
|
---|
12828 | {
|
---|
12829 | IEMOP_MNEMONIC("enter Iw,Ib");
|
---|
12830 | IEMOP_HLP_MIN_186();
|
---|
12831 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
12832 | uint16_t cbFrame; IEM_OPCODE_GET_NEXT_U16(&cbFrame);
|
---|
12833 | uint8_t u8NestingLevel; IEM_OPCODE_GET_NEXT_U8(&u8NestingLevel);
|
---|
12834 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12835 | return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_enter, pVCpu->iem.s.enmEffOpSize, cbFrame, u8NestingLevel);
|
---|
12836 | }
|
---|
12837 |
|
---|
12838 |
|
---|
12839 | /** Opcode 0xc9. */
|
---|
12840 | FNIEMOP_DEF(iemOp_leave)
|
---|
12841 | {
|
---|
12842 | IEMOP_MNEMONIC("retn");
|
---|
12843 | IEMOP_HLP_MIN_186();
|
---|
12844 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
12845 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12846 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_leave, pVCpu->iem.s.enmEffOpSize);
|
---|
12847 | }
|
---|
12848 |
|
---|
12849 |
|
---|
12850 | /** Opcode 0xca. */
|
---|
12851 | FNIEMOP_DEF(iemOp_retf_Iw)
|
---|
12852 | {
|
---|
12853 | IEMOP_MNEMONIC("retf Iw");
|
---|
12854 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
12855 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12856 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
12857 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_retf, pVCpu->iem.s.enmEffOpSize, u16Imm);
|
---|
12858 | }
|
---|
12859 |
|
---|
12860 |
|
---|
12861 | /** Opcode 0xcb. */
|
---|
12862 | FNIEMOP_DEF(iemOp_retf)
|
---|
12863 | {
|
---|
12864 | IEMOP_MNEMONIC("retf");
|
---|
12865 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12866 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
12867 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_retf, pVCpu->iem.s.enmEffOpSize, 0);
|
---|
12868 | }
|
---|
12869 |
|
---|
12870 |
|
---|
12871 | /** Opcode 0xcc. */
|
---|
12872 | FNIEMOP_DEF(iemOp_int_3)
|
---|
12873 | {
|
---|
12874 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12875 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_int, X86_XCPT_BP, true /*fIsBpInstr*/);
|
---|
12876 | }
|
---|
12877 |
|
---|
12878 |
|
---|
12879 | /** Opcode 0xcd. */
|
---|
12880 | FNIEMOP_DEF(iemOp_int_Ib)
|
---|
12881 | {
|
---|
12882 | uint8_t u8Int; IEM_OPCODE_GET_NEXT_U8(&u8Int);
|
---|
12883 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12884 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_int, u8Int, false /*fIsBpInstr*/);
|
---|
12885 | }
|
---|
12886 |
|
---|
12887 |
|
---|
12888 | /** Opcode 0xce. */
|
---|
12889 | FNIEMOP_DEF(iemOp_into)
|
---|
12890 | {
|
---|
12891 | IEMOP_MNEMONIC("into");
|
---|
12892 | IEMOP_HLP_NO_64BIT();
|
---|
12893 |
|
---|
12894 | IEM_MC_BEGIN(2, 0);
|
---|
12895 | IEM_MC_ARG_CONST(uint8_t, u8Int, /*=*/ X86_XCPT_OF, 0);
|
---|
12896 | IEM_MC_ARG_CONST(bool, fIsBpInstr, /*=*/ false, 1);
|
---|
12897 | IEM_MC_CALL_CIMPL_2(iemCImpl_int, u8Int, fIsBpInstr);
|
---|
12898 | IEM_MC_END();
|
---|
12899 | return VINF_SUCCESS;
|
---|
12900 | }
|
---|
12901 |
|
---|
12902 |
|
---|
12903 | /** Opcode 0xcf. */
|
---|
12904 | FNIEMOP_DEF(iemOp_iret)
|
---|
12905 | {
|
---|
12906 | IEMOP_MNEMONIC("iret");
|
---|
12907 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12908 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_iret, pVCpu->iem.s.enmEffOpSize);
|
---|
12909 | }
|
---|
12910 |
|
---|
12911 |
|
---|
12912 | /** Opcode 0xd0. */
|
---|
12913 | FNIEMOP_DEF(iemOp_Grp2_Eb_1)
|
---|
12914 | {
|
---|
12915 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
12916 | PCIEMOPSHIFTSIZES pImpl;
|
---|
12917 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
12918 | {
|
---|
12919 | case 0: pImpl = &g_iemAImpl_rol; IEMOP_MNEMONIC("rol Eb,1"); break;
|
---|
12920 | case 1: pImpl = &g_iemAImpl_ror; IEMOP_MNEMONIC("ror Eb,1"); break;
|
---|
12921 | case 2: pImpl = &g_iemAImpl_rcl; IEMOP_MNEMONIC("rcl Eb,1"); break;
|
---|
12922 | case 3: pImpl = &g_iemAImpl_rcr; IEMOP_MNEMONIC("rcr Eb,1"); break;
|
---|
12923 | case 4: pImpl = &g_iemAImpl_shl; IEMOP_MNEMONIC("shl Eb,1"); break;
|
---|
12924 | case 5: pImpl = &g_iemAImpl_shr; IEMOP_MNEMONIC("shr Eb,1"); break;
|
---|
12925 | case 7: pImpl = &g_iemAImpl_sar; IEMOP_MNEMONIC("sar Eb,1"); break;
|
---|
12926 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
12927 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe, well... */
|
---|
12928 | }
|
---|
12929 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_AF);
|
---|
12930 |
|
---|
12931 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
12932 | {
|
---|
12933 | /* register */
|
---|
12934 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12935 | IEM_MC_BEGIN(3, 0);
|
---|
12936 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
12937 | IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=*/1, 1);
|
---|
12938 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
12939 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
12940 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
12941 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, cShiftArg, pEFlags);
|
---|
12942 | IEM_MC_ADVANCE_RIP();
|
---|
12943 | IEM_MC_END();
|
---|
12944 | }
|
---|
12945 | else
|
---|
12946 | {
|
---|
12947 | /* memory */
|
---|
12948 | IEM_MC_BEGIN(3, 2);
|
---|
12949 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
12950 | IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=*/1, 1);
|
---|
12951 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
12952 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
12953 |
|
---|
12954 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
12955 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12956 | IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
12957 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
12958 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, cShiftArg, pEFlags);
|
---|
12959 |
|
---|
12960 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
|
---|
12961 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
12962 | IEM_MC_ADVANCE_RIP();
|
---|
12963 | IEM_MC_END();
|
---|
12964 | }
|
---|
12965 | return VINF_SUCCESS;
|
---|
12966 | }
|
---|
12967 |
|
---|
12968 |
|
---|
12969 |
|
---|
12970 | /** Opcode 0xd1. */
|
---|
12971 | FNIEMOP_DEF(iemOp_Grp2_Ev_1)
|
---|
12972 | {
|
---|
12973 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
12974 | PCIEMOPSHIFTSIZES pImpl;
|
---|
12975 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
12976 | {
|
---|
12977 | case 0: pImpl = &g_iemAImpl_rol; IEMOP_MNEMONIC("rol Ev,1"); break;
|
---|
12978 | case 1: pImpl = &g_iemAImpl_ror; IEMOP_MNEMONIC("ror Ev,1"); break;
|
---|
12979 | case 2: pImpl = &g_iemAImpl_rcl; IEMOP_MNEMONIC("rcl Ev,1"); break;
|
---|
12980 | case 3: pImpl = &g_iemAImpl_rcr; IEMOP_MNEMONIC("rcr Ev,1"); break;
|
---|
12981 | case 4: pImpl = &g_iemAImpl_shl; IEMOP_MNEMONIC("shl Ev,1"); break;
|
---|
12982 | case 5: pImpl = &g_iemAImpl_shr; IEMOP_MNEMONIC("shr Ev,1"); break;
|
---|
12983 | case 7: pImpl = &g_iemAImpl_sar; IEMOP_MNEMONIC("sar Ev,1"); break;
|
---|
12984 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
12985 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe, well... */
|
---|
12986 | }
|
---|
12987 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_AF);
|
---|
12988 |
|
---|
12989 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
12990 | {
|
---|
12991 | /* register */
|
---|
12992 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
12993 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
12994 | {
|
---|
12995 | case IEMMODE_16BIT:
|
---|
12996 | IEM_MC_BEGIN(3, 0);
|
---|
12997 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
12998 | IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=1*/1, 1);
|
---|
12999 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
13000 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
13001 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
13002 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, cShiftArg, pEFlags);
|
---|
13003 | IEM_MC_ADVANCE_RIP();
|
---|
13004 | IEM_MC_END();
|
---|
13005 | return VINF_SUCCESS;
|
---|
13006 |
|
---|
13007 | case IEMMODE_32BIT:
|
---|
13008 | IEM_MC_BEGIN(3, 0);
|
---|
13009 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
13010 | IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=1*/1, 1);
|
---|
13011 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
13012 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
13013 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
13014 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, cShiftArg, pEFlags);
|
---|
13015 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
13016 | IEM_MC_ADVANCE_RIP();
|
---|
13017 | IEM_MC_END();
|
---|
13018 | return VINF_SUCCESS;
|
---|
13019 |
|
---|
13020 | case IEMMODE_64BIT:
|
---|
13021 | IEM_MC_BEGIN(3, 0);
|
---|
13022 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
13023 | IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=1*/1, 1);
|
---|
13024 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
13025 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
13026 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
13027 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, cShiftArg, pEFlags);
|
---|
13028 | IEM_MC_ADVANCE_RIP();
|
---|
13029 | IEM_MC_END();
|
---|
13030 | return VINF_SUCCESS;
|
---|
13031 |
|
---|
13032 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
13033 | }
|
---|
13034 | }
|
---|
13035 | else
|
---|
13036 | {
|
---|
13037 | /* memory */
|
---|
13038 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
13039 | {
|
---|
13040 | case IEMMODE_16BIT:
|
---|
13041 | IEM_MC_BEGIN(3, 2);
|
---|
13042 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
13043 | IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=1*/1, 1);
|
---|
13044 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
13045 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13046 |
|
---|
13047 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13048 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13049 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
13050 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
13051 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, cShiftArg, pEFlags);
|
---|
13052 |
|
---|
13053 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
13054 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
13055 | IEM_MC_ADVANCE_RIP();
|
---|
13056 | IEM_MC_END();
|
---|
13057 | return VINF_SUCCESS;
|
---|
13058 |
|
---|
13059 | case IEMMODE_32BIT:
|
---|
13060 | IEM_MC_BEGIN(3, 2);
|
---|
13061 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
13062 | IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=1*/1, 1);
|
---|
13063 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
13064 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13065 |
|
---|
13066 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13067 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13068 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
13069 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
13070 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, cShiftArg, pEFlags);
|
---|
13071 |
|
---|
13072 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
13073 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
13074 | IEM_MC_ADVANCE_RIP();
|
---|
13075 | IEM_MC_END();
|
---|
13076 | return VINF_SUCCESS;
|
---|
13077 |
|
---|
13078 | case IEMMODE_64BIT:
|
---|
13079 | IEM_MC_BEGIN(3, 2);
|
---|
13080 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
13081 | IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=1*/1, 1);
|
---|
13082 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
13083 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13084 |
|
---|
13085 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13086 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13087 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
13088 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
13089 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, cShiftArg, pEFlags);
|
---|
13090 |
|
---|
13091 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
13092 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
13093 | IEM_MC_ADVANCE_RIP();
|
---|
13094 | IEM_MC_END();
|
---|
13095 | return VINF_SUCCESS;
|
---|
13096 |
|
---|
13097 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
13098 | }
|
---|
13099 | }
|
---|
13100 | }
|
---|
13101 |
|
---|
13102 |
|
---|
13103 | /** Opcode 0xd2. */
|
---|
13104 | FNIEMOP_DEF(iemOp_Grp2_Eb_CL)
|
---|
13105 | {
|
---|
13106 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
13107 | PCIEMOPSHIFTSIZES pImpl;
|
---|
13108 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
13109 | {
|
---|
13110 | case 0: pImpl = &g_iemAImpl_rol; IEMOP_MNEMONIC("rol Eb,CL"); break;
|
---|
13111 | case 1: pImpl = &g_iemAImpl_ror; IEMOP_MNEMONIC("ror Eb,CL"); break;
|
---|
13112 | case 2: pImpl = &g_iemAImpl_rcl; IEMOP_MNEMONIC("rcl Eb,CL"); break;
|
---|
13113 | case 3: pImpl = &g_iemAImpl_rcr; IEMOP_MNEMONIC("rcr Eb,CL"); break;
|
---|
13114 | case 4: pImpl = &g_iemAImpl_shl; IEMOP_MNEMONIC("shl Eb,CL"); break;
|
---|
13115 | case 5: pImpl = &g_iemAImpl_shr; IEMOP_MNEMONIC("shr Eb,CL"); break;
|
---|
13116 | case 7: pImpl = &g_iemAImpl_sar; IEMOP_MNEMONIC("sar Eb,CL"); break;
|
---|
13117 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
13118 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc, grr. */
|
---|
13119 | }
|
---|
13120 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_AF);
|
---|
13121 |
|
---|
13122 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
13123 | {
|
---|
13124 | /* register */
|
---|
13125 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13126 | IEM_MC_BEGIN(3, 0);
|
---|
13127 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
13128 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
13129 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
13130 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
13131 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
13132 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
13133 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, cShiftArg, pEFlags);
|
---|
13134 | IEM_MC_ADVANCE_RIP();
|
---|
13135 | IEM_MC_END();
|
---|
13136 | }
|
---|
13137 | else
|
---|
13138 | {
|
---|
13139 | /* memory */
|
---|
13140 | IEM_MC_BEGIN(3, 2);
|
---|
13141 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
13142 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
13143 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
13144 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13145 |
|
---|
13146 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13147 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13148 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
13149 | IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
13150 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
13151 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU8, pu8Dst, cShiftArg, pEFlags);
|
---|
13152 |
|
---|
13153 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
|
---|
13154 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
13155 | IEM_MC_ADVANCE_RIP();
|
---|
13156 | IEM_MC_END();
|
---|
13157 | }
|
---|
13158 | return VINF_SUCCESS;
|
---|
13159 | }
|
---|
13160 |
|
---|
13161 |
|
---|
13162 | /** Opcode 0xd3. */
|
---|
13163 | FNIEMOP_DEF(iemOp_Grp2_Ev_CL)
|
---|
13164 | {
|
---|
13165 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
13166 | PCIEMOPSHIFTSIZES pImpl;
|
---|
13167 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
13168 | {
|
---|
13169 | case 0: pImpl = &g_iemAImpl_rol; IEMOP_MNEMONIC("rol Ev,CL"); break;
|
---|
13170 | case 1: pImpl = &g_iemAImpl_ror; IEMOP_MNEMONIC("ror Ev,CL"); break;
|
---|
13171 | case 2: pImpl = &g_iemAImpl_rcl; IEMOP_MNEMONIC("rcl Ev,CL"); break;
|
---|
13172 | case 3: pImpl = &g_iemAImpl_rcr; IEMOP_MNEMONIC("rcr Ev,CL"); break;
|
---|
13173 | case 4: pImpl = &g_iemAImpl_shl; IEMOP_MNEMONIC("shl Ev,CL"); break;
|
---|
13174 | case 5: pImpl = &g_iemAImpl_shr; IEMOP_MNEMONIC("shr Ev,CL"); break;
|
---|
13175 | case 7: pImpl = &g_iemAImpl_sar; IEMOP_MNEMONIC("sar Ev,CL"); break;
|
---|
13176 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
13177 | IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* gcc maybe stupid */
|
---|
13178 | }
|
---|
13179 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_AF);
|
---|
13180 |
|
---|
13181 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
13182 | {
|
---|
13183 | /* register */
|
---|
13184 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13185 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
13186 | {
|
---|
13187 | case IEMMODE_16BIT:
|
---|
13188 | IEM_MC_BEGIN(3, 0);
|
---|
13189 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
13190 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
13191 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
13192 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
13193 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
13194 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
13195 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, cShiftArg, pEFlags);
|
---|
13196 | IEM_MC_ADVANCE_RIP();
|
---|
13197 | IEM_MC_END();
|
---|
13198 | return VINF_SUCCESS;
|
---|
13199 |
|
---|
13200 | case IEMMODE_32BIT:
|
---|
13201 | IEM_MC_BEGIN(3, 0);
|
---|
13202 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
13203 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
13204 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
13205 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
13206 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
13207 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
13208 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, cShiftArg, pEFlags);
|
---|
13209 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
|
---|
13210 | IEM_MC_ADVANCE_RIP();
|
---|
13211 | IEM_MC_END();
|
---|
13212 | return VINF_SUCCESS;
|
---|
13213 |
|
---|
13214 | case IEMMODE_64BIT:
|
---|
13215 | IEM_MC_BEGIN(3, 0);
|
---|
13216 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
13217 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
13218 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
13219 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
13220 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
13221 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
13222 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, cShiftArg, pEFlags);
|
---|
13223 | IEM_MC_ADVANCE_RIP();
|
---|
13224 | IEM_MC_END();
|
---|
13225 | return VINF_SUCCESS;
|
---|
13226 |
|
---|
13227 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
13228 | }
|
---|
13229 | }
|
---|
13230 | else
|
---|
13231 | {
|
---|
13232 | /* memory */
|
---|
13233 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
13234 | {
|
---|
13235 | case IEMMODE_16BIT:
|
---|
13236 | IEM_MC_BEGIN(3, 2);
|
---|
13237 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
13238 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
13239 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
13240 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13241 |
|
---|
13242 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13243 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13244 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
13245 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
13246 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
13247 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, cShiftArg, pEFlags);
|
---|
13248 |
|
---|
13249 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
13250 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
13251 | IEM_MC_ADVANCE_RIP();
|
---|
13252 | IEM_MC_END();
|
---|
13253 | return VINF_SUCCESS;
|
---|
13254 |
|
---|
13255 | case IEMMODE_32BIT:
|
---|
13256 | IEM_MC_BEGIN(3, 2);
|
---|
13257 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
13258 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
13259 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
13260 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13261 |
|
---|
13262 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13263 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13264 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
13265 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
13266 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
13267 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, cShiftArg, pEFlags);
|
---|
13268 |
|
---|
13269 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
13270 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
13271 | IEM_MC_ADVANCE_RIP();
|
---|
13272 | IEM_MC_END();
|
---|
13273 | return VINF_SUCCESS;
|
---|
13274 |
|
---|
13275 | case IEMMODE_64BIT:
|
---|
13276 | IEM_MC_BEGIN(3, 2);
|
---|
13277 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
13278 | IEM_MC_ARG(uint8_t, cShiftArg, 1);
|
---|
13279 | IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
|
---|
13280 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13281 |
|
---|
13282 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13283 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13284 | IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
|
---|
13285 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
13286 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
13287 | IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, cShiftArg, pEFlags);
|
---|
13288 |
|
---|
13289 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
13290 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
13291 | IEM_MC_ADVANCE_RIP();
|
---|
13292 | IEM_MC_END();
|
---|
13293 | return VINF_SUCCESS;
|
---|
13294 |
|
---|
13295 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
13296 | }
|
---|
13297 | }
|
---|
13298 | }
|
---|
13299 |
|
---|
13300 | /** Opcode 0xd4. */
|
---|
13301 | FNIEMOP_DEF(iemOp_aam_Ib)
|
---|
13302 | {
|
---|
13303 | IEMOP_MNEMONIC("aam Ib");
|
---|
13304 | uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
|
---|
13305 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13306 | IEMOP_HLP_NO_64BIT();
|
---|
13307 | if (!bImm)
|
---|
13308 | return IEMOP_RAISE_DIVIDE_ERROR();
|
---|
13309 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_aam, bImm);
|
---|
13310 | }
|
---|
13311 |
|
---|
13312 |
|
---|
13313 | /** Opcode 0xd5. */
|
---|
13314 | FNIEMOP_DEF(iemOp_aad_Ib)
|
---|
13315 | {
|
---|
13316 | IEMOP_MNEMONIC("aad Ib");
|
---|
13317 | uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
|
---|
13318 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13319 | IEMOP_HLP_NO_64BIT();
|
---|
13320 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_aad, bImm);
|
---|
13321 | }
|
---|
13322 |
|
---|
13323 |
|
---|
13324 | /** Opcode 0xd6. */
|
---|
13325 | FNIEMOP_DEF(iemOp_salc)
|
---|
13326 | {
|
---|
13327 | IEMOP_MNEMONIC("salc");
|
---|
13328 | IEMOP_HLP_MIN_286(); /* (undocument at the time) */
|
---|
13329 | uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
|
---|
13330 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13331 | IEMOP_HLP_NO_64BIT();
|
---|
13332 |
|
---|
13333 | IEM_MC_BEGIN(0, 0);
|
---|
13334 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
|
---|
13335 | IEM_MC_STORE_GREG_U8_CONST(X86_GREG_xAX, 0xff);
|
---|
13336 | } IEM_MC_ELSE() {
|
---|
13337 | IEM_MC_STORE_GREG_U8_CONST(X86_GREG_xAX, 0x00);
|
---|
13338 | } IEM_MC_ENDIF();
|
---|
13339 | IEM_MC_ADVANCE_RIP();
|
---|
13340 | IEM_MC_END();
|
---|
13341 | return VINF_SUCCESS;
|
---|
13342 | }
|
---|
13343 |
|
---|
13344 |
|
---|
13345 | /** Opcode 0xd7. */
|
---|
13346 | FNIEMOP_DEF(iemOp_xlat)
|
---|
13347 | {
|
---|
13348 | IEMOP_MNEMONIC("xlat");
|
---|
13349 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13350 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
13351 | {
|
---|
13352 | case IEMMODE_16BIT:
|
---|
13353 | IEM_MC_BEGIN(2, 0);
|
---|
13354 | IEM_MC_LOCAL(uint8_t, u8Tmp);
|
---|
13355 | IEM_MC_LOCAL(uint16_t, u16Addr);
|
---|
13356 | IEM_MC_FETCH_GREG_U8_ZX_U16(u16Addr, X86_GREG_xAX);
|
---|
13357 | IEM_MC_ADD_GREG_U16_TO_LOCAL(u16Addr, X86_GREG_xBX);
|
---|
13358 | IEM_MC_FETCH_MEM16_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u16Addr);
|
---|
13359 | IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp);
|
---|
13360 | IEM_MC_ADVANCE_RIP();
|
---|
13361 | IEM_MC_END();
|
---|
13362 | return VINF_SUCCESS;
|
---|
13363 |
|
---|
13364 | case IEMMODE_32BIT:
|
---|
13365 | IEM_MC_BEGIN(2, 0);
|
---|
13366 | IEM_MC_LOCAL(uint8_t, u8Tmp);
|
---|
13367 | IEM_MC_LOCAL(uint32_t, u32Addr);
|
---|
13368 | IEM_MC_FETCH_GREG_U8_ZX_U32(u32Addr, X86_GREG_xAX);
|
---|
13369 | IEM_MC_ADD_GREG_U32_TO_LOCAL(u32Addr, X86_GREG_xBX);
|
---|
13370 | IEM_MC_FETCH_MEM32_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u32Addr);
|
---|
13371 | IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp);
|
---|
13372 | IEM_MC_ADVANCE_RIP();
|
---|
13373 | IEM_MC_END();
|
---|
13374 | return VINF_SUCCESS;
|
---|
13375 |
|
---|
13376 | case IEMMODE_64BIT:
|
---|
13377 | IEM_MC_BEGIN(2, 0);
|
---|
13378 | IEM_MC_LOCAL(uint8_t, u8Tmp);
|
---|
13379 | IEM_MC_LOCAL(uint64_t, u64Addr);
|
---|
13380 | IEM_MC_FETCH_GREG_U8_ZX_U64(u64Addr, X86_GREG_xAX);
|
---|
13381 | IEM_MC_ADD_GREG_U64_TO_LOCAL(u64Addr, X86_GREG_xBX);
|
---|
13382 | IEM_MC_FETCH_MEM_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u64Addr);
|
---|
13383 | IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp);
|
---|
13384 | IEM_MC_ADVANCE_RIP();
|
---|
13385 | IEM_MC_END();
|
---|
13386 | return VINF_SUCCESS;
|
---|
13387 |
|
---|
13388 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
13389 | }
|
---|
13390 | }
|
---|
13391 |
|
---|
13392 |
|
---|
13393 | /**
|
---|
13394 | * Common worker for FPU instructions working on ST0 and STn, and storing the
|
---|
13395 | * result in ST0.
|
---|
13396 | *
|
---|
13397 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
13398 | */
|
---|
13399 | FNIEMOP_DEF_2(iemOpHlpFpu_st0_stN, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
|
---|
13400 | {
|
---|
13401 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13402 |
|
---|
13403 | IEM_MC_BEGIN(3, 1);
|
---|
13404 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
13405 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
13406 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
13407 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value2, 2);
|
---|
13408 |
|
---|
13409 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13410 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13411 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13412 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, bRm & X86_MODRM_RM_MASK)
|
---|
13413 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr80Value2);
|
---|
13414 | IEM_MC_STORE_FPU_RESULT(FpuRes, 0);
|
---|
13415 | IEM_MC_ELSE()
|
---|
13416 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
13417 | IEM_MC_ENDIF();
|
---|
13418 | IEM_MC_ADVANCE_RIP();
|
---|
13419 |
|
---|
13420 | IEM_MC_END();
|
---|
13421 | return VINF_SUCCESS;
|
---|
13422 | }
|
---|
13423 |
|
---|
13424 |
|
---|
13425 | /**
|
---|
13426 | * Common worker for FPU instructions working on ST0 and STn, and only affecting
|
---|
13427 | * flags.
|
---|
13428 | *
|
---|
13429 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
13430 | */
|
---|
13431 | FNIEMOP_DEF_2(iemOpHlpFpuNoStore_st0_stN, uint8_t, bRm, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
|
---|
13432 | {
|
---|
13433 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13434 |
|
---|
13435 | IEM_MC_BEGIN(3, 1);
|
---|
13436 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
13437 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
13438 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
13439 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value2, 2);
|
---|
13440 |
|
---|
13441 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13442 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13443 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13444 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, bRm & X86_MODRM_RM_MASK)
|
---|
13445 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pu16Fsw, pr80Value1, pr80Value2);
|
---|
13446 | IEM_MC_UPDATE_FSW(u16Fsw);
|
---|
13447 | IEM_MC_ELSE()
|
---|
13448 | IEM_MC_FPU_STACK_UNDERFLOW(UINT8_MAX);
|
---|
13449 | IEM_MC_ENDIF();
|
---|
13450 | IEM_MC_ADVANCE_RIP();
|
---|
13451 |
|
---|
13452 | IEM_MC_END();
|
---|
13453 | return VINF_SUCCESS;
|
---|
13454 | }
|
---|
13455 |
|
---|
13456 |
|
---|
13457 | /**
|
---|
13458 | * Common worker for FPU instructions working on ST0 and STn, only affecting
|
---|
13459 | * flags, and popping when done.
|
---|
13460 | *
|
---|
13461 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
13462 | */
|
---|
13463 | FNIEMOP_DEF_2(iemOpHlpFpuNoStore_st0_stN_pop, uint8_t, bRm, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
|
---|
13464 | {
|
---|
13465 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13466 |
|
---|
13467 | IEM_MC_BEGIN(3, 1);
|
---|
13468 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
13469 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
13470 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
13471 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value2, 2);
|
---|
13472 |
|
---|
13473 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13474 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13475 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13476 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, bRm & X86_MODRM_RM_MASK)
|
---|
13477 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pu16Fsw, pr80Value1, pr80Value2);
|
---|
13478 | IEM_MC_UPDATE_FSW_THEN_POP(u16Fsw);
|
---|
13479 | IEM_MC_ELSE()
|
---|
13480 | IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(UINT8_MAX);
|
---|
13481 | IEM_MC_ENDIF();
|
---|
13482 | IEM_MC_ADVANCE_RIP();
|
---|
13483 |
|
---|
13484 | IEM_MC_END();
|
---|
13485 | return VINF_SUCCESS;
|
---|
13486 | }
|
---|
13487 |
|
---|
13488 |
|
---|
13489 | /** Opcode 0xd8 11/0. */
|
---|
13490 | FNIEMOP_DEF_1(iemOp_fadd_stN, uint8_t, bRm)
|
---|
13491 | {
|
---|
13492 | IEMOP_MNEMONIC("fadd st0,stN");
|
---|
13493 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, bRm, iemAImpl_fadd_r80_by_r80);
|
---|
13494 | }
|
---|
13495 |
|
---|
13496 |
|
---|
13497 | /** Opcode 0xd8 11/1. */
|
---|
13498 | FNIEMOP_DEF_1(iemOp_fmul_stN, uint8_t, bRm)
|
---|
13499 | {
|
---|
13500 | IEMOP_MNEMONIC("fmul st0,stN");
|
---|
13501 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, bRm, iemAImpl_fmul_r80_by_r80);
|
---|
13502 | }
|
---|
13503 |
|
---|
13504 |
|
---|
13505 | /** Opcode 0xd8 11/2. */
|
---|
13506 | FNIEMOP_DEF_1(iemOp_fcom_stN, uint8_t, bRm)
|
---|
13507 | {
|
---|
13508 | IEMOP_MNEMONIC("fcom st0,stN");
|
---|
13509 | return FNIEMOP_CALL_2(iemOpHlpFpuNoStore_st0_stN, bRm, iemAImpl_fcom_r80_by_r80);
|
---|
13510 | }
|
---|
13511 |
|
---|
13512 |
|
---|
13513 | /** Opcode 0xd8 11/3. */
|
---|
13514 | FNIEMOP_DEF_1(iemOp_fcomp_stN, uint8_t, bRm)
|
---|
13515 | {
|
---|
13516 | IEMOP_MNEMONIC("fcomp st0,stN");
|
---|
13517 | return FNIEMOP_CALL_2(iemOpHlpFpuNoStore_st0_stN_pop, bRm, iemAImpl_fcom_r80_by_r80);
|
---|
13518 | }
|
---|
13519 |
|
---|
13520 |
|
---|
13521 | /** Opcode 0xd8 11/4. */
|
---|
13522 | FNIEMOP_DEF_1(iemOp_fsub_stN, uint8_t, bRm)
|
---|
13523 | {
|
---|
13524 | IEMOP_MNEMONIC("fsub st0,stN");
|
---|
13525 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, bRm, iemAImpl_fsub_r80_by_r80);
|
---|
13526 | }
|
---|
13527 |
|
---|
13528 |
|
---|
13529 | /** Opcode 0xd8 11/5. */
|
---|
13530 | FNIEMOP_DEF_1(iemOp_fsubr_stN, uint8_t, bRm)
|
---|
13531 | {
|
---|
13532 | IEMOP_MNEMONIC("fsubr st0,stN");
|
---|
13533 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, bRm, iemAImpl_fsubr_r80_by_r80);
|
---|
13534 | }
|
---|
13535 |
|
---|
13536 |
|
---|
13537 | /** Opcode 0xd8 11/6. */
|
---|
13538 | FNIEMOP_DEF_1(iemOp_fdiv_stN, uint8_t, bRm)
|
---|
13539 | {
|
---|
13540 | IEMOP_MNEMONIC("fdiv st0,stN");
|
---|
13541 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, bRm, iemAImpl_fdiv_r80_by_r80);
|
---|
13542 | }
|
---|
13543 |
|
---|
13544 |
|
---|
13545 | /** Opcode 0xd8 11/7. */
|
---|
13546 | FNIEMOP_DEF_1(iemOp_fdivr_stN, uint8_t, bRm)
|
---|
13547 | {
|
---|
13548 | IEMOP_MNEMONIC("fdivr st0,stN");
|
---|
13549 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, bRm, iemAImpl_fdivr_r80_by_r80);
|
---|
13550 | }
|
---|
13551 |
|
---|
13552 |
|
---|
13553 | /**
|
---|
13554 | * Common worker for FPU instructions working on ST0 and an m32r, and storing
|
---|
13555 | * the result in ST0.
|
---|
13556 | *
|
---|
13557 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
13558 | */
|
---|
13559 | FNIEMOP_DEF_2(iemOpHlpFpu_st0_m32r, uint8_t, bRm, PFNIEMAIMPLFPUR32, pfnAImpl)
|
---|
13560 | {
|
---|
13561 | IEM_MC_BEGIN(3, 3);
|
---|
13562 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
13563 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
13564 | IEM_MC_LOCAL(RTFLOAT32U, r32Val2);
|
---|
13565 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
13566 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
13567 | IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U, pr32Val2, r32Val2, 2);
|
---|
13568 |
|
---|
13569 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
13570 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13571 |
|
---|
13572 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13573 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13574 | IEM_MC_FETCH_MEM_R32(r32Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13575 |
|
---|
13576 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13577 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
13578 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr32Val2);
|
---|
13579 | IEM_MC_STORE_FPU_RESULT(FpuRes, 0);
|
---|
13580 | IEM_MC_ELSE()
|
---|
13581 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
13582 | IEM_MC_ENDIF();
|
---|
13583 | IEM_MC_ADVANCE_RIP();
|
---|
13584 |
|
---|
13585 | IEM_MC_END();
|
---|
13586 | return VINF_SUCCESS;
|
---|
13587 | }
|
---|
13588 |
|
---|
13589 |
|
---|
13590 | /** Opcode 0xd8 !11/0. */
|
---|
13591 | FNIEMOP_DEF_1(iemOp_fadd_m32r, uint8_t, bRm)
|
---|
13592 | {
|
---|
13593 | IEMOP_MNEMONIC("fadd st0,m32r");
|
---|
13594 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32r, bRm, iemAImpl_fadd_r80_by_r32);
|
---|
13595 | }
|
---|
13596 |
|
---|
13597 |
|
---|
13598 | /** Opcode 0xd8 !11/1. */
|
---|
13599 | FNIEMOP_DEF_1(iemOp_fmul_m32r, uint8_t, bRm)
|
---|
13600 | {
|
---|
13601 | IEMOP_MNEMONIC("fmul st0,m32r");
|
---|
13602 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32r, bRm, iemAImpl_fmul_r80_by_r32);
|
---|
13603 | }
|
---|
13604 |
|
---|
13605 |
|
---|
13606 | /** Opcode 0xd8 !11/2. */
|
---|
13607 | FNIEMOP_DEF_1(iemOp_fcom_m32r, uint8_t, bRm)
|
---|
13608 | {
|
---|
13609 | IEMOP_MNEMONIC("fcom st0,m32r");
|
---|
13610 |
|
---|
13611 | IEM_MC_BEGIN(3, 3);
|
---|
13612 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
13613 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
13614 | IEM_MC_LOCAL(RTFLOAT32U, r32Val2);
|
---|
13615 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
13616 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
13617 | IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U, pr32Val2, r32Val2, 2);
|
---|
13618 |
|
---|
13619 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
13620 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13621 |
|
---|
13622 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13623 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13624 | IEM_MC_FETCH_MEM_R32(r32Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13625 |
|
---|
13626 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13627 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
13628 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fcom_r80_by_r32, pu16Fsw, pr80Value1, pr32Val2);
|
---|
13629 | IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13630 | IEM_MC_ELSE()
|
---|
13631 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13632 | IEM_MC_ENDIF();
|
---|
13633 | IEM_MC_ADVANCE_RIP();
|
---|
13634 |
|
---|
13635 | IEM_MC_END();
|
---|
13636 | return VINF_SUCCESS;
|
---|
13637 | }
|
---|
13638 |
|
---|
13639 |
|
---|
13640 | /** Opcode 0xd8 !11/3. */
|
---|
13641 | FNIEMOP_DEF_1(iemOp_fcomp_m32r, uint8_t, bRm)
|
---|
13642 | {
|
---|
13643 | IEMOP_MNEMONIC("fcomp st0,m32r");
|
---|
13644 |
|
---|
13645 | IEM_MC_BEGIN(3, 3);
|
---|
13646 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
13647 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
13648 | IEM_MC_LOCAL(RTFLOAT32U, r32Val2);
|
---|
13649 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
13650 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
13651 | IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U, pr32Val2, r32Val2, 2);
|
---|
13652 |
|
---|
13653 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
13654 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13655 |
|
---|
13656 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13657 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13658 | IEM_MC_FETCH_MEM_R32(r32Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13659 |
|
---|
13660 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13661 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
13662 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fcom_r80_by_r32, pu16Fsw, pr80Value1, pr32Val2);
|
---|
13663 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13664 | IEM_MC_ELSE()
|
---|
13665 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13666 | IEM_MC_ENDIF();
|
---|
13667 | IEM_MC_ADVANCE_RIP();
|
---|
13668 |
|
---|
13669 | IEM_MC_END();
|
---|
13670 | return VINF_SUCCESS;
|
---|
13671 | }
|
---|
13672 |
|
---|
13673 |
|
---|
13674 | /** Opcode 0xd8 !11/4. */
|
---|
13675 | FNIEMOP_DEF_1(iemOp_fsub_m32r, uint8_t, bRm)
|
---|
13676 | {
|
---|
13677 | IEMOP_MNEMONIC("fsub st0,m32r");
|
---|
13678 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32r, bRm, iemAImpl_fsub_r80_by_r32);
|
---|
13679 | }
|
---|
13680 |
|
---|
13681 |
|
---|
13682 | /** Opcode 0xd8 !11/5. */
|
---|
13683 | FNIEMOP_DEF_1(iemOp_fsubr_m32r, uint8_t, bRm)
|
---|
13684 | {
|
---|
13685 | IEMOP_MNEMONIC("fsubr st0,m32r");
|
---|
13686 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32r, bRm, iemAImpl_fsubr_r80_by_r32);
|
---|
13687 | }
|
---|
13688 |
|
---|
13689 |
|
---|
13690 | /** Opcode 0xd8 !11/6. */
|
---|
13691 | FNIEMOP_DEF_1(iemOp_fdiv_m32r, uint8_t, bRm)
|
---|
13692 | {
|
---|
13693 | IEMOP_MNEMONIC("fdiv st0,m32r");
|
---|
13694 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32r, bRm, iemAImpl_fdiv_r80_by_r32);
|
---|
13695 | }
|
---|
13696 |
|
---|
13697 |
|
---|
13698 | /** Opcode 0xd8 !11/7. */
|
---|
13699 | FNIEMOP_DEF_1(iemOp_fdivr_m32r, uint8_t, bRm)
|
---|
13700 | {
|
---|
13701 | IEMOP_MNEMONIC("fdivr st0,m32r");
|
---|
13702 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32r, bRm, iemAImpl_fdivr_r80_by_r32);
|
---|
13703 | }
|
---|
13704 |
|
---|
13705 |
|
---|
13706 | /** Opcode 0xd8. */
|
---|
13707 | FNIEMOP_DEF(iemOp_EscF0)
|
---|
13708 | {
|
---|
13709 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
13710 | pVCpu->iem.s.uFpuOpcode = RT_MAKE_U16(bRm, 0xd8 & 0x7);
|
---|
13711 |
|
---|
13712 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
13713 | {
|
---|
13714 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
13715 | {
|
---|
13716 | case 0: return FNIEMOP_CALL_1(iemOp_fadd_stN, bRm);
|
---|
13717 | case 1: return FNIEMOP_CALL_1(iemOp_fmul_stN, bRm);
|
---|
13718 | case 2: return FNIEMOP_CALL_1(iemOp_fcom_stN, bRm);
|
---|
13719 | case 3: return FNIEMOP_CALL_1(iemOp_fcomp_stN, bRm);
|
---|
13720 | case 4: return FNIEMOP_CALL_1(iemOp_fsub_stN, bRm);
|
---|
13721 | case 5: return FNIEMOP_CALL_1(iemOp_fsubr_stN, bRm);
|
---|
13722 | case 6: return FNIEMOP_CALL_1(iemOp_fdiv_stN, bRm);
|
---|
13723 | case 7: return FNIEMOP_CALL_1(iemOp_fdivr_stN, bRm);
|
---|
13724 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
13725 | }
|
---|
13726 | }
|
---|
13727 | else
|
---|
13728 | {
|
---|
13729 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
13730 | {
|
---|
13731 | case 0: return FNIEMOP_CALL_1(iemOp_fadd_m32r, bRm);
|
---|
13732 | case 1: return FNIEMOP_CALL_1(iemOp_fmul_m32r, bRm);
|
---|
13733 | case 2: return FNIEMOP_CALL_1(iemOp_fcom_m32r, bRm);
|
---|
13734 | case 3: return FNIEMOP_CALL_1(iemOp_fcomp_m32r, bRm);
|
---|
13735 | case 4: return FNIEMOP_CALL_1(iemOp_fsub_m32r, bRm);
|
---|
13736 | case 5: return FNIEMOP_CALL_1(iemOp_fsubr_m32r, bRm);
|
---|
13737 | case 6: return FNIEMOP_CALL_1(iemOp_fdiv_m32r, bRm);
|
---|
13738 | case 7: return FNIEMOP_CALL_1(iemOp_fdivr_m32r, bRm);
|
---|
13739 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
13740 | }
|
---|
13741 | }
|
---|
13742 | }
|
---|
13743 |
|
---|
13744 |
|
---|
13745 | /** Opcode 0xd9 /0 mem32real
|
---|
13746 | * @sa iemOp_fld_m64r */
|
---|
13747 | FNIEMOP_DEF_1(iemOp_fld_m32r, uint8_t, bRm)
|
---|
13748 | {
|
---|
13749 | IEMOP_MNEMONIC("fld m32r");
|
---|
13750 |
|
---|
13751 | IEM_MC_BEGIN(2, 3);
|
---|
13752 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
13753 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
13754 | IEM_MC_LOCAL(RTFLOAT32U, r32Val);
|
---|
13755 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
13756 | IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U, pr32Val, r32Val, 1);
|
---|
13757 |
|
---|
13758 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
13759 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13760 |
|
---|
13761 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13762 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13763 | IEM_MC_FETCH_MEM_R32(r32Val, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13764 |
|
---|
13765 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13766 | IEM_MC_IF_FPUREG_IS_EMPTY(7)
|
---|
13767 | IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fld_r32_to_r80, pFpuRes, pr32Val);
|
---|
13768 | IEM_MC_PUSH_FPU_RESULT_MEM_OP(FpuRes, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13769 | IEM_MC_ELSE()
|
---|
13770 | IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13771 | IEM_MC_ENDIF();
|
---|
13772 | IEM_MC_ADVANCE_RIP();
|
---|
13773 |
|
---|
13774 | IEM_MC_END();
|
---|
13775 | return VINF_SUCCESS;
|
---|
13776 | }
|
---|
13777 |
|
---|
13778 |
|
---|
13779 | /** Opcode 0xd9 !11/2 mem32real */
|
---|
13780 | FNIEMOP_DEF_1(iemOp_fst_m32r, uint8_t, bRm)
|
---|
13781 | {
|
---|
13782 | IEMOP_MNEMONIC("fst m32r");
|
---|
13783 | IEM_MC_BEGIN(3, 2);
|
---|
13784 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13785 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
13786 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
13787 | IEM_MC_ARG(PRTFLOAT32U, pr32Dst, 1);
|
---|
13788 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
13789 |
|
---|
13790 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13791 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13792 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13793 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13794 |
|
---|
13795 | IEM_MC_MEM_MAP(pr32Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
13796 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13797 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
13798 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r32, pu16Fsw, pr32Dst, pr80Value);
|
---|
13799 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pr32Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
13800 | IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
13801 | IEM_MC_ELSE()
|
---|
13802 | IEM_MC_IF_FCW_IM()
|
---|
13803 | IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(pr32Dst);
|
---|
13804 | IEM_MC_MEM_COMMIT_AND_UNMAP(pr32Dst, IEM_ACCESS_DATA_W);
|
---|
13805 | IEM_MC_ENDIF();
|
---|
13806 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
13807 | IEM_MC_ENDIF();
|
---|
13808 | IEM_MC_ADVANCE_RIP();
|
---|
13809 |
|
---|
13810 | IEM_MC_END();
|
---|
13811 | return VINF_SUCCESS;
|
---|
13812 | }
|
---|
13813 |
|
---|
13814 |
|
---|
13815 | /** Opcode 0xd9 !11/3 */
|
---|
13816 | FNIEMOP_DEF_1(iemOp_fstp_m32r, uint8_t, bRm)
|
---|
13817 | {
|
---|
13818 | IEMOP_MNEMONIC("fstp m32r");
|
---|
13819 | IEM_MC_BEGIN(3, 2);
|
---|
13820 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13821 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
13822 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
13823 | IEM_MC_ARG(PRTFLOAT32U, pr32Dst, 1);
|
---|
13824 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
13825 |
|
---|
13826 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13827 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13828 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13829 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13830 |
|
---|
13831 | IEM_MC_MEM_MAP(pr32Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
13832 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13833 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
13834 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r32, pu16Fsw, pr32Dst, pr80Value);
|
---|
13835 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pr32Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
13836 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
13837 | IEM_MC_ELSE()
|
---|
13838 | IEM_MC_IF_FCW_IM()
|
---|
13839 | IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(pr32Dst);
|
---|
13840 | IEM_MC_MEM_COMMIT_AND_UNMAP(pr32Dst, IEM_ACCESS_DATA_W);
|
---|
13841 | IEM_MC_ENDIF();
|
---|
13842 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
13843 | IEM_MC_ENDIF();
|
---|
13844 | IEM_MC_ADVANCE_RIP();
|
---|
13845 |
|
---|
13846 | IEM_MC_END();
|
---|
13847 | return VINF_SUCCESS;
|
---|
13848 | }
|
---|
13849 |
|
---|
13850 |
|
---|
13851 | /** Opcode 0xd9 !11/4 */
|
---|
13852 | FNIEMOP_DEF_1(iemOp_fldenv, uint8_t, bRm)
|
---|
13853 | {
|
---|
13854 | IEMOP_MNEMONIC("fldenv m14/28byte");
|
---|
13855 | IEM_MC_BEGIN(3, 0);
|
---|
13856 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0);
|
---|
13857 | IEM_MC_ARG(uint8_t, iEffSeg, 1);
|
---|
13858 | IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 2);
|
---|
13859 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
13860 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13861 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13862 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
13863 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
13864 | IEM_MC_CALL_CIMPL_3(iemCImpl_fldenv, enmEffOpSize, iEffSeg, GCPtrEffSrc);
|
---|
13865 | IEM_MC_END();
|
---|
13866 | return VINF_SUCCESS;
|
---|
13867 | }
|
---|
13868 |
|
---|
13869 |
|
---|
13870 | /** Opcode 0xd9 !11/5 */
|
---|
13871 | FNIEMOP_DEF_1(iemOp_fldcw, uint8_t, bRm)
|
---|
13872 | {
|
---|
13873 | IEMOP_MNEMONIC("fldcw m2byte");
|
---|
13874 | IEM_MC_BEGIN(1, 1);
|
---|
13875 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
13876 | IEM_MC_ARG(uint16_t, u16Fsw, 0);
|
---|
13877 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
13878 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13879 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13880 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
13881 | IEM_MC_FETCH_MEM_U16(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
13882 | IEM_MC_CALL_CIMPL_1(iemCImpl_fldcw, u16Fsw);
|
---|
13883 | IEM_MC_END();
|
---|
13884 | return VINF_SUCCESS;
|
---|
13885 | }
|
---|
13886 |
|
---|
13887 |
|
---|
13888 | /** Opcode 0xd9 !11/6 */
|
---|
13889 | FNIEMOP_DEF_1(iemOp_fnstenv, uint8_t, bRm)
|
---|
13890 | {
|
---|
13891 | IEMOP_MNEMONIC("fstenv m14/m28byte");
|
---|
13892 | IEM_MC_BEGIN(3, 0);
|
---|
13893 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0);
|
---|
13894 | IEM_MC_ARG(uint8_t, iEffSeg, 1);
|
---|
13895 | IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 2);
|
---|
13896 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13897 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13898 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13899 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
13900 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
13901 | IEM_MC_CALL_CIMPL_3(iemCImpl_fnstenv, enmEffOpSize, iEffSeg, GCPtrEffDst);
|
---|
13902 | IEM_MC_END();
|
---|
13903 | return VINF_SUCCESS;
|
---|
13904 | }
|
---|
13905 |
|
---|
13906 |
|
---|
13907 | /** Opcode 0xd9 !11/7 */
|
---|
13908 | FNIEMOP_DEF_1(iemOp_fnstcw, uint8_t, bRm)
|
---|
13909 | {
|
---|
13910 | IEMOP_MNEMONIC("fnstcw m2byte");
|
---|
13911 | IEM_MC_BEGIN(2, 0);
|
---|
13912 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
13913 | IEM_MC_LOCAL(uint16_t, u16Fcw);
|
---|
13914 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
13915 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13916 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13917 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
13918 | IEM_MC_FETCH_FCW(u16Fcw);
|
---|
13919 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Fcw);
|
---|
13920 | IEM_MC_ADVANCE_RIP(); /* C0-C3 are documented as undefined, we leave them unmodified. */
|
---|
13921 | IEM_MC_END();
|
---|
13922 | return VINF_SUCCESS;
|
---|
13923 | }
|
---|
13924 |
|
---|
13925 |
|
---|
13926 | /** Opcode 0xd9 0xd0, 0xd9 0xd8-0xdf, ++?. */
|
---|
13927 | FNIEMOP_DEF(iemOp_fnop)
|
---|
13928 | {
|
---|
13929 | IEMOP_MNEMONIC("fnop");
|
---|
13930 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13931 |
|
---|
13932 | IEM_MC_BEGIN(0, 0);
|
---|
13933 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13934 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13935 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
13936 | /** @todo Testcase: looks like FNOP leaves FOP alone but updates FPUIP. Could be
|
---|
13937 | * intel optimizations. Investigate. */
|
---|
13938 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
13939 | IEM_MC_ADVANCE_RIP(); /* C0-C3 are documented as undefined, we leave them unmodified. */
|
---|
13940 | IEM_MC_END();
|
---|
13941 | return VINF_SUCCESS;
|
---|
13942 | }
|
---|
13943 |
|
---|
13944 |
|
---|
13945 | /** Opcode 0xd9 11/0 stN */
|
---|
13946 | FNIEMOP_DEF_1(iemOp_fld_stN, uint8_t, bRm)
|
---|
13947 | {
|
---|
13948 | IEMOP_MNEMONIC("fld stN");
|
---|
13949 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13950 |
|
---|
13951 | /** @todo Testcase: Check if this raises \#MF? Intel mentioned it not. AMD
|
---|
13952 | * indicates that it does. */
|
---|
13953 | IEM_MC_BEGIN(0, 2);
|
---|
13954 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80Value);
|
---|
13955 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
13956 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13957 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13958 |
|
---|
13959 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13960 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, bRm & X86_MODRM_RM_MASK)
|
---|
13961 | IEM_MC_SET_FPU_RESULT(FpuRes, 0 /*FSW*/, pr80Value);
|
---|
13962 | IEM_MC_PUSH_FPU_RESULT(FpuRes);
|
---|
13963 | IEM_MC_ELSE()
|
---|
13964 | IEM_MC_FPU_STACK_PUSH_UNDERFLOW();
|
---|
13965 | IEM_MC_ENDIF();
|
---|
13966 |
|
---|
13967 | IEM_MC_ADVANCE_RIP();
|
---|
13968 | IEM_MC_END();
|
---|
13969 |
|
---|
13970 | return VINF_SUCCESS;
|
---|
13971 | }
|
---|
13972 |
|
---|
13973 |
|
---|
13974 | /** Opcode 0xd9 11/3 stN */
|
---|
13975 | FNIEMOP_DEF_1(iemOp_fxch_stN, uint8_t, bRm)
|
---|
13976 | {
|
---|
13977 | IEMOP_MNEMONIC("fxch stN");
|
---|
13978 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
13979 |
|
---|
13980 | /** @todo Testcase: Check if this raises \#MF? Intel mentioned it not. AMD
|
---|
13981 | * indicates that it does. */
|
---|
13982 | IEM_MC_BEGIN(1, 3);
|
---|
13983 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80Value1);
|
---|
13984 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80Value2);
|
---|
13985 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
13986 | IEM_MC_ARG_CONST(uint8_t, iStReg, /*=*/ bRm & X86_MODRM_RM_MASK, 0);
|
---|
13987 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
13988 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
13989 |
|
---|
13990 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
13991 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, bRm & X86_MODRM_RM_MASK)
|
---|
13992 | IEM_MC_SET_FPU_RESULT(FpuRes, X86_FSW_C1, pr80Value2);
|
---|
13993 | IEM_MC_STORE_FPUREG_R80_SRC_REF(bRm & X86_MODRM_RM_MASK, pr80Value1);
|
---|
13994 | IEM_MC_STORE_FPU_RESULT(FpuRes, 0);
|
---|
13995 | IEM_MC_ELSE()
|
---|
13996 | IEM_MC_CALL_CIMPL_1(iemCImpl_fxch_underflow, iStReg);
|
---|
13997 | IEM_MC_ENDIF();
|
---|
13998 |
|
---|
13999 | IEM_MC_ADVANCE_RIP();
|
---|
14000 | IEM_MC_END();
|
---|
14001 |
|
---|
14002 | return VINF_SUCCESS;
|
---|
14003 | }
|
---|
14004 |
|
---|
14005 |
|
---|
14006 | /** Opcode 0xd9 11/4, 0xdd 11/2. */
|
---|
14007 | FNIEMOP_DEF_1(iemOp_fstp_stN, uint8_t, bRm)
|
---|
14008 | {
|
---|
14009 | IEMOP_MNEMONIC("fstp st0,stN");
|
---|
14010 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14011 |
|
---|
14012 | /* fstp st0, st0 is frequendly used as an official 'ffreep st0' sequence. */
|
---|
14013 | uint8_t const iDstReg = bRm & X86_MODRM_RM_MASK;
|
---|
14014 | if (!iDstReg)
|
---|
14015 | {
|
---|
14016 | IEM_MC_BEGIN(0, 1);
|
---|
14017 | IEM_MC_LOCAL_CONST(uint16_t, u16Fsw, /*=*/ 0);
|
---|
14018 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14019 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14020 |
|
---|
14021 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14022 | IEM_MC_IF_FPUREG_NOT_EMPTY(0)
|
---|
14023 | IEM_MC_UPDATE_FSW_THEN_POP(u16Fsw);
|
---|
14024 | IEM_MC_ELSE()
|
---|
14025 | IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(0);
|
---|
14026 | IEM_MC_ENDIF();
|
---|
14027 |
|
---|
14028 | IEM_MC_ADVANCE_RIP();
|
---|
14029 | IEM_MC_END();
|
---|
14030 | }
|
---|
14031 | else
|
---|
14032 | {
|
---|
14033 | IEM_MC_BEGIN(0, 2);
|
---|
14034 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80Value);
|
---|
14035 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
14036 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14037 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14038 |
|
---|
14039 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14040 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
14041 | IEM_MC_SET_FPU_RESULT(FpuRes, 0 /*FSW*/, pr80Value);
|
---|
14042 | IEM_MC_STORE_FPU_RESULT_THEN_POP(FpuRes, iDstReg);
|
---|
14043 | IEM_MC_ELSE()
|
---|
14044 | IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(iDstReg);
|
---|
14045 | IEM_MC_ENDIF();
|
---|
14046 |
|
---|
14047 | IEM_MC_ADVANCE_RIP();
|
---|
14048 | IEM_MC_END();
|
---|
14049 | }
|
---|
14050 | return VINF_SUCCESS;
|
---|
14051 | }
|
---|
14052 |
|
---|
14053 |
|
---|
14054 | /**
|
---|
14055 | * Common worker for FPU instructions working on ST0 and replaces it with the
|
---|
14056 | * result, i.e. unary operators.
|
---|
14057 | *
|
---|
14058 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
14059 | */
|
---|
14060 | FNIEMOP_DEF_1(iemOpHlpFpu_st0, PFNIEMAIMPLFPUR80UNARY, pfnAImpl)
|
---|
14061 | {
|
---|
14062 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14063 |
|
---|
14064 | IEM_MC_BEGIN(2, 1);
|
---|
14065 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
14066 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
14067 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 1);
|
---|
14068 |
|
---|
14069 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14070 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14071 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14072 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
14073 | IEM_MC_CALL_FPU_AIMPL_2(pfnAImpl, pFpuRes, pr80Value);
|
---|
14074 | IEM_MC_STORE_FPU_RESULT(FpuRes, 0);
|
---|
14075 | IEM_MC_ELSE()
|
---|
14076 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
14077 | IEM_MC_ENDIF();
|
---|
14078 | IEM_MC_ADVANCE_RIP();
|
---|
14079 |
|
---|
14080 | IEM_MC_END();
|
---|
14081 | return VINF_SUCCESS;
|
---|
14082 | }
|
---|
14083 |
|
---|
14084 |
|
---|
14085 | /** Opcode 0xd9 0xe0. */
|
---|
14086 | FNIEMOP_DEF(iemOp_fchs)
|
---|
14087 | {
|
---|
14088 | IEMOP_MNEMONIC("fchs st0");
|
---|
14089 | return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fchs_r80);
|
---|
14090 | }
|
---|
14091 |
|
---|
14092 |
|
---|
14093 | /** Opcode 0xd9 0xe1. */
|
---|
14094 | FNIEMOP_DEF(iemOp_fabs)
|
---|
14095 | {
|
---|
14096 | IEMOP_MNEMONIC("fabs st0");
|
---|
14097 | return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fabs_r80);
|
---|
14098 | }
|
---|
14099 |
|
---|
14100 |
|
---|
14101 | /**
|
---|
14102 | * Common worker for FPU instructions working on ST0 and only returns FSW.
|
---|
14103 | *
|
---|
14104 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
14105 | */
|
---|
14106 | FNIEMOP_DEF_1(iemOpHlpFpuNoStore_st0, PFNIEMAIMPLFPUR80UNARYFSW, pfnAImpl)
|
---|
14107 | {
|
---|
14108 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14109 |
|
---|
14110 | IEM_MC_BEGIN(2, 1);
|
---|
14111 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
14112 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
14113 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 1);
|
---|
14114 |
|
---|
14115 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14116 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14117 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14118 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
14119 | IEM_MC_CALL_FPU_AIMPL_2(pfnAImpl, pu16Fsw, pr80Value);
|
---|
14120 | IEM_MC_UPDATE_FSW(u16Fsw);
|
---|
14121 | IEM_MC_ELSE()
|
---|
14122 | IEM_MC_FPU_STACK_UNDERFLOW(UINT8_MAX);
|
---|
14123 | IEM_MC_ENDIF();
|
---|
14124 | IEM_MC_ADVANCE_RIP();
|
---|
14125 |
|
---|
14126 | IEM_MC_END();
|
---|
14127 | return VINF_SUCCESS;
|
---|
14128 | }
|
---|
14129 |
|
---|
14130 |
|
---|
14131 | /** Opcode 0xd9 0xe4. */
|
---|
14132 | FNIEMOP_DEF(iemOp_ftst)
|
---|
14133 | {
|
---|
14134 | IEMOP_MNEMONIC("ftst st0");
|
---|
14135 | return FNIEMOP_CALL_1(iemOpHlpFpuNoStore_st0, iemAImpl_ftst_r80);
|
---|
14136 | }
|
---|
14137 |
|
---|
14138 |
|
---|
14139 | /** Opcode 0xd9 0xe5. */
|
---|
14140 | FNIEMOP_DEF(iemOp_fxam)
|
---|
14141 | {
|
---|
14142 | IEMOP_MNEMONIC("fxam st0");
|
---|
14143 | return FNIEMOP_CALL_1(iemOpHlpFpuNoStore_st0, iemAImpl_fxam_r80);
|
---|
14144 | }
|
---|
14145 |
|
---|
14146 |
|
---|
14147 | /**
|
---|
14148 | * Common worker for FPU instructions pushing a constant onto the FPU stack.
|
---|
14149 | *
|
---|
14150 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
14151 | */
|
---|
14152 | FNIEMOP_DEF_1(iemOpHlpFpuPushConstant, PFNIEMAIMPLFPUR80LDCONST, pfnAImpl)
|
---|
14153 | {
|
---|
14154 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14155 |
|
---|
14156 | IEM_MC_BEGIN(1, 1);
|
---|
14157 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
14158 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
14159 |
|
---|
14160 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14161 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14162 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14163 | IEM_MC_IF_FPUREG_IS_EMPTY(7)
|
---|
14164 | IEM_MC_CALL_FPU_AIMPL_1(pfnAImpl, pFpuRes);
|
---|
14165 | IEM_MC_PUSH_FPU_RESULT(FpuRes);
|
---|
14166 | IEM_MC_ELSE()
|
---|
14167 | IEM_MC_FPU_STACK_PUSH_OVERFLOW();
|
---|
14168 | IEM_MC_ENDIF();
|
---|
14169 | IEM_MC_ADVANCE_RIP();
|
---|
14170 |
|
---|
14171 | IEM_MC_END();
|
---|
14172 | return VINF_SUCCESS;
|
---|
14173 | }
|
---|
14174 |
|
---|
14175 |
|
---|
14176 | /** Opcode 0xd9 0xe8. */
|
---|
14177 | FNIEMOP_DEF(iemOp_fld1)
|
---|
14178 | {
|
---|
14179 | IEMOP_MNEMONIC("fld1");
|
---|
14180 | return FNIEMOP_CALL_1(iemOpHlpFpuPushConstant, iemAImpl_fld1);
|
---|
14181 | }
|
---|
14182 |
|
---|
14183 |
|
---|
14184 | /** Opcode 0xd9 0xe9. */
|
---|
14185 | FNIEMOP_DEF(iemOp_fldl2t)
|
---|
14186 | {
|
---|
14187 | IEMOP_MNEMONIC("fldl2t");
|
---|
14188 | return FNIEMOP_CALL_1(iemOpHlpFpuPushConstant, iemAImpl_fldl2t);
|
---|
14189 | }
|
---|
14190 |
|
---|
14191 |
|
---|
14192 | /** Opcode 0xd9 0xea. */
|
---|
14193 | FNIEMOP_DEF(iemOp_fldl2e)
|
---|
14194 | {
|
---|
14195 | IEMOP_MNEMONIC("fldl2e");
|
---|
14196 | return FNIEMOP_CALL_1(iemOpHlpFpuPushConstant, iemAImpl_fldl2e);
|
---|
14197 | }
|
---|
14198 |
|
---|
14199 | /** Opcode 0xd9 0xeb. */
|
---|
14200 | FNIEMOP_DEF(iemOp_fldpi)
|
---|
14201 | {
|
---|
14202 | IEMOP_MNEMONIC("fldpi");
|
---|
14203 | return FNIEMOP_CALL_1(iemOpHlpFpuPushConstant, iemAImpl_fldpi);
|
---|
14204 | }
|
---|
14205 |
|
---|
14206 |
|
---|
14207 | /** Opcode 0xd9 0xec. */
|
---|
14208 | FNIEMOP_DEF(iemOp_fldlg2)
|
---|
14209 | {
|
---|
14210 | IEMOP_MNEMONIC("fldlg2");
|
---|
14211 | return FNIEMOP_CALL_1(iemOpHlpFpuPushConstant, iemAImpl_fldlg2);
|
---|
14212 | }
|
---|
14213 |
|
---|
14214 | /** Opcode 0xd9 0xed. */
|
---|
14215 | FNIEMOP_DEF(iemOp_fldln2)
|
---|
14216 | {
|
---|
14217 | IEMOP_MNEMONIC("fldln2");
|
---|
14218 | return FNIEMOP_CALL_1(iemOpHlpFpuPushConstant, iemAImpl_fldln2);
|
---|
14219 | }
|
---|
14220 |
|
---|
14221 |
|
---|
14222 | /** Opcode 0xd9 0xee. */
|
---|
14223 | FNIEMOP_DEF(iemOp_fldz)
|
---|
14224 | {
|
---|
14225 | IEMOP_MNEMONIC("fldz");
|
---|
14226 | return FNIEMOP_CALL_1(iemOpHlpFpuPushConstant, iemAImpl_fldz);
|
---|
14227 | }
|
---|
14228 |
|
---|
14229 |
|
---|
14230 | /** Opcode 0xd9 0xf0. */
|
---|
14231 | FNIEMOP_DEF(iemOp_f2xm1)
|
---|
14232 | {
|
---|
14233 | IEMOP_MNEMONIC("f2xm1 st0");
|
---|
14234 | return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_f2xm1_r80);
|
---|
14235 | }
|
---|
14236 |
|
---|
14237 |
|
---|
14238 | /** Opcode 0xd9 0xf1. */
|
---|
14239 | FNIEMOP_DEF(iemOp_fylx2)
|
---|
14240 | {
|
---|
14241 | IEMOP_MNEMONIC("fylx2 st0");
|
---|
14242 | return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fyl2x_r80);
|
---|
14243 | }
|
---|
14244 |
|
---|
14245 |
|
---|
14246 | /**
|
---|
14247 | * Common worker for FPU instructions working on ST0 and having two outputs, one
|
---|
14248 | * replacing ST0 and one pushed onto the stack.
|
---|
14249 | *
|
---|
14250 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
14251 | */
|
---|
14252 | FNIEMOP_DEF_1(iemOpHlpFpuReplace_st0_push, PFNIEMAIMPLFPUR80UNARYTWO, pfnAImpl)
|
---|
14253 | {
|
---|
14254 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14255 |
|
---|
14256 | IEM_MC_BEGIN(2, 1);
|
---|
14257 | IEM_MC_LOCAL(IEMFPURESULTTWO, FpuResTwo);
|
---|
14258 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULTTWO, pFpuResTwo, FpuResTwo, 0);
|
---|
14259 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 1);
|
---|
14260 |
|
---|
14261 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14262 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14263 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14264 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
14265 | IEM_MC_CALL_FPU_AIMPL_2(pfnAImpl, pFpuResTwo, pr80Value);
|
---|
14266 | IEM_MC_PUSH_FPU_RESULT_TWO(FpuResTwo);
|
---|
14267 | IEM_MC_ELSE()
|
---|
14268 | IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO();
|
---|
14269 | IEM_MC_ENDIF();
|
---|
14270 | IEM_MC_ADVANCE_RIP();
|
---|
14271 |
|
---|
14272 | IEM_MC_END();
|
---|
14273 | return VINF_SUCCESS;
|
---|
14274 | }
|
---|
14275 |
|
---|
14276 |
|
---|
14277 | /** Opcode 0xd9 0xf2. */
|
---|
14278 | FNIEMOP_DEF(iemOp_fptan)
|
---|
14279 | {
|
---|
14280 | IEMOP_MNEMONIC("fptan st0");
|
---|
14281 | return FNIEMOP_CALL_1(iemOpHlpFpuReplace_st0_push, iemAImpl_fptan_r80_r80);
|
---|
14282 | }
|
---|
14283 |
|
---|
14284 |
|
---|
14285 | /**
|
---|
14286 | * Common worker for FPU instructions working on STn and ST0, storing the result
|
---|
14287 | * in STn, and popping the stack unless IE, DE or ZE was raised.
|
---|
14288 | *
|
---|
14289 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
14290 | */
|
---|
14291 | FNIEMOP_DEF_2(iemOpHlpFpu_stN_st0_pop, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
|
---|
14292 | {
|
---|
14293 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14294 |
|
---|
14295 | IEM_MC_BEGIN(3, 1);
|
---|
14296 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
14297 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
14298 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
14299 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value2, 2);
|
---|
14300 |
|
---|
14301 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14302 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14303 |
|
---|
14304 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14305 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, bRm & X86_MODRM_RM_MASK, pr80Value2, 0)
|
---|
14306 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr80Value2);
|
---|
14307 | IEM_MC_STORE_FPU_RESULT_THEN_POP(FpuRes, bRm & X86_MODRM_RM_MASK);
|
---|
14308 | IEM_MC_ELSE()
|
---|
14309 | IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(bRm & X86_MODRM_RM_MASK);
|
---|
14310 | IEM_MC_ENDIF();
|
---|
14311 | IEM_MC_ADVANCE_RIP();
|
---|
14312 |
|
---|
14313 | IEM_MC_END();
|
---|
14314 | return VINF_SUCCESS;
|
---|
14315 | }
|
---|
14316 |
|
---|
14317 |
|
---|
14318 | /** Opcode 0xd9 0xf3. */
|
---|
14319 | FNIEMOP_DEF(iemOp_fpatan)
|
---|
14320 | {
|
---|
14321 | IEMOP_MNEMONIC("fpatan st1,st0");
|
---|
14322 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, 1, iemAImpl_fpatan_r80_by_r80);
|
---|
14323 | }
|
---|
14324 |
|
---|
14325 |
|
---|
14326 | /** Opcode 0xd9 0xf4. */
|
---|
14327 | FNIEMOP_DEF(iemOp_fxtract)
|
---|
14328 | {
|
---|
14329 | IEMOP_MNEMONIC("fxtract st0");
|
---|
14330 | return FNIEMOP_CALL_1(iemOpHlpFpuReplace_st0_push, iemAImpl_fxtract_r80_r80);
|
---|
14331 | }
|
---|
14332 |
|
---|
14333 |
|
---|
14334 | /** Opcode 0xd9 0xf5. */
|
---|
14335 | FNIEMOP_DEF(iemOp_fprem1)
|
---|
14336 | {
|
---|
14337 | IEMOP_MNEMONIC("fprem1 st0, st1");
|
---|
14338 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, 1, iemAImpl_fprem1_r80_by_r80);
|
---|
14339 | }
|
---|
14340 |
|
---|
14341 |
|
---|
14342 | /** Opcode 0xd9 0xf6. */
|
---|
14343 | FNIEMOP_DEF(iemOp_fdecstp)
|
---|
14344 | {
|
---|
14345 | IEMOP_MNEMONIC("fdecstp");
|
---|
14346 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14347 | /* Note! C0, C2 and C3 are documented as undefined, we clear them. */
|
---|
14348 | /** @todo Testcase: Check whether FOP, FPUIP and FPUCS are affected by
|
---|
14349 | * FINCSTP and FDECSTP. */
|
---|
14350 |
|
---|
14351 | IEM_MC_BEGIN(0,0);
|
---|
14352 |
|
---|
14353 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14354 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14355 |
|
---|
14356 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
14357 | IEM_MC_FPU_STACK_DEC_TOP();
|
---|
14358 | IEM_MC_UPDATE_FSW_CONST(0);
|
---|
14359 |
|
---|
14360 | IEM_MC_ADVANCE_RIP();
|
---|
14361 | IEM_MC_END();
|
---|
14362 | return VINF_SUCCESS;
|
---|
14363 | }
|
---|
14364 |
|
---|
14365 |
|
---|
14366 | /** Opcode 0xd9 0xf7. */
|
---|
14367 | FNIEMOP_DEF(iemOp_fincstp)
|
---|
14368 | {
|
---|
14369 | IEMOP_MNEMONIC("fincstp");
|
---|
14370 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14371 | /* Note! C0, C2 and C3 are documented as undefined, we clear them. */
|
---|
14372 | /** @todo Testcase: Check whether FOP, FPUIP and FPUCS are affected by
|
---|
14373 | * FINCSTP and FDECSTP. */
|
---|
14374 |
|
---|
14375 | IEM_MC_BEGIN(0,0);
|
---|
14376 |
|
---|
14377 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14378 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14379 |
|
---|
14380 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
14381 | IEM_MC_FPU_STACK_INC_TOP();
|
---|
14382 | IEM_MC_UPDATE_FSW_CONST(0);
|
---|
14383 |
|
---|
14384 | IEM_MC_ADVANCE_RIP();
|
---|
14385 | IEM_MC_END();
|
---|
14386 | return VINF_SUCCESS;
|
---|
14387 | }
|
---|
14388 |
|
---|
14389 |
|
---|
14390 | /** Opcode 0xd9 0xf8. */
|
---|
14391 | FNIEMOP_DEF(iemOp_fprem)
|
---|
14392 | {
|
---|
14393 | IEMOP_MNEMONIC("fprem st0, st1");
|
---|
14394 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, 1, iemAImpl_fprem_r80_by_r80);
|
---|
14395 | }
|
---|
14396 |
|
---|
14397 |
|
---|
14398 | /** Opcode 0xd9 0xf9. */
|
---|
14399 | FNIEMOP_DEF(iemOp_fyl2xp1)
|
---|
14400 | {
|
---|
14401 | IEMOP_MNEMONIC("fyl2xp1 st1,st0");
|
---|
14402 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, 1, iemAImpl_fyl2xp1_r80_by_r80);
|
---|
14403 | }
|
---|
14404 |
|
---|
14405 |
|
---|
14406 | /** Opcode 0xd9 0xfa. */
|
---|
14407 | FNIEMOP_DEF(iemOp_fsqrt)
|
---|
14408 | {
|
---|
14409 | IEMOP_MNEMONIC("fsqrt st0");
|
---|
14410 | return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fsqrt_r80);
|
---|
14411 | }
|
---|
14412 |
|
---|
14413 |
|
---|
14414 | /** Opcode 0xd9 0xfb. */
|
---|
14415 | FNIEMOP_DEF(iemOp_fsincos)
|
---|
14416 | {
|
---|
14417 | IEMOP_MNEMONIC("fsincos st0");
|
---|
14418 | return FNIEMOP_CALL_1(iemOpHlpFpuReplace_st0_push, iemAImpl_fsincos_r80_r80);
|
---|
14419 | }
|
---|
14420 |
|
---|
14421 |
|
---|
14422 | /** Opcode 0xd9 0xfc. */
|
---|
14423 | FNIEMOP_DEF(iemOp_frndint)
|
---|
14424 | {
|
---|
14425 | IEMOP_MNEMONIC("frndint st0");
|
---|
14426 | return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_frndint_r80);
|
---|
14427 | }
|
---|
14428 |
|
---|
14429 |
|
---|
14430 | /** Opcode 0xd9 0xfd. */
|
---|
14431 | FNIEMOP_DEF(iemOp_fscale)
|
---|
14432 | {
|
---|
14433 | IEMOP_MNEMONIC("fscale st0, st1");
|
---|
14434 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_stN, 1, iemAImpl_fscale_r80_by_r80);
|
---|
14435 | }
|
---|
14436 |
|
---|
14437 |
|
---|
14438 | /** Opcode 0xd9 0xfe. */
|
---|
14439 | FNIEMOP_DEF(iemOp_fsin)
|
---|
14440 | {
|
---|
14441 | IEMOP_MNEMONIC("fsin st0");
|
---|
14442 | return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fsin_r80);
|
---|
14443 | }
|
---|
14444 |
|
---|
14445 |
|
---|
14446 | /** Opcode 0xd9 0xff. */
|
---|
14447 | FNIEMOP_DEF(iemOp_fcos)
|
---|
14448 | {
|
---|
14449 | IEMOP_MNEMONIC("fcos st0");
|
---|
14450 | return FNIEMOP_CALL_1(iemOpHlpFpu_st0, iemAImpl_fcos_r80);
|
---|
14451 | }
|
---|
14452 |
|
---|
14453 |
|
---|
14454 | /** Used by iemOp_EscF1. */
|
---|
14455 | IEM_STATIC const PFNIEMOP g_apfnEscF1_E0toFF[32] =
|
---|
14456 | {
|
---|
14457 | /* 0xe0 */ iemOp_fchs,
|
---|
14458 | /* 0xe1 */ iemOp_fabs,
|
---|
14459 | /* 0xe2 */ iemOp_Invalid,
|
---|
14460 | /* 0xe3 */ iemOp_Invalid,
|
---|
14461 | /* 0xe4 */ iemOp_ftst,
|
---|
14462 | /* 0xe5 */ iemOp_fxam,
|
---|
14463 | /* 0xe6 */ iemOp_Invalid,
|
---|
14464 | /* 0xe7 */ iemOp_Invalid,
|
---|
14465 | /* 0xe8 */ iemOp_fld1,
|
---|
14466 | /* 0xe9 */ iemOp_fldl2t,
|
---|
14467 | /* 0xea */ iemOp_fldl2e,
|
---|
14468 | /* 0xeb */ iemOp_fldpi,
|
---|
14469 | /* 0xec */ iemOp_fldlg2,
|
---|
14470 | /* 0xed */ iemOp_fldln2,
|
---|
14471 | /* 0xee */ iemOp_fldz,
|
---|
14472 | /* 0xef */ iemOp_Invalid,
|
---|
14473 | /* 0xf0 */ iemOp_f2xm1,
|
---|
14474 | /* 0xf1 */ iemOp_fylx2,
|
---|
14475 | /* 0xf2 */ iemOp_fptan,
|
---|
14476 | /* 0xf3 */ iemOp_fpatan,
|
---|
14477 | /* 0xf4 */ iemOp_fxtract,
|
---|
14478 | /* 0xf5 */ iemOp_fprem1,
|
---|
14479 | /* 0xf6 */ iemOp_fdecstp,
|
---|
14480 | /* 0xf7 */ iemOp_fincstp,
|
---|
14481 | /* 0xf8 */ iemOp_fprem,
|
---|
14482 | /* 0xf9 */ iemOp_fyl2xp1,
|
---|
14483 | /* 0xfa */ iemOp_fsqrt,
|
---|
14484 | /* 0xfb */ iemOp_fsincos,
|
---|
14485 | /* 0xfc */ iemOp_frndint,
|
---|
14486 | /* 0xfd */ iemOp_fscale,
|
---|
14487 | /* 0xfe */ iemOp_fsin,
|
---|
14488 | /* 0xff */ iemOp_fcos
|
---|
14489 | };
|
---|
14490 |
|
---|
14491 |
|
---|
14492 | /** Opcode 0xd9. */
|
---|
14493 | FNIEMOP_DEF(iemOp_EscF1)
|
---|
14494 | {
|
---|
14495 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
14496 | pVCpu->iem.s.uFpuOpcode = RT_MAKE_U16(bRm, 0xd9 & 0x7);
|
---|
14497 |
|
---|
14498 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
14499 | {
|
---|
14500 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
14501 | {
|
---|
14502 | case 0: return FNIEMOP_CALL_1(iemOp_fld_stN, bRm);
|
---|
14503 | case 1: return FNIEMOP_CALL_1(iemOp_fxch_stN, bRm);
|
---|
14504 | case 2:
|
---|
14505 | if (bRm == 0xd0)
|
---|
14506 | return FNIEMOP_CALL(iemOp_fnop);
|
---|
14507 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
14508 | case 3: return FNIEMOP_CALL_1(iemOp_fstp_stN, bRm); /* Reserved. Intel behavior seems to be FSTP ST(i) though. */
|
---|
14509 | case 4:
|
---|
14510 | case 5:
|
---|
14511 | case 6:
|
---|
14512 | case 7:
|
---|
14513 | Assert((unsigned)bRm - 0xe0U < RT_ELEMENTS(g_apfnEscF1_E0toFF));
|
---|
14514 | return FNIEMOP_CALL(g_apfnEscF1_E0toFF[bRm - 0xe0]);
|
---|
14515 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
14516 | }
|
---|
14517 | }
|
---|
14518 | else
|
---|
14519 | {
|
---|
14520 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
14521 | {
|
---|
14522 | case 0: return FNIEMOP_CALL_1(iemOp_fld_m32r, bRm);
|
---|
14523 | case 1: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
14524 | case 2: return FNIEMOP_CALL_1(iemOp_fst_m32r, bRm);
|
---|
14525 | case 3: return FNIEMOP_CALL_1(iemOp_fstp_m32r, bRm);
|
---|
14526 | case 4: return FNIEMOP_CALL_1(iemOp_fldenv, bRm);
|
---|
14527 | case 5: return FNIEMOP_CALL_1(iemOp_fldcw, bRm);
|
---|
14528 | case 6: return FNIEMOP_CALL_1(iemOp_fnstenv, bRm);
|
---|
14529 | case 7: return FNIEMOP_CALL_1(iemOp_fnstcw, bRm);
|
---|
14530 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
14531 | }
|
---|
14532 | }
|
---|
14533 | }
|
---|
14534 |
|
---|
14535 |
|
---|
14536 | /** Opcode 0xda 11/0. */
|
---|
14537 | FNIEMOP_DEF_1(iemOp_fcmovb_stN, uint8_t, bRm)
|
---|
14538 | {
|
---|
14539 | IEMOP_MNEMONIC("fcmovb st0,stN");
|
---|
14540 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14541 |
|
---|
14542 | IEM_MC_BEGIN(0, 1);
|
---|
14543 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80ValueN);
|
---|
14544 |
|
---|
14545 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14546 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14547 |
|
---|
14548 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14549 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0)
|
---|
14550 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF)
|
---|
14551 | IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN);
|
---|
14552 | IEM_MC_ENDIF();
|
---|
14553 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
14554 | IEM_MC_ELSE()
|
---|
14555 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
14556 | IEM_MC_ENDIF();
|
---|
14557 | IEM_MC_ADVANCE_RIP();
|
---|
14558 |
|
---|
14559 | IEM_MC_END();
|
---|
14560 | return VINF_SUCCESS;
|
---|
14561 | }
|
---|
14562 |
|
---|
14563 |
|
---|
14564 | /** Opcode 0xda 11/1. */
|
---|
14565 | FNIEMOP_DEF_1(iemOp_fcmove_stN, uint8_t, bRm)
|
---|
14566 | {
|
---|
14567 | IEMOP_MNEMONIC("fcmove st0,stN");
|
---|
14568 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14569 |
|
---|
14570 | IEM_MC_BEGIN(0, 1);
|
---|
14571 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80ValueN);
|
---|
14572 |
|
---|
14573 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14574 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14575 |
|
---|
14576 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14577 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0)
|
---|
14578 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF)
|
---|
14579 | IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN);
|
---|
14580 | IEM_MC_ENDIF();
|
---|
14581 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
14582 | IEM_MC_ELSE()
|
---|
14583 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
14584 | IEM_MC_ENDIF();
|
---|
14585 | IEM_MC_ADVANCE_RIP();
|
---|
14586 |
|
---|
14587 | IEM_MC_END();
|
---|
14588 | return VINF_SUCCESS;
|
---|
14589 | }
|
---|
14590 |
|
---|
14591 |
|
---|
14592 | /** Opcode 0xda 11/2. */
|
---|
14593 | FNIEMOP_DEF_1(iemOp_fcmovbe_stN, uint8_t, bRm)
|
---|
14594 | {
|
---|
14595 | IEMOP_MNEMONIC("fcmovbe st0,stN");
|
---|
14596 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14597 |
|
---|
14598 | IEM_MC_BEGIN(0, 1);
|
---|
14599 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80ValueN);
|
---|
14600 |
|
---|
14601 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14602 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14603 |
|
---|
14604 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14605 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0)
|
---|
14606 | IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF)
|
---|
14607 | IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN);
|
---|
14608 | IEM_MC_ENDIF();
|
---|
14609 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
14610 | IEM_MC_ELSE()
|
---|
14611 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
14612 | IEM_MC_ENDIF();
|
---|
14613 | IEM_MC_ADVANCE_RIP();
|
---|
14614 |
|
---|
14615 | IEM_MC_END();
|
---|
14616 | return VINF_SUCCESS;
|
---|
14617 | }
|
---|
14618 |
|
---|
14619 |
|
---|
14620 | /** Opcode 0xda 11/3. */
|
---|
14621 | FNIEMOP_DEF_1(iemOp_fcmovu_stN, uint8_t, bRm)
|
---|
14622 | {
|
---|
14623 | IEMOP_MNEMONIC("fcmovu st0,stN");
|
---|
14624 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14625 |
|
---|
14626 | IEM_MC_BEGIN(0, 1);
|
---|
14627 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80ValueN);
|
---|
14628 |
|
---|
14629 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14630 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14631 |
|
---|
14632 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14633 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0)
|
---|
14634 | IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF)
|
---|
14635 | IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN);
|
---|
14636 | IEM_MC_ENDIF();
|
---|
14637 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
14638 | IEM_MC_ELSE()
|
---|
14639 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
14640 | IEM_MC_ENDIF();
|
---|
14641 | IEM_MC_ADVANCE_RIP();
|
---|
14642 |
|
---|
14643 | IEM_MC_END();
|
---|
14644 | return VINF_SUCCESS;
|
---|
14645 | }
|
---|
14646 |
|
---|
14647 |
|
---|
14648 | /**
|
---|
14649 | * Common worker for FPU instructions working on ST0 and STn, only affecting
|
---|
14650 | * flags, and popping twice when done.
|
---|
14651 | *
|
---|
14652 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
14653 | */
|
---|
14654 | FNIEMOP_DEF_1(iemOpHlpFpuNoStore_st0_stN_pop_pop, PFNIEMAIMPLFPUR80FSW, pfnAImpl)
|
---|
14655 | {
|
---|
14656 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14657 |
|
---|
14658 | IEM_MC_BEGIN(3, 1);
|
---|
14659 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
14660 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
14661 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
14662 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value2, 2);
|
---|
14663 |
|
---|
14664 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14665 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14666 |
|
---|
14667 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14668 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, 0, pr80Value2, 1)
|
---|
14669 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pu16Fsw, pr80Value1, pr80Value2);
|
---|
14670 | IEM_MC_UPDATE_FSW_THEN_POP_POP(u16Fsw);
|
---|
14671 | IEM_MC_ELSE()
|
---|
14672 | IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP();
|
---|
14673 | IEM_MC_ENDIF();
|
---|
14674 | IEM_MC_ADVANCE_RIP();
|
---|
14675 |
|
---|
14676 | IEM_MC_END();
|
---|
14677 | return VINF_SUCCESS;
|
---|
14678 | }
|
---|
14679 |
|
---|
14680 |
|
---|
14681 | /** Opcode 0xda 0xe9. */
|
---|
14682 | FNIEMOP_DEF(iemOp_fucompp)
|
---|
14683 | {
|
---|
14684 | IEMOP_MNEMONIC("fucompp st0,stN");
|
---|
14685 | return FNIEMOP_CALL_1(iemOpHlpFpuNoStore_st0_stN_pop_pop, iemAImpl_fucom_r80_by_r80);
|
---|
14686 | }
|
---|
14687 |
|
---|
14688 |
|
---|
14689 | /**
|
---|
14690 | * Common worker for FPU instructions working on ST0 and an m32i, and storing
|
---|
14691 | * the result in ST0.
|
---|
14692 | *
|
---|
14693 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
14694 | */
|
---|
14695 | FNIEMOP_DEF_2(iemOpHlpFpu_st0_m32i, uint8_t, bRm, PFNIEMAIMPLFPUI32, pfnAImpl)
|
---|
14696 | {
|
---|
14697 | IEM_MC_BEGIN(3, 3);
|
---|
14698 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
14699 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
14700 | IEM_MC_LOCAL(int32_t, i32Val2);
|
---|
14701 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
14702 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
14703 | IEM_MC_ARG_LOCAL_REF(int32_t const *, pi32Val2, i32Val2, 2);
|
---|
14704 |
|
---|
14705 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
14706 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14707 |
|
---|
14708 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14709 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14710 | IEM_MC_FETCH_MEM_I32(i32Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14711 |
|
---|
14712 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14713 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
14714 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pi32Val2);
|
---|
14715 | IEM_MC_STORE_FPU_RESULT(FpuRes, 0);
|
---|
14716 | IEM_MC_ELSE()
|
---|
14717 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
14718 | IEM_MC_ENDIF();
|
---|
14719 | IEM_MC_ADVANCE_RIP();
|
---|
14720 |
|
---|
14721 | IEM_MC_END();
|
---|
14722 | return VINF_SUCCESS;
|
---|
14723 | }
|
---|
14724 |
|
---|
14725 |
|
---|
14726 | /** Opcode 0xda !11/0. */
|
---|
14727 | FNIEMOP_DEF_1(iemOp_fiadd_m32i, uint8_t, bRm)
|
---|
14728 | {
|
---|
14729 | IEMOP_MNEMONIC("fiadd m32i");
|
---|
14730 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fiadd_r80_by_i32);
|
---|
14731 | }
|
---|
14732 |
|
---|
14733 |
|
---|
14734 | /** Opcode 0xda !11/1. */
|
---|
14735 | FNIEMOP_DEF_1(iemOp_fimul_m32i, uint8_t, bRm)
|
---|
14736 | {
|
---|
14737 | IEMOP_MNEMONIC("fimul m32i");
|
---|
14738 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fimul_r80_by_i32);
|
---|
14739 | }
|
---|
14740 |
|
---|
14741 |
|
---|
14742 | /** Opcode 0xda !11/2. */
|
---|
14743 | FNIEMOP_DEF_1(iemOp_ficom_m32i, uint8_t, bRm)
|
---|
14744 | {
|
---|
14745 | IEMOP_MNEMONIC("ficom st0,m32i");
|
---|
14746 |
|
---|
14747 | IEM_MC_BEGIN(3, 3);
|
---|
14748 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
14749 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
14750 | IEM_MC_LOCAL(int32_t, i32Val2);
|
---|
14751 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
14752 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
14753 | IEM_MC_ARG_LOCAL_REF(int32_t const *, pi32Val2, i32Val2, 2);
|
---|
14754 |
|
---|
14755 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
14756 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14757 |
|
---|
14758 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14759 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14760 | IEM_MC_FETCH_MEM_I32(i32Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14761 |
|
---|
14762 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14763 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
14764 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i32, pu16Fsw, pr80Value1, pi32Val2);
|
---|
14765 | IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14766 | IEM_MC_ELSE()
|
---|
14767 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14768 | IEM_MC_ENDIF();
|
---|
14769 | IEM_MC_ADVANCE_RIP();
|
---|
14770 |
|
---|
14771 | IEM_MC_END();
|
---|
14772 | return VINF_SUCCESS;
|
---|
14773 | }
|
---|
14774 |
|
---|
14775 |
|
---|
14776 | /** Opcode 0xda !11/3. */
|
---|
14777 | FNIEMOP_DEF_1(iemOp_ficomp_m32i, uint8_t, bRm)
|
---|
14778 | {
|
---|
14779 | IEMOP_MNEMONIC("ficomp st0,m32i");
|
---|
14780 |
|
---|
14781 | IEM_MC_BEGIN(3, 3);
|
---|
14782 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
14783 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
14784 | IEM_MC_LOCAL(int32_t, i32Val2);
|
---|
14785 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
14786 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
14787 | IEM_MC_ARG_LOCAL_REF(int32_t const *, pi32Val2, i32Val2, 2);
|
---|
14788 |
|
---|
14789 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
14790 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14791 |
|
---|
14792 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14793 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14794 | IEM_MC_FETCH_MEM_I32(i32Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14795 |
|
---|
14796 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14797 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
14798 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i32, pu16Fsw, pr80Value1, pi32Val2);
|
---|
14799 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14800 | IEM_MC_ELSE()
|
---|
14801 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14802 | IEM_MC_ENDIF();
|
---|
14803 | IEM_MC_ADVANCE_RIP();
|
---|
14804 |
|
---|
14805 | IEM_MC_END();
|
---|
14806 | return VINF_SUCCESS;
|
---|
14807 | }
|
---|
14808 |
|
---|
14809 |
|
---|
14810 | /** Opcode 0xda !11/4. */
|
---|
14811 | FNIEMOP_DEF_1(iemOp_fisub_m32i, uint8_t, bRm)
|
---|
14812 | {
|
---|
14813 | IEMOP_MNEMONIC("fisub m32i");
|
---|
14814 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fisub_r80_by_i32);
|
---|
14815 | }
|
---|
14816 |
|
---|
14817 |
|
---|
14818 | /** Opcode 0xda !11/5. */
|
---|
14819 | FNIEMOP_DEF_1(iemOp_fisubr_m32i, uint8_t, bRm)
|
---|
14820 | {
|
---|
14821 | IEMOP_MNEMONIC("fisubr m32i");
|
---|
14822 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fisubr_r80_by_i32);
|
---|
14823 | }
|
---|
14824 |
|
---|
14825 |
|
---|
14826 | /** Opcode 0xda !11/6. */
|
---|
14827 | FNIEMOP_DEF_1(iemOp_fidiv_m32i, uint8_t, bRm)
|
---|
14828 | {
|
---|
14829 | IEMOP_MNEMONIC("fidiv m32i");
|
---|
14830 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fidiv_r80_by_i32);
|
---|
14831 | }
|
---|
14832 |
|
---|
14833 |
|
---|
14834 | /** Opcode 0xda !11/7. */
|
---|
14835 | FNIEMOP_DEF_1(iemOp_fidivr_m32i, uint8_t, bRm)
|
---|
14836 | {
|
---|
14837 | IEMOP_MNEMONIC("fidivr m32i");
|
---|
14838 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m32i, bRm, iemAImpl_fidivr_r80_by_i32);
|
---|
14839 | }
|
---|
14840 |
|
---|
14841 |
|
---|
14842 | /** Opcode 0xda. */
|
---|
14843 | FNIEMOP_DEF(iemOp_EscF2)
|
---|
14844 | {
|
---|
14845 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
14846 | pVCpu->iem.s.uFpuOpcode = RT_MAKE_U16(bRm, 0xda & 0x7);
|
---|
14847 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
14848 | {
|
---|
14849 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
14850 | {
|
---|
14851 | case 0: return FNIEMOP_CALL_1(iemOp_fcmovb_stN, bRm);
|
---|
14852 | case 1: return FNIEMOP_CALL_1(iemOp_fcmove_stN, bRm);
|
---|
14853 | case 2: return FNIEMOP_CALL_1(iemOp_fcmovbe_stN, bRm);
|
---|
14854 | case 3: return FNIEMOP_CALL_1(iemOp_fcmovu_stN, bRm);
|
---|
14855 | case 4: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
14856 | case 5:
|
---|
14857 | if (bRm == 0xe9)
|
---|
14858 | return FNIEMOP_CALL(iemOp_fucompp);
|
---|
14859 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
14860 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
14861 | case 7: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
14862 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
14863 | }
|
---|
14864 | }
|
---|
14865 | else
|
---|
14866 | {
|
---|
14867 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
14868 | {
|
---|
14869 | case 0: return FNIEMOP_CALL_1(iemOp_fiadd_m32i, bRm);
|
---|
14870 | case 1: return FNIEMOP_CALL_1(iemOp_fimul_m32i, bRm);
|
---|
14871 | case 2: return FNIEMOP_CALL_1(iemOp_ficom_m32i, bRm);
|
---|
14872 | case 3: return FNIEMOP_CALL_1(iemOp_ficomp_m32i, bRm);
|
---|
14873 | case 4: return FNIEMOP_CALL_1(iemOp_fisub_m32i, bRm);
|
---|
14874 | case 5: return FNIEMOP_CALL_1(iemOp_fisubr_m32i, bRm);
|
---|
14875 | case 6: return FNIEMOP_CALL_1(iemOp_fidiv_m32i, bRm);
|
---|
14876 | case 7: return FNIEMOP_CALL_1(iemOp_fidivr_m32i, bRm);
|
---|
14877 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
14878 | }
|
---|
14879 | }
|
---|
14880 | }
|
---|
14881 |
|
---|
14882 |
|
---|
14883 | /** Opcode 0xdb !11/0. */
|
---|
14884 | FNIEMOP_DEF_1(iemOp_fild_m32i, uint8_t, bRm)
|
---|
14885 | {
|
---|
14886 | IEMOP_MNEMONIC("fild m32i");
|
---|
14887 |
|
---|
14888 | IEM_MC_BEGIN(2, 3);
|
---|
14889 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
14890 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
14891 | IEM_MC_LOCAL(int32_t, i32Val);
|
---|
14892 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
14893 | IEM_MC_ARG_LOCAL_REF(int32_t const *, pi32Val, i32Val, 1);
|
---|
14894 |
|
---|
14895 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
14896 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14897 |
|
---|
14898 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14899 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14900 | IEM_MC_FETCH_MEM_I32(i32Val, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14901 |
|
---|
14902 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14903 | IEM_MC_IF_FPUREG_IS_EMPTY(7)
|
---|
14904 | IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fild_i32_to_r80, pFpuRes, pi32Val);
|
---|
14905 | IEM_MC_PUSH_FPU_RESULT_MEM_OP(FpuRes, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14906 | IEM_MC_ELSE()
|
---|
14907 | IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
14908 | IEM_MC_ENDIF();
|
---|
14909 | IEM_MC_ADVANCE_RIP();
|
---|
14910 |
|
---|
14911 | IEM_MC_END();
|
---|
14912 | return VINF_SUCCESS;
|
---|
14913 | }
|
---|
14914 |
|
---|
14915 |
|
---|
14916 | /** Opcode 0xdb !11/1. */
|
---|
14917 | FNIEMOP_DEF_1(iemOp_fisttp_m32i, uint8_t, bRm)
|
---|
14918 | {
|
---|
14919 | IEMOP_MNEMONIC("fisttp m32i");
|
---|
14920 | IEM_MC_BEGIN(3, 2);
|
---|
14921 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
14922 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
14923 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
14924 | IEM_MC_ARG(int32_t *, pi32Dst, 1);
|
---|
14925 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
14926 |
|
---|
14927 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
14928 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14929 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14930 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14931 |
|
---|
14932 | IEM_MC_MEM_MAP(pi32Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
14933 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14934 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
14935 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fistt_r80_to_i32, pu16Fsw, pi32Dst, pr80Value);
|
---|
14936 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pi32Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
14937 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
14938 | IEM_MC_ELSE()
|
---|
14939 | IEM_MC_IF_FCW_IM()
|
---|
14940 | IEM_MC_STORE_MEM_I32_CONST_BY_REF(pi32Dst, INT32_MIN /* (integer indefinite) */);
|
---|
14941 | IEM_MC_MEM_COMMIT_AND_UNMAP(pi32Dst, IEM_ACCESS_DATA_W);
|
---|
14942 | IEM_MC_ENDIF();
|
---|
14943 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
14944 | IEM_MC_ENDIF();
|
---|
14945 | IEM_MC_ADVANCE_RIP();
|
---|
14946 |
|
---|
14947 | IEM_MC_END();
|
---|
14948 | return VINF_SUCCESS;
|
---|
14949 | }
|
---|
14950 |
|
---|
14951 |
|
---|
14952 | /** Opcode 0xdb !11/2. */
|
---|
14953 | FNIEMOP_DEF_1(iemOp_fist_m32i, uint8_t, bRm)
|
---|
14954 | {
|
---|
14955 | IEMOP_MNEMONIC("fist m32i");
|
---|
14956 | IEM_MC_BEGIN(3, 2);
|
---|
14957 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
14958 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
14959 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
14960 | IEM_MC_ARG(int32_t *, pi32Dst, 1);
|
---|
14961 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
14962 |
|
---|
14963 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
14964 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
14965 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
14966 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
14967 |
|
---|
14968 | IEM_MC_MEM_MAP(pi32Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
14969 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
14970 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
14971 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i32, pu16Fsw, pi32Dst, pr80Value);
|
---|
14972 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pi32Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
14973 | IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
14974 | IEM_MC_ELSE()
|
---|
14975 | IEM_MC_IF_FCW_IM()
|
---|
14976 | IEM_MC_STORE_MEM_I32_CONST_BY_REF(pi32Dst, INT32_MIN /* (integer indefinite) */);
|
---|
14977 | IEM_MC_MEM_COMMIT_AND_UNMAP(pi32Dst, IEM_ACCESS_DATA_W);
|
---|
14978 | IEM_MC_ENDIF();
|
---|
14979 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
14980 | IEM_MC_ENDIF();
|
---|
14981 | IEM_MC_ADVANCE_RIP();
|
---|
14982 |
|
---|
14983 | IEM_MC_END();
|
---|
14984 | return VINF_SUCCESS;
|
---|
14985 | }
|
---|
14986 |
|
---|
14987 |
|
---|
14988 | /** Opcode 0xdb !11/3. */
|
---|
14989 | FNIEMOP_DEF_1(iemOp_fistp_m32i, uint8_t, bRm)
|
---|
14990 | {
|
---|
14991 | IEMOP_MNEMONIC("fisttp m32i");
|
---|
14992 | IEM_MC_BEGIN(3, 2);
|
---|
14993 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
14994 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
14995 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
14996 | IEM_MC_ARG(int32_t *, pi32Dst, 1);
|
---|
14997 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
14998 |
|
---|
14999 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
15000 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15001 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15002 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15003 |
|
---|
15004 | IEM_MC_MEM_MAP(pi32Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
15005 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15006 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
15007 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i32, pu16Fsw, pi32Dst, pr80Value);
|
---|
15008 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pi32Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
15009 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15010 | IEM_MC_ELSE()
|
---|
15011 | IEM_MC_IF_FCW_IM()
|
---|
15012 | IEM_MC_STORE_MEM_I32_CONST_BY_REF(pi32Dst, INT32_MIN /* (integer indefinite) */);
|
---|
15013 | IEM_MC_MEM_COMMIT_AND_UNMAP(pi32Dst, IEM_ACCESS_DATA_W);
|
---|
15014 | IEM_MC_ENDIF();
|
---|
15015 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15016 | IEM_MC_ENDIF();
|
---|
15017 | IEM_MC_ADVANCE_RIP();
|
---|
15018 |
|
---|
15019 | IEM_MC_END();
|
---|
15020 | return VINF_SUCCESS;
|
---|
15021 | }
|
---|
15022 |
|
---|
15023 |
|
---|
15024 | /** Opcode 0xdb !11/5. */
|
---|
15025 | FNIEMOP_DEF_1(iemOp_fld_m80r, uint8_t, bRm)
|
---|
15026 | {
|
---|
15027 | IEMOP_MNEMONIC("fld m80r");
|
---|
15028 |
|
---|
15029 | IEM_MC_BEGIN(2, 3);
|
---|
15030 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
15031 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
15032 | IEM_MC_LOCAL(RTFLOAT80U, r80Val);
|
---|
15033 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
15034 | IEM_MC_ARG_LOCAL_REF(PCRTFLOAT80U, pr80Val, r80Val, 1);
|
---|
15035 |
|
---|
15036 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
15037 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15038 |
|
---|
15039 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15040 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15041 | IEM_MC_FETCH_MEM_R80(r80Val, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15042 |
|
---|
15043 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15044 | IEM_MC_IF_FPUREG_IS_EMPTY(7)
|
---|
15045 | IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fld_r80_from_r80, pFpuRes, pr80Val);
|
---|
15046 | IEM_MC_PUSH_FPU_RESULT_MEM_OP(FpuRes, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15047 | IEM_MC_ELSE()
|
---|
15048 | IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15049 | IEM_MC_ENDIF();
|
---|
15050 | IEM_MC_ADVANCE_RIP();
|
---|
15051 |
|
---|
15052 | IEM_MC_END();
|
---|
15053 | return VINF_SUCCESS;
|
---|
15054 | }
|
---|
15055 |
|
---|
15056 |
|
---|
15057 | /** Opcode 0xdb !11/7. */
|
---|
15058 | FNIEMOP_DEF_1(iemOp_fstp_m80r, uint8_t, bRm)
|
---|
15059 | {
|
---|
15060 | IEMOP_MNEMONIC("fstp m80r");
|
---|
15061 | IEM_MC_BEGIN(3, 2);
|
---|
15062 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
15063 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
15064 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
15065 | IEM_MC_ARG(PRTFLOAT80U, pr80Dst, 1);
|
---|
15066 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
15067 |
|
---|
15068 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
15069 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15070 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15071 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15072 |
|
---|
15073 | IEM_MC_MEM_MAP(pr80Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
15074 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15075 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
15076 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r80, pu16Fsw, pr80Dst, pr80Value);
|
---|
15077 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pr80Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
15078 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15079 | IEM_MC_ELSE()
|
---|
15080 | IEM_MC_IF_FCW_IM()
|
---|
15081 | IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(pr80Dst);
|
---|
15082 | IEM_MC_MEM_COMMIT_AND_UNMAP(pr80Dst, IEM_ACCESS_DATA_W);
|
---|
15083 | IEM_MC_ENDIF();
|
---|
15084 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15085 | IEM_MC_ENDIF();
|
---|
15086 | IEM_MC_ADVANCE_RIP();
|
---|
15087 |
|
---|
15088 | IEM_MC_END();
|
---|
15089 | return VINF_SUCCESS;
|
---|
15090 | }
|
---|
15091 |
|
---|
15092 |
|
---|
15093 | /** Opcode 0xdb 11/0. */
|
---|
15094 | FNIEMOP_DEF_1(iemOp_fcmovnb_stN, uint8_t, bRm)
|
---|
15095 | {
|
---|
15096 | IEMOP_MNEMONIC("fcmovnb st0,stN");
|
---|
15097 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15098 |
|
---|
15099 | IEM_MC_BEGIN(0, 1);
|
---|
15100 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80ValueN);
|
---|
15101 |
|
---|
15102 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15103 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15104 |
|
---|
15105 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15106 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0)
|
---|
15107 | IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_CF)
|
---|
15108 | IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN);
|
---|
15109 | IEM_MC_ENDIF();
|
---|
15110 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
15111 | IEM_MC_ELSE()
|
---|
15112 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
15113 | IEM_MC_ENDIF();
|
---|
15114 | IEM_MC_ADVANCE_RIP();
|
---|
15115 |
|
---|
15116 | IEM_MC_END();
|
---|
15117 | return VINF_SUCCESS;
|
---|
15118 | }
|
---|
15119 |
|
---|
15120 |
|
---|
15121 | /** Opcode 0xdb 11/1. */
|
---|
15122 | FNIEMOP_DEF_1(iemOp_fcmovne_stN, uint8_t, bRm)
|
---|
15123 | {
|
---|
15124 | IEMOP_MNEMONIC("fcmovne st0,stN");
|
---|
15125 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15126 |
|
---|
15127 | IEM_MC_BEGIN(0, 1);
|
---|
15128 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80ValueN);
|
---|
15129 |
|
---|
15130 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15131 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15132 |
|
---|
15133 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15134 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0)
|
---|
15135 | IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF)
|
---|
15136 | IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN);
|
---|
15137 | IEM_MC_ENDIF();
|
---|
15138 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
15139 | IEM_MC_ELSE()
|
---|
15140 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
15141 | IEM_MC_ENDIF();
|
---|
15142 | IEM_MC_ADVANCE_RIP();
|
---|
15143 |
|
---|
15144 | IEM_MC_END();
|
---|
15145 | return VINF_SUCCESS;
|
---|
15146 | }
|
---|
15147 |
|
---|
15148 |
|
---|
15149 | /** Opcode 0xdb 11/2. */
|
---|
15150 | FNIEMOP_DEF_1(iemOp_fcmovnbe_stN, uint8_t, bRm)
|
---|
15151 | {
|
---|
15152 | IEMOP_MNEMONIC("fcmovnbe st0,stN");
|
---|
15153 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15154 |
|
---|
15155 | IEM_MC_BEGIN(0, 1);
|
---|
15156 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80ValueN);
|
---|
15157 |
|
---|
15158 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15159 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15160 |
|
---|
15161 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15162 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0)
|
---|
15163 | IEM_MC_IF_EFL_NO_BITS_SET(X86_EFL_CF | X86_EFL_ZF)
|
---|
15164 | IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN);
|
---|
15165 | IEM_MC_ENDIF();
|
---|
15166 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
15167 | IEM_MC_ELSE()
|
---|
15168 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
15169 | IEM_MC_ENDIF();
|
---|
15170 | IEM_MC_ADVANCE_RIP();
|
---|
15171 |
|
---|
15172 | IEM_MC_END();
|
---|
15173 | return VINF_SUCCESS;
|
---|
15174 | }
|
---|
15175 |
|
---|
15176 |
|
---|
15177 | /** Opcode 0xdb 11/3. */
|
---|
15178 | FNIEMOP_DEF_1(iemOp_fcmovnnu_stN, uint8_t, bRm)
|
---|
15179 | {
|
---|
15180 | IEMOP_MNEMONIC("fcmovnnu st0,stN");
|
---|
15181 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15182 |
|
---|
15183 | IEM_MC_BEGIN(0, 1);
|
---|
15184 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80ValueN);
|
---|
15185 |
|
---|
15186 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15187 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15188 |
|
---|
15189 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15190 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, bRm & X86_MODRM_RM_MASK, 0)
|
---|
15191 | IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_PF)
|
---|
15192 | IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN);
|
---|
15193 | IEM_MC_ENDIF();
|
---|
15194 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
15195 | IEM_MC_ELSE()
|
---|
15196 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
15197 | IEM_MC_ENDIF();
|
---|
15198 | IEM_MC_ADVANCE_RIP();
|
---|
15199 |
|
---|
15200 | IEM_MC_END();
|
---|
15201 | return VINF_SUCCESS;
|
---|
15202 | }
|
---|
15203 |
|
---|
15204 |
|
---|
15205 | /** Opcode 0xdb 0xe0. */
|
---|
15206 | FNIEMOP_DEF(iemOp_fneni)
|
---|
15207 | {
|
---|
15208 | IEMOP_MNEMONIC("fneni (8087/ign)");
|
---|
15209 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15210 | IEM_MC_BEGIN(0,0);
|
---|
15211 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15212 | IEM_MC_ADVANCE_RIP();
|
---|
15213 | IEM_MC_END();
|
---|
15214 | return VINF_SUCCESS;
|
---|
15215 | }
|
---|
15216 |
|
---|
15217 |
|
---|
15218 | /** Opcode 0xdb 0xe1. */
|
---|
15219 | FNIEMOP_DEF(iemOp_fndisi)
|
---|
15220 | {
|
---|
15221 | IEMOP_MNEMONIC("fndisi (8087/ign)");
|
---|
15222 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15223 | IEM_MC_BEGIN(0,0);
|
---|
15224 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15225 | IEM_MC_ADVANCE_RIP();
|
---|
15226 | IEM_MC_END();
|
---|
15227 | return VINF_SUCCESS;
|
---|
15228 | }
|
---|
15229 |
|
---|
15230 |
|
---|
15231 | /** Opcode 0xdb 0xe2. */
|
---|
15232 | FNIEMOP_DEF(iemOp_fnclex)
|
---|
15233 | {
|
---|
15234 | IEMOP_MNEMONIC("fnclex");
|
---|
15235 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15236 |
|
---|
15237 | IEM_MC_BEGIN(0,0);
|
---|
15238 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15239 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
15240 | IEM_MC_CLEAR_FSW_EX();
|
---|
15241 | IEM_MC_ADVANCE_RIP();
|
---|
15242 | IEM_MC_END();
|
---|
15243 | return VINF_SUCCESS;
|
---|
15244 | }
|
---|
15245 |
|
---|
15246 |
|
---|
15247 | /** Opcode 0xdb 0xe3. */
|
---|
15248 | FNIEMOP_DEF(iemOp_fninit)
|
---|
15249 | {
|
---|
15250 | IEMOP_MNEMONIC("fninit");
|
---|
15251 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15252 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_finit, false /*fCheckXcpts*/);
|
---|
15253 | }
|
---|
15254 |
|
---|
15255 |
|
---|
15256 | /** Opcode 0xdb 0xe4. */
|
---|
15257 | FNIEMOP_DEF(iemOp_fnsetpm)
|
---|
15258 | {
|
---|
15259 | IEMOP_MNEMONIC("fnsetpm (80287/ign)"); /* set protected mode on fpu. */
|
---|
15260 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15261 | IEM_MC_BEGIN(0,0);
|
---|
15262 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15263 | IEM_MC_ADVANCE_RIP();
|
---|
15264 | IEM_MC_END();
|
---|
15265 | return VINF_SUCCESS;
|
---|
15266 | }
|
---|
15267 |
|
---|
15268 |
|
---|
15269 | /** Opcode 0xdb 0xe5. */
|
---|
15270 | FNIEMOP_DEF(iemOp_frstpm)
|
---|
15271 | {
|
---|
15272 | IEMOP_MNEMONIC("frstpm (80287XL/ign)"); /* reset pm, back to real mode. */
|
---|
15273 | #if 0 /* #UDs on newer CPUs */
|
---|
15274 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15275 | IEM_MC_BEGIN(0,0);
|
---|
15276 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15277 | IEM_MC_ADVANCE_RIP();
|
---|
15278 | IEM_MC_END();
|
---|
15279 | return VINF_SUCCESS;
|
---|
15280 | #else
|
---|
15281 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15282 | #endif
|
---|
15283 | }
|
---|
15284 |
|
---|
15285 |
|
---|
15286 | /** Opcode 0xdb 11/5. */
|
---|
15287 | FNIEMOP_DEF_1(iemOp_fucomi_stN, uint8_t, bRm)
|
---|
15288 | {
|
---|
15289 | IEMOP_MNEMONIC("fucomi st0,stN");
|
---|
15290 | return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, bRm & X86_MODRM_RM_MASK, iemAImpl_fucomi_r80_by_r80, false /*fPop*/);
|
---|
15291 | }
|
---|
15292 |
|
---|
15293 |
|
---|
15294 | /** Opcode 0xdb 11/6. */
|
---|
15295 | FNIEMOP_DEF_1(iemOp_fcomi_stN, uint8_t, bRm)
|
---|
15296 | {
|
---|
15297 | IEMOP_MNEMONIC("fcomi st0,stN");
|
---|
15298 | return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, bRm & X86_MODRM_RM_MASK, iemAImpl_fcomi_r80_by_r80, false /*fPop*/);
|
---|
15299 | }
|
---|
15300 |
|
---|
15301 |
|
---|
15302 | /** Opcode 0xdb. */
|
---|
15303 | FNIEMOP_DEF(iemOp_EscF3)
|
---|
15304 | {
|
---|
15305 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
15306 | pVCpu->iem.s.uFpuOpcode = RT_MAKE_U16(bRm, 0xdb & 0x7);
|
---|
15307 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
15308 | {
|
---|
15309 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
15310 | {
|
---|
15311 | case 0: return FNIEMOP_CALL_1(iemOp_fcmovnb_stN, bRm);
|
---|
15312 | case 1: return FNIEMOP_CALL_1(iemOp_fcmovne_stN, bRm);
|
---|
15313 | case 2: return FNIEMOP_CALL_1(iemOp_fcmovnbe_stN, bRm);
|
---|
15314 | case 3: return FNIEMOP_CALL_1(iemOp_fcmovnnu_stN, bRm);
|
---|
15315 | case 4:
|
---|
15316 | switch (bRm)
|
---|
15317 | {
|
---|
15318 | case 0xe0: return FNIEMOP_CALL(iemOp_fneni);
|
---|
15319 | case 0xe1: return FNIEMOP_CALL(iemOp_fndisi);
|
---|
15320 | case 0xe2: return FNIEMOP_CALL(iemOp_fnclex);
|
---|
15321 | case 0xe3: return FNIEMOP_CALL(iemOp_fninit);
|
---|
15322 | case 0xe4: return FNIEMOP_CALL(iemOp_fnsetpm);
|
---|
15323 | case 0xe5: return FNIEMOP_CALL(iemOp_frstpm);
|
---|
15324 | case 0xe6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15325 | case 0xe7: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15326 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
15327 | }
|
---|
15328 | break;
|
---|
15329 | case 5: return FNIEMOP_CALL_1(iemOp_fucomi_stN, bRm);
|
---|
15330 | case 6: return FNIEMOP_CALL_1(iemOp_fcomi_stN, bRm);
|
---|
15331 | case 7: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15332 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
15333 | }
|
---|
15334 | }
|
---|
15335 | else
|
---|
15336 | {
|
---|
15337 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
15338 | {
|
---|
15339 | case 0: return FNIEMOP_CALL_1(iemOp_fild_m32i, bRm);
|
---|
15340 | case 1: return FNIEMOP_CALL_1(iemOp_fisttp_m32i,bRm);
|
---|
15341 | case 2: return FNIEMOP_CALL_1(iemOp_fist_m32i, bRm);
|
---|
15342 | case 3: return FNIEMOP_CALL_1(iemOp_fistp_m32i, bRm);
|
---|
15343 | case 4: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15344 | case 5: return FNIEMOP_CALL_1(iemOp_fld_m80r, bRm);
|
---|
15345 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15346 | case 7: return FNIEMOP_CALL_1(iemOp_fstp_m80r, bRm);
|
---|
15347 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
15348 | }
|
---|
15349 | }
|
---|
15350 | }
|
---|
15351 |
|
---|
15352 |
|
---|
15353 | /**
|
---|
15354 | * Common worker for FPU instructions working on STn and ST0, and storing the
|
---|
15355 | * result in STn unless IE, DE or ZE was raised.
|
---|
15356 | *
|
---|
15357 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
15358 | */
|
---|
15359 | FNIEMOP_DEF_2(iemOpHlpFpu_stN_st0, uint8_t, bRm, PFNIEMAIMPLFPUR80, pfnAImpl)
|
---|
15360 | {
|
---|
15361 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15362 |
|
---|
15363 | IEM_MC_BEGIN(3, 1);
|
---|
15364 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
15365 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
15366 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
15367 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value2, 2);
|
---|
15368 |
|
---|
15369 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15370 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15371 |
|
---|
15372 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15373 | IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(pr80Value1, bRm & X86_MODRM_RM_MASK, pr80Value2, 0)
|
---|
15374 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pr80Value2);
|
---|
15375 | IEM_MC_STORE_FPU_RESULT(FpuRes, bRm & X86_MODRM_RM_MASK);
|
---|
15376 | IEM_MC_ELSE()
|
---|
15377 | IEM_MC_FPU_STACK_UNDERFLOW(bRm & X86_MODRM_RM_MASK);
|
---|
15378 | IEM_MC_ENDIF();
|
---|
15379 | IEM_MC_ADVANCE_RIP();
|
---|
15380 |
|
---|
15381 | IEM_MC_END();
|
---|
15382 | return VINF_SUCCESS;
|
---|
15383 | }
|
---|
15384 |
|
---|
15385 |
|
---|
15386 | /** Opcode 0xdc 11/0. */
|
---|
15387 | FNIEMOP_DEF_1(iemOp_fadd_stN_st0, uint8_t, bRm)
|
---|
15388 | {
|
---|
15389 | IEMOP_MNEMONIC("fadd stN,st0");
|
---|
15390 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0, bRm, iemAImpl_fadd_r80_by_r80);
|
---|
15391 | }
|
---|
15392 |
|
---|
15393 |
|
---|
15394 | /** Opcode 0xdc 11/1. */
|
---|
15395 | FNIEMOP_DEF_1(iemOp_fmul_stN_st0, uint8_t, bRm)
|
---|
15396 | {
|
---|
15397 | IEMOP_MNEMONIC("fmul stN,st0");
|
---|
15398 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0, bRm, iemAImpl_fmul_r80_by_r80);
|
---|
15399 | }
|
---|
15400 |
|
---|
15401 |
|
---|
15402 | /** Opcode 0xdc 11/4. */
|
---|
15403 | FNIEMOP_DEF_1(iemOp_fsubr_stN_st0, uint8_t, bRm)
|
---|
15404 | {
|
---|
15405 | IEMOP_MNEMONIC("fsubr stN,st0");
|
---|
15406 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0, bRm, iemAImpl_fsubr_r80_by_r80);
|
---|
15407 | }
|
---|
15408 |
|
---|
15409 |
|
---|
15410 | /** Opcode 0xdc 11/5. */
|
---|
15411 | FNIEMOP_DEF_1(iemOp_fsub_stN_st0, uint8_t, bRm)
|
---|
15412 | {
|
---|
15413 | IEMOP_MNEMONIC("fsub stN,st0");
|
---|
15414 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0, bRm, iemAImpl_fsub_r80_by_r80);
|
---|
15415 | }
|
---|
15416 |
|
---|
15417 |
|
---|
15418 | /** Opcode 0xdc 11/6. */
|
---|
15419 | FNIEMOP_DEF_1(iemOp_fdivr_stN_st0, uint8_t, bRm)
|
---|
15420 | {
|
---|
15421 | IEMOP_MNEMONIC("fdivr stN,st0");
|
---|
15422 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0, bRm, iemAImpl_fdivr_r80_by_r80);
|
---|
15423 | }
|
---|
15424 |
|
---|
15425 |
|
---|
15426 | /** Opcode 0xdc 11/7. */
|
---|
15427 | FNIEMOP_DEF_1(iemOp_fdiv_stN_st0, uint8_t, bRm)
|
---|
15428 | {
|
---|
15429 | IEMOP_MNEMONIC("fdiv stN,st0");
|
---|
15430 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0, bRm, iemAImpl_fdiv_r80_by_r80);
|
---|
15431 | }
|
---|
15432 |
|
---|
15433 |
|
---|
15434 | /**
|
---|
15435 | * Common worker for FPU instructions working on ST0 and a 64-bit floating point
|
---|
15436 | * memory operand, and storing the result in ST0.
|
---|
15437 | *
|
---|
15438 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
15439 | */
|
---|
15440 | FNIEMOP_DEF_2(iemOpHlpFpu_ST0_m64r, uint8_t, bRm, PFNIEMAIMPLFPUR64, pfnImpl)
|
---|
15441 | {
|
---|
15442 | IEM_MC_BEGIN(3, 3);
|
---|
15443 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
15444 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
15445 | IEM_MC_LOCAL(RTFLOAT64U, r64Factor2);
|
---|
15446 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
15447 | IEM_MC_ARG(PCRTFLOAT80U, pr80Factor1, 1);
|
---|
15448 | IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Factor2, r64Factor2, 2);
|
---|
15449 |
|
---|
15450 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
15451 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15452 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15453 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15454 |
|
---|
15455 | IEM_MC_FETCH_MEM_R64(r64Factor2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15456 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15457 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Factor1, 0)
|
---|
15458 | IEM_MC_CALL_FPU_AIMPL_3(pfnImpl, pFpuRes, pr80Factor1, pr64Factor2);
|
---|
15459 | IEM_MC_STORE_FPU_RESULT_MEM_OP(FpuRes, 0, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15460 | IEM_MC_ELSE()
|
---|
15461 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(0, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15462 | IEM_MC_ENDIF();
|
---|
15463 | IEM_MC_ADVANCE_RIP();
|
---|
15464 |
|
---|
15465 | IEM_MC_END();
|
---|
15466 | return VINF_SUCCESS;
|
---|
15467 | }
|
---|
15468 |
|
---|
15469 |
|
---|
15470 | /** Opcode 0xdc !11/0. */
|
---|
15471 | FNIEMOP_DEF_1(iemOp_fadd_m64r, uint8_t, bRm)
|
---|
15472 | {
|
---|
15473 | IEMOP_MNEMONIC("fadd m64r");
|
---|
15474 | return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fadd_r80_by_r64);
|
---|
15475 | }
|
---|
15476 |
|
---|
15477 |
|
---|
15478 | /** Opcode 0xdc !11/1. */
|
---|
15479 | FNIEMOP_DEF_1(iemOp_fmul_m64r, uint8_t, bRm)
|
---|
15480 | {
|
---|
15481 | IEMOP_MNEMONIC("fmul m64r");
|
---|
15482 | return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fmul_r80_by_r64);
|
---|
15483 | }
|
---|
15484 |
|
---|
15485 |
|
---|
15486 | /** Opcode 0xdc !11/2. */
|
---|
15487 | FNIEMOP_DEF_1(iemOp_fcom_m64r, uint8_t, bRm)
|
---|
15488 | {
|
---|
15489 | IEMOP_MNEMONIC("fcom st0,m64r");
|
---|
15490 |
|
---|
15491 | IEM_MC_BEGIN(3, 3);
|
---|
15492 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
15493 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
15494 | IEM_MC_LOCAL(RTFLOAT64U, r64Val2);
|
---|
15495 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
15496 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
15497 | IEM_MC_ARG_LOCAL_REF(PCRTFLOAT64U, pr64Val2, r64Val2, 2);
|
---|
15498 |
|
---|
15499 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
15500 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15501 |
|
---|
15502 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15503 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15504 | IEM_MC_FETCH_MEM_R64(r64Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15505 |
|
---|
15506 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15507 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
15508 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fcom_r80_by_r64, pu16Fsw, pr80Value1, pr64Val2);
|
---|
15509 | IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15510 | IEM_MC_ELSE()
|
---|
15511 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15512 | IEM_MC_ENDIF();
|
---|
15513 | IEM_MC_ADVANCE_RIP();
|
---|
15514 |
|
---|
15515 | IEM_MC_END();
|
---|
15516 | return VINF_SUCCESS;
|
---|
15517 | }
|
---|
15518 |
|
---|
15519 |
|
---|
15520 | /** Opcode 0xdc !11/3. */
|
---|
15521 | FNIEMOP_DEF_1(iemOp_fcomp_m64r, uint8_t, bRm)
|
---|
15522 | {
|
---|
15523 | IEMOP_MNEMONIC("fcomp st0,m64r");
|
---|
15524 |
|
---|
15525 | IEM_MC_BEGIN(3, 3);
|
---|
15526 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
15527 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
15528 | IEM_MC_LOCAL(RTFLOAT64U, r64Val2);
|
---|
15529 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
15530 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
15531 | IEM_MC_ARG_LOCAL_REF(PCRTFLOAT64U, pr64Val2, r64Val2, 2);
|
---|
15532 |
|
---|
15533 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
15534 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15535 |
|
---|
15536 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15537 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15538 | IEM_MC_FETCH_MEM_R64(r64Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15539 |
|
---|
15540 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15541 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
15542 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fcom_r80_by_r64, pu16Fsw, pr80Value1, pr64Val2);
|
---|
15543 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15544 | IEM_MC_ELSE()
|
---|
15545 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15546 | IEM_MC_ENDIF();
|
---|
15547 | IEM_MC_ADVANCE_RIP();
|
---|
15548 |
|
---|
15549 | IEM_MC_END();
|
---|
15550 | return VINF_SUCCESS;
|
---|
15551 | }
|
---|
15552 |
|
---|
15553 |
|
---|
15554 | /** Opcode 0xdc !11/4. */
|
---|
15555 | FNIEMOP_DEF_1(iemOp_fsub_m64r, uint8_t, bRm)
|
---|
15556 | {
|
---|
15557 | IEMOP_MNEMONIC("fsub m64r");
|
---|
15558 | return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fsub_r80_by_r64);
|
---|
15559 | }
|
---|
15560 |
|
---|
15561 |
|
---|
15562 | /** Opcode 0xdc !11/5. */
|
---|
15563 | FNIEMOP_DEF_1(iemOp_fsubr_m64r, uint8_t, bRm)
|
---|
15564 | {
|
---|
15565 | IEMOP_MNEMONIC("fsubr m64r");
|
---|
15566 | return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fsubr_r80_by_r64);
|
---|
15567 | }
|
---|
15568 |
|
---|
15569 |
|
---|
15570 | /** Opcode 0xdc !11/6. */
|
---|
15571 | FNIEMOP_DEF_1(iemOp_fdiv_m64r, uint8_t, bRm)
|
---|
15572 | {
|
---|
15573 | IEMOP_MNEMONIC("fdiv m64r");
|
---|
15574 | return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fdiv_r80_by_r64);
|
---|
15575 | }
|
---|
15576 |
|
---|
15577 |
|
---|
15578 | /** Opcode 0xdc !11/7. */
|
---|
15579 | FNIEMOP_DEF_1(iemOp_fdivr_m64r, uint8_t, bRm)
|
---|
15580 | {
|
---|
15581 | IEMOP_MNEMONIC("fdivr m64r");
|
---|
15582 | return FNIEMOP_CALL_2(iemOpHlpFpu_ST0_m64r, bRm, iemAImpl_fdivr_r80_by_r64);
|
---|
15583 | }
|
---|
15584 |
|
---|
15585 |
|
---|
15586 | /** Opcode 0xdc. */
|
---|
15587 | FNIEMOP_DEF(iemOp_EscF4)
|
---|
15588 | {
|
---|
15589 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
15590 | pVCpu->iem.s.uFpuOpcode = RT_MAKE_U16(bRm, 0xdc & 0x7);
|
---|
15591 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
15592 | {
|
---|
15593 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
15594 | {
|
---|
15595 | case 0: return FNIEMOP_CALL_1(iemOp_fadd_stN_st0, bRm);
|
---|
15596 | case 1: return FNIEMOP_CALL_1(iemOp_fmul_stN_st0, bRm);
|
---|
15597 | case 2: return FNIEMOP_CALL_1(iemOp_fcom_stN, bRm); /* Marked reserved, intel behavior is that of FCOM ST(i). */
|
---|
15598 | case 3: return FNIEMOP_CALL_1(iemOp_fcomp_stN, bRm); /* Marked reserved, intel behavior is that of FCOMP ST(i). */
|
---|
15599 | case 4: return FNIEMOP_CALL_1(iemOp_fsubr_stN_st0, bRm);
|
---|
15600 | case 5: return FNIEMOP_CALL_1(iemOp_fsub_stN_st0, bRm);
|
---|
15601 | case 6: return FNIEMOP_CALL_1(iemOp_fdivr_stN_st0, bRm);
|
---|
15602 | case 7: return FNIEMOP_CALL_1(iemOp_fdiv_stN_st0, bRm);
|
---|
15603 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
15604 | }
|
---|
15605 | }
|
---|
15606 | else
|
---|
15607 | {
|
---|
15608 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
15609 | {
|
---|
15610 | case 0: return FNIEMOP_CALL_1(iemOp_fadd_m64r, bRm);
|
---|
15611 | case 1: return FNIEMOP_CALL_1(iemOp_fmul_m64r, bRm);
|
---|
15612 | case 2: return FNIEMOP_CALL_1(iemOp_fcom_m64r, bRm);
|
---|
15613 | case 3: return FNIEMOP_CALL_1(iemOp_fcomp_m64r, bRm);
|
---|
15614 | case 4: return FNIEMOP_CALL_1(iemOp_fsub_m64r, bRm);
|
---|
15615 | case 5: return FNIEMOP_CALL_1(iemOp_fsubr_m64r, bRm);
|
---|
15616 | case 6: return FNIEMOP_CALL_1(iemOp_fdiv_m64r, bRm);
|
---|
15617 | case 7: return FNIEMOP_CALL_1(iemOp_fdivr_m64r, bRm);
|
---|
15618 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
15619 | }
|
---|
15620 | }
|
---|
15621 | }
|
---|
15622 |
|
---|
15623 |
|
---|
15624 | /** Opcode 0xdd !11/0.
|
---|
15625 | * @sa iemOp_fld_m32r */
|
---|
15626 | FNIEMOP_DEF_1(iemOp_fld_m64r, uint8_t, bRm)
|
---|
15627 | {
|
---|
15628 | IEMOP_MNEMONIC("fld m64r");
|
---|
15629 |
|
---|
15630 | IEM_MC_BEGIN(2, 3);
|
---|
15631 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
15632 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
15633 | IEM_MC_LOCAL(RTFLOAT64U, r64Val);
|
---|
15634 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
15635 | IEM_MC_ARG_LOCAL_REF(PCRTFLOAT64U, pr64Val, r64Val, 1);
|
---|
15636 |
|
---|
15637 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
15638 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15639 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15640 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15641 |
|
---|
15642 | IEM_MC_FETCH_MEM_R64(r64Val, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15643 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15644 | IEM_MC_IF_FPUREG_IS_EMPTY(7)
|
---|
15645 | IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fld_r64_to_r80, pFpuRes, pr64Val);
|
---|
15646 | IEM_MC_PUSH_FPU_RESULT_MEM_OP(FpuRes, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15647 | IEM_MC_ELSE()
|
---|
15648 | IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
15649 | IEM_MC_ENDIF();
|
---|
15650 | IEM_MC_ADVANCE_RIP();
|
---|
15651 |
|
---|
15652 | IEM_MC_END();
|
---|
15653 | return VINF_SUCCESS;
|
---|
15654 | }
|
---|
15655 |
|
---|
15656 |
|
---|
15657 | /** Opcode 0xdd !11/0. */
|
---|
15658 | FNIEMOP_DEF_1(iemOp_fisttp_m64i, uint8_t, bRm)
|
---|
15659 | {
|
---|
15660 | IEMOP_MNEMONIC("fisttp m64i");
|
---|
15661 | IEM_MC_BEGIN(3, 2);
|
---|
15662 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
15663 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
15664 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
15665 | IEM_MC_ARG(int64_t *, pi64Dst, 1);
|
---|
15666 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
15667 |
|
---|
15668 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
15669 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15670 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15671 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15672 |
|
---|
15673 | IEM_MC_MEM_MAP(pi64Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
15674 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15675 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
15676 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fistt_r80_to_i64, pu16Fsw, pi64Dst, pr80Value);
|
---|
15677 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pi64Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
15678 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15679 | IEM_MC_ELSE()
|
---|
15680 | IEM_MC_IF_FCW_IM()
|
---|
15681 | IEM_MC_STORE_MEM_I64_CONST_BY_REF(pi64Dst, INT64_MIN /* (integer indefinite) */);
|
---|
15682 | IEM_MC_MEM_COMMIT_AND_UNMAP(pi64Dst, IEM_ACCESS_DATA_W);
|
---|
15683 | IEM_MC_ENDIF();
|
---|
15684 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15685 | IEM_MC_ENDIF();
|
---|
15686 | IEM_MC_ADVANCE_RIP();
|
---|
15687 |
|
---|
15688 | IEM_MC_END();
|
---|
15689 | return VINF_SUCCESS;
|
---|
15690 | }
|
---|
15691 |
|
---|
15692 |
|
---|
15693 | /** Opcode 0xdd !11/0. */
|
---|
15694 | FNIEMOP_DEF_1(iemOp_fst_m64r, uint8_t, bRm)
|
---|
15695 | {
|
---|
15696 | IEMOP_MNEMONIC("fst m64r");
|
---|
15697 | IEM_MC_BEGIN(3, 2);
|
---|
15698 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
15699 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
15700 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
15701 | IEM_MC_ARG(PRTFLOAT64U, pr64Dst, 1);
|
---|
15702 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
15703 |
|
---|
15704 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
15705 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15706 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15707 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15708 |
|
---|
15709 | IEM_MC_MEM_MAP(pr64Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
15710 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15711 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
15712 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r64, pu16Fsw, pr64Dst, pr80Value);
|
---|
15713 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pr64Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
15714 | IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15715 | IEM_MC_ELSE()
|
---|
15716 | IEM_MC_IF_FCW_IM()
|
---|
15717 | IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(pr64Dst);
|
---|
15718 | IEM_MC_MEM_COMMIT_AND_UNMAP(pr64Dst, IEM_ACCESS_DATA_W);
|
---|
15719 | IEM_MC_ENDIF();
|
---|
15720 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15721 | IEM_MC_ENDIF();
|
---|
15722 | IEM_MC_ADVANCE_RIP();
|
---|
15723 |
|
---|
15724 | IEM_MC_END();
|
---|
15725 | return VINF_SUCCESS;
|
---|
15726 | }
|
---|
15727 |
|
---|
15728 |
|
---|
15729 |
|
---|
15730 |
|
---|
15731 | /** Opcode 0xdd !11/0. */
|
---|
15732 | FNIEMOP_DEF_1(iemOp_fstp_m64r, uint8_t, bRm)
|
---|
15733 | {
|
---|
15734 | IEMOP_MNEMONIC("fstp m64r");
|
---|
15735 | IEM_MC_BEGIN(3, 2);
|
---|
15736 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
15737 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
15738 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
15739 | IEM_MC_ARG(PRTFLOAT64U, pr64Dst, 1);
|
---|
15740 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
15741 |
|
---|
15742 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
15743 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15744 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15745 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15746 |
|
---|
15747 | IEM_MC_MEM_MAP(pr64Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
15748 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15749 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
15750 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fst_r80_to_r64, pu16Fsw, pr64Dst, pr80Value);
|
---|
15751 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pr64Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
15752 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15753 | IEM_MC_ELSE()
|
---|
15754 | IEM_MC_IF_FCW_IM()
|
---|
15755 | IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(pr64Dst);
|
---|
15756 | IEM_MC_MEM_COMMIT_AND_UNMAP(pr64Dst, IEM_ACCESS_DATA_W);
|
---|
15757 | IEM_MC_ENDIF();
|
---|
15758 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
15759 | IEM_MC_ENDIF();
|
---|
15760 | IEM_MC_ADVANCE_RIP();
|
---|
15761 |
|
---|
15762 | IEM_MC_END();
|
---|
15763 | return VINF_SUCCESS;
|
---|
15764 | }
|
---|
15765 |
|
---|
15766 |
|
---|
15767 | /** Opcode 0xdd !11/0. */
|
---|
15768 | FNIEMOP_DEF_1(iemOp_frstor, uint8_t, bRm)
|
---|
15769 | {
|
---|
15770 | IEMOP_MNEMONIC("frstor m94/108byte");
|
---|
15771 | IEM_MC_BEGIN(3, 0);
|
---|
15772 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0);
|
---|
15773 | IEM_MC_ARG(uint8_t, iEffSeg, 1);
|
---|
15774 | IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 2);
|
---|
15775 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
15776 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15777 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15778 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
15779 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
15780 | IEM_MC_CALL_CIMPL_3(iemCImpl_frstor, enmEffOpSize, iEffSeg, GCPtrEffSrc);
|
---|
15781 | IEM_MC_END();
|
---|
15782 | return VINF_SUCCESS;
|
---|
15783 | }
|
---|
15784 |
|
---|
15785 |
|
---|
15786 | /** Opcode 0xdd !11/0. */
|
---|
15787 | FNIEMOP_DEF_1(iemOp_fnsave, uint8_t, bRm)
|
---|
15788 | {
|
---|
15789 | IEMOP_MNEMONIC("fnsave m94/108byte");
|
---|
15790 | IEM_MC_BEGIN(3, 0);
|
---|
15791 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0);
|
---|
15792 | IEM_MC_ARG(uint8_t, iEffSeg, 1);
|
---|
15793 | IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 2);
|
---|
15794 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
15795 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15796 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15797 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
15798 | IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
|
---|
15799 | IEM_MC_CALL_CIMPL_3(iemCImpl_fnsave, enmEffOpSize, iEffSeg, GCPtrEffDst);
|
---|
15800 | IEM_MC_END();
|
---|
15801 | return VINF_SUCCESS;
|
---|
15802 |
|
---|
15803 | }
|
---|
15804 |
|
---|
15805 | /** Opcode 0xdd !11/0. */
|
---|
15806 | FNIEMOP_DEF_1(iemOp_fnstsw, uint8_t, bRm)
|
---|
15807 | {
|
---|
15808 | IEMOP_MNEMONIC("fnstsw m16");
|
---|
15809 |
|
---|
15810 | IEM_MC_BEGIN(0, 2);
|
---|
15811 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
15812 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
15813 |
|
---|
15814 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
15815 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15816 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15817 |
|
---|
15818 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
15819 | IEM_MC_FETCH_FSW(u16Tmp);
|
---|
15820 | IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tmp);
|
---|
15821 | IEM_MC_ADVANCE_RIP();
|
---|
15822 |
|
---|
15823 | /** @todo Debug / drop a hint to the verifier that things may differ
|
---|
15824 | * from REM. Seen 0x4020 (iem) vs 0x4000 (rem) at 0008:801c6b88 booting
|
---|
15825 | * NT4SP1. (X86_FSW_PE) */
|
---|
15826 | IEM_MC_END();
|
---|
15827 | return VINF_SUCCESS;
|
---|
15828 | }
|
---|
15829 |
|
---|
15830 |
|
---|
15831 | /** Opcode 0xdd 11/0. */
|
---|
15832 | FNIEMOP_DEF_1(iemOp_ffree_stN, uint8_t, bRm)
|
---|
15833 | {
|
---|
15834 | IEMOP_MNEMONIC("ffree stN");
|
---|
15835 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15836 | /* Note! C0, C1, C2 and C3 are documented as undefined, we leave the
|
---|
15837 | unmodified. */
|
---|
15838 |
|
---|
15839 | IEM_MC_BEGIN(0, 0);
|
---|
15840 |
|
---|
15841 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15842 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15843 |
|
---|
15844 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
15845 | IEM_MC_FPU_STACK_FREE(bRm & X86_MODRM_RM_MASK);
|
---|
15846 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
15847 |
|
---|
15848 | IEM_MC_ADVANCE_RIP();
|
---|
15849 | IEM_MC_END();
|
---|
15850 | return VINF_SUCCESS;
|
---|
15851 | }
|
---|
15852 |
|
---|
15853 |
|
---|
15854 | /** Opcode 0xdd 11/1. */
|
---|
15855 | FNIEMOP_DEF_1(iemOp_fst_stN, uint8_t, bRm)
|
---|
15856 | {
|
---|
15857 | IEMOP_MNEMONIC("fst st0,stN");
|
---|
15858 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
15859 |
|
---|
15860 | IEM_MC_BEGIN(0, 2);
|
---|
15861 | IEM_MC_LOCAL(PCRTFLOAT80U, pr80Value);
|
---|
15862 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
15863 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
15864 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
15865 |
|
---|
15866 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
15867 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
15868 | IEM_MC_SET_FPU_RESULT(FpuRes, 0 /*FSW*/, pr80Value);
|
---|
15869 | IEM_MC_STORE_FPU_RESULT(FpuRes, bRm & X86_MODRM_RM_MASK);
|
---|
15870 | IEM_MC_ELSE()
|
---|
15871 | IEM_MC_FPU_STACK_UNDERFLOW(bRm & X86_MODRM_RM_MASK);
|
---|
15872 | IEM_MC_ENDIF();
|
---|
15873 |
|
---|
15874 | IEM_MC_ADVANCE_RIP();
|
---|
15875 | IEM_MC_END();
|
---|
15876 | return VINF_SUCCESS;
|
---|
15877 | }
|
---|
15878 |
|
---|
15879 |
|
---|
15880 | /** Opcode 0xdd 11/3. */
|
---|
15881 | FNIEMOP_DEF_1(iemOp_fucom_stN_st0, uint8_t, bRm)
|
---|
15882 | {
|
---|
15883 | IEMOP_MNEMONIC("fcom st0,stN");
|
---|
15884 | return FNIEMOP_CALL_2(iemOpHlpFpuNoStore_st0_stN, bRm, iemAImpl_fucom_r80_by_r80);
|
---|
15885 | }
|
---|
15886 |
|
---|
15887 |
|
---|
15888 | /** Opcode 0xdd 11/4. */
|
---|
15889 | FNIEMOP_DEF_1(iemOp_fucomp_stN, uint8_t, bRm)
|
---|
15890 | {
|
---|
15891 | IEMOP_MNEMONIC("fcomp st0,stN");
|
---|
15892 | return FNIEMOP_CALL_2(iemOpHlpFpuNoStore_st0_stN_pop, bRm, iemAImpl_fucom_r80_by_r80);
|
---|
15893 | }
|
---|
15894 |
|
---|
15895 |
|
---|
15896 | /** Opcode 0xdd. */
|
---|
15897 | FNIEMOP_DEF(iemOp_EscF5)
|
---|
15898 | {
|
---|
15899 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
15900 | pVCpu->iem.s.uFpuOpcode = RT_MAKE_U16(bRm, 0xdd & 0x7);
|
---|
15901 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
15902 | {
|
---|
15903 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
15904 | {
|
---|
15905 | case 0: return FNIEMOP_CALL_1(iemOp_ffree_stN, bRm);
|
---|
15906 | case 1: return FNIEMOP_CALL_1(iemOp_fxch_stN, bRm); /* Reserved, intel behavior is that of XCHG ST(i). */
|
---|
15907 | case 2: return FNIEMOP_CALL_1(iemOp_fst_stN, bRm);
|
---|
15908 | case 3: return FNIEMOP_CALL_1(iemOp_fstp_stN, bRm);
|
---|
15909 | case 4: return FNIEMOP_CALL_1(iemOp_fucom_stN_st0,bRm);
|
---|
15910 | case 5: return FNIEMOP_CALL_1(iemOp_fucomp_stN, bRm);
|
---|
15911 | case 6: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15912 | case 7: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15913 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
15914 | }
|
---|
15915 | }
|
---|
15916 | else
|
---|
15917 | {
|
---|
15918 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
15919 | {
|
---|
15920 | case 0: return FNIEMOP_CALL_1(iemOp_fld_m64r, bRm);
|
---|
15921 | case 1: return FNIEMOP_CALL_1(iemOp_fisttp_m64i, bRm);
|
---|
15922 | case 2: return FNIEMOP_CALL_1(iemOp_fst_m64r, bRm);
|
---|
15923 | case 3: return FNIEMOP_CALL_1(iemOp_fstp_m64r, bRm);
|
---|
15924 | case 4: return FNIEMOP_CALL_1(iemOp_frstor, bRm);
|
---|
15925 | case 5: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
15926 | case 6: return FNIEMOP_CALL_1(iemOp_fnsave, bRm);
|
---|
15927 | case 7: return FNIEMOP_CALL_1(iemOp_fnstsw, bRm);
|
---|
15928 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
15929 | }
|
---|
15930 | }
|
---|
15931 | }
|
---|
15932 |
|
---|
15933 |
|
---|
15934 | /** Opcode 0xde 11/0. */
|
---|
15935 | FNIEMOP_DEF_1(iemOp_faddp_stN_st0, uint8_t, bRm)
|
---|
15936 | {
|
---|
15937 | IEMOP_MNEMONIC("faddp stN,st0");
|
---|
15938 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, bRm, iemAImpl_fadd_r80_by_r80);
|
---|
15939 | }
|
---|
15940 |
|
---|
15941 |
|
---|
15942 | /** Opcode 0xde 11/0. */
|
---|
15943 | FNIEMOP_DEF_1(iemOp_fmulp_stN_st0, uint8_t, bRm)
|
---|
15944 | {
|
---|
15945 | IEMOP_MNEMONIC("fmulp stN,st0");
|
---|
15946 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, bRm, iemAImpl_fmul_r80_by_r80);
|
---|
15947 | }
|
---|
15948 |
|
---|
15949 |
|
---|
15950 | /** Opcode 0xde 0xd9. */
|
---|
15951 | FNIEMOP_DEF(iemOp_fcompp)
|
---|
15952 | {
|
---|
15953 | IEMOP_MNEMONIC("fucompp st0,stN");
|
---|
15954 | return FNIEMOP_CALL_1(iemOpHlpFpuNoStore_st0_stN_pop_pop, iemAImpl_fcom_r80_by_r80);
|
---|
15955 | }
|
---|
15956 |
|
---|
15957 |
|
---|
15958 | /** Opcode 0xde 11/4. */
|
---|
15959 | FNIEMOP_DEF_1(iemOp_fsubrp_stN_st0, uint8_t, bRm)
|
---|
15960 | {
|
---|
15961 | IEMOP_MNEMONIC("fsubrp stN,st0");
|
---|
15962 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, bRm, iemAImpl_fsubr_r80_by_r80);
|
---|
15963 | }
|
---|
15964 |
|
---|
15965 |
|
---|
15966 | /** Opcode 0xde 11/5. */
|
---|
15967 | FNIEMOP_DEF_1(iemOp_fsubp_stN_st0, uint8_t, bRm)
|
---|
15968 | {
|
---|
15969 | IEMOP_MNEMONIC("fsubp stN,st0");
|
---|
15970 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, bRm, iemAImpl_fsub_r80_by_r80);
|
---|
15971 | }
|
---|
15972 |
|
---|
15973 |
|
---|
15974 | /** Opcode 0xde 11/6. */
|
---|
15975 | FNIEMOP_DEF_1(iemOp_fdivrp_stN_st0, uint8_t, bRm)
|
---|
15976 | {
|
---|
15977 | IEMOP_MNEMONIC("fdivrp stN,st0");
|
---|
15978 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, bRm, iemAImpl_fdivr_r80_by_r80);
|
---|
15979 | }
|
---|
15980 |
|
---|
15981 |
|
---|
15982 | /** Opcode 0xde 11/7. */
|
---|
15983 | FNIEMOP_DEF_1(iemOp_fdivp_stN_st0, uint8_t, bRm)
|
---|
15984 | {
|
---|
15985 | IEMOP_MNEMONIC("fdivp stN,st0");
|
---|
15986 | return FNIEMOP_CALL_2(iemOpHlpFpu_stN_st0_pop, bRm, iemAImpl_fdiv_r80_by_r80);
|
---|
15987 | }
|
---|
15988 |
|
---|
15989 |
|
---|
15990 | /**
|
---|
15991 | * Common worker for FPU instructions working on ST0 and an m16i, and storing
|
---|
15992 | * the result in ST0.
|
---|
15993 | *
|
---|
15994 | * @param pfnAImpl Pointer to the instruction implementation (assembly).
|
---|
15995 | */
|
---|
15996 | FNIEMOP_DEF_2(iemOpHlpFpu_st0_m16i, uint8_t, bRm, PFNIEMAIMPLFPUI16, pfnAImpl)
|
---|
15997 | {
|
---|
15998 | IEM_MC_BEGIN(3, 3);
|
---|
15999 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
16000 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
16001 | IEM_MC_LOCAL(int16_t, i16Val2);
|
---|
16002 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
16003 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
16004 | IEM_MC_ARG_LOCAL_REF(int16_t const *, pi16Val2, i16Val2, 2);
|
---|
16005 |
|
---|
16006 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
16007 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16008 |
|
---|
16009 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16010 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16011 | IEM_MC_FETCH_MEM_I16(i16Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16012 |
|
---|
16013 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16014 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
16015 | IEM_MC_CALL_FPU_AIMPL_3(pfnAImpl, pFpuRes, pr80Value1, pi16Val2);
|
---|
16016 | IEM_MC_STORE_FPU_RESULT(FpuRes, 0);
|
---|
16017 | IEM_MC_ELSE()
|
---|
16018 | IEM_MC_FPU_STACK_UNDERFLOW(0);
|
---|
16019 | IEM_MC_ENDIF();
|
---|
16020 | IEM_MC_ADVANCE_RIP();
|
---|
16021 |
|
---|
16022 | IEM_MC_END();
|
---|
16023 | return VINF_SUCCESS;
|
---|
16024 | }
|
---|
16025 |
|
---|
16026 |
|
---|
16027 | /** Opcode 0xde !11/0. */
|
---|
16028 | FNIEMOP_DEF_1(iemOp_fiadd_m16i, uint8_t, bRm)
|
---|
16029 | {
|
---|
16030 | IEMOP_MNEMONIC("fiadd m16i");
|
---|
16031 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m16i, bRm, iemAImpl_fiadd_r80_by_i16);
|
---|
16032 | }
|
---|
16033 |
|
---|
16034 |
|
---|
16035 | /** Opcode 0xde !11/1. */
|
---|
16036 | FNIEMOP_DEF_1(iemOp_fimul_m16i, uint8_t, bRm)
|
---|
16037 | {
|
---|
16038 | IEMOP_MNEMONIC("fimul m16i");
|
---|
16039 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m16i, bRm, iemAImpl_fimul_r80_by_i16);
|
---|
16040 | }
|
---|
16041 |
|
---|
16042 |
|
---|
16043 | /** Opcode 0xde !11/2. */
|
---|
16044 | FNIEMOP_DEF_1(iemOp_ficom_m16i, uint8_t, bRm)
|
---|
16045 | {
|
---|
16046 | IEMOP_MNEMONIC("ficom st0,m16i");
|
---|
16047 |
|
---|
16048 | IEM_MC_BEGIN(3, 3);
|
---|
16049 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
16050 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
16051 | IEM_MC_LOCAL(int16_t, i16Val2);
|
---|
16052 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
16053 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
16054 | IEM_MC_ARG_LOCAL_REF(int16_t const *, pi16Val2, i16Val2, 2);
|
---|
16055 |
|
---|
16056 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
16057 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16058 |
|
---|
16059 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16060 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16061 | IEM_MC_FETCH_MEM_I16(i16Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16062 |
|
---|
16063 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16064 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
16065 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i16, pu16Fsw, pr80Value1, pi16Val2);
|
---|
16066 | IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16067 | IEM_MC_ELSE()
|
---|
16068 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16069 | IEM_MC_ENDIF();
|
---|
16070 | IEM_MC_ADVANCE_RIP();
|
---|
16071 |
|
---|
16072 | IEM_MC_END();
|
---|
16073 | return VINF_SUCCESS;
|
---|
16074 | }
|
---|
16075 |
|
---|
16076 |
|
---|
16077 | /** Opcode 0xde !11/3. */
|
---|
16078 | FNIEMOP_DEF_1(iemOp_ficomp_m16i, uint8_t, bRm)
|
---|
16079 | {
|
---|
16080 | IEMOP_MNEMONIC("ficomp st0,m16i");
|
---|
16081 |
|
---|
16082 | IEM_MC_BEGIN(3, 3);
|
---|
16083 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
16084 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
16085 | IEM_MC_LOCAL(int16_t, i16Val2);
|
---|
16086 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
16087 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value1, 1);
|
---|
16088 | IEM_MC_ARG_LOCAL_REF(int16_t const *, pi16Val2, i16Val2, 2);
|
---|
16089 |
|
---|
16090 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
16091 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16092 |
|
---|
16093 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16094 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16095 | IEM_MC_FETCH_MEM_I16(i16Val2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16096 |
|
---|
16097 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16098 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value1, 0)
|
---|
16099 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_ficom_r80_by_i16, pu16Fsw, pr80Value1, pi16Val2);
|
---|
16100 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16101 | IEM_MC_ELSE()
|
---|
16102 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16103 | IEM_MC_ENDIF();
|
---|
16104 | IEM_MC_ADVANCE_RIP();
|
---|
16105 |
|
---|
16106 | IEM_MC_END();
|
---|
16107 | return VINF_SUCCESS;
|
---|
16108 | }
|
---|
16109 |
|
---|
16110 |
|
---|
16111 | /** Opcode 0xde !11/4. */
|
---|
16112 | FNIEMOP_DEF_1(iemOp_fisub_m16i, uint8_t, bRm)
|
---|
16113 | {
|
---|
16114 | IEMOP_MNEMONIC("fisub m16i");
|
---|
16115 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m16i, bRm, iemAImpl_fisub_r80_by_i16);
|
---|
16116 | }
|
---|
16117 |
|
---|
16118 |
|
---|
16119 | /** Opcode 0xde !11/5. */
|
---|
16120 | FNIEMOP_DEF_1(iemOp_fisubr_m16i, uint8_t, bRm)
|
---|
16121 | {
|
---|
16122 | IEMOP_MNEMONIC("fisubr m16i");
|
---|
16123 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m16i, bRm, iemAImpl_fisubr_r80_by_i16);
|
---|
16124 | }
|
---|
16125 |
|
---|
16126 |
|
---|
16127 | /** Opcode 0xde !11/6. */
|
---|
16128 | FNIEMOP_DEF_1(iemOp_fidiv_m16i, uint8_t, bRm)
|
---|
16129 | {
|
---|
16130 | IEMOP_MNEMONIC("fiadd m16i");
|
---|
16131 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m16i, bRm, iemAImpl_fidiv_r80_by_i16);
|
---|
16132 | }
|
---|
16133 |
|
---|
16134 |
|
---|
16135 | /** Opcode 0xde !11/7. */
|
---|
16136 | FNIEMOP_DEF_1(iemOp_fidivr_m16i, uint8_t, bRm)
|
---|
16137 | {
|
---|
16138 | IEMOP_MNEMONIC("fiadd m16i");
|
---|
16139 | return FNIEMOP_CALL_2(iemOpHlpFpu_st0_m16i, bRm, iemAImpl_fidivr_r80_by_i16);
|
---|
16140 | }
|
---|
16141 |
|
---|
16142 |
|
---|
16143 | /** Opcode 0xde. */
|
---|
16144 | FNIEMOP_DEF(iemOp_EscF6)
|
---|
16145 | {
|
---|
16146 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
16147 | pVCpu->iem.s.uFpuOpcode = RT_MAKE_U16(bRm, 0xde & 0x7);
|
---|
16148 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
16149 | {
|
---|
16150 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
16151 | {
|
---|
16152 | case 0: return FNIEMOP_CALL_1(iemOp_faddp_stN_st0, bRm);
|
---|
16153 | case 1: return FNIEMOP_CALL_1(iemOp_fmulp_stN_st0, bRm);
|
---|
16154 | case 2: return FNIEMOP_CALL_1(iemOp_fcomp_stN, bRm);
|
---|
16155 | case 3: if (bRm == 0xd9)
|
---|
16156 | return FNIEMOP_CALL(iemOp_fcompp);
|
---|
16157 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
16158 | case 4: return FNIEMOP_CALL_1(iemOp_fsubrp_stN_st0, bRm);
|
---|
16159 | case 5: return FNIEMOP_CALL_1(iemOp_fsubp_stN_st0, bRm);
|
---|
16160 | case 6: return FNIEMOP_CALL_1(iemOp_fdivrp_stN_st0, bRm);
|
---|
16161 | case 7: return FNIEMOP_CALL_1(iemOp_fdivp_stN_st0, bRm);
|
---|
16162 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16163 | }
|
---|
16164 | }
|
---|
16165 | else
|
---|
16166 | {
|
---|
16167 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
16168 | {
|
---|
16169 | case 0: return FNIEMOP_CALL_1(iemOp_fiadd_m16i, bRm);
|
---|
16170 | case 1: return FNIEMOP_CALL_1(iemOp_fimul_m16i, bRm);
|
---|
16171 | case 2: return FNIEMOP_CALL_1(iemOp_ficom_m16i, bRm);
|
---|
16172 | case 3: return FNIEMOP_CALL_1(iemOp_ficomp_m16i, bRm);
|
---|
16173 | case 4: return FNIEMOP_CALL_1(iemOp_fisub_m16i, bRm);
|
---|
16174 | case 5: return FNIEMOP_CALL_1(iemOp_fisubr_m16i, bRm);
|
---|
16175 | case 6: return FNIEMOP_CALL_1(iemOp_fidiv_m16i, bRm);
|
---|
16176 | case 7: return FNIEMOP_CALL_1(iemOp_fidivr_m16i, bRm);
|
---|
16177 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16178 | }
|
---|
16179 | }
|
---|
16180 | }
|
---|
16181 |
|
---|
16182 |
|
---|
16183 | /** Opcode 0xdf 11/0.
|
---|
16184 | * Undocument instruction, assumed to work like ffree + fincstp. */
|
---|
16185 | FNIEMOP_DEF_1(iemOp_ffreep_stN, uint8_t, bRm)
|
---|
16186 | {
|
---|
16187 | IEMOP_MNEMONIC("ffreep stN");
|
---|
16188 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16189 |
|
---|
16190 | IEM_MC_BEGIN(0, 0);
|
---|
16191 |
|
---|
16192 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16193 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16194 |
|
---|
16195 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
|
---|
16196 | IEM_MC_FPU_STACK_FREE(bRm & X86_MODRM_RM_MASK);
|
---|
16197 | IEM_MC_FPU_STACK_INC_TOP();
|
---|
16198 | IEM_MC_UPDATE_FPU_OPCODE_IP();
|
---|
16199 |
|
---|
16200 | IEM_MC_ADVANCE_RIP();
|
---|
16201 | IEM_MC_END();
|
---|
16202 | return VINF_SUCCESS;
|
---|
16203 | }
|
---|
16204 |
|
---|
16205 |
|
---|
16206 | /** Opcode 0xdf 0xe0. */
|
---|
16207 | FNIEMOP_DEF(iemOp_fnstsw_ax)
|
---|
16208 | {
|
---|
16209 | IEMOP_MNEMONIC("fnstsw ax");
|
---|
16210 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16211 |
|
---|
16212 | IEM_MC_BEGIN(0, 1);
|
---|
16213 | IEM_MC_LOCAL(uint16_t, u16Tmp);
|
---|
16214 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16215 | IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
|
---|
16216 | IEM_MC_FETCH_FSW(u16Tmp);
|
---|
16217 | IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp);
|
---|
16218 | IEM_MC_ADVANCE_RIP();
|
---|
16219 | IEM_MC_END();
|
---|
16220 | return VINF_SUCCESS;
|
---|
16221 | }
|
---|
16222 |
|
---|
16223 |
|
---|
16224 | /** Opcode 0xdf 11/5. */
|
---|
16225 | FNIEMOP_DEF_1(iemOp_fucomip_st0_stN, uint8_t, bRm)
|
---|
16226 | {
|
---|
16227 | IEMOP_MNEMONIC("fcomip st0,stN");
|
---|
16228 | return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, bRm & X86_MODRM_RM_MASK, iemAImpl_fcomi_r80_by_r80, true /*fPop*/);
|
---|
16229 | }
|
---|
16230 |
|
---|
16231 |
|
---|
16232 | /** Opcode 0xdf 11/6. */
|
---|
16233 | FNIEMOP_DEF_1(iemOp_fcomip_st0_stN, uint8_t, bRm)
|
---|
16234 | {
|
---|
16235 | IEMOP_MNEMONIC("fcomip st0,stN");
|
---|
16236 | return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, bRm & X86_MODRM_RM_MASK, iemAImpl_fcomi_r80_by_r80, true /*fPop*/);
|
---|
16237 | }
|
---|
16238 |
|
---|
16239 |
|
---|
16240 | /** Opcode 0xdf !11/0. */
|
---|
16241 | FNIEMOP_DEF_1(iemOp_fild_m16i, uint8_t, bRm)
|
---|
16242 | {
|
---|
16243 | IEMOP_MNEMONIC("fild m16i");
|
---|
16244 |
|
---|
16245 | IEM_MC_BEGIN(2, 3);
|
---|
16246 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
16247 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
16248 | IEM_MC_LOCAL(int16_t, i16Val);
|
---|
16249 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
16250 | IEM_MC_ARG_LOCAL_REF(int16_t const *, pi16Val, i16Val, 1);
|
---|
16251 |
|
---|
16252 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
16253 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16254 |
|
---|
16255 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16256 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16257 | IEM_MC_FETCH_MEM_I16(i16Val, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16258 |
|
---|
16259 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16260 | IEM_MC_IF_FPUREG_IS_EMPTY(7)
|
---|
16261 | IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fild_i16_to_r80, pFpuRes, pi16Val);
|
---|
16262 | IEM_MC_PUSH_FPU_RESULT_MEM_OP(FpuRes, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16263 | IEM_MC_ELSE()
|
---|
16264 | IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16265 | IEM_MC_ENDIF();
|
---|
16266 | IEM_MC_ADVANCE_RIP();
|
---|
16267 |
|
---|
16268 | IEM_MC_END();
|
---|
16269 | return VINF_SUCCESS;
|
---|
16270 | }
|
---|
16271 |
|
---|
16272 |
|
---|
16273 | /** Opcode 0xdf !11/1. */
|
---|
16274 | FNIEMOP_DEF_1(iemOp_fisttp_m16i, uint8_t, bRm)
|
---|
16275 | {
|
---|
16276 | IEMOP_MNEMONIC("fisttp m16i");
|
---|
16277 | IEM_MC_BEGIN(3, 2);
|
---|
16278 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
16279 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
16280 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
16281 | IEM_MC_ARG(int16_t *, pi16Dst, 1);
|
---|
16282 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
16283 |
|
---|
16284 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
16285 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16286 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16287 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16288 |
|
---|
16289 | IEM_MC_MEM_MAP(pi16Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
16290 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16291 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
16292 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fistt_r80_to_i16, pu16Fsw, pi16Dst, pr80Value);
|
---|
16293 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pi16Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
16294 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
16295 | IEM_MC_ELSE()
|
---|
16296 | IEM_MC_IF_FCW_IM()
|
---|
16297 | IEM_MC_STORE_MEM_I16_CONST_BY_REF(pi16Dst, INT16_MIN /* (integer indefinite) */);
|
---|
16298 | IEM_MC_MEM_COMMIT_AND_UNMAP(pi16Dst, IEM_ACCESS_DATA_W);
|
---|
16299 | IEM_MC_ENDIF();
|
---|
16300 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
16301 | IEM_MC_ENDIF();
|
---|
16302 | IEM_MC_ADVANCE_RIP();
|
---|
16303 |
|
---|
16304 | IEM_MC_END();
|
---|
16305 | return VINF_SUCCESS;
|
---|
16306 | }
|
---|
16307 |
|
---|
16308 |
|
---|
16309 | /** Opcode 0xdf !11/2. */
|
---|
16310 | FNIEMOP_DEF_1(iemOp_fist_m16i, uint8_t, bRm)
|
---|
16311 | {
|
---|
16312 | IEMOP_MNEMONIC("fistp m16i");
|
---|
16313 | IEM_MC_BEGIN(3, 2);
|
---|
16314 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
16315 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
16316 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
16317 | IEM_MC_ARG(int16_t *, pi16Dst, 1);
|
---|
16318 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
16319 |
|
---|
16320 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
16321 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16322 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16323 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16324 |
|
---|
16325 | IEM_MC_MEM_MAP(pi16Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
16326 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16327 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
16328 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i16, pu16Fsw, pi16Dst, pr80Value);
|
---|
16329 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pi16Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
16330 | IEM_MC_UPDATE_FSW_WITH_MEM_OP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
16331 | IEM_MC_ELSE()
|
---|
16332 | IEM_MC_IF_FCW_IM()
|
---|
16333 | IEM_MC_STORE_MEM_I16_CONST_BY_REF(pi16Dst, INT16_MIN /* (integer indefinite) */);
|
---|
16334 | IEM_MC_MEM_COMMIT_AND_UNMAP(pi16Dst, IEM_ACCESS_DATA_W);
|
---|
16335 | IEM_MC_ENDIF();
|
---|
16336 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
16337 | IEM_MC_ENDIF();
|
---|
16338 | IEM_MC_ADVANCE_RIP();
|
---|
16339 |
|
---|
16340 | IEM_MC_END();
|
---|
16341 | return VINF_SUCCESS;
|
---|
16342 | }
|
---|
16343 |
|
---|
16344 |
|
---|
16345 | /** Opcode 0xdf !11/3. */
|
---|
16346 | FNIEMOP_DEF_1(iemOp_fistp_m16i, uint8_t, bRm)
|
---|
16347 | {
|
---|
16348 | IEMOP_MNEMONIC("fistp m16i");
|
---|
16349 | IEM_MC_BEGIN(3, 2);
|
---|
16350 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
16351 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
16352 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
16353 | IEM_MC_ARG(int16_t *, pi16Dst, 1);
|
---|
16354 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
16355 |
|
---|
16356 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
16357 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16358 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16359 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16360 |
|
---|
16361 | IEM_MC_MEM_MAP(pi16Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
16362 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16363 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
16364 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i16, pu16Fsw, pi16Dst, pr80Value);
|
---|
16365 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pi16Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
16366 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
16367 | IEM_MC_ELSE()
|
---|
16368 | IEM_MC_IF_FCW_IM()
|
---|
16369 | IEM_MC_STORE_MEM_I16_CONST_BY_REF(pi16Dst, INT16_MIN /* (integer indefinite) */);
|
---|
16370 | IEM_MC_MEM_COMMIT_AND_UNMAP(pi16Dst, IEM_ACCESS_DATA_W);
|
---|
16371 | IEM_MC_ENDIF();
|
---|
16372 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
16373 | IEM_MC_ENDIF();
|
---|
16374 | IEM_MC_ADVANCE_RIP();
|
---|
16375 |
|
---|
16376 | IEM_MC_END();
|
---|
16377 | return VINF_SUCCESS;
|
---|
16378 | }
|
---|
16379 |
|
---|
16380 |
|
---|
16381 | /** Opcode 0xdf !11/4. */
|
---|
16382 | FNIEMOP_STUB_1(iemOp_fbld_m80d, uint8_t, bRm);
|
---|
16383 |
|
---|
16384 |
|
---|
16385 | /** Opcode 0xdf !11/5. */
|
---|
16386 | FNIEMOP_DEF_1(iemOp_fild_m64i, uint8_t, bRm)
|
---|
16387 | {
|
---|
16388 | IEMOP_MNEMONIC("fild m64i");
|
---|
16389 |
|
---|
16390 | IEM_MC_BEGIN(2, 3);
|
---|
16391 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
16392 | IEM_MC_LOCAL(IEMFPURESULT, FpuRes);
|
---|
16393 | IEM_MC_LOCAL(int64_t, i64Val);
|
---|
16394 | IEM_MC_ARG_LOCAL_REF(PIEMFPURESULT, pFpuRes, FpuRes, 0);
|
---|
16395 | IEM_MC_ARG_LOCAL_REF(int64_t const *, pi64Val, i64Val, 1);
|
---|
16396 |
|
---|
16397 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
16398 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16399 |
|
---|
16400 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16401 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16402 | IEM_MC_FETCH_MEM_I64(i64Val, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16403 |
|
---|
16404 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16405 | IEM_MC_IF_FPUREG_IS_EMPTY(7)
|
---|
16406 | IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fild_i64_to_r80, pFpuRes, pi64Val);
|
---|
16407 | IEM_MC_PUSH_FPU_RESULT_MEM_OP(FpuRes, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16408 | IEM_MC_ELSE()
|
---|
16409 | IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
16410 | IEM_MC_ENDIF();
|
---|
16411 | IEM_MC_ADVANCE_RIP();
|
---|
16412 |
|
---|
16413 | IEM_MC_END();
|
---|
16414 | return VINF_SUCCESS;
|
---|
16415 | }
|
---|
16416 |
|
---|
16417 |
|
---|
16418 | /** Opcode 0xdf !11/6. */
|
---|
16419 | FNIEMOP_STUB_1(iemOp_fbstp_m80d, uint8_t, bRm);
|
---|
16420 |
|
---|
16421 |
|
---|
16422 | /** Opcode 0xdf !11/7. */
|
---|
16423 | FNIEMOP_DEF_1(iemOp_fistp_m64i, uint8_t, bRm)
|
---|
16424 | {
|
---|
16425 | IEMOP_MNEMONIC("fistp m64i");
|
---|
16426 | IEM_MC_BEGIN(3, 2);
|
---|
16427 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
16428 | IEM_MC_LOCAL(uint16_t, u16Fsw);
|
---|
16429 | IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Fsw, u16Fsw, 0);
|
---|
16430 | IEM_MC_ARG(int64_t *, pi64Dst, 1);
|
---|
16431 | IEM_MC_ARG(PCRTFLOAT80U, pr80Value, 2);
|
---|
16432 |
|
---|
16433 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
16434 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16435 | IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE();
|
---|
16436 | IEM_MC_MAYBE_RAISE_FPU_XCPT();
|
---|
16437 |
|
---|
16438 | IEM_MC_MEM_MAP(pi64Dst, IEM_ACCESS_DATA_W, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1 /*arg*/);
|
---|
16439 | IEM_MC_PREPARE_FPU_USAGE();
|
---|
16440 | IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(pr80Value, 0)
|
---|
16441 | IEM_MC_CALL_FPU_AIMPL_3(iemAImpl_fist_r80_to_i64, pu16Fsw, pi64Dst, pr80Value);
|
---|
16442 | IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(pi64Dst, IEM_ACCESS_DATA_W, u16Fsw);
|
---|
16443 | IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(u16Fsw, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
16444 | IEM_MC_ELSE()
|
---|
16445 | IEM_MC_IF_FCW_IM()
|
---|
16446 | IEM_MC_STORE_MEM_I64_CONST_BY_REF(pi64Dst, INT64_MIN /* (integer indefinite) */);
|
---|
16447 | IEM_MC_MEM_COMMIT_AND_UNMAP(pi64Dst, IEM_ACCESS_DATA_W);
|
---|
16448 | IEM_MC_ENDIF();
|
---|
16449 | IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
16450 | IEM_MC_ENDIF();
|
---|
16451 | IEM_MC_ADVANCE_RIP();
|
---|
16452 |
|
---|
16453 | IEM_MC_END();
|
---|
16454 | return VINF_SUCCESS;
|
---|
16455 | }
|
---|
16456 |
|
---|
16457 |
|
---|
16458 | /** Opcode 0xdf. */
|
---|
16459 | FNIEMOP_DEF(iemOp_EscF7)
|
---|
16460 | {
|
---|
16461 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
16462 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
16463 | {
|
---|
16464 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
16465 | {
|
---|
16466 | case 0: return FNIEMOP_CALL_1(iemOp_ffreep_stN, bRm); /* ffree + pop afterwards, since forever according to AMD. */
|
---|
16467 | case 1: return FNIEMOP_CALL_1(iemOp_fxch_stN, bRm); /* Reserved, behaves like FXCH ST(i) on intel. */
|
---|
16468 | case 2: return FNIEMOP_CALL_1(iemOp_fstp_stN, bRm); /* Reserved, behaves like FSTP ST(i) on intel. */
|
---|
16469 | case 3: return FNIEMOP_CALL_1(iemOp_fstp_stN, bRm); /* Reserved, behaves like FSTP ST(i) on intel. */
|
---|
16470 | case 4: if (bRm == 0xe0)
|
---|
16471 | return FNIEMOP_CALL(iemOp_fnstsw_ax);
|
---|
16472 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
16473 | case 5: return FNIEMOP_CALL_1(iemOp_fucomip_st0_stN, bRm);
|
---|
16474 | case 6: return FNIEMOP_CALL_1(iemOp_fcomip_st0_stN, bRm);
|
---|
16475 | case 7: return IEMOP_RAISE_INVALID_OPCODE();
|
---|
16476 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16477 | }
|
---|
16478 | }
|
---|
16479 | else
|
---|
16480 | {
|
---|
16481 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
16482 | {
|
---|
16483 | case 0: return FNIEMOP_CALL_1(iemOp_fild_m16i, bRm);
|
---|
16484 | case 1: return FNIEMOP_CALL_1(iemOp_fisttp_m16i, bRm);
|
---|
16485 | case 2: return FNIEMOP_CALL_1(iemOp_fist_m16i, bRm);
|
---|
16486 | case 3: return FNIEMOP_CALL_1(iemOp_fistp_m16i, bRm);
|
---|
16487 | case 4: return FNIEMOP_CALL_1(iemOp_fbld_m80d, bRm);
|
---|
16488 | case 5: return FNIEMOP_CALL_1(iemOp_fild_m64i, bRm);
|
---|
16489 | case 6: return FNIEMOP_CALL_1(iemOp_fbstp_m80d, bRm);
|
---|
16490 | case 7: return FNIEMOP_CALL_1(iemOp_fistp_m64i, bRm);
|
---|
16491 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16492 | }
|
---|
16493 | }
|
---|
16494 | }
|
---|
16495 |
|
---|
16496 |
|
---|
16497 | /** Opcode 0xe0. */
|
---|
16498 | FNIEMOP_DEF(iemOp_loopne_Jb)
|
---|
16499 | {
|
---|
16500 | IEMOP_MNEMONIC("loopne Jb");
|
---|
16501 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
16502 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16503 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
16504 |
|
---|
16505 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
16506 | {
|
---|
16507 | case IEMMODE_16BIT:
|
---|
16508 | IEM_MC_BEGIN(0,0);
|
---|
16509 | IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
|
---|
16510 | IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
|
---|
16511 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16512 | } IEM_MC_ELSE() {
|
---|
16513 | IEM_MC_ADVANCE_RIP();
|
---|
16514 | } IEM_MC_ENDIF();
|
---|
16515 | IEM_MC_END();
|
---|
16516 | return VINF_SUCCESS;
|
---|
16517 |
|
---|
16518 | case IEMMODE_32BIT:
|
---|
16519 | IEM_MC_BEGIN(0,0);
|
---|
16520 | IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
|
---|
16521 | IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
|
---|
16522 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16523 | } IEM_MC_ELSE() {
|
---|
16524 | IEM_MC_ADVANCE_RIP();
|
---|
16525 | } IEM_MC_ENDIF();
|
---|
16526 | IEM_MC_END();
|
---|
16527 | return VINF_SUCCESS;
|
---|
16528 |
|
---|
16529 | case IEMMODE_64BIT:
|
---|
16530 | IEM_MC_BEGIN(0,0);
|
---|
16531 | IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
|
---|
16532 | IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
|
---|
16533 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16534 | } IEM_MC_ELSE() {
|
---|
16535 | IEM_MC_ADVANCE_RIP();
|
---|
16536 | } IEM_MC_ENDIF();
|
---|
16537 | IEM_MC_END();
|
---|
16538 | return VINF_SUCCESS;
|
---|
16539 |
|
---|
16540 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16541 | }
|
---|
16542 | }
|
---|
16543 |
|
---|
16544 |
|
---|
16545 | /** Opcode 0xe1. */
|
---|
16546 | FNIEMOP_DEF(iemOp_loope_Jb)
|
---|
16547 | {
|
---|
16548 | IEMOP_MNEMONIC("loope Jb");
|
---|
16549 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
16550 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16551 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
16552 |
|
---|
16553 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
16554 | {
|
---|
16555 | case IEMMODE_16BIT:
|
---|
16556 | IEM_MC_BEGIN(0,0);
|
---|
16557 | IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
|
---|
16558 | IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
16559 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16560 | } IEM_MC_ELSE() {
|
---|
16561 | IEM_MC_ADVANCE_RIP();
|
---|
16562 | } IEM_MC_ENDIF();
|
---|
16563 | IEM_MC_END();
|
---|
16564 | return VINF_SUCCESS;
|
---|
16565 |
|
---|
16566 | case IEMMODE_32BIT:
|
---|
16567 | IEM_MC_BEGIN(0,0);
|
---|
16568 | IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
|
---|
16569 | IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
16570 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16571 | } IEM_MC_ELSE() {
|
---|
16572 | IEM_MC_ADVANCE_RIP();
|
---|
16573 | } IEM_MC_ENDIF();
|
---|
16574 | IEM_MC_END();
|
---|
16575 | return VINF_SUCCESS;
|
---|
16576 |
|
---|
16577 | case IEMMODE_64BIT:
|
---|
16578 | IEM_MC_BEGIN(0,0);
|
---|
16579 | IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
|
---|
16580 | IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
|
---|
16581 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16582 | } IEM_MC_ELSE() {
|
---|
16583 | IEM_MC_ADVANCE_RIP();
|
---|
16584 | } IEM_MC_ENDIF();
|
---|
16585 | IEM_MC_END();
|
---|
16586 | return VINF_SUCCESS;
|
---|
16587 |
|
---|
16588 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16589 | }
|
---|
16590 | }
|
---|
16591 |
|
---|
16592 |
|
---|
16593 | /** Opcode 0xe2. */
|
---|
16594 | FNIEMOP_DEF(iemOp_loop_Jb)
|
---|
16595 | {
|
---|
16596 | IEMOP_MNEMONIC("loop Jb");
|
---|
16597 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
16598 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16599 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
16600 |
|
---|
16601 | /** @todo Check out the #GP case if EIP < CS.Base or EIP > CS.Limit when
|
---|
16602 | * using the 32-bit operand size override. How can that be restarted? See
|
---|
16603 | * weird pseudo code in intel manual. */
|
---|
16604 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
16605 | {
|
---|
16606 | case IEMMODE_16BIT:
|
---|
16607 | IEM_MC_BEGIN(0,0);
|
---|
16608 | if (-(int8_t)IEM_GET_INSTR_LEN(pVCpu) != i8Imm)
|
---|
16609 | {
|
---|
16610 | IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
|
---|
16611 | IEM_MC_IF_CX_IS_NZ() {
|
---|
16612 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16613 | } IEM_MC_ELSE() {
|
---|
16614 | IEM_MC_ADVANCE_RIP();
|
---|
16615 | } IEM_MC_ENDIF();
|
---|
16616 | }
|
---|
16617 | else
|
---|
16618 | {
|
---|
16619 | IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0);
|
---|
16620 | IEM_MC_ADVANCE_RIP();
|
---|
16621 | }
|
---|
16622 | IEM_MC_END();
|
---|
16623 | return VINF_SUCCESS;
|
---|
16624 |
|
---|
16625 | case IEMMODE_32BIT:
|
---|
16626 | IEM_MC_BEGIN(0,0);
|
---|
16627 | if (-(int8_t)IEM_GET_INSTR_LEN(pVCpu) != i8Imm)
|
---|
16628 | {
|
---|
16629 | IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
|
---|
16630 | IEM_MC_IF_ECX_IS_NZ() {
|
---|
16631 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16632 | } IEM_MC_ELSE() {
|
---|
16633 | IEM_MC_ADVANCE_RIP();
|
---|
16634 | } IEM_MC_ENDIF();
|
---|
16635 | }
|
---|
16636 | else
|
---|
16637 | {
|
---|
16638 | IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0);
|
---|
16639 | IEM_MC_ADVANCE_RIP();
|
---|
16640 | }
|
---|
16641 | IEM_MC_END();
|
---|
16642 | return VINF_SUCCESS;
|
---|
16643 |
|
---|
16644 | case IEMMODE_64BIT:
|
---|
16645 | IEM_MC_BEGIN(0,0);
|
---|
16646 | if (-(int8_t)IEM_GET_INSTR_LEN(pVCpu) != i8Imm)
|
---|
16647 | {
|
---|
16648 | IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
|
---|
16649 | IEM_MC_IF_RCX_IS_NZ() {
|
---|
16650 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16651 | } IEM_MC_ELSE() {
|
---|
16652 | IEM_MC_ADVANCE_RIP();
|
---|
16653 | } IEM_MC_ENDIF();
|
---|
16654 | }
|
---|
16655 | else
|
---|
16656 | {
|
---|
16657 | IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0);
|
---|
16658 | IEM_MC_ADVANCE_RIP();
|
---|
16659 | }
|
---|
16660 | IEM_MC_END();
|
---|
16661 | return VINF_SUCCESS;
|
---|
16662 |
|
---|
16663 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16664 | }
|
---|
16665 | }
|
---|
16666 |
|
---|
16667 |
|
---|
16668 | /** Opcode 0xe3. */
|
---|
16669 | FNIEMOP_DEF(iemOp_jecxz_Jb)
|
---|
16670 | {
|
---|
16671 | IEMOP_MNEMONIC("jecxz Jb");
|
---|
16672 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
16673 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16674 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
16675 |
|
---|
16676 | switch (pVCpu->iem.s.enmEffAddrMode)
|
---|
16677 | {
|
---|
16678 | case IEMMODE_16BIT:
|
---|
16679 | IEM_MC_BEGIN(0,0);
|
---|
16680 | IEM_MC_IF_CX_IS_NZ() {
|
---|
16681 | IEM_MC_ADVANCE_RIP();
|
---|
16682 | } IEM_MC_ELSE() {
|
---|
16683 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16684 | } IEM_MC_ENDIF();
|
---|
16685 | IEM_MC_END();
|
---|
16686 | return VINF_SUCCESS;
|
---|
16687 |
|
---|
16688 | case IEMMODE_32BIT:
|
---|
16689 | IEM_MC_BEGIN(0,0);
|
---|
16690 | IEM_MC_IF_ECX_IS_NZ() {
|
---|
16691 | IEM_MC_ADVANCE_RIP();
|
---|
16692 | } IEM_MC_ELSE() {
|
---|
16693 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16694 | } IEM_MC_ENDIF();
|
---|
16695 | IEM_MC_END();
|
---|
16696 | return VINF_SUCCESS;
|
---|
16697 |
|
---|
16698 | case IEMMODE_64BIT:
|
---|
16699 | IEM_MC_BEGIN(0,0);
|
---|
16700 | IEM_MC_IF_RCX_IS_NZ() {
|
---|
16701 | IEM_MC_ADVANCE_RIP();
|
---|
16702 | } IEM_MC_ELSE() {
|
---|
16703 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16704 | } IEM_MC_ENDIF();
|
---|
16705 | IEM_MC_END();
|
---|
16706 | return VINF_SUCCESS;
|
---|
16707 |
|
---|
16708 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16709 | }
|
---|
16710 | }
|
---|
16711 |
|
---|
16712 |
|
---|
16713 | /** Opcode 0xe4 */
|
---|
16714 | FNIEMOP_DEF(iemOp_in_AL_Ib)
|
---|
16715 | {
|
---|
16716 | IEMOP_MNEMONIC("in eAX,Ib");
|
---|
16717 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
16718 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16719 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_in, u8Imm, 1);
|
---|
16720 | }
|
---|
16721 |
|
---|
16722 |
|
---|
16723 | /** Opcode 0xe5 */
|
---|
16724 | FNIEMOP_DEF(iemOp_in_eAX_Ib)
|
---|
16725 | {
|
---|
16726 | IEMOP_MNEMONIC("in eAX,Ib");
|
---|
16727 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
16728 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16729 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_in, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4);
|
---|
16730 | }
|
---|
16731 |
|
---|
16732 |
|
---|
16733 | /** Opcode 0xe6 */
|
---|
16734 | FNIEMOP_DEF(iemOp_out_Ib_AL)
|
---|
16735 | {
|
---|
16736 | IEMOP_MNEMONIC("out Ib,AL");
|
---|
16737 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
16738 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16739 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_out, u8Imm, 1);
|
---|
16740 | }
|
---|
16741 |
|
---|
16742 |
|
---|
16743 | /** Opcode 0xe7 */
|
---|
16744 | FNIEMOP_DEF(iemOp_out_Ib_eAX)
|
---|
16745 | {
|
---|
16746 | IEMOP_MNEMONIC("out Ib,eAX");
|
---|
16747 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
16748 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16749 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_out, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4);
|
---|
16750 | }
|
---|
16751 |
|
---|
16752 |
|
---|
16753 | /** Opcode 0xe8. */
|
---|
16754 | FNIEMOP_DEF(iemOp_call_Jv)
|
---|
16755 | {
|
---|
16756 | IEMOP_MNEMONIC("call Jv");
|
---|
16757 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
16758 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
16759 | {
|
---|
16760 | case IEMMODE_16BIT:
|
---|
16761 | {
|
---|
16762 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
16763 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_call_rel_16, (int16_t)u16Imm);
|
---|
16764 | }
|
---|
16765 |
|
---|
16766 | case IEMMODE_32BIT:
|
---|
16767 | {
|
---|
16768 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
16769 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_call_rel_32, (int32_t)u32Imm);
|
---|
16770 | }
|
---|
16771 |
|
---|
16772 | case IEMMODE_64BIT:
|
---|
16773 | {
|
---|
16774 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
16775 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_call_rel_64, u64Imm);
|
---|
16776 | }
|
---|
16777 |
|
---|
16778 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16779 | }
|
---|
16780 | }
|
---|
16781 |
|
---|
16782 |
|
---|
16783 | /** Opcode 0xe9. */
|
---|
16784 | FNIEMOP_DEF(iemOp_jmp_Jv)
|
---|
16785 | {
|
---|
16786 | IEMOP_MNEMONIC("jmp Jv");
|
---|
16787 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
16788 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
16789 | {
|
---|
16790 | case IEMMODE_16BIT:
|
---|
16791 | {
|
---|
16792 | int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
|
---|
16793 | IEM_MC_BEGIN(0, 0);
|
---|
16794 | IEM_MC_REL_JMP_S16(i16Imm);
|
---|
16795 | IEM_MC_END();
|
---|
16796 | return VINF_SUCCESS;
|
---|
16797 | }
|
---|
16798 |
|
---|
16799 | case IEMMODE_64BIT:
|
---|
16800 | case IEMMODE_32BIT:
|
---|
16801 | {
|
---|
16802 | int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
|
---|
16803 | IEM_MC_BEGIN(0, 0);
|
---|
16804 | IEM_MC_REL_JMP_S32(i32Imm);
|
---|
16805 | IEM_MC_END();
|
---|
16806 | return VINF_SUCCESS;
|
---|
16807 | }
|
---|
16808 |
|
---|
16809 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
16810 | }
|
---|
16811 | }
|
---|
16812 |
|
---|
16813 |
|
---|
16814 | /** Opcode 0xea. */
|
---|
16815 | FNIEMOP_DEF(iemOp_jmp_Ap)
|
---|
16816 | {
|
---|
16817 | IEMOP_MNEMONIC("jmp Ap");
|
---|
16818 | IEMOP_HLP_NO_64BIT();
|
---|
16819 |
|
---|
16820 | /* Decode the far pointer address and pass it on to the far call C implementation. */
|
---|
16821 | uint32_t offSeg;
|
---|
16822 | if (pVCpu->iem.s.enmEffOpSize != IEMMODE_16BIT)
|
---|
16823 | IEM_OPCODE_GET_NEXT_U32(&offSeg);
|
---|
16824 | else
|
---|
16825 | IEM_OPCODE_GET_NEXT_U16_ZX_U32(&offSeg);
|
---|
16826 | uint16_t uSel; IEM_OPCODE_GET_NEXT_U16(&uSel);
|
---|
16827 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16828 | return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_FarJmp, uSel, offSeg, pVCpu->iem.s.enmEffOpSize);
|
---|
16829 | }
|
---|
16830 |
|
---|
16831 |
|
---|
16832 | /** Opcode 0xeb. */
|
---|
16833 | FNIEMOP_DEF(iemOp_jmp_Jb)
|
---|
16834 | {
|
---|
16835 | IEMOP_MNEMONIC("jmp Jb");
|
---|
16836 | int8_t i8Imm; IEM_OPCODE_GET_NEXT_S8(&i8Imm);
|
---|
16837 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16838 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
16839 |
|
---|
16840 | IEM_MC_BEGIN(0, 0);
|
---|
16841 | IEM_MC_REL_JMP_S8(i8Imm);
|
---|
16842 | IEM_MC_END();
|
---|
16843 | return VINF_SUCCESS;
|
---|
16844 | }
|
---|
16845 |
|
---|
16846 |
|
---|
16847 | /** Opcode 0xec */
|
---|
16848 | FNIEMOP_DEF(iemOp_in_AL_DX)
|
---|
16849 | {
|
---|
16850 | IEMOP_MNEMONIC("in AL,DX");
|
---|
16851 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16852 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_in_eAX_DX, 1);
|
---|
16853 | }
|
---|
16854 |
|
---|
16855 |
|
---|
16856 | /** Opcode 0xed */
|
---|
16857 | FNIEMOP_DEF(iemOp_eAX_DX)
|
---|
16858 | {
|
---|
16859 | IEMOP_MNEMONIC("in eAX,DX");
|
---|
16860 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16861 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_in_eAX_DX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4);
|
---|
16862 | }
|
---|
16863 |
|
---|
16864 |
|
---|
16865 | /** Opcode 0xee */
|
---|
16866 | FNIEMOP_DEF(iemOp_out_DX_AL)
|
---|
16867 | {
|
---|
16868 | IEMOP_MNEMONIC("out DX,AL");
|
---|
16869 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16870 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_out_DX_eAX, 1);
|
---|
16871 | }
|
---|
16872 |
|
---|
16873 |
|
---|
16874 | /** Opcode 0xef */
|
---|
16875 | FNIEMOP_DEF(iemOp_out_DX_eAX)
|
---|
16876 | {
|
---|
16877 | IEMOP_MNEMONIC("out DX,eAX");
|
---|
16878 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16879 | return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_out_DX_eAX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4);
|
---|
16880 | }
|
---|
16881 |
|
---|
16882 |
|
---|
16883 | /** Opcode 0xf0. */
|
---|
16884 | FNIEMOP_DEF(iemOp_lock)
|
---|
16885 | {
|
---|
16886 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("lock");
|
---|
16887 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_LOCK;
|
---|
16888 |
|
---|
16889 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
16890 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
16891 | }
|
---|
16892 |
|
---|
16893 |
|
---|
16894 | /** Opcode 0xf1. */
|
---|
16895 | FNIEMOP_DEF(iemOp_int_1)
|
---|
16896 | {
|
---|
16897 | IEMOP_MNEMONIC("int1"); /* icebp */
|
---|
16898 | IEMOP_HLP_MIN_386(); /** @todo does not generate #UD on 286, or so they say... */
|
---|
16899 | /** @todo testcase! */
|
---|
16900 | return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_int, X86_XCPT_DB, false /*fIsBpInstr*/);
|
---|
16901 | }
|
---|
16902 |
|
---|
16903 |
|
---|
16904 | /** Opcode 0xf2. */
|
---|
16905 | FNIEMOP_DEF(iemOp_repne)
|
---|
16906 | {
|
---|
16907 | /* This overrides any previous REPE prefix. */
|
---|
16908 | pVCpu->iem.s.fPrefixes &= ~IEM_OP_PRF_REPZ;
|
---|
16909 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("repne");
|
---|
16910 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REPNZ;
|
---|
16911 |
|
---|
16912 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
16913 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
16914 | }
|
---|
16915 |
|
---|
16916 |
|
---|
16917 | /** Opcode 0xf3. */
|
---|
16918 | FNIEMOP_DEF(iemOp_repe)
|
---|
16919 | {
|
---|
16920 | /* This overrides any previous REPNE prefix. */
|
---|
16921 | pVCpu->iem.s.fPrefixes &= ~IEM_OP_PRF_REPNZ;
|
---|
16922 | IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE("repe");
|
---|
16923 | pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_REPZ;
|
---|
16924 |
|
---|
16925 | uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
|
---|
16926 | return FNIEMOP_CALL(g_apfnOneByteMap[b]);
|
---|
16927 | }
|
---|
16928 |
|
---|
16929 |
|
---|
16930 | /** Opcode 0xf4. */
|
---|
16931 | FNIEMOP_DEF(iemOp_hlt)
|
---|
16932 | {
|
---|
16933 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16934 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_hlt);
|
---|
16935 | }
|
---|
16936 |
|
---|
16937 |
|
---|
16938 | /** Opcode 0xf5. */
|
---|
16939 | FNIEMOP_DEF(iemOp_cmc)
|
---|
16940 | {
|
---|
16941 | IEMOP_MNEMONIC("cmc");
|
---|
16942 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
16943 | IEM_MC_BEGIN(0, 0);
|
---|
16944 | IEM_MC_FLIP_EFL_BIT(X86_EFL_CF);
|
---|
16945 | IEM_MC_ADVANCE_RIP();
|
---|
16946 | IEM_MC_END();
|
---|
16947 | return VINF_SUCCESS;
|
---|
16948 | }
|
---|
16949 |
|
---|
16950 |
|
---|
16951 | /**
|
---|
16952 | * Common implementation of 'inc/dec/not/neg Eb'.
|
---|
16953 | *
|
---|
16954 | * @param bRm The RM byte.
|
---|
16955 | * @param pImpl The instruction implementation.
|
---|
16956 | */
|
---|
16957 | FNIEMOP_DEF_2(iemOpCommonUnaryEb, uint8_t, bRm, PCIEMOPUNARYSIZES, pImpl)
|
---|
16958 | {
|
---|
16959 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
16960 | {
|
---|
16961 | /* register access */
|
---|
16962 | IEM_MC_BEGIN(2, 0);
|
---|
16963 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
16964 | IEM_MC_ARG(uint32_t *, pEFlags, 1);
|
---|
16965 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
16966 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
16967 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU8, pu8Dst, pEFlags);
|
---|
16968 | IEM_MC_ADVANCE_RIP();
|
---|
16969 | IEM_MC_END();
|
---|
16970 | }
|
---|
16971 | else
|
---|
16972 | {
|
---|
16973 | /* memory access. */
|
---|
16974 | IEM_MC_BEGIN(2, 2);
|
---|
16975 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
16976 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1);
|
---|
16977 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
16978 |
|
---|
16979 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
16980 | IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
16981 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
16982 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
16983 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU8, pu8Dst, pEFlags);
|
---|
16984 | else
|
---|
16985 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnLockedU8, pu8Dst, pEFlags);
|
---|
16986 |
|
---|
16987 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
|
---|
16988 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
16989 | IEM_MC_ADVANCE_RIP();
|
---|
16990 | IEM_MC_END();
|
---|
16991 | }
|
---|
16992 | return VINF_SUCCESS;
|
---|
16993 | }
|
---|
16994 |
|
---|
16995 |
|
---|
16996 | /**
|
---|
16997 | * Common implementation of 'inc/dec/not/neg Ev'.
|
---|
16998 | *
|
---|
16999 | * @param bRm The RM byte.
|
---|
17000 | * @param pImpl The instruction implementation.
|
---|
17001 | */
|
---|
17002 | FNIEMOP_DEF_2(iemOpCommonUnaryEv, uint8_t, bRm, PCIEMOPUNARYSIZES, pImpl)
|
---|
17003 | {
|
---|
17004 | /* Registers are handled by a common worker. */
|
---|
17005 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
17006 | return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, pImpl, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17007 |
|
---|
17008 | /* Memory we do here. */
|
---|
17009 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17010 | {
|
---|
17011 | case IEMMODE_16BIT:
|
---|
17012 | IEM_MC_BEGIN(2, 2);
|
---|
17013 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
17014 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1);
|
---|
17015 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17016 |
|
---|
17017 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
17018 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
17019 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
17020 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
17021 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU16, pu16Dst, pEFlags);
|
---|
17022 | else
|
---|
17023 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnLockedU16, pu16Dst, pEFlags);
|
---|
17024 |
|
---|
17025 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
|
---|
17026 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
17027 | IEM_MC_ADVANCE_RIP();
|
---|
17028 | IEM_MC_END();
|
---|
17029 | return VINF_SUCCESS;
|
---|
17030 |
|
---|
17031 | case IEMMODE_32BIT:
|
---|
17032 | IEM_MC_BEGIN(2, 2);
|
---|
17033 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
17034 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1);
|
---|
17035 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17036 |
|
---|
17037 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
17038 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
17039 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
17040 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
17041 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU32, pu32Dst, pEFlags);
|
---|
17042 | else
|
---|
17043 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnLockedU32, pu32Dst, pEFlags);
|
---|
17044 |
|
---|
17045 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
|
---|
17046 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
17047 | IEM_MC_ADVANCE_RIP();
|
---|
17048 | IEM_MC_END();
|
---|
17049 | return VINF_SUCCESS;
|
---|
17050 |
|
---|
17051 | case IEMMODE_64BIT:
|
---|
17052 | IEM_MC_BEGIN(2, 2);
|
---|
17053 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
17054 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1);
|
---|
17055 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17056 |
|
---|
17057 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
17058 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
17059 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
17060 | if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
|
---|
17061 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU64, pu64Dst, pEFlags);
|
---|
17062 | else
|
---|
17063 | IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnLockedU64, pu64Dst, pEFlags);
|
---|
17064 |
|
---|
17065 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
|
---|
17066 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
17067 | IEM_MC_ADVANCE_RIP();
|
---|
17068 | IEM_MC_END();
|
---|
17069 | return VINF_SUCCESS;
|
---|
17070 |
|
---|
17071 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17072 | }
|
---|
17073 | }
|
---|
17074 |
|
---|
17075 |
|
---|
17076 | /** Opcode 0xf6 /0. */
|
---|
17077 | FNIEMOP_DEF_1(iemOp_grp3_test_Eb, uint8_t, bRm)
|
---|
17078 | {
|
---|
17079 | IEMOP_MNEMONIC("test Eb,Ib");
|
---|
17080 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
17081 |
|
---|
17082 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
17083 | {
|
---|
17084 | /* register access */
|
---|
17085 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
17086 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17087 |
|
---|
17088 | IEM_MC_BEGIN(3, 0);
|
---|
17089 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
17090 | IEM_MC_ARG_CONST(uint8_t, u8Src,/*=*/u8Imm, 1);
|
---|
17091 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
17092 | IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17093 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17094 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u8, pu8Dst, u8Src, pEFlags);
|
---|
17095 | IEM_MC_ADVANCE_RIP();
|
---|
17096 | IEM_MC_END();
|
---|
17097 | }
|
---|
17098 | else
|
---|
17099 | {
|
---|
17100 | /* memory access. */
|
---|
17101 | IEM_MC_BEGIN(3, 2);
|
---|
17102 | IEM_MC_ARG(uint8_t *, pu8Dst, 0);
|
---|
17103 | IEM_MC_ARG(uint8_t, u8Src, 1);
|
---|
17104 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
17105 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17106 |
|
---|
17107 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
|
---|
17108 | uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm);
|
---|
17109 | IEM_MC_ASSIGN(u8Src, u8Imm);
|
---|
17110 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17111 | IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
17112 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
17113 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u8, pu8Dst, u8Src, pEFlags);
|
---|
17114 |
|
---|
17115 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_R);
|
---|
17116 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
17117 | IEM_MC_ADVANCE_RIP();
|
---|
17118 | IEM_MC_END();
|
---|
17119 | }
|
---|
17120 | return VINF_SUCCESS;
|
---|
17121 | }
|
---|
17122 |
|
---|
17123 |
|
---|
17124 | /** Opcode 0xf7 /0. */
|
---|
17125 | FNIEMOP_DEF_1(iemOp_grp3_test_Ev, uint8_t, bRm)
|
---|
17126 | {
|
---|
17127 | IEMOP_MNEMONIC("test Ev,Iv");
|
---|
17128 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
|
---|
17129 |
|
---|
17130 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
17131 | {
|
---|
17132 | /* register access */
|
---|
17133 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17134 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17135 | {
|
---|
17136 | case IEMMODE_16BIT:
|
---|
17137 | {
|
---|
17138 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
17139 | IEM_MC_BEGIN(3, 0);
|
---|
17140 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
17141 | IEM_MC_ARG_CONST(uint16_t, u16Src,/*=*/u16Imm, 1);
|
---|
17142 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
17143 | IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17144 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17145 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u16, pu16Dst, u16Src, pEFlags);
|
---|
17146 | IEM_MC_ADVANCE_RIP();
|
---|
17147 | IEM_MC_END();
|
---|
17148 | return VINF_SUCCESS;
|
---|
17149 | }
|
---|
17150 |
|
---|
17151 | case IEMMODE_32BIT:
|
---|
17152 | {
|
---|
17153 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
17154 | IEM_MC_BEGIN(3, 0);
|
---|
17155 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
17156 | IEM_MC_ARG_CONST(uint32_t, u32Src,/*=*/u32Imm, 1);
|
---|
17157 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
17158 | IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17159 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17160 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u32, pu32Dst, u32Src, pEFlags);
|
---|
17161 | /* No clearing the high dword here - test doesn't write back the result. */
|
---|
17162 | IEM_MC_ADVANCE_RIP();
|
---|
17163 | IEM_MC_END();
|
---|
17164 | return VINF_SUCCESS;
|
---|
17165 | }
|
---|
17166 |
|
---|
17167 | case IEMMODE_64BIT:
|
---|
17168 | {
|
---|
17169 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
17170 | IEM_MC_BEGIN(3, 0);
|
---|
17171 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
17172 | IEM_MC_ARG_CONST(uint64_t, u64Src,/*=*/u64Imm, 1);
|
---|
17173 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
17174 | IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17175 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17176 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u64, pu64Dst, u64Src, pEFlags);
|
---|
17177 | IEM_MC_ADVANCE_RIP();
|
---|
17178 | IEM_MC_END();
|
---|
17179 | return VINF_SUCCESS;
|
---|
17180 | }
|
---|
17181 |
|
---|
17182 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17183 | }
|
---|
17184 | }
|
---|
17185 | else
|
---|
17186 | {
|
---|
17187 | /* memory access. */
|
---|
17188 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17189 | {
|
---|
17190 | case IEMMODE_16BIT:
|
---|
17191 | {
|
---|
17192 | IEM_MC_BEGIN(3, 2);
|
---|
17193 | IEM_MC_ARG(uint16_t *, pu16Dst, 0);
|
---|
17194 | IEM_MC_ARG(uint16_t, u16Src, 1);
|
---|
17195 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
17196 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17197 |
|
---|
17198 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 2);
|
---|
17199 | uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);
|
---|
17200 | IEM_MC_ASSIGN(u16Src, u16Imm);
|
---|
17201 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17202 | IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
17203 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
17204 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u16, pu16Dst, u16Src, pEFlags);
|
---|
17205 |
|
---|
17206 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_R);
|
---|
17207 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
17208 | IEM_MC_ADVANCE_RIP();
|
---|
17209 | IEM_MC_END();
|
---|
17210 | return VINF_SUCCESS;
|
---|
17211 | }
|
---|
17212 |
|
---|
17213 | case IEMMODE_32BIT:
|
---|
17214 | {
|
---|
17215 | IEM_MC_BEGIN(3, 2);
|
---|
17216 | IEM_MC_ARG(uint32_t *, pu32Dst, 0);
|
---|
17217 | IEM_MC_ARG(uint32_t, u32Src, 1);
|
---|
17218 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
17219 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17220 |
|
---|
17221 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
|
---|
17222 | uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);
|
---|
17223 | IEM_MC_ASSIGN(u32Src, u32Imm);
|
---|
17224 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17225 | IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
17226 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
17227 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u32, pu32Dst, u32Src, pEFlags);
|
---|
17228 |
|
---|
17229 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_R);
|
---|
17230 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
17231 | IEM_MC_ADVANCE_RIP();
|
---|
17232 | IEM_MC_END();
|
---|
17233 | return VINF_SUCCESS;
|
---|
17234 | }
|
---|
17235 |
|
---|
17236 | case IEMMODE_64BIT:
|
---|
17237 | {
|
---|
17238 | IEM_MC_BEGIN(3, 2);
|
---|
17239 | IEM_MC_ARG(uint64_t *, pu64Dst, 0);
|
---|
17240 | IEM_MC_ARG(uint64_t, u64Src, 1);
|
---|
17241 | IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
|
---|
17242 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17243 |
|
---|
17244 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);
|
---|
17245 | uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);
|
---|
17246 | IEM_MC_ASSIGN(u64Src, u64Imm);
|
---|
17247 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17248 | IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);
|
---|
17249 | IEM_MC_FETCH_EFLAGS(EFlags);
|
---|
17250 | IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u64, pu64Dst, u64Src, pEFlags);
|
---|
17251 |
|
---|
17252 | IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_R);
|
---|
17253 | IEM_MC_COMMIT_EFLAGS(EFlags);
|
---|
17254 | IEM_MC_ADVANCE_RIP();
|
---|
17255 | IEM_MC_END();
|
---|
17256 | return VINF_SUCCESS;
|
---|
17257 | }
|
---|
17258 |
|
---|
17259 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17260 | }
|
---|
17261 | }
|
---|
17262 | }
|
---|
17263 |
|
---|
17264 |
|
---|
17265 | /** Opcode 0xf6 /4, /5, /6 and /7. */
|
---|
17266 | FNIEMOP_DEF_2(iemOpCommonGrp3MulDivEb, uint8_t, bRm, PFNIEMAIMPLMULDIVU8, pfnU8)
|
---|
17267 | {
|
---|
17268 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
17269 | {
|
---|
17270 | /* register access */
|
---|
17271 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17272 | IEM_MC_BEGIN(3, 1);
|
---|
17273 | IEM_MC_ARG(uint16_t *, pu16AX, 0);
|
---|
17274 | IEM_MC_ARG(uint8_t, u8Value, 1);
|
---|
17275 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
17276 | IEM_MC_LOCAL(int32_t, rc);
|
---|
17277 |
|
---|
17278 | IEM_MC_FETCH_GREG_U8(u8Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17279 | IEM_MC_REF_GREG_U16(pu16AX, X86_GREG_xAX);
|
---|
17280 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17281 | IEM_MC_CALL_AIMPL_3(rc, pfnU8, pu16AX, u8Value, pEFlags);
|
---|
17282 | IEM_MC_IF_LOCAL_IS_Z(rc) {
|
---|
17283 | IEM_MC_ADVANCE_RIP();
|
---|
17284 | } IEM_MC_ELSE() {
|
---|
17285 | IEM_MC_RAISE_DIVIDE_ERROR();
|
---|
17286 | } IEM_MC_ENDIF();
|
---|
17287 |
|
---|
17288 | IEM_MC_END();
|
---|
17289 | }
|
---|
17290 | else
|
---|
17291 | {
|
---|
17292 | /* memory access. */
|
---|
17293 | IEM_MC_BEGIN(3, 2);
|
---|
17294 | IEM_MC_ARG(uint16_t *, pu16AX, 0);
|
---|
17295 | IEM_MC_ARG(uint8_t, u8Value, 1);
|
---|
17296 | IEM_MC_ARG(uint32_t *, pEFlags, 2);
|
---|
17297 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17298 | IEM_MC_LOCAL(int32_t, rc);
|
---|
17299 |
|
---|
17300 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
17301 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17302 | IEM_MC_FETCH_MEM_U8(u8Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
17303 | IEM_MC_REF_GREG_U16(pu16AX, X86_GREG_xAX);
|
---|
17304 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17305 | IEM_MC_CALL_AIMPL_3(rc, pfnU8, pu16AX, u8Value, pEFlags);
|
---|
17306 | IEM_MC_IF_LOCAL_IS_Z(rc) {
|
---|
17307 | IEM_MC_ADVANCE_RIP();
|
---|
17308 | } IEM_MC_ELSE() {
|
---|
17309 | IEM_MC_RAISE_DIVIDE_ERROR();
|
---|
17310 | } IEM_MC_ENDIF();
|
---|
17311 |
|
---|
17312 | IEM_MC_END();
|
---|
17313 | }
|
---|
17314 | return VINF_SUCCESS;
|
---|
17315 | }
|
---|
17316 |
|
---|
17317 |
|
---|
17318 | /** Opcode 0xf7 /4, /5, /6 and /7. */
|
---|
17319 | FNIEMOP_DEF_2(iemOpCommonGrp3MulDivEv, uint8_t, bRm, PCIEMOPMULDIVSIZES, pImpl)
|
---|
17320 | {
|
---|
17321 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
17322 |
|
---|
17323 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
17324 | {
|
---|
17325 | /* register access */
|
---|
17326 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17327 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17328 | {
|
---|
17329 | case IEMMODE_16BIT:
|
---|
17330 | {
|
---|
17331 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17332 | IEM_MC_BEGIN(4, 1);
|
---|
17333 | IEM_MC_ARG(uint16_t *, pu16AX, 0);
|
---|
17334 | IEM_MC_ARG(uint16_t *, pu16DX, 1);
|
---|
17335 | IEM_MC_ARG(uint16_t, u16Value, 2);
|
---|
17336 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
17337 | IEM_MC_LOCAL(int32_t, rc);
|
---|
17338 |
|
---|
17339 | IEM_MC_FETCH_GREG_U16(u16Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17340 | IEM_MC_REF_GREG_U16(pu16AX, X86_GREG_xAX);
|
---|
17341 | IEM_MC_REF_GREG_U16(pu16DX, X86_GREG_xDX);
|
---|
17342 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17343 | IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU16, pu16AX, pu16DX, u16Value, pEFlags);
|
---|
17344 | IEM_MC_IF_LOCAL_IS_Z(rc) {
|
---|
17345 | IEM_MC_ADVANCE_RIP();
|
---|
17346 | } IEM_MC_ELSE() {
|
---|
17347 | IEM_MC_RAISE_DIVIDE_ERROR();
|
---|
17348 | } IEM_MC_ENDIF();
|
---|
17349 |
|
---|
17350 | IEM_MC_END();
|
---|
17351 | return VINF_SUCCESS;
|
---|
17352 | }
|
---|
17353 |
|
---|
17354 | case IEMMODE_32BIT:
|
---|
17355 | {
|
---|
17356 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17357 | IEM_MC_BEGIN(4, 1);
|
---|
17358 | IEM_MC_ARG(uint32_t *, pu32AX, 0);
|
---|
17359 | IEM_MC_ARG(uint32_t *, pu32DX, 1);
|
---|
17360 | IEM_MC_ARG(uint32_t, u32Value, 2);
|
---|
17361 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
17362 | IEM_MC_LOCAL(int32_t, rc);
|
---|
17363 |
|
---|
17364 | IEM_MC_FETCH_GREG_U32(u32Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17365 | IEM_MC_REF_GREG_U32(pu32AX, X86_GREG_xAX);
|
---|
17366 | IEM_MC_REF_GREG_U32(pu32DX, X86_GREG_xDX);
|
---|
17367 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17368 | IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU32, pu32AX, pu32DX, u32Value, pEFlags);
|
---|
17369 | IEM_MC_IF_LOCAL_IS_Z(rc) {
|
---|
17370 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32AX);
|
---|
17371 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32DX);
|
---|
17372 | IEM_MC_ADVANCE_RIP();
|
---|
17373 | } IEM_MC_ELSE() {
|
---|
17374 | IEM_MC_RAISE_DIVIDE_ERROR();
|
---|
17375 | } IEM_MC_ENDIF();
|
---|
17376 |
|
---|
17377 | IEM_MC_END();
|
---|
17378 | return VINF_SUCCESS;
|
---|
17379 | }
|
---|
17380 |
|
---|
17381 | case IEMMODE_64BIT:
|
---|
17382 | {
|
---|
17383 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17384 | IEM_MC_BEGIN(4, 1);
|
---|
17385 | IEM_MC_ARG(uint64_t *, pu64AX, 0);
|
---|
17386 | IEM_MC_ARG(uint64_t *, pu64DX, 1);
|
---|
17387 | IEM_MC_ARG(uint64_t, u64Value, 2);
|
---|
17388 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
17389 | IEM_MC_LOCAL(int32_t, rc);
|
---|
17390 |
|
---|
17391 | IEM_MC_FETCH_GREG_U64(u64Value, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17392 | IEM_MC_REF_GREG_U64(pu64AX, X86_GREG_xAX);
|
---|
17393 | IEM_MC_REF_GREG_U64(pu64DX, X86_GREG_xDX);
|
---|
17394 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17395 | IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU64, pu64AX, pu64DX, u64Value, pEFlags);
|
---|
17396 | IEM_MC_IF_LOCAL_IS_Z(rc) {
|
---|
17397 | IEM_MC_ADVANCE_RIP();
|
---|
17398 | } IEM_MC_ELSE() {
|
---|
17399 | IEM_MC_RAISE_DIVIDE_ERROR();
|
---|
17400 | } IEM_MC_ENDIF();
|
---|
17401 |
|
---|
17402 | IEM_MC_END();
|
---|
17403 | return VINF_SUCCESS;
|
---|
17404 | }
|
---|
17405 |
|
---|
17406 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17407 | }
|
---|
17408 | }
|
---|
17409 | else
|
---|
17410 | {
|
---|
17411 | /* memory access. */
|
---|
17412 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17413 | {
|
---|
17414 | case IEMMODE_16BIT:
|
---|
17415 | {
|
---|
17416 | IEM_MC_BEGIN(4, 2);
|
---|
17417 | IEM_MC_ARG(uint16_t *, pu16AX, 0);
|
---|
17418 | IEM_MC_ARG(uint16_t *, pu16DX, 1);
|
---|
17419 | IEM_MC_ARG(uint16_t, u16Value, 2);
|
---|
17420 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
17421 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17422 | IEM_MC_LOCAL(int32_t, rc);
|
---|
17423 |
|
---|
17424 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
17425 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17426 | IEM_MC_FETCH_MEM_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
17427 | IEM_MC_REF_GREG_U16(pu16AX, X86_GREG_xAX);
|
---|
17428 | IEM_MC_REF_GREG_U16(pu16DX, X86_GREG_xDX);
|
---|
17429 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17430 | IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU16, pu16AX, pu16DX, u16Value, pEFlags);
|
---|
17431 | IEM_MC_IF_LOCAL_IS_Z(rc) {
|
---|
17432 | IEM_MC_ADVANCE_RIP();
|
---|
17433 | } IEM_MC_ELSE() {
|
---|
17434 | IEM_MC_RAISE_DIVIDE_ERROR();
|
---|
17435 | } IEM_MC_ENDIF();
|
---|
17436 |
|
---|
17437 | IEM_MC_END();
|
---|
17438 | return VINF_SUCCESS;
|
---|
17439 | }
|
---|
17440 |
|
---|
17441 | case IEMMODE_32BIT:
|
---|
17442 | {
|
---|
17443 | IEM_MC_BEGIN(4, 2);
|
---|
17444 | IEM_MC_ARG(uint32_t *, pu32AX, 0);
|
---|
17445 | IEM_MC_ARG(uint32_t *, pu32DX, 1);
|
---|
17446 | IEM_MC_ARG(uint32_t, u32Value, 2);
|
---|
17447 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
17448 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17449 | IEM_MC_LOCAL(int32_t, rc);
|
---|
17450 |
|
---|
17451 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
17452 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17453 | IEM_MC_FETCH_MEM_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
17454 | IEM_MC_REF_GREG_U32(pu32AX, X86_GREG_xAX);
|
---|
17455 | IEM_MC_REF_GREG_U32(pu32DX, X86_GREG_xDX);
|
---|
17456 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17457 | IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU32, pu32AX, pu32DX, u32Value, pEFlags);
|
---|
17458 | IEM_MC_IF_LOCAL_IS_Z(rc) {
|
---|
17459 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32AX);
|
---|
17460 | IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32DX);
|
---|
17461 | IEM_MC_ADVANCE_RIP();
|
---|
17462 | } IEM_MC_ELSE() {
|
---|
17463 | IEM_MC_RAISE_DIVIDE_ERROR();
|
---|
17464 | } IEM_MC_ENDIF();
|
---|
17465 |
|
---|
17466 | IEM_MC_END();
|
---|
17467 | return VINF_SUCCESS;
|
---|
17468 | }
|
---|
17469 |
|
---|
17470 | case IEMMODE_64BIT:
|
---|
17471 | {
|
---|
17472 | IEM_MC_BEGIN(4, 2);
|
---|
17473 | IEM_MC_ARG(uint64_t *, pu64AX, 0);
|
---|
17474 | IEM_MC_ARG(uint64_t *, pu64DX, 1);
|
---|
17475 | IEM_MC_ARG(uint64_t, u64Value, 2);
|
---|
17476 | IEM_MC_ARG(uint32_t *, pEFlags, 3);
|
---|
17477 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
|
---|
17478 | IEM_MC_LOCAL(int32_t, rc);
|
---|
17479 |
|
---|
17480 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
|
---|
17481 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17482 | IEM_MC_FETCH_MEM_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
|
---|
17483 | IEM_MC_REF_GREG_U64(pu64AX, X86_GREG_xAX);
|
---|
17484 | IEM_MC_REF_GREG_U64(pu64DX, X86_GREG_xDX);
|
---|
17485 | IEM_MC_REF_EFLAGS(pEFlags);
|
---|
17486 | IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU64, pu64AX, pu64DX, u64Value, pEFlags);
|
---|
17487 | IEM_MC_IF_LOCAL_IS_Z(rc) {
|
---|
17488 | IEM_MC_ADVANCE_RIP();
|
---|
17489 | } IEM_MC_ELSE() {
|
---|
17490 | IEM_MC_RAISE_DIVIDE_ERROR();
|
---|
17491 | } IEM_MC_ENDIF();
|
---|
17492 |
|
---|
17493 | IEM_MC_END();
|
---|
17494 | return VINF_SUCCESS;
|
---|
17495 | }
|
---|
17496 |
|
---|
17497 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17498 | }
|
---|
17499 | }
|
---|
17500 | }
|
---|
17501 |
|
---|
17502 | /** Opcode 0xf6. */
|
---|
17503 | FNIEMOP_DEF(iemOp_Grp3_Eb)
|
---|
17504 | {
|
---|
17505 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
17506 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
17507 | {
|
---|
17508 | case 0:
|
---|
17509 | return FNIEMOP_CALL_1(iemOp_grp3_test_Eb, bRm);
|
---|
17510 | case 1:
|
---|
17511 | /** @todo testcase: Present on <=386, most 486 (not early), Pentiums, and current CPUs too. CPUUNDOC.EXE */
|
---|
17512 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
17513 | case 2:
|
---|
17514 | IEMOP_MNEMONIC("not Eb");
|
---|
17515 | return FNIEMOP_CALL_2(iemOpCommonUnaryEb, bRm, &g_iemAImpl_not);
|
---|
17516 | case 3:
|
---|
17517 | IEMOP_MNEMONIC("neg Eb");
|
---|
17518 | return FNIEMOP_CALL_2(iemOpCommonUnaryEb, bRm, &g_iemAImpl_neg);
|
---|
17519 | case 4:
|
---|
17520 | IEMOP_MNEMONIC("mul Eb");
|
---|
17521 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
17522 | return FNIEMOP_CALL_2(iemOpCommonGrp3MulDivEb, bRm, iemAImpl_mul_u8);
|
---|
17523 | case 5:
|
---|
17524 | IEMOP_MNEMONIC("imul Eb");
|
---|
17525 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
17526 | return FNIEMOP_CALL_2(iemOpCommonGrp3MulDivEb, bRm, iemAImpl_imul_u8);
|
---|
17527 | case 6:
|
---|
17528 | IEMOP_MNEMONIC("div Eb");
|
---|
17529 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_OF | X86_EFL_CF);
|
---|
17530 | return FNIEMOP_CALL_2(iemOpCommonGrp3MulDivEb, bRm, iemAImpl_div_u8);
|
---|
17531 | case 7:
|
---|
17532 | IEMOP_MNEMONIC("idiv Eb");
|
---|
17533 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_OF | X86_EFL_CF);
|
---|
17534 | return FNIEMOP_CALL_2(iemOpCommonGrp3MulDivEb, bRm, iemAImpl_idiv_u8);
|
---|
17535 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17536 | }
|
---|
17537 | }
|
---|
17538 |
|
---|
17539 |
|
---|
17540 | /** Opcode 0xf7. */
|
---|
17541 | FNIEMOP_DEF(iemOp_Grp3_Ev)
|
---|
17542 | {
|
---|
17543 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
17544 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
17545 | {
|
---|
17546 | case 0:
|
---|
17547 | return FNIEMOP_CALL_1(iemOp_grp3_test_Ev, bRm);
|
---|
17548 | case 1:
|
---|
17549 | /** @todo testcase: Present on <=386, most 486 (not early), Pentiums, and current CPUs too. CPUUNDOC.EXE */
|
---|
17550 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
17551 | case 2:
|
---|
17552 | IEMOP_MNEMONIC("not Ev");
|
---|
17553 | return FNIEMOP_CALL_2(iemOpCommonUnaryEv, bRm, &g_iemAImpl_not);
|
---|
17554 | case 3:
|
---|
17555 | IEMOP_MNEMONIC("neg Ev");
|
---|
17556 | return FNIEMOP_CALL_2(iemOpCommonUnaryEv, bRm, &g_iemAImpl_neg);
|
---|
17557 | case 4:
|
---|
17558 | IEMOP_MNEMONIC("mul Ev");
|
---|
17559 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
17560 | return FNIEMOP_CALL_2(iemOpCommonGrp3MulDivEv, bRm, &g_iemAImpl_mul);
|
---|
17561 | case 5:
|
---|
17562 | IEMOP_MNEMONIC("imul Ev");
|
---|
17563 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
|
---|
17564 | return FNIEMOP_CALL_2(iemOpCommonGrp3MulDivEv, bRm, &g_iemAImpl_imul);
|
---|
17565 | case 6:
|
---|
17566 | IEMOP_MNEMONIC("div Ev");
|
---|
17567 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_OF | X86_EFL_CF);
|
---|
17568 | return FNIEMOP_CALL_2(iemOpCommonGrp3MulDivEv, bRm, &g_iemAImpl_div);
|
---|
17569 | case 7:
|
---|
17570 | IEMOP_MNEMONIC("idiv Ev");
|
---|
17571 | IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_OF | X86_EFL_CF);
|
---|
17572 | return FNIEMOP_CALL_2(iemOpCommonGrp3MulDivEv, bRm, &g_iemAImpl_idiv);
|
---|
17573 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17574 | }
|
---|
17575 | }
|
---|
17576 |
|
---|
17577 |
|
---|
17578 | /** Opcode 0xf8. */
|
---|
17579 | FNIEMOP_DEF(iemOp_clc)
|
---|
17580 | {
|
---|
17581 | IEMOP_MNEMONIC("clc");
|
---|
17582 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17583 | IEM_MC_BEGIN(0, 0);
|
---|
17584 | IEM_MC_CLEAR_EFL_BIT(X86_EFL_CF);
|
---|
17585 | IEM_MC_ADVANCE_RIP();
|
---|
17586 | IEM_MC_END();
|
---|
17587 | return VINF_SUCCESS;
|
---|
17588 | }
|
---|
17589 |
|
---|
17590 |
|
---|
17591 | /** Opcode 0xf9. */
|
---|
17592 | FNIEMOP_DEF(iemOp_stc)
|
---|
17593 | {
|
---|
17594 | IEMOP_MNEMONIC("stc");
|
---|
17595 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17596 | IEM_MC_BEGIN(0, 0);
|
---|
17597 | IEM_MC_SET_EFL_BIT(X86_EFL_CF);
|
---|
17598 | IEM_MC_ADVANCE_RIP();
|
---|
17599 | IEM_MC_END();
|
---|
17600 | return VINF_SUCCESS;
|
---|
17601 | }
|
---|
17602 |
|
---|
17603 |
|
---|
17604 | /** Opcode 0xfa. */
|
---|
17605 | FNIEMOP_DEF(iemOp_cli)
|
---|
17606 | {
|
---|
17607 | IEMOP_MNEMONIC("cli");
|
---|
17608 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17609 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_cli);
|
---|
17610 | }
|
---|
17611 |
|
---|
17612 |
|
---|
17613 | FNIEMOP_DEF(iemOp_sti)
|
---|
17614 | {
|
---|
17615 | IEMOP_MNEMONIC("sti");
|
---|
17616 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17617 | return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_sti);
|
---|
17618 | }
|
---|
17619 |
|
---|
17620 |
|
---|
17621 | /** Opcode 0xfc. */
|
---|
17622 | FNIEMOP_DEF(iemOp_cld)
|
---|
17623 | {
|
---|
17624 | IEMOP_MNEMONIC("cld");
|
---|
17625 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17626 | IEM_MC_BEGIN(0, 0);
|
---|
17627 | IEM_MC_CLEAR_EFL_BIT(X86_EFL_DF);
|
---|
17628 | IEM_MC_ADVANCE_RIP();
|
---|
17629 | IEM_MC_END();
|
---|
17630 | return VINF_SUCCESS;
|
---|
17631 | }
|
---|
17632 |
|
---|
17633 |
|
---|
17634 | /** Opcode 0xfd. */
|
---|
17635 | FNIEMOP_DEF(iemOp_std)
|
---|
17636 | {
|
---|
17637 | IEMOP_MNEMONIC("std");
|
---|
17638 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17639 | IEM_MC_BEGIN(0, 0);
|
---|
17640 | IEM_MC_SET_EFL_BIT(X86_EFL_DF);
|
---|
17641 | IEM_MC_ADVANCE_RIP();
|
---|
17642 | IEM_MC_END();
|
---|
17643 | return VINF_SUCCESS;
|
---|
17644 | }
|
---|
17645 |
|
---|
17646 |
|
---|
17647 | /** Opcode 0xfe. */
|
---|
17648 | FNIEMOP_DEF(iemOp_Grp4)
|
---|
17649 | {
|
---|
17650 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
17651 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
17652 | {
|
---|
17653 | case 0:
|
---|
17654 | IEMOP_MNEMONIC("inc Ev");
|
---|
17655 | return FNIEMOP_CALL_2(iemOpCommonUnaryEb, bRm, &g_iemAImpl_inc);
|
---|
17656 | case 1:
|
---|
17657 | IEMOP_MNEMONIC("dec Ev");
|
---|
17658 | return FNIEMOP_CALL_2(iemOpCommonUnaryEb, bRm, &g_iemAImpl_dec);
|
---|
17659 | default:
|
---|
17660 | IEMOP_MNEMONIC("grp4-ud");
|
---|
17661 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
17662 | }
|
---|
17663 | }
|
---|
17664 |
|
---|
17665 |
|
---|
17666 | /**
|
---|
17667 | * Opcode 0xff /2.
|
---|
17668 | * @param bRm The RM byte.
|
---|
17669 | */
|
---|
17670 | FNIEMOP_DEF_1(iemOp_Grp5_calln_Ev, uint8_t, bRm)
|
---|
17671 | {
|
---|
17672 | IEMOP_MNEMONIC("calln Ev");
|
---|
17673 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
17674 |
|
---|
17675 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
17676 | {
|
---|
17677 | /* The new RIP is taken from a register. */
|
---|
17678 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17679 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17680 | {
|
---|
17681 | case IEMMODE_16BIT:
|
---|
17682 | IEM_MC_BEGIN(1, 0);
|
---|
17683 | IEM_MC_ARG(uint16_t, u16Target, 0);
|
---|
17684 | IEM_MC_FETCH_GREG_U16(u16Target, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17685 | IEM_MC_CALL_CIMPL_1(iemCImpl_call_16, u16Target);
|
---|
17686 | IEM_MC_END()
|
---|
17687 | return VINF_SUCCESS;
|
---|
17688 |
|
---|
17689 | case IEMMODE_32BIT:
|
---|
17690 | IEM_MC_BEGIN(1, 0);
|
---|
17691 | IEM_MC_ARG(uint32_t, u32Target, 0);
|
---|
17692 | IEM_MC_FETCH_GREG_U32(u32Target, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17693 | IEM_MC_CALL_CIMPL_1(iemCImpl_call_32, u32Target);
|
---|
17694 | IEM_MC_END()
|
---|
17695 | return VINF_SUCCESS;
|
---|
17696 |
|
---|
17697 | case IEMMODE_64BIT:
|
---|
17698 | IEM_MC_BEGIN(1, 0);
|
---|
17699 | IEM_MC_ARG(uint64_t, u64Target, 0);
|
---|
17700 | IEM_MC_FETCH_GREG_U64(u64Target, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17701 | IEM_MC_CALL_CIMPL_1(iemCImpl_call_64, u64Target);
|
---|
17702 | IEM_MC_END()
|
---|
17703 | return VINF_SUCCESS;
|
---|
17704 |
|
---|
17705 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17706 | }
|
---|
17707 | }
|
---|
17708 | else
|
---|
17709 | {
|
---|
17710 | /* The new RIP is taken from a register. */
|
---|
17711 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17712 | {
|
---|
17713 | case IEMMODE_16BIT:
|
---|
17714 | IEM_MC_BEGIN(1, 1);
|
---|
17715 | IEM_MC_ARG(uint16_t, u16Target, 0);
|
---|
17716 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17717 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17718 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17719 | IEM_MC_FETCH_MEM_U16(u16Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17720 | IEM_MC_CALL_CIMPL_1(iemCImpl_call_16, u16Target);
|
---|
17721 | IEM_MC_END()
|
---|
17722 | return VINF_SUCCESS;
|
---|
17723 |
|
---|
17724 | case IEMMODE_32BIT:
|
---|
17725 | IEM_MC_BEGIN(1, 1);
|
---|
17726 | IEM_MC_ARG(uint32_t, u32Target, 0);
|
---|
17727 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17728 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17729 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17730 | IEM_MC_FETCH_MEM_U32(u32Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17731 | IEM_MC_CALL_CIMPL_1(iemCImpl_call_32, u32Target);
|
---|
17732 | IEM_MC_END()
|
---|
17733 | return VINF_SUCCESS;
|
---|
17734 |
|
---|
17735 | case IEMMODE_64BIT:
|
---|
17736 | IEM_MC_BEGIN(1, 1);
|
---|
17737 | IEM_MC_ARG(uint64_t, u64Target, 0);
|
---|
17738 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17739 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17740 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17741 | IEM_MC_FETCH_MEM_U64(u64Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17742 | IEM_MC_CALL_CIMPL_1(iemCImpl_call_64, u64Target);
|
---|
17743 | IEM_MC_END()
|
---|
17744 | return VINF_SUCCESS;
|
---|
17745 |
|
---|
17746 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17747 | }
|
---|
17748 | }
|
---|
17749 | }
|
---|
17750 |
|
---|
17751 | typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmOpSize);
|
---|
17752 |
|
---|
17753 | FNIEMOP_DEF_2(iemOpHlp_Grp5_far_Ep, uint8_t, bRm, FNIEMCIMPLFARBRANCH *, pfnCImpl)
|
---|
17754 | {
|
---|
17755 | /* Registers? How?? */
|
---|
17756 | if (RT_LIKELY((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)))
|
---|
17757 | { /* likely */ }
|
---|
17758 | else
|
---|
17759 | return IEMOP_RAISE_INVALID_OPCODE(); /* callf eax is not legal */
|
---|
17760 |
|
---|
17761 | /* Far pointer loaded from memory. */
|
---|
17762 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17763 | {
|
---|
17764 | case IEMMODE_16BIT:
|
---|
17765 | IEM_MC_BEGIN(3, 1);
|
---|
17766 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
17767 | IEM_MC_ARG(uint16_t, offSeg, 1);
|
---|
17768 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_16BIT, 2);
|
---|
17769 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17770 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17771 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17772 | IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17773 | IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 2);
|
---|
17774 | IEM_MC_CALL_CIMPL_3(pfnCImpl, u16Sel, offSeg, enmEffOpSize);
|
---|
17775 | IEM_MC_END();
|
---|
17776 | return VINF_SUCCESS;
|
---|
17777 |
|
---|
17778 | case IEMMODE_64BIT:
|
---|
17779 | /** @todo testcase: AMD does not seem to believe in the case (see bs-cpu-xcpt-1)
|
---|
17780 | * and will apparently ignore REX.W, at least for the jmp far qword [rsp]
|
---|
17781 | * and call far qword [rsp] encodings. */
|
---|
17782 | if (!IEM_IS_GUEST_CPU_AMD(pVCpu))
|
---|
17783 | {
|
---|
17784 | IEM_MC_BEGIN(3, 1);
|
---|
17785 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
17786 | IEM_MC_ARG(uint64_t, offSeg, 1);
|
---|
17787 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_16BIT, 2);
|
---|
17788 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17789 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17790 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17791 | IEM_MC_FETCH_MEM_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17792 | IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 8);
|
---|
17793 | IEM_MC_CALL_CIMPL_3(pfnCImpl, u16Sel, offSeg, enmEffOpSize);
|
---|
17794 | IEM_MC_END();
|
---|
17795 | return VINF_SUCCESS;
|
---|
17796 | }
|
---|
17797 | /* AMD falls thru. */
|
---|
17798 |
|
---|
17799 | case IEMMODE_32BIT:
|
---|
17800 | IEM_MC_BEGIN(3, 1);
|
---|
17801 | IEM_MC_ARG(uint16_t, u16Sel, 0);
|
---|
17802 | IEM_MC_ARG(uint32_t, offSeg, 1);
|
---|
17803 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, IEMMODE_32BIT, 2);
|
---|
17804 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17805 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17806 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17807 | IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17808 | IEM_MC_FETCH_MEM_U16_DISP(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, 4);
|
---|
17809 | IEM_MC_CALL_CIMPL_3(pfnCImpl, u16Sel, offSeg, enmEffOpSize);
|
---|
17810 | IEM_MC_END();
|
---|
17811 | return VINF_SUCCESS;
|
---|
17812 |
|
---|
17813 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17814 | }
|
---|
17815 | }
|
---|
17816 |
|
---|
17817 |
|
---|
17818 | /**
|
---|
17819 | * Opcode 0xff /3.
|
---|
17820 | * @param bRm The RM byte.
|
---|
17821 | */
|
---|
17822 | FNIEMOP_DEF_1(iemOp_Grp5_callf_Ep, uint8_t, bRm)
|
---|
17823 | {
|
---|
17824 | IEMOP_MNEMONIC("callf Ep");
|
---|
17825 | return FNIEMOP_CALL_2(iemOpHlp_Grp5_far_Ep, bRm, iemCImpl_callf);
|
---|
17826 | }
|
---|
17827 |
|
---|
17828 |
|
---|
17829 | /**
|
---|
17830 | * Opcode 0xff /4.
|
---|
17831 | * @param bRm The RM byte.
|
---|
17832 | */
|
---|
17833 | FNIEMOP_DEF_1(iemOp_Grp5_jmpn_Ev, uint8_t, bRm)
|
---|
17834 | {
|
---|
17835 | IEMOP_MNEMONIC("jmpn Ev");
|
---|
17836 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
17837 |
|
---|
17838 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
17839 | {
|
---|
17840 | /* The new RIP is taken from a register. */
|
---|
17841 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17842 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17843 | {
|
---|
17844 | case IEMMODE_16BIT:
|
---|
17845 | IEM_MC_BEGIN(0, 1);
|
---|
17846 | IEM_MC_LOCAL(uint16_t, u16Target);
|
---|
17847 | IEM_MC_FETCH_GREG_U16(u16Target, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17848 | IEM_MC_SET_RIP_U16(u16Target);
|
---|
17849 | IEM_MC_END()
|
---|
17850 | return VINF_SUCCESS;
|
---|
17851 |
|
---|
17852 | case IEMMODE_32BIT:
|
---|
17853 | IEM_MC_BEGIN(0, 1);
|
---|
17854 | IEM_MC_LOCAL(uint32_t, u32Target);
|
---|
17855 | IEM_MC_FETCH_GREG_U32(u32Target, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17856 | IEM_MC_SET_RIP_U32(u32Target);
|
---|
17857 | IEM_MC_END()
|
---|
17858 | return VINF_SUCCESS;
|
---|
17859 |
|
---|
17860 | case IEMMODE_64BIT:
|
---|
17861 | IEM_MC_BEGIN(0, 1);
|
---|
17862 | IEM_MC_LOCAL(uint64_t, u64Target);
|
---|
17863 | IEM_MC_FETCH_GREG_U64(u64Target, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17864 | IEM_MC_SET_RIP_U64(u64Target);
|
---|
17865 | IEM_MC_END()
|
---|
17866 | return VINF_SUCCESS;
|
---|
17867 |
|
---|
17868 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17869 | }
|
---|
17870 | }
|
---|
17871 | else
|
---|
17872 | {
|
---|
17873 | /* The new RIP is taken from a memory location. */
|
---|
17874 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17875 | {
|
---|
17876 | case IEMMODE_16BIT:
|
---|
17877 | IEM_MC_BEGIN(0, 2);
|
---|
17878 | IEM_MC_LOCAL(uint16_t, u16Target);
|
---|
17879 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17880 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17881 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17882 | IEM_MC_FETCH_MEM_U16(u16Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17883 | IEM_MC_SET_RIP_U16(u16Target);
|
---|
17884 | IEM_MC_END()
|
---|
17885 | return VINF_SUCCESS;
|
---|
17886 |
|
---|
17887 | case IEMMODE_32BIT:
|
---|
17888 | IEM_MC_BEGIN(0, 2);
|
---|
17889 | IEM_MC_LOCAL(uint32_t, u32Target);
|
---|
17890 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17891 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17892 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17893 | IEM_MC_FETCH_MEM_U32(u32Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17894 | IEM_MC_SET_RIP_U32(u32Target);
|
---|
17895 | IEM_MC_END()
|
---|
17896 | return VINF_SUCCESS;
|
---|
17897 |
|
---|
17898 | case IEMMODE_64BIT:
|
---|
17899 | IEM_MC_BEGIN(0, 2);
|
---|
17900 | IEM_MC_LOCAL(uint64_t, u64Target);
|
---|
17901 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17902 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17903 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17904 | IEM_MC_FETCH_MEM_U64(u64Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17905 | IEM_MC_SET_RIP_U64(u64Target);
|
---|
17906 | IEM_MC_END()
|
---|
17907 | return VINF_SUCCESS;
|
---|
17908 |
|
---|
17909 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17910 | }
|
---|
17911 | }
|
---|
17912 | }
|
---|
17913 |
|
---|
17914 |
|
---|
17915 | /**
|
---|
17916 | * Opcode 0xff /5.
|
---|
17917 | * @param bRm The RM byte.
|
---|
17918 | */
|
---|
17919 | FNIEMOP_DEF_1(iemOp_Grp5_jmpf_Ep, uint8_t, bRm)
|
---|
17920 | {
|
---|
17921 | IEMOP_MNEMONIC("jmpf Ep");
|
---|
17922 | return FNIEMOP_CALL_2(iemOpHlp_Grp5_far_Ep, bRm, iemCImpl_FarJmp);
|
---|
17923 | }
|
---|
17924 |
|
---|
17925 |
|
---|
17926 | /**
|
---|
17927 | * Opcode 0xff /6.
|
---|
17928 | * @param bRm The RM byte.
|
---|
17929 | */
|
---|
17930 | FNIEMOP_DEF_1(iemOp_Grp5_push_Ev, uint8_t, bRm)
|
---|
17931 | {
|
---|
17932 | IEMOP_MNEMONIC("push Ev");
|
---|
17933 |
|
---|
17934 | /* Registers are handled by a common worker. */
|
---|
17935 | if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
|
---|
17936 | return FNIEMOP_CALL_1(iemOpCommonPushGReg, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
|
---|
17937 |
|
---|
17938 | /* Memory we do here. */
|
---|
17939 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
17940 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
17941 | {
|
---|
17942 | case IEMMODE_16BIT:
|
---|
17943 | IEM_MC_BEGIN(0, 2);
|
---|
17944 | IEM_MC_LOCAL(uint16_t, u16Src);
|
---|
17945 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17946 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17947 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17948 | IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17949 | IEM_MC_PUSH_U16(u16Src);
|
---|
17950 | IEM_MC_ADVANCE_RIP();
|
---|
17951 | IEM_MC_END();
|
---|
17952 | return VINF_SUCCESS;
|
---|
17953 |
|
---|
17954 | case IEMMODE_32BIT:
|
---|
17955 | IEM_MC_BEGIN(0, 2);
|
---|
17956 | IEM_MC_LOCAL(uint32_t, u32Src);
|
---|
17957 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17958 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17959 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17960 | IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17961 | IEM_MC_PUSH_U32(u32Src);
|
---|
17962 | IEM_MC_ADVANCE_RIP();
|
---|
17963 | IEM_MC_END();
|
---|
17964 | return VINF_SUCCESS;
|
---|
17965 |
|
---|
17966 | case IEMMODE_64BIT:
|
---|
17967 | IEM_MC_BEGIN(0, 2);
|
---|
17968 | IEM_MC_LOCAL(uint64_t, u64Src);
|
---|
17969 | IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
|
---|
17970 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
|
---|
17971 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
17972 | IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
|
---|
17973 | IEM_MC_PUSH_U64(u64Src);
|
---|
17974 | IEM_MC_ADVANCE_RIP();
|
---|
17975 | IEM_MC_END();
|
---|
17976 | return VINF_SUCCESS;
|
---|
17977 |
|
---|
17978 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
17979 | }
|
---|
17980 | }
|
---|
17981 |
|
---|
17982 |
|
---|
17983 | /** Opcode 0xff. */
|
---|
17984 | FNIEMOP_DEF(iemOp_Grp5)
|
---|
17985 | {
|
---|
17986 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
|
---|
17987 | switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
|
---|
17988 | {
|
---|
17989 | case 0:
|
---|
17990 | IEMOP_MNEMONIC("inc Ev");
|
---|
17991 | return FNIEMOP_CALL_2(iemOpCommonUnaryEv, bRm, &g_iemAImpl_inc);
|
---|
17992 | case 1:
|
---|
17993 | IEMOP_MNEMONIC("dec Ev");
|
---|
17994 | return FNIEMOP_CALL_2(iemOpCommonUnaryEv, bRm, &g_iemAImpl_dec);
|
---|
17995 | case 2:
|
---|
17996 | return FNIEMOP_CALL_1(iemOp_Grp5_calln_Ev, bRm);
|
---|
17997 | case 3:
|
---|
17998 | return FNIEMOP_CALL_1(iemOp_Grp5_callf_Ep, bRm);
|
---|
17999 | case 4:
|
---|
18000 | return FNIEMOP_CALL_1(iemOp_Grp5_jmpn_Ev, bRm);
|
---|
18001 | case 5:
|
---|
18002 | return FNIEMOP_CALL_1(iemOp_Grp5_jmpf_Ep, bRm);
|
---|
18003 | case 6:
|
---|
18004 | return FNIEMOP_CALL_1(iemOp_Grp5_push_Ev, bRm);
|
---|
18005 | case 7:
|
---|
18006 | IEMOP_MNEMONIC("grp5-ud");
|
---|
18007 | return IEMOP_RAISE_INVALID_OPCODE();
|
---|
18008 | }
|
---|
18009 | AssertFailedReturn(VERR_IEM_IPE_3);
|
---|
18010 | }
|
---|
18011 |
|
---|
18012 |
|
---|
18013 |
|
---|
18014 | const PFNIEMOP g_apfnOneByteMap[256] =
|
---|
18015 | {
|
---|
18016 | /* 0x00 */ iemOp_add_Eb_Gb, iemOp_add_Ev_Gv, iemOp_add_Gb_Eb, iemOp_add_Gv_Ev,
|
---|
18017 | /* 0x04 */ iemOp_add_Al_Ib, iemOp_add_eAX_Iz, iemOp_push_ES, iemOp_pop_ES,
|
---|
18018 | /* 0x08 */ iemOp_or_Eb_Gb, iemOp_or_Ev_Gv, iemOp_or_Gb_Eb, iemOp_or_Gv_Ev,
|
---|
18019 | /* 0x0c */ iemOp_or_Al_Ib, iemOp_or_eAX_Iz, iemOp_push_CS, iemOp_2byteEscape,
|
---|
18020 | /* 0x10 */ iemOp_adc_Eb_Gb, iemOp_adc_Ev_Gv, iemOp_adc_Gb_Eb, iemOp_adc_Gv_Ev,
|
---|
18021 | /* 0x14 */ iemOp_adc_Al_Ib, iemOp_adc_eAX_Iz, iemOp_push_SS, iemOp_pop_SS,
|
---|
18022 | /* 0x18 */ iemOp_sbb_Eb_Gb, iemOp_sbb_Ev_Gv, iemOp_sbb_Gb_Eb, iemOp_sbb_Gv_Ev,
|
---|
18023 | /* 0x1c */ iemOp_sbb_Al_Ib, iemOp_sbb_eAX_Iz, iemOp_push_DS, iemOp_pop_DS,
|
---|
18024 | /* 0x20 */ iemOp_and_Eb_Gb, iemOp_and_Ev_Gv, iemOp_and_Gb_Eb, iemOp_and_Gv_Ev,
|
---|
18025 | /* 0x24 */ iemOp_and_Al_Ib, iemOp_and_eAX_Iz, iemOp_seg_ES, iemOp_daa,
|
---|
18026 | /* 0x28 */ iemOp_sub_Eb_Gb, iemOp_sub_Ev_Gv, iemOp_sub_Gb_Eb, iemOp_sub_Gv_Ev,
|
---|
18027 | /* 0x2c */ iemOp_sub_Al_Ib, iemOp_sub_eAX_Iz, iemOp_seg_CS, iemOp_das,
|
---|
18028 | /* 0x30 */ iemOp_xor_Eb_Gb, iemOp_xor_Ev_Gv, iemOp_xor_Gb_Eb, iemOp_xor_Gv_Ev,
|
---|
18029 | /* 0x34 */ iemOp_xor_Al_Ib, iemOp_xor_eAX_Iz, iemOp_seg_SS, iemOp_aaa,
|
---|
18030 | /* 0x38 */ iemOp_cmp_Eb_Gb, iemOp_cmp_Ev_Gv, iemOp_cmp_Gb_Eb, iemOp_cmp_Gv_Ev,
|
---|
18031 | /* 0x3c */ iemOp_cmp_Al_Ib, iemOp_cmp_eAX_Iz, iemOp_seg_DS, iemOp_aas,
|
---|
18032 | /* 0x40 */ iemOp_inc_eAX, iemOp_inc_eCX, iemOp_inc_eDX, iemOp_inc_eBX,
|
---|
18033 | /* 0x44 */ iemOp_inc_eSP, iemOp_inc_eBP, iemOp_inc_eSI, iemOp_inc_eDI,
|
---|
18034 | /* 0x48 */ iemOp_dec_eAX, iemOp_dec_eCX, iemOp_dec_eDX, iemOp_dec_eBX,
|
---|
18035 | /* 0x4c */ iemOp_dec_eSP, iemOp_dec_eBP, iemOp_dec_eSI, iemOp_dec_eDI,
|
---|
18036 | /* 0x50 */ iemOp_push_eAX, iemOp_push_eCX, iemOp_push_eDX, iemOp_push_eBX,
|
---|
18037 | /* 0x54 */ iemOp_push_eSP, iemOp_push_eBP, iemOp_push_eSI, iemOp_push_eDI,
|
---|
18038 | /* 0x58 */ iemOp_pop_eAX, iemOp_pop_eCX, iemOp_pop_eDX, iemOp_pop_eBX,
|
---|
18039 | /* 0x5c */ iemOp_pop_eSP, iemOp_pop_eBP, iemOp_pop_eSI, iemOp_pop_eDI,
|
---|
18040 | /* 0x60 */ iemOp_pusha, iemOp_popa, iemOp_bound_Gv_Ma_evex, iemOp_arpl_Ew_Gw_movsx_Gv_Ev,
|
---|
18041 | /* 0x64 */ iemOp_seg_FS, iemOp_seg_GS, iemOp_op_size, iemOp_addr_size,
|
---|
18042 | /* 0x68 */ iemOp_push_Iz, iemOp_imul_Gv_Ev_Iz, iemOp_push_Ib, iemOp_imul_Gv_Ev_Ib,
|
---|
18043 | /* 0x6c */ iemOp_insb_Yb_DX, iemOp_inswd_Yv_DX, iemOp_outsb_Yb_DX, iemOp_outswd_Yv_DX,
|
---|
18044 | /* 0x70 */ iemOp_jo_Jb, iemOp_jno_Jb, iemOp_jc_Jb, iemOp_jnc_Jb,
|
---|
18045 | /* 0x74 */ iemOp_je_Jb, iemOp_jne_Jb, iemOp_jbe_Jb, iemOp_jnbe_Jb,
|
---|
18046 | /* 0x78 */ iemOp_js_Jb, iemOp_jns_Jb, iemOp_jp_Jb, iemOp_jnp_Jb,
|
---|
18047 | /* 0x7c */ iemOp_jl_Jb, iemOp_jnl_Jb, iemOp_jle_Jb, iemOp_jnle_Jb,
|
---|
18048 | /* 0x80 */ iemOp_Grp1_Eb_Ib_80, iemOp_Grp1_Ev_Iz, iemOp_Grp1_Eb_Ib_82, iemOp_Grp1_Ev_Ib,
|
---|
18049 | /* 0x84 */ iemOp_test_Eb_Gb, iemOp_test_Ev_Gv, iemOp_xchg_Eb_Gb, iemOp_xchg_Ev_Gv,
|
---|
18050 | /* 0x88 */ iemOp_mov_Eb_Gb, iemOp_mov_Ev_Gv, iemOp_mov_Gb_Eb, iemOp_mov_Gv_Ev,
|
---|
18051 | /* 0x8c */ iemOp_mov_Ev_Sw, iemOp_lea_Gv_M, iemOp_mov_Sw_Ev, iemOp_Grp1A,
|
---|
18052 | /* 0x90 */ iemOp_nop, iemOp_xchg_eCX_eAX, iemOp_xchg_eDX_eAX, iemOp_xchg_eBX_eAX,
|
---|
18053 | /* 0x94 */ iemOp_xchg_eSP_eAX, iemOp_xchg_eBP_eAX, iemOp_xchg_eSI_eAX, iemOp_xchg_eDI_eAX,
|
---|
18054 | /* 0x98 */ iemOp_cbw, iemOp_cwd, iemOp_call_Ap, iemOp_wait,
|
---|
18055 | /* 0x9c */ iemOp_pushf_Fv, iemOp_popf_Fv, iemOp_sahf, iemOp_lahf,
|
---|
18056 | /* 0xa0 */ iemOp_mov_Al_Ob, iemOp_mov_rAX_Ov, iemOp_mov_Ob_AL, iemOp_mov_Ov_rAX,
|
---|
18057 | /* 0xa4 */ iemOp_movsb_Xb_Yb, iemOp_movswd_Xv_Yv, iemOp_cmpsb_Xb_Yb, iemOp_cmpswd_Xv_Yv,
|
---|
18058 | /* 0xa8 */ iemOp_test_AL_Ib, iemOp_test_eAX_Iz, iemOp_stosb_Yb_AL, iemOp_stoswd_Yv_eAX,
|
---|
18059 | /* 0xac */ iemOp_lodsb_AL_Xb, iemOp_lodswd_eAX_Xv, iemOp_scasb_AL_Xb, iemOp_scaswd_eAX_Xv,
|
---|
18060 | /* 0xb0 */ iemOp_mov_AL_Ib, iemOp_CL_Ib, iemOp_DL_Ib, iemOp_BL_Ib,
|
---|
18061 | /* 0xb4 */ iemOp_mov_AH_Ib, iemOp_CH_Ib, iemOp_DH_Ib, iemOp_BH_Ib,
|
---|
18062 | /* 0xb8 */ iemOp_eAX_Iv, iemOp_eCX_Iv, iemOp_eDX_Iv, iemOp_eBX_Iv,
|
---|
18063 | /* 0xbc */ iemOp_eSP_Iv, iemOp_eBP_Iv, iemOp_eSI_Iv, iemOp_eDI_Iv,
|
---|
18064 | /* 0xc0 */ iemOp_Grp2_Eb_Ib, iemOp_Grp2_Ev_Ib, iemOp_retn_Iw, iemOp_retn,
|
---|
18065 | /* 0xc4 */ iemOp_les_Gv_Mp_vex2, iemOp_lds_Gv_Mp_vex3, iemOp_Grp11_Eb_Ib, iemOp_Grp11_Ev_Iz,
|
---|
18066 | /* 0xc8 */ iemOp_enter_Iw_Ib, iemOp_leave, iemOp_retf_Iw, iemOp_retf,
|
---|
18067 | /* 0xcc */ iemOp_int_3, iemOp_int_Ib, iemOp_into, iemOp_iret,
|
---|
18068 | /* 0xd0 */ iemOp_Grp2_Eb_1, iemOp_Grp2_Ev_1, iemOp_Grp2_Eb_CL, iemOp_Grp2_Ev_CL,
|
---|
18069 | /* 0xd4 */ iemOp_aam_Ib, iemOp_aad_Ib, iemOp_salc, iemOp_xlat,
|
---|
18070 | /* 0xd8 */ iemOp_EscF0, iemOp_EscF1, iemOp_EscF2, iemOp_EscF3,
|
---|
18071 | /* 0xdc */ iemOp_EscF4, iemOp_EscF5, iemOp_EscF6, iemOp_EscF7,
|
---|
18072 | /* 0xe0 */ iemOp_loopne_Jb, iemOp_loope_Jb, iemOp_loop_Jb, iemOp_jecxz_Jb,
|
---|
18073 | /* 0xe4 */ iemOp_in_AL_Ib, iemOp_in_eAX_Ib, iemOp_out_Ib_AL, iemOp_out_Ib_eAX,
|
---|
18074 | /* 0xe8 */ iemOp_call_Jv, iemOp_jmp_Jv, iemOp_jmp_Ap, iemOp_jmp_Jb,
|
---|
18075 | /* 0xec */ iemOp_in_AL_DX, iemOp_eAX_DX, iemOp_out_DX_AL, iemOp_out_DX_eAX,
|
---|
18076 | /* 0xf0 */ iemOp_lock, iemOp_int_1, iemOp_repne, iemOp_repe,
|
---|
18077 | /* 0xf4 */ iemOp_hlt, iemOp_cmc, iemOp_Grp3_Eb, iemOp_Grp3_Ev,
|
---|
18078 | /* 0xf8 */ iemOp_clc, iemOp_stc, iemOp_cli, iemOp_sti,
|
---|
18079 | /* 0xfc */ iemOp_cld, iemOp_std, iemOp_Grp4, iemOp_Grp5,
|
---|
18080 | };
|
---|
18081 |
|
---|
18082 |
|
---|
18083 | /** @} */
|
---|
18084 |
|
---|
18085 | #ifdef _MSC_VER
|
---|
18086 | # pragma warning(pop)
|
---|
18087 | #endif
|
---|