VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h@ 107044

Last change on this file since 107044 was 106180, checked in by vboxsync, 2 months ago

VMM/IEM: Refactoring TbExits and other early eflags calculation postponement changes. bugref:10720
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 149.9 KB
Line 
1/* $Id: IEMAllInstVexMap2.cpp.h 106180 2024-09-30 13:51:48Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstThree0f38.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2024 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 2
33 * @{
34 */
35
36/**
37 * Common worker for AESNI/AVX instructions on the forms:
38 * - vaesxxx xmm0, xmm1, xmm2/mem128
39 *
40 * Exceptions type 4. AVX and AESNI cpuid check for 128-bit operation.
41 */
42FNIEMOP_DEF_1(iemOpCommonAvxAesNi_Vx_Hx_Wx, PFNIEMAIMPLMEDIAOPTF3U128, pfnU128)
43{
44 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
45 if (IEM_IS_MODRM_REG_MODE(bRm))
46 {
47 /*
48 * Register, register.
49 */
50 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
51 IEMOP_HLP_DONE_VEX_DECODING_L0_EX_2(fAvx, fAesNi);
52 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
53 IEM_MC_PREPARE_AVX_USAGE();
54
55 IEM_MC_LOCAL(RTUINT128U, uDst);
56 IEM_MC_ARG_LOCAL_REF(PRTUINT128U, puDst, uDst, 0);
57 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
58 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
59 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
60 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
61 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc1, puSrc2);
62 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
63 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
64 IEM_MC_ADVANCE_RIP_AND_FINISH();
65 IEM_MC_END();
66 }
67 else
68 {
69 /*
70 * Register, memory.
71 */
72 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
73 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
74 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
75 IEMOP_HLP_DONE_VEX_DECODING_L0_EX_2(fAvx, fAesNi);
76 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
77 IEM_MC_PREPARE_AVX_USAGE();
78
79 IEM_MC_LOCAL(RTUINT128U, uDst);
80 IEM_MC_ARG_LOCAL_REF(PRTUINT128U, puDst, uDst, 0);
81 IEM_MC_LOCAL(RTUINT128U, uSrc2);
82 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
83 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
85 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
86
87 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc1, puSrc2);
88 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
89 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
90 IEM_MC_ADVANCE_RIP_AND_FINISH();
91 IEM_MC_END();
92 }
93}
94
95
96/* Opcode VEX.0F38 0x00 - invalid. */
97
98
99/** Opcode VEX.66.0F38 0x00. */
100FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
101{
102 IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
103 IEMOPMEDIAOPTF3_INIT_VARS( vpshufb);
104 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
105}
106
107
108/* Opcode VEX.0F38 0x01 - invalid. */
109
110
111/** Opcode VEX.66.0F38 0x01. */
112FNIEMOP_DEF(iemOp_vphaddw_Vx_Hx_Wx)
113{
114 IEMOP_MNEMONIC3(VEX_RVM, VPHADDW, vphaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
115 IEMOPMEDIAOPTF3_INIT_VARS(vphaddw);
116 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
117}
118
119
120/* Opcode VEX.0F38 0x02 - invalid. */
121
122
123/** Opcode VEX.66.0F38 0x02. */
124FNIEMOP_DEF(iemOp_vphaddd_Vx_Hx_Wx)
125{
126 IEMOP_MNEMONIC3(VEX_RVM, VPHADDD, vphaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
127 IEMOPMEDIAOPTF3_INIT_VARS(vphaddd);
128 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
129}
130
131
132/* Opcode VEX.0F38 0x03 - invalid. */
133
134
135/** Opcode VEX.66.0F38 0x03. */
136FNIEMOP_DEF(iemOp_vphaddsw_Vx_Hx_Wx)
137{
138 IEMOP_MNEMONIC3(VEX_RVM, VPHADDSW, vphaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
139 IEMOPMEDIAOPTF3_INIT_VARS(vphaddsw);
140 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
141}
142
143
144/* Opcode VEX.0F38 0x04 - invalid. */
145
146
147/** Opcode VEX.66.0F38 0x04. */
148FNIEMOP_DEF(iemOp_vpmaddubsw_Vx_Hx_Wx)
149{
150 IEMOP_MNEMONIC3(VEX_RVM, VPMADDUBSW, vpmaddubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
151 IEMOPMEDIAOPTF3_INIT_VARS(vpmaddubsw);
152 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
153}
154
155
156/* Opcode VEX.0F38 0x05 - invalid. */
157
158
159/** Opcode VEX.66.0F38 0x05. */
160FNIEMOP_DEF(iemOp_vphsubw_Vx_Hx_Wx)
161{
162 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBW, vphsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
163 IEMOPMEDIAOPTF3_INIT_VARS(vphsubw);
164 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
165}
166
167
168/* Opcode VEX.0F38 0x06 - invalid. */
169
170
171/** Opcode VEX.66.0F38 0x06. */
172FNIEMOP_DEF(iemOp_vphsubd_Vx_Hx_Wx)
173{
174 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBD, vphsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
175 IEMOPMEDIAOPTF3_INIT_VARS(vphsubd);
176 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
177}
178
179
180/* Opcode VEX.0F38 0x07 - invalid. */
181
182
183/** Opcode VEX.66.0F38 0x07. */
184FNIEMOP_DEF(iemOp_vphsubsw_Vx_Hx_Wx)
185{
186 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBSW, vphsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
187 IEMOPMEDIAOPTF3_INIT_VARS(vphsubsw);
188 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
189}
190
191
192/* Opcode VEX.0F38 0x08 - invalid. */
193
194
195/** Opcode VEX.66.0F38 0x08. */
196FNIEMOP_DEF(iemOp_vpsignb_Vx_Hx_Wx)
197{
198 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNB, vpsignb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
199 IEMOPMEDIAOPTF3_INIT_VARS(vpsignb);
200 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
201}
202
203
204/* Opcode VEX.0F38 0x09 - invalid. */
205
206
207/** Opcode VEX.66.0F38 0x09. */
208FNIEMOP_DEF(iemOp_vpsignw_Vx_Hx_Wx)
209{
210 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNW, vpsignw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
211 IEMOPMEDIAOPTF3_INIT_VARS(vpsignw);
212 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
213}
214
215
216/* Opcode VEX.0F38 0x0a - invalid. */
217
218
219/** Opcode VEX.66.0F38 0x0a. */
220FNIEMOP_DEF(iemOp_vpsignd_Vx_Hx_Wx)
221{
222 IEMOP_MNEMONIC3(VEX_RVM, VPSIGND, vpsignd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
223 IEMOPMEDIAOPTF3_INIT_VARS(vpsignd);
224 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
225}
226
227
228/* Opcode VEX.0F38 0x0b - invalid. */
229
230
231/** Opcode VEX.66.0F38 0x0b. */
232FNIEMOP_DEF(iemOp_vpmulhrsw_Vx_Hx_Wx)
233{
234 IEMOP_MNEMONIC3(VEX_RVM, VPMULHRSW, vpmulhrsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
235 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhrsw);
236 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
237}
238
239
240/* Opcode VEX.0F38 0x0c - invalid. */
241
242
243/** Opcode VEX.66.0F38 0x0c.
244 * AVX,AVX */
245FNIEMOP_DEF(iemOp_vpermilps_Vx_Hx_Wx)
246{
247 IEMOP_MNEMONIC3(VEX_RVM, VPERMILPS, vpermilps, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
248 IEMOPMEDIAOPTF3_INIT_VARS(vpermilps);
249 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
250}
251
252
253/* Opcode VEX.0F38 0x0d - invalid. */
254
255
256/** Opcode VEX.66.0F38 0x0d.
257 * AVX,AVX */
258FNIEMOP_DEF(iemOp_vpermilpd_Vx_Hx_Wx)
259{
260 IEMOP_MNEMONIC3(VEX_RVM, VPERMILPD, vpermilpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
261 IEMOPMEDIAOPTF3_INIT_VARS(vpermilpd);
262 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
263}
264
265
266/**
267 * Common worker for AVX instructions on the forms:
268 * - vtestps/d xmm1, xmm2/mem128
269 * - vtestps/d ymm1, ymm2/mem256
270 *
271 * Takes function table for function w/o implicit state parameter.
272 *
273 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
274 */
275#define IEMOP_BODY_VTESTP_S_D(a_Instr) \
276 Assert(pVCpu->iem.s.uVexLength <= 1); \
277 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
278 if (IEM_IS_MODRM_REG_MODE(bRm)) \
279 { \
280 /* \
281 * Register, register. \
282 */ \
283 if (pVCpu->iem.s.uVexLength) \
284 { \
285 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
286 IEMOP_HLP_DONE_VEX_DECODING_W0_AND_NO_VVVV_EX(fAvx); \
287 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
288 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
289 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0); \
290 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1); \
291 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
292 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
293 IEM_MC_PREPARE_AVX_USAGE(); \
294 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); \
295 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
296 IEM_MC_REF_EFLAGS(pEFlags); \
297 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_ ## a_Instr ## _u256, \
298 iemAImpl_ ## a_Instr ## _u256_fallback), \
299 puSrc1, puSrc2, pEFlags); \
300 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
301 IEM_MC_END(); \
302 } \
303 else \
304 { \
305 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
306 IEMOP_HLP_DONE_VEX_DECODING_W0_AND_NO_VVVV_EX(fAvx); \
307 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0); \
308 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1); \
309 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
310 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
311 IEM_MC_PREPARE_AVX_USAGE(); \
312 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); \
313 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
314 IEM_MC_REF_EFLAGS(pEFlags); \
315 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_ ## a_Instr ## _u128, \
316 iemAImpl_ ## a_Instr ## _u128_fallback), \
317 puSrc1, puSrc2, pEFlags); \
318 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
319 IEM_MC_END(); \
320 } \
321 } \
322 else \
323 { \
324 /* \
325 * Register, memory. \
326 */ \
327 if (pVCpu->iem.s.uVexLength) \
328 { \
329 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
330 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
331 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
332 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
333 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0); \
334 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1); \
335 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
336 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
337 IEMOP_HLP_DONE_VEX_DECODING_W0_AND_NO_VVVV_EX(fAvx); \
338 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
339 IEM_MC_PREPARE_AVX_USAGE(); \
340 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
341 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); \
342 IEM_MC_REF_EFLAGS(pEFlags); \
343 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_ ## a_Instr ## _u256, \
344 iemAImpl_ ## a_Instr ## _u256_fallback), \
345 puSrc1, puSrc2, pEFlags); \
346 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
347 IEM_MC_END(); \
348 } \
349 else \
350 { \
351 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
352 IEM_MC_LOCAL(RTUINT128U, uSrc2); \
353 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
354 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0); \
355 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1); \
356 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
357 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
358 IEMOP_HLP_DONE_VEX_DECODING_W0_AND_NO_VVVV_EX(fAvx); \
359 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
360 IEM_MC_PREPARE_AVX_USAGE(); \
361 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
362 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); \
363 IEM_MC_REF_EFLAGS(pEFlags); \
364 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_ ## a_Instr ## _u128, \
365 iemAImpl_ ## a_Instr ## _u128_fallback), \
366 puSrc1, puSrc2, pEFlags); \
367 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
368 IEM_MC_END(); \
369 } \
370 } \
371 (void)0
372
373
374/* Opcode VEX.0F38 0x0e - invalid. */
375
376
377/**
378 * @opcode 0x0e
379 * @oppfx 0x66
380 * @opflmodify cf,zf,pf,af,sf,of
381 * @opflclear pf,af,sf,of
382 */
383FNIEMOP_DEF(iemOp_vtestps_Vx_Wx)
384{
385 /** @todo We need to check VEX.W somewhere... it is documented to \#UD on all
386 * CPU modes. */
387 IEMOP_MNEMONIC2(VEX_RM, VTESTPS, vtestps, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_W_ZERO);
388 IEMOP_BODY_VTESTP_S_D(vtestps);
389}
390
391
392/* Opcode VEX.0F38 0x0f - invalid. */
393
394
395/**
396 * @opcode 0x0f
397 * @oppfx 0x66
398 * @opflmodify cf,zf,pf,af,sf,of
399 * @opflclear pf,af,sf,of
400 */
401FNIEMOP_DEF(iemOp_vtestpd_Vx_Wx)
402{
403 /** @todo We need to check VEX.W somewhere... it is documented to \#UD on all
404 * CPU modes. */
405 IEMOP_MNEMONIC2(VEX_RM, VTESTPD, vtestpd, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_W_ZERO);
406 IEMOP_BODY_VTESTP_S_D(vtestpd);
407}
408
409
410/* Opcode VEX.0F38 0x10 - invalid */
411/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
412/* Opcode VEX.0F38 0x11 - invalid */
413/* Opcode VEX.66.0F38 0x11 - invalid */
414/* Opcode VEX.0F38 0x12 - invalid */
415/* Opcode VEX.66.0F38 0x12 - invalid */
416/* Opcode VEX.0F38 0x13 - invalid */
417/* Opcode VEX.66.0F38 0x13 (vex only). */
418FNIEMOP_STUB(iemOp_vcvtph2ps_Vx_Wx);
419/* Opcode VEX.0F38 0x14 - invalid */
420/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
421/* Opcode VEX.0F38 0x15 - invalid */
422/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
423/* Opcode VEX.0F38 0x16 - invalid */
424
425
426/** Opcode VEX.66.0F38 0x16. */
427FNIEMOP_DEF(iemOp_vpermps_Vqq_Hqq_Wqq)
428{
429 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
430 if (IEM_IS_MODRM_REG_MODE(bRm))
431 {
432 /*
433 * Register, register.
434 */
435 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
436 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
437 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
438 IEM_MC_PREPARE_AVX_USAGE();
439 IEM_MC_LOCAL(RTUINT256U, uSrc1);
440 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
441 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
442 IEM_MC_LOCAL(RTUINT256U, uSrc2);
443 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
444 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
445 IEM_MC_LOCAL(RTUINT256U, uDst);
446 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
447 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback),
448 puDst, puSrc1, puSrc2);
449 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
450 IEM_MC_ADVANCE_RIP_AND_FINISH();
451 IEM_MC_END();
452 }
453 else
454 {
455 /*
456 * Register, memory.
457 */
458 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
459 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
460 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
461 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
462 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
463 IEM_MC_PREPARE_AVX_USAGE();
464 IEM_MC_LOCAL(RTUINT256U, uSrc2);
465 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
466 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
467 IEM_MC_LOCAL(RTUINT256U, uSrc1);
468 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
469 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
470 IEM_MC_LOCAL(RTUINT256U, uDst);
471 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
472 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback),
473 puDst, puSrc1, puSrc2);
474 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
475 IEM_MC_ADVANCE_RIP_AND_FINISH();
476 IEM_MC_END();
477 }
478}
479
480
481/* Opcode VEX.0F38 0x17 - invalid */
482
483
484/**
485 * @opcode 0x17
486 * @oppfx 0x66
487 * @opflmodify cf,pf,af,zf,sf,of
488 * @opflclear pf,af,sf,of
489 */
490FNIEMOP_DEF(iemOp_vptest_Vx_Wx)
491{
492 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
493 if (IEM_IS_MODRM_REG_MODE(bRm))
494 {
495 /*
496 * Register, register.
497 */
498 if (pVCpu->iem.s.uVexLength)
499 {
500 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
501 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
502 IEM_MC_LOCAL(RTUINT256U, uSrc1);
503 IEM_MC_LOCAL(RTUINT256U, uSrc2);
504 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
505 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
506 IEM_MC_ARG(uint32_t *, pEFlags, 2);
507 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
508 IEM_MC_PREPARE_AVX_USAGE();
509 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
510 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
511 IEM_MC_REF_EFLAGS(pEFlags);
512 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
513 puSrc1, puSrc2, pEFlags);
514 IEM_MC_ADVANCE_RIP_AND_FINISH();
515 IEM_MC_END();
516 }
517 else
518 {
519 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
520 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
521 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
522 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
523 IEM_MC_ARG(uint32_t *, pEFlags, 2);
524 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
525 IEM_MC_PREPARE_AVX_USAGE();
526 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
527 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
528 IEM_MC_REF_EFLAGS(pEFlags);
529 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
530 IEM_MC_ADVANCE_RIP_AND_FINISH();
531 IEM_MC_END();
532 }
533 }
534 else
535 {
536 /*
537 * Register, memory.
538 */
539 if (pVCpu->iem.s.uVexLength)
540 {
541 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
542 IEM_MC_LOCAL(RTUINT256U, uSrc1);
543 IEM_MC_LOCAL(RTUINT256U, uSrc2);
544 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
545 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
546 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
547 IEM_MC_ARG(uint32_t *, pEFlags, 2);
548
549 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
550 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
551 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
552 IEM_MC_PREPARE_AVX_USAGE();
553
554 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
555 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
556 IEM_MC_REF_EFLAGS(pEFlags);
557 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
558 puSrc1, puSrc2, pEFlags);
559
560 IEM_MC_ADVANCE_RIP_AND_FINISH();
561 IEM_MC_END();
562 }
563 else
564 {
565 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
566 IEM_MC_LOCAL(RTUINT128U, uSrc2);
567 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
568 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
569 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
570 IEM_MC_ARG(uint32_t *, pEFlags, 2);
571
572 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
573 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
574 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
575 IEM_MC_PREPARE_AVX_USAGE();
576
577 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
578 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
579 IEM_MC_REF_EFLAGS(pEFlags);
580 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
581
582 IEM_MC_ADVANCE_RIP_AND_FINISH();
583 IEM_MC_END();
584 }
585 }
586}
587
588
589/* Opcode VEX.0F38 0x18 - invalid */
590
591
592/** Opcode VEX.66.0F38 0x18. */
593FNIEMOP_DEF(iemOp_vbroadcastss_Vx_Wd)
594{
595 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTSS, vbroadcastss, Vx, Wx, DISOPTYPE_HARMLESS, 0);
596 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
597 if (IEM_IS_MODRM_REG_MODE(bRm))
598 {
599 /*
600 * Register, register.
601 */
602 if (pVCpu->iem.s.uVexLength)
603 {
604 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
605 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
606 IEM_MC_LOCAL(uint32_t, uSrc);
607
608 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
609 IEM_MC_PREPARE_AVX_USAGE();
610
611 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
612 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
613
614 IEM_MC_ADVANCE_RIP_AND_FINISH();
615 IEM_MC_END();
616 }
617 else
618 {
619 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
620 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
621 IEM_MC_LOCAL(uint32_t, uSrc);
622
623 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
624 IEM_MC_PREPARE_AVX_USAGE();
625 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
626 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
627
628 IEM_MC_ADVANCE_RIP_AND_FINISH();
629 IEM_MC_END();
630 }
631 }
632 else
633 {
634 /*
635 * Register, memory.
636 */
637 if (pVCpu->iem.s.uVexLength)
638 {
639 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
640 IEM_MC_LOCAL(uint32_t, uSrc);
641 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
642
643 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
644 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
645 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
646 IEM_MC_PREPARE_AVX_USAGE();
647
648 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
649 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
650
651 IEM_MC_ADVANCE_RIP_AND_FINISH();
652 IEM_MC_END();
653 }
654 else
655 {
656 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
657 IEM_MC_LOCAL(uint32_t, uSrc);
658 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
659
660 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
661 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
662 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
663 IEM_MC_PREPARE_AVX_USAGE();
664
665 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
666 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
667
668 IEM_MC_ADVANCE_RIP_AND_FINISH();
669 IEM_MC_END();
670 }
671 }
672}
673
674
675/* Opcode VEX.0F38 0x19 - invalid */
676
677
678/** Opcode VEX.66.0F38 0x19. */
679FNIEMOP_DEF(iemOp_vbroadcastsd_Vqq_Wq)
680{
681 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTSD, vbroadcastsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
682 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
683 if (IEM_IS_MODRM_REG_MODE(bRm))
684 {
685 /*
686 * Register, register.
687 */
688 if (pVCpu->iem.s.uVexLength)
689 {
690 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
691 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
692 IEM_MC_LOCAL(uint64_t, uSrc);
693
694 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
695 IEM_MC_PREPARE_AVX_USAGE();
696
697 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
698 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
699
700 IEM_MC_ADVANCE_RIP_AND_FINISH();
701 IEM_MC_END();
702 }
703 else
704 {
705 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
706 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
707 IEM_MC_LOCAL(uint64_t, uSrc);
708
709 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
710 IEM_MC_PREPARE_AVX_USAGE();
711 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
712 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
713
714 IEM_MC_ADVANCE_RIP_AND_FINISH();
715 IEM_MC_END();
716 }
717 }
718 else
719 {
720 /*
721 * Register, memory.
722 */
723 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
724 IEM_MC_LOCAL(uint64_t, uSrc);
725 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
726
727 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
728 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
729 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
730 IEM_MC_PREPARE_AVX_USAGE();
731
732 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
733 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
734
735 IEM_MC_ADVANCE_RIP_AND_FINISH();
736 IEM_MC_END();
737 }
738}
739
740
741/* Opcode VEX.0F38 0x1a - invalid */
742
743
744/** Opcode VEX.66.0F38 0x1a. */
745FNIEMOP_DEF(iemOp_vbroadcastf128_Vqq_Mdq)
746{
747 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTF128, vbroadcastf128, Vx, Wx, DISOPTYPE_HARMLESS, 0);
748 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
749 if (IEM_IS_MODRM_REG_MODE(bRm))
750 {
751 /*
752 * No register, register.
753 */
754 IEMOP_RAISE_INVALID_OPCODE_RET();
755 }
756 else
757 {
758 /*
759 * Register, memory.
760 */
761 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
762 IEM_MC_LOCAL(RTUINT128U, uSrc);
763 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
764
765 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
766 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
767 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
768 IEM_MC_PREPARE_AVX_USAGE();
769
770 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
771 IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
772
773 IEM_MC_ADVANCE_RIP_AND_FINISH();
774 IEM_MC_END();
775 }
776}
777
778
779/* Opcode VEX.0F38 0x1b - invalid */
780/* Opcode VEX.66.0F38 0x1b - invalid */
781/* Opcode VEX.0F38 0x1c - invalid. */
782
783
784/** Opcode VEX.66.0F38 0x1c. */
785FNIEMOP_DEF(iemOp_vpabsb_Vx_Wx)
786{
787 IEMOP_MNEMONIC2(VEX_RM, VPABSB, vpabsb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
788 IEMOPMEDIAOPTF2_INIT_VARS(vpabsb);
789 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
790}
791
792
793/* Opcode VEX.0F38 0x1d - invalid. */
794
795
796/** Opcode VEX.66.0F38 0x1d. */
797FNIEMOP_DEF(iemOp_vpabsw_Vx_Wx)
798{
799 IEMOP_MNEMONIC2(VEX_RM, VPABSW, vpabsw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
800 IEMOPMEDIAOPTF2_INIT_VARS(vpabsw);
801 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
802}
803
804/* Opcode VEX.0F38 0x1e - invalid. */
805
806
807/** Opcode VEX.66.0F38 0x1e. */
808FNIEMOP_DEF(iemOp_vpabsd_Vx_Wx)
809{
810 IEMOP_MNEMONIC2(VEX_RM, VPABSD, vpabsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
811 IEMOPMEDIAOPTF2_INIT_VARS(vpabsd);
812 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
813}
814
815
816/* Opcode VEX.0F38 0x1f - invalid */
817/* Opcode VEX.66.0F38 0x1f - invalid */
818
819
820/** Body for the vpmov{s,z}x* instructions. */
821#define IEMOP_BODY_VPMOV_S_Z(a_Instr, a_SrcWidth, a_VexLengthMemFetch) \
822 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
823 if (IEM_IS_MODRM_REG_MODE(bRm)) \
824 { \
825 /* \
826 * Register, register. \
827 */ \
828 if (pVCpu->iem.s.uVexLength) \
829 { \
830 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
831 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
832 IEM_MC_LOCAL(RTUINT256U, uDst); \
833 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
834 IEM_MC_ARG(PCRTUINT128U, puSrc, 1); \
835 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
836 IEM_MC_PREPARE_AVX_USAGE(); \
837 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
838 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
839 iemAImpl_ ## a_Instr ## _u256_fallback), \
840 puDst, puSrc); \
841 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
842 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
843 IEM_MC_END(); \
844 } \
845 else \
846 { \
847 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
848 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
849 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
850 IEM_MC_ARG(uint ## a_SrcWidth ##_t, uSrc, 1); \
851 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
852 IEM_MC_PREPARE_AVX_USAGE(); \
853 IEM_MC_FETCH_XREG_U ## a_SrcWidth (uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0); \
854 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
855 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
856 iemAImpl_## a_Instr ## _u128_fallback), \
857 puDst, uSrc); \
858 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
859 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
860 IEM_MC_END(); \
861 } \
862 } \
863 else \
864 { \
865 /* \
866 * Register, memory. \
867 */ \
868 if (pVCpu->iem.s.uVexLength) \
869 { \
870 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
871 IEM_MC_LOCAL(RTUINT256U, uDst); \
872 IEM_MC_LOCAL(RTUINT128U, uSrc); \
873 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
874 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
875 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1); \
876 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
877 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
878 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
879 IEM_MC_PREPARE_AVX_USAGE(); \
880 a_VexLengthMemFetch(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
881 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
882 iemAImpl_ ## a_Instr ## _u256_fallback), \
883 puDst, puSrc); \
884 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
885 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
886 IEM_MC_END(); \
887 } \
888 else \
889 { \
890 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
891 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
892 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
893 IEM_MC_ARG(uint ## a_SrcWidth ##_t, uSrc, 1); \
894 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
895 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
896 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
897 IEM_MC_PREPARE_AVX_USAGE(); \
898 IEM_MC_FETCH_MEM_U ## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
899 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
900 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
901 iemAImpl_ ## a_Instr ## _u128_fallback), \
902 puDst, uSrc); \
903 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
904 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
905 IEM_MC_END(); \
906 } \
907 } \
908 (void)0
909
910/** Opcode VEX.66.0F38 0x20. */
911FNIEMOP_DEF(iemOp_vpmovsxbw_Vx_UxMq)
912{
913 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
914 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBW, vpmovsxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
915 IEMOP_BODY_VPMOV_S_Z(vpmovsxbw, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
916}
917
918
919/** Opcode VEX.66.0F38 0x21. */
920FNIEMOP_DEF(iemOp_vpmovsxbd_Vx_UxMd)
921{
922 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
923 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBD, vpmovsxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
924 IEMOP_BODY_VPMOV_S_Z(vpmovsxbd, 32, IEM_MC_FETCH_MEM_U128);
925}
926
927
928/** Opcode VEX.66.0F38 0x22. */
929FNIEMOP_DEF(iemOp_vpmovsxbq_Vx_UxMw)
930{
931 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
932 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBQ, vpmovsxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
933 IEMOP_BODY_VPMOV_S_Z(vpmovsxbq, 16, IEM_MC_FETCH_MEM_U128);
934}
935
936
937/** Opcode VEX.66.0F38 0x23. */
938FNIEMOP_DEF(iemOp_vpmovsxwd_Vx_UxMq)
939{
940 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
941 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWD, vpmovsxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
942 IEMOP_BODY_VPMOV_S_Z(vpmovsxwd, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
943}
944
945
946/** Opcode VEX.66.0F38 0x24. */
947FNIEMOP_DEF(iemOp_vpmovsxwq_Vx_UxMd)
948{
949 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
950 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWQ, vpmovsxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
951 IEMOP_BODY_VPMOV_S_Z(vpmovsxwq, 32, IEM_MC_FETCH_MEM_U128);
952}
953
954
955/** Opcode VEX.66.0F38 0x25. */
956FNIEMOP_DEF(iemOp_vpmovsxdq_Vx_UxMq)
957{
958 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
959 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXDQ, vpmovsxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
960 IEMOP_BODY_VPMOV_S_Z(vpmovsxdq, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
961}
962
963
964/* Opcode VEX.66.0F38 0x26 - invalid */
965/* Opcode VEX.66.0F38 0x27 - invalid */
966
967
968/** Opcode VEX.66.0F38 0x28. */
969FNIEMOP_DEF(iemOp_vpmuldq_Vx_Hx_Wx)
970{
971 IEMOP_MNEMONIC3(VEX_RVM, VPMULDQ, vpmuldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
972 IEMOPMEDIAOPTF3_INIT_VARS(vpmuldq);
973 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
974}
975
976
977/** Opcode VEX.66.0F38 0x29. */
978FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
979{
980 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
981 IEMOPMEDIAOPTF3_INIT_VARS(vpcmpeqq);
982 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
983}
984
985
986FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
987{
988 Assert(pVCpu->iem.s.uVexLength <= 1);
989 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
990 if (IEM_IS_MODRM_MEM_MODE(bRm))
991 {
992 if (pVCpu->iem.s.uVexLength == 0)
993 {
994 /**
995 * @opcode 0x2a
996 * @opcodesub !11 mr/reg vex.l=0
997 * @oppfx 0x66
998 * @opcpuid avx
999 * @opgroup og_avx_cachect
1000 * @opxcpttype 1
1001 * @optest op1=-1 op2=2 -> op1=2
1002 * @optest op1=0 op2=-42 -> op1=-42
1003 */
1004 /* 128-bit: Memory, register. */
1005 IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
1006 DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1007 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1008 IEM_MC_LOCAL(RTUINT128U, uSrc);
1009 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1010
1011 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1012 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1013 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1014 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1015
1016 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1017 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1018
1019 IEM_MC_ADVANCE_RIP_AND_FINISH();
1020 IEM_MC_END();
1021 }
1022 else
1023 {
1024 /**
1025 * @opdone
1026 * @opcode 0x2a
1027 * @opcodesub !11 mr/reg vex.l=1
1028 * @oppfx 0x66
1029 * @opcpuid avx2
1030 * @opgroup og_avx2_cachect
1031 * @opxcpttype 1
1032 * @optest op1=-1 op2=2 -> op1=2
1033 * @optest op1=0 op2=-42 -> op1=-42
1034 */
1035 /* 256-bit: Memory, register. */
1036 IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
1037 DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1038 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1039 IEM_MC_LOCAL(RTUINT256U, uSrc);
1040 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1041
1042 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1043 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1044 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1045 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1046
1047 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1048 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1049
1050 IEM_MC_ADVANCE_RIP_AND_FINISH();
1051 IEM_MC_END();
1052 }
1053 }
1054
1055 /**
1056 * @opdone
1057 * @opmnemonic udvex660f382arg
1058 * @opcode 0x2a
1059 * @opcodesub 11 mr/reg
1060 * @oppfx 0x66
1061 * @opunused immediate
1062 * @opcpuid avx
1063 * @optest ->
1064 */
1065 else
1066 IEMOP_RAISE_INVALID_OPCODE_RET();
1067}
1068
1069
1070/** Opcode VEX.66.0F38 0x2b. */
1071FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
1072{
1073 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1074 IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
1075 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1076}
1077
1078
1079/** Opcode VEX.66.0F38 0x2c. */
1080FNIEMOP_DEF(iemOp_vmaskmovps_Vx_Hx_Mx)
1081{
1082 // IEMOP_MNEMONIC3(RM, VMASKMOVPS, vmaskmovps, Vx, Hx, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
1083 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1084 if (!IEM_IS_MODRM_REG_MODE(bRm))
1085 {
1086 if (pVCpu->iem.s.uVexLength)
1087 {
1088 /*
1089 * YMM [ModRM:reg], YMM [vvvv], memory [ModRM:r/m]
1090 */
1091 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1092 IEM_MC_ARG_CONST(uint8_t, iYRegDst, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 0);
1093 IEM_MC_ARG_CONST(uint8_t, iYRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 1);
1094 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 3);
1095 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1096 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 2);
1097 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1098
1099 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1100 IEM_MC_PREPARE_AVX_USAGE();
1101
1102 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vmaskmovps_load_u256, iYRegDst, iYRegMsk, iEffSeg, GCPtrEffSrc);
1103
1104 IEM_MC_END();
1105 }
1106 else
1107 {
1108 /*
1109 * XMM [ModRM:reg], XMM [vvvv], memory [ModRM:r/m]
1110 */
1111 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1112 IEM_MC_ARG_CONST(uint8_t, iXRegDst, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 0);
1113 IEM_MC_ARG_CONST(uint8_t, iXRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 1);
1114 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 3);
1115 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1116 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 2);
1117 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1118
1119 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1120 IEM_MC_PREPARE_AVX_USAGE();
1121
1122 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vmaskmovps_load_u128, iXRegDst, iXRegMsk, iEffSeg, GCPtrEffSrc);
1123
1124 IEM_MC_END();
1125 }
1126 }
1127 else
1128 {
1129 /* The register, register encoding is invalid. */
1130 IEMOP_RAISE_INVALID_OPCODE_RET();
1131 }
1132}
1133
1134
1135/** Opcode VEX.66.0F38 0x2d. */
1136FNIEMOP_DEF(iemOp_vmaskmovpd_Vx_Hx_Mx)
1137{
1138 // IEMOP_MNEMONIC3(RM, VMASKMOVPD, vmaskmovpd, Vx, Hx, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
1139 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1140 if (!IEM_IS_MODRM_REG_MODE(bRm))
1141 {
1142 if (pVCpu->iem.s.uVexLength)
1143 {
1144 /*
1145 * YMM [ModRM:reg], YMM [vvvv], memory [ModRM:r/m]
1146 */
1147 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1148 IEM_MC_ARG_CONST(uint8_t, iYRegDst, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 0);
1149 IEM_MC_ARG_CONST(uint8_t, iYRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 1);
1150 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 3);
1151 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1152 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 2);
1153 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1154
1155 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1156 IEM_MC_PREPARE_AVX_USAGE();
1157
1158 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vmaskmovpd_load_u256, iYRegDst, iYRegMsk, iEffSeg, GCPtrEffSrc);
1159
1160 IEM_MC_END();
1161 }
1162 else
1163 {
1164 /*
1165 * XMM [ModRM:reg], XMM [vvvv], memory [ModRM:r/m]
1166 */
1167 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1168 IEM_MC_ARG_CONST(uint8_t, iXRegDst, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 0);
1169 IEM_MC_ARG_CONST(uint8_t, iXRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 1);
1170 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 3);
1171 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1172 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 2);
1173 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1174
1175 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1176 IEM_MC_PREPARE_AVX_USAGE();
1177
1178 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vmaskmovpd_load_u128, iXRegDst, iXRegMsk, iEffSeg, GCPtrEffSrc);
1179
1180 IEM_MC_END();
1181 }
1182 }
1183 else
1184 {
1185 /* The register, register encoding is invalid. */
1186 IEMOP_RAISE_INVALID_OPCODE_RET();
1187 }
1188}
1189
1190
1191/** Opcode VEX.66.0F38 0x2e. */
1192FNIEMOP_DEF(iemOp_vmaskmovps_Mx_Hx_Vx)
1193{
1194 // IEMOP_MNEMONIC3(RM, VMASKMOVPS, vmaskmovps, Mx, Hx, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
1195 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1196 if (!IEM_IS_MODRM_REG_MODE(bRm))
1197 {
1198 if (pVCpu->iem.s.uVexLength)
1199 {
1200 /*
1201 * memory [ModRM:r/m], YMM [vvvv], YMM [ModRM:reg]
1202 */
1203 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1204
1205 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
1206 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1207 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1208 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1209 IEM_MC_ARG_CONST(uint8_t, iYRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 2);
1210 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 3);
1211
1212 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1213 IEM_MC_PREPARE_AVX_USAGE();
1214
1215 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vmaskmovps_store_u256, iEffSeg, GCPtrEffDst, iYRegMsk, iYRegSrc);
1216
1217 IEM_MC_END();
1218 }
1219 else
1220 {
1221 /*
1222 * memory [ModRM:r/m], XMM [vvvv], XMM [ModRM:reg]
1223 */
1224 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1225
1226 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
1227 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1228 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1229 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1230 IEM_MC_ARG_CONST(uint8_t, iXRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 2);
1231 IEM_MC_ARG_CONST(uint8_t, iXRegSrc, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 3);
1232
1233 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1234 IEM_MC_PREPARE_AVX_USAGE();
1235
1236 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vmaskmovps_store_u128, iEffSeg, GCPtrEffDst, iXRegMsk, iXRegSrc);
1237
1238 IEM_MC_END();
1239 }
1240 }
1241 else
1242 {
1243 /* The register, register encoding is invalid. */
1244 IEMOP_RAISE_INVALID_OPCODE_RET();
1245 }
1246}
1247
1248
1249/** Opcode VEX.66.0F38 0x2f. */
1250FNIEMOP_DEF(iemOp_vmaskmovpd_Mx_Hx_Vx)
1251{
1252 // IEMOP_MNEMONIC3(RM, VMASKMOVPD, vmaskmovpd, Mx, Hx, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
1253 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1254 if (!IEM_IS_MODRM_REG_MODE(bRm))
1255 {
1256 if (pVCpu->iem.s.uVexLength)
1257 {
1258 /*
1259 * memory [ModRM:r/m], YMM [vvvv], YMM [ModRM:reg]
1260 */
1261 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1262
1263 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
1264 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1265 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1266 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1267 IEM_MC_ARG_CONST(uint8_t, iYRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 2);
1268 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 3);
1269
1270 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1271 IEM_MC_PREPARE_AVX_USAGE();
1272
1273 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vmaskmovpd_store_u256, iEffSeg, GCPtrEffDst, iYRegMsk, iYRegSrc);
1274
1275 IEM_MC_END();
1276 }
1277 else
1278 {
1279 /*
1280 * memory [ModRM:r/m], XMM [vvvv], XMM [ModRM:reg]
1281 */
1282 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1283
1284 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
1285 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1286 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1287 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1288 IEM_MC_ARG_CONST(uint8_t, iXRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 2);
1289 IEM_MC_ARG_CONST(uint8_t, iXRegSrc, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 3);
1290
1291 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1292 IEM_MC_PREPARE_AVX_USAGE();
1293
1294 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vmaskmovpd_store_u128, iEffSeg, GCPtrEffDst, iXRegMsk, iXRegSrc);
1295
1296 IEM_MC_END();
1297 }
1298 }
1299 else
1300 {
1301 /* The register, register encoding is invalid. */
1302 IEMOP_RAISE_INVALID_OPCODE_RET();
1303 }
1304}
1305
1306
1307/** Opcode VEX.66.0F38 0x30. */
1308FNIEMOP_DEF(iemOp_vpmovzxbw_Vx_UxMq)
1309{
1310 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1311 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBW, vpmovzxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
1312 IEMOP_BODY_VPMOV_S_Z(vpmovzxbw, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
1313}
1314
1315
1316/** Opcode VEX.66.0F38 0x31. */
1317FNIEMOP_DEF(iemOp_vpmovzxbd_Vx_UxMd)
1318{
1319 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1320 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBD, vpmovzxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
1321 IEMOP_BODY_VPMOV_S_Z(vpmovzxbd, 32, IEM_MC_FETCH_MEM_U128);
1322}
1323
1324
1325/** Opcode VEX.66.0F38 0x32. */
1326FNIEMOP_DEF(iemOp_vpmovzxbq_Vx_UxMw)
1327{
1328 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1329 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBQ, vpmovzxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
1330 IEMOP_BODY_VPMOV_S_Z(vpmovzxbq, 16, IEM_MC_FETCH_MEM_U128);
1331}
1332
1333
1334/** Opcode VEX.66.0F38 0x33. */
1335FNIEMOP_DEF(iemOp_vpmovzxwd_Vx_UxMq)
1336{
1337 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1338 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWD, vpmovzxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
1339 IEMOP_BODY_VPMOV_S_Z(vpmovzxwd, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
1340}
1341
1342
1343/** Opcode VEX.66.0F38 0x34. */
1344FNIEMOP_DEF(iemOp_vpmovzxwq_Vx_UxMd)
1345{
1346 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1347 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWQ, vpmovzxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
1348 IEMOP_BODY_VPMOV_S_Z(vpmovzxwq, 32, IEM_MC_FETCH_MEM_U128);
1349}
1350
1351
1352/** Opcode VEX.66.0F38 0x35. */
1353FNIEMOP_DEF(iemOp_vpmovzxdq_Vx_UxMq)
1354{
1355 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1356 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXDQ, vpmovzxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
1357 IEMOP_BODY_VPMOV_S_Z(vpmovzxdq, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
1358}
1359
1360
1361/* Opcode VEX.66.0F38 0x36. */
1362FNIEMOP_DEF(iemOp_vpermd_Vqq_Hqq_Wqq)
1363{
1364 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1365 if (IEM_IS_MODRM_REG_MODE(bRm))
1366 {
1367 /*
1368 * Register, register.
1369 */
1370 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1371 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1372 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1373 IEM_MC_PREPARE_AVX_USAGE();
1374 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1375 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1376 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1377 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1378 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1379 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1380 IEM_MC_LOCAL(RTUINT256U, uDst);
1381 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1382 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback),
1383 puDst, puSrc1, puSrc2);
1384 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1385 IEM_MC_ADVANCE_RIP_AND_FINISH();
1386 IEM_MC_END();
1387 }
1388 else
1389 {
1390 /*
1391 * Register, memory.
1392 */
1393 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1394 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1395 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1396 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1397 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1398 IEM_MC_PREPARE_AVX_USAGE();
1399 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1400 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1401 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1402 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1403 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1404 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1405 IEM_MC_LOCAL(RTUINT256U, uDst);
1406 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1407 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback),
1408 puDst, puSrc1, puSrc2);
1409 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1410 IEM_MC_ADVANCE_RIP_AND_FINISH();
1411 IEM_MC_END();
1412 }
1413}
1414
1415
1416/** Opcode VEX.66.0F38 0x37. */
1417FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
1418{
1419 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1420 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtq);
1421 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1422}
1423
1424
1425/** Opcode VEX.66.0F38 0x38. */
1426FNIEMOP_DEF(iemOp_vpminsb_Vx_Hx_Wx)
1427{
1428 IEMOP_MNEMONIC3(VEX_RVM, VPMINSB, vpminsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1429 IEMOPMEDIAOPTF3_INIT_VARS( vpminsb);
1430 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1431}
1432
1433
1434/** Opcode VEX.66.0F38 0x39. */
1435FNIEMOP_DEF(iemOp_vpminsd_Vx_Hx_Wx)
1436{
1437 IEMOP_MNEMONIC3(VEX_RVM, VPMINSD, vpminsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1438 IEMOPMEDIAOPTF3_INIT_VARS( vpminsd);
1439 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1440}
1441
1442
1443/** Opcode VEX.66.0F38 0x3a. */
1444FNIEMOP_DEF(iemOp_vpminuw_Vx_Hx_Wx)
1445{
1446 IEMOP_MNEMONIC3(VEX_RVM, VPMINUW, vpminuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1447 IEMOPMEDIAOPTF3_INIT_VARS( vpminuw);
1448 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1449}
1450
1451
1452/** Opcode VEX.66.0F38 0x3b. */
1453FNIEMOP_DEF(iemOp_vpminud_Vx_Hx_Wx)
1454{
1455 IEMOP_MNEMONIC3(VEX_RVM, VPMINUD, vpminud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1456 IEMOPMEDIAOPTF3_INIT_VARS( vpminud);
1457 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1458}
1459
1460
1461/** Opcode VEX.66.0F38 0x3c. */
1462FNIEMOP_DEF(iemOp_vpmaxsb_Vx_Hx_Wx)
1463{
1464 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSB, vpmaxsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1465 IEMOPMEDIAOPTF3_INIT_VARS( vpmaxsb);
1466 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1467}
1468
1469
1470/** Opcode VEX.66.0F38 0x3d. */
1471FNIEMOP_DEF(iemOp_vpmaxsd_Vx_Hx_Wx)
1472{
1473 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSD, vpmaxsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1474 IEMOPMEDIAOPTF3_INIT_VARS( vpmaxsd);
1475 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1476}
1477
1478
1479/** Opcode VEX.66.0F38 0x3e. */
1480FNIEMOP_DEF(iemOp_vpmaxuw_Vx_Hx_Wx)
1481{
1482 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUW, vpmaxuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1483 IEMOPMEDIAOPTF3_INIT_VARS( vpmaxuw);
1484 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1485}
1486
1487
1488/** Opcode VEX.66.0F38 0x3f. */
1489FNIEMOP_DEF(iemOp_vpmaxud_Vx_Hx_Wx)
1490{
1491 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUD, vpmaxud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1492 IEMOPMEDIAOPTF3_INIT_VARS( vpmaxud);
1493 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1494}
1495
1496
1497/** Opcode VEX.66.0F38 0x40. */
1498FNIEMOP_DEF(iemOp_vpmulld_Vx_Hx_Wx)
1499{
1500 IEMOP_MNEMONIC3(VEX_RVM, VPMULLD, vpmulld, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1501 IEMOPMEDIAOPTF3_INIT_VARS(vpmulld);
1502 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1503}
1504
1505
1506/** Opcode VEX.66.0F38 0x41. */
1507FNIEMOP_DEF(iemOp_vphminposuw_Vdq_Wdq)
1508{
1509 IEMOP_MNEMONIC2(VEX_RM, VPHMINPOSUW, vphminposuw, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1510 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1511 if (IEM_IS_MODRM_REG_MODE(bRm))
1512 {
1513 /*
1514 * Register, register.
1515 */
1516 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1517 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1518 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1519 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1520 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1521 IEM_MC_PREPARE_AVX_USAGE();
1522 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1523 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1524 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback),
1525 puDst, puSrc);
1526 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1527 IEM_MC_ADVANCE_RIP_AND_FINISH();
1528 IEM_MC_END();
1529 }
1530 else
1531 {
1532 /*
1533 * Register, memory.
1534 */
1535 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1536 IEM_MC_LOCAL(RTUINT128U, uSrc);
1537 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1538 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1539 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1540
1541 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1542 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1543 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1544 IEM_MC_PREPARE_AVX_USAGE();
1545
1546 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1547 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1548 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback),
1549 puDst, puSrc);
1550 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1551
1552 IEM_MC_ADVANCE_RIP_AND_FINISH();
1553 IEM_MC_END();
1554 }
1555}
1556
1557
1558/* Opcode VEX.66.0F38 0x42 - invalid. */
1559/* Opcode VEX.66.0F38 0x43 - invalid. */
1560/* Opcode VEX.66.0F38 0x44 - invalid. */
1561
1562
1563/** Opcode VEX.66.0F38 0x45. */
1564FNIEMOP_DEF(iemOp_vpsrlvd_q_Vx_Hx_Wx)
1565{
1566 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1567 {
1568 IEMOP_MNEMONIC3(VEX_RVM, VPSRLVQ, vpsrlvq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1569 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlvq);
1570 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1571 }
1572 else
1573 {
1574 /**
1575 * @opdone
1576 */
1577 IEMOP_MNEMONIC3(VEX_RVM, VPSRLVD, vpsrlvd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1578 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlvd);
1579 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1580 }
1581}
1582
1583
1584/** Opcode VEX.66.0F38 0x46. */
1585FNIEMOP_DEF(iemOp_vpsravd_Vx_Hx_Wx)
1586{
1587 IEMOP_MNEMONIC3(VEX_RVM, VPSRAVD, vpsravd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1588 IEMOPMEDIAOPTF3_INIT_VARS(vpsravd);
1589 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1590}
1591
1592
1593/** Opcode VEX.66.0F38 0x47. */
1594FNIEMOP_DEF(iemOp_vpsllvd_q_Vx_Hx_Wx)
1595{
1596 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1597 {
1598 IEMOP_MNEMONIC3(VEX_RVM, VPSLLVQ, vpsllvq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1599 IEMOPMEDIAOPTF3_INIT_VARS(vpsllvq);
1600 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1601 }
1602 else
1603 {
1604 /**
1605 * @opdone
1606 */
1607 IEMOP_MNEMONIC3(VEX_RVM, VPSLLVD, vpsllvd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1608 IEMOPMEDIAOPTF3_INIT_VARS(vpsllvd);
1609 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1610 }
1611}
1612
1613
1614/* Opcode VEX.66.0F38 0x48 - invalid. */
1615/* Opcode VEX.66.0F38 0x49 - invalid. */
1616/* Opcode VEX.66.0F38 0x4a - invalid. */
1617/* Opcode VEX.66.0F38 0x4b - invalid. */
1618/* Opcode VEX.66.0F38 0x4c - invalid. */
1619/* Opcode VEX.66.0F38 0x4d - invalid. */
1620/* Opcode VEX.66.0F38 0x4e - invalid. */
1621/* Opcode VEX.66.0F38 0x4f - invalid. */
1622
1623/* Opcode VEX.66.0F38 0x50 - invalid. */
1624/* Opcode VEX.66.0F38 0x51 - invalid. */
1625/* Opcode VEX.66.0F38 0x52 - invalid. */
1626/* Opcode VEX.66.0F38 0x53 - invalid. */
1627/* Opcode VEX.66.0F38 0x54 - invalid. */
1628/* Opcode VEX.66.0F38 0x55 - invalid. */
1629/* Opcode VEX.66.0F38 0x56 - invalid. */
1630/* Opcode VEX.66.0F38 0x57 - invalid. */
1631
1632
1633/** Opcode VEX.66.0F38 0x58. */
1634FNIEMOP_DEF(iemOp_vpbroadcastd_Vx_Wx)
1635{
1636 IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTD, vpbroadcastd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1637 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1638 if (IEM_IS_MODRM_REG_MODE(bRm))
1639 {
1640 /*
1641 * Register, register.
1642 */
1643 if (pVCpu->iem.s.uVexLength)
1644 {
1645 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1646 IEM_MC_LOCAL(uint32_t, uSrc);
1647
1648 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1649 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1650 IEM_MC_PREPARE_AVX_USAGE();
1651
1652 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1653 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1654
1655 IEM_MC_ADVANCE_RIP_AND_FINISH();
1656 IEM_MC_END();
1657 }
1658 else
1659 {
1660 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1661 IEM_MC_LOCAL(uint32_t, uSrc);
1662
1663 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1664 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1665 IEM_MC_PREPARE_AVX_USAGE();
1666 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1667 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1668
1669 IEM_MC_ADVANCE_RIP_AND_FINISH();
1670 IEM_MC_END();
1671 }
1672 }
1673 else
1674 {
1675 /*
1676 * Register, memory.
1677 */
1678 if (pVCpu->iem.s.uVexLength)
1679 {
1680 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1681 IEM_MC_LOCAL(uint32_t, uSrc);
1682 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1683
1684 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1685 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1686 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1687 IEM_MC_PREPARE_AVX_USAGE();
1688
1689 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1690 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1691
1692 IEM_MC_ADVANCE_RIP_AND_FINISH();
1693 IEM_MC_END();
1694 }
1695 else
1696 {
1697 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1698 IEM_MC_LOCAL(uint32_t, uSrc);
1699 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1700
1701 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1702 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1703 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1704 IEM_MC_PREPARE_AVX_USAGE();
1705
1706 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1707 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1708
1709 IEM_MC_ADVANCE_RIP_AND_FINISH();
1710 IEM_MC_END();
1711 }
1712 }
1713}
1714
1715
1716/** Opcode VEX.66.0F38 0x59. */
1717FNIEMOP_DEF(iemOp_vpbroadcastq_Vx_Wx)
1718{
1719 IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTQ, vpbroadcastq, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1720 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1721 if (IEM_IS_MODRM_REG_MODE(bRm))
1722 {
1723 /*
1724 * Register, register.
1725 */
1726 if (pVCpu->iem.s.uVexLength)
1727 {
1728 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1729 IEM_MC_LOCAL(uint64_t, uSrc);
1730
1731 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1732 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1733 IEM_MC_PREPARE_AVX_USAGE();
1734
1735 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1736 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1737
1738 IEM_MC_ADVANCE_RIP_AND_FINISH();
1739 IEM_MC_END();
1740 }
1741 else
1742 {
1743 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1744 IEM_MC_LOCAL(uint64_t, uSrc);
1745
1746 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1747 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1748 IEM_MC_PREPARE_AVX_USAGE();
1749 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1750 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1751
1752 IEM_MC_ADVANCE_RIP_AND_FINISH();
1753 IEM_MC_END();
1754 }
1755 }
1756 else
1757 {
1758 /*
1759 * Register, memory.
1760 */
1761 if (pVCpu->iem.s.uVexLength)
1762 {
1763 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1764 IEM_MC_LOCAL(uint64_t, uSrc);
1765 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1766
1767 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1768 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1769 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1770 IEM_MC_PREPARE_AVX_USAGE();
1771
1772 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1773 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1774
1775 IEM_MC_ADVANCE_RIP_AND_FINISH();
1776 IEM_MC_END();
1777 }
1778 else
1779 {
1780 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1781 IEM_MC_LOCAL(uint64_t, uSrc);
1782 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1783
1784 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1785 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1786 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1787 IEM_MC_PREPARE_AVX_USAGE();
1788
1789 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1790 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1791
1792 IEM_MC_ADVANCE_RIP_AND_FINISH();
1793 IEM_MC_END();
1794 }
1795 }
1796}
1797
1798
1799/** Opcode VEX.66.0F38 0x5a. */
1800FNIEMOP_DEF(iemOp_vbroadcasti128_Vqq_Mdq)
1801{
1802 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTI128, vbroadcasti128, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1803 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1804 if (IEM_IS_MODRM_REG_MODE(bRm))
1805 {
1806 /*
1807 * No register, register.
1808 */
1809 IEMOP_RAISE_INVALID_OPCODE_RET();
1810 }
1811 else
1812 {
1813 /*
1814 * Register, memory.
1815 */
1816 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1817 IEM_MC_LOCAL(RTUINT128U, uSrc);
1818 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1819
1820 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1821 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
1822 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1823 IEM_MC_PREPARE_AVX_USAGE();
1824
1825 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1826 IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1827
1828 IEM_MC_ADVANCE_RIP_AND_FINISH();
1829 IEM_MC_END();
1830 }
1831}
1832
1833
1834/* Opcode VEX.66.0F38 0x5b - invalid. */
1835/* Opcode VEX.66.0F38 0x5c - invalid. */
1836/* Opcode VEX.66.0F38 0x5d - invalid. */
1837/* Opcode VEX.66.0F38 0x5e - invalid. */
1838/* Opcode VEX.66.0F38 0x5f - invalid. */
1839
1840/* Opcode VEX.66.0F38 0x60 - invalid. */
1841/* Opcode VEX.66.0F38 0x61 - invalid. */
1842/* Opcode VEX.66.0F38 0x62 - invalid. */
1843/* Opcode VEX.66.0F38 0x63 - invalid. */
1844/* Opcode VEX.66.0F38 0x64 - invalid. */
1845/* Opcode VEX.66.0F38 0x65 - invalid. */
1846/* Opcode VEX.66.0F38 0x66 - invalid. */
1847/* Opcode VEX.66.0F38 0x67 - invalid. */
1848/* Opcode VEX.66.0F38 0x68 - invalid. */
1849/* Opcode VEX.66.0F38 0x69 - invalid. */
1850/* Opcode VEX.66.0F38 0x6a - invalid. */
1851/* Opcode VEX.66.0F38 0x6b - invalid. */
1852/* Opcode VEX.66.0F38 0x6c - invalid. */
1853/* Opcode VEX.66.0F38 0x6d - invalid. */
1854/* Opcode VEX.66.0F38 0x6e - invalid. */
1855/* Opcode VEX.66.0F38 0x6f - invalid. */
1856
1857/* Opcode VEX.66.0F38 0x70 - invalid. */
1858/* Opcode VEX.66.0F38 0x71 - invalid. */
1859/* Opcode VEX.66.0F38 0x72 - invalid. */
1860/* Opcode VEX.66.0F38 0x73 - invalid. */
1861/* Opcode VEX.66.0F38 0x74 - invalid. */
1862/* Opcode VEX.66.0F38 0x75 - invalid. */
1863/* Opcode VEX.66.0F38 0x76 - invalid. */
1864/* Opcode VEX.66.0F38 0x77 - invalid. */
1865
1866
1867/** Opcode VEX.66.0F38 0x78. */
1868FNIEMOP_DEF(iemOp_vpbroadcastb_Vx_Wx)
1869{
1870 IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTB, vpbroadcastb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1871 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1872 if (IEM_IS_MODRM_REG_MODE(bRm))
1873 {
1874 /*
1875 * Register, register.
1876 */
1877 if (pVCpu->iem.s.uVexLength)
1878 {
1879 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1880 IEM_MC_LOCAL(uint8_t, uSrc);
1881
1882 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1883 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1884 IEM_MC_PREPARE_AVX_USAGE();
1885
1886 IEM_MC_FETCH_XREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1887 IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1888
1889 IEM_MC_ADVANCE_RIP_AND_FINISH();
1890 IEM_MC_END();
1891 }
1892 else
1893 {
1894 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1895 IEM_MC_LOCAL(uint8_t, uSrc);
1896
1897 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1898 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1899 IEM_MC_PREPARE_AVX_USAGE();
1900 IEM_MC_FETCH_XREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1901 IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1902
1903 IEM_MC_ADVANCE_RIP_AND_FINISH();
1904 IEM_MC_END();
1905 }
1906 }
1907 else
1908 {
1909 /*
1910 * Register, memory.
1911 */
1912 if (pVCpu->iem.s.uVexLength)
1913 {
1914 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1915 IEM_MC_LOCAL(uint8_t, uSrc);
1916 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1917
1918 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1919 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1920 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1921 IEM_MC_PREPARE_AVX_USAGE();
1922
1923 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1924 IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1925
1926 IEM_MC_ADVANCE_RIP_AND_FINISH();
1927 IEM_MC_END();
1928 }
1929 else
1930 {
1931 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1932 IEM_MC_LOCAL(uint8_t, uSrc);
1933 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1934
1935 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1936 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1937 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1938 IEM_MC_PREPARE_AVX_USAGE();
1939
1940 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1941 IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1942
1943 IEM_MC_ADVANCE_RIP_AND_FINISH();
1944 IEM_MC_END();
1945 }
1946 }
1947}
1948
1949
1950/** Opcode VEX.66.0F38 0x79. */
1951FNIEMOP_DEF(iemOp_vpbroadcastw_Vx_Wx)
1952{
1953 IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTW, vpbroadcastw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1954 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1955 if (IEM_IS_MODRM_REG_MODE(bRm))
1956 {
1957 /*
1958 * Register, register.
1959 */
1960 if (pVCpu->iem.s.uVexLength)
1961 {
1962 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1963 IEM_MC_LOCAL(uint16_t, uSrc);
1964
1965 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1966 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1967 IEM_MC_PREPARE_AVX_USAGE();
1968
1969 IEM_MC_FETCH_XREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1970 IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1971
1972 IEM_MC_ADVANCE_RIP_AND_FINISH();
1973 IEM_MC_END();
1974 }
1975 else
1976 {
1977 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1978 IEM_MC_LOCAL(uint16_t, uSrc);
1979
1980 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1981 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1982 IEM_MC_PREPARE_AVX_USAGE();
1983 IEM_MC_FETCH_XREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1984 IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1985
1986 IEM_MC_ADVANCE_RIP_AND_FINISH();
1987 IEM_MC_END();
1988 }
1989 }
1990 else
1991 {
1992 /*
1993 * Register, memory.
1994 */
1995 if (pVCpu->iem.s.uVexLength)
1996 {
1997 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1998 IEM_MC_LOCAL(uint16_t, uSrc);
1999 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2000
2001 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2002 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
2003 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2004 IEM_MC_PREPARE_AVX_USAGE();
2005
2006 IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2007 IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2008
2009 IEM_MC_ADVANCE_RIP_AND_FINISH();
2010 IEM_MC_END();
2011 }
2012 else
2013 {
2014 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2015 IEM_MC_LOCAL(uint16_t, uSrc);
2016 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2017
2018 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2019 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
2020 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2021 IEM_MC_PREPARE_AVX_USAGE();
2022
2023 IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2024 IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2025
2026 IEM_MC_ADVANCE_RIP_AND_FINISH();
2027 IEM_MC_END();
2028 }
2029 }
2030}
2031
2032
2033/* Opcode VEX.66.0F38 0x7a - invalid. */
2034/* Opcode VEX.66.0F38 0x7b - invalid. */
2035/* Opcode VEX.66.0F38 0x7c - invalid. */
2036/* Opcode VEX.66.0F38 0x7d - invalid. */
2037/* Opcode VEX.66.0F38 0x7e - invalid. */
2038/* Opcode VEX.66.0F38 0x7f - invalid. */
2039
2040/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
2041/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
2042/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
2043/* Opcode VEX.66.0F38 0x83 - invalid. */
2044/* Opcode VEX.66.0F38 0x84 - invalid. */
2045/* Opcode VEX.66.0F38 0x85 - invalid. */
2046/* Opcode VEX.66.0F38 0x86 - invalid. */
2047/* Opcode VEX.66.0F38 0x87 - invalid. */
2048/* Opcode VEX.66.0F38 0x88 - invalid. */
2049/* Opcode VEX.66.0F38 0x89 - invalid. */
2050/* Opcode VEX.66.0F38 0x8a - invalid. */
2051/* Opcode VEX.66.0F38 0x8b - invalid. */
2052
2053
2054/** Opcode VEX.66.0F38 0x8c. */
2055FNIEMOP_DEF(iemOp_vpmaskmovd_q_Vx_Hx_Mx)
2056{
2057 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2058 if (!IEM_IS_MODRM_REG_MODE(bRm))
2059 {
2060 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2061 {
2062 // IEMOP_MNEMONIC3(RM, VPMASKMOVQ, vpmaskmovq, Vx, Hx, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
2063 if (pVCpu->iem.s.uVexLength)
2064 {
2065 /*
2066 * YMM [ModRM:reg], YMM [vvvv], memory [ModRM:r/m]
2067 */
2068 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2069 IEM_MC_ARG_CONST(uint8_t, iYRegDst, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 0);
2070 IEM_MC_ARG_CONST(uint8_t, iYRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 1);
2071 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 3);
2072 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2073 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 2);
2074 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2075
2076 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2077 IEM_MC_PREPARE_AVX_USAGE();
2078
2079 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vpmaskmovq_load_u256, iYRegDst, iYRegMsk, iEffSeg, GCPtrEffSrc);
2080
2081 IEM_MC_END();
2082 }
2083 else
2084 {
2085 /*
2086 * XMM [ModRM:reg], XMM [vvvv], memory [ModRM:r/m]
2087 */
2088 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2089 IEM_MC_ARG_CONST(uint8_t, iXRegDst, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 0);
2090 IEM_MC_ARG_CONST(uint8_t, iXRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 1);
2091 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 3);
2092 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2093 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 2);
2094 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2095
2096 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2097 IEM_MC_PREPARE_AVX_USAGE();
2098
2099 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vpmaskmovq_load_u128, iXRegDst, iXRegMsk, iEffSeg, GCPtrEffSrc);
2100
2101 IEM_MC_END();
2102 }
2103 }
2104 else
2105 {
2106 // IEMOP_MNEMONIC3(RM, VPMASKMOVD, vpmaskmovd, Vx, Hx, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
2107 if (pVCpu->iem.s.uVexLength)
2108 {
2109 /*
2110 * YMM [ModRM:reg], YMM [vvvv], memory [ModRM:r/m]
2111 */
2112 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2113 IEM_MC_ARG_CONST(uint8_t, iYRegDst, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 0);
2114 IEM_MC_ARG_CONST(uint8_t, iYRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 1);
2115 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 3);
2116 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2117 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 2);
2118 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2119
2120 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2121 IEM_MC_PREPARE_AVX_USAGE();
2122
2123 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vpmaskmovd_load_u256, iYRegDst, iYRegMsk, iEffSeg, GCPtrEffSrc);
2124
2125 IEM_MC_END();
2126 }
2127 else
2128 {
2129 /*
2130 * XMM [ModRM:reg], XMM [vvvv], memory [ModRM:r/m]
2131 */
2132 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2133 IEM_MC_ARG_CONST(uint8_t, iXRegDst, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 0);
2134 IEM_MC_ARG_CONST(uint8_t, iXRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 1);
2135 IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 3);
2136 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2137 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 2);
2138 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2139
2140 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2141 IEM_MC_PREPARE_AVX_USAGE();
2142
2143 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vpmaskmovd_load_u128, iXRegDst, iXRegMsk, iEffSeg, GCPtrEffSrc);
2144
2145 IEM_MC_END();
2146 }
2147 }
2148 }
2149 else
2150 {
2151 /* The register, register encoding is invalid. */
2152 IEMOP_RAISE_INVALID_OPCODE_RET();
2153 }
2154}
2155
2156
2157/* Opcode VEX.66.0F38 0x8d - invalid. */
2158
2159
2160/** Opcode VEX.66.0F38 0x8e. */
2161FNIEMOP_DEF(iemOp_vpmaskmovd_q_Mx_Vx_Hx)
2162{
2163 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2164 if (!IEM_IS_MODRM_REG_MODE(bRm))
2165 {
2166 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2167 {
2168 // IEMOP_MNEMONIC3(RM, VPMASKMOVQ, vpmaskmovq, Mx, Hx, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
2169 if (pVCpu->iem.s.uVexLength)
2170 {
2171 /*
2172 * memory [ModRM:r/m], YMM [vvvv], YMM [ModRM:reg]
2173 */
2174 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2175
2176 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
2177 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
2178 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
2179 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2180 IEM_MC_ARG_CONST(uint8_t, iYRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 2);
2181 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 3);
2182
2183 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2184 IEM_MC_PREPARE_AVX_USAGE();
2185
2186 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vpmaskmovq_store_u256, iEffSeg, GCPtrEffDst, iYRegMsk, iYRegSrc);
2187
2188 IEM_MC_END();
2189 }
2190 else
2191 {
2192 /*
2193 * memory [ModRM:r/m], XMM [vvvv], XMM [ModRM:reg]
2194 */
2195 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2196
2197 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
2198 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
2199 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
2200 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2201 IEM_MC_ARG_CONST(uint8_t, iXRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 2);
2202 IEM_MC_ARG_CONST(uint8_t, iXRegSrc, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 3);
2203
2204 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2205 IEM_MC_PREPARE_AVX_USAGE();
2206
2207 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vpmaskmovq_store_u128, iEffSeg, GCPtrEffDst, iXRegMsk, iXRegSrc);
2208
2209 IEM_MC_END();
2210 }
2211 }
2212 else
2213 {
2214 // IEMOP_MNEMONIC3(RM, VPMASKMOVD, vpmaskmovd, Mx, Hx, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
2215 if (pVCpu->iem.s.uVexLength)
2216 {
2217 /*
2218 * memory [ModRM:r/m], YMM [vvvv], YMM [ModRM:reg]
2219 */
2220 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2221
2222 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
2223 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
2224 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
2225 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2226 IEM_MC_ARG_CONST(uint8_t, iYRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 2);
2227 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 3);
2228
2229 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2230 IEM_MC_PREPARE_AVX_USAGE();
2231
2232 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vpmaskmovd_store_u256, iEffSeg, GCPtrEffDst, iYRegMsk, iYRegSrc);
2233
2234 IEM_MC_END();
2235 }
2236 else
2237 {
2238 /*
2239 * memory [ModRM:r/m], XMM [vvvv], XMM [ModRM:reg]
2240 */
2241 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2242
2243 IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 1);
2244 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
2245 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
2246 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2247 IEM_MC_ARG_CONST(uint8_t, iXRegMsk, /*=*/ IEM_GET_EFFECTIVE_VVVV(pVCpu), 2);
2248 IEM_MC_ARG_CONST(uint8_t, iXRegSrc, /*=*/ IEM_GET_MODRM_REG(pVCpu, bRm), 3);
2249
2250 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2251 IEM_MC_PREPARE_AVX_USAGE();
2252
2253 IEM_MC_CALL_CIMPL_4(0, 0, iemCImpl_vpmaskmovd_store_u128, iEffSeg, GCPtrEffDst, iXRegMsk, iXRegSrc);
2254
2255 IEM_MC_END();
2256 }
2257 }
2258 }
2259 else
2260 {
2261 /* The register, register encoding is invalid. */
2262 IEMOP_RAISE_INVALID_OPCODE_RET();
2263 }
2264}
2265
2266
2267/* Opcode VEX.66.0F38 0x8f - invalid. */
2268
2269
2270/**
2271 * Common worker for xxgatherxx AVX2 instructions
2272 */
2273FNIEMOP_DEF_1(iemOpCommonAvx2Gather_Vx_Hx_Wx, bool, fIdxQword)
2274{
2275 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2276 if (IEM_IS_MODRM_REG_MODE(bRm))
2277 IEMOP_RAISE_INVALID_OPCODE_RET(); /* no register form */
2278
2279 /* Doing a partial IEM_MC_CALC_RM_EFF_ADDR by hand here. It is simplified
2280 by (V)SIB being a hard requirement. */
2281 if ((bRm & X86_MODRM_RM_MASK) != 4 /*VSIB*/)
2282 IEMOP_RAISE_INVALID_OPCODE_RET();
2283
2284 uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
2285
2286 uint32_t u32Disp = 0; /* Should've been 'offDisp', but python script needs the 'u32' type hint to cope. */
2287 if ((bRm & X86_MODRM_MOD_MASK) == (X86_MOD_MEM1 << X86_MODRM_MOD_SHIFT))
2288 IEM_OPCODE_GET_NEXT_S8_SX_U32(&u32Disp);
2289 else if ((bRm & X86_MODRM_MOD_MASK) == (X86_MOD_MEM4 << X86_MODRM_MOD_SHIFT))
2290 IEM_OPCODE_GET_NEXT_U32(&u32Disp);
2291
2292 /* We pack arguments into a single 32-bit value, because passing them individually
2293 would greatly exceed the max number of arguments the code generator can handle. */
2294 IEMGATHERARGS PackedArgs = {0};
2295 PackedArgs.s.iYRegDst = IEM_GET_MODRM_REG(pVCpu, bRm);
2296 PackedArgs.s.iYRegIdc = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2297 PackedArgs.s.iYRegMsk = IEM_GET_EFFECTIVE_VVVV(pVCpu);
2298 PackedArgs.s.iGRegBase = (bSib & X86_SIB_BASE_MASK) | pVCpu->iem.s.uRexB;
2299 PackedArgs.s.iEffSeg = pVCpu->iem.s.iEffSeg;
2300 if ( (PackedArgs.s.iGRegBase == X86_GREG_xSP || PackedArgs.s.iGRegBase == X86_GREG_xBP)
2301 && !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SEG_MASK))
2302 PackedArgs.s.iEffSeg = X86_SREG_SS;
2303 PackedArgs.s.iScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2304 PackedArgs.s.enmEffOpSize = pVCpu->iem.s.enmEffOpSize;
2305 PackedArgs.s.enmEffAddrMode = pVCpu->iem.s.enmEffAddrMode;
2306 PackedArgs.s.fVex256 = pVCpu->iem.s.uVexLength;
2307 PackedArgs.s.fIdxQword = fIdxQword;
2308 PackedArgs.s.fValQword = (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) ? 1 : 0;
2309
2310 uint32_t const u32PackedArgs = PackedArgs.u; /* Workaround: Python gets confused if we directly use 'PackedArgs.u' below. */
2311
2312 /* Call the C helper: */
2313 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2314 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2315 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2316 IEM_MC_PREPARE_AVX_USAGE();
2317 IEM_MC_ARG_CONST(uint32_t, u32PackedArgsArg, u32PackedArgs, 0);
2318 IEM_MC_ARG_CONST(uint32_t, u32DispArg, u32Disp, 1);
2319 IEM_MC_CALL_CIMPL_2(0, 0, iemCImpl_vpgather_worker_xx, u32PackedArgsArg, u32DispArg);
2320 IEM_MC_END();
2321}
2322
2323/** Opcode VEX.66.0F38 0x90 (vex only). */
2324FNIEMOP_DEF(iemOp_vpgatherdd_q_Vx_Hx_Wx)
2325{
2326 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2327 IEMOP_MNEMONIC3(VEX_RMV_MEM, VPGATHERDQ, vpgatherdq, Vx, MVx, Hx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); /** @todo? */
2328 else
2329 /**
2330 * @opdone
2331 */
2332 IEMOP_MNEMONIC3(VEX_RMV_MEM, VPGATHERDD, vpgatherdd, Vx, MVx, Hx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); /** @todo? */
2333 return FNIEMOP_CALL_1(iemOpCommonAvx2Gather_Vx_Hx_Wx, 0);
2334}
2335
2336/** Opcode VEX.66.0F38 0x91 (vex only). */
2337FNIEMOP_DEF(iemOp_vpgatherqd_q_Vx_Hx_Wx)
2338{
2339 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2340 IEMOP_MNEMONIC3(VEX_RMV_MEM, VPGATHERQQ, vpgatherqq, Vx, MVx, Hx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); /** @todo? */
2341 else
2342 /**
2343 * @opdone
2344 */
2345 IEMOP_MNEMONIC3(VEX_RMV_MEM, VPGATHERQD, vpgatherqd, Vx, MVx, Hx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); /** @todo? */
2346 return FNIEMOP_CALL_1(iemOpCommonAvx2Gather_Vx_Hx_Wx, 1);
2347}
2348
2349/** Opcode VEX.66.0F38 0x92 (vex only). */
2350FNIEMOP_DEF(iemOp_vgatherdps_d_Vx_Hx_Wx)
2351{
2352 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2353 IEMOP_MNEMONIC3(VEX_RMV_MEM, VGATHERDPD, vgatherdpd, Vx, MVx, Hx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); /** @todo? */
2354 else
2355 /**
2356 * @opdone
2357 */
2358 IEMOP_MNEMONIC3(VEX_RMV_MEM, VGATHERDPS, vgatherdps, Vx, MVx, Hx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); /** @todo? */
2359 return FNIEMOP_CALL_1(iemOpCommonAvx2Gather_Vx_Hx_Wx, 0);
2360}
2361
2362/** Opcode VEX.66.0F38 0x93 (vex only). */
2363FNIEMOP_DEF(iemOp_vgatherqps_d_Vx_Hx_Wx)
2364{
2365 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2366 IEMOP_MNEMONIC3(VEX_RMV_MEM, VGATHERQPD, vgatherqpd, Vx, MVx, Hx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); /** @todo? */
2367 else
2368 /**
2369 * @opdone
2370 */
2371 IEMOP_MNEMONIC3(VEX_RMV_MEM, VGATHERQPS, vgatherqps, Vx, MVx, Hx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); /** @todo? */
2372 return FNIEMOP_CALL_1(iemOpCommonAvx2Gather_Vx_Hx_Wx, 1);
2373}
2374
2375/* Opcode VEX.66.0F38 0x94 - invalid. */
2376/* Opcode VEX.66.0F38 0x95 - invalid. */
2377/** Opcode VEX.66.0F38 0x96 (vex only). */
2378FNIEMOP_STUB(iemOp_vfmaddsub132ps_d_Vx_Hx_Wx);
2379/** Opcode VEX.66.0F38 0x97 (vex only). */
2380FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
2381/** Opcode VEX.66.0F38 0x98 (vex only). */
2382FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
2383/** Opcode VEX.66.0F38 0x99 (vex only). */
2384FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
2385/** Opcode VEX.66.0F38 0x9a (vex only). */
2386FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
2387/** Opcode VEX.66.0F38 0x9b (vex only). */
2388FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
2389/** Opcode VEX.66.0F38 0x9c (vex only). */
2390FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
2391/** Opcode VEX.66.0F38 0x9d (vex only). */
2392FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
2393/** Opcode VEX.66.0F38 0x9e (vex only). */
2394FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
2395/** Opcode VEX.66.0F38 0x9f (vex only). */
2396FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
2397
2398/* Opcode VEX.66.0F38 0xa0 - invalid. */
2399/* Opcode VEX.66.0F38 0xa1 - invalid. */
2400/* Opcode VEX.66.0F38 0xa2 - invalid. */
2401/* Opcode VEX.66.0F38 0xa3 - invalid. */
2402/* Opcode VEX.66.0F38 0xa4 - invalid. */
2403/* Opcode VEX.66.0F38 0xa5 - invalid. */
2404/** Opcode VEX.66.0F38 0xa6 (vex only). */
2405FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
2406/** Opcode VEX.66.0F38 0xa7 (vex only). */
2407FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
2408/** Opcode VEX.66.0F38 0xa8 (vex only). */
2409FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
2410/** Opcode VEX.66.0F38 0xa9 (vex only). */
2411FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
2412/** Opcode VEX.66.0F38 0xaa (vex only). */
2413FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
2414/** Opcode VEX.66.0F38 0xab (vex only). */
2415FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
2416/** Opcode VEX.66.0F38 0xac (vex only). */
2417FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
2418/** Opcode VEX.66.0F38 0xad (vex only). */
2419FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
2420/** Opcode VEX.66.0F38 0xae (vex only). */
2421FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
2422/** Opcode VEX.66.0F38 0xaf (vex only). */
2423FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
2424
2425/* Opcode VEX.66.0F38 0xb0 - invalid. */
2426/* Opcode VEX.66.0F38 0xb1 - invalid. */
2427/* Opcode VEX.66.0F38 0xb2 - invalid. */
2428/* Opcode VEX.66.0F38 0xb3 - invalid. */
2429/* Opcode VEX.66.0F38 0xb4 - invalid. */
2430/* Opcode VEX.66.0F38 0xb5 - invalid. */
2431/** Opcode VEX.66.0F38 0xb6 (vex only). */
2432FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
2433/** Opcode VEX.66.0F38 0xb7 (vex only). */
2434FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
2435/** Opcode VEX.66.0F38 0xb8 (vex only). */
2436FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
2437/** Opcode VEX.66.0F38 0xb9 (vex only). */
2438FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
2439/** Opcode VEX.66.0F38 0xba (vex only). */
2440FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
2441/** Opcode VEX.66.0F38 0xbb (vex only). */
2442FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
2443/** Opcode VEX.66.0F38 0xbc (vex only). */
2444FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
2445/** Opcode VEX.66.0F38 0xbd (vex only). */
2446FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
2447/** Opcode VEX.66.0F38 0xbe (vex only). */
2448FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
2449/** Opcode VEX.66.0F38 0xbf (vex only). */
2450FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
2451
2452/* Opcode VEX.0F38 0xc0 - invalid. */
2453/* Opcode VEX.66.0F38 0xc0 - invalid. */
2454/* Opcode VEX.0F38 0xc1 - invalid. */
2455/* Opcode VEX.66.0F38 0xc1 - invalid. */
2456/* Opcode VEX.0F38 0xc2 - invalid. */
2457/* Opcode VEX.66.0F38 0xc2 - invalid. */
2458/* Opcode VEX.0F38 0xc3 - invalid. */
2459/* Opcode VEX.66.0F38 0xc3 - invalid. */
2460/* Opcode VEX.0F38 0xc4 - invalid. */
2461/* Opcode VEX.66.0F38 0xc4 - invalid. */
2462/* Opcode VEX.0F38 0xc5 - invalid. */
2463/* Opcode VEX.66.0F38 0xc5 - invalid. */
2464/* Opcode VEX.0F38 0xc6 - invalid. */
2465/* Opcode VEX.66.0F38 0xc6 - invalid. */
2466/* Opcode VEX.0F38 0xc7 - invalid. */
2467/* Opcode VEX.66.0F38 0xc7 - invalid. */
2468/* Opcode VEX.0F38 0xc8 - invalid. */
2469/* Opcode VEX.66.0F38 0xc8 - invalid. */
2470/* Opcode VEX.0F38 0xc9 - invalid. */
2471/* Opcode VEX.66.0F38 0xc9 - invalid. */
2472/* Opcode VEX.0F38 0xca. */
2473/* Opcode VEX.66.0F38 0xca - invalid. */
2474/* Opcode VEX.0F38 0xcb - invalid. */
2475/* Opcode VEX.66.0F38 0xcb - invalid. */
2476/* Opcode VEX.0F38 0xcc - invalid. */
2477/* Opcode VEX.66.0F38 0xcc - invalid. */
2478/* Opcode VEX.0F38 0xcd - invalid. */
2479/* Opcode VEX.66.0F38 0xcd - invalid. */
2480/* Opcode VEX.0F38 0xce - invalid. */
2481/* Opcode VEX.66.0F38 0xce - invalid. */
2482/* Opcode VEX.0F38 0xcf - invalid. */
2483/* Opcode VEX.66.0F38 0xcf - invalid. */
2484
2485/* Opcode VEX.66.0F38 0xd0 - invalid. */
2486/* Opcode VEX.66.0F38 0xd1 - invalid. */
2487/* Opcode VEX.66.0F38 0xd2 - invalid. */
2488/* Opcode VEX.66.0F38 0xd3 - invalid. */
2489/* Opcode VEX.66.0F38 0xd4 - invalid. */
2490/* Opcode VEX.66.0F38 0xd5 - invalid. */
2491/* Opcode VEX.66.0F38 0xd6 - invalid. */
2492/* Opcode VEX.66.0F38 0xd7 - invalid. */
2493/* Opcode VEX.66.0F38 0xd8 - invalid. */
2494/* Opcode VEX.66.0F38 0xd9 - invalid. */
2495/* Opcode VEX.66.0F38 0xda - invalid. */
2496
2497
2498/** Opcode VEX.66.0F38 0xdb. */
2499FNIEMOP_DEF(iemOp_vaesimc_Vdq_Wdq)
2500{
2501 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2502 if (IEM_IS_MODRM_REG_MODE(bRm))
2503 {
2504 /*
2505 * Register, register.
2506 */
2507 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2508 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX_2(fAvx, fAesNi);
2509 IEM_MC_ARG(PRTUINT128U, puDst, 0);
2510 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2511 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2512 IEM_MC_PREPARE_AVX_USAGE();
2513 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2514 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2515 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback), puDst, puSrc);
2516 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
2517 IEM_MC_ADVANCE_RIP_AND_FINISH();
2518 IEM_MC_END();
2519 }
2520 else
2521 {
2522 /*
2523 * Register, memory.
2524 */
2525 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2526 IEM_MC_ARG(PRTUINT128U, puDst, 0);
2527 IEM_MC_LOCAL(RTUINT128U, uSrc);
2528 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
2529 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2530
2531 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2532 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX_2(fAvx, fAesNi);
2533 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2534 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2535
2536 IEM_MC_PREPARE_AVX_USAGE();
2537 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2538 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback), puDst, puSrc);
2539 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
2540 IEM_MC_ADVANCE_RIP_AND_FINISH();
2541 IEM_MC_END();
2542 }
2543}
2544
2545
2546/** Opcode VEX.66.0F38 0xdc. */
2547FNIEMOP_DEF(iemOp_vaesenc_Vdq_Wdq)
2548{
2549 IEMOP_MNEMONIC3(VEX_RVM, VAESENC, vaesenc, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2550 return FNIEMOP_CALL_1(iemOpCommonAvxAesNi_Vx_Hx_Wx,
2551 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback)); /* ASSUMES fAesNi on the host implies fAvx. */
2552}
2553
2554
2555/** Opcode VEX.66.0F38 0xdd. */
2556FNIEMOP_DEF(iemOp_vaesenclast_Vdq_Wdq)
2557{
2558 IEMOP_MNEMONIC3(VEX_RVM, VAESENCLAST, vaesenclast, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2559 return FNIEMOP_CALL_1(iemOpCommonAvxAesNi_Vx_Hx_Wx,
2560 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback)); /* ASSUMES fAesNi on the host implies fAvx. */
2561}
2562
2563
2564/** Opcode VEX.66.0F38 0xde. */
2565FNIEMOP_DEF(iemOp_vaesdec_Vdq_Wdq)
2566{
2567 IEMOP_MNEMONIC3(VEX_RVM, VAESDEC, vaesdec, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2568 return FNIEMOP_CALL_1(iemOpCommonAvxAesNi_Vx_Hx_Wx,
2569 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback)); /* ASSUMES fAesNi on the host implies fAvx. */
2570}
2571
2572
2573/** Opcode VEX.66.0F38 0xdf. */
2574FNIEMOP_DEF(iemOp_vaesdeclast_Vdq_Wdq)
2575{
2576 IEMOP_MNEMONIC3(VEX_RVM, VAESDECLAST, vaesdeclast, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2577 return FNIEMOP_CALL_1(iemOpCommonAvxAesNi_Vx_Hx_Wx,
2578 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback)); /* ASSUMES fAesNi on the host implies fAvx. */
2579}
2580
2581
2582/* Opcode VEX.66.0F38 0xe0 - invalid. */
2583/* Opcode VEX.66.0F38 0xe1 - invalid. */
2584/* Opcode VEX.66.0F38 0xe2 - invalid. */
2585/* Opcode VEX.66.0F38 0xe3 - invalid. */
2586/* Opcode VEX.66.0F38 0xe4 - invalid. */
2587/* Opcode VEX.66.0F38 0xe5 - invalid. */
2588/* Opcode VEX.66.0F38 0xe6 - invalid. */
2589/* Opcode VEX.66.0F38 0xe7 - invalid. */
2590/* Opcode VEX.66.0F38 0xe8 - invalid. */
2591/* Opcode VEX.66.0F38 0xe9 - invalid. */
2592/* Opcode VEX.66.0F38 0xea - invalid. */
2593/* Opcode VEX.66.0F38 0xeb - invalid. */
2594/* Opcode VEX.66.0F38 0xec - invalid. */
2595/* Opcode VEX.66.0F38 0xed - invalid. */
2596/* Opcode VEX.66.0F38 0xee - invalid. */
2597/* Opcode VEX.66.0F38 0xef - invalid. */
2598
2599
2600/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
2601/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
2602/* Opcode VEX.F3.0F38 0xf0 - invalid. */
2603/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
2604
2605/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
2606/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
2607/* Opcode VEX.F3.0F38 0xf1 - invalid. */
2608/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
2609
2610/**
2611 * @opcode 0xf2
2612 * @oppfx none
2613 * @opflmodify cf,pf,af,zf,sf,of
2614 * @opflclear cf,of
2615 * @opflundef pf,af
2616 * @note VEX only
2617 */
2618FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
2619{
2620 IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2621 IEMOP_HLP_IGNORE_VEX_W_PREFIX_IF_NOT_IN_64BIT();
2622 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF);
2623 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2624 if (IEM_IS_MODRM_REG_MODE(bRm))
2625 {
2626 /*
2627 * Register, register.
2628 */
2629 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2630 {
2631 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2632 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
2633 IEM_MC_ARG(uint64_t *, pDst, 0);
2634 IEM_MC_ARG(uint64_t, uSrc1, 1);
2635 IEM_MC_ARG(uint64_t, uSrc2, 2);
2636 IEM_MC_ARG(uint32_t *, pEFlags, 3);
2637 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2638 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2639 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2640 IEM_MC_REF_EFLAGS(pEFlags);
2641 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
2642 pDst, uSrc1, uSrc2, pEFlags);
2643 IEM_MC_ADVANCE_RIP_AND_FINISH();
2644 IEM_MC_END();
2645 }
2646 else
2647 {
2648 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2649 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
2650 IEM_MC_ARG(uint32_t *, pDst, 0);
2651 IEM_MC_ARG(uint32_t, uSrc1, 1);
2652 IEM_MC_ARG(uint32_t, uSrc2, 2);
2653 IEM_MC_ARG(uint32_t *, pEFlags, 3);
2654 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2655 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2656 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2657 IEM_MC_REF_EFLAGS(pEFlags);
2658 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
2659 pDst, uSrc1, uSrc2, pEFlags);
2660 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
2661 IEM_MC_ADVANCE_RIP_AND_FINISH();
2662 IEM_MC_END();
2663 }
2664 }
2665 else
2666 {
2667 /*
2668 * Register, memory.
2669 */
2670 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2671 {
2672 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2673 IEM_MC_ARG(uint64_t *, pDst, 0);
2674 IEM_MC_ARG(uint64_t, uSrc1, 1);
2675 IEM_MC_ARG(uint64_t, uSrc2, 2);
2676 IEM_MC_ARG(uint32_t *, pEFlags, 3);
2677 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2678 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2679 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
2680 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2681 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2682 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2683 IEM_MC_REF_EFLAGS(pEFlags);
2684 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
2685 pDst, uSrc1, uSrc2, pEFlags);
2686 IEM_MC_ADVANCE_RIP_AND_FINISH();
2687 IEM_MC_END();
2688 }
2689 else
2690 {
2691 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2692 IEM_MC_ARG(uint32_t *, pDst, 0);
2693 IEM_MC_ARG(uint32_t, uSrc1, 1);
2694 IEM_MC_ARG(uint32_t, uSrc2, 2);
2695 IEM_MC_ARG(uint32_t *, pEFlags, 3);
2696 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2697 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2698 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
2699 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2700 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2701 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2702 IEM_MC_REF_EFLAGS(pEFlags);
2703 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
2704 pDst, uSrc1, uSrc2, pEFlags);
2705 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
2706 IEM_MC_ADVANCE_RIP_AND_FINISH();
2707 IEM_MC_END();
2708 }
2709 }
2710}
2711
2712/* Opcode VEX.66.0F38 0xf2 - invalid. */
2713/* Opcode VEX.F3.0F38 0xf2 - invalid. */
2714/* Opcode VEX.F2.0F38 0xf2 - invalid. */
2715
2716
2717/* Opcode VEX.0F38 0xf3 - invalid. */
2718/* Opcode VEX.66.0F38 0xf3 - invalid. */
2719
2720/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
2721
2722/** Body for the vex group 17 instructions. */
2723#define IEMOP_BODY_By_Ey(a_Instr) \
2724 IEMOP_HLP_IGNORE_VEX_W_PREFIX_IF_NOT_IN_64BIT(); \
2725 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF); \
2726 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2727 { \
2728 /* \
2729 * Register, register. \
2730 */ \
2731 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2732 { \
2733 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2734 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
2735 IEM_MC_ARG(uint64_t, uSrc, 2); \
2736 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2737 IEM_MC_ARG(uint64_t *, pDst, 1); \
2738 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2739 IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
2740 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, \
2741 IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
2742 iemAImpl_ ## a_Instr ## _u64_fallback), fEFlagsIn, pDst, uSrc); \
2743 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
2744 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2745 IEM_MC_END(); \
2746 } \
2747 else \
2748 { \
2749 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2750 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
2751 IEM_MC_ARG(uint32_t, uSrc, 2); \
2752 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2753 IEM_MC_ARG(uint32_t *, pDst, 1); \
2754 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2755 IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
2756 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, \
2757 IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
2758 iemAImpl_ ## a_Instr ## _u32_fallback), fEFlagsIn, pDst, uSrc); \
2759 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2760 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
2761 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2762 IEM_MC_END(); \
2763 } \
2764 } \
2765 else \
2766 { \
2767 /* \
2768 * Register, memory. \
2769 */ \
2770 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2771 { \
2772 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2773 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2774 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2775 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
2776 \
2777 IEM_MC_ARG(uint64_t, uSrc, 2); \
2778 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2779 IEM_MC_ARG(uint64_t *, pDst, 1); \
2780 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2781 IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
2782 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, \
2783 IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
2784 iemAImpl_ ## a_Instr ## _u64_fallback), fEFlagsIn, pDst, uSrc); \
2785 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
2786 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2787 IEM_MC_END(); \
2788 } \
2789 else \
2790 { \
2791 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2792 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2793 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2794 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
2795 \
2796 IEM_MC_ARG(uint32_t, uSrc, 2); \
2797 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2798 IEM_MC_ARG(uint32_t *, pDst, 1); \
2799 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2800 IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
2801 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, \
2802 IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
2803 iemAImpl_ ## a_Instr ## _u32_fallback), fEFlagsIn, pDst, uSrc); \
2804 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2805 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
2806 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2807 IEM_MC_END(); \
2808 } \
2809 } \
2810 (void)0
2811
2812
2813/**
2814 * @opmaps vexgrp17
2815 * @opcode /1
2816 * @opflmodify cf,pf,af,zf,sf,of
2817 * @opflclear of
2818 * @opflundef pf,af
2819 */
2820FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
2821{
2822 IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2823 IEMOP_BODY_By_Ey(blsr);
2824}
2825
2826
2827/**
2828 * @opmaps vexgrp17
2829 * @opcode /2
2830 * @opflmodify cf,pf,af,zf,sf,of
2831 * @opflclear zf,of
2832 * @opflundef pf,af
2833 */
2834FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
2835{
2836 IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2837 IEMOP_BODY_By_Ey(blsmsk);
2838}
2839
2840
2841/**
2842 * @opmaps vexgrp17
2843 * @opcode /3
2844 * @opflmodify cf,pf,af,zf,sf,of
2845 * @opflclear of
2846 * @opflundef pf,af
2847 */
2848FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
2849{
2850 IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2851 IEMOP_BODY_By_Ey(blsi);
2852}
2853
2854
2855/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
2856/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
2857/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
2858/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
2859
2860/**
2861 * Group 17 jump table for the VEX.F3 variant.
2862 */
2863IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
2864{
2865 /* /0 */ iemOp_InvalidWithRM,
2866 /* /1 */ iemOp_VGrp17_blsr_By_Ey,
2867 /* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
2868 /* /3 */ iemOp_VGrp17_blsi_By_Ey,
2869 /* /4 */ iemOp_InvalidWithRM,
2870 /* /5 */ iemOp_InvalidWithRM,
2871 /* /6 */ iemOp_InvalidWithRM,
2872 /* /7 */ iemOp_InvalidWithRM
2873};
2874AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
2875
2876/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
2877FNIEMOP_DEF(iemOp_VGrp17_f3)
2878{
2879 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2880 return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
2881}
2882
2883/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
2884
2885
2886/* Opcode VEX.0F38 0xf4 - invalid. */
2887/* Opcode VEX.66.0F38 0xf4 - invalid. */
2888/* Opcode VEX.F3.0F38 0xf4 - invalid. */
2889/* Opcode VEX.F2.0F38 0xf4 - invalid. */
2890
2891/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
2892#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
2893 IEMOP_HLP_IGNORE_VEX_W_PREFIX_IF_NOT_IN_64BIT(); \
2894 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
2895 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2896 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2897 { \
2898 /* \
2899 * Register, register. \
2900 */ \
2901 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2902 { \
2903 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2904 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2905 IEM_MC_ARG(uint64_t *, pDst, 0); \
2906 IEM_MC_ARG(uint64_t, uSrc1, 1); \
2907 IEM_MC_ARG(uint64_t, uSrc2, 2); \
2908 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2909 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2910 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2911 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2912 IEM_MC_REF_EFLAGS(pEFlags); \
2913 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
2914 iemAImpl_ ## a_Instr ## _u64_fallback), \
2915 pDst, uSrc1, uSrc2, pEFlags); \
2916 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2917 IEM_MC_END(); \
2918 } \
2919 else \
2920 { \
2921 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2922 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2923 IEM_MC_ARG(uint32_t *, pDst, 0); \
2924 IEM_MC_ARG(uint32_t, uSrc1, 1); \
2925 IEM_MC_ARG(uint32_t, uSrc2, 2); \
2926 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2927 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2928 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2929 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2930 IEM_MC_REF_EFLAGS(pEFlags); \
2931 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2932 iemAImpl_ ## a_Instr ## _u32_fallback), \
2933 pDst, uSrc1, uSrc2, pEFlags); \
2934 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2935 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2936 IEM_MC_END(); \
2937 } \
2938 } \
2939 else \
2940 { \
2941 /* \
2942 * Register, memory. \
2943 */ \
2944 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2945 { \
2946 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2947 IEM_MC_ARG(uint64_t *, pDst, 0); \
2948 IEM_MC_ARG(uint64_t, uSrc1, 1); \
2949 IEM_MC_ARG(uint64_t, uSrc2, 2); \
2950 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2951 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2952 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2953 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2954 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2955 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2956 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2957 IEM_MC_REF_EFLAGS(pEFlags); \
2958 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
2959 iemAImpl_ ## a_Instr ## _u64_fallback), \
2960 pDst, uSrc1, uSrc2, pEFlags); \
2961 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2962 IEM_MC_END(); \
2963 } \
2964 else \
2965 { \
2966 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2967 IEM_MC_ARG(uint32_t *, pDst, 0); \
2968 IEM_MC_ARG(uint32_t, uSrc1, 1); \
2969 IEM_MC_ARG(uint32_t, uSrc2, 2); \
2970 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2971 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2972 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2973 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2974 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2975 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2976 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2977 IEM_MC_REF_EFLAGS(pEFlags); \
2978 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2979 iemAImpl_ ## a_Instr ## _u32_fallback), \
2980 pDst, uSrc1, uSrc2, pEFlags); \
2981 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2982 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2983 IEM_MC_END(); \
2984 } \
2985 } \
2986 (void)0
2987
2988/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
2989#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember) \
2990 IEMOP_HLP_IGNORE_VEX_W_PREFIX_IF_NOT_IN_64BIT(); \
2991 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2992 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2993 { \
2994 /* \
2995 * Register, register. \
2996 */ \
2997 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2998 { \
2999 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
3000 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
3001 IEM_MC_ARG(uint64_t *, pDst, 0); \
3002 IEM_MC_ARG(uint64_t, uSrc1, 1); \
3003 IEM_MC_ARG(uint64_t, uSrc2, 2); \
3004 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
3005 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
3006 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
3007 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
3008 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
3009 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
3010 IEM_MC_END(); \
3011 } \
3012 else \
3013 { \
3014 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
3015 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
3016 IEM_MC_ARG(uint32_t *, pDst, 0); \
3017 IEM_MC_ARG(uint32_t, uSrc1, 1); \
3018 IEM_MC_ARG(uint32_t, uSrc2, 2); \
3019 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
3020 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
3021 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
3022 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
3023 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
3024 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
3025 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
3026 IEM_MC_END(); \
3027 } \
3028 } \
3029 else \
3030 { \
3031 /* \
3032 * Register, memory. \
3033 */ \
3034 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
3035 { \
3036 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
3037 IEM_MC_ARG(uint64_t *, pDst, 0); \
3038 IEM_MC_ARG(uint64_t, uSrc1, 1); \
3039 IEM_MC_ARG(uint64_t, uSrc2, 2); \
3040 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
3041 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
3042 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
3043 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
3044 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
3045 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
3046 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
3047 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
3048 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
3049 IEM_MC_END(); \
3050 } \
3051 else \
3052 { \
3053 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
3054 IEM_MC_ARG(uint32_t *, pDst, 0); \
3055 IEM_MC_ARG(uint32_t, uSrc1, 1); \
3056 IEM_MC_ARG(uint32_t, uSrc2, 2); \
3057 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
3058 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
3059 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
3060 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
3061 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
3062 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
3063 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
3064 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
3065 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
3066 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
3067 IEM_MC_END(); \
3068 } \
3069 } \
3070 (void)0
3071
3072/**
3073 * @opcode 0xf5
3074 * @oppfx none
3075 * @opflmodify cf,pf,af,zf,sf,of
3076 * @opflclear of
3077 * @opflundef pf,af
3078 * @note VEX only
3079 */
3080FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
3081{
3082 IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
3083 IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF | X86_EFL_PF);
3084}
3085
3086/* Opcode VEX.66.0F38 0xf5 - invalid. */
3087
3088/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
3089#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
3090 IEMOP_HLP_IGNORE_VEX_W_PREFIX_IF_NOT_IN_64BIT(); \
3091 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
3092 if (IEM_IS_MODRM_REG_MODE(bRm)) \
3093 { \
3094 /* \
3095 * Register, register. \
3096 */ \
3097 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
3098 { \
3099 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
3100 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
3101 IEM_MC_ARG(uint64_t *, pDst, 0); \
3102 IEM_MC_ARG(uint64_t, uSrc1, 1); \
3103 IEM_MC_ARG(uint64_t, uSrc2, 2); \
3104 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
3105 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
3106 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
3107 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
3108 iemAImpl_ ## a_Instr ## _u64, \
3109 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
3110 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
3111 IEM_MC_END(); \
3112 } \
3113 else \
3114 { \
3115 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
3116 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
3117 IEM_MC_ARG(uint32_t *, pDst, 0); \
3118 IEM_MC_ARG(uint32_t, uSrc1, 1); \
3119 IEM_MC_ARG(uint32_t, uSrc2, 2); \
3120 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
3121 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
3122 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
3123 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
3124 iemAImpl_ ## a_Instr ## _u32, \
3125 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
3126 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
3127 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
3128 IEM_MC_END(); \
3129 } \
3130 } \
3131 else \
3132 { \
3133 /* \
3134 * Register, memory. \
3135 */ \
3136 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
3137 { \
3138 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
3139 IEM_MC_ARG(uint64_t *, pDst, 0); \
3140 IEM_MC_ARG(uint64_t, uSrc1, 1); \
3141 IEM_MC_ARG(uint64_t, uSrc2, 2); \
3142 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
3143 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
3144 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
3145 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
3146 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
3147 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
3148 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
3149 iemAImpl_ ## a_Instr ## _u64, \
3150 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
3151 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
3152 IEM_MC_END(); \
3153 } \
3154 else \
3155 { \
3156 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
3157 IEM_MC_ARG(uint32_t *, pDst, 0); \
3158 IEM_MC_ARG(uint32_t, uSrc1, 1); \
3159 IEM_MC_ARG(uint32_t, uSrc2, 2); \
3160 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
3161 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
3162 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
3163 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
3164 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
3165 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
3166 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
3167 iemAImpl_ ## a_Instr ## _u32, \
3168 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
3169 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
3170 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
3171 IEM_MC_END(); \
3172 } \
3173 } \
3174 (void)0
3175
3176
3177/** Opcode VEX.F3.0F38 0xf5 (vex only). */
3178FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
3179{
3180 IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
3181 IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
3182}
3183
3184
3185/** Opcode VEX.F2.0F38 0xf5 (vex only). */
3186FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
3187{
3188 IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
3189 IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
3190}
3191
3192
3193/* Opcode VEX.0F38 0xf6 - invalid. */
3194/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
3195/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
3196
3197
3198/**
3199 * @opcode 0xf6
3200 * @oppfx 0xf2
3201 * @opflclass unchanged
3202 */
3203FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
3204{
3205 IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
3206 IEMOP_HLP_IGNORE_VEX_W_PREFIX_IF_NOT_IN_64BIT();
3207 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3208 if (IEM_IS_MODRM_REG_MODE(bRm))
3209 {
3210 /*
3211 * Register, register.
3212 */
3213 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3214 {
3215 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
3216 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
3217 IEM_MC_ARG(uint64_t *, pDst1, 0);
3218 IEM_MC_ARG(uint64_t *, pDst2, 1);
3219 IEM_MC_ARG(uint64_t, uSrc1, 2);
3220 IEM_MC_ARG(uint64_t, uSrc2, 3);
3221 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
3222 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
3223 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
3224 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
3225 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
3226 pDst1, pDst2, uSrc1, uSrc2);
3227 IEM_MC_ADVANCE_RIP_AND_FINISH();
3228 IEM_MC_END();
3229 }
3230 else
3231 {
3232 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3233 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
3234 IEM_MC_ARG(uint32_t *, pDst1, 0);
3235 IEM_MC_ARG(uint32_t *, pDst2, 1);
3236 IEM_MC_ARG(uint32_t, uSrc1, 2);
3237 IEM_MC_ARG(uint32_t, uSrc2, 3);
3238 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
3239 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
3240 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
3241 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
3242 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
3243 pDst1, pDst2, uSrc1, uSrc2);
3244 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu));
3245 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
3246 IEM_MC_ADVANCE_RIP_AND_FINISH();
3247 IEM_MC_END();
3248 }
3249 }
3250 else
3251 {
3252 /*
3253 * Register, memory.
3254 */
3255 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3256 {
3257 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
3258 IEM_MC_ARG(uint64_t *, pDst1, 0);
3259 IEM_MC_ARG(uint64_t *, pDst2, 1);
3260 IEM_MC_ARG(uint64_t, uSrc1, 2);
3261 IEM_MC_ARG(uint64_t, uSrc2, 3);
3262 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3263 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3264 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
3265 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3266 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
3267 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
3268 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
3269 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
3270 pDst1, pDst2, uSrc1, uSrc2);
3271 IEM_MC_ADVANCE_RIP_AND_FINISH();
3272 IEM_MC_END();
3273 }
3274 else
3275 {
3276 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3277 IEM_MC_ARG(uint32_t *, pDst1, 0);
3278 IEM_MC_ARG(uint32_t *, pDst2, 1);
3279 IEM_MC_ARG(uint32_t, uSrc1, 2);
3280 IEM_MC_ARG(uint32_t, uSrc2, 3);
3281 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3282 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3283 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
3284 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3285 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
3286 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
3287 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
3288 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
3289 pDst1, pDst2, uSrc1, uSrc2);
3290 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu));
3291 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
3292 IEM_MC_ADVANCE_RIP_AND_FINISH();
3293 IEM_MC_END();
3294 }
3295 }
3296}
3297
3298
3299/**
3300 * @opcode 0xf7
3301 * @oppfx none
3302 * @opflmodify cf,pf,af,zf,sf,of
3303 * @opflclear cf,of
3304 * @opflundef pf,af,sf
3305 */
3306FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
3307{
3308 IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
3309 IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
3310}
3311
3312
3313/**
3314 * @opcode 0xf7
3315 * @oppfx 0x66
3316 * @opflclass unchanged
3317 */
3318FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
3319{
3320 IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
3321 IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2);
3322}
3323
3324
3325/**
3326 * @opcode 0xf7
3327 * @oppfx 0xf3
3328 * @opflclass unchanged
3329 */
3330FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
3331{
3332 IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
3333 IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2);
3334}
3335
3336
3337/**
3338 * @opcode 0xf7
3339 * @oppfx 0xf2
3340 * @opflclass unchanged
3341 */
3342FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
3343{
3344 IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
3345 IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2);
3346}
3347
3348/* Opcode VEX.0F38 0xf8 - invalid. */
3349/* Opcode VEX.66.0F38 0xf8 - invalid. */
3350/* Opcode VEX.F3.0F38 0xf8 - invalid. */
3351/* Opcode VEX.F2.0F38 0xf8 - invalid. */
3352
3353/* Opcode VEX.0F38 0xf9 - invalid. */
3354/* Opcode VEX.66.0F38 0xf9 - invalid. */
3355/* Opcode VEX.F3.0F38 0xf9 - invalid. */
3356/* Opcode VEX.F2.0F38 0xf9 - invalid. */
3357
3358/* Opcode VEX.0F38 0xfa - invalid. */
3359/* Opcode VEX.66.0F38 0xfa - invalid. */
3360/* Opcode VEX.F3.0F38 0xfa - invalid. */
3361/* Opcode VEX.F2.0F38 0xfa - invalid. */
3362
3363/* Opcode VEX.0F38 0xfb - invalid. */
3364/* Opcode VEX.66.0F38 0xfb - invalid. */
3365/* Opcode VEX.F3.0F38 0xfb - invalid. */
3366/* Opcode VEX.F2.0F38 0xfb - invalid. */
3367
3368/* Opcode VEX.0F38 0xfc - invalid. */
3369/* Opcode VEX.66.0F38 0xfc - invalid. */
3370/* Opcode VEX.F3.0F38 0xfc - invalid. */
3371/* Opcode VEX.F2.0F38 0xfc - invalid. */
3372
3373/* Opcode VEX.0F38 0xfd - invalid. */
3374/* Opcode VEX.66.0F38 0xfd - invalid. */
3375/* Opcode VEX.F3.0F38 0xfd - invalid. */
3376/* Opcode VEX.F2.0F38 0xfd - invalid. */
3377
3378/* Opcode VEX.0F38 0xfe - invalid. */
3379/* Opcode VEX.66.0F38 0xfe - invalid. */
3380/* Opcode VEX.F3.0F38 0xfe - invalid. */
3381/* Opcode VEX.F2.0F38 0xfe - invalid. */
3382
3383/* Opcode VEX.0F38 0xff - invalid. */
3384/* Opcode VEX.66.0F38 0xff - invalid. */
3385/* Opcode VEX.F3.0F38 0xff - invalid. */
3386/* Opcode VEX.F2.0F38 0xff - invalid. */
3387
3388
3389/**
3390 * VEX opcode map \#2.
3391 *
3392 * @sa g_apfnThreeByte0f38
3393 */
3394const PFNIEMOP g_apfnVexMap2[] =
3395{
3396 /* no prefix, 066h prefix f3h prefix, f2h prefix */
3397 /* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3398 /* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3399 /* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3400 /* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3401 /* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3402 /* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3403 /* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3404 /* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3405 /* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3406 /* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3407 /* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3408 /* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3409 /* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3410 /* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3411 /* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3412 /* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3413
3414 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
3415 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
3416 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
3417 /* 0x13 */ iemOp_InvalidNeedRM, iemOp_vcvtph2ps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3418 /* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
3419 /* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
3420 /* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3421 /* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3422 /* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3423 /* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3424 /* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3425 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
3426 /* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3427 /* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3428 /* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3429 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
3430
3431 /* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3432 /* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3433 /* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3434 /* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3435 /* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3436 /* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3437 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
3438 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
3439 /* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3440 /* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3441 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3442 /* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3443 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3444 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3445 /* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3446 /* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3447
3448 /* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3449 /* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3450 /* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3451 /* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3452 /* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3453 /* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3454 /* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3455 /* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3456 /* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3457 /* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3458 /* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3459 /* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3460 /* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3461 /* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3462 /* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3463 /* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3464
3465 /* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3466 /* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3467 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
3468 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
3469 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
3470 /* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3471 /* 0x46 */ iemOp_InvalidNeedRM, iemOp_vpsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3472 /* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3473 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
3474 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
3475 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
3476 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
3477 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
3478 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
3479 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
3480 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
3481
3482 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
3483 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
3484 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
3485 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
3486 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
3487 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
3488 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
3489 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
3490 /* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3491 /* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3492 /* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3493 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
3494 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
3495 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
3496 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
3497 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
3498
3499 /* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
3500 /* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
3501 /* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
3502 /* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
3503 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
3504 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
3505 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
3506 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
3507 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
3508 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
3509 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
3510 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
3511 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
3512 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
3513 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
3514 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
3515
3516 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
3517 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
3518 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
3519 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
3520 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
3521 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
3522 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
3523 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
3524 /* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3525 /* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3526 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
3527 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
3528 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
3529 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
3530 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
3531 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
3532
3533 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
3534 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
3535 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
3536 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
3537 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
3538 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
3539 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
3540 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
3541 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
3542 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
3543 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
3544 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
3545 /* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3546 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
3547 /* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3548 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
3549
3550 /* 0x90 */ iemOp_InvalidNeedRM, iemOp_vpgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3551 /* 0x91 */ iemOp_InvalidNeedRM, iemOp_vpgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3552 /* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3553 /* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3554 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
3555 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
3556 /* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3557 /* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3558 /* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3559 /* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3560 /* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3561 /* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3562 /* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3563 /* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3564 /* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3565 /* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3566
3567 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3568 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3569 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3570 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3571 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3572 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3573 /* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3574 /* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3575 /* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3576 /* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3577 /* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3578 /* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3579 /* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3580 /* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3581 /* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3582 /* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3583
3584 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3585 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3586 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3587 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3588 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3589 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3590 /* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3591 /* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3592 /* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3593 /* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3594 /* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3595 /* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3596 /* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3597 /* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3598 /* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3599 /* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3600
3601 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3602 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3603 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3604 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3605 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3606 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3607 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3608 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3609 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3610 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3611 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
3612 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
3613 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
3614 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
3615 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
3616 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
3617
3618 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3619 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3620 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3621 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3622 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3623 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3624 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3625 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3626 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3627 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3628 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
3629 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3630 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3631 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3632 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3633 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3634
3635 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3636 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3637 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3638 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3639 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3640 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3641 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3642 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3643 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3644 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3645 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
3646 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
3647 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
3648 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
3649 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
3650 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
3651
3652 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3653 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3654 /* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3655 /* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3656 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3657 /* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
3658 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
3659 /* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
3660 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3661 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3662 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
3663 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
3664 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
3665 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
3666 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
3667 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
3668};
3669AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
3670
3671/** @} */
3672
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette