IEMAllInstThree0f3a.cpp.h@ 106061

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1	/* $Id: IEMAllInstThree0f3a.cpp.h 106061 2024-09-16 14:03:52Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstVexMap3.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33	* @{
34	*/
35
36	/**
37	* Common worker for SSSE3 instructions on the forms:
38	* pxxx xmm1, xmm2/mem128, imm8
39	*
40	* Proper alignment of the 128-bit operand is enforced.
41	* Exceptions type 4. SSSE3 cpuid checks.
42	*
43	* @sa iemOpCommonSse41_FullFullImm8_To_Full
44	*/
45	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
55	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
56	IEM_MC_ARG(PRTUINT128U, puDst, 0);
57	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
59	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
60	IEM_MC_PREPARE_SSE_USAGE();
61	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64	IEM_MC_ADVANCE_RIP_AND_FINISH();
65	IEM_MC_END();
66	}
67	else
68	{
69	/*
70	* Register, memory.
71	*/
72	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
73	IEM_MC_ARG(PRTUINT128U, puDst, 0);
74	IEM_MC_LOCAL(RTUINT128U, uSrc);
75	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
79	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
81	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
82	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
83	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85	IEM_MC_PREPARE_SSE_USAGE();
86	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89	IEM_MC_ADVANCE_RIP_AND_FINISH();
90	IEM_MC_END();
91	}
92	}
93
94
95	/**
96	* Common worker for SSE 4.1 instructions on the forms:
97	* pxxx xmm1, xmm2/mem128, imm8
98	*
99	* Proper alignment of the 128-bit operand is enforced.
100	* No SIMD exceptions. SSE 4.1 cpuid checks.
101	*
102	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
103	*/
104	FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
105	{
106	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107	if (IEM_IS_MODRM_REG_MODE(bRm))
108	{
109	/*
110	* XMM, XMM, imm8
111	*/
112	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
114	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
115	IEM_MC_ARG(PRTUINT128U, puDst, 0);
116	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
118	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
119	IEM_MC_PREPARE_SSE_USAGE();
120	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
121	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
122	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
123	IEM_MC_ADVANCE_RIP_AND_FINISH();
124	IEM_MC_END();
125	}
126	else
127	{
128	/*
129	* XMM, [mem128], imm8.
130	*/
131	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
132	IEM_MC_ARG(PRTUINT128U, puDst, 0);
133	IEM_MC_LOCAL(RTUINT128U, uSrc);
134	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
135	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
136
137	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
138	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
139	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
140	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
141	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
142	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143
144	IEM_MC_PREPARE_SSE_USAGE();
145	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
146	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
147
148	IEM_MC_ADVANCE_RIP_AND_FINISH();
149	IEM_MC_END();
150	}
151	}
152
153
154	/**
155	* Common worker for SSE 4.1 instructions of the form:
156	* xxx xmm1, xmm2/mem128, imm8
157	*
158	* Proper alignment of the 128-bit operand is enforced.
159	* MXCSR is used as input and output.
160	* Exceptions type 4. SSE 4.1 cpuid checks.
161	*
162	* @sa iemOpCommonSse41_FullFullImm8_To_Full
163	*/
164	FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAF3XMMIMM8, pfnU128)
165	{
166	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167	if (IEM_IS_MODRM_REG_MODE(bRm))
168	{
169	/*
170	* XMM, XMM, imm8.
171	*/
172	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
174	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
175	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
176	IEM_MC_LOCAL(X86XMMREG, Dst);
177	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
178	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
179	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
180	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
181	IEM_MC_PREPARE_SSE_USAGE();
182
183	IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
184	IEM_MC_CALL_SSE_AIMPL_3(pfnU128, pDst, pSrc, bImmArg);
185	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
186
187	IEM_MC_ADVANCE_RIP_AND_FINISH();
188	IEM_MC_END();
189	}
190	else
191	{
192	/*
193	* XMM, [mem128], imm8.
194	*/
195	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
196	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
197	IEM_MC_LOCAL(X86XMMREG, Dst);
198	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
199	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
200	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
201
202	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
203	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
204	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
205	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
206	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
207	IEM_MC_PREPARE_SSE_USAGE();
208
209	IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
210	IEM_MC_CALL_SSE_AIMPL_3(pfnU128, pDst, pSrc, bImmArg);
211	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
212
213	IEM_MC_ADVANCE_RIP_AND_FINISH();
214	IEM_MC_END();
215	}
216	}
217
218
219	/**
220	* Common worker for SSE 4.1 instructions of the form:
221	* xxx xmm1, xmm2/mem128, imm8
222	*
223	* Proper alignment of the 128-bit operand is enforced.
224	* MXCSR is used as input and output.
225	* Exceptions type 4. SSE 4.1 cpuid checks.
226	*
227	* @sa iemOpCommonSse41_FullFullImm8_To_Full
228	*/
229	FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullImm8_To_Full, PFNIEMAIMPLMEDIAF2U128IMM8, pfnU128)
230	{
231	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
232	if (IEM_IS_MODRM_REG_MODE(bRm))
233	{
234	/*
235	* XMM, XMM, imm8.
236	*/
237	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
238	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
239	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
240	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
241	IEM_MC_PREPARE_SSE_USAGE();
242	IEM_MC_LOCAL(X86XMMREG, uDst);
243	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
244	IEM_MC_ARG( PCX86XMMREG, puSrc, 1);
245	IEM_MC_REF_XREG_XMM_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
246	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
247	IEM_MC_CALL_SSE_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
248	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
249	IEM_MC_ADVANCE_RIP_AND_FINISH();
250	IEM_MC_END();
251	}
252	else
253	{
254	/*
255	* XMM, [mem128], imm8.
256	*/
257	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
258	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
259	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
260	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
261	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
262	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
263	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
264	IEM_MC_PREPARE_SSE_USAGE();
265	IEM_MC_LOCAL(X86XMMREG, uSrc);
266	IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
267	IEM_MC_LOCAL(X86XMMREG, uDst);
268	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
269	IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc, uSrc, 1);
270	IEM_MC_CALL_SSE_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
271	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
272	IEM_MC_ADVANCE_RIP_AND_FINISH();
273	IEM_MC_END();
274	}
275	}
276
277
278	/**
279	* Common worker for SSE-style AES-NI instructions of the form:
280	* aesxxx xmm1, xmm2/mem128, imm8
281	*
282	* Proper alignment of the 128-bit operand is enforced.
283	* Exceptions type 4. AES-NI cpuid checks.
284	*
285	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
286	* @sa iemOpCommonSse41_FullFullImm8_To_Full
287	*/
288	FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
289	{
290	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
291	if (IEM_IS_MODRM_REG_MODE(bRm))
292	{
293	/*
294	* Register, register.
295	*/
296	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
297	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
298	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
299	IEM_MC_ARG(PRTUINT128U, puDst, 0);
300	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
301	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
302	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
303	IEM_MC_PREPARE_SSE_USAGE();
304	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
305	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
306	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
307	IEM_MC_ADVANCE_RIP_AND_FINISH();
308	IEM_MC_END();
309	}
310	else
311	{
312	/*
313	* Register, memory.
314	*/
315	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
316	IEM_MC_ARG(PRTUINT128U, puDst, 0);
317	IEM_MC_LOCAL(RTUINT128U, uSrc);
318	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
319	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
320
321	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
322	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
323	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
324	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
325	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
326	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
327
328	IEM_MC_PREPARE_SSE_USAGE();
329	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
330	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
331
332	IEM_MC_ADVANCE_RIP_AND_FINISH();
333	IEM_MC_END();
334	}
335	}
336
337
338	/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
339	/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
340	/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
341	/* Opcode 0x66 0x0f 0x03 - invalid */
342	/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
343	/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
344	/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
345	/* Opcode 0x66 0x0f 0x07 - invalid */
346	/** Opcode 0x66 0x0f 0x08. */
347	FNIEMOP_DEF(iemOp_roundps_Vx_Wx_Ib)
348	{
349	IEMOP_MNEMONIC3(RMI, ROUNDPS, roundps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
350	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullImm8_To_Full,
351	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback));
352	}
353
354
355	/** Opcode 0x66 0x0f 0x09. */
356	FNIEMOP_DEF(iemOp_roundpd_Vx_Wx_Ib)
357	{
358	IEMOP_MNEMONIC3(RMI, ROUNDPD, roundpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
359	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullImm8_To_Full,
360	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback));
361	}
362
363
364	/** Opcode 0x66 0x0f 0x0a. */
365	FNIEMOP_DEF(iemOp_roundss_Vss_Wss_Ib)
366	{
367	/* The instruction form is very similar to CMPSS. */
368	IEMOP_MNEMONIC3(RMI, ROUNDSS, roundss, Vss, Wss, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
369
370	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
371	if (IEM_IS_MODRM_REG_MODE(bRm))
372	{
373	/*
374	* XMM32, XMM32.
375	*/
376	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
377	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
378	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
379	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
380	IEM_MC_LOCAL(X86XMMREG, Dst);
381	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
382	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
383	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
384	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
385	IEM_MC_PREPARE_SSE_USAGE();
386	IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
387	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_roundss_u128, pDst, pSrc, bImmArg);
388	IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iDword/, Dst);
389
390	IEM_MC_ADVANCE_RIP_AND_FINISH();
391	IEM_MC_END();
392	}
393	else
394	{
395	/*
396	* XMM32, [mem32].
397	*/
398	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
399	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
400	IEM_MC_LOCAL(X86XMMREG, Dst);
401	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
402	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
403	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
404
405	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
406	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
407	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
408	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
409	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
410	IEM_MC_PREPARE_SSE_USAGE();
411
412	IEM_MC_FETCH_MEM_XMM_U32_AND_XREG_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
413	0 /a_iDword/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
414	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_roundss_u128, pDst, pSrc, bImmArg);
415	IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iDword/, Dst);
416
417	IEM_MC_ADVANCE_RIP_AND_FINISH();
418	IEM_MC_END();
419	}
420	}
421
422	/** Opcode 0x66 0x0f 0x0b. */
423	FNIEMOP_DEF(iemOp_roundsd_Vsd_Wsd_Ib)
424	{
425	/* The instruction form is very similar to CMPSD. */
426	IEMOP_MNEMONIC3(RMI, ROUNDSD, roundsd, Vsd, Wsd, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
427
428	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
429	if (IEM_IS_MODRM_REG_MODE(bRm))
430	{
431	/*
432	* XMM64, XMM64, imm8.
433	*/
434	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
435	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
436	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
437	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
438	IEM_MC_LOCAL(X86XMMREG, Dst);
439	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
440	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
441	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
442	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
443	IEM_MC_PREPARE_SSE_USAGE();
444	IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
445	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_roundsd_u128, pDst, pSrc, bImmArg);
446	IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iQword/, Dst);
447
448	IEM_MC_ADVANCE_RIP_AND_FINISH();
449	IEM_MC_END();
450	}
451	else
452	{
453	/*
454	* XMM64, [mem64], imm8.
455	*/
456	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
457	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
458	IEM_MC_LOCAL(X86XMMREG, Dst);
459	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
460	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
461	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
462
463	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
464	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
465	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
466	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
467	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
468	IEM_MC_PREPARE_SSE_USAGE();
469
470	IEM_MC_FETCH_MEM_XMM_U64_AND_XREG_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
471	0 /a_iQword /, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
472	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_roundsd_u128, pDst, pSrc, bImmArg);
473	IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iQword/, Dst);
474
475	IEM_MC_ADVANCE_RIP_AND_FINISH();
476	IEM_MC_END();
477	}
478	}
479
480
481	/** Opcode 0x66 0x0f 0x0c. */
482	FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
483	{
484	IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
485	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
486	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
487	}
488
489
490	/** Opcode 0x66 0x0f 0x0d. */
491	FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
492	{
493	IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
494	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
495	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
496	}
497
498
499	/** Opcode 0x66 0x0f 0x0e. */
500	FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
501	{
502	IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
503	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
504	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
505	}
506
507
508	/** Opcode 0x0f 0x0f. */
509	FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
510	{
511	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
512	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
513	if (IEM_IS_MODRM_REG_MODE(bRm))
514	{
515	/*
516	* Register, register.
517	*/
518	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
519	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
520	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
521	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
522	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
523	IEM_MC_ARG(uint64_t *, pDst, 0);
524	IEM_MC_ARG(uint64_t, uSrc, 1);
525	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
526	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
527	IEM_MC_PREPARE_FPU_USAGE();
528	IEM_MC_FPU_TO_MMX_MODE();
529	IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
530	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
531	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
532	pDst, uSrc, bImmArg);
533	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
534	IEM_MC_ADVANCE_RIP_AND_FINISH();
535	IEM_MC_END();
536	}
537	else
538	{
539	/*
540	* Register, memory.
541	*/
542	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
543	IEM_MC_ARG(uint64_t *, pDst, 0);
544	IEM_MC_ARG(uint64_t, uSrc, 1);
545	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
546
547	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
548	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
549	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
550	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
551	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
552	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
553
554	IEM_MC_PREPARE_FPU_USAGE();
555	IEM_MC_FPU_TO_MMX_MODE();
556	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
557	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
558	pDst, uSrc, bImmArg);
559	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
560
561	IEM_MC_ADVANCE_RIP_AND_FINISH();
562	IEM_MC_END();
563	}
564	}
565
566
567	/** Opcode 0x66 0x0f 0x0f. */
568	FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
569	{
570	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
571	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
572	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
573	}
574
575
576	/* Opcode 0x66 0x0f 0x10 - invalid */
577	/* Opcode 0x66 0x0f 0x11 - invalid */
578	/* Opcode 0x66 0x0f 0x12 - invalid */
579	/* Opcode 0x66 0x0f 0x13 - invalid */
580
581
582	/** Opcode 0x66 0x0f 0x14. */
583	FNIEMOP_DEF(iemOp_pextrb_RdMb_Vdq_Ib)
584	{
585	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
586	IEMOP_MNEMONIC3(MRI, PEXTRB, pextrb, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
587	if (IEM_IS_MODRM_REG_MODE(bRm))
588	{
589	/*
590	* greg32, XMM.
591	*/
592	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
593	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
594	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
595	IEM_MC_LOCAL(uint8_t, uValue);
596	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
597	IEM_MC_PREPARE_SSE_USAGE();
598	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/);
599	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
600	IEM_MC_ADVANCE_RIP_AND_FINISH();
601	IEM_MC_END();
602	}
603	else
604	{
605	/*
606	* [mem8], XMM.
607	*/
608	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
609	IEM_MC_LOCAL(uint8_t, uValue);
610	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
611
612	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
613	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
614	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
615	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
616	IEM_MC_PREPARE_SSE_USAGE();
617
618	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/);
619	IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
620	IEM_MC_ADVANCE_RIP_AND_FINISH();
621	IEM_MC_END();
622	}
623	}
624
625
626	/** Opcode 0x66 0x0f 0x15. */
627	FNIEMOP_DEF(iemOp_pextrw_RdMw_Vdq_Ib)
628	{
629	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
630	IEMOP_MNEMONIC3(MRI, PEXTRW, pextrw, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
631	if (IEM_IS_MODRM_REG_MODE(bRm))
632	{
633	/*
634	* greg32, XMM.
635	*/
636	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
637	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
638	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
639	IEM_MC_LOCAL(uint16_t, uValue);
640	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
641	IEM_MC_PREPARE_SSE_USAGE();
642	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7 /a_iWord/);
643	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
644	IEM_MC_ADVANCE_RIP_AND_FINISH();
645	IEM_MC_END();
646	}
647	else
648	{
649	/*
650	* [mem16], XMM.
651	*/
652	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
653	IEM_MC_LOCAL(uint16_t, uValue);
654	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
655
656	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
657	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
658	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
659	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
660	IEM_MC_PREPARE_SSE_USAGE();
661
662	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7 /a_iWord/);
663	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
664	IEM_MC_ADVANCE_RIP_AND_FINISH();
665	IEM_MC_END();
666	}
667	}
668
669
670	FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib)
671	{
672	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
673	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
674	{
675	/**
676	* @opcode 0x16
677	* @opcodesub rex.w=1
678	* @oppfx 0x66
679	* @opcpuid sse
680	*/
681	IEMOP_MNEMONIC3(MRI, PEXTRQ, pextrq, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
682	if (IEM_IS_MODRM_REG_MODE(bRm))
683	{
684	/*
685	* greg64, XMM.
686	*/
687	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
688	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
689	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
690	IEM_MC_LOCAL(uint64_t, uSrc);
691	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
692	IEM_MC_PREPARE_SSE_USAGE();
693	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /a_iQword/);
694	IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
695	IEM_MC_ADVANCE_RIP_AND_FINISH();
696	IEM_MC_END();
697	}
698	else
699	{
700	/*
701	* [mem64], XMM.
702	*/
703	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
704	IEM_MC_LOCAL(uint64_t, uSrc);
705	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
706
707	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
708	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
709	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
710	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
711	IEM_MC_PREPARE_SSE_USAGE();
712
713	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /a_iQword/);
714	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
715	IEM_MC_ADVANCE_RIP_AND_FINISH();
716	IEM_MC_END();
717	}
718	}
719	else
720	{
721	/**
722	* @opdone
723	* @opcode 0x16
724	* @opcodesub rex.w=0
725	* @oppfx 0x66
726	* @opcpuid sse
727	*/
728	IEMOP_MNEMONIC3(MRI, PEXTRD, pextrd, Ey, Vd, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
729	if (IEM_IS_MODRM_REG_MODE(bRm))
730	{
731	/*
732	* greg32, XMM.
733	*/
734	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
735	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
736	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
737	IEM_MC_LOCAL(uint32_t, uSrc);
738	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
739	IEM_MC_PREPARE_SSE_USAGE();
740	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/);
741	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
742	IEM_MC_ADVANCE_RIP_AND_FINISH();
743	IEM_MC_END();
744	}
745	else
746	{
747	/*
748	* [mem32], XMM.
749	*/
750	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
751	IEM_MC_LOCAL(uint32_t, uSrc);
752	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
753
754	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
755	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
756	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
757	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
758	IEM_MC_PREPARE_SSE_USAGE();
759	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/);
760	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
761	IEM_MC_ADVANCE_RIP_AND_FINISH();
762	IEM_MC_END();
763	}
764	}
765	}
766
767
768	/** Opcode 0x66 0x0f 0x17. */
769	FNIEMOP_DEF(iemOp_extractps_Ed_Vdq_Ib)
770	{
771	IEMOP_MNEMONIC3(MRI, EXTRACTPS, extractps, Ed, Vdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
772	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
773	if (IEM_IS_MODRM_REG_MODE(bRm))
774	{
775	/*
776	* greg32, XMM.
777	*/
778	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
779	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
780	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
781	IEM_MC_LOCAL(uint32_t, uSrc);
782	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
783	IEM_MC_PREPARE_SSE_USAGE();
784	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/);
785	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
786	IEM_MC_ADVANCE_RIP_AND_FINISH();
787	IEM_MC_END();
788	}
789	else
790	{
791	/*
792	* [mem32], XMM.
793	*/
794	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
795	IEM_MC_LOCAL(uint32_t, uSrc);
796	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
797
798	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
799	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
800	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
801	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
802	IEM_MC_PREPARE_SSE_USAGE();
803	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/);
804	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
805	IEM_MC_ADVANCE_RIP_AND_FINISH();
806	IEM_MC_END();
807	}
808	}
809
810
811	/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
812	/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
813	/* Opcode 0x66 0x0f 0x1a - invalid */
814	/* Opcode 0x66 0x0f 0x1b - invalid */
815	/* Opcode 0x66 0x0f 0x1c - invalid */
816	/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
817	/* Opcode 0x66 0x0f 0x1e - invalid */
818	/* Opcode 0x66 0x0f 0x1f - invalid */
819
820
821	/** Opcode 0x66 0x0f 0x20. */
822	FNIEMOP_DEF(iemOp_pinsrb_Vdq_RyMb_Ib)
823	{
824	IEMOP_MNEMONIC3(RMI, PINSRB, pinsrb, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
825	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
826	if (IEM_IS_MODRM_REG_MODE(bRm))
827	{
828	/*
829	* XMM, greg32.
830	*/
831	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
832	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
833	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
834	IEM_MC_LOCAL(uint8_t, uSrc);
835	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
836	IEM_MC_PREPARE_SSE_USAGE();
837	IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
838	IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/, uSrc);
839	IEM_MC_ADVANCE_RIP_AND_FINISH();
840	IEM_MC_END();
841	}
842	else
843	{
844	/*
845	* XMM, [mem8].
846	*/
847	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
848	IEM_MC_LOCAL(uint8_t, uSrc);
849	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
850
851	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
852	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
853	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
854	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
855	IEM_MC_PREPARE_SSE_USAGE();
856
857	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
858	IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/, uSrc);
859	IEM_MC_ADVANCE_RIP_AND_FINISH();
860	IEM_MC_END();
861	}
862	}
863
864	/** Opcode 0x66 0x0f 0x21, */
865	FNIEMOP_DEF(iemOp_insertps_Vdq_UdqMd_Ib)
866	{
867	IEMOP_MNEMONIC3(RMI, INSERTPS, insertps, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0); /// @todo
868	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
869	if (IEM_IS_MODRM_REG_MODE(bRm))
870	{
871	/*
872	* XMM, XMM.
873	*/
874	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
875	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
876	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
877	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
878	IEM_MC_PREPARE_SSE_USAGE();
879
880	IEM_MC_LOCAL(uint32_t, uSrc);
881	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), (bImm >> 6) & 3);
882	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc);
883	IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
884
885	IEM_MC_ADVANCE_RIP_AND_FINISH();
886	IEM_MC_END();
887	}
888	else
889	{
890	/*
891	* XMM, [mem32].
892	*/
893	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
894	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
895	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
896	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
897
898	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
899	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
900	IEM_MC_PREPARE_SSE_USAGE();
901
902	IEM_MC_LOCAL(uint32_t, uSrc);
903	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
904	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc);
905	IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
906	IEM_MC_ADVANCE_RIP_AND_FINISH();
907	IEM_MC_END();
908	}
909	}
910
911	FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib)
912	{
913	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
914	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
915	{
916	/**
917	* @opcode 0x22
918	* @opcodesub rex.w=1
919	* @oppfx 0x66
920	* @opcpuid sse
921	*/
922	IEMOP_MNEMONIC3(RMI, PINSRQ, pinsrq, Vq, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
923	if (IEM_IS_MODRM_REG_MODE(bRm))
924	{
925	/*
926	* XMM, greg64.
927	*/
928	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
929	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
930	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
931	IEM_MC_LOCAL(uint64_t, uSrc);
932	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
933	IEM_MC_PREPARE_SSE_USAGE();
934	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
935	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /a_iQword/, uSrc);
936	IEM_MC_ADVANCE_RIP_AND_FINISH();
937	IEM_MC_END();
938	}
939	else
940	{
941	/*
942	* XMM, [mem64].
943	*/
944	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
945	IEM_MC_LOCAL(uint64_t, uSrc);
946	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
947
948	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
949	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
950	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
951	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
952	IEM_MC_PREPARE_SSE_USAGE();
953
954	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
955	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /a_iQword/, uSrc);
956	IEM_MC_ADVANCE_RIP_AND_FINISH();
957	IEM_MC_END();
958	}
959	}
960	else
961	{
962	/**
963	* @opdone
964	* @opcode 0x22
965	* @opcodesub rex.w=0
966	* @oppfx 0x66
967	* @opcpuid sse
968	*/
969	IEMOP_MNEMONIC3(RMI, PINSRD, pinsrd, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
970	if (IEM_IS_MODRM_REG_MODE(bRm))
971	{
972	/*
973	* XMM, greg32.
974	*/
975	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
976	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
977	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
978	IEM_MC_LOCAL(uint32_t, uSrc);
979	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
980	IEM_MC_PREPARE_SSE_USAGE();
981	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
982	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/, uSrc);
983	IEM_MC_ADVANCE_RIP_AND_FINISH();
984	IEM_MC_END();
985	}
986	else
987	{
988	/*
989	* XMM, [mem32].
990	*/
991	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
992	IEM_MC_LOCAL(uint32_t, uSrc);
993	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
994
995	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
996	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
997	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
998	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
999	IEM_MC_PREPARE_SSE_USAGE();
1000
1001	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1002	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/, uSrc);
1003	IEM_MC_ADVANCE_RIP_AND_FINISH();
1004	IEM_MC_END();
1005	}
1006	}
1007	}
1008
1009
1010	/* Opcode 0x66 0x0f 0x23 - invalid */
1011	/* Opcode 0x66 0x0f 0x24 - invalid */
1012	/* Opcode 0x66 0x0f 0x25 - invalid */
1013	/* Opcode 0x66 0x0f 0x26 - invalid */
1014	/* Opcode 0x66 0x0f 0x27 - invalid */
1015	/* Opcode 0x66 0x0f 0x28 - invalid */
1016	/* Opcode 0x66 0x0f 0x29 - invalid */
1017	/* Opcode 0x66 0x0f 0x2a - invalid */
1018	/* Opcode 0x66 0x0f 0x2b - invalid */
1019	/* Opcode 0x66 0x0f 0x2c - invalid */
1020	/* Opcode 0x66 0x0f 0x2d - invalid */
1021	/* Opcode 0x66 0x0f 0x2e - invalid */
1022	/* Opcode 0x66 0x0f 0x2f - invalid */
1023
1024
1025	/* Opcode 0x66 0x0f 0x30 - invalid */
1026	/* Opcode 0x66 0x0f 0x31 - invalid */
1027	/* Opcode 0x66 0x0f 0x32 - invalid */
1028	/* Opcode 0x66 0x0f 0x33 - invalid */
1029	/* Opcode 0x66 0x0f 0x34 - invalid */
1030	/* Opcode 0x66 0x0f 0x35 - invalid */
1031	/* Opcode 0x66 0x0f 0x36 - invalid */
1032	/* Opcode 0x66 0x0f 0x37 - invalid */
1033	/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
1034	/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
1035	/* Opcode 0x66 0x0f 0x3a - invalid */
1036	/* Opcode 0x66 0x0f 0x3b - invalid */
1037	/* Opcode 0x66 0x0f 0x3c - invalid */
1038	/* Opcode 0x66 0x0f 0x3d - invalid */
1039	/* Opcode 0x66 0x0f 0x3e - invalid */
1040	/* Opcode 0x66 0x0f 0x3f - invalid */
1041
1042
1043	/** Opcode 0x66 0x0f 0x40. */
1044	FNIEMOP_DEF(iemOp_dpps_Vx_Wx_Ib)
1045	{
1046	IEMOP_MNEMONIC3(RMI, DPPS, dpps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1047	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
1048	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback));
1049	}
1050
1051
1052	/** Opcode 0x66 0x0f 0x41, */
1053	FNIEMOP_DEF(iemOp_dppd_Vdq_Wdq_Ib)
1054	{
1055	IEMOP_MNEMONIC3(RMI, DPPD, dppd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1056	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
1057	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback));
1058	}
1059
1060
1061	/** Opcode 0x66 0x0f 0x42. */
1062	FNIEMOP_DEF(iemOp_mpsadbw_Vx_Wx_Ib)
1063	{
1064	IEMOP_MNEMONIC3(RMI, MPSADBW, mpsadbw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1065	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
1066	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback));
1067	}
1068
1069
1070	/* Opcode 0x66 0x0f 0x43 - invalid */
1071
1072
1073	/** Opcode 0x66 0x0f 0x44. */
1074	FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
1075	{
1076	IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1077
1078	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1079	if (IEM_IS_MODRM_REG_MODE(bRm))
1080	{
1081	/*
1082	* Register, register.
1083	*/
1084	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1085	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1086	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fPclMul);
1087	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1088	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1089	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1090	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1091	IEM_MC_PREPARE_SSE_USAGE();
1092	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1093	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1094	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1095	iemAImpl_pclmulqdq_u128,
1096	iemAImpl_pclmulqdq_u128_fallback),
1097	puDst, puSrc, bImmArg);
1098	IEM_MC_ADVANCE_RIP_AND_FINISH();
1099	IEM_MC_END();
1100	}
1101	else
1102	{
1103	/*
1104	* Register, memory.
1105	*/
1106	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1107	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1108	IEM_MC_LOCAL(RTUINT128U, uSrc);
1109	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1110	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1111
1112	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1113	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1114	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1115	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fPclMul);
1116	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1117	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1118
1119	IEM_MC_PREPARE_SSE_USAGE();
1120	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1121	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1122	iemAImpl_pclmulqdq_u128,
1123	iemAImpl_pclmulqdq_u128_fallback),
1124	puDst, puSrc, bImmArg);
1125
1126	IEM_MC_ADVANCE_RIP_AND_FINISH();
1127	IEM_MC_END();
1128	}
1129	}
1130
1131
1132	/* Opcode 0x66 0x0f 0x45 - invalid */
1133	/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
1134	/* Opcode 0x66 0x0f 0x47 - invalid */
1135	/* Opcode 0x66 0x0f 0x48 - invalid */
1136	/* Opcode 0x66 0x0f 0x49 - invalid */
1137	/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
1138	/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
1139	/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
1140	/* Opcode 0x66 0x0f 0x4d - invalid */
1141	/* Opcode 0x66 0x0f 0x4e - invalid */
1142	/* Opcode 0x66 0x0f 0x4f - invalid */
1143
1144
1145	/* Opcode 0x66 0x0f 0x50 - invalid */
1146	/* Opcode 0x66 0x0f 0x51 - invalid */
1147	/* Opcode 0x66 0x0f 0x52 - invalid */
1148	/* Opcode 0x66 0x0f 0x53 - invalid */
1149	/* Opcode 0x66 0x0f 0x54 - invalid */
1150	/* Opcode 0x66 0x0f 0x55 - invalid */
1151	/* Opcode 0x66 0x0f 0x56 - invalid */
1152	/* Opcode 0x66 0x0f 0x57 - invalid */
1153	/* Opcode 0x66 0x0f 0x58 - invalid */
1154	/* Opcode 0x66 0x0f 0x59 - invalid */
1155	/* Opcode 0x66 0x0f 0x5a - invalid */
1156	/* Opcode 0x66 0x0f 0x5b - invalid */
1157	/* Opcode 0x66 0x0f 0x5c - invalid */
1158	/* Opcode 0x66 0x0f 0x5d - invalid */
1159	/* Opcode 0x66 0x0f 0x5e - invalid */
1160	/* Opcode 0x66 0x0f 0x5f - invalid */
1161
1162
1163	/**
1164	* @opcode 0x60
1165	* @oppfx 0x66
1166	* @opflmodify cf,pf,af,zf,sf,of
1167	* @opflclear pf,af
1168	*/
1169	FNIEMOP_DEF(iemOp_pcmpestrm_Vdq_Wdq_Ib)
1170	{
1171	IEMOP_MNEMONIC3(RMI, PCMPESTRM, pcmpestrm, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1172
1173	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1174	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1175	{
1176	if (IEM_IS_MODRM_REG_MODE(bRm))
1177	{
1178	/*
1179	* Register, register.
1180	*/
1181	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1182	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1183	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1184	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1185	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1186	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1187	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1188	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1189	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1190	IEM_MC_PREPARE_SSE_USAGE();
1191	IEM_MC_FETCH_XREG_PAIR_U128_AND_RAX_RDX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1192	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1193	IEM_MC_REF_EFLAGS(pEFlags);
1194	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1195	iemAImpl_pcmpestrm_u128,
1196	iemAImpl_pcmpestrm_u128_fallback),
1197	puDst, pEFlags, pSrc, bImmArg);
1198	IEM_MC_ADVANCE_RIP_AND_FINISH();
1199	IEM_MC_END();
1200	}
1201	else
1202	{
1203	/*
1204	* Register, memory.
1205	*/
1206	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1207	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1208	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1209	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1210	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1211	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1212
1213	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1214	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1215	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1216	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1217	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1218	IEM_MC_PREPARE_SSE_USAGE();
1219
1220	IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
1221	pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1222	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1223	IEM_MC_REF_EFLAGS(pEFlags);
1224	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1225	iemAImpl_pcmpestrm_u128,
1226	iemAImpl_pcmpestrm_u128_fallback),
1227	puDst, pEFlags, pSrc, bImmArg);
1228	IEM_MC_ADVANCE_RIP_AND_FINISH();
1229	IEM_MC_END();
1230	}
1231	}
1232	else
1233	{
1234	if (IEM_IS_MODRM_REG_MODE(bRm))
1235	{
1236	/*
1237	* Register, register.
1238	*/
1239	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1240	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1241	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1242	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1243	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1244	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1245	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1246	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1247	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1248	IEM_MC_PREPARE_SSE_USAGE();
1249	IEM_MC_FETCH_XREG_PAIR_U128_AND_EAX_EDX_U32_SX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1250	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1251	IEM_MC_REF_EFLAGS(pEFlags);
1252	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1253	iemAImpl_pcmpestrm_u128,
1254	iemAImpl_pcmpestrm_u128_fallback),
1255	puDst, pEFlags, pSrc, bImmArg);
1256	IEM_MC_ADVANCE_RIP_AND_FINISH();
1257	IEM_MC_END();
1258	}
1259	else
1260	{
1261	/*
1262	* Register, memory.
1263	*/
1264	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1265	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1266	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1267	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1268	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1269	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1270
1271	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1272	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1273	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1274	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1275	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1276	IEM_MC_PREPARE_SSE_USAGE();
1277
1278	IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
1279	pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1280	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1281	IEM_MC_REF_EFLAGS(pEFlags);
1282	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1283	iemAImpl_pcmpestrm_u128,
1284	iemAImpl_pcmpestrm_u128_fallback),
1285	puDst, pEFlags, pSrc, bImmArg);
1286	IEM_MC_ADVANCE_RIP_AND_FINISH();
1287	IEM_MC_END();
1288	}
1289	}
1290	}
1291
1292
1293	/**
1294	* @opcode 0x61
1295	* @oppfx 0x66
1296	* @opflmodify cf,pf,af,zf,sf,of
1297	* @opflclear pf,af
1298	*/
1299	FNIEMOP_DEF(iemOp_pcmpestri_Vdq_Wdq_Ib)
1300	{
1301	IEMOP_MNEMONIC3(RMI, PCMPESTRI, pcmpestri, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1302
1303	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1304	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1305	{
1306	if (IEM_IS_MODRM_REG_MODE(bRm))
1307	{
1308	/*
1309	* Register, register.
1310	*/
1311	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1312	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1313	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1314	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1315	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1316	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1317	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1318	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1319	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1320	IEM_MC_PREPARE_SSE_USAGE();
1321	IEM_MC_FETCH_XREG_PAIR_U128_AND_RAX_RDX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1322	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1323	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1324	IEM_MC_REF_EFLAGS(pEFlags);
1325	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1326	iemAImpl_pcmpestri_u128,
1327	iemAImpl_pcmpestri_u128_fallback),
1328	pu32Ecx, pEFlags, pSrc, bImmArg);
1329	/** @todo testcase: High dword of RCX cleared? */
1330	IEM_MC_ADVANCE_RIP_AND_FINISH();
1331	IEM_MC_END();
1332	}
1333	else
1334	{
1335	/*
1336	* Register, memory.
1337	*/
1338	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1339	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1340	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1341	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1342	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1343	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1344
1345	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1346	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1347	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1348	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1349	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1350	IEM_MC_PREPARE_SSE_USAGE();
1351
1352	IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
1353	pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1354	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1355	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1356	IEM_MC_REF_EFLAGS(pEFlags);
1357	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1358	iemAImpl_pcmpestri_u128,
1359	iemAImpl_pcmpestri_u128_fallback),
1360	pu32Ecx, pEFlags, pSrc, bImmArg);
1361	/** @todo testcase: High dword of RCX cleared? */
1362	IEM_MC_ADVANCE_RIP_AND_FINISH();
1363	IEM_MC_END();
1364	}
1365	}
1366	else
1367	{
1368	if (IEM_IS_MODRM_REG_MODE(bRm))
1369	{
1370	/*
1371	* Register, register.
1372	*/
1373	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1374	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1375	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1376	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1377	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1378	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1379	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1380	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1381	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1382	IEM_MC_PREPARE_SSE_USAGE();
1383	IEM_MC_FETCH_XREG_PAIR_U128_AND_EAX_EDX_U32_SX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1384	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1385	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1386	IEM_MC_REF_EFLAGS(pEFlags);
1387	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1388	iemAImpl_pcmpestri_u128,
1389	iemAImpl_pcmpestri_u128_fallback),
1390	pu32Ecx, pEFlags, pSrc, bImmArg);
1391	/** @todo testcase: High dword of RCX cleared? */
1392	IEM_MC_ADVANCE_RIP_AND_FINISH();
1393	IEM_MC_END();
1394	}
1395	else
1396	{
1397	/*
1398	* Register, memory.
1399	*/
1400	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1401	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1402	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1403	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1404	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1405	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1406
1407	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1408	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1409	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1410	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1411	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1412	IEM_MC_PREPARE_SSE_USAGE();
1413
1414	IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
1415	pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1416	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1417	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1418	IEM_MC_REF_EFLAGS(pEFlags);
1419	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1420	iemAImpl_pcmpestri_u128,
1421	iemAImpl_pcmpestri_u128_fallback),
1422	pu32Ecx, pEFlags, pSrc, bImmArg);
1423	/** @todo testcase: High dword of RCX cleared? */
1424	IEM_MC_ADVANCE_RIP_AND_FINISH();
1425	IEM_MC_END();
1426	}
1427	}
1428	}
1429
1430
1431	/**
1432	* @opcode 0x62
1433	* @oppfx 0x66
1434	* @opflmodify cf,pf,af,zf,sf,of
1435	* @opflclear pf,af
1436	*/
1437	FNIEMOP_DEF(iemOp_pcmpistrm_Vdq_Wdq_Ib)
1438	{
1439	IEMOP_MNEMONIC3(RMI, PCMPISTRM, pcmpistrm, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1440
1441	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1442	if (IEM_IS_MODRM_REG_MODE(bRm))
1443	{
1444	/*
1445	* Register, register.
1446	*/
1447	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1448	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1449	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1450	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1451	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1452	IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1453	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1454	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1455	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1456	IEM_MC_PREPARE_SSE_USAGE();
1457	IEM_MC_FETCH_XREG_PAIR_U128(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1458	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1459	IEM_MC_REF_EFLAGS(pEFlags);
1460	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1461	iemAImpl_pcmpistrm_u128,
1462	iemAImpl_pcmpistrm_u128_fallback),
1463	puDst, pEFlags, pSrc, bImmArg);
1464	IEM_MC_ADVANCE_RIP_AND_FINISH();
1465	IEM_MC_END();
1466	}
1467	else
1468	{
1469	/*
1470	* Register, memory.
1471	*/
1472	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1473	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1474	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1475	IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1476	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1477	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1478
1479	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1480	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1481	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1482	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1483	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1484	IEM_MC_PREPARE_SSE_USAGE();
1485
1486	IEM_MC_FETCH_MEM_U128_AND_XREG_U128(Src, IEM_GET_MODRM_REG(pVCpu, bRm), pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1487	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1488	IEM_MC_REF_EFLAGS(pEFlags);
1489	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1490	iemAImpl_pcmpistrm_u128,
1491	iemAImpl_pcmpistrm_u128_fallback),
1492	puDst, pEFlags, pSrc, bImmArg);
1493	IEM_MC_ADVANCE_RIP_AND_FINISH();
1494	IEM_MC_END();
1495	}
1496	}
1497
1498
1499	/**
1500	* @opcode 0x63
1501	* @oppfx 0x66
1502	* @opflmodify cf,pf,af,zf,sf,of
1503	* @opflclear pf,af
1504	*/
1505	FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
1506	{
1507	IEMOP_MNEMONIC3(RMI, PCMPISTRI, pcmpistri, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1508
1509	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1510	if (IEM_IS_MODRM_REG_MODE(bRm))
1511	{
1512	/*
1513	* Register, register.
1514	*/
1515	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1516	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1517	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1518	IEM_MC_ARG(uint32_t *, pEFlags, 0);
1519	IEM_MC_ARG(PCRTUINT128U, pSrc1, 1);
1520	IEM_MC_ARG(PCRTUINT128U, pSrc2, 2);
1521	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1522	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1523	IEM_MC_PREPARE_SSE_USAGE();
1524	IEM_MC_REF_XREG_U128_CONST(pSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1525	IEM_MC_REF_XREG_U128_CONST(pSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1526	IEM_MC_REF_EFLAGS(pEFlags);
1527	IEM_MC_CALL_AIMPL_4(uint32_t, u32Ecx,
1528	IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1529	iemAImpl_pcmpistri_u128,
1530	iemAImpl_pcmpistri_u128_fallback),
1531	pEFlags, pSrc1, pSrc2, bImmArg);
1532	/** @todo testcase: High dword of RCX cleared? */
1533	IEM_MC_STORE_GREG_U32(X86_GREG_xCX, u32Ecx);
1534	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1535
1536	IEM_MC_ADVANCE_RIP_AND_FINISH();
1537	IEM_MC_END();
1538	}
1539	else
1540	{
1541	/*
1542	* Register, memory.
1543	*/
1544	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1545	IEM_MC_ARG(uint32_t *, pEFlags, 0);
1546	IEM_MC_ARG(PCRTUINT128U, pSrc1, 1);
1547	IEM_MC_LOCAL(RTUINT128U, Src2);
1548	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc2, Src2, 2);
1549	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1550
1551	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1552	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1553	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1554	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1555	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1556	IEM_MC_PREPARE_SSE_USAGE();
1557
1558	IEM_MC_FETCH_MEM_U128(Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1559	IEM_MC_REF_XREG_U128_CONST(pSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1560	IEM_MC_REF_EFLAGS(pEFlags);
1561	IEM_MC_CALL_AIMPL_4(uint32_t, u32Ecx,
1562	IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1563	iemAImpl_pcmpistri_u128,
1564	iemAImpl_pcmpistri_u128_fallback),
1565	pEFlags, pSrc1, pSrc2, bImmArg);
1566	/** @todo testcase: High dword of RCX cleared? */
1567	IEM_MC_STORE_GREG_U32(X86_GREG_xCX, u32Ecx);
1568	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1569	IEM_MC_ADVANCE_RIP_AND_FINISH();
1570	IEM_MC_END();
1571	}
1572	}
1573
1574
1575	/* Opcode 0x66 0x0f 0x64 - invalid */
1576	/* Opcode 0x66 0x0f 0x65 - invalid */
1577	/* Opcode 0x66 0x0f 0x66 - invalid */
1578	/* Opcode 0x66 0x0f 0x67 - invalid */
1579	/* Opcode 0x66 0x0f 0x68 - invalid */
1580	/* Opcode 0x66 0x0f 0x69 - invalid */
1581	/* Opcode 0x66 0x0f 0x6a - invalid */
1582	/* Opcode 0x66 0x0f 0x6b - invalid */
1583	/* Opcode 0x66 0x0f 0x6c - invalid */
1584	/* Opcode 0x66 0x0f 0x6d - invalid */
1585	/* Opcode 0x66 0x0f 0x6e - invalid */
1586	/* Opcode 0x66 0x0f 0x6f - invalid */
1587
1588	/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
1589
1590
1591	/* Opcode 0x0f 0xc0 - invalid */
1592	/* Opcode 0x0f 0xc1 - invalid */
1593	/* Opcode 0x0f 0xc2 - invalid */
1594	/* Opcode 0x0f 0xc3 - invalid */
1595	/* Opcode 0x0f 0xc4 - invalid */
1596	/* Opcode 0x0f 0xc5 - invalid */
1597	/* Opcode 0x0f 0xc6 - invalid */
1598	/* Opcode 0x0f 0xc7 - invalid */
1599	/* Opcode 0x0f 0xc8 - invalid */
1600	/* Opcode 0x0f 0xc9 - invalid */
1601	/* Opcode 0x0f 0xca - invalid */
1602	/* Opcode 0x0f 0xcb - invalid */
1603
1604
1605	/* Opcode 0x0f 0xcc */
1606	FNIEMOP_DEF(iemOp_sha1rnds4_Vdq_Wdq_Ib)
1607	{
1608	IEMOP_MNEMONIC3(RMI, SHA1RNDS4, sha1rnds4, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1609
1610	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1611	if (IEM_IS_MODRM_REG_MODE(bRm))
1612	{
1613	/*
1614	* XMM, XMM, imm8
1615	*/
1616	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1617	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1618	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1619	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1620	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1621	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1622	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1623	IEM_MC_PREPARE_SSE_USAGE();
1624	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1625	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1626	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha,
1627	iemAImpl_sha1rnds4_u128,
1628	iemAImpl_sha1rnds4_u128_fallback),
1629	puDst, puSrc, bImmArg);
1630	IEM_MC_ADVANCE_RIP_AND_FINISH();
1631	IEM_MC_END();
1632	}
1633	else
1634	{
1635	/*
1636	* XMM, [mem128], imm8.
1637	*/
1638	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1639	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1640	IEM_MC_LOCAL(RTUINT128U, uSrc);
1641	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1642	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1643
1644	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1645	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1646	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1647	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1648	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1649	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1650
1651	IEM_MC_PREPARE_SSE_USAGE();
1652	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1653	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha,
1654	iemAImpl_sha1rnds4_u128,
1655	iemAImpl_sha1rnds4_u128_fallback),
1656	puDst, puSrc, bImmArg);
1657	IEM_MC_ADVANCE_RIP_AND_FINISH();
1658	IEM_MC_END();
1659	}
1660	}
1661
1662
1663	/* Opcode 0x0f 0xcd - invalid */
1664	/* Opcode 0x0f 0xce - invalid */
1665	/* Opcode 0x0f 0xcf - invalid */
1666
1667
1668	/* Opcode 0x66 0x0f 0xd0 - invalid */
1669	/* Opcode 0x66 0x0f 0xd1 - invalid */
1670	/* Opcode 0x66 0x0f 0xd2 - invalid */
1671	/* Opcode 0x66 0x0f 0xd3 - invalid */
1672	/* Opcode 0x66 0x0f 0xd4 - invalid */
1673	/* Opcode 0x66 0x0f 0xd5 - invalid */
1674	/* Opcode 0x66 0x0f 0xd6 - invalid */
1675	/* Opcode 0x66 0x0f 0xd7 - invalid */
1676	/* Opcode 0x66 0x0f 0xd8 - invalid */
1677	/* Opcode 0x66 0x0f 0xd9 - invalid */
1678	/* Opcode 0x66 0x0f 0xda - invalid */
1679	/* Opcode 0x66 0x0f 0xdb - invalid */
1680	/* Opcode 0x66 0x0f 0xdc - invalid */
1681	/* Opcode 0x66 0x0f 0xdd - invalid */
1682	/* Opcode 0x66 0x0f 0xde - invalid */
1683
1684
1685	/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
1686	FNIEMOP_DEF(iemOp_aeskeygen_Vdq_Wdq_Ib)
1687	{
1688	IEMOP_MNEMONIC3(RMI, AESKEYGEN, aeskeygen, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1689	return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFullImm8_To_Full,
1690	IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback));
1691	}
1692
1693
1694	/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
1695
1696
1697	/**
1698	* Three byte opcode map, first two bytes are 0x0f 0x3a.
1699	* @sa g_apfnVexMap2
1700	*/
1701	const PFNIEMOP g_apfnThreeByte0f3a[] =
1702	{
1703	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1704	/* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1705	/* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1706	/* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1707	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1708	/* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1709	/* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1710	/* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1711	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1712	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1713	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1714	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1715	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1716	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1717	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1718	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1719	/* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1720
1721	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1722	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1723	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1724	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1725	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1726	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1727	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1728	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1729	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1730	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1731	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1732	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1733	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1734	/* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1735	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1736	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1737
1738	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1739	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1740	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1741	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1742	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1743	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1744	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1745	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1746	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1747	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1748	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1749	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1750	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1751	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1752	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1753	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1754
1755	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1756	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1757	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1758	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1759	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1760	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1761	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1762	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1763	/* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1764	/* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1765	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1766	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1767	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1768	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1769	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1770	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1771
1772	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1773	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1774	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1775	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1776	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1777	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1778	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1779	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1780	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1781	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1782	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1783	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1784	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1785	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1786	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1787	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1788
1789	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1790	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1791	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1792	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1793	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1794	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1795	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1796	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1797	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1798	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1799	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1800	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1801	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1802	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1803	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1804	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1805
1806	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1807	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1808	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1809	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1810	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1811	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1812	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1813	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1814	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1815	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1816	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1817	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1818	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1819	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1820	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1821	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1822
1823	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1824	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1825	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1826	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1827	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1828	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1829	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1830	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1831	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1832	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1833	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1834	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1835	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1836	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1837	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1838	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1839
1840	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1841	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1842	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1843	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1844	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1845	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1846	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1847	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1848	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1849	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1850	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1851	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1852	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1853	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1854	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1855	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1856
1857	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1858	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1859	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1860	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1861	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1862	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1863	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1864	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1865	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1866	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1867	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1868	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1869	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1870	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1871	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1872	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1873
1874	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1875	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1876	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1877	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1878	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1879	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1880	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1881	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1882	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1883	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1884	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1885	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1886	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1887	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1888	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1889	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1890
1891	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1892	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1893	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1894	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1895	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1896	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1897	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1898	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1899	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1900	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1901	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1902	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1903	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1904	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1905	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1906	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1907
1908	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1909	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1910	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1911	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1912	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1913	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1914	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1915	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1916	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1917	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1918	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1919	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1920	/* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1921	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1922	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1923	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1924
1925	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1926	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1927	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1928	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1929	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1930	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1931	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1932	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1933	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1934	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1935	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1936	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1937	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1938	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1939	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1940	/* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1941
1942	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1943	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1944	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1945	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1946	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1947	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1948	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1949	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1950	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1951	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1952	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1953	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1954	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1955	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1956	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1957	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1958
1959	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1960	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1961	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1962	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1963	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1964	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1965	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1966	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1967	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1968	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1969	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1970	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1971	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1972	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1973	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1974	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1975	};
1976	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
1977
1978	/** @} */
1979

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstThree0f3a.cpp.h@ 106061

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