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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstThree0f38.cpp.h@ 106402

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1/* $Id: IEMAllInstThree0f38.cpp.h 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstVexMap2.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2024 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name Three byte opcodes with first two bytes 0x0f 0x38
33 * @{
34 */
35
36/**
37 * Common worker for MMX instructions on the form:
38 * pxxx mm1, mm2/mem64
39 * that was introduced with SSE3.
40 *
41 * The @a pfnU64 worker function takes no FXSAVE state, just the operands.
42 */
43FNIEMOP_DEF_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3, PFNIEMAIMPLMEDIAOPTF2U64, pfnU64)
44{
45 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
46 if (IEM_IS_MODRM_REG_MODE(bRm))
47 {
48 /*
49 * MMX, MMX.
50 */
51 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
52 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
53 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
54 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
55 IEM_MC_ARG(uint64_t *, pDst, 0);
56 IEM_MC_ARG(uint64_t const *, pSrc, 1);
57 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
58 IEM_MC_PREPARE_FPU_USAGE();
59 IEM_MC_FPU_TO_MMX_MODE();
60
61 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
62 IEM_MC_REF_MREG_U64_CONST(pSrc, IEM_GET_MODRM_RM_8(bRm));
63 IEM_MC_CALL_VOID_AIMPL_2(pfnU64, pDst, pSrc);
64 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
65
66 IEM_MC_ADVANCE_RIP_AND_FINISH();
67 IEM_MC_END();
68 }
69 else
70 {
71 /*
72 * MMX, [mem64].
73 */
74 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
75 IEM_MC_ARG(uint64_t *, pDst, 0);
76 IEM_MC_LOCAL(uint64_t, uSrc);
77 IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
78 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
79
80 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
81 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
82 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
83 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85 IEM_MC_PREPARE_FPU_USAGE();
86 IEM_MC_FPU_TO_MMX_MODE();
87
88 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
89 IEM_MC_CALL_VOID_AIMPL_2(pfnU64, pDst, pSrc);
90 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
91
92 IEM_MC_ADVANCE_RIP_AND_FINISH();
93 IEM_MC_END();
94 }
95}
96
97
98/**
99 * Common worker for SSSE3 instructions on the forms:
100 * pxxx xmm1, xmm2/mem128
101 *
102 * Proper alignment of the 128-bit operand is enforced.
103 * Exceptions type 4. SSSE3 cpuid checks.
104 *
105 * The @a pfnU128 worker function takes no FXSAVE state, just the operands.
106 *
107 * @sa iemOpCommonSse2Opt_FullFull_To_Full
108 */
109FNIEMOP_DEF_1(iemOpCommonSsse3Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
110{
111 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
112 if (IEM_IS_MODRM_REG_MODE(bRm))
113 {
114 /*
115 * Register, register.
116 */
117 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
118 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
119 IEM_MC_ARG(PRTUINT128U, puDst, 0);
120 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
121 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
122 IEM_MC_PREPARE_SSE_USAGE();
123 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
124 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
125 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
126 IEM_MC_ADVANCE_RIP_AND_FINISH();
127 IEM_MC_END();
128 }
129 else
130 {
131 /*
132 * Register, memory.
133 */
134 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
135 IEM_MC_ARG(PRTUINT128U, puDst, 0);
136 IEM_MC_LOCAL(RTUINT128U, uSrc);
137 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
138 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
139
140 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
141 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
142 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
143 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
144
145 IEM_MC_PREPARE_SSE_USAGE();
146 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
147 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
148
149 IEM_MC_ADVANCE_RIP_AND_FINISH();
150 IEM_MC_END();
151 }
152}
153
154
155/**
156 * Common worker for SSE4.1 instructions on the forms:
157 * pxxx xmm1, xmm2/mem128
158 *
159 * Proper alignment of the 128-bit operand is enforced.
160 * Exceptions type 4. SSE4.1 cpuid checks.
161 *
162 * The @a pfnU128 worker function takes no FXSAVE state, just the operands.
163 *
164 * @sa iemOpCommonSse2Opt_FullFull_To_Full, iemOpCommonSsse3Opt_FullFull_To_Full,
165 * iemOpCommonSse41Opt_FullFull_To_Full, iemOpCommonSse42Opt_FullFull_To_Full
166 */
167FNIEMOP_DEF_1(iemOpCommonSse41Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
168{
169 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
170 if (IEM_IS_MODRM_REG_MODE(bRm))
171 {
172 /*
173 * Register, register.
174 */
175 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
176 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
177 IEM_MC_ARG(PRTUINT128U, puDst, 0);
178 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
179 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
180 IEM_MC_PREPARE_SSE_USAGE();
181 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
182 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
183 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
184 IEM_MC_ADVANCE_RIP_AND_FINISH();
185 IEM_MC_END();
186 }
187 else
188 {
189 /*
190 * Register, memory.
191 */
192 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
193 IEM_MC_ARG(PRTUINT128U, puDst, 0);
194 IEM_MC_LOCAL(RTUINT128U, uSrc);
195 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
196 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
197
198 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
199 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
200 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
201 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
202
203 IEM_MC_PREPARE_SSE_USAGE();
204 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
205 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
206
207 IEM_MC_ADVANCE_RIP_AND_FINISH();
208 IEM_MC_END();
209 }
210}
211
212
213/**
214 * Common worker for SSE4.2 instructions on the forms:
215 * pxxx xmm1, xmm2/mem128
216 *
217 * Proper alignment of the 128-bit operand is enforced.
218 * Exceptions type 4. SSE4.2 cpuid checks.
219 *
220 * @sa iemOpCommonSse2Opt_FullFull_To_Full, iemOpCommonSsse3Opt_FullFull_To_Full,
221 * iemOpCommonSse41Opt_FullFull_To_Full
222 */
223FNIEMOP_DEF_1(iemOpCommonSse42Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
224{
225 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
226 if (IEM_IS_MODRM_REG_MODE(bRm))
227 {
228 /*
229 * Register, register.
230 */
231 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
232 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
233 IEM_MC_ARG(PRTUINT128U, puDst, 0);
234 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
235 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
236 IEM_MC_PREPARE_SSE_USAGE();
237 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
238 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
239 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
240 IEM_MC_ADVANCE_RIP_AND_FINISH();
241 IEM_MC_END();
242 }
243 else
244 {
245 /*
246 * Register, memory.
247 */
248 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
249 IEM_MC_ARG(PRTUINT128U, puDst, 0);
250 IEM_MC_LOCAL(RTUINT128U, uSrc);
251 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
252 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
253
254 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
255 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
256 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
257 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
258
259 IEM_MC_PREPARE_SSE_USAGE();
260 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
261 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
262
263 IEM_MC_ADVANCE_RIP_AND_FINISH();
264 IEM_MC_END();
265 }
266}
267
268
269/**
270 * Common worker for SSE-style AES-NI instructions of the form:
271 * aesxxx xmm1, xmm2/mem128
272 *
273 * Proper alignment of the 128-bit operand is enforced.
274 * Exceptions type 4. AES-NI cpuid checks.
275 *
276 * Unlike iemOpCommonSse41_FullFull_To_Full, the @a pfnU128 worker function
277 * takes no FXSAVE state, just the operands.
278 *
279 * @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
280 * iemOpCommonSse41_FullFull_To_Full, iemOpCommonSha_FullFull_To_Full
281 */
282FNIEMOP_DEF_1(iemOpCommonAesNi_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
283{
284 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
285 if (IEM_IS_MODRM_REG_MODE(bRm))
286 {
287 /*
288 * Register, register.
289 */
290 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
291 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
292 IEM_MC_ARG(PRTUINT128U, puDst, 0);
293 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
294 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
295 IEM_MC_PREPARE_SSE_USAGE();
296 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
297 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
298 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
299 IEM_MC_ADVANCE_RIP_AND_FINISH();
300 IEM_MC_END();
301 }
302 else
303 {
304 /*
305 * Register, memory.
306 */
307 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
308 IEM_MC_ARG(PRTUINT128U, puDst, 0);
309 IEM_MC_LOCAL(RTUINT128U, uSrc);
310 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
311 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
312
313 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
314 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
315 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
316 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
317
318 IEM_MC_PREPARE_SSE_USAGE();
319 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
320 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
321
322 IEM_MC_ADVANCE_RIP_AND_FINISH();
323 IEM_MC_END();
324 }
325}
326
327
328/**
329 * Common worker for SSE-style SHA instructions of the form:
330 * shaxxx xmm1, xmm2/mem128
331 *
332 * Proper alignment of the 128-bit operand is enforced.
333 * Exceptions type 4. SHA cpuid checks.
334 *
335 * Unlike iemOpCommonSse41_FullFull_To_Full, the @a pfnU128 worker function
336 * takes no FXSAVE state, just the operands.
337 *
338 * @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
339 * iemOpCommonSse41_FullFull_To_Full, iemOpCommonSse42_FullFull_To_Full,
340 * iemOpCommonAesNi_FullFull_To_Full
341 */
342FNIEMOP_DEF_1(iemOpCommonSha_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
343{
344 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
345 if (IEM_IS_MODRM_REG_MODE(bRm))
346 {
347 /*
348 * Register, register.
349 */
350 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
351 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
352 IEM_MC_ARG(PRTUINT128U, puDst, 0);
353 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
354 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
355 IEM_MC_PREPARE_SSE_USAGE();
356 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
357 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
358 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
359 IEM_MC_ADVANCE_RIP_AND_FINISH();
360 IEM_MC_END();
361 }
362 else
363 {
364 /*
365 * Register, memory.
366 */
367 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
368 IEM_MC_ARG(PRTUINT128U, puDst, 0);
369 IEM_MC_LOCAL(RTUINT128U, uSrc);
370 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
371 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
372
373 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
374 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
375 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
376 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
377
378 IEM_MC_PREPARE_SSE_USAGE();
379 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
380 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
381
382 IEM_MC_ADVANCE_RIP_AND_FINISH();
383 IEM_MC_END();
384 }
385}
386
387
388/** Opcode 0x0f 0x38 0x00. */
389FNIEMOP_DEF(iemOp_pshufb_Pq_Qq)
390{
391 IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
392 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
393 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u64,&iemAImpl_pshufb_u64_fallback));
394}
395
396
397/** Opcode 0x66 0x0f 0x38 0x00. */
398FNIEMOP_DEF(iemOp_pshufb_Vx_Wx)
399{
400 IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
401 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
402 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback));
403
404}
405
406
407/* Opcode 0x0f 0x38 0x01. */
408FNIEMOP_DEF(iemOp_phaddw_Pq_Qq)
409{
410 IEMOP_MNEMONIC2(RM, PHADDW, phaddw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
411 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
412 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddw_u64,&iemAImpl_phaddw_u64_fallback));
413}
414
415
416/** Opcode 0x66 0x0f 0x38 0x01. */
417FNIEMOP_DEF(iemOp_phaddw_Vx_Wx)
418{
419 IEMOP_MNEMONIC2(RM, PHADDW, phaddw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
420 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
421 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback));
422
423}
424
425
426/** Opcode 0x0f 0x38 0x02. */
427FNIEMOP_DEF(iemOp_phaddd_Pq_Qq)
428{
429 IEMOP_MNEMONIC2(RM, PHADDD, phaddd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
430 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
431 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddd_u64,&iemAImpl_phaddd_u64_fallback));
432}
433
434
435/** Opcode 0x66 0x0f 0x38 0x02. */
436FNIEMOP_DEF(iemOp_phaddd_Vx_Wx)
437{
438 IEMOP_MNEMONIC2(RM, PHADDD, phaddd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
439 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
440 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback));
441
442}
443
444
445/** Opcode 0x0f 0x38 0x03. */
446FNIEMOP_DEF(iemOp_phaddsw_Pq_Qq)
447{
448 IEMOP_MNEMONIC2(RM, PHADDSW, phaddsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
449 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
450 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddsw_u64,&iemAImpl_phaddsw_u64_fallback));
451}
452
453
454/** Opcode 0x66 0x0f 0x38 0x03. */
455FNIEMOP_DEF(iemOp_phaddsw_Vx_Wx)
456{
457 IEMOP_MNEMONIC2(RM, PHADDSW, phaddsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
458 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
459 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback));
460
461}
462
463
464/** Opcode 0x0f 0x38 0x04. */
465FNIEMOP_DEF(iemOp_pmaddubsw_Pq_Qq)
466{
467 IEMOP_MNEMONIC2(RM, PMADDUBSW, pmaddubsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
468 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
469 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmaddubsw_u64, &iemAImpl_pmaddubsw_u64_fallback));
470}
471
472
473/** Opcode 0x66 0x0f 0x38 0x04. */
474FNIEMOP_DEF(iemOp_pmaddubsw_Vx_Wx)
475{
476 IEMOP_MNEMONIC2(RM, PMADDUBSW, pmaddubsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
477 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
478 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback));
479
480}
481
482
483/** Opcode 0x0f 0x38 0x05. */
484FNIEMOP_DEF(iemOp_phsubw_Pq_Qq)
485{
486 IEMOP_MNEMONIC2(RM, PHSUBW, phsubw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
487 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
488 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubw_u64,&iemAImpl_phsubw_u64_fallback));
489}
490
491
492/** Opcode 0x66 0x0f 0x38 0x05. */
493FNIEMOP_DEF(iemOp_phsubw_Vx_Wx)
494{
495 IEMOP_MNEMONIC2(RM, PHSUBW, phsubw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
496 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
497 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback));
498
499}
500
501
502/** Opcode 0x0f 0x38 0x06. */
503FNIEMOP_DEF(iemOp_phsubd_Pq_Qq)
504{
505 IEMOP_MNEMONIC2(RM, PHSUBD, phsubd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
506 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
507 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubd_u64,&iemAImpl_phsubd_u64_fallback));
508}
509
510
511
512/** Opcode 0x66 0x0f 0x38 0x06. */
513FNIEMOP_DEF(iemOp_phsubd_Vx_Wx)
514{
515 IEMOP_MNEMONIC2(RM, PHSUBD, phsubd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
516 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
517 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback));
518
519}
520
521
522/** Opcode 0x0f 0x38 0x07. */
523FNIEMOP_DEF(iemOp_phsubsw_Pq_Qq)
524{
525 IEMOP_MNEMONIC2(RM, PHSUBSW, phsubsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
526 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
527 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubsw_u64,&iemAImpl_phsubsw_u64_fallback));
528}
529
530
531/** Opcode 0x66 0x0f 0x38 0x07. */
532FNIEMOP_DEF(iemOp_phsubsw_Vx_Wx)
533{
534 IEMOP_MNEMONIC2(RM, PHSUBSW, phsubsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
535 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
536 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback));
537
538}
539
540
541/** Opcode 0x0f 0x38 0x08. */
542FNIEMOP_DEF(iemOp_psignb_Pq_Qq)
543{
544 IEMOP_MNEMONIC2(RM, PSIGNB, psignb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
545 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
546 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignb_u64, &iemAImpl_psignb_u64_fallback));
547}
548
549
550/** Opcode 0x66 0x0f 0x38 0x08. */
551FNIEMOP_DEF(iemOp_psignb_Vx_Wx)
552{
553 IEMOP_MNEMONIC2(RM, PSIGNB, psignb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
554 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
555 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback));
556
557}
558
559
560/** Opcode 0x0f 0x38 0x09. */
561FNIEMOP_DEF(iemOp_psignw_Pq_Qq)
562{
563 IEMOP_MNEMONIC2(RM, PSIGNW, psignw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
564 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
565 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignw_u64, &iemAImpl_psignw_u64_fallback));
566}
567
568
569/** Opcode 0x66 0x0f 0x38 0x09. */
570FNIEMOP_DEF(iemOp_psignw_Vx_Wx)
571{
572 IEMOP_MNEMONIC2(RM, PSIGNW, psignw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
573 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
574 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback));
575
576}
577
578
579/** Opcode 0x0f 0x38 0x0a. */
580FNIEMOP_DEF(iemOp_psignd_Pq_Qq)
581{
582 IEMOP_MNEMONIC2(RM, PSIGND, psignd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
583 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
584 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignd_u64, &iemAImpl_psignd_u64_fallback));
585}
586
587
588/** Opcode 0x66 0x0f 0x38 0x0a. */
589FNIEMOP_DEF(iemOp_psignd_Vx_Wx)
590{
591 IEMOP_MNEMONIC2(RM, PSIGND, psignd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
592 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
593 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback));
594
595}
596
597
598/** Opcode 0x0f 0x38 0x0b. */
599FNIEMOP_DEF(iemOp_pmulhrsw_Pq_Qq)
600{
601 IEMOP_MNEMONIC2(RM, PMULHRSW, pmulhrsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
602 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
603 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmulhrsw_u64, &iemAImpl_pmulhrsw_u64_fallback));
604}
605
606
607/** Opcode 0x66 0x0f 0x38 0x0b. */
608FNIEMOP_DEF(iemOp_pmulhrsw_Vx_Wx)
609{
610 IEMOP_MNEMONIC2(RM, PMULHRSW, pmulhrsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
611 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
612 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback));
613
614}
615
616
617/* Opcode 0x0f 0x38 0x0c - invalid. */
618/* Opcode 0x66 0x0f 0x38 0x0c - invalid (vex only). */
619/* Opcode 0x0f 0x38 0x0d - invalid. */
620/* Opcode 0x66 0x0f 0x38 0x0d - invalid (vex only). */
621/* Opcode 0x0f 0x38 0x0e - invalid. */
622/* Opcode 0x66 0x0f 0x38 0x0e - invalid (vex only). */
623/* Opcode 0x0f 0x38 0x0f - invalid. */
624/* Opcode 0x66 0x0f 0x38 0x0f - invalid (vex only). */
625
626
627/* Opcode 0x0f 0x38 0x10 - invalid */
628
629
630/** Body for the *blend* instructions. */
631#define IEMOP_BODY_P_BLEND_X(a_Instr) \
632 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
633 if (IEM_IS_MODRM_REG_MODE(bRm)) \
634 { \
635 /* \
636 * Register, register. \
637 */ \
638 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
639 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
640 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
641 IEM_MC_ARG(PCRTUINT128U, puSrc, 1); \
642 IEM_MC_ARG(PCRTUINT128U, puMask, 2); \
643 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); \
644 IEM_MC_PREPARE_SSE_USAGE(); \
645 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
646 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
647 IEM_MC_REF_XREG_U128_CONST(puMask, 0); \
648 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
649 iemAImpl_ ## a_Instr ## _u128, \
650 iemAImpl_ ## a_Instr ## _u128_fallback), \
651 puDst, puSrc, puMask); \
652 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
653 IEM_MC_END(); \
654 } \
655 else \
656 { \
657 /* \
658 * Register, memory. \
659 */ \
660 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
661 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
662 IEM_MC_LOCAL(RTUINT128U, uSrc); \
663 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
664 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1); \
665 IEM_MC_ARG(PCRTUINT128U, puMask, 2); \
666 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
667 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
668 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); \
669 IEM_MC_PREPARE_SSE_USAGE(); \
670 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
671 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
672 IEM_MC_REF_XREG_U128_CONST(puMask, 0); \
673 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
674 iemAImpl_ ## a_Instr ## _u128, \
675 iemAImpl_ ## a_Instr ## _u128_fallback), \
676 puDst, puSrc, puMask); \
677 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
678 IEM_MC_END(); \
679 } \
680 (void)0
681
682/** Opcode 0x66 0x0f 0x38 0x10 (legacy only). */
683FNIEMOP_DEF(iemOp_pblendvb_Vdq_Wdq)
684{
685 IEMOP_MNEMONIC3EX(pblendvb_Vdq_Wdq_XMM0, "pblendvb Vdq,Wdq,xmm0",
686 RM0, PBLENDVB, pblendvb, Vdq, Wdq, REG_XMM0, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
687 IEMOP_BODY_P_BLEND_X(pblendvb);
688}
689
690
691/* Opcode 0x0f 0x38 0x11 - invalid */
692/* Opcode 0x66 0x0f 0x38 0x11 - invalid */
693/* Opcode 0x0f 0x38 0x12 - invalid */
694/* Opcode 0x66 0x0f 0x38 0x12 - invalid */
695/* Opcode 0x0f 0x38 0x13 - invalid */
696/* Opcode 0x66 0x0f 0x38 0x13 - invalid (vex only). */
697/* Opcode 0x0f 0x38 0x14 - invalid */
698
699
700/** Opcode 0x66 0x0f 0x38 0x14 (legacy only). */
701FNIEMOP_DEF(iemOp_blendvps_Vdq_Wdq)
702{
703 IEMOP_MNEMONIC3EX(blendvps_Vdq_Wdq_XMM0, "blendvps Vdq,Wdq,xmm0",
704 RM0, BLENDVPS, blendvps, Vdq, Wdq, REG_XMM0, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
705 IEMOP_BODY_P_BLEND_X(blendvps);
706}
707
708
709/* Opcode 0x0f 0x38 0x15 - invalid */
710
711
712/** Opcode 0x66 0x0f 0x38 0x15 (legacy only). */
713FNIEMOP_DEF(iemOp_blendvpd_Vdq_Wdq)
714{
715 IEMOP_MNEMONIC3EX(blendvpd_Vdq_Wdq_XMM0, "blendvpd Vdq,Wdq,xmm0",
716 RM0, BLENDVPD, blendvpd, Vdq, Wdq, REG_XMM0, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
717 IEMOP_BODY_P_BLEND_X(blendvpd);
718}
719
720
721/* Opcode 0x0f 0x38 0x16 - invalid */
722/* Opcode 0x66 0x0f 0x38 0x16 - invalid (vex only). */
723/* Opcode 0x0f 0x38 0x17 - invalid */
724
725
726/**
727 * @opcode 0x17
728 * @oppfx 0x66
729 * @opflmodify cf,pf,af,zf,sf,of
730 * @opflclear pf,af,sf,of
731 */
732FNIEMOP_DEF(iemOp_ptest_Vx_Wx)
733{
734 IEMOP_MNEMONIC2(RM, PTEST, ptest, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
735 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
736 if (IEM_IS_MODRM_REG_MODE(bRm))
737 {
738 /*
739 * Register, register.
740 */
741 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
742 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
743 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
744 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
745 IEM_MC_ARG(uint32_t *, pEFlags, 2);
746 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
747 IEM_MC_PREPARE_SSE_USAGE();
748 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
749 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
750 IEM_MC_REF_EFLAGS(pEFlags);
751 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
752 IEM_MC_ADVANCE_RIP_AND_FINISH();
753 IEM_MC_END();
754 }
755 else
756 {
757 /*
758 * Register, memory.
759 */
760 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
761 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
762 IEM_MC_LOCAL(RTUINT128U, uSrc2);
763 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
764 IEM_MC_ARG(uint32_t *, pEFlags, 2);
765 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
766
767 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
768 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
769 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
770 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
771
772 IEM_MC_PREPARE_SSE_USAGE();
773 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
774 IEM_MC_REF_EFLAGS(pEFlags);
775 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
776
777 IEM_MC_ADVANCE_RIP_AND_FINISH();
778 IEM_MC_END();
779 }
780}
781
782
783/* Opcode 0x0f 0x38 0x18 - invalid */
784/* Opcode 0x66 0x0f 0x38 0x18 - invalid (vex only). */
785/* Opcode 0x0f 0x38 0x19 - invalid */
786/* Opcode 0x66 0x0f 0x38 0x19 - invalid (vex only). */
787/* Opcode 0x0f 0x38 0x1a - invalid */
788/* Opcode 0x66 0x0f 0x38 0x1a - invalid (vex only). */
789/* Opcode 0x0f 0x38 0x1b - invalid */
790/* Opcode 0x66 0x0f 0x38 0x1b - invalid */
791
792
793/** Opcode 0x0f 0x38 0x1c. */
794FNIEMOP_DEF(iemOp_pabsb_Pq_Qq)
795{
796 IEMOP_MNEMONIC2(RM, PABSB, pabsb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
797 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
798 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsb_u64, &iemAImpl_pabsb_u64_fallback));
799}
800
801
802/** Opcode 0x66 0x0f 0x38 0x1c. */
803FNIEMOP_DEF(iemOp_pabsb_Vx_Wx)
804{
805 IEMOP_MNEMONIC2(RM, PABSB, pabsb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
806 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
807 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback));
808
809}
810
811
812/** Opcode 0x0f 0x38 0x1d. */
813FNIEMOP_DEF(iemOp_pabsw_Pq_Qq)
814{
815 IEMOP_MNEMONIC2(RM, PABSW, pabsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
816 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
817 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsw_u64, &iemAImpl_pabsw_u64_fallback));
818}
819
820
821/** Opcode 0x66 0x0f 0x38 0x1d. */
822FNIEMOP_DEF(iemOp_pabsw_Vx_Wx)
823{
824 IEMOP_MNEMONIC2(RM, PABSW, pabsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
825 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
826 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback));
827
828}
829
830
831/** Opcode 0x0f 0x38 0x1e. */
832FNIEMOP_DEF(iemOp_pabsd_Pq_Qq)
833{
834 IEMOP_MNEMONIC2(RM, PABSD, pabsd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
835 return FNIEMOP_CALL_1(iemOpCommonMmxOpt_FullFull_To_Full_Ssse3,
836 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsd_u64, &iemAImpl_pabsd_u64_fallback));
837}
838
839
840/** Opcode 0x66 0x0f 0x38 0x1e. */
841FNIEMOP_DEF(iemOp_pabsd_Vx_Wx)
842{
843 IEMOP_MNEMONIC2(RM, PABSD, pabsd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
844 return FNIEMOP_CALL_1(iemOpCommonSsse3Opt_FullFull_To_Full,
845 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback));
846
847}
848
849
850/* Opcode 0x0f 0x38 0x1f - invalid */
851/* Opcode 0x66 0x0f 0x38 0x1f - invalid */
852
853
854/** Body for the pmov{s,z}x* instructions. */
855#define IEMOP_BODY_PMOV_S_Z(a_Instr, a_SrcWidth, a_fRegNativeArchs, a_fMemNativeArchs) \
856 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
857 if (IEM_IS_MODRM_REG_MODE(bRm)) \
858 { \
859 /* \
860 * Register, register. \
861 */ \
862 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
863 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
864 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
865 IEM_MC_ARG(uint ## a_SrcWidth ## _t, uSrc, 1); \
866 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); \
867 IEM_MC_PREPARE_SSE_USAGE(); \
868 IEM_MC_NATIVE_IF(a_fRegNativeArchs) { \
869 IEM_MC_NATIVE_EMIT_2(RT_CONCAT3(iemNativeEmit_,a_Instr,_rr_u128), IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm)); \
870 } IEM_MC_NATIVE_ELSE() { \
871 IEM_MC_FETCH_XREG_U ## a_SrcWidth (uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0); \
872 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
873 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
874 iemAImpl_ ## a_Instr ## _u128, \
875 iemAImpl_v ## a_Instr ## _u128_fallback), \
876 puDst, uSrc); \
877 } IEM_MC_NATIVE_ENDIF(); \
878 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
879 IEM_MC_END(); \
880 } \
881 else \
882 { \
883 /* \
884 * Register, memory. \
885 */ \
886 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
887 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
888 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
889 IEM_MC_ARG(uint ## a_SrcWidth ## _t, uSrc, 1); \
890 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
891 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
892 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); \
893 IEM_MC_PREPARE_SSE_USAGE(); \
894 IEM_MC_FETCH_MEM_U## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
895 IEM_MC_NATIVE_IF(a_fMemNativeArchs) { \
896 IEM_MC_NATIVE_EMIT_2(RT_CONCAT3(iemNativeEmit_,a_Instr,_rv_u128), IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); \
897 } IEM_MC_NATIVE_ELSE() { \
898 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
899 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
900 iemAImpl_ ## a_Instr ## _u128, \
901 iemAImpl_v ## a_Instr ## _u128_fallback), \
902 puDst, uSrc); \
903 } IEM_MC_NATIVE_ENDIF(); \
904 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
905 IEM_MC_END(); \
906 } \
907 (void)0
908
909
910/** Opcode 0x66 0x0f 0x38 0x20. */
911FNIEMOP_DEF(iemOp_pmovsxbw_Vx_UxMq)
912{
913 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
914 IEMOP_MNEMONIC2(RM, PMOVSXBW, pmovsxbw, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
915 IEMOP_BODY_PMOV_S_Z(pmovsxbw, 64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
916}
917
918
919/** Opcode 0x66 0x0f 0x38 0x21. */
920FNIEMOP_DEF(iemOp_pmovsxbd_Vx_UxMd)
921{
922 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
923 IEMOP_MNEMONIC2(RM, PMOVSXBD, pmovsxbd, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
924 IEMOP_BODY_PMOV_S_Z(pmovsxbd, 32, 0, 0);
925}
926
927
928/** Opcode 0x66 0x0f 0x38 0x22. */
929FNIEMOP_DEF(iemOp_pmovsxbq_Vx_UxMw)
930{
931 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
932 IEMOP_MNEMONIC2(RM, PMOVSXBQ, pmovsxbq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
933 IEMOP_BODY_PMOV_S_Z(pmovsxbq, 16, 0, 0);
934}
935
936
937/** Opcode 0x66 0x0f 0x38 0x23. */
938FNIEMOP_DEF(iemOp_pmovsxwd_Vx_UxMq)
939{
940 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
941 IEMOP_MNEMONIC2(RM, PMOVSXWD, pmovsxwd, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
942 IEMOP_BODY_PMOV_S_Z(pmovsxwd, 64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
943}
944
945
946/** Opcode 0x66 0x0f 0x38 0x24. */
947FNIEMOP_DEF(iemOp_pmovsxwq_Vx_UxMd)
948{
949 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
950 IEMOP_MNEMONIC2(RM, PMOVSXWQ, pmovsxwq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
951 IEMOP_BODY_PMOV_S_Z(pmovsxwq, 32, 0, 0);
952}
953
954
955/** Opcode 0x66 0x0f 0x38 0x25. */
956FNIEMOP_DEF(iemOp_pmovsxdq_Vx_UxMq)
957{
958 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
959 IEMOP_MNEMONIC2(RM, PMOVSXDQ, pmovsxdq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
960 IEMOP_BODY_PMOV_S_Z(pmovsxdq, 64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
961}
962
963
964/* Opcode 0x66 0x0f 0x38 0x26 - invalid */
965/* Opcode 0x66 0x0f 0x38 0x27 - invalid */
966
967
968/** Opcode 0x66 0x0f 0x38 0x28. */
969FNIEMOP_DEF(iemOp_pmuldq_Vx_Wx)
970{
971 IEMOP_MNEMONIC2(RM, PMULDQ, pmuldq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
972 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
973 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback));
974}
975
976
977/** Opcode 0x66 0x0f 0x38 0x29. */
978FNIEMOP_DEF(iemOp_pcmpeqq_Vx_Wx)
979{
980 IEMOP_MNEMONIC2(RM, PCMPEQQ, pcmpeqq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
981 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
982 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback));
983}
984
985
986/**
987 * @opcode 0x2a
988 * @opcodesub !11 mr/reg
989 * @oppfx 0x66
990 * @opcpuid sse4.1
991 * @opgroup og_sse41_cachect
992 * @opxcpttype 1
993 * @optest op1=-1 op2=2 -> op1=2
994 * @optest op1=0 op2=-42 -> op1=-42
995 */
996FNIEMOP_DEF(iemOp_movntdqa_Vdq_Mdq)
997{
998 IEMOP_MNEMONIC2(RM_MEM, MOVNTDQA, movntdqa, Vdq_WO, Mdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
999 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1000 if (IEM_IS_MODRM_MEM_MODE(bRm))
1001 {
1002 /* Register, memory. */
1003 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1004 IEM_MC_LOCAL(RTUINT128U, uSrc);
1005 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1006
1007 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1008 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
1009 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1010 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1011
1012 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1013 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1014
1015 IEM_MC_ADVANCE_RIP_AND_FINISH();
1016 IEM_MC_END();
1017 }
1018
1019 /**
1020 * @opdone
1021 * @opmnemonic ud660f382areg
1022 * @opcode 0x2a
1023 * @opcodesub 11 mr/reg
1024 * @oppfx 0x66
1025 * @opunused immediate
1026 * @opcpuid sse
1027 * @optest ->
1028 */
1029 else
1030 IEMOP_RAISE_INVALID_OPCODE_RET();
1031}
1032
1033
1034/** Opcode 0x66 0x0f 0x38 0x2b. */
1035FNIEMOP_DEF(iemOp_packusdw_Vx_Wx)
1036{
1037 IEMOP_MNEMONIC2(RM, PACKUSDW, packusdw, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1038 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full, iemAImpl_packusdw_u128);
1039}
1040
1041
1042/* Opcode 0x66 0x0f 0x38 0x2c - invalid (vex only). */
1043/* Opcode 0x66 0x0f 0x38 0x2d - invalid (vex only). */
1044/* Opcode 0x66 0x0f 0x38 0x2e - invalid (vex only). */
1045/* Opcode 0x66 0x0f 0x38 0x2f - invalid (vex only). */
1046
1047/** Opcode 0x66 0x0f 0x38 0x30. */
1048FNIEMOP_DEF(iemOp_pmovzxbw_Vx_UxMq)
1049{
1050 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1051 IEMOP_MNEMONIC2(RM, PMOVZXBW, pmovzxbw, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1052 IEMOP_BODY_PMOV_S_Z(pmovzxbw, 64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
1053}
1054
1055
1056/** Opcode 0x66 0x0f 0x38 0x31. */
1057FNIEMOP_DEF(iemOp_pmovzxbd_Vx_UxMd)
1058{
1059 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1060 IEMOP_MNEMONIC2(RM, PMOVZXBD, pmovzxbd, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1061 IEMOP_BODY_PMOV_S_Z(pmovzxbd, 32, 0, 0);
1062}
1063
1064
1065/** Opcode 0x66 0x0f 0x38 0x32. */
1066FNIEMOP_DEF(iemOp_pmovzxbq_Vx_UxMw)
1067{
1068 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1069 IEMOP_MNEMONIC2(RM, PMOVZXBQ, pmovzxbq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1070 IEMOP_BODY_PMOV_S_Z(pmovzxbq, 16, 0, 0);
1071}
1072
1073
1074/** Opcode 0x66 0x0f 0x38 0x33. */
1075FNIEMOP_DEF(iemOp_pmovzxwd_Vx_UxMq)
1076{
1077 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1078 IEMOP_MNEMONIC2(RM, PMOVZXWD, pmovzxwd, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1079 IEMOP_BODY_PMOV_S_Z(pmovzxwd, 64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
1080}
1081
1082
1083/** Opcode 0x66 0x0f 0x38 0x34. */
1084FNIEMOP_DEF(iemOp_pmovzxwq_Vx_UxMd)
1085{
1086 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1087 IEMOP_MNEMONIC2(RM, PMOVZXWQ, pmovzxwq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1088 IEMOP_BODY_PMOV_S_Z(pmovzxwq, 32, 0, 0);
1089}
1090
1091
1092/** Opcode 0x66 0x0f 0x38 0x35. */
1093FNIEMOP_DEF(iemOp_pmovzxdq_Vx_UxMq)
1094{
1095 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1096 IEMOP_MNEMONIC2(RM, PMOVZXDQ, pmovzxdq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1097 IEMOP_BODY_PMOV_S_Z(pmovzxdq, 64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
1098}
1099
1100
1101/* Opcode 0x66 0x0f 0x38 0x36 - invalid (vex only). */
1102
1103
1104/** Opcode 0x66 0x0f 0x38 0x37. */
1105FNIEMOP_DEF(iemOp_pcmpgtq_Vx_Wx)
1106{
1107 IEMOP_MNEMONIC2(RM, PCMPGTQ, pcmpgtq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1108 return FNIEMOP_CALL_1(iemOpCommonSse42Opt_FullFull_To_Full,
1109 IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback));
1110}
1111
1112
1113/** Opcode 0x66 0x0f 0x38 0x38. */
1114FNIEMOP_DEF(iemOp_pminsb_Vx_Wx)
1115{
1116 IEMOP_MNEMONIC2(RM, PMINSB, pminsb, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1117 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1118 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback));
1119}
1120
1121
1122/** Opcode 0x66 0x0f 0x38 0x39. */
1123FNIEMOP_DEF(iemOp_pminsd_Vx_Wx)
1124{
1125 IEMOP_MNEMONIC2(RM, PMINSD, pminsd, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1126 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1127 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback));
1128}
1129
1130
1131/** Opcode 0x66 0x0f 0x38 0x3a. */
1132FNIEMOP_DEF(iemOp_pminuw_Vx_Wx)
1133{
1134 IEMOP_MNEMONIC2(RM, PMINUW, pminuw, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1135 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1136 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback));
1137}
1138
1139
1140/** Opcode 0x66 0x0f 0x38 0x3b. */
1141FNIEMOP_DEF(iemOp_pminud_Vx_Wx)
1142{
1143 IEMOP_MNEMONIC2(RM, PMINUD, pminud, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1144 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1145 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback));
1146}
1147
1148
1149/** Opcode 0x66 0x0f 0x38 0x3c. */
1150FNIEMOP_DEF(iemOp_pmaxsb_Vx_Wx)
1151{
1152 IEMOP_MNEMONIC2(RM, PMAXSB, pmaxsb, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1153 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1154 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback));
1155}
1156
1157
1158/** Opcode 0x66 0x0f 0x38 0x3d. */
1159FNIEMOP_DEF(iemOp_pmaxsd_Vx_Wx)
1160{
1161 IEMOP_MNEMONIC2(RM, PMAXSD, pmaxsd, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1162 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1163 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback));
1164}
1165
1166
1167/** Opcode 0x66 0x0f 0x38 0x3e. */
1168FNIEMOP_DEF(iemOp_pmaxuw_Vx_Wx)
1169{
1170 IEMOP_MNEMONIC2(RM, PMAXUW, pmaxuw, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1171 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1172 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback));
1173}
1174
1175
1176/** Opcode 0x66 0x0f 0x38 0x3f. */
1177FNIEMOP_DEF(iemOp_pmaxud_Vx_Wx)
1178{
1179 IEMOP_MNEMONIC2(RM, PMAXUD, pmaxud, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1180 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1181 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback));
1182}
1183
1184
1185/** Opcode 0x66 0x0f 0x38 0x40. */
1186FNIEMOP_DEF(iemOp_pmulld_Vx_Wx)
1187{
1188 IEMOP_MNEMONIC2(RM, PMULLD, pmulld, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1189 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1190 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback));
1191}
1192
1193
1194/** Opcode 0x66 0x0f 0x38 0x41. */
1195FNIEMOP_DEF(iemOp_phminposuw_Vdq_Wdq)
1196{
1197 IEMOP_MNEMONIC2(RM, PHMINPOSUW, phminposuw, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1198 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1199 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback));
1200}
1201
1202
1203/* Opcode 0x66 0x0f 0x38 0x42 - invalid. */
1204/* Opcode 0x66 0x0f 0x38 0x43 - invalid. */
1205/* Opcode 0x66 0x0f 0x38 0x44 - invalid. */
1206/* Opcode 0x66 0x0f 0x38 0x45 - invalid (vex only). */
1207/* Opcode 0x66 0x0f 0x38 0x46 - invalid (vex only). */
1208/* Opcode 0x66 0x0f 0x38 0x47 - invalid (vex only). */
1209/* Opcode 0x66 0x0f 0x38 0x48 - invalid. */
1210/* Opcode 0x66 0x0f 0x38 0x49 - invalid. */
1211/* Opcode 0x66 0x0f 0x38 0x4a - invalid. */
1212/* Opcode 0x66 0x0f 0x38 0x4b - invalid. */
1213/* Opcode 0x66 0x0f 0x38 0x4c - invalid. */
1214/* Opcode 0x66 0x0f 0x38 0x4d - invalid. */
1215/* Opcode 0x66 0x0f 0x38 0x4e - invalid. */
1216/* Opcode 0x66 0x0f 0x38 0x4f - invalid. */
1217
1218/* Opcode 0x66 0x0f 0x38 0x50 - invalid. */
1219/* Opcode 0x66 0x0f 0x38 0x51 - invalid. */
1220/* Opcode 0x66 0x0f 0x38 0x52 - invalid. */
1221/* Opcode 0x66 0x0f 0x38 0x53 - invalid. */
1222/* Opcode 0x66 0x0f 0x38 0x54 - invalid. */
1223/* Opcode 0x66 0x0f 0x38 0x55 - invalid. */
1224/* Opcode 0x66 0x0f 0x38 0x56 - invalid. */
1225/* Opcode 0x66 0x0f 0x38 0x57 - invalid. */
1226/* Opcode 0x66 0x0f 0x38 0x58 - invalid (vex only). */
1227/* Opcode 0x66 0x0f 0x38 0x59 - invalid (vex only). */
1228/* Opcode 0x66 0x0f 0x38 0x5a - invalid (vex only). */
1229/* Opcode 0x66 0x0f 0x38 0x5b - invalid. */
1230/* Opcode 0x66 0x0f 0x38 0x5c - invalid. */
1231/* Opcode 0x66 0x0f 0x38 0x5d - invalid. */
1232/* Opcode 0x66 0x0f 0x38 0x5e - invalid. */
1233/* Opcode 0x66 0x0f 0x38 0x5f - invalid. */
1234
1235/* Opcode 0x66 0x0f 0x38 0x60 - invalid. */
1236/* Opcode 0x66 0x0f 0x38 0x61 - invalid. */
1237/* Opcode 0x66 0x0f 0x38 0x62 - invalid. */
1238/* Opcode 0x66 0x0f 0x38 0x63 - invalid. */
1239/* Opcode 0x66 0x0f 0x38 0x64 - invalid. */
1240/* Opcode 0x66 0x0f 0x38 0x65 - invalid. */
1241/* Opcode 0x66 0x0f 0x38 0x66 - invalid. */
1242/* Opcode 0x66 0x0f 0x38 0x67 - invalid. */
1243/* Opcode 0x66 0x0f 0x38 0x68 - invalid. */
1244/* Opcode 0x66 0x0f 0x38 0x69 - invalid. */
1245/* Opcode 0x66 0x0f 0x38 0x6a - invalid. */
1246/* Opcode 0x66 0x0f 0x38 0x6b - invalid. */
1247/* Opcode 0x66 0x0f 0x38 0x6c - invalid. */
1248/* Opcode 0x66 0x0f 0x38 0x6d - invalid. */
1249/* Opcode 0x66 0x0f 0x38 0x6e - invalid. */
1250/* Opcode 0x66 0x0f 0x38 0x6f - invalid. */
1251
1252/* Opcode 0x66 0x0f 0x38 0x70 - invalid. */
1253/* Opcode 0x66 0x0f 0x38 0x71 - invalid. */
1254/* Opcode 0x66 0x0f 0x38 0x72 - invalid. */
1255/* Opcode 0x66 0x0f 0x38 0x73 - invalid. */
1256/* Opcode 0x66 0x0f 0x38 0x74 - invalid. */
1257/* Opcode 0x66 0x0f 0x38 0x75 - invalid. */
1258/* Opcode 0x66 0x0f 0x38 0x76 - invalid. */
1259/* Opcode 0x66 0x0f 0x38 0x77 - invalid. */
1260/* Opcode 0x66 0x0f 0x38 0x78 - invalid (vex only). */
1261/* Opcode 0x66 0x0f 0x38 0x79 - invalid (vex only). */
1262/* Opcode 0x66 0x0f 0x38 0x7a - invalid. */
1263/* Opcode 0x66 0x0f 0x38 0x7b - invalid. */
1264/* Opcode 0x66 0x0f 0x38 0x7c - invalid. */
1265/* Opcode 0x66 0x0f 0x38 0x7d - invalid. */
1266/* Opcode 0x66 0x0f 0x38 0x7e - invalid. */
1267/* Opcode 0x66 0x0f 0x38 0x7f - invalid. */
1268
1269/** Opcode 0x66 0x0f 0x38 0x80. */
1270#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1271FNIEMOP_DEF(iemOp_invept_Gy_Mdq)
1272{
1273 IEMOP_MNEMONIC(invept, "invept Gy,Mdq");
1274 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1275 if (IEM_IS_MODRM_MEM_MODE(bRm))
1276 {
1277 /* Register, memory. */
1278 IEMOP_HLP_NO_REAL_OR_V86_MODE();
1279 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1280 {
1281 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1282 IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
1283 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
1284 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1285 IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
1286 IEMOP_HLP_VMX_INSTR( "invept", kVmxVDiag_Invept);
1287 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1288 IEM_MC_ARG(uint64_t, uInveptType, 2);
1289 IEM_MC_FETCH_GREG_U64(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
1290 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 0,
1291 iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
1292 IEM_MC_END();
1293 }
1294 else
1295 {
1296 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1297 IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
1298 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
1299 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1300 IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
1301 IEMOP_HLP_VMX_INSTR( "invept", kVmxVDiag_Invept);
1302 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1303 IEM_MC_ARG(uint32_t, uInveptType, 2);
1304 IEM_MC_FETCH_GREG_U32(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
1305 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 0,
1306 iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
1307 IEM_MC_END();
1308 }
1309 }
1310 Log(("iemOp_invept_Gy_Mdq: invalid encoding -> #UD\n"));
1311 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1312 IEMOP_RAISE_INVALID_OPCODE_RET();
1313}
1314#else
1315FNIEMOP_UD_STUB(iemOp_invept_Gy_Mdq);
1316#endif
1317
1318/** Opcode 0x66 0x0f 0x38 0x81. */
1319#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1320FNIEMOP_DEF(iemOp_invvpid_Gy_Mdq)
1321{
1322 IEMOP_MNEMONIC(invvpid, "invvpid Gy,Mdq");
1323 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1324 if (IEM_IS_MODRM_MEM_MODE(bRm))
1325 {
1326 /* Register, memory. */
1327 IEMOP_HLP_NO_REAL_OR_V86_MODE();
1328 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1329 {
1330 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1331 IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
1332 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
1333 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1334 IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
1335 IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
1336 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1337 IEM_MC_ARG(uint64_t, uInvvpidType, 2);
1338 IEM_MC_FETCH_GREG_U64(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1339 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 0,
1340 iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
1341 IEM_MC_END();
1342 }
1343 else
1344 {
1345 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1346 IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
1347 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
1348 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1349 IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
1350 IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
1351 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1352 IEM_MC_ARG(uint32_t, uInvvpidType, 2);
1353 IEM_MC_FETCH_GREG_U32(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1354 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_STATUS_FLAGS, 0,
1355 iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
1356 IEM_MC_END();
1357 }
1358 }
1359 Log(("iemOp_invvpid_Gy_Mdq: invalid encoding -> #UD\n"));
1360 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1361 IEMOP_RAISE_INVALID_OPCODE_RET();
1362}
1363#else
1364FNIEMOP_UD_STUB(iemOp_invvpid_Gy_Mdq);
1365#endif
1366
1367/** Opcode 0x66 0x0f 0x38 0x82. */
1368FNIEMOP_DEF(iemOp_invpcid_Gy_Mdq)
1369{
1370 IEMOP_MNEMONIC(invpcid, "invpcid Gy,Mdq");
1371 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1372 if (IEM_IS_MODRM_MEM_MODE(bRm))
1373 {
1374 /* Register, memory. */
1375 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1376 {
1377 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1378 IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
1379 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
1380 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1381 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1382 IEM_MC_ARG(uint64_t, uInvpcidType, 2);
1383 IEM_MC_FETCH_GREG_U64(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1384 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
1385 IEM_MC_END();
1386 }
1387 else
1388 {
1389 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1390 IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
1391 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
1392 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1393 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
1394 IEM_MC_ARG(uint32_t, uInvpcidType, 2);
1395 IEM_MC_FETCH_GREG_U32(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1396 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
1397 IEM_MC_END();
1398 }
1399 }
1400 Log(("iemOp_invpcid_Gy_Mdq: invalid encoding -> #UD\n"));
1401 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1402 IEMOP_RAISE_INVALID_OPCODE_RET();
1403}
1404
1405
1406/* Opcode 0x66 0x0f 0x38 0x83 - invalid. */
1407/* Opcode 0x66 0x0f 0x38 0x84 - invalid. */
1408/* Opcode 0x66 0x0f 0x38 0x85 - invalid. */
1409/* Opcode 0x66 0x0f 0x38 0x86 - invalid. */
1410/* Opcode 0x66 0x0f 0x38 0x87 - invalid. */
1411/* Opcode 0x66 0x0f 0x38 0x88 - invalid. */
1412/* Opcode 0x66 0x0f 0x38 0x89 - invalid. */
1413/* Opcode 0x66 0x0f 0x38 0x8a - invalid. */
1414/* Opcode 0x66 0x0f 0x38 0x8b - invalid. */
1415/* Opcode 0x66 0x0f 0x38 0x8c - invalid (vex only). */
1416/* Opcode 0x66 0x0f 0x38 0x8d - invalid. */
1417/* Opcode 0x66 0x0f 0x38 0x8e - invalid (vex only). */
1418/* Opcode 0x66 0x0f 0x38 0x8f - invalid. */
1419
1420/* Opcode 0x66 0x0f 0x38 0x90 - invalid (vex only). */
1421/* Opcode 0x66 0x0f 0x38 0x91 - invalid (vex only). */
1422/* Opcode 0x66 0x0f 0x38 0x92 - invalid (vex only). */
1423/* Opcode 0x66 0x0f 0x38 0x93 - invalid (vex only). */
1424/* Opcode 0x66 0x0f 0x38 0x94 - invalid. */
1425/* Opcode 0x66 0x0f 0x38 0x95 - invalid. */
1426/* Opcode 0x66 0x0f 0x38 0x96 - invalid (vex only). */
1427/* Opcode 0x66 0x0f 0x38 0x97 - invalid (vex only). */
1428/* Opcode 0x66 0x0f 0x38 0x98 - invalid (vex only). */
1429/* Opcode 0x66 0x0f 0x38 0x99 - invalid (vex only). */
1430/* Opcode 0x66 0x0f 0x38 0x9a - invalid (vex only). */
1431/* Opcode 0x66 0x0f 0x38 0x9b - invalid (vex only). */
1432/* Opcode 0x66 0x0f 0x38 0x9c - invalid (vex only). */
1433/* Opcode 0x66 0x0f 0x38 0x9d - invalid (vex only). */
1434/* Opcode 0x66 0x0f 0x38 0x9e - invalid (vex only). */
1435/* Opcode 0x66 0x0f 0x38 0x9f - invalid (vex only). */
1436
1437/* Opcode 0x66 0x0f 0x38 0xa0 - invalid. */
1438/* Opcode 0x66 0x0f 0x38 0xa1 - invalid. */
1439/* Opcode 0x66 0x0f 0x38 0xa2 - invalid. */
1440/* Opcode 0x66 0x0f 0x38 0xa3 - invalid. */
1441/* Opcode 0x66 0x0f 0x38 0xa4 - invalid. */
1442/* Opcode 0x66 0x0f 0x38 0xa5 - invalid. */
1443/* Opcode 0x66 0x0f 0x38 0xa6 - invalid (vex only). */
1444/* Opcode 0x66 0x0f 0x38 0xa7 - invalid (vex only). */
1445/* Opcode 0x66 0x0f 0x38 0xa8 - invalid (vex only). */
1446/* Opcode 0x66 0x0f 0x38 0xa9 - invalid (vex only). */
1447/* Opcode 0x66 0x0f 0x38 0xaa - invalid (vex only). */
1448/* Opcode 0x66 0x0f 0x38 0xab - invalid (vex only). */
1449/* Opcode 0x66 0x0f 0x38 0xac - invalid (vex only). */
1450/* Opcode 0x66 0x0f 0x38 0xad - invalid (vex only). */
1451/* Opcode 0x66 0x0f 0x38 0xae - invalid (vex only). */
1452/* Opcode 0x66 0x0f 0x38 0xaf - invalid (vex only). */
1453
1454/* Opcode 0x66 0x0f 0x38 0xb0 - invalid. */
1455/* Opcode 0x66 0x0f 0x38 0xb1 - invalid. */
1456/* Opcode 0x66 0x0f 0x38 0xb2 - invalid. */
1457/* Opcode 0x66 0x0f 0x38 0xb3 - invalid. */
1458/* Opcode 0x66 0x0f 0x38 0xb4 - invalid. */
1459/* Opcode 0x66 0x0f 0x38 0xb5 - invalid. */
1460/* Opcode 0x66 0x0f 0x38 0xb6 - invalid (vex only). */
1461/* Opcode 0x66 0x0f 0x38 0xb7 - invalid (vex only). */
1462/* Opcode 0x66 0x0f 0x38 0xb8 - invalid (vex only). */
1463/* Opcode 0x66 0x0f 0x38 0xb9 - invalid (vex only). */
1464/* Opcode 0x66 0x0f 0x38 0xba - invalid (vex only). */
1465/* Opcode 0x66 0x0f 0x38 0xbb - invalid (vex only). */
1466/* Opcode 0x66 0x0f 0x38 0xbc - invalid (vex only). */
1467/* Opcode 0x66 0x0f 0x38 0xbd - invalid (vex only). */
1468/* Opcode 0x66 0x0f 0x38 0xbe - invalid (vex only). */
1469/* Opcode 0x66 0x0f 0x38 0xbf - invalid (vex only). */
1470
1471/* Opcode 0x0f 0x38 0xc0 - invalid. */
1472/* Opcode 0x66 0x0f 0x38 0xc0 - invalid. */
1473/* Opcode 0x0f 0x38 0xc1 - invalid. */
1474/* Opcode 0x66 0x0f 0x38 0xc1 - invalid. */
1475/* Opcode 0x0f 0x38 0xc2 - invalid. */
1476/* Opcode 0x66 0x0f 0x38 0xc2 - invalid. */
1477/* Opcode 0x0f 0x38 0xc3 - invalid. */
1478/* Opcode 0x66 0x0f 0x38 0xc3 - invalid. */
1479/* Opcode 0x0f 0x38 0xc4 - invalid. */
1480/* Opcode 0x66 0x0f 0x38 0xc4 - invalid. */
1481/* Opcode 0x0f 0x38 0xc5 - invalid. */
1482/* Opcode 0x66 0x0f 0x38 0xc5 - invalid. */
1483/* Opcode 0x0f 0x38 0xc6 - invalid. */
1484/* Opcode 0x66 0x0f 0x38 0xc6 - invalid. */
1485/* Opcode 0x0f 0x38 0xc7 - invalid. */
1486/* Opcode 0x66 0x0f 0x38 0xc7 - invalid. */
1487
1488
1489/** Opcode 0x0f 0x38 0xc8. */
1490FNIEMOP_DEF(iemOp_sha1nexte_Vdq_Wdq)
1491{
1492 IEMOP_MNEMONIC2(RM, SHA1NEXTE, sha1nexte, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1493 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1494 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback));
1495}
1496
1497
1498/* Opcode 0x66 0x0f 0x38 0xc8 - invalid. */
1499
1500
1501/** Opcode 0x0f 0x38 0xc9. */
1502FNIEMOP_DEF(iemOp_sha1msg1_Vdq_Wdq)
1503{
1504 IEMOP_MNEMONIC2(RM, SHA1MSG1, sha1msg1, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1505 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1506 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback));
1507}
1508
1509
1510/* Opcode 0x66 0x0f 0x38 0xc9 - invalid. */
1511
1512
1513/** Opcode 0x0f 0x38 0xca. */
1514FNIEMOP_DEF(iemOp_sha1msg2_Vdq_Wdq)
1515{
1516 IEMOP_MNEMONIC2(RM, SHA1MSG2, sha1msg2, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1517 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1518 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback));
1519}
1520
1521
1522/* Opcode 0x66 0x0f 0x38 0xca - invalid. */
1523
1524
1525/** Opcode 0x0f 0x38 0xcb. */
1526FNIEMOP_DEF(iemOp_sha256rnds2_Vdq_Wdq)
1527{
1528 IEMOP_MNEMONIC2(RM, SHA256RNDS2, sha256rnds2, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES); /** @todo Actually RMI with implicit XMM0 */
1529 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1530 if (IEM_IS_MODRM_REG_MODE(bRm))
1531 {
1532 /*
1533 * Register, register.
1534 */
1535 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1536 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1537 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1538 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1539 IEM_MC_ARG(PCRTUINT128U, puXmm0, 2);
1540 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1541 IEM_MC_PREPARE_SSE_USAGE();
1542 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1543 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1544 IEM_MC_REF_XREG_U128_CONST(puXmm0, 0);
1545 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256rnds2_u128, iemAImpl_sha256rnds2_u128_fallback),
1546 puDst, puSrc, puXmm0);
1547 IEM_MC_ADVANCE_RIP_AND_FINISH();
1548 IEM_MC_END();
1549 }
1550 else
1551 {
1552 /*
1553 * Register, memory.
1554 */
1555 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1556 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1557 IEM_MC_LOCAL(RTUINT128U, uSrc);
1558 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1559 IEM_MC_ARG(PCRTUINT128U, puXmm0, 2);
1560 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1561
1562 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1563 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1564 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1565 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1566
1567 IEM_MC_PREPARE_SSE_USAGE();
1568 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1569 IEM_MC_REF_XREG_U128_CONST(puXmm0, 0);
1570 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256rnds2_u128, iemAImpl_sha256rnds2_u128_fallback),
1571 puDst, puSrc, puXmm0);
1572 IEM_MC_ADVANCE_RIP_AND_FINISH();
1573 IEM_MC_END();
1574 }
1575}
1576
1577
1578/* Opcode 0x66 0x0f 0x38 0xcb - invalid. */
1579
1580
1581/** Opcode 0x0f 0x38 0xcc. */
1582FNIEMOP_DEF(iemOp_sha256msg1_Vdq_Wdq)
1583{
1584 IEMOP_MNEMONIC2(RM, SHA256MSG1, sha256msg1, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1585 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1586 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback));
1587}
1588
1589
1590/* Opcode 0x66 0x0f 0x38 0xcc - invalid. */
1591
1592
1593/** Opcode 0x0f 0x38 0xcd. */
1594FNIEMOP_DEF(iemOp_sha256msg2_Vdq_Wdq)
1595{
1596 IEMOP_MNEMONIC2(RM, SHA256MSG2, sha256msg2, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1597 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1598 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback));
1599}
1600
1601
1602/* Opcode 0x66 0x0f 0x38 0xcd - invalid. */
1603/* Opcode 0x0f 0x38 0xce - invalid. */
1604/* Opcode 0x66 0x0f 0x38 0xce - invalid. */
1605/* Opcode 0x0f 0x38 0xcf - invalid. */
1606/* Opcode 0x66 0x0f 0x38 0xcf - invalid. */
1607
1608/* Opcode 0x66 0x0f 0x38 0xd0 - invalid. */
1609/* Opcode 0x66 0x0f 0x38 0xd1 - invalid. */
1610/* Opcode 0x66 0x0f 0x38 0xd2 - invalid. */
1611/* Opcode 0x66 0x0f 0x38 0xd3 - invalid. */
1612/* Opcode 0x66 0x0f 0x38 0xd4 - invalid. */
1613/* Opcode 0x66 0x0f 0x38 0xd5 - invalid. */
1614/* Opcode 0x66 0x0f 0x38 0xd6 - invalid. */
1615/* Opcode 0x66 0x0f 0x38 0xd7 - invalid. */
1616/* Opcode 0x66 0x0f 0x38 0xd8 - invalid. */
1617/* Opcode 0x66 0x0f 0x38 0xd9 - invalid. */
1618/* Opcode 0x66 0x0f 0x38 0xda - invalid. */
1619
1620
1621/** Opcode 0x66 0x0f 0x38 0xdb. */
1622FNIEMOP_DEF(iemOp_aesimc_Vdq_Wdq)
1623{
1624 IEMOP_MNEMONIC2(RM, AESIMC, aesimc, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1625 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1626 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback));
1627}
1628
1629
1630/** Opcode 0x66 0x0f 0x38 0xdc. */
1631FNIEMOP_DEF(iemOp_aesenc_Vdq_Wdq)
1632{
1633 IEMOP_MNEMONIC2(RM, AESENC, aesenc, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1634 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1635 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback));
1636}
1637
1638
1639/** Opcode 0x66 0x0f 0x38 0xdd. */
1640FNIEMOP_DEF(iemOp_aesenclast_Vdq_Wdq)
1641{
1642 IEMOP_MNEMONIC2(RM, AESENCLAST, aesenclast, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1643 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1644 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback));
1645}
1646
1647
1648/** Opcode 0x66 0x0f 0x38 0xde. */
1649FNIEMOP_DEF(iemOp_aesdec_Vdq_Wdq)
1650{
1651 IEMOP_MNEMONIC2(RM, AESDEC, aesdec, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1652 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1653 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback));
1654}
1655
1656
1657/** Opcode 0x66 0x0f 0x38 0xdf. */
1658FNIEMOP_DEF(iemOp_aesdeclast_Vdq_Wdq)
1659{
1660 IEMOP_MNEMONIC2(RM, AESDECLAST, aesdeclast, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1661 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1662 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback));
1663}
1664
1665
1666/* Opcode 0x66 0x0f 0x38 0xe0 - invalid. */
1667/* Opcode 0x66 0x0f 0x38 0xe1 - invalid. */
1668/* Opcode 0x66 0x0f 0x38 0xe2 - invalid. */
1669/* Opcode 0x66 0x0f 0x38 0xe3 - invalid. */
1670/* Opcode 0x66 0x0f 0x38 0xe4 - invalid. */
1671/* Opcode 0x66 0x0f 0x38 0xe5 - invalid. */
1672/* Opcode 0x66 0x0f 0x38 0xe6 - invalid. */
1673/* Opcode 0x66 0x0f 0x38 0xe7 - invalid. */
1674/* Opcode 0x66 0x0f 0x38 0xe8 - invalid. */
1675/* Opcode 0x66 0x0f 0x38 0xe9 - invalid. */
1676/* Opcode 0x66 0x0f 0x38 0xea - invalid. */
1677/* Opcode 0x66 0x0f 0x38 0xeb - invalid. */
1678/* Opcode 0x66 0x0f 0x38 0xec - invalid. */
1679/* Opcode 0x66 0x0f 0x38 0xed - invalid. */
1680/* Opcode 0x66 0x0f 0x38 0xee - invalid. */
1681/* Opcode 0x66 0x0f 0x38 0xef - invalid. */
1682
1683
1684/** Opcode [0x66] 0x0f 0x38 0xf0. */
1685FNIEMOP_DEF(iemOp_movbe_Gv_Mv)
1686{
1687 IEMOP_MNEMONIC2(RM, MOVBE, movbe, Gv, Ev, DISOPTYPE_HARMLESS, 0);
1688 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovBe)
1689 return iemOp_InvalidNeedRM(pVCpu);
1690
1691 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1692 if (!IEM_IS_MODRM_REG_MODE(bRm))
1693 {
1694 /*
1695 * Register, memory.
1696 */
1697 switch (pVCpu->iem.s.enmEffOpSize)
1698 {
1699 case IEMMODE_16BIT:
1700 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1701 IEM_MC_LOCAL(uint16_t, uSrc);
1702 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1703
1704 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1705 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1706 IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1707
1708 IEM_MC_BSWAP_LOCAL_U16(uSrc);
1709 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1710
1711 IEM_MC_ADVANCE_RIP_AND_FINISH();
1712 IEM_MC_END();
1713 break;
1714
1715 case IEMMODE_32BIT:
1716 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0);
1717 IEM_MC_LOCAL(uint32_t, uSrc);
1718 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1719
1720 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1721 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1722 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1723
1724 IEM_MC_BSWAP_LOCAL_U32(uSrc);
1725 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1726
1727 IEM_MC_ADVANCE_RIP_AND_FINISH();
1728 IEM_MC_END();
1729 break;
1730
1731 case IEMMODE_64BIT:
1732 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1733 IEM_MC_LOCAL(uint64_t, uSrc);
1734 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1735
1736 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1737 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1738 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1739
1740 IEM_MC_BSWAP_LOCAL_U64(uSrc);
1741 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1742
1743 IEM_MC_ADVANCE_RIP_AND_FINISH();
1744 IEM_MC_END();
1745 break;
1746
1747 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1748 }
1749 }
1750 else
1751 {
1752 /* Reg/reg not supported. */
1753 IEMOP_RAISE_INVALID_OPCODE_RET();
1754 }
1755}
1756
1757
1758/* Opcode 0xf3 0x0f 0x38 0xf0 - invalid. */
1759
1760
1761/** Opcode 0xf2 0x0f 0x38 0xf0. */
1762FNIEMOP_DEF(iemOp_crc32_Gd_Eb)
1763{
1764 IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Eb, DISOPTYPE_HARMLESS, 0);
1765 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1766 return iemOp_InvalidNeedRM(pVCpu);
1767
1768 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1769 if (IEM_IS_MODRM_REG_MODE(bRm))
1770 {
1771 /*
1772 * Register, register.
1773 */
1774 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1775 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1776 IEM_MC_ARG(uint32_t *, puDst, 0);
1777 IEM_MC_ARG(uint8_t, uSrc, 1);
1778 IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1779 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1780 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1781 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1782 IEM_MC_ADVANCE_RIP_AND_FINISH();
1783 IEM_MC_END();
1784 }
1785 else
1786 {
1787 /*
1788 * Register, memory.
1789 */
1790 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1791 IEM_MC_ARG(uint32_t *, puDst, 0);
1792 IEM_MC_ARG(uint8_t, uSrc, 1);
1793 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1794
1795 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1796 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1797 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1798
1799 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1800 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1801 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1802
1803 IEM_MC_ADVANCE_RIP_AND_FINISH();
1804 IEM_MC_END();
1805 }
1806}
1807
1808
1809/** Opcode [0x66] 0x0f 0x38 0xf1. */
1810FNIEMOP_DEF(iemOp_movbe_Mv_Gv)
1811{
1812 IEMOP_MNEMONIC2(MR, MOVBE, movbe, Ev, Gv, DISOPTYPE_HARMLESS, 0);
1813 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovBe)
1814 return iemOp_InvalidNeedRM(pVCpu);
1815
1816 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1817 if (!IEM_IS_MODRM_REG_MODE(bRm))
1818 {
1819 /*
1820 * Memory, register.
1821 */
1822 switch (pVCpu->iem.s.enmEffOpSize)
1823 {
1824 case IEMMODE_16BIT:
1825 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1826 IEM_MC_LOCAL(uint16_t, u16Value);
1827 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
1828 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1829 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1830 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_REG(pVCpu, bRm));
1831 IEM_MC_BSWAP_LOCAL_U16(u16Value);
1832 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value);
1833 IEM_MC_ADVANCE_RIP_AND_FINISH();
1834 IEM_MC_END();
1835 break;
1836
1837 case IEMMODE_32BIT:
1838 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0);
1839 IEM_MC_LOCAL(uint32_t, u32Value);
1840 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
1841 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1842 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1843 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm));
1844 IEM_MC_BSWAP_LOCAL_U32(u32Value);
1845 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value);
1846 IEM_MC_ADVANCE_RIP_AND_FINISH();
1847 IEM_MC_END();
1848 break;
1849
1850 case IEMMODE_64BIT:
1851 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1852 IEM_MC_LOCAL(uint64_t, u64Value);
1853 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
1854 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1855 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1856 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm));
1857 IEM_MC_BSWAP_LOCAL_U64(u64Value);
1858 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value);
1859 IEM_MC_ADVANCE_RIP_AND_FINISH();
1860 IEM_MC_END();
1861 break;
1862
1863 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1864 }
1865 }
1866 else
1867 {
1868 /* Reg/reg not supported. */
1869 IEMOP_RAISE_INVALID_OPCODE_RET();
1870 }
1871}
1872
1873
1874/* Opcode 0xf3 0x0f 0x38 0xf1 - invalid. */
1875
1876
1877/** Opcode 0xf2 0x0f 0x38 0xf1. */
1878FNIEMOP_DEF(iemOp_crc32_Gv_Ev)
1879{
1880 IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Ev, DISOPTYPE_HARMLESS, 0);
1881 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1882 return iemOp_InvalidNeedRM(pVCpu);
1883
1884 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1885 if (IEM_IS_MODRM_REG_MODE(bRm))
1886 {
1887 /*
1888 * Register, register.
1889 */
1890 switch (pVCpu->iem.s.enmEffOpSize)
1891 {
1892 case IEMMODE_16BIT:
1893 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1894 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1895 IEM_MC_ARG(uint32_t *, puDst, 0);
1896 IEM_MC_ARG(uint16_t, uSrc, 1);
1897 IEM_MC_FETCH_GREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1898 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1899 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1900 puDst, uSrc);
1901 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1902 IEM_MC_ADVANCE_RIP_AND_FINISH();
1903 IEM_MC_END();
1904 break;
1905
1906 case IEMMODE_32BIT:
1907 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0);
1908 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1909 IEM_MC_ARG(uint32_t *, puDst, 0);
1910 IEM_MC_ARG(uint32_t, uSrc, 1);
1911 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1912 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1913 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1914 puDst, uSrc);
1915 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1916 IEM_MC_ADVANCE_RIP_AND_FINISH();
1917 IEM_MC_END();
1918 break;
1919
1920 case IEMMODE_64BIT:
1921 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1922 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1923 IEM_MC_ARG(uint32_t *, puDst, 0);
1924 IEM_MC_ARG(uint64_t, uSrc, 1);
1925 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1926 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1927 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1928 puDst, uSrc);
1929 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1930 IEM_MC_ADVANCE_RIP_AND_FINISH();
1931 IEM_MC_END();
1932 break;
1933
1934 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1935 }
1936 }
1937 else
1938 {
1939 /*
1940 * Register, memory.
1941 */
1942 switch (pVCpu->iem.s.enmEffOpSize)
1943 {
1944 case IEMMODE_16BIT:
1945 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1946 IEM_MC_ARG(uint32_t *, puDst, 0);
1947 IEM_MC_ARG(uint16_t, uSrc, 1);
1948 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1949
1950 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1951 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1952 IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1953
1954 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1955 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1956 puDst, uSrc);
1957 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1958
1959 IEM_MC_ADVANCE_RIP_AND_FINISH();
1960 IEM_MC_END();
1961 break;
1962
1963 case IEMMODE_32BIT:
1964 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0);
1965 IEM_MC_ARG(uint32_t *, puDst, 0);
1966 IEM_MC_ARG(uint32_t, uSrc, 1);
1967 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1968
1969 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1970 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1971 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1972
1973 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1974 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1975 puDst, uSrc);
1976 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1977
1978 IEM_MC_ADVANCE_RIP_AND_FINISH();
1979 IEM_MC_END();
1980 break;
1981
1982 case IEMMODE_64BIT:
1983 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1984 IEM_MC_ARG(uint32_t *, puDst, 0);
1985 IEM_MC_ARG(uint64_t, uSrc, 1);
1986 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1987
1988 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1989 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1990 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1991
1992 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1993 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1994 puDst, uSrc);
1995 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1996
1997 IEM_MC_ADVANCE_RIP_AND_FINISH();
1998 IEM_MC_END();
1999 break;
2000
2001 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2002 }
2003 }
2004}
2005
2006
2007/* Opcode 0x0f 0x38 0xf2 - invalid (vex only). */
2008/* Opcode 0x66 0x0f 0x38 0xf2 - invalid. */
2009/* Opcode 0xf3 0x0f 0x38 0xf2 - invalid. */
2010/* Opcode 0xf2 0x0f 0x38 0xf2 - invalid. */
2011
2012/* Opcode 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
2013/* Opcode 0x66 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
2014/* Opcode 0xf3 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
2015/* Opcode 0xf2 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
2016
2017/* Opcode 0x0f 0x38 0xf4 - invalid. */
2018/* Opcode 0x66 0x0f 0x38 0xf4 - invalid. */
2019/* Opcode 0xf3 0x0f 0x38 0xf4 - invalid. */
2020/* Opcode 0xf2 0x0f 0x38 0xf4 - invalid. */
2021
2022/* Opcode 0x0f 0x38 0xf5 - invalid (vex only). */
2023/* Opcode 0x66 0x0f 0x38 0xf5 - invalid. */
2024/* Opcode 0xf3 0x0f 0x38 0xf5 - invalid (vex only). */
2025/* Opcode 0xf2 0x0f 0x38 0xf5 - invalid (vex only). */
2026
2027/* Opcode 0x0f 0x38 0xf6 - invalid. */
2028
2029#define ADX_EMIT(a_Variant) \
2030 do \
2031 { \
2032 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdx) \
2033 return iemOp_InvalidNeedRM(pVCpu); \
2034 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2035 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2036 { \
2037 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2038 { \
2039 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2040 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
2041 IEM_MC_ARG(uint64_t, u64Src, 2); \
2042 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2043 IEM_MC_ARG(uint64_t *, pu64Dst, 1); \
2044 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2045 IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
2046 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, \
2047 IEM_SELECT_HOST_OR_FALLBACK(fAdx, iemAImpl_## a_Variant ##_u64, iemAImpl_## a_Variant ##_u64_fallback), \
2048 fEFlagsIn, pu64Dst, u64Src); \
2049 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
2050 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2051 IEM_MC_END(); \
2052 } \
2053 else \
2054 { \
2055 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2056 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2057 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
2058 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
2059 \
2060 IEM_MC_ARG(uint64_t, u64Src, 2); \
2061 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2062 IEM_MC_ARG(uint64_t *, pu64Dst, 1); \
2063 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2064 IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
2065 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, \
2066 IEM_SELECT_HOST_OR_FALLBACK(fAdx, iemAImpl_## a_Variant ##_u64, iemAImpl_## a_Variant ##_u64_fallback), \
2067 fEFlagsIn, pu64Dst, u64Src); \
2068 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
2069 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2070 IEM_MC_END(); \
2071 } \
2072 } \
2073 else \
2074 { \
2075 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2076 { \
2077 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2078 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
2079 IEM_MC_ARG(uint32_t, u32Src, 2); \
2080 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2081 IEM_MC_ARG(uint32_t *, pu32Dst, 1); \
2082 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2083 IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
2084 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, \
2085 IEM_SELECT_HOST_OR_FALLBACK(fAdx, iemAImpl_## a_Variant ##_u32, iemAImpl_## a_Variant ##_u32_fallback), \
2086 fEFlagsIn, pu32Dst, u32Src); \
2087 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
2088 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2089 IEM_MC_END(); \
2090 } \
2091 else \
2092 { \
2093 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2094 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2095 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
2096 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
2097 \
2098 IEM_MC_ARG(uint32_t, u32Src, 2); \
2099 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2100 IEM_MC_ARG(uint32_t *, pu32Dst, 1); \
2101 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2102 IEM_MC_ARG_EFLAGS( fEFlagsIn, 0); \
2103 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, \
2104 IEM_SELECT_HOST_OR_FALLBACK(fAdx, iemAImpl_## a_Variant ##_u32, iemAImpl_## a_Variant ##_u32_fallback), \
2105 fEFlagsIn, pu32Dst, u32Src); \
2106 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
2107 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2108 IEM_MC_END(); \
2109 } \
2110 } \
2111 } while(0)
2112
2113
2114/**
2115 * @opcode 0xf6
2116 * @oppfx 0x66
2117 * @opfltest cf
2118 * @opflmodify cf
2119 */
2120FNIEMOP_DEF(iemOp_adcx_Gy_Ey)
2121{
2122 IEMOP_MNEMONIC2(RM, ADCX, adcx, Gy, Ey, DISOPTYPE_HARMLESS, 0);
2123 ADX_EMIT(adcx);
2124}
2125
2126
2127/**
2128 * @opcode 0xf6
2129 * @oppfx 0xf3
2130 * @opfltest of
2131 * @opflmodify of
2132 */
2133FNIEMOP_DEF(iemOp_adox_Gy_Ey)
2134{
2135 IEMOP_MNEMONIC2(RM, ADOX, adox, Gy, Ey, DISOPTYPE_HARMLESS, 0);
2136 ADX_EMIT(adox);
2137}
2138
2139
2140/* Opcode 0xf2 0x0f 0x38 0xf6 - invalid (vex only). */
2141
2142/* Opcode 0x0f 0x38 0xf7 - invalid (vex only). */
2143/* Opcode 0x66 0x0f 0x38 0xf7 - invalid (vex only). */
2144/* Opcode 0xf3 0x0f 0x38 0xf7 - invalid (vex only). */
2145/* Opcode 0xf2 0x0f 0x38 0xf7 - invalid (vex only). */
2146
2147/* Opcode 0x0f 0x38 0xf8 - invalid. */
2148/* Opcode 0x66 0x0f 0x38 0xf8 - invalid. */
2149/* Opcode 0xf3 0x0f 0x38 0xf8 - invalid. */
2150/* Opcode 0xf2 0x0f 0x38 0xf8 - invalid. */
2151
2152/* Opcode 0x0f 0x38 0xf9 - invalid. */
2153/* Opcode 0x66 0x0f 0x38 0xf9 - invalid. */
2154/* Opcode 0xf3 0x0f 0x38 0xf9 - invalid. */
2155/* Opcode 0xf2 0x0f 0x38 0xf9 - invalid. */
2156
2157/* Opcode 0x0f 0x38 0xfa - invalid. */
2158/* Opcode 0x66 0x0f 0x38 0xfa - invalid. */
2159/* Opcode 0xf3 0x0f 0x38 0xfa - invalid. */
2160/* Opcode 0xf2 0x0f 0x38 0xfa - invalid. */
2161
2162/* Opcode 0x0f 0x38 0xfb - invalid. */
2163/* Opcode 0x66 0x0f 0x38 0xfb - invalid. */
2164/* Opcode 0xf3 0x0f 0x38 0xfb - invalid. */
2165/* Opcode 0xf2 0x0f 0x38 0xfb - invalid. */
2166
2167/* Opcode 0x0f 0x38 0xfc - invalid. */
2168/* Opcode 0x66 0x0f 0x38 0xfc - invalid. */
2169/* Opcode 0xf3 0x0f 0x38 0xfc - invalid. */
2170/* Opcode 0xf2 0x0f 0x38 0xfc - invalid. */
2171
2172/* Opcode 0x0f 0x38 0xfd - invalid. */
2173/* Opcode 0x66 0x0f 0x38 0xfd - invalid. */
2174/* Opcode 0xf3 0x0f 0x38 0xfd - invalid. */
2175/* Opcode 0xf2 0x0f 0x38 0xfd - invalid. */
2176
2177/* Opcode 0x0f 0x38 0xfe - invalid. */
2178/* Opcode 0x66 0x0f 0x38 0xfe - invalid. */
2179/* Opcode 0xf3 0x0f 0x38 0xfe - invalid. */
2180/* Opcode 0xf2 0x0f 0x38 0xfe - invalid. */
2181
2182/* Opcode 0x0f 0x38 0xff - invalid. */
2183/* Opcode 0x66 0x0f 0x38 0xff - invalid. */
2184/* Opcode 0xf3 0x0f 0x38 0xff - invalid. */
2185/* Opcode 0xf2 0x0f 0x38 0xff - invalid. */
2186
2187
2188/**
2189 * Three byte opcode map, first two bytes are 0x0f 0x38.
2190 * @sa g_apfnVexMap2
2191 */
2192const PFNIEMOP g_apfnThreeByte0f38[] =
2193{
2194 /* no prefix, 066h prefix f3h prefix, f2h prefix */
2195 /* 0x00 */ iemOp_pshufb_Pq_Qq, iemOp_pshufb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2196 /* 0x01 */ iemOp_phaddw_Pq_Qq, iemOp_phaddw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2197 /* 0x02 */ iemOp_phaddd_Pq_Qq, iemOp_phaddd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2198 /* 0x03 */ iemOp_phaddsw_Pq_Qq, iemOp_phaddsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2199 /* 0x04 */ iemOp_pmaddubsw_Pq_Qq, iemOp_pmaddubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2200 /* 0x05 */ iemOp_phsubw_Pq_Qq, iemOp_phsubw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2201 /* 0x06 */ iemOp_phsubd_Pq_Qq, iemOp_phsubd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2202 /* 0x07 */ iemOp_phsubsw_Pq_Qq, iemOp_phsubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2203 /* 0x08 */ iemOp_psignb_Pq_Qq, iemOp_psignb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2204 /* 0x09 */ iemOp_psignw_Pq_Qq, iemOp_psignw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2205 /* 0x0a */ iemOp_psignd_Pq_Qq, iemOp_psignd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2206 /* 0x0b */ iemOp_pmulhrsw_Pq_Qq, iemOp_pmulhrsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2207 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
2208 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
2209 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
2210 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
2211
2212 /* 0x10 */ iemOp_InvalidNeedRM, iemOp_pblendvb_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2213 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
2214 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
2215 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
2216 /* 0x14 */ iemOp_InvalidNeedRM, iemOp_blendvps_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2217 /* 0x15 */ iemOp_InvalidNeedRM, iemOp_blendvpd_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2218 /* 0x16 */ IEMOP_X4(iemOp_InvalidNeedRM),
2219 /* 0x17 */ iemOp_InvalidNeedRM, iemOp_ptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2220 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
2221 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
2222 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
2223 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
2224 /* 0x1c */ iemOp_pabsb_Pq_Qq, iemOp_pabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2225 /* 0x1d */ iemOp_pabsw_Pq_Qq, iemOp_pabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2226 /* 0x1e */ iemOp_pabsd_Pq_Qq, iemOp_pabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2227 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
2228
2229 /* 0x20 */ iemOp_InvalidNeedRM, iemOp_pmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2230 /* 0x21 */ iemOp_InvalidNeedRM, iemOp_pmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2231 /* 0x22 */ iemOp_InvalidNeedRM, iemOp_pmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2232 /* 0x23 */ iemOp_InvalidNeedRM, iemOp_pmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2233 /* 0x24 */ iemOp_InvalidNeedRM, iemOp_pmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2234 /* 0x25 */ iemOp_InvalidNeedRM, iemOp_pmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2235 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
2236 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
2237 /* 0x28 */ iemOp_InvalidNeedRM, iemOp_pmuldq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2238 /* 0x29 */ iemOp_InvalidNeedRM, iemOp_pcmpeqq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2239 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_movntdqa_Vdq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2240 /* 0x2b */ iemOp_InvalidNeedRM, iemOp_packusdw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2241 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRM),
2242 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRM),
2243 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRM),
2244 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRM),
2245
2246 /* 0x30 */ iemOp_InvalidNeedRM, iemOp_pmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2247 /* 0x31 */ iemOp_InvalidNeedRM, iemOp_pmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2248 /* 0x32 */ iemOp_InvalidNeedRM, iemOp_pmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2249 /* 0x33 */ iemOp_InvalidNeedRM, iemOp_pmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2250 /* 0x34 */ iemOp_InvalidNeedRM, iemOp_pmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2251 /* 0x35 */ iemOp_InvalidNeedRM, iemOp_pmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2252 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
2253 /* 0x37 */ iemOp_InvalidNeedRM, iemOp_pcmpgtq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2254 /* 0x38 */ iemOp_InvalidNeedRM, iemOp_pminsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2255 /* 0x39 */ iemOp_InvalidNeedRM, iemOp_pminsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2256 /* 0x3a */ iemOp_InvalidNeedRM, iemOp_pminuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2257 /* 0x3b */ iemOp_InvalidNeedRM, iemOp_pminud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2258 /* 0x3c */ iemOp_InvalidNeedRM, iemOp_pmaxsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2259 /* 0x3d */ iemOp_InvalidNeedRM, iemOp_pmaxsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2260 /* 0x3e */ iemOp_InvalidNeedRM, iemOp_pmaxuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2261 /* 0x3f */ iemOp_InvalidNeedRM, iemOp_pmaxud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2262
2263 /* 0x40 */ iemOp_InvalidNeedRM, iemOp_pmulld_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2264 /* 0x41 */ iemOp_InvalidNeedRM, iemOp_phminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2265 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
2266 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
2267 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
2268 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
2269 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
2270 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
2271 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
2272 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
2273 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
2274 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
2275 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
2276 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
2277 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
2278 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
2279
2280 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
2281 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
2282 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
2283 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
2284 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
2285 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
2286 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
2287 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
2288 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRM),
2289 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRM),
2290 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRM),
2291 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
2292 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
2293 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
2294 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
2295 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
2296
2297 /* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
2298 /* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
2299 /* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
2300 /* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
2301 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
2302 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
2303 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
2304 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
2305 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
2306 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
2307 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
2308 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
2309 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
2310 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
2311 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
2312 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
2313
2314 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
2315 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
2316 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
2317 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
2318 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
2319 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
2320 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
2321 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
2322 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
2323 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
2324 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
2325 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
2326 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
2327 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
2328 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
2329 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
2330
2331 /* 0x80 */ iemOp_InvalidNeedRM, iemOp_invept_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2332 /* 0x81 */ iemOp_InvalidNeedRM, iemOp_invvpid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2333 /* 0x82 */ iemOp_InvalidNeedRM, iemOp_invpcid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2334 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
2335 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
2336 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
2337 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
2338 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
2339 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
2340 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
2341 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
2342 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
2343 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
2344 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
2345 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
2346 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
2347
2348 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
2349 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
2350 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
2351 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
2352 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
2353 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
2354 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
2355 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
2356 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
2357 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
2358 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
2359 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
2360 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
2361 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
2362 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
2363 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
2364
2365 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2366 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2367 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2368 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2369 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2370 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2371 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2372 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2373 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2374 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2375 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
2376 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
2377 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
2378 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
2379 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRM),
2380 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
2381
2382 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2383 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2384 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2385 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2386 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2387 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2388 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2389 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2390 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2391 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2392 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
2393 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
2394 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
2395 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
2396 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
2397 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
2398
2399 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2400 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2401 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2402 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2403 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2404 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2405 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2406 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2407 /* 0xc8 */ iemOp_sha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2408 /* 0xc9 */ iemOp_sha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2409 /* 0xca */ iemOp_sha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2410 /* 0xcb */ iemOp_sha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2411 /* 0xcc */ iemOp_sha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2412 /* 0xcd */ iemOp_sha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2413 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
2414 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
2415
2416 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2417 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2418 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2419 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2420 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2421 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2422 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2423 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2424 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2425 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2426 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
2427 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_aesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2428 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_aesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2429 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_aesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2430 /* 0xde */ iemOp_InvalidNeedRM, iemOp_aesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2431 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_aesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2432
2433 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2434 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2435 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2436 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2437 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2438 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2439 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2440 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2441 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2442 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2443 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
2444 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
2445 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
2446 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
2447 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
2448 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
2449
2450 /* 0xf0 */ iemOp_movbe_Gv_Mv, iemOp_movbe_Gv_Mv, iemOp_InvalidNeedRM, iemOp_crc32_Gd_Eb,
2451 /* 0xf1 */ iemOp_movbe_Mv_Gv, iemOp_movbe_Mv_Gv, iemOp_InvalidNeedRM, iemOp_crc32_Gv_Ev,
2452 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2453 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2454 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2455 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2456 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_adcx_Gy_Ey, iemOp_adox_Gy_Ey, iemOp_InvalidNeedRM,
2457 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2458 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2459 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2460 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
2461 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
2462 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
2463 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
2464 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
2465 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
2466};
2467AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f38) == 1024);
2468
2469/** @} */
2470
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