VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 99196

Last change on this file since 99196 was 99164, checked in by vboxsync, 2 years ago

VMM/IEM: Nested VMX: bugref:10318 Fixed vmlaunch/vmresume emulation to save/restore non-zero secondary processor-based execution VM-controls when the 'activate secondary controls' bit is not set.
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1/* $Id: IEMAllCImplVmxInstr.cpp 99164 2023-03-24 06:20:40Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM_VMX
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/dbgf.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/gim.h>
40#include <VBox/vmm/hm.h>
41#include <VBox/vmm/pgm.h>
42#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
43# include <VBox/vmm/hmvmxinline.h>
44#endif
45#include <VBox/vmm/tm.h>
46#include "IEMInternal.h"
47#include <VBox/vmm/vmcc.h>
48#include <VBox/log.h>
49#include <VBox/err.h>
50#include <VBox/param.h>
51#include <VBox/disopcode.h>
52#include <iprt/asm-math.h>
53#include <iprt/assert.h>
54#include <iprt/string.h>
55#include <iprt/x86.h>
56
57#include "IEMInline.h"
58
59
60/*********************************************************************************************************************************
61* Defined Constants And Macros *
62*********************************************************************************************************************************/
63#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
64/**
65 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
66 * relative offsets.
67 */
68# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
69# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
70# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
71# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
77# if 0
78# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
79# endif
80# else /* !IEM_WITH_CODE_TLB */
81# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
82 do \
83 { \
84 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
86 } while (0)
87
88# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
89
90# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
91 do \
92 { \
93 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
94 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
95 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
96 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
97 } while (0)
98
99# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
100 do \
101 { \
102 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
103 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
104 } while (0)
105
106# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
107 do \
108 { \
109 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
110 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
111 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
112 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
113 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
114 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
115 } while (0)
116
117# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
118 do \
119 { \
120 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
121 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
122 } while (0)
123
124# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
125 do \
126 { \
127 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
128 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
129 } while (0)
130
131# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
132 do \
133 { \
134 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
135 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
136 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
137 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
138 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
139 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
140 } while (0)
141# endif /* !IEM_WITH_CODE_TLB */
142
143/** Check for VMX instructions requiring to be in VMX operation.
144 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
145# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
146 do \
147 { \
148 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
149 { /* likely */ } \
150 else \
151 { \
152 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
153 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
154 return iemRaiseUndefinedOpcode(a_pVCpu); \
155 } \
156 } while (0)
157
158/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
159# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
160 do \
161 { \
162 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
163 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
164 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
165 return VERR_VMX_VMENTRY_FAILED; \
166 } while (0)
167
168/** Marks a VM-exit failure with a diagnostic reason and logs. */
169# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
170 do \
171 { \
172 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
173 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
174 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
175 } while (0)
176
177/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
178# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
179 do \
180 { \
181 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
182 return VERR_VMX_VMEXIT_FAILED; \
183 } while (0)
184
185
186/*********************************************************************************************************************************
187* Global Variables *
188*********************************************************************************************************************************/
189/** @todo NSTVMX: The following VM-exit intercepts are pending:
190 * VMX_EXIT_IO_SMI
191 * VMX_EXIT_SMI
192 * VMX_EXIT_GETSEC
193 * VMX_EXIT_RSM
194 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
195 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
196 * VMX_EXIT_RDRAND
197 * VMX_EXIT_VMFUNC
198 * VMX_EXIT_ENCLS
199 * VMX_EXIT_RDSEED
200 * VMX_EXIT_PML_FULL
201 * VMX_EXIT_XSAVES
202 * VMX_EXIT_XRSTORS
203 */
204/**
205 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
206 *
207 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
208 * second dimension is the Index, see VMXVMCSFIELD.
209 */
210uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
211{
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u16HlatPrefixSize),
218 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
219 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
220 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
221 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
222 },
223 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
224 {
225 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
227 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
230 },
231 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
232 {
233 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
234 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
235 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
236 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
237 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
238 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
239 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
240 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
241 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
242 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
243 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 34 */ UINT16_MAX
247 },
248 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
249 {
250 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
251 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
252 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
253 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
254 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
255 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
256 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
257 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
258 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
259 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
260 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
261 },
262 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
263 {
264 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
265 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
266 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
267 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
268 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
269 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
270 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
271 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
272 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
273 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
274 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
275 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
276 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
277 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
278 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
279 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
280 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
281 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
282 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
283 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
284 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
285 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
286 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
287 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
288 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
289 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
290 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
291 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap),
292 /* 28 */ UINT16_MAX,
293 /* 29 */ UINT16_MAX,
294 /* 30 */ UINT16_MAX,
295 /* 31 */ RT_UOFFSETOF(VMXVVMCS, u64PconfigExitBitmap),
296 /* 32 */ RT_UOFFSETOF(VMXVVMCS, u64HlatPtr),
297 /* 33 */ UINT16_MAX,
298 /* 34 */ RT_UOFFSETOF(VMXVVMCS, u64ExitCtls2)
299 },
300 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
301 {
302 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
303 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
304 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 33-34*/ UINT16_MAX, UINT16_MAX
308 },
309 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
322 /* 11 */ UINT16_MAX,
323 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
324 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
325 /* 21-28 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
326 /* 29-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
327 },
328 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
329 {
330 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
331 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
332 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
333 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
334 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
337 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
338 },
339 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
340 {
341 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
342 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
343 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
344 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
345 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
346 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
347 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
348 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
349 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
350 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
351 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
352 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
353 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
354 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
355 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
356 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
357 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
358 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
359 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
360 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
361 /* 34 */ UINT16_MAX
362 },
363 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
364 {
365 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
366 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
367 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
368 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
369 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
370 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
371 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
372 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
373 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
374 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
375 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
376 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
377 },
378 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
379 {
380 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
381 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
382 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
383 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
384 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
385 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
386 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
387 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
388 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
389 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
390 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
391 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
392 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
393 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
394 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
395 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
396 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
397 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
398 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
399 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
400 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
401 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
402 /* 22 */ UINT16_MAX,
403 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
404 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
410 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
411 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
412 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
413 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
414 /* 33-34 */ UINT16_MAX, UINT16_MAX
415 },
416 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
417 {
418 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
419 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
420 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
421 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
422 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
423 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
424 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
425 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
426 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
429 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
430 },
431 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
432 {
433 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
434 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
435 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
436 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
437 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
438 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
439 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
440 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
441 /* 22-29 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
442 /* 30-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
443 },
444 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
445 {
446 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
447 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
448 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
449 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
450 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
451 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
452 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
453 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
454 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
455 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
456 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
457 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
458 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
459 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
460 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
461 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
462 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
463 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
464 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
465 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
466 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
467 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
468 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
469 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
470 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
471 },
472 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
473 {
474 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
475 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
476 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
477 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
478 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
479 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
480 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
481 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
482 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
483 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
484 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
485 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
486 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
487 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
488 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
489 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
490 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
491 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
492 }
493};
494
495
496/**
497 * Gets a host selector from the VMCS.
498 *
499 * @param pVmcs Pointer to the virtual VMCS.
500 * @param iSelReg The index of the segment register (X86_SREG_XXX).
501 */
502DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
503{
504 Assert(iSegReg < X86_SREG_COUNT);
505 RTSEL HostSel;
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 HostSel = *(uint16_t *)pbField;
515 return HostSel;
516}
517
518
519/**
520 * Sets a guest segment register in the VMCS.
521 *
522 * @param pVmcs Pointer to the virtual VMCS.
523 * @param iSegReg The index of the segment register (X86_SREG_XXX).
524 * @param pSelReg Pointer to the segment register.
525 */
526static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
527{
528 Assert(pSelReg);
529 Assert(iSegReg < X86_SREG_COUNT);
530
531 /* Selector. */
532 {
533 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
534 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
535 uint8_t const uWidthType = (uWidth << 2) | uType;
536 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
537 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
538 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
539 uint8_t *pbVmcs = (uint8_t *)pVmcs;
540 uint8_t *pbField = pbVmcs + offField;
541 *(uint16_t *)pbField = pSelReg->Sel;
542 }
543
544 /* Limit. */
545 {
546 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
547 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
548 uint8_t const uWidthType = (uWidth << 2) | uType;
549 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
550 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
551 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
552 uint8_t *pbVmcs = (uint8_t *)pVmcs;
553 uint8_t *pbField = pbVmcs + offField;
554 *(uint32_t *)pbField = pSelReg->u32Limit;
555 }
556
557 /* Base. */
558 {
559 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
560 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
561 uint8_t const uWidthType = (uWidth << 2) | uType;
562 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
563 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
564 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
565 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
566 uint8_t const *pbField = pbVmcs + offField;
567 *(uint64_t *)pbField = pSelReg->u64Base;
568 }
569
570 /* Attributes. */
571 {
572 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
573 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
574 | X86DESCATTR_UNUSABLE;
575 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
576 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
577 uint8_t const uWidthType = (uWidth << 2) | uType;
578 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
579 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
580 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
581 uint8_t *pbVmcs = (uint8_t *)pVmcs;
582 uint8_t *pbField = pbVmcs + offField;
583 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
584 }
585}
586
587
588/**
589 * Gets a guest segment register from the VMCS.
590 *
591 * @returns VBox status code.
592 * @param pVmcs Pointer to the virtual VMCS.
593 * @param iSegReg The index of the segment register (X86_SREG_XXX).
594 * @param pSelReg Where to store the segment register (only updated when
595 * VINF_SUCCESS is returned).
596 *
597 * @remarks Warning! This does not validate the contents of the retrieved segment
598 * register.
599 */
600static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
601{
602 Assert(pSelReg);
603 Assert(iSegReg < X86_SREG_COUNT);
604
605 /* Selector. */
606 uint16_t u16Sel;
607 {
608 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
609 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
610 uint8_t const uWidthType = (uWidth << 2) | uType;
611 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
612 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
613 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
614 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
615 uint8_t const *pbField = pbVmcs + offField;
616 u16Sel = *(uint16_t *)pbField;
617 }
618
619 /* Limit. */
620 uint32_t u32Limit;
621 {
622 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
623 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
624 uint8_t const uWidthType = (uWidth << 2) | uType;
625 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
626 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
627 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
628 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
629 uint8_t const *pbField = pbVmcs + offField;
630 u32Limit = *(uint32_t *)pbField;
631 }
632
633 /* Base. */
634 uint64_t u64Base;
635 {
636 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
637 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
638 uint8_t const uWidthType = (uWidth << 2) | uType;
639 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
640 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
641 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
642 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
643 uint8_t const *pbField = pbVmcs + offField;
644 u64Base = *(uint64_t *)pbField;
645 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
646 }
647
648 /* Attributes. */
649 uint32_t u32Attr;
650 {
651 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
652 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
653 uint8_t const uWidthType = (uWidth << 2) | uType;
654 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
655 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
656 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
657 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
658 uint8_t const *pbField = pbVmcs + offField;
659 u32Attr = *(uint32_t *)pbField;
660 }
661
662 pSelReg->Sel = u16Sel;
663 pSelReg->ValidSel = u16Sel;
664 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
665 pSelReg->u32Limit = u32Limit;
666 pSelReg->u64Base = u64Base;
667 pSelReg->Attr.u = u32Attr;
668 return VINF_SUCCESS;
669}
670
671
672/**
673 * Converts an IEM exception event type to a VMX event type.
674 *
675 * @returns The VMX event type.
676 * @param uVector The interrupt / exception vector.
677 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
678 */
679DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
680{
681 /* Paranoia (callers may use these interchangeably). */
682 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
683 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
684 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
685 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
686 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
687 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
688 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
689 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
690 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
691 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
692 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
693 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
694
695 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
696 {
697 if (uVector == X86_XCPT_NMI)
698 return VMX_EXIT_INT_INFO_TYPE_NMI;
699 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
700 }
701
702 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
703 {
704 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
705 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
706 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
707 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
708 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
709 }
710
711 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
712 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
713}
714
715
716/**
717 * Determines whether the guest is using PAE paging given the VMCS.
718 *
719 * @returns @c true if PAE paging mode is used, @c false otherwise.
720 * @param pVmcs Pointer to the virtual VMCS.
721 *
722 * @warning Only use this prior to switching the guest-CPU state with the
723 * nested-guest CPU state!
724 */
725DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
726{
727 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
728 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
729 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
730}
731
732
733/**
734 * Sets the Exit qualification VMCS field.
735 *
736 * @param pVCpu The cross context virtual CPU structure.
737 * @param u64ExitQual The Exit qualification.
738 */
739DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
740{
741 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
742}
743
744
745/**
746 * Sets the VM-exit interruption information field.
747 *
748 * @param pVCpu The cross context virtual CPU structure.
749 * @param uExitIntInfo The VM-exit interruption information.
750 */
751DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
752{
753 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
754}
755
756
757/**
758 * Sets the VM-exit interruption error code.
759 *
760 * @param pVCpu The cross context virtual CPU structure.
761 * @param uErrCode The error code.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
764{
765 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
766}
767
768
769/**
770 * Sets the IDT-vectoring information field.
771 *
772 * @param pVCpu The cross context virtual CPU structure.
773 * @param uIdtVectorInfo The IDT-vectoring information.
774 */
775DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
776{
777 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
778}
779
780
781/**
782 * Sets the IDT-vectoring error code field.
783 *
784 * @param pVCpu The cross context virtual CPU structure.
785 * @param uErrCode The error code.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
788{
789 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
790}
791
792
793/**
794 * Sets the VM-exit guest-linear address VMCS field.
795 *
796 * @param pVCpu The cross context virtual CPU structure.
797 * @param uGuestLinearAddr The VM-exit guest-linear address.
798 */
799DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
800{
801 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
802 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
803 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
804}
805
806
807/**
808 * Sets the VM-exit guest-physical address VMCS field.
809 *
810 * @param pVCpu The cross context virtual CPU structure.
811 * @param uGuestPhysAddr The VM-exit guest-physical address.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
814{
815 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
816}
817
818
819/**
820 * Sets the VM-exit instruction length VMCS field.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param cbInstr The VM-exit instruction length in bytes.
824 *
825 * @remarks Callers may clear this field to 0. Hence, this function does not check
826 * the validity of the instruction length.
827 */
828DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
829{
830 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
831}
832
833
834/**
835 * Sets the VM-exit instruction info. VMCS field.
836 *
837 * @param pVCpu The cross context virtual CPU structure.
838 * @param uExitInstrInfo The VM-exit instruction information.
839 */
840DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
841{
842 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
843}
844
845
846/**
847 * Sets the guest pending-debug exceptions field.
848 *
849 * @param pVCpu The cross context virtual CPU structure.
850 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
851 */
852DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
853{
854 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
855 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
856}
857
858
859/**
860 * Implements VMSucceed for VMX instruction success.
861 *
862 * @param pVCpu The cross context virtual CPU structure.
863 */
864DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
865{
866 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
867}
868
869
870/**
871 * Implements VMFailInvalid for VMX instruction failure.
872 *
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
876{
877 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
878}
879
880
881/**
882 * Implements VMFail for VMX instruction failure.
883 *
884 * @param pVCpu The cross context virtual CPU structure.
885 * @param enmInsErr The VM instruction error.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
888{
889 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
890}
891
892
893/**
894 * Checks if the given auto-load/store MSR area count is valid for the
895 * implementation.
896 *
897 * @returns @c true if it's within the valid limit, @c false otherwise.
898 * @param pVCpu The cross context virtual CPU structure.
899 * @param uMsrCount The MSR area count to check.
900 */
901DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
902{
903 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
904 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
905 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
906 if (uMsrCount <= cMaxSupportedMsrs)
907 return true;
908 return false;
909}
910
911
912/**
913 * Flushes the current VMCS contents back to guest memory.
914 *
915 * @returns VBox status code.
916 * @param pVCpu The cross context virtual CPU structure.
917 */
918DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
919{
920 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
921 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
922 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
923 return rc;
924}
925
926
927/**
928 * Populates the current VMCS contents from guest memory.
929 *
930 * @returns VBox status code.
931 * @param pVCpu The cross context virtual CPU structure.
932 */
933DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
934{
935 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
936 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
937 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
938 return rc;
939}
940
941
942/**
943 * Gets the instruction diagnostic for segment base checks during VM-entry of a
944 * nested-guest.
945 *
946 * @param iSegReg The segment index (X86_SREG_XXX).
947 */
948static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
949{
950 switch (iSegReg)
951 {
952 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
953 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
954 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
955 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
956 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
957 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
958 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
959 }
960}
961
962
963/**
964 * Gets the instruction diagnostic for segment base checks during VM-entry of a
965 * nested-guest that is in Virtual-8086 mode.
966 *
967 * @param iSegReg The segment index (X86_SREG_XXX).
968 */
969static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
970{
971 switch (iSegReg)
972 {
973 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
974 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
975 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
976 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
977 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
978 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
979 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
980 }
981}
982
983
984/**
985 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
986 * nested-guest that is in Virtual-8086 mode.
987 *
988 * @param iSegReg The segment index (X86_SREG_XXX).
989 */
990static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
991{
992 switch (iSegReg)
993 {
994 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
995 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
996 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
997 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
998 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
999 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1000 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1001 }
1002}
1003
1004
1005/**
1006 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1007 * nested-guest that is in Virtual-8086 mode.
1008 *
1009 * @param iSegReg The segment index (X86_SREG_XXX).
1010 */
1011static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
1012{
1013 switch (iSegReg)
1014 {
1015 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1016 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1017 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1018 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1019 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1020 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1021 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1022 }
1023}
1024
1025
1026/**
1027 * Gets the instruction diagnostic for segment attributes reserved bits failure
1028 * during VM-entry of a nested-guest.
1029 *
1030 * @param iSegReg The segment index (X86_SREG_XXX).
1031 */
1032static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1033{
1034 switch (iSegReg)
1035 {
1036 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1037 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1038 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1039 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1040 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1041 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1042 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1043 }
1044}
1045
1046
1047/**
1048 * Gets the instruction diagnostic for segment attributes descriptor-type
1049 * (code/segment or system) failure during VM-entry of a nested-guest.
1050 *
1051 * @param iSegReg The segment index (X86_SREG_XXX).
1052 */
1053static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1054{
1055 switch (iSegReg)
1056 {
1057 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1058 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1059 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1060 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1061 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1062 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1063 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1064 }
1065}
1066
1067
1068/**
1069 * Gets the instruction diagnostic for segment attributes descriptor-type
1070 * (code/segment or system) failure during VM-entry of a nested-guest.
1071 *
1072 * @param iSegReg The segment index (X86_SREG_XXX).
1073 */
1074static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1075{
1076 switch (iSegReg)
1077 {
1078 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1079 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1080 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1081 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1082 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1083 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1084 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1085 }
1086}
1087
1088
1089/**
1090 * Gets the instruction diagnostic for segment attribute granularity failure during
1091 * VM-entry of a nested-guest.
1092 *
1093 * @param iSegReg The segment index (X86_SREG_XXX).
1094 */
1095static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1096{
1097 switch (iSegReg)
1098 {
1099 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1100 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1101 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1102 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1103 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1104 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1105 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1106 }
1107}
1108
1109/**
1110 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1111 * VM-entry of a nested-guest.
1112 *
1113 * @param iSegReg The segment index (X86_SREG_XXX).
1114 */
1115static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1116{
1117 switch (iSegReg)
1118 {
1119 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1120 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1121 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1122 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1123 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1124 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1125 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1126 }
1127}
1128
1129
1130/**
1131 * Gets the instruction diagnostic for segment attribute type accessed failure
1132 * during VM-entry of a nested-guest.
1133 *
1134 * @param iSegReg The segment index (X86_SREG_XXX).
1135 */
1136static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1137{
1138 switch (iSegReg)
1139 {
1140 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1141 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1142 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1143 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1144 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1145 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1146 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1147 }
1148}
1149
1150
1151/**
1152 * Saves the guest control registers, debug registers and some MSRs are part of
1153 * VM-exit.
1154 *
1155 * @param pVCpu The cross context virtual CPU structure.
1156 */
1157static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1158{
1159 /*
1160 * Saves the guest control registers, debug registers and some MSRs.
1161 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1162 */
1163 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1164
1165 /* Save control registers. */
1166 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1167 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1168 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1169
1170 /* Save SYSENTER CS, ESP, EIP. */
1171 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1172 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1173 {
1174 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1175 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1176 }
1177 else
1178 {
1179 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1180 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1181 }
1182
1183 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1184 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1185 {
1186 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1187 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1188 }
1189
1190 /* Save PAT MSR. */
1191 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1192 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1193
1194 /* Save EFER MSR. */
1195 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1196 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1197
1198 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1199 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1200
1201 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1202}
1203
1204
1205/**
1206 * Saves the guest force-flags in preparation of entering the nested-guest.
1207 *
1208 * @param pVCpu The cross context virtual CPU structure.
1209 */
1210static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1211{
1212 /* We shouldn't be called multiple times during VM-entry. */
1213 Assert(pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit == 0);
1214
1215 /* MTF should not be set outside VMX non-root mode. */
1216 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1217
1218 /*
1219 * Preserve the required force-flags.
1220 *
1221 * We cache and clear force-flags that would affect the execution of the
1222 * nested-guest. Cached flags are then restored while returning to the guest
1223 * if necessary.
1224 *
1225 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1226 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1227 * instruction. Interrupt inhibition for any nested-guest instruction
1228 * is supplied by the guest-interruptibility state VMCS field and will
1229 * be set up as part of loading the guest state. Technically
1230 * blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1231 * disallow it since we can't distinguish it from blocking-by-MovSS
1232 * and no nested-hypervisor we care about uses STI immediately
1233 * followed by VMLAUNCH/VMRESUME.
1234 *
1235 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1236 * successful VM-entry (due to invalid guest-state) need to continue
1237 * blocking NMIs if it was in effect before VM-entry.
1238 *
1239 * - MTF need not be preserved as it's used only in VMX non-root mode and
1240 * is supplied through the VM-execution controls.
1241 *
1242 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1243 * we will be able to generate interrupts that may cause VM-exits for
1244 * the nested-guest.
1245 */
1246 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_INHIBIT_NMI;
1247}
1248
1249
1250/**
1251 * Restores the guest force-flags in preparation of exiting the nested-guest.
1252 *
1253 * @param pVCpu The cross context virtual CPU structure.
1254 */
1255static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1256{
1257 /** @todo r=bird: why aren't we clearing the nested guest flags first here?
1258 * If there is some other code doing that already, it would be great
1259 * to point to it here... */
1260 pVCpu->cpum.GstCtx.eflags.uBoth |= pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit;
1261 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = 0;
1262}
1263
1264
1265/**
1266 * Performs the VMX transition to/from VMX non-root mode.
1267 *
1268 * @param pVCpu The cross context virtual CPU structure.
1269*/
1270static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1271{
1272 /*
1273 * Inform PGM about paging mode changes.
1274 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1275 * see comment in iemMemPageTranslateAndCheckAccess().
1276 */
1277 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1278 true /* fForce */);
1279 if (RT_SUCCESS(rc))
1280 { /* likely */ }
1281 else
1282 return rc;
1283
1284 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1285 IEMTlbInvalidateAll(pVCpu);
1286
1287 /* Inform CPUM (recompiler), can later be removed. */
1288 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1289
1290 /* Re-initialize IEM cache/state after the drastic mode switch. */
1291 iemReInitExec(pVCpu);
1292 return rc;
1293}
1294
1295
1296/**
1297 * Calculates the current VMX-preemption timer value.
1298 *
1299 * @returns The current VMX-preemption timer value.
1300 * @param pVCpu The cross context virtual CPU structure.
1301 */
1302static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1303{
1304 /*
1305 * Assume the following:
1306 * PreemptTimerShift = 5
1307 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1308 * EntryTick = 50000 (TSC at time of VM-entry)
1309 *
1310 * CurTick Delta PreemptTimerVal
1311 * ----------------------------------
1312 * 60000 10000 2
1313 * 80000 30000 1
1314 * 90000 40000 0 -> VM-exit.
1315 *
1316 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1317 * The saved VMX-preemption timer value is calculated as follows:
1318 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1319 * E.g.:
1320 * Delta = 10000
1321 * Tmp = 10000 / (2 * 10000) = 0.5
1322 * NewPt = 2 - 0.5 = 2
1323 * Delta = 30000
1324 * Tmp = 30000 / (2 * 10000) = 1.5
1325 * NewPt = 2 - 1.5 = 1
1326 * Delta = 40000
1327 * Tmp = 40000 / 20000 = 2
1328 * NewPt = 2 - 2 = 0
1329 */
1330 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1331 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1332 if (uVmcsPreemptVal > 0)
1333 {
1334 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1335 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1336 uint64_t const uDelta = uCurTick - uEntryTick;
1337 uint32_t const uPreemptTimer = uVmcsPreemptVal
1338 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1339 return uPreemptTimer;
1340 }
1341 return 0;
1342}
1343
1344
1345/**
1346 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1347 *
1348 * @param pVCpu The cross context virtual CPU structure.
1349 */
1350static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1351{
1352 /*
1353 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1354 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1355 */
1356 /* CS, SS, ES, DS, FS, GS. */
1357 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1358 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1359 {
1360 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1361 if (!pSelReg->Attr.n.u1Unusable)
1362 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1363 else
1364 {
1365 /*
1366 * For unusable segments the attributes are undefined except for CS and SS.
1367 * For the rest we don't bother preserving anything but the unusable bit.
1368 */
1369 switch (iSegReg)
1370 {
1371 case X86_SREG_CS:
1372 pVmcs->GuestCs = pSelReg->Sel;
1373 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1374 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1375 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1376 | X86DESCATTR_UNUSABLE);
1377 break;
1378
1379 case X86_SREG_SS:
1380 pVmcs->GuestSs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1384 break;
1385
1386 case X86_SREG_DS:
1387 pVmcs->GuestDs = pSelReg->Sel;
1388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1389 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1390 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1391 break;
1392
1393 case X86_SREG_ES:
1394 pVmcs->GuestEs = pSelReg->Sel;
1395 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1396 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1397 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1398 break;
1399
1400 case X86_SREG_FS:
1401 pVmcs->GuestFs = pSelReg->Sel;
1402 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1403 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1404 break;
1405
1406 case X86_SREG_GS:
1407 pVmcs->GuestGs = pSelReg->Sel;
1408 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1409 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1410 break;
1411 }
1412 }
1413 }
1414
1415 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1416 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1417 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1418 | X86DESCATTR_UNUSABLE;
1419 /* LDTR. */
1420 {
1421 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1422 pVmcs->GuestLdtr = pSelReg->Sel;
1423 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1424 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1425 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1426 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1427 }
1428
1429 /* TR. */
1430 {
1431 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1432 pVmcs->GuestTr = pSelReg->Sel;
1433 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1434 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1435 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1436 }
1437
1438 /* GDTR. */
1439 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1440 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1441
1442 /* IDTR. */
1443 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1444 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1445}
1446
1447
1448/**
1449 * Saves guest non-register state as part of VM-exit.
1450 *
1451 * @param pVCpu The cross context virtual CPU structure.
1452 * @param uExitReason The VM-exit reason.
1453 */
1454static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1455{
1456 /*
1457 * Save guest non-register state.
1458 * See Intel spec. 27.3.4 "Saving Non-Register State".
1459 */
1460 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1461
1462 /*
1463 * Activity state.
1464 * Most VM-exits will occur in the active state. However, if the first instruction
1465 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1466 * the VM-exit will be from the HLT activity state.
1467 *
1468 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1469 */
1470 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1471 * not? */
1472 EMSTATE const enmActivityState = EMGetState(pVCpu);
1473 switch (enmActivityState)
1474 {
1475 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1476 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1477 }
1478
1479 /*
1480 * Interruptibility-state.
1481 */
1482 /* NMI. */
1483 pVmcs->u32GuestIntrState = 0;
1484 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1485 {
1486 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1487 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1488 }
1489 else
1490 {
1491 if (CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
1492 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1493 }
1494
1495 /* Blocking-by-STI. */
1496 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
1497 { /* probable */}
1498 else
1499 {
1500 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1501 * currently. */
1502 if (pVCpu->cpum.GstCtx.rip == pVCpu->cpum.GstCtx.uRipInhibitInt)
1503 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI; /** @todo r=bird: Why the STI one? MOVSS seems to block more and the one to use. */
1504
1505 /* Clear inhibition unconditionally since we've ensured it isn't set prior to executing VMLAUNCH/VMRESUME. */
1506 CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
1507 }
1508 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1509
1510 /*
1511 * Pending debug exceptions.
1512 *
1513 * For VM-exits where it is not applicable, we can safely zero out the field.
1514 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1515 */
1516 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1517 && uExitReason != VMX_EXIT_SMI
1518 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1519 && !VMXIsVmexitTrapLike(uExitReason))
1520 {
1521 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1522 * block-by-MovSS is in effect. */
1523 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1524 }
1525
1526 /*
1527 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1528 *
1529 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1530 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1531 */
1532 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1533 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1534 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1535
1536 /*
1537 * Save the guest PAE PDPTEs.
1538 */
1539 if ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1540 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
1541 {
1542 /*
1543 * Without EPT or when the nested-guest is not using PAE paging, the values saved
1544 * in the VMCS during VM-exit are undefined. We zero them here for consistency.
1545 */
1546 pVmcs->u64GuestPdpte0.u = 0;
1547 pVmcs->u64GuestPdpte1.u = 0;
1548 pVmcs->u64GuestPdpte2.u = 0;
1549 pVmcs->u64GuestPdpte3.u = 0;
1550 }
1551 else
1552 {
1553 /*
1554 * With EPT and when the nested-guest is using PAE paging, we update the PDPTEs from
1555 * the nested-guest CPU context. Both IEM (Mov CRx) and hardware-assisted execution
1556 * of the nested-guest is expected to have updated them.
1557 */
1558 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1559 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1560 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1561 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1562 }
1563
1564 /* Clear PGM's copy of the EPT pointer for added safety. */
1565 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1566 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1567}
1568
1569
1570/**
1571 * Saves the guest-state as part of VM-exit.
1572 *
1573 * @returns VBox status code.
1574 * @param pVCpu The cross context virtual CPU structure.
1575 * @param uExitReason The VM-exit reason.
1576 */
1577static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1578{
1579 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1580 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1581
1582 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1583 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1584 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1585
1586 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1587}
1588
1589
1590/**
1591 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1592 *
1593 * @returns VBox status code.
1594 * @param pVCpu The cross context virtual CPU structure.
1595 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1596 */
1597static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1598{
1599 /*
1600 * Save guest MSRs.
1601 * See Intel spec. 27.4 "Saving MSRs".
1602 */
1603 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1604 const char * const pszFailure = "VMX-abort";
1605
1606 /*
1607 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1608 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1609 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1610 */
1611 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1612 if (!cMsrs)
1613 return VINF_SUCCESS;
1614
1615 /*
1616 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1617 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1618 * implementation causes a VMX-abort followed by a triple-fault.
1619 */
1620 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1621 if (fIsMsrCountValid)
1622 { /* likely */ }
1623 else
1624 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1625
1626 /*
1627 * Optimization if the nested hypervisor is using the same guest-physical page for both
1628 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1629 */
1630 PVMXAUTOMSR pMsrArea;
1631 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1632 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1633 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1634 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1635 else
1636 {
1637 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1638 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1639 if (RT_SUCCESS(rc))
1640 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1641 else
1642 {
1643 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1644 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1645 }
1646 }
1647
1648 /*
1649 * Update VM-exit MSR store area.
1650 */
1651 PVMXAUTOMSR pMsr = pMsrArea;
1652 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1653 {
1654 if ( !pMsr->u32Reserved
1655 && pMsr->u32Msr != MSR_IA32_SMBASE
1656 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1657 {
1658 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1659 if (rcStrict == VINF_SUCCESS)
1660 continue;
1661
1662 /*
1663 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1664 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1665 * recording the MSR index in the auxiliary info. field and indicated further by our
1666 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1667 * if possible, or come up with a better, generic solution.
1668 */
1669 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1670 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1671 ? kVmxVDiag_Vmexit_MsrStoreRing3
1672 : kVmxVDiag_Vmexit_MsrStore;
1673 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1674 }
1675 else
1676 {
1677 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1678 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1679 }
1680 }
1681
1682 /*
1683 * Commit the VM-exit MSR store are to guest memory.
1684 */
1685 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1686 if (RT_SUCCESS(rc))
1687 return VINF_SUCCESS;
1688
1689 NOREF(uExitReason);
1690 NOREF(pszFailure);
1691
1692 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1693 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1694}
1695
1696
1697/**
1698 * Performs a VMX abort (due to an fatal error during VM-exit).
1699 *
1700 * @returns Strict VBox status code.
1701 * @param pVCpu The cross context virtual CPU structure.
1702 * @param enmAbort The VMX abort reason.
1703 */
1704static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1705{
1706 /*
1707 * Perform the VMX abort.
1708 * See Intel spec. 27.7 "VMX Aborts".
1709 */
1710 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1711
1712 /* We don't support SMX yet. */
1713 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1714 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1715 {
1716 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1717 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1718 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1719 }
1720
1721 return VINF_EM_TRIPLE_FAULT;
1722}
1723
1724
1725/**
1726 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1727 *
1728 * @param pVCpu The cross context virtual CPU structure.
1729 */
1730static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1731{
1732 /*
1733 * Load host control registers, debug registers and MSRs.
1734 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1735 */
1736 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1737 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1738
1739 /* CR0. */
1740 {
1741 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1742 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK;
1743 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1744 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1745 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1746
1747 /* Verify we have not modified CR0 fixed bits in VMX operation. */
1748#ifdef VBOX_STRICT
1749 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
1750 bool const fUx = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1751 AssertMsg( (uValidHostCr0 & uCr0Mb1) == uCr0Mb1
1752 && (uValidHostCr0 & ~VMX_V_CR0_FIXED1) == 0,
1753 ("host=%#RX64 guest=%#RX64 mb1=%#RX64 valid_host_cr0=%#RX64 fUx=%RTbool\n",
1754 uHostCr0, uGuestCr0, uCr0Mb1, uValidHostCr0, fUx));
1755#endif
1756 Assert(!(uValidHostCr0 >> 32));
1757 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1758 }
1759
1760 /* CR4. */
1761 {
1762 /* CR4 fixed bits are not modified. */
1763 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1764 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1765 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1766 uint64_t uValidHostCr4 = (uHostCr4 & uCr4Mb0) | uCr4Mb1;
1767 if (fHostInLongMode)
1768 uValidHostCr4 |= X86_CR4_PAE;
1769 else
1770 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1771
1772 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1773 AssertMsg( (uValidHostCr4 & uCr4Mb1) == uCr4Mb1
1774 && (uValidHostCr4 & ~uCr4Mb0) == 0,
1775 ("host=%#RX64 guest=%#RX64, uCr4Mb1=%#RX64 uCr4Mb0=%#RX64 valid_host_cr4=%#RX64\n",
1776 uHostCr4, pVCpu->cpum.GstCtx.cr4, uCr4Mb1, uCr4Mb0, uValidHostCr4));
1777 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1778 }
1779
1780 /* CR3 (host value validated while checking host-state during VM-entry). */
1781 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1782
1783 /* DR7. */
1784 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1785
1786 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1787
1788 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1789 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1790 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1791 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1792
1793 /* FS, GS bases are loaded later while we load host segment registers. */
1794
1795 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1796 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1797 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1798 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1799 {
1800 if (fHostInLongMode)
1801 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1802 else
1803 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1804 }
1805
1806 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1807
1808 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1809 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1810 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1811
1812 /* We don't support IA32_BNDCFGS MSR yet. */
1813}
1814
1815
1816/**
1817 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1818 *
1819 * @param pVCpu The cross context virtual CPU structure.
1820 */
1821static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1822{
1823 /*
1824 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1825 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1826 *
1827 * Warning! Be careful to not touch fields that are reserved by VT-x,
1828 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1829 */
1830 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1831 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1832
1833 /* CS, SS, ES, DS, FS, GS. */
1834 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1835 {
1836 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1837 bool const fUnusable = RT_BOOL(HostSel == 0);
1838 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1839
1840 /* Selector. */
1841 pSelReg->Sel = HostSel;
1842 pSelReg->ValidSel = HostSel;
1843 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1844
1845 /* Limit. */
1846 pSelReg->u32Limit = 0xffffffff;
1847
1848 /* Base. */
1849 pSelReg->u64Base = 0;
1850
1851 /* Attributes. */
1852 if (iSegReg == X86_SREG_CS)
1853 {
1854 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1855 pSelReg->Attr.n.u1DescType = 1;
1856 pSelReg->Attr.n.u2Dpl = 0;
1857 pSelReg->Attr.n.u1Present = 1;
1858 pSelReg->Attr.n.u1Long = fHostInLongMode;
1859 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1860 pSelReg->Attr.n.u1Granularity = 1;
1861 Assert(!pSelReg->Attr.n.u1Unusable);
1862 Assert(!fUnusable);
1863 }
1864 else
1865 {
1866 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1867 pSelReg->Attr.n.u1DescType = 1;
1868 pSelReg->Attr.n.u2Dpl = 0;
1869 pSelReg->Attr.n.u1Present = 1;
1870 pSelReg->Attr.n.u1DefBig = 1;
1871 pSelReg->Attr.n.u1Granularity = 1;
1872 pSelReg->Attr.n.u1Unusable = fUnusable;
1873 }
1874 }
1875
1876 /* FS base. */
1877 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1878 || fHostInLongMode)
1879 {
1880 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1881 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1882 }
1883
1884 /* GS base. */
1885 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1886 || fHostInLongMode)
1887 {
1888 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1889 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1890 }
1891
1892 /* TR. */
1893 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1894 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1895 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1896 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1897 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1898 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1899 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1900 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1901 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1902 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1903 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1904 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1905 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1906
1907 /* LDTR (Warning! do not touch the base and limits here). */
1908 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1909 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1910 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1911 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1912
1913 /* GDTR. */
1914 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1915 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1916 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1917
1918 /* IDTR.*/
1919 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1920 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1921 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1922}
1923
1924
1925/**
1926 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1927 *
1928 * @returns VBox status code.
1929 * @param pVCpu The cross context virtual CPU structure.
1930 * @param uExitReason The VMX instruction name (for logging purposes).
1931 */
1932static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1933{
1934 /*
1935 * Load host MSRs.
1936 * See Intel spec. 27.6 "Loading MSRs".
1937 */
1938 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1939 const char * const pszFailure = "VMX-abort";
1940
1941 /*
1942 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1943 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1944 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1945 */
1946 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1947 if (!cMsrs)
1948 return VINF_SUCCESS;
1949
1950 /*
1951 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1952 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1953 * implementation causes a VMX-abort followed by a triple-fault.
1954 */
1955 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1956 if (fIsMsrCountValid)
1957 { /* likely */ }
1958 else
1959 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1960
1961 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1962 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1963 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1964 if (RT_SUCCESS(rc))
1965 {
1966 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1967 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1968 {
1969 if ( !pMsr->u32Reserved
1970 && pMsr->u32Msr != MSR_K8_FS_BASE
1971 && pMsr->u32Msr != MSR_K8_GS_BASE
1972 && pMsr->u32Msr != MSR_K6_EFER
1973 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1974 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1975 {
1976 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1977 if (rcStrict == VINF_SUCCESS)
1978 continue;
1979
1980 /*
1981 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1982 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1983 * recording the MSR index in the auxiliary info. field and indicated further by our
1984 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1985 * if possible, or come up with a better, generic solution.
1986 */
1987 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1988 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1989 ? kVmxVDiag_Vmexit_MsrLoadRing3
1990 : kVmxVDiag_Vmexit_MsrLoad;
1991 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1992 }
1993 else
1994 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1995 }
1996 }
1997 else
1998 {
1999 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2000 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2001 }
2002
2003 NOREF(uExitReason);
2004 NOREF(pszFailure);
2005 return VINF_SUCCESS;
2006}
2007
2008
2009/**
2010 * Loads the host state as part of VM-exit.
2011 *
2012 * @returns Strict VBox status code.
2013 * @param pVCpu The cross context virtual CPU structure.
2014 * @param uExitReason The VM-exit reason (for logging purposes).
2015 */
2016static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
2017{
2018 /*
2019 * Load host state.
2020 * See Intel spec. 27.5 "Loading Host State".
2021 */
2022 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2023 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2024
2025 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2026 if ( CPUMIsGuestInLongMode(pVCpu)
2027 && !fHostInLongMode)
2028 {
2029 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2030 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2031 }
2032
2033 /*
2034 * Check host PAE PDPTEs prior to loading the host state.
2035 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2036 */
2037 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2038 && !fHostInLongMode
2039 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2040 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2041 {
2042 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2043 if (RT_SUCCESS(rc))
2044 { /* likely*/ }
2045 else
2046 {
2047 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2048 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2049 }
2050 }
2051
2052 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2053 iemVmxVmexitLoadHostSegRegs(pVCpu);
2054
2055 /*
2056 * Load host RIP, RSP and RFLAGS.
2057 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2058 */
2059 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2060 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2061 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2062
2063 /* Clear address range monitoring. */
2064 EMMonitorWaitClear(pVCpu);
2065
2066 /* Perform the VMX transition (PGM updates). */
2067 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2068 if (rcStrict == VINF_SUCCESS)
2069 { /* likely */ }
2070 else if (RT_SUCCESS(rcStrict))
2071 {
2072 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2073 uExitReason));
2074 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2075 }
2076 else
2077 {
2078 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2079 return VBOXSTRICTRC_VAL(rcStrict);
2080 }
2081
2082 Assert(rcStrict == VINF_SUCCESS);
2083
2084 /* Load MSRs from the VM-exit auto-load MSR area. */
2085 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2086 if (RT_FAILURE(rc))
2087 {
2088 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2089 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2090 }
2091 return VINF_SUCCESS;
2092}
2093
2094
2095/**
2096 * Gets VM-exit instruction information along with any displacement for an
2097 * instruction VM-exit.
2098 *
2099 * @returns The VM-exit instruction information.
2100 * @param pVCpu The cross context virtual CPU structure.
2101 * @param uExitReason The VM-exit reason.
2102 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2103 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2104 * NULL.
2105 */
2106static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2107{
2108 RTGCPTR GCPtrDisp;
2109 VMXEXITINSTRINFO ExitInstrInfo;
2110 ExitInstrInfo.u = 0;
2111
2112 /*
2113 * Get and parse the ModR/M byte from our decoded opcodes.
2114 */
2115 uint8_t bRm;
2116 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2117 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2118 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2119 {
2120 /*
2121 * ModR/M indicates register addressing.
2122 *
2123 * The primary/secondary register operands are reported in the iReg1 or iReg2
2124 * fields depending on whether it is a read/write form.
2125 */
2126 uint8_t idxReg1;
2127 uint8_t idxReg2;
2128 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2129 {
2130 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2131 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2132 }
2133 else
2134 {
2135 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2136 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2137 }
2138 ExitInstrInfo.All.u2Scaling = 0;
2139 ExitInstrInfo.All.iReg1 = idxReg1;
2140 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2141 ExitInstrInfo.All.fIsRegOperand = 1;
2142 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2143 ExitInstrInfo.All.iSegReg = 0;
2144 ExitInstrInfo.All.iIdxReg = 0;
2145 ExitInstrInfo.All.fIdxRegInvalid = 1;
2146 ExitInstrInfo.All.iBaseReg = 0;
2147 ExitInstrInfo.All.fBaseRegInvalid = 1;
2148 ExitInstrInfo.All.iReg2 = idxReg2;
2149
2150 /* Displacement not applicable for register addressing. */
2151 GCPtrDisp = 0;
2152 }
2153 else
2154 {
2155 /*
2156 * ModR/M indicates memory addressing.
2157 */
2158 uint8_t uScale = 0;
2159 bool fBaseRegValid = false;
2160 bool fIdxRegValid = false;
2161 uint8_t iBaseReg = 0;
2162 uint8_t iIdxReg = 0;
2163 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2164 {
2165 /*
2166 * Parse the ModR/M, displacement for 16-bit addressing mode.
2167 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2168 */
2169 uint16_t u16Disp = 0;
2170 uint8_t const offDisp = offModRm + sizeof(bRm);
2171 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2172 {
2173 /* Displacement without any registers. */
2174 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2175 }
2176 else
2177 {
2178 /* Register (index and base). */
2179 switch (bRm & X86_MODRM_RM_MASK)
2180 {
2181 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2182 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2183 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2184 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2185 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2186 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2187 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2188 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2189 }
2190
2191 /* Register + displacement. */
2192 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2193 {
2194 case 0: break;
2195 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2196 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2197 default:
2198 {
2199 /* Register addressing, handled at the beginning. */
2200 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2201 break;
2202 }
2203 }
2204 }
2205
2206 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2207 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2208 }
2209 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2210 {
2211 /*
2212 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2213 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2214 */
2215 uint32_t u32Disp = 0;
2216 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2217 {
2218 /* Displacement without any registers. */
2219 uint8_t const offDisp = offModRm + sizeof(bRm);
2220 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2221 }
2222 else
2223 {
2224 /* Register (and perhaps scale, index and base). */
2225 uint8_t offDisp = offModRm + sizeof(bRm);
2226 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2227 if (iBaseReg == 4)
2228 {
2229 /* An SIB byte follows the ModR/M byte, parse it. */
2230 uint8_t bSib;
2231 uint8_t const offSib = offModRm + sizeof(bRm);
2232 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2233
2234 /* A displacement may follow SIB, update its offset. */
2235 offDisp += sizeof(bSib);
2236
2237 /* Get the scale. */
2238 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2239
2240 /* Get the index register. */
2241 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2242 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2243
2244 /* Get the base register. */
2245 iBaseReg = bSib & X86_SIB_BASE_MASK;
2246 fBaseRegValid = true;
2247 if (iBaseReg == 5)
2248 {
2249 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2250 {
2251 /* Mod is 0 implies a 32-bit displacement with no base. */
2252 fBaseRegValid = false;
2253 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2254 }
2255 else
2256 {
2257 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2258 iBaseReg = X86_GREG_xBP;
2259 }
2260 }
2261 }
2262
2263 /* Register + displacement. */
2264 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2265 {
2266 case 0: /* Handled above */ break;
2267 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2268 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2269 default:
2270 {
2271 /* Register addressing, handled at the beginning. */
2272 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2273 break;
2274 }
2275 }
2276 }
2277
2278 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2279 }
2280 else
2281 {
2282 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2283
2284 /*
2285 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2286 * See Intel instruction spec. 2.2 "IA-32e Mode".
2287 */
2288 uint64_t u64Disp = 0;
2289 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2290 if (fRipRelativeAddr)
2291 {
2292 /*
2293 * RIP-relative addressing mode.
2294 *
2295 * The displacement is 32-bit signed implying an offset range of +/-2G.
2296 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2297 */
2298 uint8_t const offDisp = offModRm + sizeof(bRm);
2299 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2300 }
2301 else
2302 {
2303 uint8_t offDisp = offModRm + sizeof(bRm);
2304
2305 /*
2306 * Register (and perhaps scale, index and base).
2307 *
2308 * REX.B extends the most-significant bit of the base register. However, REX.B
2309 * is ignored while determining whether an SIB follows the opcode. Hence, we
2310 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2311 *
2312 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2313 */
2314 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2315 if (iBaseReg == 4)
2316 {
2317 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2318 uint8_t bSib;
2319 uint8_t const offSib = offModRm + sizeof(bRm);
2320 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2321
2322 /* Displacement may follow SIB, update its offset. */
2323 offDisp += sizeof(bSib);
2324
2325 /* Get the scale. */
2326 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2327
2328 /* Get the index. */
2329 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2330 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2331
2332 /* Get the base. */
2333 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2334 fBaseRegValid = true;
2335 if (iBaseReg == 5)
2336 {
2337 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2338 {
2339 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2340 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2341 }
2342 else
2343 {
2344 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2345 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2346 }
2347 }
2348 }
2349 iBaseReg |= pVCpu->iem.s.uRexB;
2350
2351 /* Register + displacement. */
2352 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2353 {
2354 case 0: /* Handled above */ break;
2355 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2356 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2357 default:
2358 {
2359 /* Register addressing, handled at the beginning. */
2360 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2361 break;
2362 }
2363 }
2364 }
2365
2366 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2367 }
2368
2369 /*
2370 * The primary or secondary register operand is reported in iReg2 depending
2371 * on whether the primary operand is in read/write form.
2372 */
2373 uint8_t idxReg2;
2374 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2375 {
2376 idxReg2 = bRm & X86_MODRM_RM_MASK;
2377 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2378 idxReg2 |= pVCpu->iem.s.uRexB;
2379 }
2380 else
2381 {
2382 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2383 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2384 idxReg2 |= pVCpu->iem.s.uRexReg;
2385 }
2386 ExitInstrInfo.All.u2Scaling = uScale;
2387 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2388 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2389 ExitInstrInfo.All.fIsRegOperand = 0;
2390 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2391 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2392 ExitInstrInfo.All.iIdxReg = iIdxReg;
2393 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2394 ExitInstrInfo.All.iBaseReg = iBaseReg;
2395 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2396 ExitInstrInfo.All.iReg2 = idxReg2;
2397 }
2398
2399 /*
2400 * Handle exceptions to the norm for certain instructions.
2401 * (e.g. some instructions convey an instruction identity in place of iReg2).
2402 */
2403 switch (uExitReason)
2404 {
2405 case VMX_EXIT_GDTR_IDTR_ACCESS:
2406 {
2407 Assert(VMXINSTRID_IS_VALID(uInstrId));
2408 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2409 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2410 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2411 break;
2412 }
2413
2414 case VMX_EXIT_LDTR_TR_ACCESS:
2415 {
2416 Assert(VMXINSTRID_IS_VALID(uInstrId));
2417 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2418 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2419 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2420 break;
2421 }
2422
2423 case VMX_EXIT_RDRAND:
2424 case VMX_EXIT_RDSEED:
2425 {
2426 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2427 break;
2428 }
2429 }
2430
2431 /* Update displacement and return the constructed VM-exit instruction information field. */
2432 if (pGCPtrDisp)
2433 *pGCPtrDisp = GCPtrDisp;
2434
2435 return ExitInstrInfo.u;
2436}
2437
2438
2439/**
2440 * VMX VM-exit handler.
2441 *
2442 * @returns Strict VBox status code.
2443 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2444 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2445 * triple-fault.
2446 *
2447 * @param pVCpu The cross context virtual CPU structure.
2448 * @param uExitReason The VM-exit reason.
2449 * @param u64ExitQual The Exit qualification.
2450 *
2451 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2452 * called. Failures during VM-entry can cause VM-exits as well, so we
2453 * -cannot- assert we're in VMX non-root mode here.
2454 */
2455VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2456{
2457# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2458 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2459 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2460 return VERR_IEM_IPE_7;
2461# else
2462 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2463
2464 /* Just count this as an exit and be done with that. */
2465 pVCpu->iem.s.cPotentialExits++;
2466
2467 /*
2468 * Import all the guest-CPU state.
2469 *
2470 * HM on returning to guest execution would have to reset up a whole lot of state
2471 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2472 * the state and flag reloading the entire state on re-entry. So import the entire
2473 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2474 */
2475 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2476
2477 /*
2478 * Ensure VM-entry interruption information valid bit is cleared.
2479 *
2480 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2481 * by invalid-guest state or machine-check exceptions) also clear this bit.
2482 *
2483 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2484 */
2485 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2486 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2487
2488 /*
2489 * Update the VM-exit reason and Exit qualification.
2490 * Other VMCS read-only data fields are expected to be updated by the caller already.
2491 */
2492 pVmcs->u32RoExitReason = uExitReason;
2493 pVmcs->u64RoExitQual.u = u64ExitQual;
2494
2495 Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2496 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2497 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u));
2498
2499 /*
2500 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2501 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2502 */
2503 {
2504 uint8_t uVector;
2505 uint32_t fFlags;
2506 uint32_t uErrCode;
2507 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2508 if (fInEventDelivery)
2509 {
2510 /*
2511 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2512 * caused by a triple-fault or the original event results in a double-fault that
2513 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2514 * original event information into the IDT-vectoring information fields.
2515 *
2516 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2517 */
2518 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2519 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2520 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2521 {
2522 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2523 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2524 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2525 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2526 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2527 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2528 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2529 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2530 Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2531 pVCpu->cpum.GstCtx.cr2));
2532 }
2533 }
2534 }
2535
2536 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2537 Assert(pVmcs->u64RoIoRcx.u == 0);
2538 Assert(pVmcs->u64RoIoRsi.u == 0);
2539 Assert(pVmcs->u64RoIoRdi.u == 0);
2540 Assert(pVmcs->u64RoIoRip.u == 0);
2541
2542 /*
2543 * Save the guest state back into the VMCS.
2544 * We only need to save the state when the VM-entry was successful.
2545 */
2546 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2547 if (!fVmentryFailed)
2548 {
2549 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2550 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2551 {
2552 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2553 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2554 }
2555
2556 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2557 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2558
2559 /*
2560 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2561 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2562 *
2563 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2564 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2565 * as guest-CPU state would not been modified. Hence for now, we do this only when
2566 * the VM-entry succeeded.
2567 */
2568 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2569 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2570 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2571 {
2572 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2573 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2574 else
2575 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2576 }
2577
2578 /*
2579 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2580 * occurs in enclave mode/SMM which we don't support yet.
2581 *
2582 * If we ever add support for it, we can pass just the lower bits to the functions
2583 * below, till then an assert should suffice.
2584 */
2585 Assert(!RT_HI_U16(uExitReason));
2586
2587 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2588 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2589 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2590 if (RT_SUCCESS(rc))
2591 { /* likely */ }
2592 else
2593 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2594
2595 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2596 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit &= ~CPUMCTX_INHIBIT_NMI;
2597 }
2598 else
2599 {
2600 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2601 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2602 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2603 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2604 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2605 }
2606
2607 /*
2608 * Stop any running VMX-preemption timer if necessary.
2609 */
2610 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2611 CPUMStopGuestVmxPremptTimer(pVCpu);
2612
2613 /*
2614 * Clear any pending VMX nested-guest force-flags.
2615 * These force-flags have no effect on (outer) guest execution and will
2616 * be re-evaluated and setup on the next nested-guest VM-entry.
2617 */
2618 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2619
2620 /*
2621 * We're no longer in nested-guest execution mode.
2622 *
2623 * It is important to do this prior to loading the host state because
2624 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2625 * second-level address translation while switching to host CR3.
2626 */
2627 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2628
2629 /* Restore the host (outer guest) state. */
2630 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2631 if (RT_SUCCESS(rcStrict))
2632 {
2633 Assert(rcStrict == VINF_SUCCESS);
2634 rcStrict = VINF_VMX_VMEXIT;
2635 }
2636 else
2637 Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2638
2639 /*
2640 * Restore non-zero Secondary-processor based VM-execution controls
2641 * when the "activate secondary controls" bit was not set.
2642 */
2643 if (pVmcs->u32RestoreProcCtls2)
2644 {
2645 Assert(!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS));
2646 pVmcs->u32ProcCtls2 = pVmcs->u32RestoreProcCtls2;
2647 pVmcs->u32RestoreProcCtls2 = 0;
2648 }
2649
2650 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2651 {
2652 /* Notify HM that the current VMCS fields have been modified. */
2653 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2654
2655 /* Notify HM that we've completed the VM-exit. */
2656 HMNotifyVmxNstGstVmexit(pVCpu);
2657 }
2658
2659# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2660 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2661 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2662 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2663 if (rcSched != VINF_SUCCESS)
2664 iemSetPassUpStatus(pVCpu, rcSched);
2665# endif
2666 return rcStrict;
2667# endif
2668}
2669
2670
2671/**
2672 * VMX VM-exit handler for VM-exits due to instruction execution.
2673 *
2674 * This is intended for instructions where the caller provides all the relevant
2675 * VM-exit information.
2676 *
2677 * @returns Strict VBox status code.
2678 * @param pVCpu The cross context virtual CPU structure.
2679 * @param pExitInfo Pointer to the VM-exit information.
2680 */
2681static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2682{
2683 /*
2684 * For instructions where any of the following fields are not applicable:
2685 * - Exit qualification must be cleared.
2686 * - VM-exit instruction info. is undefined.
2687 * - Guest-linear address is undefined.
2688 * - Guest-physical address is undefined.
2689 *
2690 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2691 * instruction execution. For VM-exits that are not due to instruction execution this
2692 * field is undefined.
2693 *
2694 * In our implementation in IEM, all undefined fields are generally cleared. However,
2695 * if the caller supplies information (from say the physical CPU directly) it is
2696 * then possible that the undefined fields are not cleared.
2697 *
2698 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2699 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2700 */
2701 Assert(pExitInfo);
2702 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2703 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2704 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2705
2706 /* Update all the relevant fields from the VM-exit instruction information struct. */
2707 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2708 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2709 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2710 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2711
2712 /* Perform the VM-exit. */
2713 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2714}
2715
2716
2717/**
2718 * VMX VM-exit handler for VM-exits due to instruction execution.
2719 *
2720 * This is intended for instructions that only provide the VM-exit instruction
2721 * length.
2722 *
2723 * @param pVCpu The cross context virtual CPU structure.
2724 * @param uExitReason The VM-exit reason.
2725 * @param cbInstr The instruction length in bytes.
2726 */
2727VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2728{
2729#ifdef VBOX_STRICT
2730 /*
2731 * To prevent us from shooting ourselves in the foot.
2732 * The follow instructions should convey more than just the instruction length.
2733 */
2734 switch (uExitReason)
2735 {
2736 case VMX_EXIT_INVEPT:
2737 case VMX_EXIT_INVPCID:
2738 case VMX_EXIT_INVVPID:
2739 case VMX_EXIT_LDTR_TR_ACCESS:
2740 case VMX_EXIT_GDTR_IDTR_ACCESS:
2741 case VMX_EXIT_VMCLEAR:
2742 case VMX_EXIT_VMPTRLD:
2743 case VMX_EXIT_VMPTRST:
2744 case VMX_EXIT_VMREAD:
2745 case VMX_EXIT_VMWRITE:
2746 case VMX_EXIT_VMXON:
2747 case VMX_EXIT_XRSTORS:
2748 case VMX_EXIT_XSAVES:
2749 case VMX_EXIT_RDRAND:
2750 case VMX_EXIT_RDSEED:
2751 case VMX_EXIT_IO_INSTR:
2752 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2753 break;
2754 }
2755#endif
2756
2757 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_INSTR_LEN(uExitReason, cbInstr);
2758 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2759}
2760
2761
2762/**
2763 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2764 *
2765 * @returns Strict VBox status code.
2766 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2767 * @thread EMT(pVCpu)
2768 */
2769VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2770{
2771 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2772 Assert(!pVCpu->iem.s.cActiveMappings);
2773 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2774}
2775
2776
2777/**
2778 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2779 *
2780 * @returns Strict VBox status code.
2781 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2782 * @param uVector The SIPI vector.
2783 * @thread EMT(pVCpu)
2784 */
2785VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2786{
2787 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2788 Assert(!pVCpu->iem.s.cActiveMappings);
2789 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2790}
2791
2792
2793/**
2794 * Interface for HM and EM to emulate a VM-exit.
2795 *
2796 * If a specialized version of a VM-exit handler exists, that must be used instead.
2797 *
2798 * @returns Strict VBox status code.
2799 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2800 * @param uExitReason The VM-exit reason.
2801 * @param u64ExitQual The Exit qualification.
2802 * @thread EMT(pVCpu)
2803 */
2804VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2805{
2806 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2807 Assert(!pVCpu->iem.s.cActiveMappings);
2808 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2809}
2810
2811
2812/**
2813 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2814 *
2815 * This is meant to be used for those instructions that VMX provides additional
2816 * decoding information beyond just the instruction length!
2817 *
2818 * @returns Strict VBox status code.
2819 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2820 * @param pExitInfo Pointer to the VM-exit information.
2821 * @thread EMT(pVCpu)
2822 */
2823VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2824{
2825 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2826 Assert(!pVCpu->iem.s.cActiveMappings);
2827 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2828}
2829
2830
2831/**
2832 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2833 *
2834 * This is meant to be used for those instructions that VMX provides only the
2835 * instruction length.
2836 *
2837 * @returns Strict VBox status code.
2838 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2839 * @param pExitInfo Pointer to the VM-exit information.
2840 * @param cbInstr The instruction length in bytes.
2841 * @thread EMT(pVCpu)
2842 */
2843VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2844{
2845 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2846 Assert(!pVCpu->iem.s.cActiveMappings);
2847 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2848}
2849
2850
2851/**
2852 * VMX VM-exit handler for VM-exits due to instruction execution.
2853 *
2854 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2855 * instruction information and Exit qualification fields.
2856 *
2857 * @param pVCpu The cross context virtual CPU structure.
2858 * @param uExitReason The VM-exit reason.
2859 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2860 * @param cbInstr The instruction length in bytes.
2861 *
2862 * @remarks Do not use this for INS/OUTS instruction.
2863 */
2864VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2865{
2866#ifdef VBOX_STRICT
2867 /*
2868 * To prevent us from shooting ourselves in the foot.
2869 * The follow instructions convey specific info that require using their respective handlers.
2870 */
2871 switch (uExitReason)
2872 {
2873 case VMX_EXIT_INVEPT:
2874 case VMX_EXIT_INVPCID:
2875 case VMX_EXIT_INVVPID:
2876 case VMX_EXIT_LDTR_TR_ACCESS:
2877 case VMX_EXIT_GDTR_IDTR_ACCESS:
2878 case VMX_EXIT_VMCLEAR:
2879 case VMX_EXIT_VMPTRLD:
2880 case VMX_EXIT_VMPTRST:
2881 case VMX_EXIT_VMREAD:
2882 case VMX_EXIT_VMWRITE:
2883 case VMX_EXIT_VMXON:
2884 case VMX_EXIT_XRSTORS:
2885 case VMX_EXIT_XSAVES:
2886 case VMX_EXIT_RDRAND:
2887 case VMX_EXIT_RDSEED:
2888 break;
2889 default:
2890 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2891 break;
2892 }
2893#endif
2894
2895 /*
2896 * Update the Exit qualification field with displacement bytes.
2897 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2898 */
2899 /* Construct the VM-exit instruction information. */
2900 RTGCPTR GCPtrDisp;
2901 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2902
2903 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(uExitReason, GCPtrDisp, uInstrInfo, cbInstr);
2904 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2905}
2906
2907
2908/**
2909 * VMX VM-exit handler for VM-exits due to INVLPG.
2910 *
2911 * @returns Strict VBox status code.
2912 * @param pVCpu The cross context virtual CPU structure.
2913 * @param GCPtrPage The guest-linear address of the page being invalidated.
2914 * @param cbInstr The instruction length in bytes.
2915 */
2916VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2917{
2918 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_INVLPG, GCPtrPage, cbInstr);
2919 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2920 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2921}
2922
2923
2924/**
2925 * VMX VM-exit handler for VM-exits due to LMSW.
2926 *
2927 * @returns Strict VBox status code.
2928 * @param pVCpu The cross context virtual CPU structure.
2929 * @param uGuestCr0 The current guest CR0.
2930 * @param pu16NewMsw The machine-status word specified in LMSW's source
2931 * operand. This will be updated depending on the VMX
2932 * guest/host CR0 mask if LMSW is not intercepted.
2933 * @param GCPtrEffDst The guest-linear address of the source operand in case
2934 * of a memory operand. For register operand, pass
2935 * NIL_RTGCPTR.
2936 * @param cbInstr The instruction length in bytes.
2937 */
2938VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2939 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2940{
2941 Assert(pu16NewMsw);
2942
2943 uint16_t const uNewMsw = *pu16NewMsw;
2944 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2945 {
2946 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2947 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2948 VMXVEXITINFO ExitInfo
2949 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2950 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2951 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2952 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw)
2953 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW),
2954 cbInstr);
2955 if (fMemOperand)
2956 {
2957 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2958 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2959 }
2960 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2961 }
2962
2963 /*
2964 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2965 * CR0 guest/host mask must be left unmodified.
2966 *
2967 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2968 */
2969 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2970 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2971 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2972
2973 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2974}
2975
2976
2977/**
2978 * VMX VM-exit handler for VM-exits due to CLTS.
2979 *
2980 * @returns Strict VBox status code.
2981 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2982 * VM-exit but must not modify the guest CR0.TS bit.
2983 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2984 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2985 * CR0 fixed bits in VMX operation).
2986 * @param pVCpu The cross context virtual CPU structure.
2987 * @param cbInstr The instruction length in bytes.
2988 */
2989VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2990{
2991 /*
2992 * If CR0.TS is owned by the host:
2993 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2994 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2995 * CLTS instruction completes without clearing CR0.TS.
2996 *
2997 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2998 */
2999 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3000 if (fGstHostMask & X86_CR0_TS)
3001 {
3002 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u & X86_CR0_TS)
3003 {
3004 Log2(("clts: Guest intercept -> VM-exit\n"));
3005 VMXVEXITINFO const ExitInfo
3006 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3007 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3008 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3009 VMX_EXIT_QUAL_CRX_ACCESS_CLTS),
3010 cbInstr);
3011 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3012 }
3013 return VINF_VMX_MODIFIES_BEHAVIOR;
3014 }
3015
3016 /*
3017 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3018 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3019 */
3020 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3021}
3022
3023
3024/**
3025 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3026 * (CR0/CR4 write).
3027 *
3028 * @returns Strict VBox status code.
3029 * @param pVCpu The cross context virtual CPU structure.
3030 * @param iCrReg The control register (either CR0 or CR4).
3031 * @param uGuestCrX The current guest CR0/CR4.
3032 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3033 * VM-exit is caused.
3034 * @param iGReg The general register from which the CR0/CR4 value is being
3035 * loaded.
3036 * @param cbInstr The instruction length in bytes.
3037 */
3038VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3039 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3040{
3041 Assert(puNewCrX);
3042 Assert(iCrReg == 0 || iCrReg == 4);
3043 Assert(iGReg < X86_GREG_COUNT);
3044
3045 uint64_t const uNewCrX = *puNewCrX;
3046 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3047 {
3048 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3049 VMXVEXITINFO const ExitInfo
3050 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3051 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3052 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3053 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3054 cbInstr);
3055 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3056 }
3057
3058 /*
3059 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3060 * must not be modified the instruction.
3061 *
3062 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3063 */
3064 uint64_t uGuestCrX;
3065 uint64_t fGstHostMask;
3066 if (iCrReg == 0)
3067 {
3068 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3069 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3070 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3071 }
3072 else
3073 {
3074 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3075 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3076 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3077 }
3078
3079 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3080 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3081}
3082
3083
3084/**
3085 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3086 *
3087 * @returns VBox strict status code.
3088 * @param pVCpu The cross context virtual CPU structure.
3089 * @param iGReg The general register to which the CR3 value is being stored.
3090 * @param cbInstr The instruction length in bytes.
3091 */
3092VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3093{
3094 Assert(iGReg < X86_GREG_COUNT);
3095 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3096
3097 /*
3098 * If the CR3-store exiting control is set, we must cause a VM-exit.
3099 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3100 */
3101 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3102 {
3103 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3104 VMXVEXITINFO const ExitInfo
3105 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3106 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3107 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3108 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3109 cbInstr);
3110 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3111 }
3112 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3113}
3114
3115
3116/**
3117 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3118 *
3119 * @returns VBox strict status code.
3120 * @param pVCpu The cross context virtual CPU structure.
3121 * @param uNewCr3 The new CR3 value.
3122 * @param iGReg The general register from which the CR3 value is being
3123 * loaded.
3124 * @param cbInstr The instruction length in bytes.
3125 */
3126VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3127{
3128 Assert(iGReg < X86_GREG_COUNT);
3129
3130 /*
3131 * If the CR3-load exiting control is set and the new CR3 value does not
3132 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3133 *
3134 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3135 */
3136 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3137 {
3138 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3139 VMXVEXITINFO const ExitInfo
3140 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3141 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3142 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3143 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3144 VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3145 cbInstr);
3146 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3147 }
3148 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3149}
3150
3151
3152/**
3153 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3154 *
3155 * @returns VBox strict status code.
3156 * @param pVCpu The cross context virtual CPU structure.
3157 * @param iGReg The general register to which the CR8 value is being stored.
3158 * @param cbInstr The instruction length in bytes.
3159 */
3160VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3161{
3162 Assert(iGReg < X86_GREG_COUNT);
3163
3164 /*
3165 * If the CR8-store exiting control is set, we must cause a VM-exit.
3166 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3167 */
3168 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3169 {
3170 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3171 VMXVEXITINFO const ExitInfo
3172 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3173 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3174 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3175 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3176 cbInstr);
3177 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3178 }
3179 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3180}
3181
3182
3183/**
3184 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3185 *
3186 * @returns VBox strict status code.
3187 * @param pVCpu The cross context virtual CPU structure.
3188 * @param iGReg The general register from which the CR8 value is being
3189 * loaded.
3190 * @param cbInstr The instruction length in bytes.
3191 */
3192VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3193{
3194 Assert(iGReg < X86_GREG_COUNT);
3195
3196 /*
3197 * If the CR8-load exiting control is set, we must cause a VM-exit.
3198 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3199 */
3200 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3201 {
3202 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3203 VMXVEXITINFO const ExitInfo
3204 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3205 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3206 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3207 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3208 cbInstr);
3209 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3210 }
3211 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3212}
3213
3214
3215/**
3216 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3217 * GReg,DRx' (DRx read).
3218 *
3219 * @returns VBox strict status code.
3220 * @param pVCpu The cross context virtual CPU structure.
3221 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3222 * VMXINSTRID_MOV_FROM_DRX).
3223 * @param iDrReg The debug register being accessed.
3224 * @param iGReg The general register to/from which the DRx value is being
3225 * store/loaded.
3226 * @param cbInstr The instruction length in bytes.
3227 */
3228VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3229 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3230{
3231 Assert(iDrReg <= 7);
3232 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3233 Assert(iGReg < X86_GREG_COUNT);
3234
3235 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3236 {
3237 VMXVEXITINFO const ExitInfo
3238 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_DRX,
3239 RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3240 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg)
3241 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION,
3242 uInstrId == VMXINSTRID_MOV_TO_DRX
3243 ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3244 : VMX_EXIT_QUAL_DRX_DIRECTION_READ),
3245 cbInstr);
3246 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3247 }
3248
3249 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3250}
3251
3252
3253/**
3254 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3255 *
3256 * @returns VBox strict status code.
3257 * @param pVCpu The cross context virtual CPU structure.
3258 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3259 * VMXINSTRID_IO_OUT).
3260 * @param u16Port The I/O port being accessed.
3261 * @param fImm Whether the I/O port was encoded using an immediate operand
3262 * or the implicit DX register.
3263 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3264 * @param cbInstr The instruction length in bytes.
3265 */
3266VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3267 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3268{
3269 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3270 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3271
3272 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3273 {
3274 VMXVEXITINFO const ExitInfo
3275 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_IO_INSTR,
3276 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3277 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3278 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port)
3279 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION,
3280 uInstrId == VMXINSTRID_IO_IN
3281 ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3282 : VMX_EXIT_QUAL_IO_DIRECTION_OUT),
3283 cbInstr);
3284 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3285 }
3286 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3287}
3288
3289
3290/**
3291 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3292 *
3293 * @returns VBox strict status code.
3294 * @param pVCpu The cross context virtual CPU structure.
3295 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3296 * VMXINSTRID_IO_OUTS).
3297 * @param u16Port The I/O port being accessed.
3298 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3299 * @param fRep Whether the instruction has a REP prefix or not.
3300 * @param ExitInstrInfo The VM-exit instruction info. field.
3301 * @param cbInstr The instruction length in bytes.
3302 */
3303VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3304 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3305{
3306 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3307 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3308 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3309 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3310 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3311
3312 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3313 {
3314 /*
3315 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3316 */
3317 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3318 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3319 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3320 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3321 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3322
3323 uint32_t uDirection;
3324 uint64_t uGuestLinearAddr;
3325 if (uInstrId == VMXINSTRID_IO_INS)
3326 {
3327 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3328 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3329 }
3330 else
3331 {
3332 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3333 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3334 }
3335
3336 /*
3337 * If the segment is unusable, the guest-linear address in undefined.
3338 * We shall clear it for consistency.
3339 *
3340 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3341 */
3342 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3343 uGuestLinearAddr = 0;
3344
3345 VMXVEXITINFO const ExitInfo
3346 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(VMX_EXIT_IO_INSTR,
3347 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3348 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3349 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3350 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3351 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING,
3352 VMX_EXIT_QUAL_IO_ENCODING_DX)
3353 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port),
3354 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo
3355 ? ExitInstrInfo.u : 0,
3356 cbInstr,
3357 uGuestLinearAddr);
3358 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3359 }
3360
3361 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3362}
3363
3364
3365/**
3366 * VMX VM-exit handler for VM-exits due to MWAIT.
3367 *
3368 * @returns VBox strict status code.
3369 * @param pVCpu The cross context virtual CPU structure.
3370 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3371 * @param cbInstr The instruction length in bytes.
3372 */
3373VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3374{
3375 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MWAIT, fMonitorHwArmed, cbInstr);
3376 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3377}
3378
3379
3380/**
3381 * VMX VM-exit handler for VM-exits due to PAUSE.
3382 *
3383 * @returns VBox strict status code.
3384 * @param pVCpu The cross context virtual CPU structure.
3385 * @param cbInstr The instruction length in bytes.
3386 */
3387static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3388{
3389 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3390
3391 /*
3392 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3393 * "PAUSE-loop exiting" control.
3394 *
3395 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3396 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3397 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3398 * a VM-exit.
3399 *
3400 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3401 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3402 */
3403 bool fIntercept = false;
3404 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3405 fIntercept = true;
3406 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3407 && pVCpu->iem.s.uCpl == 0)
3408 {
3409 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3410
3411 /*
3412 * A previous-PAUSE-tick value of 0 is used to identify the first time
3413 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3414 * consider this to be the first execution of PAUSE in a loop according
3415 * to the Intel.
3416 *
3417 * All subsequent records for the previous-PAUSE-tick we ensure that it
3418 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3419 */
3420 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3421 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3422 uint64_t const uTick = TMCpuTickGet(pVCpu);
3423 uint32_t const uPleGap = pVmcs->u32PleGap;
3424 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3425 if ( *puPrevPauseTick == 0
3426 || uTick - *puPrevPauseTick > uPleGap)
3427 *puFirstPauseLoopTick = uTick;
3428 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3429 fIntercept = true;
3430
3431 *puPrevPauseTick = uTick | 1;
3432 }
3433
3434 if (fIntercept)
3435 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3436
3437 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3438}
3439
3440
3441/**
3442 * VMX VM-exit handler for VM-exits due to task switches.
3443 *
3444 * @returns VBox strict status code.
3445 * @param pVCpu The cross context virtual CPU structure.
3446 * @param enmTaskSwitch The cause of the task switch.
3447 * @param SelNewTss The selector of the new TSS.
3448 * @param cbInstr The instruction length in bytes.
3449 */
3450VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3451{
3452 /*
3453 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3454 *
3455 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3456 * instruction or delivery of the exception generated by one of these instructions
3457 * lead to a task switch through a task gate in the IDT, we need to provide the
3458 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3459 * leaves the VM-exit instruction length field undefined.
3460 *
3461 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3462 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3463 */
3464 Assert(cbInstr <= 15);
3465
3466 uint8_t uType;
3467 switch (enmTaskSwitch)
3468 {
3469 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3470 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3471 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3472 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3473 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3474 }
3475
3476 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3477 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3478 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3479 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3480}
3481
3482
3483/**
3484 * VMX VM-exit handler for trap-like VM-exits.
3485 *
3486 * @returns VBox strict status code.
3487 * @param pVCpu The cross context virtual CPU structure.
3488 * @param pExitInfo Pointer to the VM-exit information.
3489 * @param pExitEventInfo Pointer to the VM-exit event information.
3490 */
3491static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3492{
3493 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3494 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3495 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3496}
3497
3498
3499/**
3500 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3501 * Virtualized-EOI, TPR-below threshold).
3502 *
3503 * @returns Strict VBox status code.
3504 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3505 * @param pExitInfo Pointer to the VM-exit information.
3506 * @thread EMT(pVCpu)
3507 */
3508VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3509{
3510 Assert(pExitInfo);
3511 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3512 Assert(!pVCpu->iem.s.cActiveMappings);
3513 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3514}
3515
3516
3517/**
3518 * VMX VM-exit handler for VM-exits due to task switches.
3519 *
3520 * This is intended for task switches where the caller provides all the relevant
3521 * VM-exit information.
3522 *
3523 * @returns VBox strict status code.
3524 * @param pVCpu The cross context virtual CPU structure.
3525 * @param pExitInfo Pointer to the VM-exit information.
3526 * @param pExitEventInfo Pointer to the VM-exit event information.
3527 */
3528static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3529 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3530{
3531 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3532 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3533 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3534 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3535 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3536}
3537
3538
3539/**
3540 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3541 *
3542 * @returns Strict VBox status code.
3543 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3544 * @param pExitInfo Pointer to the VM-exit information.
3545 * @param pExitEventInfo Pointer to the VM-exit event information.
3546 * @thread EMT(pVCpu)
3547 */
3548VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3549{
3550 Assert(pExitInfo);
3551 Assert(pExitEventInfo);
3552 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3553 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3554 Assert(!pVCpu->iem.s.cActiveMappings);
3555 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3556}
3557
3558
3559/**
3560 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3561 *
3562 * @returns VBox strict status code.
3563 * @param pVCpu The cross context virtual CPU structure.
3564 */
3565VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3566{
3567 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3568 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3569
3570 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3571 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3572
3573 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3574 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3575 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3576
3577 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3578 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3579}
3580
3581
3582/**
3583 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3584 *
3585 * @returns Strict VBox status code.
3586 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3587 * @thread EMT(pVCpu)
3588 */
3589VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3590{
3591 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3592 Assert(!pVCpu->iem.s.cActiveMappings);
3593 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3594}
3595
3596
3597/**
3598 * VMX VM-exit handler for VM-exits due to external interrupts.
3599 *
3600 * @returns VBox strict status code.
3601 * @param pVCpu The cross context virtual CPU structure.
3602 * @param uVector The external interrupt vector (pass 0 if the interrupt
3603 * is still pending since we typically won't know the
3604 * vector).
3605 * @param fIntPending Whether the external interrupt is pending or
3606 * acknowledged in the interrupt controller.
3607 */
3608static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3609{
3610 Assert(!fIntPending || uVector == 0);
3611
3612 /* The VM-exit is subject to "External interrupt exiting" being set. */
3613 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3614 {
3615 if (fIntPending)
3616 {
3617 /*
3618 * If the interrupt is pending and we don't need to acknowledge the
3619 * interrupt on VM-exit, cause the VM-exit immediately.
3620 *
3621 * See Intel spec 25.2 "Other Causes Of VM Exits".
3622 */
3623 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3624 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3625
3626 /*
3627 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3628 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3629 * acknowledged that the interrupt has been consumed. Callers would have to call
3630 * us again after getting the vector (and ofc, with fIntPending with false).
3631 */
3632 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3633 }
3634
3635 /*
3636 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3637 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3638 * all set, we need to record the vector of the external interrupt in the
3639 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3640 *
3641 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3642 */
3643 uint32_t uExitIntInfo;
3644 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3645 {
3646 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3647 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3648 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3649 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3650 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3651 }
3652 else
3653 uExitIntInfo = 0;
3654 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3655
3656 /*
3657 * Cause the VM-exit whether or not the vector has been stored
3658 * in the VM-exit interruption-information field.
3659 */
3660 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3661 }
3662
3663 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3664}
3665
3666
3667/**
3668 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3669 *
3670 * @returns Strict VBox status code.
3671 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3672 * @param uVector The external interrupt vector (pass 0 if the external
3673 * interrupt is still pending).
3674 * @param fIntPending Whether the external interrupt is pending or
3675 * acknowdledged in the interrupt controller.
3676 * @thread EMT(pVCpu)
3677 */
3678VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3679{
3680 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3681 Assert(!pVCpu->iem.s.cActiveMappings);
3682 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3683}
3684
3685
3686/**
3687 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3688 * an event.
3689 *
3690 * @returns VBox strict status code.
3691 * @param pVCpu The cross context virtual CPU structure.
3692 */
3693VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3694{
3695 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3696 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3697 {
3698 /*
3699 * The NMI-unblocking due to IRET field need not be set for double faults.
3700 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3701 */
3702 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3703 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3704 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3705 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3706 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3707 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3708 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3709 }
3710
3711 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3712}
3713
3714
3715/**
3716 * VMX VM-exit handler for VM-exit due to delivery of an events.
3717 *
3718 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3719 * all the relevant VM-exit information.
3720 *
3721 * @returns VBox strict status code.
3722 * @param pVCpu The cross context virtual CPU structure.
3723 * @param pExitInfo Pointer to the VM-exit information.
3724 * @param pExitEventInfo Pointer to the VM-exit event information.
3725 */
3726static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3727{
3728 Assert(pExitInfo);
3729 Assert(pExitEventInfo);
3730 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3731 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3732
3733 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3734 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3735 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3736 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3737 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3738 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3739}
3740
3741
3742/**
3743 * Interface for HM and EM to emulate VM-exit due to NMIs.
3744 *
3745 * @returns Strict VBox status code.
3746 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3747 * @thread EMT(pVCpu)
3748 */
3749VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3750{
3751 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_ONLY_REASON(VMX_EXIT_XCPT_OR_NMI);
3752 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_INT( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3753 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE,
3754 VMX_EXIT_INT_INFO_TYPE_NMI)
3755 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR,
3756 X86_XCPT_NMI),
3757 0);
3758 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3759 Assert(!pVCpu->iem.s.cActiveMappings);
3760 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3761}
3762
3763
3764/**
3765 * Interface for HM and EM to emulate VM-exit due to exceptions.
3766 *
3767 * Exception includes NMIs, software exceptions (those generated by INT3 or
3768 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3769 *
3770 * @returns Strict VBox status code.
3771 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3772 * @param pExitInfo Pointer to the VM-exit information.
3773 * @param pExitEventInfo Pointer to the VM-exit event information.
3774 * @thread EMT(pVCpu)
3775 */
3776VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3777{
3778 Assert(pExitInfo);
3779 Assert(pExitEventInfo);
3780 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3781 Assert(!pVCpu->iem.s.cActiveMappings);
3782 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3783}
3784
3785
3786/**
3787 * VMX VM-exit handler for VM-exits due to delivery of an event.
3788 *
3789 * @returns VBox strict status code.
3790 * @param pVCpu The cross context virtual CPU structure.
3791 * @param uVector The interrupt / exception vector.
3792 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3793 * @param uErrCode The error code associated with the event.
3794 * @param uCr2 The CR2 value in case of a \#PF exception.
3795 * @param cbInstr The instruction length in bytes.
3796 */
3797VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3798 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3799{
3800 /*
3801 * If the event is being injected as part of VM-entry, it is -not- subject to event
3802 * intercepts in the nested-guest. However, secondary exceptions that occur during
3803 * injection of any event -are- subject to event interception.
3804 *
3805 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3806 */
3807 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3808 {
3809 /*
3810 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3811 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3812 *
3813 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3814 */
3815 if ( uVector == X86_XCPT_NMI
3816 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3817 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3818 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3819 else
3820 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3821
3822 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3823 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3824 }
3825
3826 /*
3827 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3828 * If not, the caller will continue delivery of the external interrupt as it would
3829 * normally. The interrupt is no longer pending in the interrupt controller at this
3830 * point.
3831 */
3832 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3833 {
3834 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3835 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3836 }
3837
3838 /*
3839 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3840 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3841 * interrupts.
3842 */
3843 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3844 bool fIntercept;
3845 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3846 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3847 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3848 else
3849 {
3850 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3851 fIntercept = false;
3852 }
3853
3854 /*
3855 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3856 * relevant VM-exit information and cause the VM-exit.
3857 */
3858 if (fIntercept)
3859 {
3860 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3861
3862 /* Construct the rest of the event related information fields and cause the VM-exit. */
3863 uint64_t u64ExitQual;
3864 if (uVector == X86_XCPT_PF)
3865 {
3866 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3867 u64ExitQual = uCr2;
3868 }
3869 else if (uVector == X86_XCPT_DB)
3870 {
3871 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3872 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3873 }
3874 else
3875 u64ExitQual = 0;
3876
3877 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3878 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3879 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3880 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3881 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3882 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3883 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3884 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3885 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3886 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3887
3888 /*
3889 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3890 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3891 * length.
3892 */
3893 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3894 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3895 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3896 else
3897 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3898
3899 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3900 }
3901
3902 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3903}
3904
3905
3906/**
3907 * VMX VM-exit handler for EPT misconfiguration.
3908 *
3909 * @param pVCpu The cross context virtual CPU structure.
3910 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3911 * This need not be page aligned (e.g. nested-guest in real
3912 * mode).
3913 */
3914static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3915{
3916 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3917 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3918}
3919
3920
3921/**
3922 * VMX VM-exit handler for EPT misconfiguration.
3923 *
3924 * This is intended for EPT misconfigurations where the caller provides all the
3925 * relevant VM-exit information.
3926 *
3927 * @param pVCpu The cross context virtual CPU structure.
3928 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3929 * This need not be page aligned (e.g. nested-guest in real
3930 * mode).
3931 * @param pExitEventInfo Pointer to the VM-exit event information.
3932 */
3933static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3934{
3935 Assert(pExitEventInfo);
3936 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3937 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3938 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3939 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3940 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3941}
3942
3943
3944/**
3945 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3946 *
3947 * @returns Strict VBox status code.
3948 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3949 * @param GCPhysAddr The nested-guest physical address causing the EPT
3950 * misconfiguration.
3951 * @param pExitEventInfo Pointer to the VM-exit event information.
3952 * @thread EMT(pVCpu)
3953 */
3954VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3955{
3956 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3957
3958 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3959 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3960 Assert(!pVCpu->iem.s.cActiveMappings);
3961 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3962}
3963
3964
3965/**
3966 * VMX VM-exit handler for EPT violation.
3967 *
3968 * @param pVCpu The cross context virtual CPU structure.
3969 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3970 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3971 * @param fEptAccess The EPT paging structure bits.
3972 * @param GCPhysAddr The physical address causing the EPT violation. This
3973 * need not be page aligned (e.g. nested-guest in real
3974 * mode).
3975 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3976 * EPT violation. If @c false, GCPtrAddr must be 0.
3977 * @param GCPtrAddr The linear address causing the EPT violation.
3978 * @param cbInstr The VM-exit instruction length.
3979 */
3980static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3981 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3982 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3983{
3984 /*
3985 * If the linear address isn't valid (can happen when loading PDPTEs
3986 * as part of MOV CR execution) the linear address field is undefined.
3987 * While we can leave it this way, it's preferrable to zero it for consistency.
3988 */
3989 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
3990
3991 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3992 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
3993
3994 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
3995 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
3996 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
3997 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3998 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
3999 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
4000 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
4001 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
4002 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
4003 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4004 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
4005
4006 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
4007 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
4008 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
4009 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
4010 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
4011 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
4012 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
4013 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
4014 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4015
4016#ifdef VBOX_STRICT
4017 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4018 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4019 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4020 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4021 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4022 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4023#endif
4024
4025 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4026 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4027 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4028
4029 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4030}
4031
4032
4033/**
4034 * VMX VM-exit handler for EPT violation.
4035 *
4036 * This is intended for EPT violations where the caller provides all the
4037 * relevant VM-exit information.
4038 *
4039 * @returns VBox strict status code.
4040 * @param pVCpu The cross context virtual CPU structure.
4041 * @param pExitInfo Pointer to the VM-exit information.
4042 * @param pExitEventInfo Pointer to the VM-exit event information.
4043 */
4044static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4045 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4046{
4047 Assert(pExitInfo);
4048 Assert(pExitEventInfo);
4049 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4050 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4051
4052 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4053 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4054
4055 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4056 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4057 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4058 else
4059 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4060 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4061 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4062}
4063
4064
4065/**
4066 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4067 *
4068 * @returns Strict VBox status code.
4069 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4070 * @param pExitInfo Pointer to the VM-exit information.
4071 * @param pExitEventInfo Pointer to the VM-exit event information.
4072 * @thread EMT(pVCpu)
4073 */
4074VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4075 PCVMXVEXITEVENTINFO pExitEventInfo)
4076{
4077 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4078
4079 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4080 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4081 Assert(!pVCpu->iem.s.cActiveMappings);
4082 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4083}
4084
4085
4086/**
4087 * VMX VM-exit handler for EPT-induced VM-exits.
4088 *
4089 * @param pVCpu The cross context virtual CPU structure.
4090 * @param pWalk The page walk info.
4091 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4092 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4093 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4094 * applicable.
4095 */
4096VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4097{
4098 Assert(pWalk->fIsSlat);
4099 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4100 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4101 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4102
4103 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4104 {
4105 LogFlow(("EptViolation: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4106 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4107 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4108 pWalk->GCPtr, cbInstr);
4109 }
4110
4111 LogFlow(("EptMisconfig: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4112 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4113 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4114}
4115
4116
4117/**
4118 * VMX VM-exit handler for APIC accesses.
4119 *
4120 * @param pVCpu The cross context virtual CPU structure.
4121 * @param offAccess The offset of the register being accessed.
4122 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4123 */
4124static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4125{
4126 VMXAPICACCESS enmAccess;
4127 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4128 if (fInEventDelivery)
4129 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4130 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4131 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4132 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4133 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4134 else
4135 enmAccess = VMXAPICACCESS_LINEAR_READ;
4136
4137 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4138 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4139 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4140}
4141
4142
4143/**
4144 * VMX VM-exit handler for APIC accesses.
4145 *
4146 * This is intended for APIC accesses where the caller provides all the
4147 * relevant VM-exit information.
4148 *
4149 * @returns VBox strict status code.
4150 * @param pVCpu The cross context virtual CPU structure.
4151 * @param pExitInfo Pointer to the VM-exit information.
4152 * @param pExitEventInfo Pointer to the VM-exit event information.
4153 */
4154static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4155 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4156{
4157 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4158 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4159 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4160 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4161 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4162 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4163 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4164 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4165 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4166}
4167
4168
4169/**
4170 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4171 *
4172 * @returns Strict VBox status code.
4173 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4174 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4175 *
4176 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4177 * @param pExitInfo Pointer to the VM-exit information.
4178 * @param pExitEventInfo Pointer to the VM-exit event information.
4179 * @thread EMT(pVCpu)
4180 */
4181VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4182{
4183 Assert(pExitInfo);
4184 Assert(pExitEventInfo);
4185 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4186 Assert(!pVCpu->iem.s.cActiveMappings);
4187 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4188}
4189
4190
4191/**
4192 * VMX VM-exit handler for APIC-write VM-exits.
4193 *
4194 * @param pVCpu The cross context virtual CPU structure.
4195 * @param offApic The write to the virtual-APIC page offset that caused this
4196 * VM-exit.
4197 */
4198static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4199{
4200 Assert(offApic < XAPIC_OFF_END + 4);
4201 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4202 offApic &= UINT16_C(0xfff);
4203 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4204}
4205
4206
4207/**
4208 * Clears any pending virtual-APIC write emulation.
4209 *
4210 * @returns The virtual-APIC offset that was written before clearing it.
4211 * @param pVCpu The cross context virtual CPU structure.
4212 */
4213DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4214{
4215 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4216 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4217 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4218 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4219 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4220 return offVirtApicWrite;
4221}
4222
4223
4224/**
4225 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4226 *
4227 * @returns The register from the virtual-APIC page.
4228 * @param pVCpu The cross context virtual CPU structure.
4229 * @param offReg The offset of the register being read.
4230 */
4231uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4232{
4233 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4234
4235 uint32_t uReg = 0;
4236 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4237 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4238 AssertMsgStmt(RT_SUCCESS(rc),
4239 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4240 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4241 uReg = 0);
4242 return uReg;
4243}
4244
4245
4246/**
4247 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4248 *
4249 * @returns The register from the virtual-APIC page.
4250 * @param pVCpu The cross context virtual CPU structure.
4251 * @param offReg The offset of the register being read.
4252 */
4253static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4254{
4255 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4256
4257 uint64_t uReg = 0;
4258 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4259 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4260 AssertMsgStmt(RT_SUCCESS(rc),
4261 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4262 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4263 uReg = 0);
4264 return uReg;
4265}
4266
4267
4268/**
4269 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4270 *
4271 * @param pVCpu The cross context virtual CPU structure.
4272 * @param offReg The offset of the register being written.
4273 * @param uReg The register value to write.
4274 */
4275void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4276{
4277 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4278
4279 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4280 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4281 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4282 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4283}
4284
4285
4286/**
4287 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4288 *
4289 * @param pVCpu The cross context virtual CPU structure.
4290 * @param offReg The offset of the register being written.
4291 * @param uReg The register value to write.
4292 */
4293static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4294{
4295 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4296
4297 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4298 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4299 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4300 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4301}
4302
4303
4304/**
4305 * Sets the vector in a virtual-APIC 256-bit sparse register.
4306 *
4307 * @param pVCpu The cross context virtual CPU structure.
4308 * @param offReg The offset of the 256-bit spare register.
4309 * @param uVector The vector to set.
4310 *
4311 * @remarks This is based on our APIC device code.
4312 */
4313static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4314{
4315 /* Determine the vector offset within the chunk. */
4316 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4317
4318 /* Read the chunk at the offset. */
4319 uint32_t uReg;
4320 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4321 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4322 if (RT_SUCCESS(rc))
4323 {
4324 /* Modify the chunk. */
4325 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4326 uReg |= RT_BIT(idxVectorBit);
4327
4328 /* Write the chunk. */
4329 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4330 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4331 uVector, offReg, GCPhysVirtApic, rc));
4332 }
4333 else
4334 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4335 uVector, offReg, GCPhysVirtApic, rc));
4336}
4337
4338
4339/**
4340 * Clears the vector in a virtual-APIC 256-bit sparse register.
4341 *
4342 * @param pVCpu The cross context virtual CPU structure.
4343 * @param offReg The offset of the 256-bit spare register.
4344 * @param uVector The vector to clear.
4345 *
4346 * @remarks This is based on our APIC device code.
4347 */
4348static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4349{
4350 /* Determine the vector offset within the chunk. */
4351 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4352
4353 /* Read the chunk at the offset. */
4354 uint32_t uReg;
4355 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4356 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4357 if (RT_SUCCESS(rc))
4358 {
4359 /* Modify the chunk. */
4360 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4361 uReg &= ~RT_BIT(idxVectorBit);
4362
4363 /* Write the chunk. */
4364 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4365 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4366 uVector, offReg, GCPhysVirtApic, rc));
4367 }
4368 else
4369 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4370 uVector, offReg, GCPhysVirtApic, rc));
4371}
4372
4373
4374/**
4375 * Checks if a memory access to the APIC-access page must causes an APIC-access
4376 * VM-exit.
4377 *
4378 * @param pVCpu The cross context virtual CPU structure.
4379 * @param offAccess The offset of the register being accessed.
4380 * @param cbAccess The size of the access in bytes.
4381 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4382 *
4383 * @remarks This must not be used for MSR-based APIC-access page accesses!
4384 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4385 */
4386static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4387{
4388 Assert(cbAccess > 0);
4389 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4390
4391 /*
4392 * We must cause a VM-exit if any of the following are true:
4393 * - TPR shadowing isn't active.
4394 * - The access size exceeds 32-bits.
4395 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4396 *
4397 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4398 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4399 */
4400 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4401 || cbAccess > sizeof(uint32_t)
4402 || ((offAccess + cbAccess - 1) & 0xc)
4403 || offAccess >= XAPIC_OFF_END + 4)
4404 return true;
4405
4406 /*
4407 * If the access is part of an operation where we have already
4408 * virtualized a virtual-APIC write, we must cause a VM-exit.
4409 */
4410 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4411 return true;
4412
4413 /*
4414 * Check write accesses to the APIC-access page that cause VM-exits.
4415 */
4416 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4417 {
4418 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4419 {
4420 /*
4421 * With APIC-register virtualization, a write access to any of the
4422 * following registers are virtualized. Accessing any other register
4423 * causes a VM-exit.
4424 */
4425 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4426 switch (offAlignedAccess)
4427 {
4428 case XAPIC_OFF_ID:
4429 case XAPIC_OFF_TPR:
4430 case XAPIC_OFF_EOI:
4431 case XAPIC_OFF_LDR:
4432 case XAPIC_OFF_DFR:
4433 case XAPIC_OFF_SVR:
4434 case XAPIC_OFF_ESR:
4435 case XAPIC_OFF_ICR_LO:
4436 case XAPIC_OFF_ICR_HI:
4437 case XAPIC_OFF_LVT_TIMER:
4438 case XAPIC_OFF_LVT_THERMAL:
4439 case XAPIC_OFF_LVT_PERF:
4440 case XAPIC_OFF_LVT_LINT0:
4441 case XAPIC_OFF_LVT_LINT1:
4442 case XAPIC_OFF_LVT_ERROR:
4443 case XAPIC_OFF_TIMER_ICR:
4444 case XAPIC_OFF_TIMER_DCR:
4445 break;
4446 default:
4447 return true;
4448 }
4449 }
4450 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4451 {
4452 /*
4453 * With virtual-interrupt delivery, a write access to any of the
4454 * following registers are virtualized. Accessing any other register
4455 * causes a VM-exit.
4456 *
4457 * Note! The specification does not allow writing to offsets in-between
4458 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4459 */
4460 switch (offAccess)
4461 {
4462 case XAPIC_OFF_TPR:
4463 case XAPIC_OFF_EOI:
4464 case XAPIC_OFF_ICR_LO:
4465 break;
4466 default:
4467 return true;
4468 }
4469 }
4470 else
4471 {
4472 /*
4473 * Without APIC-register virtualization or virtual-interrupt delivery,
4474 * only TPR accesses are virtualized.
4475 */
4476 if (offAccess == XAPIC_OFF_TPR)
4477 { /* likely */ }
4478 else
4479 return true;
4480 }
4481 }
4482 else
4483 {
4484 /*
4485 * Check read accesses to the APIC-access page that cause VM-exits.
4486 */
4487 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4488 {
4489 /*
4490 * With APIC-register virtualization, a read access to any of the
4491 * following registers are virtualized. Accessing any other register
4492 * causes a VM-exit.
4493 */
4494 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4495 switch (offAlignedAccess)
4496 {
4497 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4498 case XAPIC_OFF_ID:
4499 case XAPIC_OFF_VERSION:
4500 case XAPIC_OFF_TPR:
4501 case XAPIC_OFF_EOI:
4502 case XAPIC_OFF_LDR:
4503 case XAPIC_OFF_DFR:
4504 case XAPIC_OFF_SVR:
4505 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4506 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4507 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4508 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4509 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4510 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4511 case XAPIC_OFF_ESR:
4512 case XAPIC_OFF_ICR_LO:
4513 case XAPIC_OFF_ICR_HI:
4514 case XAPIC_OFF_LVT_TIMER:
4515 case XAPIC_OFF_LVT_THERMAL:
4516 case XAPIC_OFF_LVT_PERF:
4517 case XAPIC_OFF_LVT_LINT0:
4518 case XAPIC_OFF_LVT_LINT1:
4519 case XAPIC_OFF_LVT_ERROR:
4520 case XAPIC_OFF_TIMER_ICR:
4521 case XAPIC_OFF_TIMER_DCR:
4522 break;
4523 default:
4524 return true;
4525 }
4526 }
4527 else
4528 {
4529 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4530 if (offAccess == XAPIC_OFF_TPR)
4531 { /* likely */ }
4532 else
4533 return true;
4534 }
4535 }
4536
4537 /* The APIC access is virtualized, does not cause a VM-exit. */
4538 return false;
4539}
4540
4541
4542/**
4543 * Virtualizes a memory-based APIC access by certain instructions even though they
4544 * do not use the address to access memory.
4545 *
4546 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4547 * page-faults but do not use the address to access memory.
4548 *
4549 * @param pVCpu The cross context virtual CPU structure.
4550 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4551 * @param cbAccess The size of the access in bytes.
4552 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4553 */
4554VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4555{
4556 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4557 Assert(pGCPhysAccess);
4558
4559 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4560 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4561 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4562
4563 if (GCPhysAccess == GCPhysApic)
4564 {
4565 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4566 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4567 if (fIntercept)
4568 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4569
4570 *pGCPhysAccess = GCPhysApic | offAccess;
4571 return VINF_VMX_MODIFIES_BEHAVIOR;
4572 }
4573
4574 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4575}
4576
4577
4578/**
4579 * Virtualizes a memory-based APIC access.
4580 *
4581 * @returns VBox strict status code.
4582 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4583 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4584 *
4585 * @param pVCpu The cross context virtual CPU structure.
4586 * @param offAccess The offset of the register being accessed (within the
4587 * APIC-access page).
4588 * @param cbAccess The size of the access in bytes.
4589 * @param pvData Pointer to the data being written or where to store the data
4590 * being read.
4591 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4592 */
4593static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4594 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4595{
4596 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4597 Assert(pvData);
4598
4599 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4600 if (fIntercept)
4601 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4602
4603 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4604 {
4605 /*
4606 * A write access to the APIC-access page that is virtualized (rather than
4607 * causing a VM-exit) writes data to the virtual-APIC page.
4608 */
4609 uint32_t const u32Data = *(uint32_t *)pvData;
4610 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4611
4612 /*
4613 * Record the currently updated APIC offset, as we need this later for figuring
4614 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4615 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4616 *
4617 * After completion of the current operation, we need to perform TPR virtualization,
4618 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4619 *
4620 * The current operation may be a REP-prefixed string instruction, execution of any
4621 * other instruction, or delivery of an event through the IDT.
4622 *
4623 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4624 * performed now but later after completion of the current operation.
4625 *
4626 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4627 */
4628 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4629
4630 LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4631 }
4632 else
4633 {
4634 /*
4635 * A read access from the APIC-access page that is virtualized (rather than
4636 * causing a VM-exit) returns data from the virtual-APIC page.
4637 *
4638 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4639 */
4640 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4641
4642 Assert(cbAccess <= 4);
4643 Assert(offAccess < XAPIC_OFF_END + 4);
4644 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4645
4646 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4647 u32Data &= s_auAccessSizeMasks[cbAccess];
4648 *(uint32_t *)pvData = u32Data;
4649
4650 LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4651 }
4652
4653 return VINF_VMX_MODIFIES_BEHAVIOR;
4654}
4655
4656
4657/**
4658 * Virtualizes an MSR-based APIC read access.
4659 *
4660 * @returns VBox strict status code.
4661 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4662 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4663 * handled by the x2APIC device.
4664 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4665 * not within the range of valid MSRs, caller must raise \#GP(0).
4666 * @param pVCpu The cross context virtual CPU structure.
4667 * @param idMsr The x2APIC MSR being read.
4668 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4669 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4670 */
4671static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4672{
4673 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4674 Assert(pu64Value);
4675
4676 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4677 {
4678 if ( idMsr >= MSR_IA32_X2APIC_START
4679 && idMsr <= MSR_IA32_X2APIC_END)
4680 {
4681 uint16_t const offReg = (idMsr & 0xff) << 4;
4682 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4683 *pu64Value = u64Value;
4684 return VINF_VMX_MODIFIES_BEHAVIOR;
4685 }
4686 return VERR_OUT_OF_RANGE;
4687 }
4688
4689 if (idMsr == MSR_IA32_X2APIC_TPR)
4690 {
4691 uint16_t const offReg = (idMsr & 0xff) << 4;
4692 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4693 *pu64Value = u64Value;
4694 return VINF_VMX_MODIFIES_BEHAVIOR;
4695 }
4696
4697 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4698}
4699
4700
4701/**
4702 * Virtualizes an MSR-based APIC write access.
4703 *
4704 * @returns VBox strict status code.
4705 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4706 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4707 * not within the range of valid MSRs, caller must raise \#GP(0).
4708 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4709 *
4710 * @param pVCpu The cross context virtual CPU structure.
4711 * @param idMsr The x2APIC MSR being written.
4712 * @param u64Value The value of the x2APIC MSR being written.
4713 */
4714static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4715{
4716 /*
4717 * Check if the access is to be virtualized.
4718 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4719 */
4720 if ( idMsr == MSR_IA32_X2APIC_TPR
4721 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4722 && ( idMsr == MSR_IA32_X2APIC_EOI
4723 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4724 {
4725 /* Validate the MSR write depending on the register. */
4726 switch (idMsr)
4727 {
4728 case MSR_IA32_X2APIC_TPR:
4729 case MSR_IA32_X2APIC_SELF_IPI:
4730 {
4731 if (u64Value & UINT64_C(0xffffffffffffff00))
4732 return VERR_OUT_OF_RANGE;
4733 break;
4734 }
4735 case MSR_IA32_X2APIC_EOI:
4736 {
4737 if (u64Value != 0)
4738 return VERR_OUT_OF_RANGE;
4739 break;
4740 }
4741 }
4742
4743 /* Write the MSR to the virtual-APIC page. */
4744 uint16_t const offReg = (idMsr & 0xff) << 4;
4745 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4746
4747 /*
4748 * Record the currently updated APIC offset, as we need this later for figuring
4749 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4750 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4751 */
4752 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4753
4754 return VINF_VMX_MODIFIES_BEHAVIOR;
4755 }
4756
4757 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4758}
4759
4760
4761/**
4762 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4763 *
4764 * @returns Strict VBox status code.
4765 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4766 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4767 * the x2APIC device.
4768 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4769 *
4770 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4771 * @param idMsr The MSR being read.
4772 * @param pu64Value Pointer to the value being written or where to store the
4773 * value being read.
4774 * @param fWrite Whether this is an MSR write or read access.
4775 * @thread EMT(pVCpu)
4776 */
4777VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4778{
4779 Assert(pu64Value);
4780
4781 VBOXSTRICTRC rcStrict;
4782 if (fWrite)
4783 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4784 else
4785 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4786 Assert(!pVCpu->iem.s.cActiveMappings);
4787 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4788
4789}
4790
4791
4792/**
4793 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4794 *
4795 * @returns VBox status code.
4796 * @retval VINF_SUCCESS when the highest set bit is found.
4797 * @retval VERR_NOT_FOUND when no bit is set.
4798 *
4799 * @param pVCpu The cross context virtual CPU structure.
4800 * @param offReg The offset of the APIC 256-bit sparse register.
4801 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4802 * set in the register. Only valid when VINF_SUCCESS is
4803 * returned.
4804 *
4805 * @remarks The format of the 256-bit sparse register here mirrors that found in
4806 * real APIC hardware.
4807 */
4808static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4809{
4810 Assert(offReg < XAPIC_OFF_END + 4);
4811 Assert(pidxHighestBit);
4812
4813 /*
4814 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4815 * However, in each fragment only the first 4 bytes are used.
4816 */
4817 uint8_t const cFrags = 8;
4818 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4819 {
4820 uint16_t const offFrag = iFrag * 16;
4821 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4822 if (!u32Frag)
4823 continue;
4824
4825 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4826 Assert(idxHighestBit > 0);
4827 --idxHighestBit;
4828 Assert(idxHighestBit <= UINT8_MAX);
4829 *pidxHighestBit = idxHighestBit;
4830 return VINF_SUCCESS;
4831 }
4832 return VERR_NOT_FOUND;
4833}
4834
4835
4836/**
4837 * Evaluates pending virtual interrupts.
4838 *
4839 * @param pVCpu The cross context virtual CPU structure.
4840 */
4841static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4842{
4843 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4844
4845 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4846 {
4847 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4848 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4849
4850 if ((uRvi >> 4) > (uPpr >> 4))
4851 {
4852 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4853 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4854 }
4855 else
4856 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4857 }
4858}
4859
4860
4861/**
4862 * Performs PPR virtualization.
4863 *
4864 * @returns VBox strict status code.
4865 * @param pVCpu The cross context virtual CPU structure.
4866 */
4867static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4868{
4869 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4870 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4871
4872 /*
4873 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4874 * or EOI-virtualization.
4875 *
4876 * See Intel spec. 29.1.3 "PPR Virtualization".
4877 */
4878 uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4879 uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4880
4881 uint32_t uPpr;
4882 if ((uTpr & 0xf0) >= uSvi)
4883 uPpr = uTpr;
4884 else
4885 uPpr = uSvi;
4886
4887 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4888 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4889}
4890
4891
4892/**
4893 * Performs VMX TPR virtualization.
4894 *
4895 * @returns VBox strict status code.
4896 * @param pVCpu The cross context virtual CPU structure.
4897 */
4898static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4899{
4900 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4901
4902 /*
4903 * We should have already performed the virtual-APIC write to the TPR offset
4904 * in the virtual-APIC page. We now perform TPR virtualization.
4905 *
4906 * See Intel spec. 29.1.2 "TPR Virtualization".
4907 */
4908 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4909 {
4910 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4911 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4912
4913 /*
4914 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4915 * See Intel spec. 29.1.2 "TPR Virtualization".
4916 */
4917 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4918 {
4919 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4920 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4921 }
4922 }
4923 else
4924 {
4925 iemVmxPprVirtualization(pVCpu);
4926 iemVmxEvalPendingVirtIntrs(pVCpu);
4927 }
4928
4929 return VINF_SUCCESS;
4930}
4931
4932
4933/**
4934 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4935 * not.
4936 *
4937 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4938 * @param pVCpu The cross context virtual CPU structure.
4939 * @param uVector The interrupt that was acknowledged using an EOI.
4940 */
4941static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4942{
4943 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4944 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4945
4946 if (uVector < 64)
4947 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4948 if (uVector < 128)
4949 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4950 if (uVector < 192)
4951 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4952 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4953}
4954
4955
4956/**
4957 * Performs EOI virtualization.
4958 *
4959 * @returns VBox strict status code.
4960 * @param pVCpu The cross context virtual CPU structure.
4961 */
4962static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4963{
4964 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4965 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4966
4967 /*
4968 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4969 * and get the next guest-interrupt that's in-service (if any).
4970 *
4971 * See Intel spec. 29.1.4 "EOI Virtualization".
4972 */
4973 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4974 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4975 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4976
4977 uint8_t uVector = uSvi;
4978 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4979
4980 uVector = 0;
4981 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4982
4983 if (uVector)
4984 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4985 else
4986 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4987
4988 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4989 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4990
4991 iemVmxPprVirtualization(pVCpu);
4992 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4993 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4994 iemVmxEvalPendingVirtIntrs(pVCpu);
4995 return VINF_SUCCESS;
4996}
4997
4998
4999/**
5000 * Performs self-IPI virtualization.
5001 *
5002 * @returns VBox strict status code.
5003 * @param pVCpu The cross context virtual CPU structure.
5004 */
5005static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
5006{
5007 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5008 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5009
5010 /*
5011 * We should have already performed the virtual-APIC write to the self-IPI offset
5012 * in the virtual-APIC page. We now perform self-IPI virtualization.
5013 *
5014 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5015 */
5016 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5017 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5018 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5019 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5020 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5021 if (uVector > uRvi)
5022 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5023 iemVmxEvalPendingVirtIntrs(pVCpu);
5024 return VINF_SUCCESS;
5025}
5026
5027
5028/**
5029 * Performs VMX APIC-write emulation.
5030 *
5031 * @returns VBox strict status code.
5032 * @param pVCpu The cross context virtual CPU structure.
5033 */
5034VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5035{
5036 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5037
5038 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5039 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5040
5041 /*
5042 * Perform APIC-write emulation based on the virtual-APIC register written.
5043 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5044 */
5045 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5046 VBOXSTRICTRC rcStrict;
5047 switch (offApicWrite)
5048 {
5049 case XAPIC_OFF_TPR:
5050 {
5051 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5052 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5053 uTpr &= UINT32_C(0x000000ff);
5054 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5055 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5056 rcStrict = iemVmxTprVirtualization(pVCpu);
5057 break;
5058 }
5059
5060 case XAPIC_OFF_EOI:
5061 {
5062 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5063 {
5064 /* Clear VEOI and perform EOI virtualization. */
5065 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5066 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5067 rcStrict = iemVmxEoiVirtualization(pVCpu);
5068 }
5069 else
5070 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5071 break;
5072 }
5073
5074 case XAPIC_OFF_ICR_LO:
5075 {
5076 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5077 {
5078 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5079 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5080 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5081 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5082 if ( !(uIcrLo & fIcrLoMb0)
5083 && (uIcrLo & fIcrLoMb1))
5084 {
5085 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5086 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5087 }
5088 else
5089 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5090 }
5091 else
5092 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5093 break;
5094 }
5095
5096 case XAPIC_OFF_ICR_HI:
5097 {
5098 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5099 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5100 uIcrHi &= UINT32_C(0xff000000);
5101 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5102 rcStrict = VINF_SUCCESS;
5103 break;
5104 }
5105
5106 default:
5107 {
5108 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5109 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5110 break;
5111 }
5112 }
5113
5114 return rcStrict;
5115}
5116
5117
5118/**
5119 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5120 * VM-exit.
5121 *
5122 * @returns Strict VBox status code.
5123 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5124 * @thread EMT(pVCpu)
5125 */
5126VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5127{
5128 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5129 Assert(!pVCpu->iem.s.cActiveMappings);
5130 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5131}
5132
5133
5134/**
5135 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5136 *
5137 * @param pVCpu The cross context virtual CPU structure.
5138 * @param pszInstr The VMX instruction name (for logging purposes).
5139 */
5140DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5141{
5142 /*
5143 * Guest Control Registers, Debug Registers, and MSRs.
5144 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5145 */
5146 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5147 const char * const pszFailure = "VM-exit";
5148 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5149
5150 /* CR0 reserved bits. */
5151 {
5152 /* CR0 MB1 bits. */
5153 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
5154 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5155 { /* likely */ }
5156 else
5157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5158
5159 /* CR0 MBZ bits. */
5160 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5161 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5162 { /* likely */ }
5163 else
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5165
5166 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5167 if ( !fUnrestrictedGuest
5168 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5169 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5171 }
5172
5173 /* CR4 reserved bits. */
5174 {
5175 /* CR4 MB1 bits. */
5176 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5177 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5178 { /* likely */ }
5179 else
5180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5181
5182 /* CR4 MBZ bits. */
5183 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5184 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5185 { /* likely */ }
5186 else
5187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5188 }
5189
5190 /* DEBUGCTL MSR. */
5191 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5192 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5193 { /* likely */ }
5194 else
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5196
5197 /* 64-bit CPU checks. */
5198 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5199 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5200 {
5201 if (fGstInLongMode)
5202 {
5203 /* PAE must be set. */
5204 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5205 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5206 { /* likely */ }
5207 else
5208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5209 }
5210 else
5211 {
5212 /* PCIDE should not be set. */
5213 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5214 { /* likely */ }
5215 else
5216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5217 }
5218
5219 /* CR3. */
5220 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5221 { /* likely */ }
5222 else
5223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5224
5225 /* DR7. */
5226 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5227 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5228 { /* likely */ }
5229 else
5230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5231
5232 /* SYSENTER ESP and SYSENTER EIP. */
5233 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5234 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5235 { /* likely */ }
5236 else
5237 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5238 }
5239
5240 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5241 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5242
5243 /* PAT MSR. */
5244 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5245 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5246 { /* likely */ }
5247 else
5248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5249
5250 /* EFER MSR. */
5251 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5252 {
5253 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5254 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5255 { /* likely */ }
5256 else
5257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5258
5259 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5260 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5261 if ( fGstLma == fGstInLongMode
5262 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5263 || fGstLma == fGstLme))
5264 { /* likely */ }
5265 else
5266 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5267 }
5268
5269 /* We don't support IA32_BNDCFGS MSR yet. */
5270 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5271
5272 NOREF(pszInstr);
5273 NOREF(pszFailure);
5274 return VINF_SUCCESS;
5275}
5276
5277
5278/**
5279 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5280 *
5281 * @param pVCpu The cross context virtual CPU structure.
5282 * @param pszInstr The VMX instruction name (for logging purposes).
5283 */
5284DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5285{
5286 /*
5287 * Segment registers.
5288 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5289 */
5290 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5291 const char * const pszFailure = "VM-exit";
5292 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5293 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5294 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5295
5296 /* Selectors. */
5297 if ( !fGstInV86Mode
5298 && !fUnrestrictedGuest
5299 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5301
5302 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5303 {
5304 CPUMSELREG SelReg;
5305 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5306 if (RT_LIKELY(rc == VINF_SUCCESS))
5307 { /* likely */ }
5308 else
5309 return rc;
5310
5311 /*
5312 * Virtual-8086 mode checks.
5313 */
5314 if (fGstInV86Mode)
5315 {
5316 /* Base address. */
5317 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5318 { /* likely */ }
5319 else
5320 {
5321 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5323 }
5324
5325 /* Limit. */
5326 if (SelReg.u32Limit == 0xffff)
5327 { /* likely */ }
5328 else
5329 {
5330 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5332 }
5333
5334 /* Attribute. */
5335 if (SelReg.Attr.u == 0xf3)
5336 { /* likely */ }
5337 else
5338 {
5339 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5341 }
5342
5343 /* We're done; move to checking the next segment. */
5344 continue;
5345 }
5346
5347 /* Checks done by 64-bit CPUs. */
5348 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5349 {
5350 /* Base address. */
5351 if ( iSegReg == X86_SREG_FS
5352 || iSegReg == X86_SREG_GS)
5353 {
5354 if (X86_IS_CANONICAL(SelReg.u64Base))
5355 { /* likely */ }
5356 else
5357 {
5358 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5360 }
5361 }
5362 else if (iSegReg == X86_SREG_CS)
5363 {
5364 if (!RT_HI_U32(SelReg.u64Base))
5365 { /* likely */ }
5366 else
5367 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5368 }
5369 else
5370 {
5371 if ( SelReg.Attr.n.u1Unusable
5372 || !RT_HI_U32(SelReg.u64Base))
5373 { /* likely */ }
5374 else
5375 {
5376 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5378 }
5379 }
5380 }
5381
5382 /*
5383 * Checks outside Virtual-8086 mode.
5384 */
5385 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5386 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5387 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5388 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5389 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5390 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5391 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5392 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5393
5394 /* Code or usable segment. */
5395 if ( iSegReg == X86_SREG_CS
5396 || fUsable)
5397 {
5398 /* Reserved bits (bits 31:17 and bits 11:8). */
5399 if (!(SelReg.Attr.u & 0xfffe0f00))
5400 { /* likely */ }
5401 else
5402 {
5403 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5405 }
5406
5407 /* Descriptor type. */
5408 if (fCodeDataSeg)
5409 { /* likely */ }
5410 else
5411 {
5412 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5414 }
5415
5416 /* Present. */
5417 if (fPresent)
5418 { /* likely */ }
5419 else
5420 {
5421 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5423 }
5424
5425 /* Granularity. */
5426 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5427 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5428 { /* likely */ }
5429 else
5430 {
5431 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5433 }
5434 }
5435
5436 if (iSegReg == X86_SREG_CS)
5437 {
5438 /* Segment Type and DPL. */
5439 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5440 && fUnrestrictedGuest)
5441 {
5442 if (uDpl == 0)
5443 { /* likely */ }
5444 else
5445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5446 }
5447 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5448 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5449 {
5450 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5451 if (uDpl == AttrSs.n.u2Dpl)
5452 { /* likely */ }
5453 else
5454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5455 }
5456 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5457 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5458 {
5459 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5460 if (uDpl <= AttrSs.n.u2Dpl)
5461 { /* likely */ }
5462 else
5463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5464 }
5465 else
5466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5467
5468 /* Def/Big. */
5469 if ( fGstInLongMode
5470 && fSegLong)
5471 {
5472 if (uDefBig == 0)
5473 { /* likely */ }
5474 else
5475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5476 }
5477 }
5478 else if (iSegReg == X86_SREG_SS)
5479 {
5480 /* Segment Type. */
5481 if ( !fUsable
5482 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5483 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5484 { /* likely */ }
5485 else
5486 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5487
5488 /* DPL. */
5489 if (!fUnrestrictedGuest)
5490 {
5491 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5492 { /* likely */ }
5493 else
5494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5495 }
5496 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5497 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5498 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5499 {
5500 if (uDpl == 0)
5501 { /* likely */ }
5502 else
5503 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5504 }
5505 }
5506 else
5507 {
5508 /* DS, ES, FS, GS. */
5509 if (fUsable)
5510 {
5511 /* Segment type. */
5512 if (uSegType & X86_SEL_TYPE_ACCESSED)
5513 { /* likely */ }
5514 else
5515 {
5516 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5517 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5518 }
5519
5520 if ( !(uSegType & X86_SEL_TYPE_CODE)
5521 || (uSegType & X86_SEL_TYPE_READ))
5522 { /* likely */ }
5523 else
5524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5525
5526 /* DPL. */
5527 if ( !fUnrestrictedGuest
5528 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5529 {
5530 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5531 { /* likely */ }
5532 else
5533 {
5534 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5536 }
5537 }
5538 }
5539 }
5540 }
5541
5542 /*
5543 * LDTR.
5544 */
5545 {
5546 CPUMSELREG Ldtr;
5547 Ldtr.Sel = pVmcs->GuestLdtr;
5548 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5549 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5550 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5551
5552 if (!Ldtr.Attr.n.u1Unusable)
5553 {
5554 /* Selector. */
5555 if (!(Ldtr.Sel & X86_SEL_LDT))
5556 { /* likely */ }
5557 else
5558 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5559
5560 /* Base. */
5561 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5562 {
5563 if (X86_IS_CANONICAL(Ldtr.u64Base))
5564 { /* likely */ }
5565 else
5566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5567 }
5568
5569 /* Attributes. */
5570 /* Reserved bits (bits 31:17 and bits 11:8). */
5571 if (!(Ldtr.Attr.u & 0xfffe0f00))
5572 { /* likely */ }
5573 else
5574 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5575
5576 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5577 { /* likely */ }
5578 else
5579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5580
5581 if (!Ldtr.Attr.n.u1DescType)
5582 { /* likely */ }
5583 else
5584 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5585
5586 if (Ldtr.Attr.n.u1Present)
5587 { /* likely */ }
5588 else
5589 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5590
5591 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5592 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5593 { /* likely */ }
5594 else
5595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5596 }
5597 }
5598
5599 /*
5600 * TR.
5601 */
5602 {
5603 CPUMSELREG Tr;
5604 Tr.Sel = pVmcs->GuestTr;
5605 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5606 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5607 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5608
5609 /* Selector. */
5610 if (!(Tr.Sel & X86_SEL_LDT))
5611 { /* likely */ }
5612 else
5613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5614
5615 /* Base. */
5616 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5617 {
5618 if (X86_IS_CANONICAL(Tr.u64Base))
5619 { /* likely */ }
5620 else
5621 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5622 }
5623
5624 /* Attributes. */
5625 /* Reserved bits (bits 31:17 and bits 11:8). */
5626 if (!(Tr.Attr.u & 0xfffe0f00))
5627 { /* likely */ }
5628 else
5629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5630
5631 if (!Tr.Attr.n.u1Unusable)
5632 { /* likely */ }
5633 else
5634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5635
5636 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5637 || ( !fGstInLongMode
5638 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5639 { /* likely */ }
5640 else
5641 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5642
5643 if (!Tr.Attr.n.u1DescType)
5644 { /* likely */ }
5645 else
5646 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5647
5648 if (Tr.Attr.n.u1Present)
5649 { /* likely */ }
5650 else
5651 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5652
5653 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5654 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5655 { /* likely */ }
5656 else
5657 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5658 }
5659
5660 NOREF(pszInstr);
5661 NOREF(pszFailure);
5662 return VINF_SUCCESS;
5663}
5664
5665
5666/**
5667 * Checks guest GDTR and IDTR as part of VM-entry.
5668 *
5669 * @param pVCpu The cross context virtual CPU structure.
5670 * @param pszInstr The VMX instruction name (for logging purposes).
5671 */
5672DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5673{
5674 /*
5675 * GDTR and IDTR.
5676 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5677 */
5678 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5679 const char *const pszFailure = "VM-exit";
5680
5681 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5682 {
5683 /* Base. */
5684 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5685 { /* likely */ }
5686 else
5687 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5688
5689 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5690 { /* likely */ }
5691 else
5692 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5693 }
5694
5695 /* Limit. */
5696 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5697 { /* likely */ }
5698 else
5699 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5700
5701 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5702 { /* likely */ }
5703 else
5704 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5705
5706 NOREF(pszInstr);
5707 NOREF(pszFailure);
5708 return VINF_SUCCESS;
5709}
5710
5711
5712/**
5713 * Checks guest RIP and RFLAGS as part of VM-entry.
5714 *
5715 * @param pVCpu The cross context virtual CPU structure.
5716 * @param pszInstr The VMX instruction name (for logging purposes).
5717 */
5718DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5719{
5720 /*
5721 * RIP and RFLAGS.
5722 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5723 */
5724 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5725 const char *const pszFailure = "VM-exit";
5726 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5727
5728 /* RIP. */
5729 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5730 {
5731 X86DESCATTR AttrCs;
5732 AttrCs.u = pVmcs->u32GuestCsAttr;
5733 if ( !fGstInLongMode
5734 || !AttrCs.n.u1Long)
5735 {
5736 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5737 { /* likely */ }
5738 else
5739 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5740 }
5741
5742 if ( fGstInLongMode
5743 && AttrCs.n.u1Long)
5744 {
5745 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5746 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5747 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5748 { /* likely */ }
5749 else
5750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5751 }
5752 }
5753
5754 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5755 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5756 : pVmcs->u64GuestRFlags.s.Lo;
5757 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5758 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5759 { /* likely */ }
5760 else
5761 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5762
5763 if (!(uGuestRFlags & X86_EFL_VM))
5764 { /* likely */ }
5765 else
5766 {
5767 if ( fGstInLongMode
5768 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5769 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5770 }
5771
5772 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5773 {
5774 if (uGuestRFlags & X86_EFL_IF)
5775 { /* likely */ }
5776 else
5777 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5778 }
5779
5780 NOREF(pszInstr);
5781 NOREF(pszFailure);
5782 return VINF_SUCCESS;
5783}
5784
5785
5786/**
5787 * Checks guest non-register state as part of VM-entry.
5788 *
5789 * @param pVCpu The cross context virtual CPU structure.
5790 * @param pszInstr The VMX instruction name (for logging purposes).
5791 */
5792DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5793{
5794 /*
5795 * Guest non-register state.
5796 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5797 */
5798 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5799 const char *const pszFailure = "VM-exit";
5800
5801 /*
5802 * Activity state.
5803 */
5804 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5805 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5806 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5807 { /* likely */ }
5808 else
5809 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5810
5811 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5812 if ( !AttrSs.n.u2Dpl
5813 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5814 { /* likely */ }
5815 else
5816 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5817
5818 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5819 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5820 {
5821 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5822 { /* likely */ }
5823 else
5824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5825 }
5826
5827 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5828 {
5829 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5830 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5831 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5832 switch (pVmcs->u32GuestActivityState)
5833 {
5834 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5835 {
5836 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5837 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5838 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5839 && ( uVector == X86_XCPT_DB
5840 || uVector == X86_XCPT_MC))
5841 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5842 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5843 { /* likely */ }
5844 else
5845 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5846 break;
5847 }
5848
5849 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5850 {
5851 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5852 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5853 && uVector == X86_XCPT_MC))
5854 { /* likely */ }
5855 else
5856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5857 break;
5858 }
5859
5860 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5861 default:
5862 break;
5863 }
5864 }
5865
5866 /*
5867 * Interruptibility state.
5868 */
5869 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5870 { /* likely */ }
5871 else
5872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5873
5874 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5875 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5876 { /* likely */ }
5877 else
5878 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5879
5880 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5881 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5882 { /* likely */ }
5883 else
5884 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5885
5886 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5887 {
5888 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5889 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5890 {
5891 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5892 { /* likely */ }
5893 else
5894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5895 }
5896 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5897 {
5898 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5899 { /* likely */ }
5900 else
5901 {
5902 /*
5903 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5904 * We update the Exit qualification only when blocking-by-STI is set
5905 * without blocking-by-MovSS being set. Although in practise it does not
5906 * make much difference since the order of checks are implementation defined.
5907 */
5908 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5909 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5910 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5911 }
5912
5913 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5914 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5915 { /* likely */ }
5916 else
5917 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5918 }
5919 }
5920
5921 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5922 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5923 { /* likely */ }
5924 else
5925 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5926
5927 /* We don't support SGX yet. So enclave-interruption must not be set. */
5928 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5929 { /* likely */ }
5930 else
5931 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5932
5933 /*
5934 * Pending debug exceptions.
5935 */
5936 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5937 ? pVmcs->u64GuestPendingDbgXcpts.u
5938 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5939 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5940 { /* likely */ }
5941 else
5942 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5943
5944 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5945 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5946 {
5947 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5948 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5949 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5950 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5951
5952 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5953 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5954 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5956 }
5957
5958 /* We don't support RTM (Real-time Transactional Memory) yet. */
5959 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5960 { /* likely */ }
5961 else
5962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5963
5964 /*
5965 * VMCS link pointer.
5966 */
5967 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5968 {
5969 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5970 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5971 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5972 { /* likely */ }
5973 else
5974 {
5975 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5976 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5977 }
5978
5979 /* Validate the address. */
5980 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5981 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5982 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5983 { /* likely */ }
5984 else
5985 {
5986 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5987 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5988 }
5989 }
5990
5991 NOREF(pszInstr);
5992 NOREF(pszFailure);
5993 return VINF_SUCCESS;
5994}
5995
5996
5997#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5998/**
5999 * Checks guest PDPTEs as part of VM-entry.
6000 *
6001 * @param pVCpu The cross context virtual CPU structure.
6002 * @param pszInstr The VMX instruction name (for logging purposes).
6003 */
6004static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6005{
6006 /*
6007 * Guest PDPTEs.
6008 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6009 */
6010 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6011 const char * const pszFailure = "VM-exit";
6012
6013 /*
6014 * When EPT is used, we need to validate the PAE PDPTEs provided in the VMCS.
6015 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6016 */
6017 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6018 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6019 {
6020 /* Get PDPTEs from the VMCS. */
6021 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6022 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6023 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6024 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6025 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6026
6027 /* Check validity of the PDPTEs. */
6028 if (PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]))
6029 { /* likely */ }
6030 else
6031 {
6032 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6033 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6034 }
6035 }
6036
6037 NOREF(pszFailure);
6038 NOREF(pszInstr);
6039 return VINF_SUCCESS;
6040}
6041#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6042
6043
6044/**
6045 * Checks guest-state as part of VM-entry.
6046 *
6047 * @returns VBox status code.
6048 * @param pVCpu The cross context virtual CPU structure.
6049 * @param pszInstr The VMX instruction name (for logging purposes).
6050 */
6051static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6052{
6053 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6054 if (RT_SUCCESS(rc))
6055 {
6056 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6057 if (RT_SUCCESS(rc))
6058 {
6059 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6060 if (RT_SUCCESS(rc))
6061 {
6062 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6063 if (RT_SUCCESS(rc))
6064 {
6065 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6066#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6067 if (RT_SUCCESS(rc))
6068 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6069#endif
6070 }
6071 }
6072 }
6073 }
6074 return rc;
6075}
6076
6077
6078/**
6079 * Checks host-state as part of VM-entry.
6080 *
6081 * @returns VBox status code.
6082 * @param pVCpu The cross context virtual CPU structure.
6083 * @param pszInstr The VMX instruction name (for logging purposes).
6084 */
6085static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6086{
6087 /*
6088 * Host Control Registers and MSRs.
6089 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6090 */
6091 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6092 const char * const pszFailure = "VMFail";
6093
6094 /* CR0 reserved bits. */
6095 {
6096 /* CR0 MB1 bits. */
6097 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
6098 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6099 { /* likely */ }
6100 else
6101 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6102
6103 /* CR0 MBZ bits. */
6104 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6105 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6106 { /* likely */ }
6107 else
6108 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6109 }
6110
6111 /* CR4 reserved bits. */
6112 {
6113 /* CR4 MB1 bits. */
6114 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6115 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6116 { /* likely */ }
6117 else
6118 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6119
6120 /* CR4 MBZ bits. */
6121 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6122 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6123 { /* likely */ }
6124 else
6125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6126 }
6127
6128 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6129 {
6130 /* CR3 reserved bits. */
6131 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6132 { /* likely */ }
6133 else
6134 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6135
6136 /* SYSENTER ESP and SYSENTER EIP. */
6137 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6138 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6139 { /* likely */ }
6140 else
6141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6142 }
6143
6144 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6145 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6146
6147 /* PAT MSR. */
6148 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6149 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6150 { /* likely */ }
6151 else
6152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6153
6154 /* EFER MSR. */
6155 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6156 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6157 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6158 {
6159 if (!(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6160 { /* likely */ }
6161 else
6162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6163
6164 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6165 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6166 if ( fHostInLongMode == fHostLma
6167 && fHostInLongMode == fHostLme)
6168 { /* likely */ }
6169 else
6170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6171 }
6172
6173 /*
6174 * Host Segment and Descriptor-Table Registers.
6175 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6176 */
6177 /* Selector RPL and TI. */
6178 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6179 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6180 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6181 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6182 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6183 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6184 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6185 { /* likely */ }
6186 else
6187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6188
6189 /* CS and TR selectors cannot be 0. */
6190 if ( pVmcs->HostCs
6191 && pVmcs->HostTr)
6192 { /* likely */ }
6193 else
6194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6195
6196 /* SS cannot be 0 if 32-bit host. */
6197 if ( fHostInLongMode
6198 || pVmcs->HostSs)
6199 { /* likely */ }
6200 else
6201 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6202
6203 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6204 {
6205 /* FS, GS, GDTR, IDTR, TR base address. */
6206 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6207 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6208 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6209 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6210 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6211 { /* likely */ }
6212 else
6213 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6214 }
6215
6216 /*
6217 * Host address-space size for 64-bit CPUs.
6218 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6219 */
6220 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6221 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6222 {
6223 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6224
6225 /* Logical processor in IA-32e mode. */
6226 if (fCpuInLongMode)
6227 {
6228 if (fHostInLongMode)
6229 {
6230 /* PAE must be set. */
6231 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6232 { /* likely */ }
6233 else
6234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6235
6236 /* RIP must be canonical. */
6237 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6238 { /* likely */ }
6239 else
6240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6241 }
6242 else
6243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6244 }
6245 else
6246 {
6247 /* Logical processor is outside IA-32e mode. */
6248 if ( !fGstInLongMode
6249 && !fHostInLongMode)
6250 {
6251 /* PCIDE should not be set. */
6252 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6253 { /* likely */ }
6254 else
6255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6256
6257 /* The high 32-bits of RIP MBZ. */
6258 if (!pVmcs->u64HostRip.s.Hi)
6259 { /* likely */ }
6260 else
6261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6262 }
6263 else
6264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6265 }
6266 }
6267 else
6268 {
6269 /* Host address-space size for 32-bit CPUs. */
6270 if ( !fGstInLongMode
6271 && !fHostInLongMode)
6272 { /* likely */ }
6273 else
6274 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6275 }
6276
6277 NOREF(pszInstr);
6278 NOREF(pszFailure);
6279 return VINF_SUCCESS;
6280}
6281
6282
6283#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6284/**
6285 * Checks the EPT pointer VMCS field as part of VM-entry.
6286 *
6287 * @returns VBox status code.
6288 * @param pVCpu The cross context virtual CPU structure.
6289 * @param uEptPtr The EPT pointer to check.
6290 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6291 * updated on success). Optional, can be NULL.
6292 */
6293static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6294{
6295 VMXVDIAG enmVmxDiag;
6296
6297 /* Reserved bits. */
6298 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6299 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6300 if (uEptPtr & fValidMask)
6301 {
6302 /* Memory Type. */
6303 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6304 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6305 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6306 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6307 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6308 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6309 {
6310 /*
6311 * Page walk length (PML4).
6312 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6313 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6314 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6315 */
6316 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6317 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6318 {
6319 /* Access and dirty bits support in EPT structures. */
6320 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6321 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6322 return VINF_SUCCESS;
6323
6324 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6325 }
6326 else
6327 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6328 }
6329 else
6330 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6331 }
6332 else
6333 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6334
6335 if (penmVmxDiag)
6336 *penmVmxDiag = enmVmxDiag;
6337 return VERR_VMX_VMENTRY_FAILED;
6338}
6339#endif
6340
6341
6342/**
6343 * Checks VMCS controls fields as part of VM-entry.
6344 *
6345 * @returns VBox status code.
6346 * @param pVCpu The cross context virtual CPU structure.
6347 * @param pszInstr The VMX instruction name (for logging purposes).
6348 *
6349 * @remarks This may update secondary-processor based VM-execution control fields
6350 * in the current VMCS if necessary.
6351 */
6352static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6353{
6354 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6355 const char * const pszFailure = "VMFail";
6356 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6357
6358 /*
6359 * VM-execution controls.
6360 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6361 */
6362 {
6363 /* Pin-based VM-execution controls. */
6364 {
6365 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6366 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6367 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6368 { /* likely */ }
6369 else
6370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6371
6372 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6373 { /* likely */ }
6374 else
6375 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6376 }
6377
6378 /* Processor-based VM-execution controls. */
6379 {
6380 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6381 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6382 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6383 { /* likely */ }
6384 else
6385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6386
6387 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6388 { /* likely */ }
6389 else
6390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6391 }
6392
6393 /* Secondary processor-based VM-execution controls. */
6394 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6395 {
6396 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6397 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6398 { /* likely */ }
6399 else
6400 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6401
6402 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6403 { /* likely */ }
6404 else
6405 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6406 }
6407 else if (pVmcs->u32ProcCtls2)
6408 {
6409 /*
6410 * If the "activate secondary controls" is clear, then the secondary processor-based VM-execution controls
6411 * is treated as 0.
6412 *
6413 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6414 *
6415 * Since this is a rather rare occurrence (only observed for a few VM-entries with Microsoft Hyper-V
6416 * enabled Windows Server 2008 R2 guest), it's not worth changing every place that reads this control to
6417 * also check the "activate secondary controls" bit. Instead, we temporarily save the guest programmed
6418 * control here, zero out the value the rest of our code uses and restore the guest programmed value
6419 * on VM-exit.
6420 */
6421 pVmcs->u32RestoreProcCtls2 = pVmcs->u32ProcCtls2;
6422 pVmcs->u32ProcCtls2 = 0;
6423 }
6424
6425 /* CR3-target count. */
6426 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6427 { /* likely */ }
6428 else
6429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6430
6431 /* I/O bitmaps physical addresses. */
6432 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6433 {
6434 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6435 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6436 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6437 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6438 { /* likely */ }
6439 else
6440 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6441
6442 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6443 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6444 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6445 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6446 { /* likely */ }
6447 else
6448 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6449 }
6450
6451 /* MSR bitmap physical address. */
6452 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6453 {
6454 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6455 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6456 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6457 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6458 { /* likely */ }
6459 else
6460 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6461 }
6462
6463 /* TPR shadow related controls. */
6464 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6465 {
6466 /* Virtual-APIC page physical address. */
6467 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6468 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6469 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6470 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6471 { /* likely */ }
6472 else
6473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6474
6475 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6476 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6477 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6478 { /* likely */ }
6479 else
6480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6481
6482 /* The rest done XXX document */
6483 }
6484 else
6485 {
6486 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6487 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6488 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6489 { /* likely */ }
6490 else
6491 {
6492 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6493 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6494 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6496 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6497 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6498 }
6499 }
6500
6501 /* NMI exiting and virtual-NMIs. */
6502 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6503 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6504 { /* likely */ }
6505 else
6506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6507
6508 /* Virtual-NMIs and NMI-window exiting. */
6509 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6510 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6511 { /* likely */ }
6512 else
6513 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6514
6515 /* Virtualize APIC accesses. */
6516 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6517 {
6518 /* APIC-access physical address. */
6519 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6520 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6521 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6522 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6523 { /* likely */ }
6524 else
6525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6526
6527 /*
6528 * Disallow APIC-access page and virtual-APIC page from being the same address.
6529 * Note! This is not an Intel requirement, but one imposed by our implementation.
6530 */
6531 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6532 * redirecting accesses between the APIC-access page and the virtual-APIC
6533 * page. If any nested hypervisor requires this, we can implement it later. */
6534 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6535 {
6536 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6537 if (GCPhysVirtApic != GCPhysApicAccess)
6538 { /* likely */ }
6539 else
6540 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6541 }
6542 }
6543
6544 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6545 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6546 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6547 { /* likely */ }
6548 else
6549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6550
6551 /* Virtual-interrupt delivery requires external interrupt exiting. */
6552 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6553 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6554 { /* likely */ }
6555 else
6556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6557
6558 /* VPID. */
6559 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6560 || pVmcs->u16Vpid != 0)
6561 { /* likely */ }
6562 else
6563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6564
6565#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6566 /* Extended-Page-Table Pointer (EPTP). */
6567 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6568 {
6569 VMXVDIAG enmVmxDiag;
6570 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6571 if (RT_SUCCESS(rc))
6572 { /* likely */ }
6573 else
6574 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6575 }
6576#else
6577 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6578 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6579#endif
6580 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6581 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6582 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6583 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6584 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6585
6586 /* VMCS shadowing. */
6587 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6588 {
6589 /* VMREAD-bitmap physical address. */
6590 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6591 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6592 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6593 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6594 { /* likely */ }
6595 else
6596 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6597
6598 /* VMWRITE-bitmap physical address. */
6599 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6600 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6601 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6602 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6603 { /* likely */ }
6604 else
6605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6606 }
6607 }
6608
6609 /*
6610 * VM-exit controls.
6611 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6612 */
6613 {
6614 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6615 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6616 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6617 { /* likely */ }
6618 else
6619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6620
6621 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6622 { /* likely */ }
6623 else
6624 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6625
6626 /* Save preemption timer without activating it. */
6627 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6628 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6629 { /* likely */ }
6630 else
6631 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6632
6633 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6634 if (pVmcs->u32ExitMsrStoreCount)
6635 {
6636 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6637 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6638 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6639 { /* likely */ }
6640 else
6641 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6642 }
6643
6644 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6645 if (pVmcs->u32ExitMsrLoadCount)
6646 {
6647 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6648 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6649 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6650 { /* likely */ }
6651 else
6652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6653 }
6654 }
6655
6656 /*
6657 * VM-entry controls.
6658 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6659 */
6660 {
6661 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6662 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6663 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6664 { /* likely */ }
6665 else
6666 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6667
6668 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6669 { /* likely */ }
6670 else
6671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6672
6673 /* Event injection. */
6674 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6675 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6676 {
6677 /* Type and vector. */
6678 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6679 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6680 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6681 if ( !uRsvd
6682 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6683 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6684 { /* likely */ }
6685 else
6686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6687
6688 /* Exception error code. */
6689 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6690 {
6691 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6692 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6693 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6694 { /* likely */ }
6695 else
6696 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6697
6698 /* Exceptions that provide an error code. */
6699 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6700 && ( uVector == X86_XCPT_DF
6701 || uVector == X86_XCPT_TS
6702 || uVector == X86_XCPT_NP
6703 || uVector == X86_XCPT_SS
6704 || uVector == X86_XCPT_GP
6705 || uVector == X86_XCPT_PF
6706 || uVector == X86_XCPT_AC))
6707 { /* likely */ }
6708 else
6709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6710
6711 /* Exception error-code reserved bits. */
6712 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6713 { /* likely */ }
6714 else
6715 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6716
6717 /* Injecting a software interrupt, software exception or privileged software exception. */
6718 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6719 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6720 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6721 {
6722 /* Instruction length must be in the range 0-15. */
6723 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6724 { /* likely */ }
6725 else
6726 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6727
6728 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6729 if ( pVmcs->u32EntryInstrLen != 0
6730 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6731 { /* likely */ }
6732 else
6733 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6734 }
6735 }
6736 }
6737
6738 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6739 if (pVmcs->u32EntryMsrLoadCount)
6740 {
6741 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6742 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6743 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6744 { /* likely */ }
6745 else
6746 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6747 }
6748
6749 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6750 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6751 }
6752
6753 NOREF(pszInstr);
6754 NOREF(pszFailure);
6755 return VINF_SUCCESS;
6756}
6757
6758
6759/**
6760 * Loads the guest control registers, debug register and some MSRs as part of
6761 * VM-entry.
6762 *
6763 * @param pVCpu The cross context virtual CPU structure.
6764 */
6765static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6766{
6767 /*
6768 * Load guest control registers, debug registers and MSRs.
6769 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6770 */
6771 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6772
6773 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6774 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6775 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6776 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6777 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6778 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6779
6780 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6781 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6782
6783 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6784 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6785 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6786
6787 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6788 {
6789 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6790
6791 /* EFER MSR. */
6792 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6793 {
6794 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6795 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6796 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6797 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6798 if (fGstInLongMode)
6799 {
6800 /* If the nested-guest is in long mode, LMA and LME are both set. */
6801 Assert(fGstPaging);
6802 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6803 }
6804 else
6805 {
6806 /*
6807 * If the nested-guest is outside long mode:
6808 * - With paging: LMA is cleared, LME is cleared.
6809 * - Without paging: LMA is cleared, LME is left unmodified.
6810 */
6811 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6812 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6813 }
6814 }
6815 /* else: see below. */
6816 }
6817
6818 /* PAT MSR. */
6819 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6820 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6821
6822 /* EFER MSR. */
6823 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6824 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6825
6826 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6827 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6828
6829 /* We don't support IA32_BNDCFGS MSR yet. */
6830 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6831
6832 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6833}
6834
6835
6836/**
6837 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6838 *
6839 * @param pVCpu The cross context virtual CPU structure.
6840 */
6841static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6842{
6843 /*
6844 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6845 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6846 */
6847 /* CS, SS, ES, DS, FS, GS. */
6848 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6849 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6850 {
6851 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6852 CPUMSELREG VmcsSelReg;
6853 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6854 AssertRC(rc); NOREF(rc);
6855 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6856 {
6857 pGstSelReg->Sel = VmcsSelReg.Sel;
6858 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6859 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6860 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6861 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6862 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6863 }
6864 else
6865 {
6866 pGstSelReg->Sel = VmcsSelReg.Sel;
6867 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6868 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6869 switch (iSegReg)
6870 {
6871 case X86_SREG_CS:
6872 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6873 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6874 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6875 break;
6876
6877 case X86_SREG_SS:
6878 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6879 pGstSelReg->u32Limit = 0;
6880 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6881 break;
6882
6883 case X86_SREG_ES:
6884 case X86_SREG_DS:
6885 pGstSelReg->u64Base = 0;
6886 pGstSelReg->u32Limit = 0;
6887 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6888 break;
6889
6890 case X86_SREG_FS:
6891 case X86_SREG_GS:
6892 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6893 pGstSelReg->u32Limit = 0;
6894 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6895 break;
6896 }
6897 Assert(pGstSelReg->Attr.n.u1Unusable);
6898 }
6899 }
6900
6901 /* LDTR. */
6902 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6903 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6904 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6905 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6906 {
6907 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6908 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6909 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6910 }
6911 else
6912 {
6913 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6914 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6915 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6916 }
6917
6918 /* TR. */
6919 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6920 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6921 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6922 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6923 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6924 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6925 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6926
6927 /* GDTR. */
6928 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6929 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6930
6931 /* IDTR. */
6932 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6933 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6934}
6935
6936
6937/**
6938 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6939 *
6940 * @returns VBox status code.
6941 * @param pVCpu The cross context virtual CPU structure.
6942 * @param pszInstr The VMX instruction name (for logging purposes).
6943 */
6944static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6945{
6946 /*
6947 * Load guest MSRs.
6948 * See Intel spec. 26.4 "Loading MSRs".
6949 */
6950 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6951 const char *const pszFailure = "VM-exit";
6952
6953 /*
6954 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6955 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6956 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6957 */
6958 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6959 if (!cMsrs)
6960 return VINF_SUCCESS;
6961
6962 /*
6963 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6964 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6965 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6966 */
6967 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6968 if (fIsMsrCountValid)
6969 { /* likely */ }
6970 else
6971 {
6972 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6973 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6974 }
6975
6976 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6977 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6978 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6979 if (RT_SUCCESS(rc))
6980 {
6981 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6982 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6983 {
6984 if ( !pMsr->u32Reserved
6985 && pMsr->u32Msr != MSR_K8_FS_BASE
6986 && pMsr->u32Msr != MSR_K8_GS_BASE
6987 && pMsr->u32Msr != MSR_K6_EFER
6988 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6989 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6990 {
6991 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6992 if (rcStrict == VINF_SUCCESS)
6993 continue;
6994
6995 /*
6996 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6997 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6998 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6999 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7000 * MSR in ring-0 if possible, or come up with a better, generic solution.
7001 */
7002 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7003 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7004 ? kVmxVDiag_Vmentry_MsrLoadRing3
7005 : kVmxVDiag_Vmentry_MsrLoad;
7006 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7007 }
7008 else
7009 {
7010 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7011 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7012 }
7013 }
7014 }
7015 else
7016 {
7017 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7018 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7019 }
7020
7021 NOREF(pszInstr);
7022 NOREF(pszFailure);
7023 return VINF_SUCCESS;
7024}
7025
7026
7027/**
7028 * Loads the guest-state non-register state as part of VM-entry.
7029 *
7030 * @returns VBox status code.
7031 * @param pVCpu The cross context virtual CPU structure.
7032 * @param pszInstr The VMX instruction name (for logging purposes).
7033 *
7034 * @remarks This must be called only after loading the nested-guest register state
7035 * (especially nested-guest RIP).
7036 */
7037static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7038{
7039 /*
7040 * Load guest non-register state.
7041 * See Intel spec. 26.6 "Special Features of VM Entry"
7042 */
7043 const char *const pszFailure = "VM-exit";
7044 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7045
7046 /*
7047 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7048 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7049 *
7050 * See Intel spec. 26.6.1 "Interruptibility State".
7051 */
7052 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7053 if ( !fEntryVectoring
7054 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7055 CPUMSetInInterruptShadowEx(&pVCpu->cpum.GstCtx, pVmcs->u64GuestRip.u);
7056 else
7057 Assert(!CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx));
7058
7059 /* NMI blocking. */
7060 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7061 {
7062 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7063 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7064 else
7065 {
7066 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7067 CPUMSetInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
7068 }
7069 }
7070 else
7071 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7072
7073 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7074
7075 /*
7076 * Set PGM's copy of the EPT pointer.
7077 * The EPTP has already been validated while checking guest state.
7078 *
7079 * It is important to do this prior to mapping PAE PDPTEs (below).
7080 */
7081 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7082 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7083
7084 /*
7085 * Load the guest's PAE PDPTEs.
7086 */
7087 if (!iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7088 {
7089 /*
7090 * When PAE paging is not used we clear the PAE PDPTEs for safety
7091 * in case we might be switching from a PAE host to a non-PAE guest.
7092 */
7093 pVCpu->cpum.GstCtx.aPaePdpes[0].u = 0;
7094 pVCpu->cpum.GstCtx.aPaePdpes[1].u = 0;
7095 pVCpu->cpum.GstCtx.aPaePdpes[2].u = 0;
7096 pVCpu->cpum.GstCtx.aPaePdpes[3].u = 0;
7097 }
7098 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7099 {
7100 /*
7101 * With EPT and the nested-guest using PAE paging, we've already validated the PAE PDPTEs
7102 * while checking the guest state. We can load them into the nested-guest CPU state now.
7103 * They'll later be used while mapping CR3 and the PAE PDPTEs.
7104 */
7105 pVCpu->cpum.GstCtx.aPaePdpes[0].u = pVmcs->u64GuestPdpte0.u;
7106 pVCpu->cpum.GstCtx.aPaePdpes[1].u = pVmcs->u64GuestPdpte1.u;
7107 pVCpu->cpum.GstCtx.aPaePdpes[2].u = pVmcs->u64GuestPdpte2.u;
7108 pVCpu->cpum.GstCtx.aPaePdpes[3].u = pVmcs->u64GuestPdpte3.u;
7109 }
7110 else
7111 {
7112 /*
7113 * Without EPT and the nested-guest using PAE paging, we must load the PAE PDPTEs
7114 * referenced by CR3. This involves loading (and mapping) CR3 and validating them now.
7115 */
7116 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7117 if (RT_SUCCESS(rc))
7118 { /* likely */ }
7119 else
7120 {
7121 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7122 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7123 }
7124 }
7125
7126 /* VPID is irrelevant. We don't support VPID yet. */
7127
7128 /* Clear address-range monitoring. */
7129 EMMonitorWaitClear(pVCpu);
7130
7131 return VINF_SUCCESS;
7132}
7133
7134
7135/**
7136 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7137 *
7138 * @param pVCpu The cross context virtual CPU structure.
7139 * @param pszInstr The VMX instruction name (for logging purposes).
7140 *
7141 * @remarks This assumes various VMCS related data structure pointers have already
7142 * been verified prior to calling this function.
7143 */
7144static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7145{
7146 const char *const pszFailure = "VM-exit";
7147 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7148
7149 /*
7150 * Virtualize APIC accesses.
7151 */
7152 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7153 {
7154 /* APIC-access physical address. */
7155 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7156
7157 /*
7158 * Register the handler for the APIC-access page.
7159 *
7160 * We don't deregister the APIC-access page handler during the VM-exit as a different
7161 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7162 *
7163 * We leave the page registered until the first access that happens outside VMX non-root
7164 * mode. Guest software is allowed to access structures such as the APIC-access page
7165 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7166 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7167 *
7168 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7169 */
7170 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
7171 {
7172 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7173 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess | X86_PAGE_4K_OFFSET_MASK,
7174 pVM->iem.s.hVmxApicAccessPage, 0 /*uUser*/, NULL /*pszDesc*/);
7175 if (RT_SUCCESS(rc))
7176 { /* likely */ }
7177 else
7178 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7179 }
7180 }
7181
7182 /*
7183 * VMCS shadowing.
7184 */
7185 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7186 {
7187 /* Read the VMREAD-bitmap. */
7188 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7189 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7190 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7191 if (RT_SUCCESS(rc))
7192 { /* likely */ }
7193 else
7194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7195
7196 /* Read the VMWRITE-bitmap. */
7197 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7198 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7199 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7200 if (RT_SUCCESS(rc))
7201 { /* likely */ }
7202 else
7203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7204 }
7205
7206 /*
7207 * I/O bitmaps.
7208 */
7209 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7210 {
7211 /* Read the IO bitmap A. */
7212 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7213 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7214 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7215 if (RT_SUCCESS(rc))
7216 { /* likely */ }
7217 else
7218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7219
7220 /* Read the IO bitmap B. */
7221 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7222 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7223 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7224 if (RT_SUCCESS(rc))
7225 { /* likely */ }
7226 else
7227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7228 }
7229
7230 /*
7231 * TPR shadow and Virtual-APIC page.
7232 */
7233 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7234 {
7235 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7236 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7237 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7238 {
7239 /* Read the VTPR from the virtual-APIC page. */
7240 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7241 uint8_t u8VTpr;
7242 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7243 if (RT_SUCCESS(rc))
7244 { /* likely */ }
7245 else
7246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7247
7248 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7249 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7250 { /* likely */ }
7251 else
7252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7253 }
7254 }
7255
7256 /*
7257 * VMCS link pointer.
7258 */
7259 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7260 {
7261 /* Read the VMCS-link pointer from guest memory. */
7262 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7263 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7264 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7265 if (RT_SUCCESS(rc))
7266 { /* likely */ }
7267 else
7268 {
7269 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7271 }
7272
7273 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7274 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7275 { /* likely */ }
7276 else
7277 {
7278 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7280 }
7281
7282 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7283 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7284 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7285 { /* likely */ }
7286 else
7287 {
7288 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7289 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7290 }
7291
7292 /* Update our cache of the guest physical address of the shadow VMCS. */
7293 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7294 }
7295
7296 /*
7297 * MSR bitmap.
7298 */
7299 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7300 {
7301 /* Read the MSR bitmap. */
7302 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7303 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7304 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7305 if (RT_SUCCESS(rc))
7306 { /* likely */ }
7307 else
7308 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7309 }
7310
7311 NOREF(pszFailure);
7312 NOREF(pszInstr);
7313 return VINF_SUCCESS;
7314}
7315
7316
7317/**
7318 * Loads the guest-state as part of VM-entry.
7319 *
7320 * @returns VBox status code.
7321 * @param pVCpu The cross context virtual CPU structure.
7322 * @param pszInstr The VMX instruction name (for logging purposes).
7323 *
7324 * @remarks This must be done after all the necessary steps prior to loading of
7325 * guest-state (e.g. checking various VMCS state).
7326 */
7327static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7328{
7329 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7330 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7331
7332 /* Load guest segment registers. */
7333 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7334
7335 /*
7336 * Load guest RIP, RSP and RFLAGS.
7337 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7338 */
7339 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7340 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7341 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7342 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7343
7344 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7345 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7346 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7347
7348 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7349 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7350 if (rc == VINF_SUCCESS)
7351 { /* likely */ }
7352 else
7353 return rc;
7354
7355 /* Load VMX related structures and state referenced by the VMCS. */
7356 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7357 if (rc == VINF_SUCCESS)
7358 { /* likely */ }
7359 else
7360 return rc;
7361
7362 NOREF(pszInstr);
7363 return VINF_SUCCESS;
7364}
7365
7366
7367/**
7368 * Returns whether there are is a pending debug exception on VM-entry.
7369 *
7370 * @param pVCpu The cross context virtual CPU structure.
7371 * @param pszInstr The VMX instruction name (for logging purposes).
7372 */
7373static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7374{
7375 /*
7376 * Pending debug exceptions.
7377 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7378 */
7379 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7380 Assert(pVmcs);
7381
7382 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7383 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7384 if (fPendingDbgXcpt)
7385 {
7386 uint8_t uEntryIntInfoType;
7387 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7388 if (fEntryVectoring)
7389 {
7390 switch (uEntryIntInfoType)
7391 {
7392 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7393 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7394 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7395 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7396 fPendingDbgXcpt = false;
7397 break;
7398
7399 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7400 {
7401 /*
7402 * Whether the pending debug exception for software exceptions other than
7403 * #BP and #OF is delivered after injecting the exception or is discard
7404 * is CPU implementation specific. We will discard them (easier).
7405 */
7406 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7407 if ( uVector != X86_XCPT_BP
7408 && uVector != X86_XCPT_OF)
7409 fPendingDbgXcpt = false;
7410 RT_FALL_THRU();
7411 }
7412 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7413 {
7414 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7415 fPendingDbgXcpt = false;
7416 break;
7417 }
7418 }
7419 }
7420 else
7421 {
7422 /*
7423 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7424 * pending debug exception is held pending or is discarded is CPU implementation
7425 * specific. We will discard them (easier).
7426 */
7427 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7428 fPendingDbgXcpt = false;
7429
7430 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7431 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7432 fPendingDbgXcpt = false;
7433 }
7434 }
7435
7436 NOREF(pszInstr);
7437 return fPendingDbgXcpt;
7438}
7439
7440
7441/**
7442 * Set up the monitor-trap flag (MTF).
7443 *
7444 * @param pVCpu The cross context virtual CPU structure.
7445 * @param pszInstr The VMX instruction name (for logging purposes).
7446 */
7447static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7448{
7449 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7450 Assert(pVmcs);
7451 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7452 {
7453 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7454 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7455 }
7456 else
7457 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7458 NOREF(pszInstr);
7459}
7460
7461
7462/**
7463 * Sets up NMI-window exiting.
7464 *
7465 * @param pVCpu The cross context virtual CPU structure.
7466 * @param pszInstr The VMX instruction name (for logging purposes).
7467 */
7468static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7469{
7470 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7471 Assert(pVmcs);
7472 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7473 {
7474 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7475 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7476 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7477 }
7478 else
7479 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7480 NOREF(pszInstr);
7481}
7482
7483
7484/**
7485 * Sets up interrupt-window exiting.
7486 *
7487 * @param pVCpu The cross context virtual CPU structure.
7488 * @param pszInstr The VMX instruction name (for logging purposes).
7489 */
7490static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7491{
7492 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7493 Assert(pVmcs);
7494 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7495 {
7496 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7497 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7498 }
7499 else
7500 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7501 NOREF(pszInstr);
7502}
7503
7504
7505/**
7506 * Set up the VMX-preemption timer.
7507 *
7508 * @param pVCpu The cross context virtual CPU structure.
7509 * @param pszInstr The VMX instruction name (for logging purposes).
7510 */
7511static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7512{
7513 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7514 Assert(pVmcs);
7515 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7516 {
7517 /*
7518 * If the timer is 0, we must cause a VM-exit before executing the first
7519 * nested-guest instruction. So we can flag as though the timer has already
7520 * expired and we will check and cause a VM-exit at the right priority elsewhere
7521 * in the code.
7522 */
7523 uint64_t uEntryTick;
7524 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7525 if (uPreemptTimer)
7526 {
7527 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7528 AssertRC(rc);
7529 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7530 }
7531 else
7532 {
7533 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7534 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7535 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7536 }
7537
7538 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7539 }
7540 else
7541 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7542
7543 NOREF(pszInstr);
7544}
7545
7546
7547/**
7548 * Injects an event using TRPM given a VM-entry interruption info and related
7549 * fields.
7550 *
7551 * @param pVCpu The cross context virtual CPU structure.
7552 * @param pszInstr The VMX instruction name (for logging purposes).
7553 * @param uEntryIntInfo The VM-entry interruption info.
7554 * @param uErrCode The error code associated with the event if any.
7555 * @param cbInstr The VM-entry instruction length (for software
7556 * interrupts and software exceptions). Pass 0
7557 * otherwise.
7558 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7559 */
7560static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7561 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7562{
7563 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7564
7565 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7566 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7567 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7568
7569 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7570
7571 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7572 AssertRC(rc);
7573 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7574
7575 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7576 {
7577 TRPMSetErrorCode(pVCpu, uErrCode);
7578 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7579 }
7580
7581 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7582 {
7583 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7584 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7585 }
7586 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7587 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7588 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7589 {
7590 TRPMSetInstrLength(pVCpu, cbInstr);
7591 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7592 }
7593
7594 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7595 {
7596 TRPMSetTrapDueToIcebp(pVCpu);
7597 Log(("%s: Injecting: icebp\n", pszInstr));
7598 }
7599
7600 NOREF(pszInstr);
7601}
7602
7603
7604/**
7605 * Performs event injection (if any) as part of VM-entry.
7606 *
7607 * @param pVCpu The cross context virtual CPU structure.
7608 * @param pszInstr The VMX instruction name (for logging purposes).
7609 */
7610static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7611{
7612 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7613
7614 /*
7615 * Inject events.
7616 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7617 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7618 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7619 * the actually delivery of this event.
7620 *
7621 * See Intel spec. 26.5 "Event Injection".
7622 */
7623 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7624 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7625
7626 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7627 if (fEntryIntInfoValid)
7628 {
7629 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7630 {
7631 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7632 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7633 }
7634 else
7635 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7636 pVCpu->cpum.GstCtx.cr2);
7637
7638 /*
7639 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7640 *
7641 * However, we do it here on VM-entry as well because while it isn't visible to guest
7642 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7643 * execution using hardware-assisted VMX, it will not try to inject the event again.
7644 *
7645 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7646 */
7647 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7648 }
7649 else
7650 {
7651 /*
7652 * Inject any pending guest debug exception.
7653 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7654 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7655 */
7656 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7657 if (fPendingDbgXcpt)
7658 {
7659 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7660 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7661 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7662 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7663 0 /* GCPtrFaultAddress */);
7664 }
7665 }
7666
7667 NOREF(pszInstr);
7668}
7669
7670
7671/**
7672 * Initializes all read-only VMCS fields as part of VM-entry.
7673 *
7674 * @param pVCpu The cross context virtual CPU structure.
7675 */
7676static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7677{
7678 /*
7679 * Any VMCS field which we do not establish on every VM-exit but may potentially
7680 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7681 * specified to be undefined, needs to be initialized here.
7682 *
7683 * Thus, it is especially important to clear the Exit qualification field
7684 * since it must be zero for VM-exits where it is not used. Similarly, the
7685 * VM-exit interruption information field's valid bit needs to be cleared for
7686 * the same reasons.
7687 */
7688 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7689 Assert(pVmcs);
7690
7691 /* 16-bit (none currently). */
7692 /* 32-bit. */
7693 pVmcs->u32RoVmInstrError = 0;
7694 pVmcs->u32RoExitReason = 0;
7695 pVmcs->u32RoExitIntInfo = 0;
7696 pVmcs->u32RoExitIntErrCode = 0;
7697 pVmcs->u32RoIdtVectoringInfo = 0;
7698 pVmcs->u32RoIdtVectoringErrCode = 0;
7699 pVmcs->u32RoExitInstrLen = 0;
7700 pVmcs->u32RoExitInstrInfo = 0;
7701
7702 /* 64-bit. */
7703 pVmcs->u64RoGuestPhysAddr.u = 0;
7704
7705 /* Natural-width. */
7706 pVmcs->u64RoExitQual.u = 0;
7707 pVmcs->u64RoIoRcx.u = 0;
7708 pVmcs->u64RoIoRsi.u = 0;
7709 pVmcs->u64RoIoRdi.u = 0;
7710 pVmcs->u64RoIoRip.u = 0;
7711 pVmcs->u64RoGuestLinearAddr.u = 0;
7712}
7713
7714
7715/**
7716 * VMLAUNCH/VMRESUME instruction execution worker.
7717 *
7718 * @returns Strict VBox status code.
7719 * @param pVCpu The cross context virtual CPU structure.
7720 * @param cbInstr The instruction length in bytes.
7721 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7722 * VMXINSTRID_VMRESUME).
7723 *
7724 * @remarks Common VMX instruction checks are already expected to by the caller,
7725 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7726 */
7727static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7728{
7729# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7730 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7731 return VINF_EM_RAW_EMULATE_INSTR;
7732# else
7733 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7734 || uInstrId == VMXINSTRID_VMRESUME);
7735 const char * const pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7736
7737 /* Nested-guest intercept. */
7738 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7739 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7740
7741 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7742
7743 /*
7744 * Basic VM-entry checks.
7745 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7746 * The checks following that do not have to follow a specific order.
7747 *
7748 * See Intel spec. 26.1 "Basic VM-entry Checks".
7749 */
7750
7751 /* CPL. */
7752 if (pVCpu->iem.s.uCpl == 0)
7753 { /* likely */ }
7754 else
7755 {
7756 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7757 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7758 return iemRaiseGeneralProtectionFault0(pVCpu);
7759 }
7760
7761 /* Current VMCS valid. */
7762 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7763 { /* likely */ }
7764 else
7765 {
7766 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7767 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7768 iemVmxVmFailInvalid(pVCpu);
7769 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7770 }
7771
7772 /* Current VMCS is not a shadow VMCS. */
7773 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7774 { /* likely */ }
7775 else
7776 {
7777 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7778 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7779 iemVmxVmFailInvalid(pVCpu);
7780 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7781 }
7782
7783 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7784 * use block-by-STI here which is not quite correct. */
7785 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
7786 { /* likely */ }
7787 else
7788 {
7789 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7790 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7791 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7792 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7793 }
7794
7795 if (uInstrId == VMXINSTRID_VMLAUNCH)
7796 {
7797 /* VMLAUNCH with non-clear VMCS. */
7798 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7799 { /* likely */ }
7800 else
7801 {
7802 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7803 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7804 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7805 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7806 }
7807 }
7808 else
7809 {
7810 /* VMRESUME with non-launched VMCS. */
7811 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7812 { /* likely */ }
7813 else
7814 {
7815 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7816 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7817 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7818 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7819 }
7820 }
7821
7822 /*
7823 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7824 * while entering VMX non-root mode. We do some of this while checking VM-execution
7825 * controls. The nested hypervisor should not make assumptions and cannot expect
7826 * predictable behavior if changes to these structures are made in guest memory while
7827 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7828 * modify them anyway as we cache them in host memory.
7829 *
7830 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7831 */
7832 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7833
7834 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7835 if (RT_SUCCESS(rc))
7836 {
7837 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7838 if (RT_SUCCESS(rc))
7839 {
7840 /*
7841 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7842 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7843 * ones that may occur during VM-entry below).
7844 */
7845 iemVmxVmentryInitReadOnlyFields(pVCpu);
7846
7847 /*
7848 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7849 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7850 * VM-exit when required.
7851 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7852 */
7853 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7854
7855 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7856 Assert(pVmcs);
7857
7858 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7859 if (RT_SUCCESS(rc))
7860 {
7861 /*
7862 * We've now entered nested-guest execution.
7863 *
7864 * It is important do this prior to loading the guest state because
7865 * as part of loading the guest state, PGM (and perhaps other components
7866 * in the future) relies on detecting whether VMX non-root mode has been
7867 * entered.
7868 */
7869 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7870
7871 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7872 if (RT_SUCCESS(rc))
7873 {
7874 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7875 if (RT_SUCCESS(rc))
7876 {
7877 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7878
7879 /* VMLAUNCH instruction must update the VMCS launch state. */
7880 if (uInstrId == VMXINSTRID_VMLAUNCH)
7881 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7882
7883 /* Perform the VMX transition (PGM updates). */
7884 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7885 if (rcStrict == VINF_SUCCESS)
7886 { /* likely */ }
7887 else if (RT_SUCCESS(rcStrict))
7888 {
7889 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7890 VBOXSTRICTRC_VAL(rcStrict)));
7891 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7892 }
7893 else
7894 {
7895 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7896 return rcStrict;
7897 }
7898
7899 /* Paranoia. */
7900 Assert(rcStrict == VINF_SUCCESS);
7901
7902 /*
7903 * The priority of potential VM-exits during VM-entry is important.
7904 * The priorities of VM-exits and events are listed from highest
7905 * to lowest as follows:
7906 *
7907 * 1. Event injection.
7908 * 2. Trap on task-switch (T flag set in TSS).
7909 * 3. TPR below threshold / APIC-write.
7910 * 4. SMI, INIT.
7911 * 5. MTF exit.
7912 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7913 * 7. VMX-preemption timer.
7914 * 9. NMI-window exit.
7915 * 10. NMI injection.
7916 * 11. Interrupt-window exit.
7917 * 12. Virtual-interrupt injection.
7918 * 13. Interrupt injection.
7919 * 14. Process next instruction (fetch, decode, execute).
7920 */
7921
7922 /* Setup VMX-preemption timer. */
7923 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7924
7925 /* Setup monitor-trap flag. */
7926 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7927
7928 /* Setup NMI-window exiting. */
7929 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7930
7931 /* Setup interrupt-window exiting. */
7932 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7933
7934 /*
7935 * Inject any event that the nested hypervisor wants to inject.
7936 * Note! We cannot immediately perform the event injection here as we may have
7937 * pending PGM operations to perform due to switching page tables and/or
7938 * mode.
7939 */
7940 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7941
7942# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7943 /* Reschedule to IEM-only execution of the nested-guest. */
7944 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7945 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7946 if (rcSched != VINF_SUCCESS)
7947 iemSetPassUpStatus(pVCpu, rcSched);
7948# endif
7949
7950 /* Finally, done. */
7951 Log2(("vmentry: %s: cs:rip=%04x:%08RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7952 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7953 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7954 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7955 return VINF_SUCCESS;
7956 }
7957 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7958 }
7959 }
7960 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7961 }
7962
7963 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7964 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7965 }
7966
7967 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7968 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7969# endif
7970}
7971
7972
7973/**
7974 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7975 *
7976 * @returns Strict VBox status code.
7977 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7978 * @param cbInstr The instruction length in bytes.
7979 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7980 * VMXINSTRID_VMRESUME).
7981 * @thread EMT(pVCpu)
7982 */
7983VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7984{
7985 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7986 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7987
7988 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7989 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7990 Assert(!pVCpu->iem.s.cActiveMappings);
7991 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
7992}
7993
7994
7995/**
7996 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7997 * (causes a VM-exit) or not.
7998 *
7999 * @returns @c true if the instruction is intercepted, @c false otherwise.
8000 * @param pVCpu The cross context virtual CPU structure.
8001 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
8002 * VMX_EXIT_WRMSR).
8003 * @param idMsr The MSR.
8004 */
8005bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
8006{
8007 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
8008 Assert( uExitReason == VMX_EXIT_RDMSR
8009 || uExitReason == VMX_EXIT_WRMSR);
8010
8011 /* Consult the MSR bitmap if the feature is supported. */
8012 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
8013 Assert(pVmcs);
8014 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
8015 {
8016 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
8017 if (uExitReason == VMX_EXIT_RDMSR)
8018 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
8019 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
8020 }
8021
8022 /* Without MSR bitmaps, all MSR accesses are intercepted. */
8023 return true;
8024}
8025
8026
8027/**
8028 * VMREAD instruction execution worker that does not perform any validation checks.
8029 *
8030 * Callers are expected to have performed the necessary checks and to ensure the
8031 * VMREAD will succeed.
8032 *
8033 * @param pVmcs Pointer to the virtual VMCS.
8034 * @param pu64Dst Where to write the VMCS value.
8035 * @param u64VmcsField The VMCS field.
8036 *
8037 * @remarks May be called with interrupts disabled.
8038 */
8039static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8040{
8041 VMXVMCSFIELD VmcsField;
8042 VmcsField.u = u64VmcsField;
8043 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8044 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8045 uint8_t const uWidthType = (uWidth << 2) | uType;
8046 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8047 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8048 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8049 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8050 uWidth, uType, uIndex, uIndex));
8051 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8052
8053 /*
8054 * Read the VMCS component based on the field's effective width.
8055 *
8056 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8057 * indicates high bits (little endian).
8058 *
8059 * Note! The caller is responsible to trim the result and update registers
8060 * or memory locations are required. Here we just zero-extend to the largest
8061 * type (i.e. 64-bits).
8062 */
8063 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8064 uint8_t const *pbField = pbVmcs + offField;
8065 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8066 switch (uEffWidth)
8067 {
8068 case VMX_VMCSFIELD_WIDTH_64BIT:
8069 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8070 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8071 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8072 }
8073}
8074
8075
8076/**
8077 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8078 *
8079 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8080 * are performed. Bounds checks are strict builds only.
8081 *
8082 * @param pVmcs Pointer to the virtual VMCS.
8083 * @param u64VmcsField The VMCS field.
8084 * @param pu64Dst Where to store the VMCS value.
8085 *
8086 * @remarks May be called with interrupts disabled.
8087 * @todo This should probably be moved to CPUM someday.
8088 */
8089VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8090{
8091 AssertPtr(pVmcs);
8092 AssertPtr(pu64Dst);
8093 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8094}
8095
8096
8097/**
8098 * VMREAD common (memory/register) instruction execution worker.
8099 *
8100 * @returns Strict VBox status code.
8101 * @param pVCpu The cross context virtual CPU structure.
8102 * @param cbInstr The instruction length in bytes.
8103 * @param pu64Dst Where to write the VMCS value (only updated when
8104 * VINF_SUCCESS is returned).
8105 * @param u64VmcsField The VMCS field.
8106 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8107 * NULL.
8108 */
8109static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8110 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8111{
8112 /* Nested-guest intercept. */
8113 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8114 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8115 {
8116 if (pExitInfo)
8117 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8118 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8119 }
8120
8121 /* CPL. */
8122 if (pVCpu->iem.s.uCpl == 0)
8123 { /* likely */ }
8124 else
8125 {
8126 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8127 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8128 return iemRaiseGeneralProtectionFault0(pVCpu);
8129 }
8130
8131 pVCpu->iem.s.cPotentialExits++;
8132
8133 /* VMCS pointer in root mode. */
8134 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8135 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8136 { /* likely */ }
8137 else
8138 {
8139 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8140 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8141 iemVmxVmFailInvalid(pVCpu);
8142 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8143 }
8144
8145 /* VMCS-link pointer in non-root mode. */
8146 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8147 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8148 { /* likely */ }
8149 else
8150 {
8151 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8152 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8153 iemVmxVmFailInvalid(pVCpu);
8154 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8155 }
8156
8157 /* Supported VMCS field. */
8158 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8159 { /* likely */ }
8160 else
8161 {
8162 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8163 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8164 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8165 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8166 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8167 }
8168
8169 /*
8170 * Reading from the current or shadow VMCS.
8171 */
8172 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8173 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8174 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8175 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8176 Log4(("vmread %#RX64 => %#RX64\n", u64VmcsField, *pu64Dst));
8177 return VINF_SUCCESS;
8178}
8179
8180
8181/**
8182 * VMREAD (64-bit register) instruction execution worker.
8183 *
8184 * @returns Strict VBox status code.
8185 * @param pVCpu The cross context virtual CPU structure.
8186 * @param cbInstr The instruction length in bytes.
8187 * @param pu64Dst Where to store the VMCS field's value.
8188 * @param u64VmcsField The VMCS field.
8189 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8190 * NULL.
8191 */
8192static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8193 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8194{
8195 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8196 if (rcStrict == VINF_SUCCESS)
8197 {
8198 iemVmxVmSucceed(pVCpu);
8199 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8200 }
8201
8202 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8203 return rcStrict;
8204}
8205
8206
8207/**
8208 * VMREAD (32-bit register) instruction execution worker.
8209 *
8210 * @returns Strict VBox status code.
8211 * @param pVCpu The cross context virtual CPU structure.
8212 * @param cbInstr The instruction length in bytes.
8213 * @param pu32Dst Where to store the VMCS field's value.
8214 * @param u32VmcsField The VMCS field.
8215 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8216 * NULL.
8217 */
8218static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8219 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8220{
8221 uint64_t u64Dst;
8222 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8223 if (rcStrict == VINF_SUCCESS)
8224 {
8225 *pu32Dst = u64Dst;
8226 iemVmxVmSucceed(pVCpu);
8227 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8228 }
8229
8230 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8231 return rcStrict;
8232}
8233
8234
8235/**
8236 * VMREAD (memory) instruction execution worker.
8237 *
8238 * @returns Strict VBox status code.
8239 * @param pVCpu The cross context virtual CPU structure.
8240 * @param cbInstr The instruction length in bytes.
8241 * @param iEffSeg The effective segment register to use with @a u64Val.
8242 * Pass UINT8_MAX if it is a register access.
8243 * @param GCPtrDst The guest linear address to store the VMCS field's
8244 * value.
8245 * @param u64VmcsField The VMCS field.
8246 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8247 * NULL.
8248 */
8249static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8250 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8251{
8252 uint64_t u64Dst;
8253 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8254 if (rcStrict == VINF_SUCCESS)
8255 {
8256 /*
8257 * Write the VMCS field's value to the location specified in guest-memory.
8258 */
8259 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8260 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8261 else
8262 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8263 if (rcStrict == VINF_SUCCESS)
8264 {
8265 iemVmxVmSucceed(pVCpu);
8266 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8267 }
8268
8269 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8270 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8271 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8272 return rcStrict;
8273 }
8274
8275 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8276 return rcStrict;
8277}
8278
8279
8280/**
8281 * Interface for HM and EM to emulate the VMREAD instruction.
8282 *
8283 * @returns Strict VBox status code.
8284 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8285 * @param pExitInfo Pointer to the VM-exit information.
8286 * @thread EMT(pVCpu)
8287 */
8288VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8289{
8290 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8291 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8292 Assert(pExitInfo);
8293
8294 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8295
8296 VBOXSTRICTRC rcStrict;
8297 uint8_t const cbInstr = pExitInfo->cbInstr;
8298 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8299 uint64_t const u64FieldEnc = fIs64BitMode
8300 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8301 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8302 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8303 {
8304 if (fIs64BitMode)
8305 {
8306 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8307 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8308 }
8309 else
8310 {
8311 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8312 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8313 }
8314 }
8315 else
8316 {
8317 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8318 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8319 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8320 }
8321 Assert(!pVCpu->iem.s.cActiveMappings);
8322 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8323}
8324
8325
8326/**
8327 * VMWRITE instruction execution worker that does not perform any validation
8328 * checks.
8329 *
8330 * Callers are expected to have performed the necessary checks and to ensure the
8331 * VMWRITE will succeed.
8332 *
8333 * @param pVmcs Pointer to the virtual VMCS.
8334 * @param u64Val The value to write.
8335 * @param u64VmcsField The VMCS field.
8336 *
8337 * @remarks May be called with interrupts disabled.
8338 */
8339static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8340{
8341 VMXVMCSFIELD VmcsField;
8342 VmcsField.u = u64VmcsField;
8343 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8344 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8345 uint8_t const uWidthType = (uWidth << 2) | uType;
8346 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8347 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8348 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8349 Assert(offField < VMX_V_VMCS_SIZE);
8350 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8351
8352 /*
8353 * Write the VMCS component based on the field's effective width.
8354 *
8355 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8356 * indicates high bits (little endian).
8357 */
8358 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8359 uint8_t *pbField = pbVmcs + offField;
8360 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8361 switch (uEffWidth)
8362 {
8363 case VMX_VMCSFIELD_WIDTH_64BIT:
8364 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8365 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8366 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8367 }
8368}
8369
8370
8371/**
8372 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8373 *
8374 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8375 * are performed. Bounds checks are strict builds only.
8376 *
8377 * @param pVmcs Pointer to the virtual VMCS.
8378 * @param u64VmcsField The VMCS field.
8379 * @param u64Val The value to write.
8380 *
8381 * @remarks May be called with interrupts disabled.
8382 * @todo This should probably be moved to CPUM someday.
8383 */
8384VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8385{
8386 AssertPtr(pVmcs);
8387 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8388}
8389
8390
8391/**
8392 * VMWRITE instruction execution worker.
8393 *
8394 * @returns Strict VBox status code.
8395 * @param pVCpu The cross context virtual CPU structure.
8396 * @param cbInstr The instruction length in bytes.
8397 * @param iEffSeg The effective segment register to use with @a u64Val.
8398 * Pass UINT8_MAX if it is a register access.
8399 * @param u64Val The value to write (or guest linear address to the
8400 * value), @a iEffSeg will indicate if it's a memory
8401 * operand.
8402 * @param u64VmcsField The VMCS field.
8403 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8404 * NULL.
8405 */
8406static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8407 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8408{
8409 /* Nested-guest intercept. */
8410 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8411 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8412 {
8413 if (pExitInfo)
8414 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8415 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8416 }
8417
8418 /* CPL. */
8419 if (pVCpu->iem.s.uCpl == 0)
8420 { /* likely */ }
8421 else
8422 {
8423 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8424 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8425 return iemRaiseGeneralProtectionFault0(pVCpu);
8426 }
8427
8428 pVCpu->iem.s.cPotentialExits++;
8429
8430 /* VMCS pointer in root mode. */
8431 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8432 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8433 { /* likely */ }
8434 else
8435 {
8436 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8437 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8438 iemVmxVmFailInvalid(pVCpu);
8439 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8440 }
8441
8442 /* VMCS-link pointer in non-root mode. */
8443 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8444 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8445 { /* likely */ }
8446 else
8447 {
8448 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8449 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8450 iemVmxVmFailInvalid(pVCpu);
8451 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8452 }
8453
8454 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8455 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8456 if (!fIsRegOperand)
8457 {
8458 /* Read the value from the specified guest memory location. */
8459 VBOXSTRICTRC rcStrict;
8460 RTGCPTR const GCPtrVal = u64Val;
8461 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8462 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8463 else
8464 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8465 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8466 {
8467 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8468 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8469 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8470 return rcStrict;
8471 }
8472 }
8473 else
8474 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8475
8476 /* Supported VMCS field. */
8477 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8478 { /* likely */ }
8479 else
8480 {
8481 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8482 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8483 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8484 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8485 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8486 }
8487
8488 /* Read-only VMCS field. */
8489 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8490 if ( !fIsFieldReadOnly
8491 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8492 { /* likely */ }
8493 else
8494 {
8495 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8496 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8497 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8498 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8499 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8500 }
8501
8502 /*
8503 * Write to the current or shadow VMCS.
8504 */
8505 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8506 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8507 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8508 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8509 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8510 Log4(("vmwrite %#RX64 <= %#RX64\n", u64VmcsField, u64Val));
8511
8512 if ( !fInVmxNonRootMode
8513 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8514 {
8515 /* Notify HM that the VMCS content might have changed. */
8516 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8517 }
8518
8519 iemVmxVmSucceed(pVCpu);
8520 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8521}
8522
8523
8524/**
8525 * Interface for HM and EM to emulate the VMWRITE instruction.
8526 *
8527 * @returns Strict VBox status code.
8528 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8529 * @param pExitInfo Pointer to the VM-exit information.
8530 * @thread EMT(pVCpu)
8531 */
8532VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8533{
8534 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8535 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8536 Assert(pExitInfo);
8537
8538 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8539
8540 uint64_t u64Val;
8541 uint8_t iEffSeg;
8542 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8543 {
8544 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8545 iEffSeg = UINT8_MAX;
8546 }
8547 else
8548 {
8549 u64Val = pExitInfo->GCPtrEffAddr;
8550 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8551 }
8552 uint8_t const cbInstr = pExitInfo->cbInstr;
8553 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8554 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8555 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8556 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8557 Assert(!pVCpu->iem.s.cActiveMappings);
8558 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8559}
8560
8561
8562/**
8563 * VMCLEAR instruction execution worker.
8564 *
8565 * @returns Strict VBox status code.
8566 * @param pVCpu The cross context virtual CPU structure.
8567 * @param cbInstr The instruction length in bytes.
8568 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8569 * @param GCPtrVmcs The linear address of the VMCS pointer.
8570 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8571 *
8572 * @remarks Common VMX instruction checks are already expected to by the caller,
8573 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8574 */
8575static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8576 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8577{
8578 /* Nested-guest intercept. */
8579 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8580 {
8581 if (pExitInfo)
8582 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8583 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8584 }
8585
8586 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8587
8588 /* CPL. */
8589 if (pVCpu->iem.s.uCpl == 0)
8590 { /* likely */ }
8591 else
8592 {
8593 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8594 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8595 return iemRaiseGeneralProtectionFault0(pVCpu);
8596 }
8597
8598 /* Get the VMCS pointer from the location specified by the source memory operand. */
8599 RTGCPHYS GCPhysVmcs;
8600 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8601 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8602 { /* likely */ }
8603 else
8604 {
8605 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8606 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8607 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8608 return rcStrict;
8609 }
8610
8611 /* VMCS pointer alignment. */
8612 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8613 { /* likely */ }
8614 else
8615 {
8616 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8617 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8618 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8619 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8620 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8621 }
8622
8623 /* VMCS physical-address width limits. */
8624 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8625 { /* likely */ }
8626 else
8627 {
8628 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8629 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8630 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8631 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8632 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8633 }
8634
8635 /* VMCS is not the VMXON region. */
8636 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8637 { /* likely */ }
8638 else
8639 {
8640 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8641 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8642 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8643 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8644 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8645 }
8646
8647 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8648 restriction imposed by our implementation. */
8649 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8650 { /* likely */ }
8651 else
8652 {
8653 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8654 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8655 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8656 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8657 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8658 }
8659
8660 /*
8661 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8662 *
8663 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8664 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8665 * to 'clear'.
8666 */
8667 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8668 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8669 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8670 {
8671 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8672 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8673 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8674 }
8675 else
8676 {
8677 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8678 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8679 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8680 if (RT_FAILURE(rcStrict))
8681 return rcStrict;
8682 }
8683
8684 iemVmxVmSucceed(pVCpu);
8685 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8686}
8687
8688
8689/**
8690 * Interface for HM and EM to emulate the VMCLEAR instruction.
8691 *
8692 * @returns Strict VBox status code.
8693 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8694 * @param pExitInfo Pointer to the VM-exit information.
8695 * @thread EMT(pVCpu)
8696 */
8697VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8698{
8699 Assert(pExitInfo);
8700 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8701 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8702
8703 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8704
8705 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8706 uint8_t const cbInstr = pExitInfo->cbInstr;
8707 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8708 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8709 Assert(!pVCpu->iem.s.cActiveMappings);
8710 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8711}
8712
8713
8714/**
8715 * VMPTRST instruction execution worker.
8716 *
8717 * @returns Strict VBox status code.
8718 * @param pVCpu The cross context virtual CPU structure.
8719 * @param cbInstr The instruction length in bytes.
8720 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8721 * @param GCPtrVmcs The linear address of where to store the current VMCS
8722 * pointer.
8723 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8724 *
8725 * @remarks Common VMX instruction checks are already expected to by the caller,
8726 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8727 */
8728static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8729 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8730{
8731 /* Nested-guest intercept. */
8732 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8733 {
8734 if (pExitInfo)
8735 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8736 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8737 }
8738
8739 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8740
8741 /* CPL. */
8742 if (pVCpu->iem.s.uCpl == 0)
8743 { /* likely */ }
8744 else
8745 {
8746 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8747 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8748 return iemRaiseGeneralProtectionFault0(pVCpu);
8749 }
8750
8751 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8752 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8753 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8754 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8755 {
8756 iemVmxVmSucceed(pVCpu);
8757 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8758 }
8759
8760 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8761 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8762 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8763 return rcStrict;
8764}
8765
8766
8767/**
8768 * Interface for HM and EM to emulate the VMPTRST instruction.
8769 *
8770 * @returns Strict VBox status code.
8771 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8772 * @param pExitInfo Pointer to the VM-exit information.
8773 * @thread EMT(pVCpu)
8774 */
8775VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8776{
8777 Assert(pExitInfo);
8778 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8779 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8780
8781 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8782
8783 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8784 uint8_t const cbInstr = pExitInfo->cbInstr;
8785 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8786 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8787 Assert(!pVCpu->iem.s.cActiveMappings);
8788 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8789}
8790
8791
8792/**
8793 * VMPTRLD instruction execution worker.
8794 *
8795 * @returns Strict VBox status code.
8796 * @param pVCpu The cross context virtual CPU structure.
8797 * @param cbInstr The instruction length in bytes.
8798 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8799 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8800 *
8801 * @remarks Common VMX instruction checks are already expected to by the caller,
8802 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8803 */
8804static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8805 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8806{
8807 /* Nested-guest intercept. */
8808 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8809 {
8810 if (pExitInfo)
8811 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8812 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8813 }
8814
8815 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8816
8817 /* CPL. */
8818 if (pVCpu->iem.s.uCpl == 0)
8819 { /* likely */ }
8820 else
8821 {
8822 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8823 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8824 return iemRaiseGeneralProtectionFault0(pVCpu);
8825 }
8826
8827 /* Get the VMCS pointer from the location specified by the source memory operand. */
8828 RTGCPHYS GCPhysVmcs;
8829 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8830 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8831 { /* likely */ }
8832 else
8833 {
8834 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8835 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8836 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8837 return rcStrict;
8838 }
8839
8840 /* VMCS pointer alignment. */
8841 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8842 { /* likely */ }
8843 else
8844 {
8845 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8846 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8847 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8848 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8849 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8850 }
8851
8852 /* VMCS physical-address width limits. */
8853 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8854 { /* likely */ }
8855 else
8856 {
8857 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8858 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8859 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8860 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8861 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8862 }
8863
8864 /* VMCS is not the VMXON region. */
8865 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8866 { /* likely */ }
8867 else
8868 {
8869 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8870 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8871 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8872 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8873 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8874 }
8875
8876 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8877 restriction imposed by our implementation. */
8878 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8879 { /* likely */ }
8880 else
8881 {
8882 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8883 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8884 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8885 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8886 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8887 }
8888
8889 /* Read just the VMCS revision from the VMCS. */
8890 VMXVMCSREVID VmcsRevId;
8891 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8892 if (RT_SUCCESS(rc))
8893 { /* likely */ }
8894 else
8895 {
8896 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8897 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8898 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8899 return rc;
8900 }
8901
8902 /*
8903 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8904 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8905 */
8906 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8907 && ( !VmcsRevId.n.fIsShadowVmcs
8908 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8909 { /* likely */ }
8910 else
8911 {
8912 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8913 {
8914 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8915 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8916 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8917 }
8918 else
8919 {
8920 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8921 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8922 }
8923 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8924 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8925 }
8926
8927 /*
8928 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8929 * the cache of an existing, current VMCS back to guest memory before loading a new,
8930 * different current VMCS.
8931 */
8932 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8933 {
8934 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8935 {
8936 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8937 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8938 }
8939
8940 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8941 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8942 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8943 if (RT_SUCCESS(rc))
8944 {
8945 /* Notify HM that a new, current VMCS is loaded. */
8946 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8947 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8948 }
8949 else
8950 {
8951 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8952 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8953 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8954 return rc;
8955 }
8956 }
8957
8958 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8959 iemVmxVmSucceed(pVCpu);
8960 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8961}
8962
8963
8964/**
8965 * Interface for HM and EM to emulate the VMPTRLD instruction.
8966 *
8967 * @returns Strict VBox status code.
8968 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8969 * @param pExitInfo Pointer to the VM-exit information.
8970 * @thread EMT(pVCpu)
8971 */
8972VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8973{
8974 Assert(pExitInfo);
8975 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8976 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8977
8978 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8979
8980 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8981 uint8_t const cbInstr = pExitInfo->cbInstr;
8982 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8983 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8984 Assert(!pVCpu->iem.s.cActiveMappings);
8985 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8986}
8987
8988
8989/**
8990 * INVVPID instruction execution worker.
8991 *
8992 * @returns Strict VBox status code.
8993 * @param pVCpu The cross context virtual CPU structure.
8994 * @param cbInstr The instruction length in bytes.
8995 * @param iEffSeg The segment of the invvpid descriptor.
8996 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8997 * @param u64InvvpidType The invalidation type.
8998 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8999 * NULL.
9000 *
9001 * @remarks Common VMX instruction checks are already expected to by the caller,
9002 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9003 */
9004VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
9005 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9006{
9007 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
9008 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
9009 return iemRaiseUndefinedOpcode(pVCpu);
9010
9011 /* Nested-guest intercept. */
9012 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9013 {
9014 if (pExitInfo)
9015 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9016 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
9017 }
9018
9019 /* CPL. */
9020 if (pVCpu->iem.s.uCpl != 0)
9021 {
9022 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9023 return iemRaiseGeneralProtectionFault0(pVCpu);
9024 }
9025
9026 /*
9027 * Validate INVVPID invalidation type.
9028 *
9029 * The instruction specifies exactly ONE of the supported invalidation types.
9030 *
9031 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9032 * supported. In theory, it's possible for a CPU to not support flushing individual
9033 * addresses but all the other types or any other combination. We do not take any
9034 * shortcuts here by assuming the types we currently expose to the guest.
9035 */
9036 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9037 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9038 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9039 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9040 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9041 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9042
9043 bool afSupportedTypes[4];
9044 afSupportedTypes[0] = fTypeIndivAddr;
9045 afSupportedTypes[1] = fTypeSingleCtx;
9046 afSupportedTypes[2] = fTypeAllCtx;
9047 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9048
9049 if ( fInvvpidSupported
9050 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9051 && afSupportedTypes[u64InvvpidType & 3])
9052 { /* likely */ }
9053 else
9054 {
9055 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9056 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9057 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9058 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9059 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9060 }
9061
9062 /*
9063 * Fetch the invvpid descriptor from guest memory.
9064 */
9065 RTUINT128U uDesc;
9066 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9067 if (rcStrict == VINF_SUCCESS)
9068 {
9069 /*
9070 * Validate the descriptor.
9071 */
9072 if (uDesc.s.Lo <= 0xffff)
9073 { /* likely */ }
9074 else
9075 {
9076 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9077 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9078 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9079 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9080 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9081 }
9082
9083 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9084 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9085 uint16_t const uVpid = uDesc.Words.w0;
9086 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9087 switch (u64InvvpidType)
9088 {
9089 case VMXTLBFLUSHVPID_INDIV_ADDR:
9090 {
9091 if (uVpid != 0)
9092 {
9093 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9094 {
9095 /* Invalidate mappings for the linear address tagged with VPID. */
9096 /** @todo PGM support for VPID? Currently just flush everything. */
9097 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9098 iemVmxVmSucceed(pVCpu);
9099 }
9100 else
9101 {
9102 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9103 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9104 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9105 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9106 }
9107 }
9108 else
9109 {
9110 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9111 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9112 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9113 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9114 }
9115 break;
9116 }
9117
9118 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9119 {
9120 if (uVpid != 0)
9121 {
9122 /* Invalidate all mappings with VPID. */
9123 /** @todo PGM support for VPID? Currently just flush everything. */
9124 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9125 iemVmxVmSucceed(pVCpu);
9126 }
9127 else
9128 {
9129 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9130 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9131 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9132 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9133 }
9134 break;
9135 }
9136
9137 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9138 {
9139 /* Invalidate all mappings with non-zero VPIDs. */
9140 /** @todo PGM support for VPID? Currently just flush everything. */
9141 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9142 iemVmxVmSucceed(pVCpu);
9143 break;
9144 }
9145
9146 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9147 {
9148 if (uVpid != 0)
9149 {
9150 /* Invalidate all mappings with VPID except global translations. */
9151 /** @todo PGM support for VPID? Currently just flush everything. */
9152 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9153 iemVmxVmSucceed(pVCpu);
9154 }
9155 else
9156 {
9157 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9158 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9159 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9160 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9161 }
9162 break;
9163 }
9164 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9165 }
9166 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9167 }
9168 return rcStrict;
9169}
9170
9171
9172/**
9173 * Interface for HM and EM to emulate the INVVPID instruction.
9174 *
9175 * @returns Strict VBox status code.
9176 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9177 * @param pExitInfo Pointer to the VM-exit information.
9178 * @thread EMT(pVCpu)
9179 */
9180VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9181{
9182 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9183 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9184 Assert(pExitInfo);
9185
9186 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9187
9188 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9189 uint8_t const cbInstr = pExitInfo->cbInstr;
9190 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9191 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9192 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9193 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9194 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9195 Assert(!pVCpu->iem.s.cActiveMappings);
9196 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9197}
9198
9199#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9200
9201/**
9202 * INVEPT instruction execution worker.
9203 *
9204 * @returns Strict VBox status code.
9205 * @param pVCpu The cross context virtual CPU structure.
9206 * @param cbInstr The instruction length in bytes.
9207 * @param iEffSeg The segment of the invept descriptor.
9208 * @param GCPtrInveptDesc The address of invept descriptor.
9209 * @param u64InveptType The invalidation type.
9210 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9211 * NULL.
9212 *
9213 * @remarks Common VMX instruction checks are already expected to by the caller,
9214 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9215 */
9216static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9217 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9218{
9219 /* Check if EPT is supported, otherwise raise #UD. */
9220 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9221 return iemRaiseUndefinedOpcode(pVCpu);
9222
9223 /* Nested-guest intercept. */
9224 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9225 {
9226 if (pExitInfo)
9227 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9228 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9229 }
9230
9231 /* CPL. */
9232 if (pVCpu->iem.s.uCpl != 0)
9233 {
9234 Log(("invept: CPL != 0 -> #GP(0)\n"));
9235 return iemRaiseGeneralProtectionFault0(pVCpu);
9236 }
9237
9238 /*
9239 * Validate INVEPT invalidation type.
9240 *
9241 * The instruction specifies exactly ONE of the supported invalidation types.
9242 *
9243 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9244 * supported. In theory, it's possible for a CPU to not support flushing individual
9245 * addresses but all the other types or any other combination. We do not take any
9246 * shortcuts here by assuming the types we currently expose to the guest.
9247 */
9248 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9249 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9250 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9251 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9252
9253 bool afSupportedTypes[4];
9254 afSupportedTypes[0] = false;
9255 afSupportedTypes[1] = fTypeSingleCtx;
9256 afSupportedTypes[2] = fTypeAllCtx;
9257 afSupportedTypes[3] = false;
9258
9259 if ( fInveptSupported
9260 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9261 && afSupportedTypes[u64InveptType & 3])
9262 { /* likely */ }
9263 else
9264 {
9265 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9266 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9267 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9268 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9269 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9270 }
9271
9272 /*
9273 * Fetch the invept descriptor from guest memory.
9274 */
9275 RTUINT128U uDesc;
9276 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9277 if (rcStrict == VINF_SUCCESS)
9278 {
9279 /*
9280 * Validate the descriptor.
9281 *
9282 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9283 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9284 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9285 * better to be strict in our emulation until proven otherwise.
9286 */
9287 if (uDesc.s.Hi)
9288 {
9289 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9290 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9291 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9292 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9293 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9294 }
9295
9296 /*
9297 * Flush TLB mappings based on the EPT type.
9298 */
9299 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9300 {
9301 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9302 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9303 if (RT_SUCCESS(rc))
9304 { /* likely */ }
9305 else
9306 {
9307 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9308 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9309 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9310 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9311 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9312 }
9313 }
9314
9315 /** @todo PGM support for EPT tags? Currently just flush everything. */
9316 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9317 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9318 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9319
9320 iemVmxVmSucceed(pVCpu);
9321 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9322 }
9323
9324 return rcStrict;
9325}
9326
9327
9328/**
9329 * Interface for HM and EM to emulate the INVEPT instruction.
9330 *
9331 * @returns Strict VBox status code.
9332 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9333 * @param pExitInfo Pointer to the VM-exit information.
9334 * @thread EMT(pVCpu)
9335 */
9336VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9337{
9338 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9339 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9340 Assert(pExitInfo);
9341
9342 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9343
9344 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9345 uint8_t const cbInstr = pExitInfo->cbInstr;
9346 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9347 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9348 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9349 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9350 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9351 Assert(!pVCpu->iem.s.cActiveMappings);
9352 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9353}
9354
9355#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9356
9357/**
9358 * VMXON instruction execution worker.
9359 *
9360 * @returns Strict VBox status code.
9361 * @param pVCpu The cross context virtual CPU structure.
9362 * @param cbInstr The instruction length in bytes.
9363 * @param iEffSeg The effective segment register to use with @a
9364 * GCPtrVmxon.
9365 * @param GCPtrVmxon The linear address of the VMXON pointer.
9366 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9367 *
9368 * @remarks Common VMX instruction checks are already expected to by the caller,
9369 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9370 */
9371static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9372 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9373{
9374 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9375 {
9376 /* CPL. */
9377 if (pVCpu->iem.s.uCpl == 0)
9378 { /* likely */ }
9379 else
9380 {
9381 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9382 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9383 return iemRaiseGeneralProtectionFault0(pVCpu);
9384 }
9385
9386 /* A20M (A20 Masked) mode. */
9387 if (PGMPhysIsA20Enabled(pVCpu))
9388 { /* likely */ }
9389 else
9390 {
9391 Log(("vmxon: A20M mode -> #GP(0)\n"));
9392 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9393 return iemRaiseGeneralProtectionFault0(pVCpu);
9394 }
9395
9396 /* CR0. */
9397 {
9398 /*
9399 * CR0 MB1 bits.
9400 *
9401 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9402 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9403 * when the guest running in VMX non-root mode with unrestricted-guest control
9404 * enabled in the VMCS.
9405 */
9406 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9407 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9408 { /* likely */ }
9409 else
9410 {
9411 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9412 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9413 return iemRaiseGeneralProtectionFault0(pVCpu);
9414 }
9415
9416 /* CR0 MBZ bits. */
9417 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9418 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9419 { /* likely */ }
9420 else
9421 {
9422 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9423 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9424 return iemRaiseGeneralProtectionFault0(pVCpu);
9425 }
9426 }
9427
9428 /* CR4. */
9429 {
9430 /* CR4 MB1 bits. */
9431 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9432 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9433 { /* likely */ }
9434 else
9435 {
9436 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9437 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9438 return iemRaiseGeneralProtectionFault0(pVCpu);
9439 }
9440
9441 /* CR4 MBZ bits. */
9442 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9443 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9444 { /* likely */ }
9445 else
9446 {
9447 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9448 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9449 return iemRaiseGeneralProtectionFault0(pVCpu);
9450 }
9451 }
9452
9453 /* Feature control MSR's LOCK and VMXON bits. */
9454 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9455 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9456 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9457 { /* likely */ }
9458 else
9459 {
9460 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9461 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9462 return iemRaiseGeneralProtectionFault0(pVCpu);
9463 }
9464
9465 /* Get the VMXON pointer from the location specified by the source memory operand. */
9466 RTGCPHYS GCPhysVmxon;
9467 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9468 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9469 { /* likely */ }
9470 else
9471 {
9472 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9473 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9474 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9475 return rcStrict;
9476 }
9477
9478 /* VMXON region pointer alignment. */
9479 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9480 { /* likely */ }
9481 else
9482 {
9483 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9484 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9485 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9486 iemVmxVmFailInvalid(pVCpu);
9487 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9488 }
9489
9490 /* VMXON physical-address width limits. */
9491 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9492 { /* likely */ }
9493 else
9494 {
9495 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9496 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9497 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9498 iemVmxVmFailInvalid(pVCpu);
9499 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9500 }
9501
9502 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9503 restriction imposed by our implementation. */
9504 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9505 { /* likely */ }
9506 else
9507 {
9508 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9509 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9510 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9511 iemVmxVmFailInvalid(pVCpu);
9512 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9513 }
9514
9515 /* Read the VMCS revision ID from the VMXON region. */
9516 VMXVMCSREVID VmcsRevId;
9517 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9518 if (RT_SUCCESS(rc))
9519 { /* likely */ }
9520 else
9521 {
9522 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9523 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9524 return rc;
9525 }
9526
9527 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9528 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9529 { /* likely */ }
9530 else
9531 {
9532 /* Revision ID mismatch. */
9533 if (!VmcsRevId.n.fIsShadowVmcs)
9534 {
9535 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9536 VmcsRevId.n.u31RevisionId));
9537 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9538 iemVmxVmFailInvalid(pVCpu);
9539 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9540 }
9541
9542 /* Shadow VMCS disallowed. */
9543 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9544 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9545 iemVmxVmFailInvalid(pVCpu);
9546 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9547 }
9548
9549 /*
9550 * Record that we're in VMX operation, block INIT, block and disable A20M.
9551 */
9552 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9553 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9554 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9555
9556 /* Clear address-range monitoring. */
9557 EMMonitorWaitClear(pVCpu);
9558 /** @todo NSTVMX: Intel PT. */
9559
9560 iemVmxVmSucceed(pVCpu);
9561 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9562 }
9563 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9564 {
9565 /* Nested-guest intercept. */
9566 if (pExitInfo)
9567 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9568 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9569 }
9570
9571 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9572
9573 /* CPL. */
9574 if (pVCpu->iem.s.uCpl > 0)
9575 {
9576 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9577 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9578 return iemRaiseGeneralProtectionFault0(pVCpu);
9579 }
9580
9581 /* VMXON when already in VMX root mode. */
9582 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9583 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9584 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9585}
9586
9587
9588/**
9589 * Interface for HM and EM to emulate the VMXON instruction.
9590 *
9591 * @returns Strict VBox status code.
9592 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9593 * @param pExitInfo Pointer to the VM-exit information.
9594 * @thread EMT(pVCpu)
9595 */
9596VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9597{
9598 Assert(pExitInfo);
9599 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9600 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9601
9602 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9603
9604 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9605 uint8_t const cbInstr = pExitInfo->cbInstr;
9606 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9607 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9608 Assert(!pVCpu->iem.s.cActiveMappings);
9609 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9610}
9611
9612
9613/**
9614 * Implements 'VMXOFF'.
9615 *
9616 * @remarks Common VMX instruction checks are already expected to by the caller,
9617 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9618 */
9619IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9620{
9621 /* Nested-guest intercept. */
9622 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9623 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9624
9625 /* CPL. */
9626 if (pVCpu->iem.s.uCpl == 0)
9627 { /* likely */ }
9628 else
9629 {
9630 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9631 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9632 return iemRaiseGeneralProtectionFault0(pVCpu);
9633 }
9634
9635 /* Dual monitor treatment of SMIs and SMM. */
9636 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9637 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9638 { /* likely */ }
9639 else
9640 {
9641 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9642 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9643 }
9644
9645 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9646 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9647 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9648
9649 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9650 { /** @todo NSTVMX: Unblock SMI. */ }
9651
9652 EMMonitorWaitClear(pVCpu);
9653 /** @todo NSTVMX: Unblock and enable A20M. */
9654
9655 iemVmxVmSucceed(pVCpu);
9656 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9657}
9658
9659
9660/**
9661 * Interface for HM and EM to emulate the VMXOFF instruction.
9662 *
9663 * @returns Strict VBox status code.
9664 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9665 * @param cbInstr The instruction length in bytes.
9666 * @thread EMT(pVCpu)
9667 */
9668VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9669{
9670 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9671 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9672
9673 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9674 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9675 Assert(!pVCpu->iem.s.cActiveMappings);
9676 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9677}
9678
9679
9680/**
9681 * Implements 'VMXON'.
9682 */
9683IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9684{
9685 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9686}
9687
9688
9689/**
9690 * Implements 'VMLAUNCH'.
9691 */
9692IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9693{
9694 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9695}
9696
9697
9698/**
9699 * Implements 'VMRESUME'.
9700 */
9701IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9702{
9703 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9704}
9705
9706
9707/**
9708 * Implements 'VMPTRLD'.
9709 */
9710IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9711{
9712 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9713}
9714
9715
9716/**
9717 * Implements 'VMPTRST'.
9718 */
9719IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9720{
9721 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9722}
9723
9724
9725/**
9726 * Implements 'VMCLEAR'.
9727 */
9728IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9729{
9730 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9731}
9732
9733
9734/**
9735 * Implements 'VMWRITE' register.
9736 */
9737IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9738{
9739 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9740}
9741
9742
9743/**
9744 * Implements 'VMWRITE' memory.
9745 */
9746IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9747{
9748 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9749}
9750
9751
9752/**
9753 * Implements 'VMREAD' register (64-bit).
9754 */
9755IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9756{
9757 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9758}
9759
9760
9761/**
9762 * Implements 'VMREAD' register (32-bit).
9763 */
9764IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint64_t *, pu64Dst, uint32_t, u32VmcsField)
9765{
9766 VBOXSTRICTRC const rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, (uint32_t *)pu64Dst, u32VmcsField, NULL /* pExitInfo */);
9767 /* Zero the high part of the register on success. */
9768 if (rcStrict == VINF_SUCCESS)
9769 *pu64Dst = (uint32_t)*pu64Dst;
9770 return rcStrict;
9771}
9772
9773
9774/**
9775 * Implements 'VMREAD' memory, 64-bit register.
9776 */
9777IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9778{
9779 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9780}
9781
9782
9783/**
9784 * Implements 'VMREAD' memory, 32-bit register.
9785 */
9786IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9787{
9788 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9789}
9790
9791
9792/**
9793 * Implements 'INVVPID'.
9794 */
9795IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9796{
9797 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9798}
9799
9800
9801#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9802/**
9803 * Implements 'INVEPT'.
9804 */
9805IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9806{
9807 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9808}
9809#endif
9810
9811
9812/**
9813 * Implements VMX's implementation of PAUSE.
9814 */
9815IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9816{
9817 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9818 {
9819 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9820 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9821 return rcStrict;
9822 }
9823
9824 /*
9825 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9826 * a VM-exit, the instruction operates normally.
9827 */
9828 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9829}
9830
9831#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9832
9833
9834/**
9835 * Implements 'VMCALL'.
9836 */
9837IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9838{
9839 pVCpu->iem.s.cPotentialExits++;
9840
9841#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9842 /* Nested-guest intercept. */
9843 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9844 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9845#endif
9846
9847 /* Join forces with vmmcall. */
9848 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9849}
9850
9851
9852#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9853
9854/**
9855 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9856 *
9857 * @remarks The @a uUser argument is currently unused.
9858 */
9859DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9860 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9861 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9862{
9863 RT_NOREF3(pvPhys, enmOrigin, uUser);
9864
9865 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9866 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9867 {
9868 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9869 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9870
9871 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9872 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9873
9874 LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9875 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9876 if (RT_FAILURE(rcStrict))
9877 return rcStrict;
9878
9879 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9880 return VINF_SUCCESS;
9881 }
9882
9883 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9884 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9885 if (RT_FAILURE(rc))
9886 return rc;
9887
9888 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9889 return VINF_PGM_HANDLER_DO_DEFAULT;
9890}
9891
9892
9893# ifndef IN_RING3
9894/**
9895 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9896 * \#PF access handler callback for guest VMX APIC-access page.}
9897 */
9898DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
9899 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9900
9901{
9902 RT_NOREF3(pVM, pCtx, uUser);
9903
9904 /*
9905 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9906 * Otherwise we must deregister the page and allow regular RAM access.
9907 * Failing to do so lands us with endless EPT VM-exits.
9908 */
9909 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9910 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9911 {
9912 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9913 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9914
9915 /*
9916 * Check if the access causes an APIC-access VM-exit.
9917 */
9918 uint32_t fAccess;
9919 if (uErr & X86_TRAP_PF_ID)
9920 fAccess = IEM_ACCESS_INSTRUCTION;
9921 else if (uErr & X86_TRAP_PF_RW)
9922 fAccess = IEM_ACCESS_DATA_W;
9923 else
9924 fAccess = IEM_ACCESS_DATA_R;
9925
9926 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9927 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9928 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9929 LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
9930 if (fIntercept)
9931 {
9932 /*
9933 * Query the source VM-exit (from the execution engine) that caused this access
9934 * within the APIC-access page. Currently only HM is supported.
9935 */
9936 AssertMsg(VM_IS_HM_ENABLED(pVM),
9937 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
9938
9939 HMEXITAUX HmExitAux;
9940 RT_ZERO(HmExitAux);
9941 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9942 | HMVMX_READ_EXIT_QUALIFICATION
9943 | HMVMX_READ_IDT_VECTORING_INFO
9944 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9945 AssertRC(rc);
9946
9947 /*
9948 * Verify the VM-exit reason must be an EPT violation.
9949 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9950 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9951 */
9952 AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9953 ("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
9954 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
9955
9956 /*
9957 * Construct the virtual APIC-access VM-exit.
9958 */
9959 VMXAPICACCESS enmAccess;
9960 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9961 {
9962 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9963 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9964 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9965 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9966 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9967 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9968 else
9969 enmAccess = VMXAPICACCESS_LINEAR_READ;
9970
9971 /* For linear-address accesss the instruction length must be valid. */
9972 AssertMsg(HmExitAux.Vmx.cbInstr > 0,
9973 ("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
9974 }
9975 else
9976 {
9977 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9978 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
9979 else
9980 {
9981 /** @todo How to distinguish between monitoring/trace vs other instructions
9982 * here? */
9983 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
9984 }
9985
9986 /* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
9987 HmExitAux.Vmx.cbInstr = 0;
9988 }
9989
9990 /*
9991 * Raise the APIC-access VM-exit.
9992 */
9993 LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
9994 VMXVEXITINFO const ExitInfo
9995 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_APIC_ACCESS,
9996 RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
9997 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess),
9998 HmExitAux.Vmx.cbInstr);
9999 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_IDT(HmExitAux.Vmx.uIdtVectoringInfo,
10000 HmExitAux.Vmx.uIdtVectoringErrCode);
10001 VBOXSTRICTRC const rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
10002 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
10003 }
10004
10005 /*
10006 * The access isn't intercepted, which means it needs to be virtualized.
10007 *
10008 * This requires emulating the instruction because we need the bytes being
10009 * read/written by the instruction not just the offset being accessed within
10010 * the APIC-access page (which we derive from the faulting address).
10011 */
10012 LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
10013 return VINF_EM_RAW_EMULATE_INSTR;
10014 }
10015
10016 /** @todo This isn't ideal but works for now as nested-hypervisors generally play
10017 * nice because the spec states that this page should be modified only when
10018 * no CPU refers to it VMX non-root mode. Nonetheless, we could use an atomic
10019 * reference counter to ensure the aforementioned condition before
10020 * de-registering the page. */
10021 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10022 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10023 if (RT_FAILURE(rc))
10024 return rc;
10025
10026 return VINF_SUCCESS;
10027}
10028# endif /* !IN_RING3 */
10029
10030#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10031
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