VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 97698

Last change on this file since 97698 was 97694, checked in by vboxsync, 2 years ago

VMM/IEM: Added support for hardware instruction breakpoints (DRx). Corrected some DR6 updating for single stepping. bugref:9898
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1/* $Id: IEMAllCImplVmxInstr.cpp 97694 2022-11-28 22:08:14Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM_VMX
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/dbgf.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/gim.h>
40#include <VBox/vmm/hm.h>
41#include <VBox/vmm/pgm.h>
42#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
43# include <VBox/vmm/hmvmxinline.h>
44#endif
45#include <VBox/vmm/tm.h>
46#include "IEMInternal.h"
47#include <VBox/vmm/vmcc.h>
48#include <VBox/log.h>
49#include <VBox/err.h>
50#include <VBox/param.h>
51#include <VBox/disopcode.h>
52#include <iprt/asm-math.h>
53#include <iprt/assert.h>
54#include <iprt/string.h>
55#include <iprt/x86.h>
56
57#include "IEMInline.h"
58
59
60/*********************************************************************************************************************************
61* Defined Constants And Macros *
62*********************************************************************************************************************************/
63#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
64/**
65 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
66 * relative offsets.
67 */
68# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
69# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
70# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
71# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
77# if 0
78# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
79# endif
80# else /* !IEM_WITH_CODE_TLB */
81# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
82 do \
83 { \
84 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
86 } while (0)
87
88# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
89
90# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
91 do \
92 { \
93 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
94 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
95 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
96 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
97 } while (0)
98
99# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
100 do \
101 { \
102 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
103 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
104 } while (0)
105
106# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
107 do \
108 { \
109 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
110 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
111 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
112 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
113 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
114 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
115 } while (0)
116
117# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
118 do \
119 { \
120 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
121 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
122 } while (0)
123
124# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
125 do \
126 { \
127 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
128 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
129 } while (0)
130
131# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
132 do \
133 { \
134 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
135 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
136 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
137 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
138 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
139 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
140 } while (0)
141# endif /* !IEM_WITH_CODE_TLB */
142
143/** Check for VMX instructions requiring to be in VMX operation.
144 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
145# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
146 do \
147 { \
148 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
149 { /* likely */ } \
150 else \
151 { \
152 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
153 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
154 return iemRaiseUndefinedOpcode(a_pVCpu); \
155 } \
156 } while (0)
157
158/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
159# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
160 do \
161 { \
162 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
163 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
164 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
165 return VERR_VMX_VMENTRY_FAILED; \
166 } while (0)
167
168/** Marks a VM-exit failure with a diagnostic reason and logs. */
169# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
170 do \
171 { \
172 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
173 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
174 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
175 } while (0)
176
177/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
178# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
179 do \
180 { \
181 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
182 return VERR_VMX_VMEXIT_FAILED; \
183 } while (0)
184
185
186/*********************************************************************************************************************************
187* Global Variables *
188*********************************************************************************************************************************/
189/** @todo NSTVMX: The following VM-exit intercepts are pending:
190 * VMX_EXIT_IO_SMI
191 * VMX_EXIT_SMI
192 * VMX_EXIT_GETSEC
193 * VMX_EXIT_RSM
194 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
195 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
196 * VMX_EXIT_RDRAND
197 * VMX_EXIT_VMFUNC
198 * VMX_EXIT_ENCLS
199 * VMX_EXIT_RDSEED
200 * VMX_EXIT_PML_FULL
201 * VMX_EXIT_XSAVES
202 * VMX_EXIT_XRSTORS
203 */
204/**
205 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
206 *
207 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
208 * second dimension is the Index, see VMXVMCSFIELD.
209 */
210uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
211{
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u16HlatPrefixSize),
218 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
219 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
220 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
221 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
222 },
223 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
224 {
225 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
227 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
230 },
231 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
232 {
233 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
234 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
235 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
236 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
237 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
238 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
239 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
240 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
241 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
242 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
243 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 34 */ UINT16_MAX
247 },
248 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
249 {
250 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
251 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
252 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
253 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
254 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
255 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
256 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
257 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
258 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
259 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
260 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
261 },
262 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
263 {
264 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
265 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
266 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
267 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
268 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
269 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
270 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
271 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
272 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
273 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
274 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
275 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
276 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
277 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
278 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
279 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
280 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
281 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
282 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
283 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
284 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
285 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
286 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
287 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
288 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
289 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
290 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
291 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap),
292 /* 28 */ UINT16_MAX,
293 /* 29 */ UINT16_MAX,
294 /* 30 */ UINT16_MAX,
295 /* 31 */ RT_UOFFSETOF(VMXVVMCS, u64PconfigExitBitmap),
296 /* 32 */ RT_UOFFSETOF(VMXVVMCS, u64HlatPtr),
297 /* 33 */ UINT16_MAX,
298 /* 34 */ RT_UOFFSETOF(VMXVVMCS, u64ExitCtls2)
299 },
300 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
301 {
302 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
303 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
304 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 33-34*/ UINT16_MAX, UINT16_MAX
308 },
309 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
322 /* 11 */ UINT16_MAX,
323 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
324 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
325 /* 21-28 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
326 /* 29-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
327 },
328 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
329 {
330 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
331 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
332 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
333 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
334 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
337 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
338 },
339 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
340 {
341 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
342 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
343 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
344 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
345 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
346 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
347 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
348 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
349 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
350 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
351 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
352 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
353 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
354 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
355 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
356 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
357 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
358 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
359 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
360 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
361 /* 34 */ UINT16_MAX
362 },
363 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
364 {
365 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
366 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
367 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
368 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
369 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
370 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
371 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
372 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
373 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
374 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
375 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
376 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
377 },
378 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
379 {
380 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
381 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
382 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
383 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
384 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
385 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
386 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
387 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
388 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
389 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
390 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
391 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
392 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
393 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
394 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
395 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
396 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
397 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
398 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
399 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
400 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
401 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
402 /* 22 */ UINT16_MAX,
403 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
404 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
410 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
411 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
412 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
413 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
414 /* 33-34 */ UINT16_MAX, UINT16_MAX
415 },
416 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
417 {
418 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
419 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
420 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
421 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
422 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
423 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
424 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
425 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
426 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
429 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
430 },
431 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
432 {
433 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
434 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
435 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
436 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
437 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
438 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
439 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
440 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
441 /* 22-29 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
442 /* 30-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
443 },
444 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
445 {
446 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
447 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
448 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
449 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
450 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
451 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
452 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
453 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
454 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
455 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
456 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
457 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
458 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
459 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
460 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
461 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
462 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
463 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
464 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
465 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
466 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
467 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
468 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
469 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
470 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
471 },
472 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
473 {
474 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
475 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
476 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
477 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
478 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
479 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
480 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
481 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
482 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
483 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
484 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
485 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
486 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
487 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
488 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
489 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
490 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
491 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
492 }
493};
494
495
496/**
497 * Gets a host selector from the VMCS.
498 *
499 * @param pVmcs Pointer to the virtual VMCS.
500 * @param iSelReg The index of the segment register (X86_SREG_XXX).
501 */
502DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
503{
504 Assert(iSegReg < X86_SREG_COUNT);
505 RTSEL HostSel;
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 HostSel = *(uint16_t *)pbField;
515 return HostSel;
516}
517
518
519/**
520 * Sets a guest segment register in the VMCS.
521 *
522 * @param pVmcs Pointer to the virtual VMCS.
523 * @param iSegReg The index of the segment register (X86_SREG_XXX).
524 * @param pSelReg Pointer to the segment register.
525 */
526static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
527{
528 Assert(pSelReg);
529 Assert(iSegReg < X86_SREG_COUNT);
530
531 /* Selector. */
532 {
533 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
534 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
535 uint8_t const uWidthType = (uWidth << 2) | uType;
536 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
537 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
538 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
539 uint8_t *pbVmcs = (uint8_t *)pVmcs;
540 uint8_t *pbField = pbVmcs + offField;
541 *(uint16_t *)pbField = pSelReg->Sel;
542 }
543
544 /* Limit. */
545 {
546 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
547 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
548 uint8_t const uWidthType = (uWidth << 2) | uType;
549 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
550 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
551 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
552 uint8_t *pbVmcs = (uint8_t *)pVmcs;
553 uint8_t *pbField = pbVmcs + offField;
554 *(uint32_t *)pbField = pSelReg->u32Limit;
555 }
556
557 /* Base. */
558 {
559 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
560 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
561 uint8_t const uWidthType = (uWidth << 2) | uType;
562 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
563 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
564 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
565 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
566 uint8_t const *pbField = pbVmcs + offField;
567 *(uint64_t *)pbField = pSelReg->u64Base;
568 }
569
570 /* Attributes. */
571 {
572 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
573 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
574 | X86DESCATTR_UNUSABLE;
575 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
576 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
577 uint8_t const uWidthType = (uWidth << 2) | uType;
578 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
579 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
580 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
581 uint8_t *pbVmcs = (uint8_t *)pVmcs;
582 uint8_t *pbField = pbVmcs + offField;
583 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
584 }
585}
586
587
588/**
589 * Gets a guest segment register from the VMCS.
590 *
591 * @returns VBox status code.
592 * @param pVmcs Pointer to the virtual VMCS.
593 * @param iSegReg The index of the segment register (X86_SREG_XXX).
594 * @param pSelReg Where to store the segment register (only updated when
595 * VINF_SUCCESS is returned).
596 *
597 * @remarks Warning! This does not validate the contents of the retrieved segment
598 * register.
599 */
600static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
601{
602 Assert(pSelReg);
603 Assert(iSegReg < X86_SREG_COUNT);
604
605 /* Selector. */
606 uint16_t u16Sel;
607 {
608 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
609 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
610 uint8_t const uWidthType = (uWidth << 2) | uType;
611 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
612 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
613 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
614 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
615 uint8_t const *pbField = pbVmcs + offField;
616 u16Sel = *(uint16_t *)pbField;
617 }
618
619 /* Limit. */
620 uint32_t u32Limit;
621 {
622 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
623 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
624 uint8_t const uWidthType = (uWidth << 2) | uType;
625 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
626 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
627 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
628 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
629 uint8_t const *pbField = pbVmcs + offField;
630 u32Limit = *(uint32_t *)pbField;
631 }
632
633 /* Base. */
634 uint64_t u64Base;
635 {
636 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
637 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
638 uint8_t const uWidthType = (uWidth << 2) | uType;
639 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
640 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
641 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
642 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
643 uint8_t const *pbField = pbVmcs + offField;
644 u64Base = *(uint64_t *)pbField;
645 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
646 }
647
648 /* Attributes. */
649 uint32_t u32Attr;
650 {
651 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
652 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
653 uint8_t const uWidthType = (uWidth << 2) | uType;
654 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
655 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
656 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
657 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
658 uint8_t const *pbField = pbVmcs + offField;
659 u32Attr = *(uint32_t *)pbField;
660 }
661
662 pSelReg->Sel = u16Sel;
663 pSelReg->ValidSel = u16Sel;
664 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
665 pSelReg->u32Limit = u32Limit;
666 pSelReg->u64Base = u64Base;
667 pSelReg->Attr.u = u32Attr;
668 return VINF_SUCCESS;
669}
670
671
672/**
673 * Converts an IEM exception event type to a VMX event type.
674 *
675 * @returns The VMX event type.
676 * @param uVector The interrupt / exception vector.
677 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
678 */
679DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
680{
681 /* Paranoia (callers may use these interchangeably). */
682 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
683 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
684 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
685 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
686 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
687 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
688 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
689 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
690 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
691 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
692 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
693 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
694
695 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
696 {
697 if (uVector == X86_XCPT_NMI)
698 return VMX_EXIT_INT_INFO_TYPE_NMI;
699 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
700 }
701
702 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
703 {
704 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
705 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
706 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
707 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
708 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
709 }
710
711 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
712 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
713}
714
715
716/**
717 * Determines whether the guest is using PAE paging given the VMCS.
718 *
719 * @returns @c true if PAE paging mode is used, @c false otherwise.
720 * @param pVmcs Pointer to the virtual VMCS.
721 *
722 * @warning Only use this prior to switching the guest-CPU state with the
723 * nested-guest CPU state!
724 */
725DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
726{
727 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
728 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
729 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
730}
731
732
733/**
734 * Sets the Exit qualification VMCS field.
735 *
736 * @param pVCpu The cross context virtual CPU structure.
737 * @param u64ExitQual The Exit qualification.
738 */
739DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
740{
741 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
742}
743
744
745/**
746 * Sets the VM-exit interruption information field.
747 *
748 * @param pVCpu The cross context virtual CPU structure.
749 * @param uExitIntInfo The VM-exit interruption information.
750 */
751DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
752{
753 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
754}
755
756
757/**
758 * Sets the VM-exit interruption error code.
759 *
760 * @param pVCpu The cross context virtual CPU structure.
761 * @param uErrCode The error code.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
764{
765 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
766}
767
768
769/**
770 * Sets the IDT-vectoring information field.
771 *
772 * @param pVCpu The cross context virtual CPU structure.
773 * @param uIdtVectorInfo The IDT-vectoring information.
774 */
775DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
776{
777 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
778}
779
780
781/**
782 * Sets the IDT-vectoring error code field.
783 *
784 * @param pVCpu The cross context virtual CPU structure.
785 * @param uErrCode The error code.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
788{
789 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
790}
791
792
793/**
794 * Sets the VM-exit guest-linear address VMCS field.
795 *
796 * @param pVCpu The cross context virtual CPU structure.
797 * @param uGuestLinearAddr The VM-exit guest-linear address.
798 */
799DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
800{
801 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
802 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
803 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
804}
805
806
807/**
808 * Sets the VM-exit guest-physical address VMCS field.
809 *
810 * @param pVCpu The cross context virtual CPU structure.
811 * @param uGuestPhysAddr The VM-exit guest-physical address.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
814{
815 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
816}
817
818
819/**
820 * Sets the VM-exit instruction length VMCS field.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param cbInstr The VM-exit instruction length in bytes.
824 *
825 * @remarks Callers may clear this field to 0. Hence, this function does not check
826 * the validity of the instruction length.
827 */
828DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
829{
830 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
831}
832
833
834/**
835 * Sets the VM-exit instruction info. VMCS field.
836 *
837 * @param pVCpu The cross context virtual CPU structure.
838 * @param uExitInstrInfo The VM-exit instruction information.
839 */
840DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
841{
842 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
843}
844
845
846/**
847 * Sets the guest pending-debug exceptions field.
848 *
849 * @param pVCpu The cross context virtual CPU structure.
850 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
851 */
852DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
853{
854 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
855 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
856}
857
858
859/**
860 * Implements VMSucceed for VMX instruction success.
861 *
862 * @param pVCpu The cross context virtual CPU structure.
863 */
864DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
865{
866 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
867}
868
869
870/**
871 * Implements VMFailInvalid for VMX instruction failure.
872 *
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
876{
877 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
878}
879
880
881/**
882 * Implements VMFail for VMX instruction failure.
883 *
884 * @param pVCpu The cross context virtual CPU structure.
885 * @param enmInsErr The VM instruction error.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
888{
889 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
890}
891
892
893/**
894 * Checks if the given auto-load/store MSR area count is valid for the
895 * implementation.
896 *
897 * @returns @c true if it's within the valid limit, @c false otherwise.
898 * @param pVCpu The cross context virtual CPU structure.
899 * @param uMsrCount The MSR area count to check.
900 */
901DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
902{
903 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
904 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
905 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
906 if (uMsrCount <= cMaxSupportedMsrs)
907 return true;
908 return false;
909}
910
911
912/**
913 * Flushes the current VMCS contents back to guest memory.
914 *
915 * @returns VBox status code.
916 * @param pVCpu The cross context virtual CPU structure.
917 */
918DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
919{
920 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
921 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
922 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
923 return rc;
924}
925
926
927/**
928 * Populates the current VMCS contents from guest memory.
929 *
930 * @returns VBox status code.
931 * @param pVCpu The cross context virtual CPU structure.
932 */
933DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
934{
935 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
936 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
937 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
938 return rc;
939}
940
941
942/**
943 * Gets the instruction diagnostic for segment base checks during VM-entry of a
944 * nested-guest.
945 *
946 * @param iSegReg The segment index (X86_SREG_XXX).
947 */
948static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
949{
950 switch (iSegReg)
951 {
952 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
953 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
954 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
955 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
956 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
957 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
958 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
959 }
960}
961
962
963/**
964 * Gets the instruction diagnostic for segment base checks during VM-entry of a
965 * nested-guest that is in Virtual-8086 mode.
966 *
967 * @param iSegReg The segment index (X86_SREG_XXX).
968 */
969static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
970{
971 switch (iSegReg)
972 {
973 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
974 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
975 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
976 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
977 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
978 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
979 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
980 }
981}
982
983
984/**
985 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
986 * nested-guest that is in Virtual-8086 mode.
987 *
988 * @param iSegReg The segment index (X86_SREG_XXX).
989 */
990static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
991{
992 switch (iSegReg)
993 {
994 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
995 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
996 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
997 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
998 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
999 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1000 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1001 }
1002}
1003
1004
1005/**
1006 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1007 * nested-guest that is in Virtual-8086 mode.
1008 *
1009 * @param iSegReg The segment index (X86_SREG_XXX).
1010 */
1011static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
1012{
1013 switch (iSegReg)
1014 {
1015 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1016 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1017 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1018 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1019 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1020 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1021 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1022 }
1023}
1024
1025
1026/**
1027 * Gets the instruction diagnostic for segment attributes reserved bits failure
1028 * during VM-entry of a nested-guest.
1029 *
1030 * @param iSegReg The segment index (X86_SREG_XXX).
1031 */
1032static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1033{
1034 switch (iSegReg)
1035 {
1036 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1037 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1038 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1039 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1040 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1041 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1042 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1043 }
1044}
1045
1046
1047/**
1048 * Gets the instruction diagnostic for segment attributes descriptor-type
1049 * (code/segment or system) failure during VM-entry of a nested-guest.
1050 *
1051 * @param iSegReg The segment index (X86_SREG_XXX).
1052 */
1053static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1054{
1055 switch (iSegReg)
1056 {
1057 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1058 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1059 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1060 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1061 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1062 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1063 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1064 }
1065}
1066
1067
1068/**
1069 * Gets the instruction diagnostic for segment attributes descriptor-type
1070 * (code/segment or system) failure during VM-entry of a nested-guest.
1071 *
1072 * @param iSegReg The segment index (X86_SREG_XXX).
1073 */
1074static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1075{
1076 switch (iSegReg)
1077 {
1078 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1079 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1080 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1081 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1082 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1083 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1084 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1085 }
1086}
1087
1088
1089/**
1090 * Gets the instruction diagnostic for segment attribute granularity failure during
1091 * VM-entry of a nested-guest.
1092 *
1093 * @param iSegReg The segment index (X86_SREG_XXX).
1094 */
1095static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1096{
1097 switch (iSegReg)
1098 {
1099 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1100 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1101 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1102 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1103 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1104 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1105 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1106 }
1107}
1108
1109/**
1110 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1111 * VM-entry of a nested-guest.
1112 *
1113 * @param iSegReg The segment index (X86_SREG_XXX).
1114 */
1115static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1116{
1117 switch (iSegReg)
1118 {
1119 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1120 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1121 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1122 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1123 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1124 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1125 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1126 }
1127}
1128
1129
1130/**
1131 * Gets the instruction diagnostic for segment attribute type accessed failure
1132 * during VM-entry of a nested-guest.
1133 *
1134 * @param iSegReg The segment index (X86_SREG_XXX).
1135 */
1136static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1137{
1138 switch (iSegReg)
1139 {
1140 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1141 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1142 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1143 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1144 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1145 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1146 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1147 }
1148}
1149
1150
1151/**
1152 * Saves the guest control registers, debug registers and some MSRs are part of
1153 * VM-exit.
1154 *
1155 * @param pVCpu The cross context virtual CPU structure.
1156 */
1157static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1158{
1159 /*
1160 * Saves the guest control registers, debug registers and some MSRs.
1161 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1162 */
1163 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1164
1165 /* Save control registers. */
1166 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1167 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1168 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1169
1170 /* Save SYSENTER CS, ESP, EIP. */
1171 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1172 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1173 {
1174 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1175 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1176 }
1177 else
1178 {
1179 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1180 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1181 }
1182
1183 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1184 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1185 {
1186 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1187 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1188 }
1189
1190 /* Save PAT MSR. */
1191 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1192 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1193
1194 /* Save EFER MSR. */
1195 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1196 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1197
1198 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1199 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1200
1201 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1202}
1203
1204
1205/**
1206 * Saves the guest force-flags in preparation of entering the nested-guest.
1207 *
1208 * @param pVCpu The cross context virtual CPU structure.
1209 */
1210static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1211{
1212 /* We shouldn't be called multiple times during VM-entry. */
1213 Assert(pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit == 0);
1214
1215 /* MTF should not be set outside VMX non-root mode. */
1216 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1217
1218 /*
1219 * Preserve the required force-flags.
1220 *
1221 * We cache and clear force-flags that would affect the execution of the
1222 * nested-guest. Cached flags are then restored while returning to the guest
1223 * if necessary.
1224 *
1225 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1226 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1227 * instruction. Interrupt inhibition for any nested-guest instruction
1228 * is supplied by the guest-interruptibility state VMCS field and will
1229 * be set up as part of loading the guest state. Technically
1230 * blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1231 * disallow it since we can't distinguish it from blocking-by-MovSS
1232 * and no nested-hypervisor we care about uses STI immediately
1233 * followed by VMLAUNCH/VMRESUME.
1234 *
1235 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1236 * successful VM-entry (due to invalid guest-state) need to continue
1237 * blocking NMIs if it was in effect before VM-entry.
1238 *
1239 * - MTF need not be preserved as it's used only in VMX non-root mode and
1240 * is supplied through the VM-execution controls.
1241 *
1242 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1243 * we will be able to generate interrupts that may cause VM-exits for
1244 * the nested-guest.
1245 */
1246 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_INHIBIT_NMI;
1247}
1248
1249
1250/**
1251 * Restores the guest force-flags in preparation of exiting the nested-guest.
1252 *
1253 * @param pVCpu The cross context virtual CPU structure.
1254 */
1255static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1256{
1257 /** @todo r=bird: why aren't we clearing the nested guest flags first here?
1258 * If there is some other code doing that already, it would be great
1259 * to point to it here... */
1260 pVCpu->cpum.GstCtx.eflags.uBoth |= pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit;
1261 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = 0;
1262}
1263
1264
1265/**
1266 * Performs the VMX transition to/from VMX non-root mode.
1267 *
1268 * @param pVCpu The cross context virtual CPU structure.
1269*/
1270static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1271{
1272 /*
1273 * Inform PGM about paging mode changes.
1274 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1275 * see comment in iemMemPageTranslateAndCheckAccess().
1276 */
1277 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1278 true /* fForce */);
1279 if (RT_SUCCESS(rc))
1280 { /* likely */ }
1281 else
1282 return rc;
1283
1284 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1285 IEMTlbInvalidateAll(pVCpu);
1286
1287 /* Inform CPUM (recompiler), can later be removed. */
1288 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1289
1290 /* Re-initialize IEM cache/state after the drastic mode switch. */
1291 iemReInitExec(pVCpu);
1292 return rc;
1293}
1294
1295
1296/**
1297 * Calculates the current VMX-preemption timer value.
1298 *
1299 * @returns The current VMX-preemption timer value.
1300 * @param pVCpu The cross context virtual CPU structure.
1301 */
1302static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1303{
1304 /*
1305 * Assume the following:
1306 * PreemptTimerShift = 5
1307 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1308 * EntryTick = 50000 (TSC at time of VM-entry)
1309 *
1310 * CurTick Delta PreemptTimerVal
1311 * ----------------------------------
1312 * 60000 10000 2
1313 * 80000 30000 1
1314 * 90000 40000 0 -> VM-exit.
1315 *
1316 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1317 * The saved VMX-preemption timer value is calculated as follows:
1318 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1319 * E.g.:
1320 * Delta = 10000
1321 * Tmp = 10000 / (2 * 10000) = 0.5
1322 * NewPt = 2 - 0.5 = 2
1323 * Delta = 30000
1324 * Tmp = 30000 / (2 * 10000) = 1.5
1325 * NewPt = 2 - 1.5 = 1
1326 * Delta = 40000
1327 * Tmp = 40000 / 20000 = 2
1328 * NewPt = 2 - 2 = 0
1329 */
1330 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1331 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1332 if (uVmcsPreemptVal > 0)
1333 {
1334 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1335 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1336 uint64_t const uDelta = uCurTick - uEntryTick;
1337 uint32_t const uPreemptTimer = uVmcsPreemptVal
1338 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1339 return uPreemptTimer;
1340 }
1341 return 0;
1342}
1343
1344
1345/**
1346 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1347 *
1348 * @param pVCpu The cross context virtual CPU structure.
1349 */
1350static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1351{
1352 /*
1353 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1354 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1355 */
1356 /* CS, SS, ES, DS, FS, GS. */
1357 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1358 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1359 {
1360 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1361 if (!pSelReg->Attr.n.u1Unusable)
1362 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1363 else
1364 {
1365 /*
1366 * For unusable segments the attributes are undefined except for CS and SS.
1367 * For the rest we don't bother preserving anything but the unusable bit.
1368 */
1369 switch (iSegReg)
1370 {
1371 case X86_SREG_CS:
1372 pVmcs->GuestCs = pSelReg->Sel;
1373 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1374 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1375 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1376 | X86DESCATTR_UNUSABLE);
1377 break;
1378
1379 case X86_SREG_SS:
1380 pVmcs->GuestSs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1384 break;
1385
1386 case X86_SREG_DS:
1387 pVmcs->GuestDs = pSelReg->Sel;
1388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1389 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1390 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1391 break;
1392
1393 case X86_SREG_ES:
1394 pVmcs->GuestEs = pSelReg->Sel;
1395 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1396 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1397 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1398 break;
1399
1400 case X86_SREG_FS:
1401 pVmcs->GuestFs = pSelReg->Sel;
1402 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1403 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1404 break;
1405
1406 case X86_SREG_GS:
1407 pVmcs->GuestGs = pSelReg->Sel;
1408 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1409 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1410 break;
1411 }
1412 }
1413 }
1414
1415 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1416 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1417 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1418 | X86DESCATTR_UNUSABLE;
1419 /* LDTR. */
1420 {
1421 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1422 pVmcs->GuestLdtr = pSelReg->Sel;
1423 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1424 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1425 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1426 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1427 }
1428
1429 /* TR. */
1430 {
1431 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1432 pVmcs->GuestTr = pSelReg->Sel;
1433 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1434 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1435 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1436 }
1437
1438 /* GDTR. */
1439 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1440 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1441
1442 /* IDTR. */
1443 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1444 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1445}
1446
1447
1448/**
1449 * Saves guest non-register state as part of VM-exit.
1450 *
1451 * @param pVCpu The cross context virtual CPU structure.
1452 * @param uExitReason The VM-exit reason.
1453 */
1454static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1455{
1456 /*
1457 * Save guest non-register state.
1458 * See Intel spec. 27.3.4 "Saving Non-Register State".
1459 */
1460 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1461
1462 /*
1463 * Activity state.
1464 * Most VM-exits will occur in the active state. However, if the first instruction
1465 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1466 * the VM-exit will be from the HLT activity state.
1467 *
1468 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1469 */
1470 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1471 * not? */
1472 EMSTATE const enmActivityState = EMGetState(pVCpu);
1473 switch (enmActivityState)
1474 {
1475 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1476 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1477 }
1478
1479 /*
1480 * Interruptibility-state.
1481 */
1482 /* NMI. */
1483 pVmcs->u32GuestIntrState = 0;
1484 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1485 {
1486 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1487 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1488 }
1489 else
1490 {
1491 if (CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
1492 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1493 }
1494
1495 /* Blocking-by-STI. */
1496 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
1497 { /* probable */}
1498 else
1499 {
1500 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1501 * currently. */
1502 if (pVCpu->cpum.GstCtx.rip == pVCpu->cpum.GstCtx.uRipInhibitInt)
1503 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI; /** @todo r=bird: Why the STI one? MOVSS seems to block more and the one to use. */
1504
1505 /* Clear inhibition unconditionally since we've ensured it isn't set prior to executing VMLAUNCH/VMRESUME. */
1506 CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
1507 }
1508 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1509
1510 /*
1511 * Pending debug exceptions.
1512 *
1513 * For VM-exits where it is not applicable, we can safely zero out the field.
1514 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1515 */
1516 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1517 && uExitReason != VMX_EXIT_SMI
1518 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1519 && !VMXIsVmexitTrapLike(uExitReason))
1520 {
1521 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1522 * block-by-MovSS is in effect. */
1523 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1524 }
1525
1526 /*
1527 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1528 *
1529 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1530 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1531 */
1532 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1533 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1534 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1535
1536 /*
1537 * Save the guest PAE PDPTEs.
1538 */
1539 if ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1540 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
1541 {
1542 /*
1543 * Without EPT or when the nested-guest is not using PAE paging, the values saved
1544 * in the VMCS during VM-exit are undefined. We zero them here for consistency.
1545 */
1546 pVmcs->u64GuestPdpte0.u = 0;
1547 pVmcs->u64GuestPdpte1.u = 0;
1548 pVmcs->u64GuestPdpte2.u = 0;
1549 pVmcs->u64GuestPdpte3.u = 0;
1550 }
1551 else
1552 {
1553 /*
1554 * With EPT and when the nested-guest is using PAE paging, we update the PDPTEs from
1555 * the nested-guest CPU context. Both IEM (Mov CRx) and hardware-assisted execution
1556 * of the nested-guest is expected to have updated them.
1557 */
1558 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1559 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1560 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1561 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1562 }
1563
1564 /* Clear PGM's copy of the EPT pointer for added safety. */
1565 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1566 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1567}
1568
1569
1570/**
1571 * Saves the guest-state as part of VM-exit.
1572 *
1573 * @returns VBox status code.
1574 * @param pVCpu The cross context virtual CPU structure.
1575 * @param uExitReason The VM-exit reason.
1576 */
1577static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1578{
1579 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1580 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1581
1582 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1583 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1584 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1585
1586 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1587}
1588
1589
1590/**
1591 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1592 *
1593 * @returns VBox status code.
1594 * @param pVCpu The cross context virtual CPU structure.
1595 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1596 */
1597static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1598{
1599 /*
1600 * Save guest MSRs.
1601 * See Intel spec. 27.4 "Saving MSRs".
1602 */
1603 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1604 const char * const pszFailure = "VMX-abort";
1605
1606 /*
1607 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1608 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1609 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1610 */
1611 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1612 if (!cMsrs)
1613 return VINF_SUCCESS;
1614
1615 /*
1616 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1617 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1618 * implementation causes a VMX-abort followed by a triple-fault.
1619 */
1620 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1621 if (fIsMsrCountValid)
1622 { /* likely */ }
1623 else
1624 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1625
1626 /*
1627 * Optimization if the nested hypervisor is using the same guest-physical page for both
1628 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1629 */
1630 PVMXAUTOMSR pMsrArea;
1631 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1632 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1633 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1634 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1635 else
1636 {
1637 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1638 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1639 if (RT_SUCCESS(rc))
1640 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1641 else
1642 {
1643 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1644 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1645 }
1646 }
1647
1648 /*
1649 * Update VM-exit MSR store area.
1650 */
1651 PVMXAUTOMSR pMsr = pMsrArea;
1652 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1653 {
1654 if ( !pMsr->u32Reserved
1655 && pMsr->u32Msr != MSR_IA32_SMBASE
1656 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1657 {
1658 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1659 if (rcStrict == VINF_SUCCESS)
1660 continue;
1661
1662 /*
1663 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1664 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1665 * recording the MSR index in the auxiliary info. field and indicated further by our
1666 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1667 * if possible, or come up with a better, generic solution.
1668 */
1669 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1670 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1671 ? kVmxVDiag_Vmexit_MsrStoreRing3
1672 : kVmxVDiag_Vmexit_MsrStore;
1673 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1674 }
1675 else
1676 {
1677 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1678 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1679 }
1680 }
1681
1682 /*
1683 * Commit the VM-exit MSR store are to guest memory.
1684 */
1685 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1686 if (RT_SUCCESS(rc))
1687 return VINF_SUCCESS;
1688
1689 NOREF(uExitReason);
1690 NOREF(pszFailure);
1691
1692 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1693 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1694}
1695
1696
1697/**
1698 * Performs a VMX abort (due to an fatal error during VM-exit).
1699 *
1700 * @returns Strict VBox status code.
1701 * @param pVCpu The cross context virtual CPU structure.
1702 * @param enmAbort The VMX abort reason.
1703 */
1704static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1705{
1706 /*
1707 * Perform the VMX abort.
1708 * See Intel spec. 27.7 "VMX Aborts".
1709 */
1710 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1711
1712 /* We don't support SMX yet. */
1713 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1714 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1715 {
1716 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1717 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1718 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1719 }
1720
1721 return VINF_EM_TRIPLE_FAULT;
1722}
1723
1724
1725/**
1726 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1727 *
1728 * @param pVCpu The cross context virtual CPU structure.
1729 */
1730static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1731{
1732 /*
1733 * Load host control registers, debug registers and MSRs.
1734 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1735 */
1736 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1737 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1738
1739 /* CR0. */
1740 {
1741 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1742 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu);
1743 uint64_t const uCr0Mb0 = VMX_V_CR0_FIXED1;
1744 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1745 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1746 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1747 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1748
1749 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1750 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1751 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1752 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1753 }
1754
1755 /* CR4. */
1756 {
1757 /* CR4 fixed bits are not modified. */
1758 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1759 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1760 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1761 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1762 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1763 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1764 if (fHostInLongMode)
1765 uValidHostCr4 |= X86_CR4_PAE;
1766 else
1767 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1768
1769 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1770 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1771 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1772 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1773 }
1774
1775 /* CR3 (host value validated while checking host-state during VM-entry). */
1776 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1777
1778 /* DR7. */
1779 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1780
1781 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1782
1783 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1784 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1785 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1786 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1787
1788 /* FS, GS bases are loaded later while we load host segment registers. */
1789
1790 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1791 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1792 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1793 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1794 {
1795 if (fHostInLongMode)
1796 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1797 else
1798 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1799 }
1800
1801 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1802
1803 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1804 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1805 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1806
1807 /* We don't support IA32_BNDCFGS MSR yet. */
1808}
1809
1810
1811/**
1812 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1813 *
1814 * @param pVCpu The cross context virtual CPU structure.
1815 */
1816static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1817{
1818 /*
1819 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1820 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1821 *
1822 * Warning! Be careful to not touch fields that are reserved by VT-x,
1823 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1824 */
1825 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1826 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1827
1828 /* CS, SS, ES, DS, FS, GS. */
1829 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1830 {
1831 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1832 bool const fUnusable = RT_BOOL(HostSel == 0);
1833 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1834
1835 /* Selector. */
1836 pSelReg->Sel = HostSel;
1837 pSelReg->ValidSel = HostSel;
1838 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1839
1840 /* Limit. */
1841 pSelReg->u32Limit = 0xffffffff;
1842
1843 /* Base. */
1844 pSelReg->u64Base = 0;
1845
1846 /* Attributes. */
1847 if (iSegReg == X86_SREG_CS)
1848 {
1849 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1850 pSelReg->Attr.n.u1DescType = 1;
1851 pSelReg->Attr.n.u2Dpl = 0;
1852 pSelReg->Attr.n.u1Present = 1;
1853 pSelReg->Attr.n.u1Long = fHostInLongMode;
1854 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1855 pSelReg->Attr.n.u1Granularity = 1;
1856 Assert(!pSelReg->Attr.n.u1Unusable);
1857 Assert(!fUnusable);
1858 }
1859 else
1860 {
1861 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1862 pSelReg->Attr.n.u1DescType = 1;
1863 pSelReg->Attr.n.u2Dpl = 0;
1864 pSelReg->Attr.n.u1Present = 1;
1865 pSelReg->Attr.n.u1DefBig = 1;
1866 pSelReg->Attr.n.u1Granularity = 1;
1867 pSelReg->Attr.n.u1Unusable = fUnusable;
1868 }
1869 }
1870
1871 /* FS base. */
1872 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1873 || fHostInLongMode)
1874 {
1875 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1876 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1877 }
1878
1879 /* GS base. */
1880 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1881 || fHostInLongMode)
1882 {
1883 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1884 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1885 }
1886
1887 /* TR. */
1888 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1889 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1890 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1891 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1892 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1893 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1894 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1895 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1896 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1897 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1898 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1899 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1900 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1901
1902 /* LDTR (Warning! do not touch the base and limits here). */
1903 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1904 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1905 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1906 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1907
1908 /* GDTR. */
1909 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1910 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1911 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1912
1913 /* IDTR.*/
1914 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1915 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1916 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1917}
1918
1919
1920/**
1921 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1922 *
1923 * @returns VBox status code.
1924 * @param pVCpu The cross context virtual CPU structure.
1925 * @param uExitReason The VMX instruction name (for logging purposes).
1926 */
1927static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1928{
1929 /*
1930 * Load host MSRs.
1931 * See Intel spec. 27.6 "Loading MSRs".
1932 */
1933 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1934 const char * const pszFailure = "VMX-abort";
1935
1936 /*
1937 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1938 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1939 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1940 */
1941 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1942 if (!cMsrs)
1943 return VINF_SUCCESS;
1944
1945 /*
1946 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1947 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1948 * implementation causes a VMX-abort followed by a triple-fault.
1949 */
1950 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1951 if (fIsMsrCountValid)
1952 { /* likely */ }
1953 else
1954 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1955
1956 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1957 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1958 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1959 if (RT_SUCCESS(rc))
1960 {
1961 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1962 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1963 {
1964 if ( !pMsr->u32Reserved
1965 && pMsr->u32Msr != MSR_K8_FS_BASE
1966 && pMsr->u32Msr != MSR_K8_GS_BASE
1967 && pMsr->u32Msr != MSR_K6_EFER
1968 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1969 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1970 {
1971 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1972 if (rcStrict == VINF_SUCCESS)
1973 continue;
1974
1975 /*
1976 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1977 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1978 * recording the MSR index in the auxiliary info. field and indicated further by our
1979 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1980 * if possible, or come up with a better, generic solution.
1981 */
1982 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1983 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1984 ? kVmxVDiag_Vmexit_MsrLoadRing3
1985 : kVmxVDiag_Vmexit_MsrLoad;
1986 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1987 }
1988 else
1989 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1990 }
1991 }
1992 else
1993 {
1994 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1995 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1996 }
1997
1998 NOREF(uExitReason);
1999 NOREF(pszFailure);
2000 return VINF_SUCCESS;
2001}
2002
2003
2004/**
2005 * Loads the host state as part of VM-exit.
2006 *
2007 * @returns Strict VBox status code.
2008 * @param pVCpu The cross context virtual CPU structure.
2009 * @param uExitReason The VM-exit reason (for logging purposes).
2010 */
2011static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
2012{
2013 /*
2014 * Load host state.
2015 * See Intel spec. 27.5 "Loading Host State".
2016 */
2017 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2018 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2019
2020 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2021 if ( CPUMIsGuestInLongMode(pVCpu)
2022 && !fHostInLongMode)
2023 {
2024 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2025 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2026 }
2027
2028 /*
2029 * Check host PAE PDPTEs prior to loading the host state.
2030 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2031 */
2032 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2033 && !fHostInLongMode
2034 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2035 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2036 {
2037 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2038 if (RT_SUCCESS(rc))
2039 { /* likely*/ }
2040 else
2041 {
2042 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2043 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2044 }
2045 }
2046
2047 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2048 iemVmxVmexitLoadHostSegRegs(pVCpu);
2049
2050 /*
2051 * Load host RIP, RSP and RFLAGS.
2052 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2053 */
2054 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2055 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2056 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2057
2058 /* Clear address range monitoring. */
2059 EMMonitorWaitClear(pVCpu);
2060
2061 /* Perform the VMX transition (PGM updates). */
2062 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2063 if (rcStrict == VINF_SUCCESS)
2064 { /* likely */ }
2065 else if (RT_SUCCESS(rcStrict))
2066 {
2067 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2068 uExitReason));
2069 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2070 }
2071 else
2072 {
2073 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2074 return VBOXSTRICTRC_VAL(rcStrict);
2075 }
2076
2077 Assert(rcStrict == VINF_SUCCESS);
2078
2079 /* Load MSRs from the VM-exit auto-load MSR area. */
2080 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2081 if (RT_FAILURE(rc))
2082 {
2083 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2084 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2085 }
2086 return VINF_SUCCESS;
2087}
2088
2089
2090/**
2091 * Gets VM-exit instruction information along with any displacement for an
2092 * instruction VM-exit.
2093 *
2094 * @returns The VM-exit instruction information.
2095 * @param pVCpu The cross context virtual CPU structure.
2096 * @param uExitReason The VM-exit reason.
2097 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2098 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2099 * NULL.
2100 */
2101static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2102{
2103 RTGCPTR GCPtrDisp;
2104 VMXEXITINSTRINFO ExitInstrInfo;
2105 ExitInstrInfo.u = 0;
2106
2107 /*
2108 * Get and parse the ModR/M byte from our decoded opcodes.
2109 */
2110 uint8_t bRm;
2111 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2112 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2113 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2114 {
2115 /*
2116 * ModR/M indicates register addressing.
2117 *
2118 * The primary/secondary register operands are reported in the iReg1 or iReg2
2119 * fields depending on whether it is a read/write form.
2120 */
2121 uint8_t idxReg1;
2122 uint8_t idxReg2;
2123 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2124 {
2125 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2126 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2127 }
2128 else
2129 {
2130 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2131 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2132 }
2133 ExitInstrInfo.All.u2Scaling = 0;
2134 ExitInstrInfo.All.iReg1 = idxReg1;
2135 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2136 ExitInstrInfo.All.fIsRegOperand = 1;
2137 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2138 ExitInstrInfo.All.iSegReg = 0;
2139 ExitInstrInfo.All.iIdxReg = 0;
2140 ExitInstrInfo.All.fIdxRegInvalid = 1;
2141 ExitInstrInfo.All.iBaseReg = 0;
2142 ExitInstrInfo.All.fBaseRegInvalid = 1;
2143 ExitInstrInfo.All.iReg2 = idxReg2;
2144
2145 /* Displacement not applicable for register addressing. */
2146 GCPtrDisp = 0;
2147 }
2148 else
2149 {
2150 /*
2151 * ModR/M indicates memory addressing.
2152 */
2153 uint8_t uScale = 0;
2154 bool fBaseRegValid = false;
2155 bool fIdxRegValid = false;
2156 uint8_t iBaseReg = 0;
2157 uint8_t iIdxReg = 0;
2158 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2159 {
2160 /*
2161 * Parse the ModR/M, displacement for 16-bit addressing mode.
2162 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2163 */
2164 uint16_t u16Disp = 0;
2165 uint8_t const offDisp = offModRm + sizeof(bRm);
2166 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2167 {
2168 /* Displacement without any registers. */
2169 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2170 }
2171 else
2172 {
2173 /* Register (index and base). */
2174 switch (bRm & X86_MODRM_RM_MASK)
2175 {
2176 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2177 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2178 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2179 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2180 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2181 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2182 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2183 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2184 }
2185
2186 /* Register + displacement. */
2187 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2188 {
2189 case 0: break;
2190 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2191 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2192 default:
2193 {
2194 /* Register addressing, handled at the beginning. */
2195 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2196 break;
2197 }
2198 }
2199 }
2200
2201 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2202 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2203 }
2204 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2205 {
2206 /*
2207 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2208 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2209 */
2210 uint32_t u32Disp = 0;
2211 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2212 {
2213 /* Displacement without any registers. */
2214 uint8_t const offDisp = offModRm + sizeof(bRm);
2215 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2216 }
2217 else
2218 {
2219 /* Register (and perhaps scale, index and base). */
2220 uint8_t offDisp = offModRm + sizeof(bRm);
2221 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2222 if (iBaseReg == 4)
2223 {
2224 /* An SIB byte follows the ModR/M byte, parse it. */
2225 uint8_t bSib;
2226 uint8_t const offSib = offModRm + sizeof(bRm);
2227 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2228
2229 /* A displacement may follow SIB, update its offset. */
2230 offDisp += sizeof(bSib);
2231
2232 /* Get the scale. */
2233 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2234
2235 /* Get the index register. */
2236 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2237 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2238
2239 /* Get the base register. */
2240 iBaseReg = bSib & X86_SIB_BASE_MASK;
2241 fBaseRegValid = true;
2242 if (iBaseReg == 5)
2243 {
2244 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2245 {
2246 /* Mod is 0 implies a 32-bit displacement with no base. */
2247 fBaseRegValid = false;
2248 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2249 }
2250 else
2251 {
2252 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2253 iBaseReg = X86_GREG_xBP;
2254 }
2255 }
2256 }
2257
2258 /* Register + displacement. */
2259 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2260 {
2261 case 0: /* Handled above */ break;
2262 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2263 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2264 default:
2265 {
2266 /* Register addressing, handled at the beginning. */
2267 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2268 break;
2269 }
2270 }
2271 }
2272
2273 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2274 }
2275 else
2276 {
2277 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2278
2279 /*
2280 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2281 * See Intel instruction spec. 2.2 "IA-32e Mode".
2282 */
2283 uint64_t u64Disp = 0;
2284 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2285 if (fRipRelativeAddr)
2286 {
2287 /*
2288 * RIP-relative addressing mode.
2289 *
2290 * The displacement is 32-bit signed implying an offset range of +/-2G.
2291 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2292 */
2293 uint8_t const offDisp = offModRm + sizeof(bRm);
2294 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2295 }
2296 else
2297 {
2298 uint8_t offDisp = offModRm + sizeof(bRm);
2299
2300 /*
2301 * Register (and perhaps scale, index and base).
2302 *
2303 * REX.B extends the most-significant bit of the base register. However, REX.B
2304 * is ignored while determining whether an SIB follows the opcode. Hence, we
2305 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2306 *
2307 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2308 */
2309 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2310 if (iBaseReg == 4)
2311 {
2312 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2313 uint8_t bSib;
2314 uint8_t const offSib = offModRm + sizeof(bRm);
2315 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2316
2317 /* Displacement may follow SIB, update its offset. */
2318 offDisp += sizeof(bSib);
2319
2320 /* Get the scale. */
2321 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2322
2323 /* Get the index. */
2324 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2325 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2326
2327 /* Get the base. */
2328 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2329 fBaseRegValid = true;
2330 if (iBaseReg == 5)
2331 {
2332 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2333 {
2334 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2335 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2336 }
2337 else
2338 {
2339 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2340 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2341 }
2342 }
2343 }
2344 iBaseReg |= pVCpu->iem.s.uRexB;
2345
2346 /* Register + displacement. */
2347 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2348 {
2349 case 0: /* Handled above */ break;
2350 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2351 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2352 default:
2353 {
2354 /* Register addressing, handled at the beginning. */
2355 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2356 break;
2357 }
2358 }
2359 }
2360
2361 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2362 }
2363
2364 /*
2365 * The primary or secondary register operand is reported in iReg2 depending
2366 * on whether the primary operand is in read/write form.
2367 */
2368 uint8_t idxReg2;
2369 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2370 {
2371 idxReg2 = bRm & X86_MODRM_RM_MASK;
2372 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2373 idxReg2 |= pVCpu->iem.s.uRexB;
2374 }
2375 else
2376 {
2377 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2378 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2379 idxReg2 |= pVCpu->iem.s.uRexReg;
2380 }
2381 ExitInstrInfo.All.u2Scaling = uScale;
2382 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2383 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2384 ExitInstrInfo.All.fIsRegOperand = 0;
2385 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2386 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2387 ExitInstrInfo.All.iIdxReg = iIdxReg;
2388 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2389 ExitInstrInfo.All.iBaseReg = iBaseReg;
2390 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2391 ExitInstrInfo.All.iReg2 = idxReg2;
2392 }
2393
2394 /*
2395 * Handle exceptions to the norm for certain instructions.
2396 * (e.g. some instructions convey an instruction identity in place of iReg2).
2397 */
2398 switch (uExitReason)
2399 {
2400 case VMX_EXIT_GDTR_IDTR_ACCESS:
2401 {
2402 Assert(VMXINSTRID_IS_VALID(uInstrId));
2403 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2404 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2405 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2406 break;
2407 }
2408
2409 case VMX_EXIT_LDTR_TR_ACCESS:
2410 {
2411 Assert(VMXINSTRID_IS_VALID(uInstrId));
2412 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2413 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2414 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2415 break;
2416 }
2417
2418 case VMX_EXIT_RDRAND:
2419 case VMX_EXIT_RDSEED:
2420 {
2421 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2422 break;
2423 }
2424 }
2425
2426 /* Update displacement and return the constructed VM-exit instruction information field. */
2427 if (pGCPtrDisp)
2428 *pGCPtrDisp = GCPtrDisp;
2429
2430 return ExitInstrInfo.u;
2431}
2432
2433
2434/**
2435 * VMX VM-exit handler.
2436 *
2437 * @returns Strict VBox status code.
2438 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2439 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2440 * triple-fault.
2441 *
2442 * @param pVCpu The cross context virtual CPU structure.
2443 * @param uExitReason The VM-exit reason.
2444 * @param u64ExitQual The Exit qualification.
2445 *
2446 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2447 * called. Failures during VM-entry can cause VM-exits as well, so we
2448 * -cannot- assert we're in VMX non-root mode here.
2449 */
2450VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2451{
2452# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2453 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2454 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2455 return VERR_IEM_IPE_7;
2456# else
2457 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2458
2459 /* Just count this as an exit and be done with that. */
2460 pVCpu->iem.s.cPotentialExits++;
2461
2462 /*
2463 * Import all the guest-CPU state.
2464 *
2465 * HM on returning to guest execution would have to reset up a whole lot of state
2466 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2467 * the state and flag reloading the entire state on re-entry. So import the entire
2468 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2469 */
2470 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2471
2472 /*
2473 * Ensure VM-entry interruption information valid bit is cleared.
2474 *
2475 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2476 * by invalid-guest state or machine-check exceptions) also clear this bit.
2477 *
2478 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2479 */
2480 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2481 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2482
2483 /*
2484 * Update the VM-exit reason and Exit qualification.
2485 * Other VMCS read-only data fields are expected to be updated by the caller already.
2486 */
2487 pVmcs->u32RoExitReason = uExitReason;
2488 pVmcs->u64RoExitQual.u = u64ExitQual;
2489
2490 Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2491 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2492 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u));
2493
2494 /*
2495 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2496 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2497 */
2498 {
2499 uint8_t uVector;
2500 uint32_t fFlags;
2501 uint32_t uErrCode;
2502 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2503 if (fInEventDelivery)
2504 {
2505 /*
2506 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2507 * caused by a triple-fault or the original event results in a double-fault that
2508 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2509 * original event information into the IDT-vectoring information fields.
2510 *
2511 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2512 */
2513 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2514 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2515 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2516 {
2517 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2518 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2519 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2520 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2521 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2522 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2523 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2524 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2525 Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2526 pVCpu->cpum.GstCtx.cr2));
2527 }
2528 }
2529 }
2530
2531 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2532 Assert(pVmcs->u64RoIoRcx.u == 0);
2533 Assert(pVmcs->u64RoIoRsi.u == 0);
2534 Assert(pVmcs->u64RoIoRdi.u == 0);
2535 Assert(pVmcs->u64RoIoRip.u == 0);
2536
2537 /*
2538 * Save the guest state back into the VMCS.
2539 * We only need to save the state when the VM-entry was successful.
2540 */
2541 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2542 if (!fVmentryFailed)
2543 {
2544 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2545 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2546 {
2547 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2548 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2549 }
2550
2551 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2552 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2553
2554 /*
2555 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2556 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2557 *
2558 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2559 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2560 * as guest-CPU state would not been modified. Hence for now, we do this only when
2561 * the VM-entry succeeded.
2562 */
2563 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2564 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2565 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2566 {
2567 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2568 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2569 else
2570 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2571 }
2572
2573 /*
2574 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2575 * occurs in enclave mode/SMM which we don't support yet.
2576 *
2577 * If we ever add support for it, we can pass just the lower bits to the functions
2578 * below, till then an assert should suffice.
2579 */
2580 Assert(!RT_HI_U16(uExitReason));
2581
2582 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2583 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2584 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2585 if (RT_SUCCESS(rc))
2586 { /* likely */ }
2587 else
2588 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2589
2590 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2591 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit &= ~CPUMCTX_INHIBIT_NMI;
2592 }
2593 else
2594 {
2595 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2596 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2597 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2598 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2599 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2600 }
2601
2602 /*
2603 * Stop any running VMX-preemption timer if necessary.
2604 */
2605 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2606 CPUMStopGuestVmxPremptTimer(pVCpu);
2607
2608 /*
2609 * Clear any pending VMX nested-guest force-flags.
2610 * These force-flags have no effect on (outer) guest execution and will
2611 * be re-evaluated and setup on the next nested-guest VM-entry.
2612 */
2613 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2614
2615 /*
2616 * We're no longer in nested-guest execution mode.
2617 *
2618 * It is important to do this prior to loading the host state because
2619 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2620 * second-level address translation while switching to host CR3.
2621 */
2622 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2623
2624 /* Restore the host (outer guest) state. */
2625 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2626 if (RT_SUCCESS(rcStrict))
2627 {
2628 Assert(rcStrict == VINF_SUCCESS);
2629 rcStrict = VINF_VMX_VMEXIT;
2630 }
2631 else
2632 Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2633
2634 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2635 {
2636 /* Notify HM that the current VMCS fields have been modified. */
2637 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2638
2639 /* Notify HM that we've completed the VM-exit. */
2640 HMNotifyVmxNstGstVmexit(pVCpu);
2641 }
2642
2643# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2644 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2645 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2646 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2647 if (rcSched != VINF_SUCCESS)
2648 iemSetPassUpStatus(pVCpu, rcSched);
2649# endif
2650 return rcStrict;
2651# endif
2652}
2653
2654
2655/**
2656 * VMX VM-exit handler for VM-exits due to instruction execution.
2657 *
2658 * This is intended for instructions where the caller provides all the relevant
2659 * VM-exit information.
2660 *
2661 * @returns Strict VBox status code.
2662 * @param pVCpu The cross context virtual CPU structure.
2663 * @param pExitInfo Pointer to the VM-exit information.
2664 */
2665static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2666{
2667 /*
2668 * For instructions where any of the following fields are not applicable:
2669 * - Exit qualification must be cleared.
2670 * - VM-exit instruction info. is undefined.
2671 * - Guest-linear address is undefined.
2672 * - Guest-physical address is undefined.
2673 *
2674 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2675 * instruction execution. For VM-exits that are not due to instruction execution this
2676 * field is undefined.
2677 *
2678 * In our implementation in IEM, all undefined fields are generally cleared. However,
2679 * if the caller supplies information (from say the physical CPU directly) it is
2680 * then possible that the undefined fields are not cleared.
2681 *
2682 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2683 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2684 */
2685 Assert(pExitInfo);
2686 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2687 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2688 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2689
2690 /* Update all the relevant fields from the VM-exit instruction information struct. */
2691 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2692 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2693 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2694 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2695
2696 /* Perform the VM-exit. */
2697 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2698}
2699
2700
2701/**
2702 * VMX VM-exit handler for VM-exits due to instruction execution.
2703 *
2704 * This is intended for instructions that only provide the VM-exit instruction
2705 * length.
2706 *
2707 * @param pVCpu The cross context virtual CPU structure.
2708 * @param uExitReason The VM-exit reason.
2709 * @param cbInstr The instruction length in bytes.
2710 */
2711VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2712{
2713#ifdef VBOX_STRICT
2714 /*
2715 * To prevent us from shooting ourselves in the foot.
2716 * The follow instructions should convey more than just the instruction length.
2717 */
2718 switch (uExitReason)
2719 {
2720 case VMX_EXIT_INVEPT:
2721 case VMX_EXIT_INVPCID:
2722 case VMX_EXIT_INVVPID:
2723 case VMX_EXIT_LDTR_TR_ACCESS:
2724 case VMX_EXIT_GDTR_IDTR_ACCESS:
2725 case VMX_EXIT_VMCLEAR:
2726 case VMX_EXIT_VMPTRLD:
2727 case VMX_EXIT_VMPTRST:
2728 case VMX_EXIT_VMREAD:
2729 case VMX_EXIT_VMWRITE:
2730 case VMX_EXIT_VMXON:
2731 case VMX_EXIT_XRSTORS:
2732 case VMX_EXIT_XSAVES:
2733 case VMX_EXIT_RDRAND:
2734 case VMX_EXIT_RDSEED:
2735 case VMX_EXIT_IO_INSTR:
2736 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2737 break;
2738 }
2739#endif
2740
2741 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_INSTR_LEN(uExitReason, cbInstr);
2742 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2743}
2744
2745
2746/**
2747 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2748 *
2749 * @returns Strict VBox status code.
2750 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2751 * @thread EMT(pVCpu)
2752 */
2753VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2754{
2755 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2756 Assert(!pVCpu->iem.s.cActiveMappings);
2757 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2758}
2759
2760
2761/**
2762 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2763 *
2764 * @returns Strict VBox status code.
2765 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2766 * @param uVector The SIPI vector.
2767 * @thread EMT(pVCpu)
2768 */
2769VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2770{
2771 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2772 Assert(!pVCpu->iem.s.cActiveMappings);
2773 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2774}
2775
2776
2777/**
2778 * Interface for HM and EM to emulate a VM-exit.
2779 *
2780 * If a specialized version of a VM-exit handler exists, that must be used instead.
2781 *
2782 * @returns Strict VBox status code.
2783 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2784 * @param uExitReason The VM-exit reason.
2785 * @param u64ExitQual The Exit qualification.
2786 * @thread EMT(pVCpu)
2787 */
2788VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2789{
2790 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2791 Assert(!pVCpu->iem.s.cActiveMappings);
2792 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2793}
2794
2795
2796/**
2797 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2798 *
2799 * This is meant to be used for those instructions that VMX provides additional
2800 * decoding information beyond just the instruction length!
2801 *
2802 * @returns Strict VBox status code.
2803 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2804 * @param pExitInfo Pointer to the VM-exit information.
2805 * @thread EMT(pVCpu)
2806 */
2807VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2808{
2809 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2810 Assert(!pVCpu->iem.s.cActiveMappings);
2811 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2812}
2813
2814
2815/**
2816 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2817 *
2818 * This is meant to be used for those instructions that VMX provides only the
2819 * instruction length.
2820 *
2821 * @returns Strict VBox status code.
2822 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2823 * @param pExitInfo Pointer to the VM-exit information.
2824 * @param cbInstr The instruction length in bytes.
2825 * @thread EMT(pVCpu)
2826 */
2827VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2828{
2829 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2830 Assert(!pVCpu->iem.s.cActiveMappings);
2831 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2832}
2833
2834
2835/**
2836 * VMX VM-exit handler for VM-exits due to instruction execution.
2837 *
2838 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2839 * instruction information and Exit qualification fields.
2840 *
2841 * @param pVCpu The cross context virtual CPU structure.
2842 * @param uExitReason The VM-exit reason.
2843 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2844 * @param cbInstr The instruction length in bytes.
2845 *
2846 * @remarks Do not use this for INS/OUTS instruction.
2847 */
2848VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2849{
2850#ifdef VBOX_STRICT
2851 /*
2852 * To prevent us from shooting ourselves in the foot.
2853 * The follow instructions convey specific info that require using their respective handlers.
2854 */
2855 switch (uExitReason)
2856 {
2857 case VMX_EXIT_INVEPT:
2858 case VMX_EXIT_INVPCID:
2859 case VMX_EXIT_INVVPID:
2860 case VMX_EXIT_LDTR_TR_ACCESS:
2861 case VMX_EXIT_GDTR_IDTR_ACCESS:
2862 case VMX_EXIT_VMCLEAR:
2863 case VMX_EXIT_VMPTRLD:
2864 case VMX_EXIT_VMPTRST:
2865 case VMX_EXIT_VMREAD:
2866 case VMX_EXIT_VMWRITE:
2867 case VMX_EXIT_VMXON:
2868 case VMX_EXIT_XRSTORS:
2869 case VMX_EXIT_XSAVES:
2870 case VMX_EXIT_RDRAND:
2871 case VMX_EXIT_RDSEED:
2872 break;
2873 default:
2874 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2875 break;
2876 }
2877#endif
2878
2879 /*
2880 * Update the Exit qualification field with displacement bytes.
2881 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2882 */
2883 /* Construct the VM-exit instruction information. */
2884 RTGCPTR GCPtrDisp;
2885 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2886
2887 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(uExitReason, GCPtrDisp, uInstrInfo, cbInstr);
2888 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2889}
2890
2891
2892/**
2893 * VMX VM-exit handler for VM-exits due to INVLPG.
2894 *
2895 * @returns Strict VBox status code.
2896 * @param pVCpu The cross context virtual CPU structure.
2897 * @param GCPtrPage The guest-linear address of the page being invalidated.
2898 * @param cbInstr The instruction length in bytes.
2899 */
2900VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2901{
2902 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_INVLPG, GCPtrPage, cbInstr);
2903 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2904 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2905}
2906
2907
2908/**
2909 * VMX VM-exit handler for VM-exits due to LMSW.
2910 *
2911 * @returns Strict VBox status code.
2912 * @param pVCpu The cross context virtual CPU structure.
2913 * @param uGuestCr0 The current guest CR0.
2914 * @param pu16NewMsw The machine-status word specified in LMSW's source
2915 * operand. This will be updated depending on the VMX
2916 * guest/host CR0 mask if LMSW is not intercepted.
2917 * @param GCPtrEffDst The guest-linear address of the source operand in case
2918 * of a memory operand. For register operand, pass
2919 * NIL_RTGCPTR.
2920 * @param cbInstr The instruction length in bytes.
2921 */
2922VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2923 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2924{
2925 Assert(pu16NewMsw);
2926
2927 uint16_t const uNewMsw = *pu16NewMsw;
2928 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2929 {
2930 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2931 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2932 VMXVEXITINFO ExitInfo
2933 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2934 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2935 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2936 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw)
2937 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW),
2938 cbInstr);
2939 if (fMemOperand)
2940 {
2941 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2942 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2943 }
2944 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2945 }
2946
2947 /*
2948 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2949 * CR0 guest/host mask must be left unmodified.
2950 *
2951 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2952 */
2953 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2954 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2955 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2956
2957 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2958}
2959
2960
2961/**
2962 * VMX VM-exit handler for VM-exits due to CLTS.
2963 *
2964 * @returns Strict VBox status code.
2965 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2966 * VM-exit but must not modify the guest CR0.TS bit.
2967 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2968 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2969 * CR0 fixed bits in VMX operation).
2970 * @param pVCpu The cross context virtual CPU structure.
2971 * @param cbInstr The instruction length in bytes.
2972 */
2973VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2974{
2975 /*
2976 * If CR0.TS is owned by the host:
2977 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2978 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2979 * CLTS instruction completes without clearing CR0.TS.
2980 *
2981 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2982 */
2983 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2984 if (fGstHostMask & X86_CR0_TS)
2985 {
2986 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u & X86_CR0_TS)
2987 {
2988 Log2(("clts: Guest intercept -> VM-exit\n"));
2989 VMXVEXITINFO const ExitInfo
2990 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2991 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2992 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
2993 VMX_EXIT_QUAL_CRX_ACCESS_CLTS),
2994 cbInstr);
2995 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2996 }
2997 return VINF_VMX_MODIFIES_BEHAVIOR;
2998 }
2999
3000 /*
3001 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3002 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3003 */
3004 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3005}
3006
3007
3008/**
3009 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3010 * (CR0/CR4 write).
3011 *
3012 * @returns Strict VBox status code.
3013 * @param pVCpu The cross context virtual CPU structure.
3014 * @param iCrReg The control register (either CR0 or CR4).
3015 * @param uGuestCrX The current guest CR0/CR4.
3016 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3017 * VM-exit is caused.
3018 * @param iGReg The general register from which the CR0/CR4 value is being
3019 * loaded.
3020 * @param cbInstr The instruction length in bytes.
3021 */
3022VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3023 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3024{
3025 Assert(puNewCrX);
3026 Assert(iCrReg == 0 || iCrReg == 4);
3027 Assert(iGReg < X86_GREG_COUNT);
3028
3029 uint64_t const uNewCrX = *puNewCrX;
3030 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3031 {
3032 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3033 VMXVEXITINFO const ExitInfo
3034 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3035 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3036 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3037 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3038 cbInstr);
3039 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3040 }
3041
3042 /*
3043 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3044 * must not be modified the instruction.
3045 *
3046 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3047 */
3048 uint64_t uGuestCrX;
3049 uint64_t fGstHostMask;
3050 if (iCrReg == 0)
3051 {
3052 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3053 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3054 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3055 }
3056 else
3057 {
3058 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3059 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3060 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3061 }
3062
3063 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3064 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3065}
3066
3067
3068/**
3069 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3070 *
3071 * @returns VBox strict status code.
3072 * @param pVCpu The cross context virtual CPU structure.
3073 * @param iGReg The general register to which the CR3 value is being stored.
3074 * @param cbInstr The instruction length in bytes.
3075 */
3076VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3077{
3078 Assert(iGReg < X86_GREG_COUNT);
3079 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3080
3081 /*
3082 * If the CR3-store exiting control is set, we must cause a VM-exit.
3083 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3084 */
3085 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3086 {
3087 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3088 VMXVEXITINFO const ExitInfo
3089 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3090 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3091 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3093 cbInstr);
3094 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3095 }
3096 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3097}
3098
3099
3100/**
3101 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3102 *
3103 * @returns VBox strict status code.
3104 * @param pVCpu The cross context virtual CPU structure.
3105 * @param uNewCr3 The new CR3 value.
3106 * @param iGReg The general register from which the CR3 value is being
3107 * loaded.
3108 * @param cbInstr The instruction length in bytes.
3109 */
3110VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3111{
3112 Assert(iGReg < X86_GREG_COUNT);
3113
3114 /*
3115 * If the CR3-load exiting control is set and the new CR3 value does not
3116 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3117 *
3118 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3119 */
3120 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3121 {
3122 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3123 VMXVEXITINFO const ExitInfo
3124 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3125 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3126 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3127 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3128 VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3129 cbInstr);
3130 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3131 }
3132 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3133}
3134
3135
3136/**
3137 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3138 *
3139 * @returns VBox strict status code.
3140 * @param pVCpu The cross context virtual CPU structure.
3141 * @param iGReg The general register to which the CR8 value is being stored.
3142 * @param cbInstr The instruction length in bytes.
3143 */
3144VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3145{
3146 Assert(iGReg < X86_GREG_COUNT);
3147
3148 /*
3149 * If the CR8-store exiting control is set, we must cause a VM-exit.
3150 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3151 */
3152 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3153 {
3154 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3155 VMXVEXITINFO const ExitInfo
3156 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3157 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3158 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3159 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3160 cbInstr);
3161 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3162 }
3163 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3164}
3165
3166
3167/**
3168 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3169 *
3170 * @returns VBox strict status code.
3171 * @param pVCpu The cross context virtual CPU structure.
3172 * @param iGReg The general register from which the CR8 value is being
3173 * loaded.
3174 * @param cbInstr The instruction length in bytes.
3175 */
3176VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3177{
3178 Assert(iGReg < X86_GREG_COUNT);
3179
3180 /*
3181 * If the CR8-load exiting control is set, we must cause a VM-exit.
3182 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3183 */
3184 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3185 {
3186 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3187 VMXVEXITINFO const ExitInfo
3188 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3189 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3190 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3191 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3192 cbInstr);
3193 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3194 }
3195 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3196}
3197
3198
3199/**
3200 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3201 * GReg,DRx' (DRx read).
3202 *
3203 * @returns VBox strict status code.
3204 * @param pVCpu The cross context virtual CPU structure.
3205 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3206 * VMXINSTRID_MOV_FROM_DRX).
3207 * @param iDrReg The debug register being accessed.
3208 * @param iGReg The general register to/from which the DRx value is being
3209 * store/loaded.
3210 * @param cbInstr The instruction length in bytes.
3211 */
3212VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3213 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3214{
3215 Assert(iDrReg <= 7);
3216 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3217 Assert(iGReg < X86_GREG_COUNT);
3218
3219 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3220 {
3221 VMXVEXITINFO const ExitInfo
3222 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_DRX,
3223 RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3224 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg)
3225 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION,
3226 uInstrId == VMXINSTRID_MOV_TO_DRX
3227 ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3228 : VMX_EXIT_QUAL_DRX_DIRECTION_READ),
3229 cbInstr);
3230 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3231 }
3232
3233 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3234}
3235
3236
3237/**
3238 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3239 *
3240 * @returns VBox strict status code.
3241 * @param pVCpu The cross context virtual CPU structure.
3242 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3243 * VMXINSTRID_IO_OUT).
3244 * @param u16Port The I/O port being accessed.
3245 * @param fImm Whether the I/O port was encoded using an immediate operand
3246 * or the implicit DX register.
3247 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3248 * @param cbInstr The instruction length in bytes.
3249 */
3250VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3251 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3252{
3253 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3254 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3255
3256 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3257 {
3258 VMXVEXITINFO const ExitInfo
3259 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_IO_INSTR,
3260 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3261 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3262 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port)
3263 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION,
3264 uInstrId == VMXINSTRID_IO_IN
3265 ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3266 : VMX_EXIT_QUAL_IO_DIRECTION_OUT),
3267 cbInstr);
3268 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3269 }
3270 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3271}
3272
3273
3274/**
3275 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3276 *
3277 * @returns VBox strict status code.
3278 * @param pVCpu The cross context virtual CPU structure.
3279 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3280 * VMXINSTRID_IO_OUTS).
3281 * @param u16Port The I/O port being accessed.
3282 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3283 * @param fRep Whether the instruction has a REP prefix or not.
3284 * @param ExitInstrInfo The VM-exit instruction info. field.
3285 * @param cbInstr The instruction length in bytes.
3286 */
3287VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3288 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3289{
3290 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3291 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3292 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3293 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3294 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3295
3296 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3297 {
3298 /*
3299 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3300 */
3301 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3302 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3303 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3304 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3305 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3306
3307 uint32_t uDirection;
3308 uint64_t uGuestLinearAddr;
3309 if (uInstrId == VMXINSTRID_IO_INS)
3310 {
3311 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3312 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3313 }
3314 else
3315 {
3316 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3317 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3318 }
3319
3320 /*
3321 * If the segment is unusable, the guest-linear address in undefined.
3322 * We shall clear it for consistency.
3323 *
3324 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3325 */
3326 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3327 uGuestLinearAddr = 0;
3328
3329 VMXVEXITINFO const ExitInfo
3330 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(VMX_EXIT_IO_INSTR,
3331 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3332 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3333 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3334 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3335 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING,
3336 VMX_EXIT_QUAL_IO_ENCODING_DX)
3337 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port),
3338 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo
3339 ? ExitInstrInfo.u : 0,
3340 cbInstr,
3341 uGuestLinearAddr);
3342 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3343 }
3344
3345 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3346}
3347
3348
3349/**
3350 * VMX VM-exit handler for VM-exits due to MWAIT.
3351 *
3352 * @returns VBox strict status code.
3353 * @param pVCpu The cross context virtual CPU structure.
3354 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3355 * @param cbInstr The instruction length in bytes.
3356 */
3357VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3358{
3359 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MWAIT, fMonitorHwArmed, cbInstr);
3360 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3361}
3362
3363
3364/**
3365 * VMX VM-exit handler for VM-exits due to PAUSE.
3366 *
3367 * @returns VBox strict status code.
3368 * @param pVCpu The cross context virtual CPU structure.
3369 * @param cbInstr The instruction length in bytes.
3370 */
3371static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3372{
3373 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3374
3375 /*
3376 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3377 * "PAUSE-loop exiting" control.
3378 *
3379 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3380 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3381 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3382 * a VM-exit.
3383 *
3384 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3385 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3386 */
3387 bool fIntercept = false;
3388 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3389 fIntercept = true;
3390 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3391 && pVCpu->iem.s.uCpl == 0)
3392 {
3393 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3394
3395 /*
3396 * A previous-PAUSE-tick value of 0 is used to identify the first time
3397 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3398 * consider this to be the first execution of PAUSE in a loop according
3399 * to the Intel.
3400 *
3401 * All subsequent records for the previous-PAUSE-tick we ensure that it
3402 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3403 */
3404 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3405 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3406 uint64_t const uTick = TMCpuTickGet(pVCpu);
3407 uint32_t const uPleGap = pVmcs->u32PleGap;
3408 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3409 if ( *puPrevPauseTick == 0
3410 || uTick - *puPrevPauseTick > uPleGap)
3411 *puFirstPauseLoopTick = uTick;
3412 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3413 fIntercept = true;
3414
3415 *puPrevPauseTick = uTick | 1;
3416 }
3417
3418 if (fIntercept)
3419 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3420
3421 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3422}
3423
3424
3425/**
3426 * VMX VM-exit handler for VM-exits due to task switches.
3427 *
3428 * @returns VBox strict status code.
3429 * @param pVCpu The cross context virtual CPU structure.
3430 * @param enmTaskSwitch The cause of the task switch.
3431 * @param SelNewTss The selector of the new TSS.
3432 * @param cbInstr The instruction length in bytes.
3433 */
3434VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3435{
3436 /*
3437 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3438 *
3439 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3440 * instruction or delivery of the exception generated by one of these instructions
3441 * lead to a task switch through a task gate in the IDT, we need to provide the
3442 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3443 * leaves the VM-exit instruction length field undefined.
3444 *
3445 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3446 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3447 */
3448 Assert(cbInstr <= 15);
3449
3450 uint8_t uType;
3451 switch (enmTaskSwitch)
3452 {
3453 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3454 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3455 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3456 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3457 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3458 }
3459
3460 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3461 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3462 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3463 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3464}
3465
3466
3467/**
3468 * VMX VM-exit handler for trap-like VM-exits.
3469 *
3470 * @returns VBox strict status code.
3471 * @param pVCpu The cross context virtual CPU structure.
3472 * @param pExitInfo Pointer to the VM-exit information.
3473 * @param pExitEventInfo Pointer to the VM-exit event information.
3474 */
3475static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3476{
3477 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3478 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3479 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3480}
3481
3482
3483/**
3484 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3485 * Virtualized-EOI, TPR-below threshold).
3486 *
3487 * @returns Strict VBox status code.
3488 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3489 * @param pExitInfo Pointer to the VM-exit information.
3490 * @thread EMT(pVCpu)
3491 */
3492VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3493{
3494 Assert(pExitInfo);
3495 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3496 Assert(!pVCpu->iem.s.cActiveMappings);
3497 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3498}
3499
3500
3501/**
3502 * VMX VM-exit handler for VM-exits due to task switches.
3503 *
3504 * This is intended for task switches where the caller provides all the relevant
3505 * VM-exit information.
3506 *
3507 * @returns VBox strict status code.
3508 * @param pVCpu The cross context virtual CPU structure.
3509 * @param pExitInfo Pointer to the VM-exit information.
3510 * @param pExitEventInfo Pointer to the VM-exit event information.
3511 */
3512static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3513 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3514{
3515 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3516 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3517 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3518 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3519 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3520}
3521
3522
3523/**
3524 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3525 *
3526 * @returns Strict VBox status code.
3527 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3528 * @param pExitInfo Pointer to the VM-exit information.
3529 * @param pExitEventInfo Pointer to the VM-exit event information.
3530 * @thread EMT(pVCpu)
3531 */
3532VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3533{
3534 Assert(pExitInfo);
3535 Assert(pExitEventInfo);
3536 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3537 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3538 Assert(!pVCpu->iem.s.cActiveMappings);
3539 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3540}
3541
3542
3543/**
3544 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3545 *
3546 * @returns VBox strict status code.
3547 * @param pVCpu The cross context virtual CPU structure.
3548 */
3549VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3550{
3551 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3552 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3553
3554 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3555 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3556
3557 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3558 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3559 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3560
3561 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3562 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3563}
3564
3565
3566/**
3567 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3568 *
3569 * @returns Strict VBox status code.
3570 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3571 * @thread EMT(pVCpu)
3572 */
3573VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3574{
3575 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3576 Assert(!pVCpu->iem.s.cActiveMappings);
3577 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3578}
3579
3580
3581/**
3582 * VMX VM-exit handler for VM-exits due to external interrupts.
3583 *
3584 * @returns VBox strict status code.
3585 * @param pVCpu The cross context virtual CPU structure.
3586 * @param uVector The external interrupt vector (pass 0 if the interrupt
3587 * is still pending since we typically won't know the
3588 * vector).
3589 * @param fIntPending Whether the external interrupt is pending or
3590 * acknowledged in the interrupt controller.
3591 */
3592static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3593{
3594 Assert(!fIntPending || uVector == 0);
3595
3596 /* The VM-exit is subject to "External interrupt exiting" being set. */
3597 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3598 {
3599 if (fIntPending)
3600 {
3601 /*
3602 * If the interrupt is pending and we don't need to acknowledge the
3603 * interrupt on VM-exit, cause the VM-exit immediately.
3604 *
3605 * See Intel spec 25.2 "Other Causes Of VM Exits".
3606 */
3607 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3608 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3609
3610 /*
3611 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3612 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3613 * acknowledged that the interrupt has been consumed. Callers would have to call
3614 * us again after getting the vector (and ofc, with fIntPending with false).
3615 */
3616 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3617 }
3618
3619 /*
3620 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3621 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3622 * all set, we need to record the vector of the external interrupt in the
3623 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3624 *
3625 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3626 */
3627 uint32_t uExitIntInfo;
3628 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3629 {
3630 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3631 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3632 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3633 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3634 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3635 }
3636 else
3637 uExitIntInfo = 0;
3638 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3639
3640 /*
3641 * Cause the VM-exit whether or not the vector has been stored
3642 * in the VM-exit interruption-information field.
3643 */
3644 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3645 }
3646
3647 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3648}
3649
3650
3651/**
3652 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3653 *
3654 * @returns Strict VBox status code.
3655 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3656 * @param uVector The external interrupt vector (pass 0 if the external
3657 * interrupt is still pending).
3658 * @param fIntPending Whether the external interrupt is pending or
3659 * acknowdledged in the interrupt controller.
3660 * @thread EMT(pVCpu)
3661 */
3662VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3663{
3664 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3665 Assert(!pVCpu->iem.s.cActiveMappings);
3666 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3667}
3668
3669
3670/**
3671 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3672 * an event.
3673 *
3674 * @returns VBox strict status code.
3675 * @param pVCpu The cross context virtual CPU structure.
3676 */
3677VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3678{
3679 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3680 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3681 {
3682 /*
3683 * The NMI-unblocking due to IRET field need not be set for double faults.
3684 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3685 */
3686 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3687 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3688 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3689 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3690 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3691 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3692 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3693 }
3694
3695 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3696}
3697
3698
3699/**
3700 * VMX VM-exit handler for VM-exit due to delivery of an events.
3701 *
3702 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3703 * all the relevant VM-exit information.
3704 *
3705 * @returns VBox strict status code.
3706 * @param pVCpu The cross context virtual CPU structure.
3707 * @param pExitInfo Pointer to the VM-exit information.
3708 * @param pExitEventInfo Pointer to the VM-exit event information.
3709 */
3710static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3711{
3712 Assert(pExitInfo);
3713 Assert(pExitEventInfo);
3714 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3715 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3716
3717 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3718 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3719 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3720 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3721 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3722 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3723}
3724
3725
3726/**
3727 * Interface for HM and EM to emulate VM-exit due to NMIs.
3728 *
3729 * @returns Strict VBox status code.
3730 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3731 * @thread EMT(pVCpu)
3732 */
3733VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3734{
3735 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_ONLY_REASON(VMX_EXIT_XCPT_OR_NMI);
3736 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_INT( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3737 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE,
3738 VMX_EXIT_INT_INFO_TYPE_NMI)
3739 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR,
3740 X86_XCPT_NMI),
3741 0);
3742 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3743 Assert(!pVCpu->iem.s.cActiveMappings);
3744 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3745}
3746
3747
3748/**
3749 * Interface for HM and EM to emulate VM-exit due to exceptions.
3750 *
3751 * Exception includes NMIs, software exceptions (those generated by INT3 or
3752 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3753 *
3754 * @returns Strict VBox status code.
3755 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3756 * @param pExitInfo Pointer to the VM-exit information.
3757 * @param pExitEventInfo Pointer to the VM-exit event information.
3758 * @thread EMT(pVCpu)
3759 */
3760VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3761{
3762 Assert(pExitInfo);
3763 Assert(pExitEventInfo);
3764 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3765 Assert(!pVCpu->iem.s.cActiveMappings);
3766 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3767}
3768
3769
3770/**
3771 * VMX VM-exit handler for VM-exits due to delivery of an event.
3772 *
3773 * @returns VBox strict status code.
3774 * @param pVCpu The cross context virtual CPU structure.
3775 * @param uVector The interrupt / exception vector.
3776 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3777 * @param uErrCode The error code associated with the event.
3778 * @param uCr2 The CR2 value in case of a \#PF exception.
3779 * @param cbInstr The instruction length in bytes.
3780 */
3781VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3782 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3783{
3784 /*
3785 * If the event is being injected as part of VM-entry, it is -not- subject to event
3786 * intercepts in the nested-guest. However, secondary exceptions that occur during
3787 * injection of any event -are- subject to event interception.
3788 *
3789 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3790 */
3791 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3792 {
3793 /*
3794 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3795 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3796 *
3797 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3798 */
3799 if ( uVector == X86_XCPT_NMI
3800 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3801 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3802 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3803 else
3804 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3805
3806 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3807 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3808 }
3809
3810 /*
3811 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3812 * If not, the caller will continue delivery of the external interrupt as it would
3813 * normally. The interrupt is no longer pending in the interrupt controller at this
3814 * point.
3815 */
3816 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3817 {
3818 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3819 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3820 }
3821
3822 /*
3823 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3824 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3825 * interrupts.
3826 */
3827 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3828 bool fIntercept;
3829 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3830 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3831 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3832 else
3833 {
3834 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3835 fIntercept = false;
3836 }
3837
3838 /*
3839 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3840 * relevant VM-exit information and cause the VM-exit.
3841 */
3842 if (fIntercept)
3843 {
3844 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3845
3846 /* Construct the rest of the event related information fields and cause the VM-exit. */
3847 uint64_t u64ExitQual;
3848 if (uVector == X86_XCPT_PF)
3849 {
3850 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3851 u64ExitQual = uCr2;
3852 }
3853 else if (uVector == X86_XCPT_DB)
3854 {
3855 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3856 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3857 }
3858 else
3859 u64ExitQual = 0;
3860
3861 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3862 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3863 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3864 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3865 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3866 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3867 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3868 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3869 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3870 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3871
3872 /*
3873 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3874 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3875 * length.
3876 */
3877 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3878 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3879 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3880 else
3881 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3882
3883 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3884 }
3885
3886 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3887}
3888
3889
3890/**
3891 * VMX VM-exit handler for EPT misconfiguration.
3892 *
3893 * @param pVCpu The cross context virtual CPU structure.
3894 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3895 * This need not be page aligned (e.g. nested-guest in real
3896 * mode).
3897 */
3898static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3899{
3900 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3901 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3902}
3903
3904
3905/**
3906 * VMX VM-exit handler for EPT misconfiguration.
3907 *
3908 * This is intended for EPT misconfigurations where the caller provides all the
3909 * relevant VM-exit information.
3910 *
3911 * @param pVCpu The cross context virtual CPU structure.
3912 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3913 * This need not be page aligned (e.g. nested-guest in real
3914 * mode).
3915 * @param pExitEventInfo Pointer to the VM-exit event information.
3916 */
3917static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3918{
3919 Assert(pExitEventInfo);
3920 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3921 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3922 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3923 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3924 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3925}
3926
3927
3928/**
3929 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3930 *
3931 * @returns Strict VBox status code.
3932 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3933 * @param GCPhysAddr The nested-guest physical address causing the EPT
3934 * misconfiguration.
3935 * @param pExitEventInfo Pointer to the VM-exit event information.
3936 * @thread EMT(pVCpu)
3937 */
3938VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3939{
3940 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3941
3942 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3943 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3944 Assert(!pVCpu->iem.s.cActiveMappings);
3945 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3946}
3947
3948
3949/**
3950 * VMX VM-exit handler for EPT violation.
3951 *
3952 * @param pVCpu The cross context virtual CPU structure.
3953 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3954 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3955 * @param fEptAccess The EPT paging structure bits.
3956 * @param GCPhysAddr The physical address causing the EPT violation. This
3957 * need not be page aligned (e.g. nested-guest in real
3958 * mode).
3959 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3960 * EPT violation. If @c false, GCPtrAddr must be 0.
3961 * @param GCPtrAddr The linear address causing the EPT violation.
3962 * @param cbInstr The VM-exit instruction length.
3963 */
3964static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3965 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3966 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3967{
3968 /*
3969 * If the linear address isn't valid (can happen when loading PDPTEs
3970 * as part of MOV CR execution) the linear address field is undefined.
3971 * While we can leave it this way, it's preferrable to zero it for consistency.
3972 */
3973 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
3974
3975 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3976 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
3977
3978 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
3979 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
3980 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
3981 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3982 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
3983 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
3984 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3985 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3986 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3987 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3988 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
3989
3990 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3991 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3992 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3993 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3994 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3995 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3996 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
3997 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
3998 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3999
4000#ifdef VBOX_STRICT
4001 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4002 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4003 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4004 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4005 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4006 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4007#endif
4008
4009 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4010 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4011 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4012
4013 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4014}
4015
4016
4017/**
4018 * VMX VM-exit handler for EPT violation.
4019 *
4020 * This is intended for EPT violations where the caller provides all the
4021 * relevant VM-exit information.
4022 *
4023 * @returns VBox strict status code.
4024 * @param pVCpu The cross context virtual CPU structure.
4025 * @param pExitInfo Pointer to the VM-exit information.
4026 * @param pExitEventInfo Pointer to the VM-exit event information.
4027 */
4028static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4029 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4030{
4031 Assert(pExitInfo);
4032 Assert(pExitEventInfo);
4033 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4034 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4035
4036 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4037 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4038
4039 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4040 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4041 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4042 else
4043 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4044 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4045 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4046}
4047
4048
4049/**
4050 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4051 *
4052 * @returns Strict VBox status code.
4053 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4054 * @param pExitInfo Pointer to the VM-exit information.
4055 * @param pExitEventInfo Pointer to the VM-exit event information.
4056 * @thread EMT(pVCpu)
4057 */
4058VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4059 PCVMXVEXITEVENTINFO pExitEventInfo)
4060{
4061 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4062
4063 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4064 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4065 Assert(!pVCpu->iem.s.cActiveMappings);
4066 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4067}
4068
4069
4070/**
4071 * VMX VM-exit handler for EPT-induced VM-exits.
4072 *
4073 * @param pVCpu The cross context virtual CPU structure.
4074 * @param pWalk The page walk info.
4075 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4076 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4077 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4078 * applicable.
4079 */
4080VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4081{
4082 Assert(pWalk->fIsSlat);
4083 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4084 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4085 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4086
4087 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4088 {
4089 LogFlow(("EptViolation: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4090 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4091 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4092 pWalk->GCPtr, cbInstr);
4093 }
4094
4095 LogFlow(("EptMisconfig: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4096 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4097 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4098}
4099
4100
4101/**
4102 * VMX VM-exit handler for APIC accesses.
4103 *
4104 * @param pVCpu The cross context virtual CPU structure.
4105 * @param offAccess The offset of the register being accessed.
4106 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4107 */
4108static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4109{
4110 VMXAPICACCESS enmAccess;
4111 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4112 if (fInEventDelivery)
4113 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4114 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4115 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4116 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4117 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4118 else
4119 enmAccess = VMXAPICACCESS_LINEAR_READ;
4120
4121 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4122 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4123 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4124}
4125
4126
4127/**
4128 * VMX VM-exit handler for APIC accesses.
4129 *
4130 * This is intended for APIC accesses where the caller provides all the
4131 * relevant VM-exit information.
4132 *
4133 * @returns VBox strict status code.
4134 * @param pVCpu The cross context virtual CPU structure.
4135 * @param pExitInfo Pointer to the VM-exit information.
4136 * @param pExitEventInfo Pointer to the VM-exit event information.
4137 */
4138static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4139 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4140{
4141 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4142 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4143 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4144 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4145 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4146 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4147 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4148 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4149 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4150}
4151
4152
4153/**
4154 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4155 *
4156 * @returns Strict VBox status code.
4157 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4158 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4159 *
4160 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4161 * @param pExitInfo Pointer to the VM-exit information.
4162 * @param pExitEventInfo Pointer to the VM-exit event information.
4163 * @thread EMT(pVCpu)
4164 */
4165VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4166{
4167 Assert(pExitInfo);
4168 Assert(pExitEventInfo);
4169 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4170 Assert(!pVCpu->iem.s.cActiveMappings);
4171 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4172}
4173
4174
4175/**
4176 * VMX VM-exit handler for APIC-write VM-exits.
4177 *
4178 * @param pVCpu The cross context virtual CPU structure.
4179 * @param offApic The write to the virtual-APIC page offset that caused this
4180 * VM-exit.
4181 */
4182static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4183{
4184 Assert(offApic < XAPIC_OFF_END + 4);
4185 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4186 offApic &= UINT16_C(0xfff);
4187 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4188}
4189
4190
4191/**
4192 * Clears any pending virtual-APIC write emulation.
4193 *
4194 * @returns The virtual-APIC offset that was written before clearing it.
4195 * @param pVCpu The cross context virtual CPU structure.
4196 */
4197DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4198{
4199 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4200 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4201 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4202 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4203 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4204 return offVirtApicWrite;
4205}
4206
4207
4208/**
4209 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4210 *
4211 * @returns The register from the virtual-APIC page.
4212 * @param pVCpu The cross context virtual CPU structure.
4213 * @param offReg The offset of the register being read.
4214 */
4215uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4216{
4217 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4218
4219 uint32_t uReg = 0;
4220 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4221 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4222 AssertMsgStmt(RT_SUCCESS(rc),
4223 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4224 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4225 uReg = 0);
4226 return uReg;
4227}
4228
4229
4230/**
4231 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4232 *
4233 * @returns The register from the virtual-APIC page.
4234 * @param pVCpu The cross context virtual CPU structure.
4235 * @param offReg The offset of the register being read.
4236 */
4237static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4238{
4239 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4240
4241 uint64_t uReg = 0;
4242 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4243 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4244 AssertMsgStmt(RT_SUCCESS(rc),
4245 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4246 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4247 uReg = 0);
4248 return uReg;
4249}
4250
4251
4252/**
4253 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4254 *
4255 * @param pVCpu The cross context virtual CPU structure.
4256 * @param offReg The offset of the register being written.
4257 * @param uReg The register value to write.
4258 */
4259void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4260{
4261 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4262
4263 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4264 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4265 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4266 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4267}
4268
4269
4270/**
4271 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4272 *
4273 * @param pVCpu The cross context virtual CPU structure.
4274 * @param offReg The offset of the register being written.
4275 * @param uReg The register value to write.
4276 */
4277static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4278{
4279 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4280
4281 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4282 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4283 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4284 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4285}
4286
4287
4288/**
4289 * Sets the vector in a virtual-APIC 256-bit sparse register.
4290 *
4291 * @param pVCpu The cross context virtual CPU structure.
4292 * @param offReg The offset of the 256-bit spare register.
4293 * @param uVector The vector to set.
4294 *
4295 * @remarks This is based on our APIC device code.
4296 */
4297static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4298{
4299 /* Determine the vector offset within the chunk. */
4300 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4301
4302 /* Read the chunk at the offset. */
4303 uint32_t uReg;
4304 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4305 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4306 if (RT_SUCCESS(rc))
4307 {
4308 /* Modify the chunk. */
4309 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4310 uReg |= RT_BIT(idxVectorBit);
4311
4312 /* Write the chunk. */
4313 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4314 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4315 uVector, offReg, GCPhysVirtApic, rc));
4316 }
4317 else
4318 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4319 uVector, offReg, GCPhysVirtApic, rc));
4320}
4321
4322
4323/**
4324 * Clears the vector in a virtual-APIC 256-bit sparse register.
4325 *
4326 * @param pVCpu The cross context virtual CPU structure.
4327 * @param offReg The offset of the 256-bit spare register.
4328 * @param uVector The vector to clear.
4329 *
4330 * @remarks This is based on our APIC device code.
4331 */
4332static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4333{
4334 /* Determine the vector offset within the chunk. */
4335 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4336
4337 /* Read the chunk at the offset. */
4338 uint32_t uReg;
4339 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4340 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4341 if (RT_SUCCESS(rc))
4342 {
4343 /* Modify the chunk. */
4344 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4345 uReg &= ~RT_BIT(idxVectorBit);
4346
4347 /* Write the chunk. */
4348 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4349 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4350 uVector, offReg, GCPhysVirtApic, rc));
4351 }
4352 else
4353 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4354 uVector, offReg, GCPhysVirtApic, rc));
4355}
4356
4357
4358/**
4359 * Checks if a memory access to the APIC-access page must causes an APIC-access
4360 * VM-exit.
4361 *
4362 * @param pVCpu The cross context virtual CPU structure.
4363 * @param offAccess The offset of the register being accessed.
4364 * @param cbAccess The size of the access in bytes.
4365 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4366 *
4367 * @remarks This must not be used for MSR-based APIC-access page accesses!
4368 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4369 */
4370static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4371{
4372 Assert(cbAccess > 0);
4373 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4374
4375 /*
4376 * We must cause a VM-exit if any of the following are true:
4377 * - TPR shadowing isn't active.
4378 * - The access size exceeds 32-bits.
4379 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4380 *
4381 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4382 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4383 */
4384 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4385 || cbAccess > sizeof(uint32_t)
4386 || ((offAccess + cbAccess - 1) & 0xc)
4387 || offAccess >= XAPIC_OFF_END + 4)
4388 return true;
4389
4390 /*
4391 * If the access is part of an operation where we have already
4392 * virtualized a virtual-APIC write, we must cause a VM-exit.
4393 */
4394 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4395 return true;
4396
4397 /*
4398 * Check write accesses to the APIC-access page that cause VM-exits.
4399 */
4400 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4401 {
4402 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4403 {
4404 /*
4405 * With APIC-register virtualization, a write access to any of the
4406 * following registers are virtualized. Accessing any other register
4407 * causes a VM-exit.
4408 */
4409 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4410 switch (offAlignedAccess)
4411 {
4412 case XAPIC_OFF_ID:
4413 case XAPIC_OFF_TPR:
4414 case XAPIC_OFF_EOI:
4415 case XAPIC_OFF_LDR:
4416 case XAPIC_OFF_DFR:
4417 case XAPIC_OFF_SVR:
4418 case XAPIC_OFF_ESR:
4419 case XAPIC_OFF_ICR_LO:
4420 case XAPIC_OFF_ICR_HI:
4421 case XAPIC_OFF_LVT_TIMER:
4422 case XAPIC_OFF_LVT_THERMAL:
4423 case XAPIC_OFF_LVT_PERF:
4424 case XAPIC_OFF_LVT_LINT0:
4425 case XAPIC_OFF_LVT_LINT1:
4426 case XAPIC_OFF_LVT_ERROR:
4427 case XAPIC_OFF_TIMER_ICR:
4428 case XAPIC_OFF_TIMER_DCR:
4429 break;
4430 default:
4431 return true;
4432 }
4433 }
4434 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4435 {
4436 /*
4437 * With virtual-interrupt delivery, a write access to any of the
4438 * following registers are virtualized. Accessing any other register
4439 * causes a VM-exit.
4440 *
4441 * Note! The specification does not allow writing to offsets in-between
4442 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4443 */
4444 switch (offAccess)
4445 {
4446 case XAPIC_OFF_TPR:
4447 case XAPIC_OFF_EOI:
4448 case XAPIC_OFF_ICR_LO:
4449 break;
4450 default:
4451 return true;
4452 }
4453 }
4454 else
4455 {
4456 /*
4457 * Without APIC-register virtualization or virtual-interrupt delivery,
4458 * only TPR accesses are virtualized.
4459 */
4460 if (offAccess == XAPIC_OFF_TPR)
4461 { /* likely */ }
4462 else
4463 return true;
4464 }
4465 }
4466 else
4467 {
4468 /*
4469 * Check read accesses to the APIC-access page that cause VM-exits.
4470 */
4471 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4472 {
4473 /*
4474 * With APIC-register virtualization, a read access to any of the
4475 * following registers are virtualized. Accessing any other register
4476 * causes a VM-exit.
4477 */
4478 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4479 switch (offAlignedAccess)
4480 {
4481 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4482 case XAPIC_OFF_ID:
4483 case XAPIC_OFF_VERSION:
4484 case XAPIC_OFF_TPR:
4485 case XAPIC_OFF_EOI:
4486 case XAPIC_OFF_LDR:
4487 case XAPIC_OFF_DFR:
4488 case XAPIC_OFF_SVR:
4489 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4490 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4491 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4492 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4493 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4494 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4495 case XAPIC_OFF_ESR:
4496 case XAPIC_OFF_ICR_LO:
4497 case XAPIC_OFF_ICR_HI:
4498 case XAPIC_OFF_LVT_TIMER:
4499 case XAPIC_OFF_LVT_THERMAL:
4500 case XAPIC_OFF_LVT_PERF:
4501 case XAPIC_OFF_LVT_LINT0:
4502 case XAPIC_OFF_LVT_LINT1:
4503 case XAPIC_OFF_LVT_ERROR:
4504 case XAPIC_OFF_TIMER_ICR:
4505 case XAPIC_OFF_TIMER_DCR:
4506 break;
4507 default:
4508 return true;
4509 }
4510 }
4511 else
4512 {
4513 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4514 if (offAccess == XAPIC_OFF_TPR)
4515 { /* likely */ }
4516 else
4517 return true;
4518 }
4519 }
4520
4521 /* The APIC access is virtualized, does not cause a VM-exit. */
4522 return false;
4523}
4524
4525
4526/**
4527 * Virtualizes a memory-based APIC access by certain instructions even though they
4528 * do not use the address to access memory.
4529 *
4530 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4531 * page-faults but do not use the address to access memory.
4532 *
4533 * @param pVCpu The cross context virtual CPU structure.
4534 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4535 * @param cbAccess The size of the access in bytes.
4536 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4537 */
4538VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4539{
4540 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4541 Assert(pGCPhysAccess);
4542
4543 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4544 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4545 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4546
4547 if (GCPhysAccess == GCPhysApic)
4548 {
4549 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4550 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4551 if (fIntercept)
4552 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4553
4554 *pGCPhysAccess = GCPhysApic | offAccess;
4555 return VINF_VMX_MODIFIES_BEHAVIOR;
4556 }
4557
4558 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4559}
4560
4561
4562/**
4563 * Virtualizes a memory-based APIC access.
4564 *
4565 * @returns VBox strict status code.
4566 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4567 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4568 *
4569 * @param pVCpu The cross context virtual CPU structure.
4570 * @param offAccess The offset of the register being accessed (within the
4571 * APIC-access page).
4572 * @param cbAccess The size of the access in bytes.
4573 * @param pvData Pointer to the data being written or where to store the data
4574 * being read.
4575 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4576 */
4577static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4578 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4579{
4580 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4581 Assert(pvData);
4582
4583 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4584 if (fIntercept)
4585 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4586
4587 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4588 {
4589 /*
4590 * A write access to the APIC-access page that is virtualized (rather than
4591 * causing a VM-exit) writes data to the virtual-APIC page.
4592 */
4593 uint32_t const u32Data = *(uint32_t *)pvData;
4594 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4595
4596 /*
4597 * Record the currently updated APIC offset, as we need this later for figuring
4598 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4599 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4600 *
4601 * After completion of the current operation, we need to perform TPR virtualization,
4602 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4603 *
4604 * The current operation may be a REP-prefixed string instruction, execution of any
4605 * other instruction, or delivery of an event through the IDT.
4606 *
4607 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4608 * performed now but later after completion of the current operation.
4609 *
4610 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4611 */
4612 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4613
4614 LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4615 }
4616 else
4617 {
4618 /*
4619 * A read access from the APIC-access page that is virtualized (rather than
4620 * causing a VM-exit) returns data from the virtual-APIC page.
4621 *
4622 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4623 */
4624 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4625
4626 Assert(cbAccess <= 4);
4627 Assert(offAccess < XAPIC_OFF_END + 4);
4628 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4629
4630 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4631 u32Data &= s_auAccessSizeMasks[cbAccess];
4632 *(uint32_t *)pvData = u32Data;
4633
4634 LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4635 }
4636
4637 return VINF_VMX_MODIFIES_BEHAVIOR;
4638}
4639
4640
4641/**
4642 * Virtualizes an MSR-based APIC read access.
4643 *
4644 * @returns VBox strict status code.
4645 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4646 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4647 * handled by the x2APIC device.
4648 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4649 * not within the range of valid MSRs, caller must raise \#GP(0).
4650 * @param pVCpu The cross context virtual CPU structure.
4651 * @param idMsr The x2APIC MSR being read.
4652 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4653 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4654 */
4655static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4656{
4657 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4658 Assert(pu64Value);
4659
4660 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4661 {
4662 if ( idMsr >= MSR_IA32_X2APIC_START
4663 && idMsr <= MSR_IA32_X2APIC_END)
4664 {
4665 uint16_t const offReg = (idMsr & 0xff) << 4;
4666 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4667 *pu64Value = u64Value;
4668 return VINF_VMX_MODIFIES_BEHAVIOR;
4669 }
4670 return VERR_OUT_OF_RANGE;
4671 }
4672
4673 if (idMsr == MSR_IA32_X2APIC_TPR)
4674 {
4675 uint16_t const offReg = (idMsr & 0xff) << 4;
4676 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4677 *pu64Value = u64Value;
4678 return VINF_VMX_MODIFIES_BEHAVIOR;
4679 }
4680
4681 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4682}
4683
4684
4685/**
4686 * Virtualizes an MSR-based APIC write access.
4687 *
4688 * @returns VBox strict status code.
4689 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4690 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4691 * not within the range of valid MSRs, caller must raise \#GP(0).
4692 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4693 *
4694 * @param pVCpu The cross context virtual CPU structure.
4695 * @param idMsr The x2APIC MSR being written.
4696 * @param u64Value The value of the x2APIC MSR being written.
4697 */
4698static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4699{
4700 /*
4701 * Check if the access is to be virtualized.
4702 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4703 */
4704 if ( idMsr == MSR_IA32_X2APIC_TPR
4705 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4706 && ( idMsr == MSR_IA32_X2APIC_EOI
4707 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4708 {
4709 /* Validate the MSR write depending on the register. */
4710 switch (idMsr)
4711 {
4712 case MSR_IA32_X2APIC_TPR:
4713 case MSR_IA32_X2APIC_SELF_IPI:
4714 {
4715 if (u64Value & UINT64_C(0xffffffffffffff00))
4716 return VERR_OUT_OF_RANGE;
4717 break;
4718 }
4719 case MSR_IA32_X2APIC_EOI:
4720 {
4721 if (u64Value != 0)
4722 return VERR_OUT_OF_RANGE;
4723 break;
4724 }
4725 }
4726
4727 /* Write the MSR to the virtual-APIC page. */
4728 uint16_t const offReg = (idMsr & 0xff) << 4;
4729 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4730
4731 /*
4732 * Record the currently updated APIC offset, as we need this later for figuring
4733 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4734 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4735 */
4736 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4737
4738 return VINF_VMX_MODIFIES_BEHAVIOR;
4739 }
4740
4741 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4742}
4743
4744
4745/**
4746 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4747 *
4748 * @returns Strict VBox status code.
4749 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4750 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4751 * the x2APIC device.
4752 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4753 *
4754 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4755 * @param idMsr The MSR being read.
4756 * @param pu64Value Pointer to the value being written or where to store the
4757 * value being read.
4758 * @param fWrite Whether this is an MSR write or read access.
4759 * @thread EMT(pVCpu)
4760 */
4761VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4762{
4763 Assert(pu64Value);
4764
4765 VBOXSTRICTRC rcStrict;
4766 if (fWrite)
4767 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4768 else
4769 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4770 Assert(!pVCpu->iem.s.cActiveMappings);
4771 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4772
4773}
4774
4775
4776/**
4777 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4778 *
4779 * @returns VBox status code.
4780 * @retval VINF_SUCCESS when the highest set bit is found.
4781 * @retval VERR_NOT_FOUND when no bit is set.
4782 *
4783 * @param pVCpu The cross context virtual CPU structure.
4784 * @param offReg The offset of the APIC 256-bit sparse register.
4785 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4786 * set in the register. Only valid when VINF_SUCCESS is
4787 * returned.
4788 *
4789 * @remarks The format of the 256-bit sparse register here mirrors that found in
4790 * real APIC hardware.
4791 */
4792static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4793{
4794 Assert(offReg < XAPIC_OFF_END + 4);
4795 Assert(pidxHighestBit);
4796
4797 /*
4798 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4799 * However, in each fragment only the first 4 bytes are used.
4800 */
4801 uint8_t const cFrags = 8;
4802 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4803 {
4804 uint16_t const offFrag = iFrag * 16;
4805 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4806 if (!u32Frag)
4807 continue;
4808
4809 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4810 Assert(idxHighestBit > 0);
4811 --idxHighestBit;
4812 Assert(idxHighestBit <= UINT8_MAX);
4813 *pidxHighestBit = idxHighestBit;
4814 return VINF_SUCCESS;
4815 }
4816 return VERR_NOT_FOUND;
4817}
4818
4819
4820/**
4821 * Evaluates pending virtual interrupts.
4822 *
4823 * @param pVCpu The cross context virtual CPU structure.
4824 */
4825static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4826{
4827 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4828
4829 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4830 {
4831 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4832 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4833
4834 if ((uRvi >> 4) > (uPpr >> 4))
4835 {
4836 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4837 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4838 }
4839 else
4840 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4841 }
4842}
4843
4844
4845/**
4846 * Performs PPR virtualization.
4847 *
4848 * @returns VBox strict status code.
4849 * @param pVCpu The cross context virtual CPU structure.
4850 */
4851static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4852{
4853 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4854 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4855
4856 /*
4857 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4858 * or EOI-virtualization.
4859 *
4860 * See Intel spec. 29.1.3 "PPR Virtualization".
4861 */
4862 uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4863 uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4864
4865 uint32_t uPpr;
4866 if ((uTpr & 0xf0) >= uSvi)
4867 uPpr = uTpr;
4868 else
4869 uPpr = uSvi;
4870
4871 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4872 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4873}
4874
4875
4876/**
4877 * Performs VMX TPR virtualization.
4878 *
4879 * @returns VBox strict status code.
4880 * @param pVCpu The cross context virtual CPU structure.
4881 */
4882static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4883{
4884 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4885
4886 /*
4887 * We should have already performed the virtual-APIC write to the TPR offset
4888 * in the virtual-APIC page. We now perform TPR virtualization.
4889 *
4890 * See Intel spec. 29.1.2 "TPR Virtualization".
4891 */
4892 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4893 {
4894 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4895 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4896
4897 /*
4898 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4899 * See Intel spec. 29.1.2 "TPR Virtualization".
4900 */
4901 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4902 {
4903 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4904 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4905 }
4906 }
4907 else
4908 {
4909 iemVmxPprVirtualization(pVCpu);
4910 iemVmxEvalPendingVirtIntrs(pVCpu);
4911 }
4912
4913 return VINF_SUCCESS;
4914}
4915
4916
4917/**
4918 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4919 * not.
4920 *
4921 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4922 * @param pVCpu The cross context virtual CPU structure.
4923 * @param uVector The interrupt that was acknowledged using an EOI.
4924 */
4925static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4926{
4927 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4928 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4929
4930 if (uVector < 64)
4931 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4932 if (uVector < 128)
4933 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4934 if (uVector < 192)
4935 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4936 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4937}
4938
4939
4940/**
4941 * Performs EOI virtualization.
4942 *
4943 * @returns VBox strict status code.
4944 * @param pVCpu The cross context virtual CPU structure.
4945 */
4946static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4947{
4948 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4949 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4950
4951 /*
4952 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4953 * and get the next guest-interrupt that's in-service (if any).
4954 *
4955 * See Intel spec. 29.1.4 "EOI Virtualization".
4956 */
4957 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4958 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4959 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4960
4961 uint8_t uVector = uSvi;
4962 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4963
4964 uVector = 0;
4965 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4966
4967 if (uVector)
4968 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4969 else
4970 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4971
4972 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4973 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4974
4975 iemVmxPprVirtualization(pVCpu);
4976 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4977 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4978 iemVmxEvalPendingVirtIntrs(pVCpu);
4979 return VINF_SUCCESS;
4980}
4981
4982
4983/**
4984 * Performs self-IPI virtualization.
4985 *
4986 * @returns VBox strict status code.
4987 * @param pVCpu The cross context virtual CPU structure.
4988 */
4989static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4990{
4991 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4992 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4993
4994 /*
4995 * We should have already performed the virtual-APIC write to the self-IPI offset
4996 * in the virtual-APIC page. We now perform self-IPI virtualization.
4997 *
4998 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4999 */
5000 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5001 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5002 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5003 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5004 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5005 if (uVector > uRvi)
5006 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5007 iemVmxEvalPendingVirtIntrs(pVCpu);
5008 return VINF_SUCCESS;
5009}
5010
5011
5012/**
5013 * Performs VMX APIC-write emulation.
5014 *
5015 * @returns VBox strict status code.
5016 * @param pVCpu The cross context virtual CPU structure.
5017 */
5018VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5019{
5020 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5021
5022 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5023 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5024
5025 /*
5026 * Perform APIC-write emulation based on the virtual-APIC register written.
5027 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5028 */
5029 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5030 VBOXSTRICTRC rcStrict;
5031 switch (offApicWrite)
5032 {
5033 case XAPIC_OFF_TPR:
5034 {
5035 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5036 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5037 uTpr &= UINT32_C(0x000000ff);
5038 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5039 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5040 rcStrict = iemVmxTprVirtualization(pVCpu);
5041 break;
5042 }
5043
5044 case XAPIC_OFF_EOI:
5045 {
5046 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5047 {
5048 /* Clear VEOI and perform EOI virtualization. */
5049 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5050 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5051 rcStrict = iemVmxEoiVirtualization(pVCpu);
5052 }
5053 else
5054 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5055 break;
5056 }
5057
5058 case XAPIC_OFF_ICR_LO:
5059 {
5060 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5061 {
5062 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5063 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5064 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5065 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5066 if ( !(uIcrLo & fIcrLoMb0)
5067 && (uIcrLo & fIcrLoMb1))
5068 {
5069 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5070 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5071 }
5072 else
5073 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5074 }
5075 else
5076 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5077 break;
5078 }
5079
5080 case XAPIC_OFF_ICR_HI:
5081 {
5082 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5083 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5084 uIcrHi &= UINT32_C(0xff000000);
5085 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5086 rcStrict = VINF_SUCCESS;
5087 break;
5088 }
5089
5090 default:
5091 {
5092 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5093 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5094 break;
5095 }
5096 }
5097
5098 return rcStrict;
5099}
5100
5101
5102/**
5103 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5104 * VM-exit.
5105 *
5106 * @returns Strict VBox status code.
5107 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5108 * @thread EMT(pVCpu)
5109 */
5110VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5111{
5112 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5113 Assert(!pVCpu->iem.s.cActiveMappings);
5114 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5115}
5116
5117
5118/**
5119 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5120 *
5121 * @param pVCpu The cross context virtual CPU structure.
5122 * @param pszInstr The VMX instruction name (for logging purposes).
5123 */
5124DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5125{
5126 /*
5127 * Guest Control Registers, Debug Registers, and MSRs.
5128 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5129 */
5130 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5131 const char * const pszFailure = "VM-exit";
5132 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5133
5134 /* CR0 reserved bits. */
5135 {
5136 /* CR0 MB1 bits. */
5137 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
5138 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5139 { /* likely */ }
5140 else
5141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5142
5143 /* CR0 MBZ bits. */
5144 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5145 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5146 { /* likely */ }
5147 else
5148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5149
5150 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5151 if ( !fUnrestrictedGuest
5152 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5153 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5154 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5155 }
5156
5157 /* CR4 reserved bits. */
5158 {
5159 /* CR4 MB1 bits. */
5160 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5161 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5162 { /* likely */ }
5163 else
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5165
5166 /* CR4 MBZ bits. */
5167 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5168 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5169 { /* likely */ }
5170 else
5171 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5172 }
5173
5174 /* DEBUGCTL MSR. */
5175 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5176 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5177 { /* likely */ }
5178 else
5179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5180
5181 /* 64-bit CPU checks. */
5182 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5183 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5184 {
5185 if (fGstInLongMode)
5186 {
5187 /* PAE must be set. */
5188 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5189 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5190 { /* likely */ }
5191 else
5192 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5193 }
5194 else
5195 {
5196 /* PCIDE should not be set. */
5197 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5198 { /* likely */ }
5199 else
5200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5201 }
5202
5203 /* CR3. */
5204 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5205 { /* likely */ }
5206 else
5207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5208
5209 /* DR7. */
5210 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5211 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5212 { /* likely */ }
5213 else
5214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5215
5216 /* SYSENTER ESP and SYSENTER EIP. */
5217 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5218 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5219 { /* likely */ }
5220 else
5221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5222 }
5223
5224 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5225 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5226
5227 /* PAT MSR. */
5228 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5229 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5230 { /* likely */ }
5231 else
5232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5233
5234 /* EFER MSR. */
5235 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5236 {
5237 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5238 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5239 { /* likely */ }
5240 else
5241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5242
5243 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5244 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5245 if ( fGstLma == fGstInLongMode
5246 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5247 || fGstLma == fGstLme))
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5251 }
5252
5253 /* We don't support IA32_BNDCFGS MSR yet. */
5254 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5255
5256 NOREF(pszInstr);
5257 NOREF(pszFailure);
5258 return VINF_SUCCESS;
5259}
5260
5261
5262/**
5263 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5264 *
5265 * @param pVCpu The cross context virtual CPU structure.
5266 * @param pszInstr The VMX instruction name (for logging purposes).
5267 */
5268DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5269{
5270 /*
5271 * Segment registers.
5272 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5273 */
5274 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5275 const char * const pszFailure = "VM-exit";
5276 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5277 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5278 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5279
5280 /* Selectors. */
5281 if ( !fGstInV86Mode
5282 && !fUnrestrictedGuest
5283 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5284 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5285
5286 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5287 {
5288 CPUMSELREG SelReg;
5289 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5290 if (RT_LIKELY(rc == VINF_SUCCESS))
5291 { /* likely */ }
5292 else
5293 return rc;
5294
5295 /*
5296 * Virtual-8086 mode checks.
5297 */
5298 if (fGstInV86Mode)
5299 {
5300 /* Base address. */
5301 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5302 { /* likely */ }
5303 else
5304 {
5305 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5307 }
5308
5309 /* Limit. */
5310 if (SelReg.u32Limit == 0xffff)
5311 { /* likely */ }
5312 else
5313 {
5314 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5316 }
5317
5318 /* Attribute. */
5319 if (SelReg.Attr.u == 0xf3)
5320 { /* likely */ }
5321 else
5322 {
5323 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5325 }
5326
5327 /* We're done; move to checking the next segment. */
5328 continue;
5329 }
5330
5331 /* Checks done by 64-bit CPUs. */
5332 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5333 {
5334 /* Base address. */
5335 if ( iSegReg == X86_SREG_FS
5336 || iSegReg == X86_SREG_GS)
5337 {
5338 if (X86_IS_CANONICAL(SelReg.u64Base))
5339 { /* likely */ }
5340 else
5341 {
5342 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5343 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5344 }
5345 }
5346 else if (iSegReg == X86_SREG_CS)
5347 {
5348 if (!RT_HI_U32(SelReg.u64Base))
5349 { /* likely */ }
5350 else
5351 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5352 }
5353 else
5354 {
5355 if ( SelReg.Attr.n.u1Unusable
5356 || !RT_HI_U32(SelReg.u64Base))
5357 { /* likely */ }
5358 else
5359 {
5360 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5361 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5362 }
5363 }
5364 }
5365
5366 /*
5367 * Checks outside Virtual-8086 mode.
5368 */
5369 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5370 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5371 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5372 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5373 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5374 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5375 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5376 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5377
5378 /* Code or usable segment. */
5379 if ( iSegReg == X86_SREG_CS
5380 || fUsable)
5381 {
5382 /* Reserved bits (bits 31:17 and bits 11:8). */
5383 if (!(SelReg.Attr.u & 0xfffe0f00))
5384 { /* likely */ }
5385 else
5386 {
5387 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5389 }
5390
5391 /* Descriptor type. */
5392 if (fCodeDataSeg)
5393 { /* likely */ }
5394 else
5395 {
5396 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5397 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5398 }
5399
5400 /* Present. */
5401 if (fPresent)
5402 { /* likely */ }
5403 else
5404 {
5405 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5407 }
5408
5409 /* Granularity. */
5410 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5411 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5412 { /* likely */ }
5413 else
5414 {
5415 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5417 }
5418 }
5419
5420 if (iSegReg == X86_SREG_CS)
5421 {
5422 /* Segment Type and DPL. */
5423 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5424 && fUnrestrictedGuest)
5425 {
5426 if (uDpl == 0)
5427 { /* likely */ }
5428 else
5429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5430 }
5431 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5432 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5433 {
5434 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5435 if (uDpl == AttrSs.n.u2Dpl)
5436 { /* likely */ }
5437 else
5438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5439 }
5440 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5441 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5442 {
5443 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5444 if (uDpl <= AttrSs.n.u2Dpl)
5445 { /* likely */ }
5446 else
5447 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5448 }
5449 else
5450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5451
5452 /* Def/Big. */
5453 if ( fGstInLongMode
5454 && fSegLong)
5455 {
5456 if (uDefBig == 0)
5457 { /* likely */ }
5458 else
5459 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5460 }
5461 }
5462 else if (iSegReg == X86_SREG_SS)
5463 {
5464 /* Segment Type. */
5465 if ( !fUsable
5466 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5467 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5468 { /* likely */ }
5469 else
5470 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5471
5472 /* DPL. */
5473 if (!fUnrestrictedGuest)
5474 {
5475 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5476 { /* likely */ }
5477 else
5478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5479 }
5480 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5481 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5482 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5483 {
5484 if (uDpl == 0)
5485 { /* likely */ }
5486 else
5487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5488 }
5489 }
5490 else
5491 {
5492 /* DS, ES, FS, GS. */
5493 if (fUsable)
5494 {
5495 /* Segment type. */
5496 if (uSegType & X86_SEL_TYPE_ACCESSED)
5497 { /* likely */ }
5498 else
5499 {
5500 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5501 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5502 }
5503
5504 if ( !(uSegType & X86_SEL_TYPE_CODE)
5505 || (uSegType & X86_SEL_TYPE_READ))
5506 { /* likely */ }
5507 else
5508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5509
5510 /* DPL. */
5511 if ( !fUnrestrictedGuest
5512 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5513 {
5514 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5515 { /* likely */ }
5516 else
5517 {
5518 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5519 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5520 }
5521 }
5522 }
5523 }
5524 }
5525
5526 /*
5527 * LDTR.
5528 */
5529 {
5530 CPUMSELREG Ldtr;
5531 Ldtr.Sel = pVmcs->GuestLdtr;
5532 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5533 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5534 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5535
5536 if (!Ldtr.Attr.n.u1Unusable)
5537 {
5538 /* Selector. */
5539 if (!(Ldtr.Sel & X86_SEL_LDT))
5540 { /* likely */ }
5541 else
5542 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5543
5544 /* Base. */
5545 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5546 {
5547 if (X86_IS_CANONICAL(Ldtr.u64Base))
5548 { /* likely */ }
5549 else
5550 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5551 }
5552
5553 /* Attributes. */
5554 /* Reserved bits (bits 31:17 and bits 11:8). */
5555 if (!(Ldtr.Attr.u & 0xfffe0f00))
5556 { /* likely */ }
5557 else
5558 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5559
5560 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5561 { /* likely */ }
5562 else
5563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5564
5565 if (!Ldtr.Attr.n.u1DescType)
5566 { /* likely */ }
5567 else
5568 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5569
5570 if (Ldtr.Attr.n.u1Present)
5571 { /* likely */ }
5572 else
5573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5574
5575 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5576 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5577 { /* likely */ }
5578 else
5579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5580 }
5581 }
5582
5583 /*
5584 * TR.
5585 */
5586 {
5587 CPUMSELREG Tr;
5588 Tr.Sel = pVmcs->GuestTr;
5589 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5590 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5591 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5592
5593 /* Selector. */
5594 if (!(Tr.Sel & X86_SEL_LDT))
5595 { /* likely */ }
5596 else
5597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5598
5599 /* Base. */
5600 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5601 {
5602 if (X86_IS_CANONICAL(Tr.u64Base))
5603 { /* likely */ }
5604 else
5605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5606 }
5607
5608 /* Attributes. */
5609 /* Reserved bits (bits 31:17 and bits 11:8). */
5610 if (!(Tr.Attr.u & 0xfffe0f00))
5611 { /* likely */ }
5612 else
5613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5614
5615 if (!Tr.Attr.n.u1Unusable)
5616 { /* likely */ }
5617 else
5618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5619
5620 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5621 || ( !fGstInLongMode
5622 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5623 { /* likely */ }
5624 else
5625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5626
5627 if (!Tr.Attr.n.u1DescType)
5628 { /* likely */ }
5629 else
5630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5631
5632 if (Tr.Attr.n.u1Present)
5633 { /* likely */ }
5634 else
5635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5636
5637 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5638 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5639 { /* likely */ }
5640 else
5641 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5642 }
5643
5644 NOREF(pszInstr);
5645 NOREF(pszFailure);
5646 return VINF_SUCCESS;
5647}
5648
5649
5650/**
5651 * Checks guest GDTR and IDTR as part of VM-entry.
5652 *
5653 * @param pVCpu The cross context virtual CPU structure.
5654 * @param pszInstr The VMX instruction name (for logging purposes).
5655 */
5656DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5657{
5658 /*
5659 * GDTR and IDTR.
5660 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5661 */
5662 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5663 const char *const pszFailure = "VM-exit";
5664
5665 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5666 {
5667 /* Base. */
5668 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5669 { /* likely */ }
5670 else
5671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5672
5673 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5674 { /* likely */ }
5675 else
5676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5677 }
5678
5679 /* Limit. */
5680 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5681 { /* likely */ }
5682 else
5683 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5684
5685 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5686 { /* likely */ }
5687 else
5688 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5689
5690 NOREF(pszInstr);
5691 NOREF(pszFailure);
5692 return VINF_SUCCESS;
5693}
5694
5695
5696/**
5697 * Checks guest RIP and RFLAGS as part of VM-entry.
5698 *
5699 * @param pVCpu The cross context virtual CPU structure.
5700 * @param pszInstr The VMX instruction name (for logging purposes).
5701 */
5702DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5703{
5704 /*
5705 * RIP and RFLAGS.
5706 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5707 */
5708 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5709 const char *const pszFailure = "VM-exit";
5710 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5711
5712 /* RIP. */
5713 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5714 {
5715 X86DESCATTR AttrCs;
5716 AttrCs.u = pVmcs->u32GuestCsAttr;
5717 if ( !fGstInLongMode
5718 || !AttrCs.n.u1Long)
5719 {
5720 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5721 { /* likely */ }
5722 else
5723 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5724 }
5725
5726 if ( fGstInLongMode
5727 && AttrCs.n.u1Long)
5728 {
5729 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5730 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5731 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5732 { /* likely */ }
5733 else
5734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5735 }
5736 }
5737
5738 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5739 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5740 : pVmcs->u64GuestRFlags.s.Lo;
5741 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5742 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5743 { /* likely */ }
5744 else
5745 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5746
5747 if (!(uGuestRFlags & X86_EFL_VM))
5748 { /* likely */ }
5749 else
5750 {
5751 if ( fGstInLongMode
5752 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5753 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5754 }
5755
5756 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5757 {
5758 if (uGuestRFlags & X86_EFL_IF)
5759 { /* likely */ }
5760 else
5761 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5762 }
5763
5764 NOREF(pszInstr);
5765 NOREF(pszFailure);
5766 return VINF_SUCCESS;
5767}
5768
5769
5770/**
5771 * Checks guest non-register state as part of VM-entry.
5772 *
5773 * @param pVCpu The cross context virtual CPU structure.
5774 * @param pszInstr The VMX instruction name (for logging purposes).
5775 */
5776DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5777{
5778 /*
5779 * Guest non-register state.
5780 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5781 */
5782 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5783 const char *const pszFailure = "VM-exit";
5784
5785 /*
5786 * Activity state.
5787 */
5788 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5789 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5790 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5791 { /* likely */ }
5792 else
5793 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5794
5795 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5796 if ( !AttrSs.n.u2Dpl
5797 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5798 { /* likely */ }
5799 else
5800 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5801
5802 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5803 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5804 {
5805 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5806 { /* likely */ }
5807 else
5808 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5809 }
5810
5811 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5812 {
5813 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5814 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5815 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5816 switch (pVmcs->u32GuestActivityState)
5817 {
5818 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5819 {
5820 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5821 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5822 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5823 && ( uVector == X86_XCPT_DB
5824 || uVector == X86_XCPT_MC))
5825 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5826 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5827 { /* likely */ }
5828 else
5829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5830 break;
5831 }
5832
5833 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5834 {
5835 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5836 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5837 && uVector == X86_XCPT_MC))
5838 { /* likely */ }
5839 else
5840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5841 break;
5842 }
5843
5844 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5845 default:
5846 break;
5847 }
5848 }
5849
5850 /*
5851 * Interruptibility state.
5852 */
5853 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5854 { /* likely */ }
5855 else
5856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5857
5858 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5859 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5860 { /* likely */ }
5861 else
5862 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5863
5864 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5865 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5866 { /* likely */ }
5867 else
5868 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5869
5870 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5871 {
5872 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5873 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5874 {
5875 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5876 { /* likely */ }
5877 else
5878 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5879 }
5880 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5881 {
5882 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5883 { /* likely */ }
5884 else
5885 {
5886 /*
5887 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5888 * We update the Exit qualification only when blocking-by-STI is set
5889 * without blocking-by-MovSS being set. Although in practise it does not
5890 * make much difference since the order of checks are implementation defined.
5891 */
5892 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5893 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5895 }
5896
5897 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5898 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5899 { /* likely */ }
5900 else
5901 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5902 }
5903 }
5904
5905 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5906 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5907 { /* likely */ }
5908 else
5909 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5910
5911 /* We don't support SGX yet. So enclave-interruption must not be set. */
5912 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5913 { /* likely */ }
5914 else
5915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5916
5917 /*
5918 * Pending debug exceptions.
5919 */
5920 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5921 ? pVmcs->u64GuestPendingDbgXcpts.u
5922 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5923 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5924 { /* likely */ }
5925 else
5926 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5927
5928 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5929 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5930 {
5931 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5932 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5933 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5934 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5935
5936 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5937 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5938 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5939 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5940 }
5941
5942 /* We don't support RTM (Real-time Transactional Memory) yet. */
5943 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5944 { /* likely */ }
5945 else
5946 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5947
5948 /*
5949 * VMCS link pointer.
5950 */
5951 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5952 {
5953 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5954 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5955 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5956 { /* likely */ }
5957 else
5958 {
5959 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5960 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5961 }
5962
5963 /* Validate the address. */
5964 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5965 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5966 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5967 { /* likely */ }
5968 else
5969 {
5970 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5972 }
5973 }
5974
5975 NOREF(pszInstr);
5976 NOREF(pszFailure);
5977 return VINF_SUCCESS;
5978}
5979
5980
5981#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5982/**
5983 * Checks guest PDPTEs as part of VM-entry.
5984 *
5985 * @param pVCpu The cross context virtual CPU structure.
5986 * @param pszInstr The VMX instruction name (for logging purposes).
5987 */
5988static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
5989{
5990 /*
5991 * Guest PDPTEs.
5992 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5993 */
5994 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5995 const char * const pszFailure = "VM-exit";
5996
5997 /*
5998 * When EPT is used, we need to validate the PAE PDPTEs provided in the VMCS.
5999 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6000 */
6001 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6002 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6003 {
6004 /* Get PDPTEs from the VMCS. */
6005 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6006 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6007 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6008 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6009 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6010
6011 /* Check validity of the PDPTEs. */
6012 if (PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]))
6013 { /* likely */ }
6014 else
6015 {
6016 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6017 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6018 }
6019 }
6020
6021 NOREF(pszFailure);
6022 NOREF(pszInstr);
6023 return VINF_SUCCESS;
6024}
6025#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6026
6027
6028/**
6029 * Checks guest-state as part of VM-entry.
6030 *
6031 * @returns VBox status code.
6032 * @param pVCpu The cross context virtual CPU structure.
6033 * @param pszInstr The VMX instruction name (for logging purposes).
6034 */
6035static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6036{
6037 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6038 if (RT_SUCCESS(rc))
6039 {
6040 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6041 if (RT_SUCCESS(rc))
6042 {
6043 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6044 if (RT_SUCCESS(rc))
6045 {
6046 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6047 if (RT_SUCCESS(rc))
6048 {
6049 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6050#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6051 if (RT_SUCCESS(rc))
6052 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6053#endif
6054 }
6055 }
6056 }
6057 }
6058 return rc;
6059}
6060
6061
6062/**
6063 * Checks host-state as part of VM-entry.
6064 *
6065 * @returns VBox status code.
6066 * @param pVCpu The cross context virtual CPU structure.
6067 * @param pszInstr The VMX instruction name (for logging purposes).
6068 */
6069static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6070{
6071 /*
6072 * Host Control Registers and MSRs.
6073 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6074 */
6075 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6076 const char * const pszFailure = "VMFail";
6077
6078 /* CR0 reserved bits. */
6079 {
6080 /* CR0 MB1 bits. */
6081 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
6082 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6083 { /* likely */ }
6084 else
6085 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6086
6087 /* CR0 MBZ bits. */
6088 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6089 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6090 { /* likely */ }
6091 else
6092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6093 }
6094
6095 /* CR4 reserved bits. */
6096 {
6097 /* CR4 MB1 bits. */
6098 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6099 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6100 { /* likely */ }
6101 else
6102 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6103
6104 /* CR4 MBZ bits. */
6105 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6106 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6107 { /* likely */ }
6108 else
6109 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6110 }
6111
6112 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6113 {
6114 /* CR3 reserved bits. */
6115 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6116 { /* likely */ }
6117 else
6118 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6119
6120 /* SYSENTER ESP and SYSENTER EIP. */
6121 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6122 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6123 { /* likely */ }
6124 else
6125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6126 }
6127
6128 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6129 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6130
6131 /* PAT MSR. */
6132 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6133 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6134 { /* likely */ }
6135 else
6136 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6137
6138 /* EFER MSR. */
6139 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6140 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6141 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6142 {
6143 if (!(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6144 { /* likely */ }
6145 else
6146 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6147
6148 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6149 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6150 if ( fHostInLongMode == fHostLma
6151 && fHostInLongMode == fHostLme)
6152 { /* likely */ }
6153 else
6154 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6155 }
6156
6157 /*
6158 * Host Segment and Descriptor-Table Registers.
6159 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6160 */
6161 /* Selector RPL and TI. */
6162 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6163 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6164 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6165 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6166 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6167 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6168 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6169 { /* likely */ }
6170 else
6171 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6172
6173 /* CS and TR selectors cannot be 0. */
6174 if ( pVmcs->HostCs
6175 && pVmcs->HostTr)
6176 { /* likely */ }
6177 else
6178 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6179
6180 /* SS cannot be 0 if 32-bit host. */
6181 if ( fHostInLongMode
6182 || pVmcs->HostSs)
6183 { /* likely */ }
6184 else
6185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6186
6187 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6188 {
6189 /* FS, GS, GDTR, IDTR, TR base address. */
6190 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6191 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6192 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6193 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6194 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6195 { /* likely */ }
6196 else
6197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6198 }
6199
6200 /*
6201 * Host address-space size for 64-bit CPUs.
6202 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6203 */
6204 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6205 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6206 {
6207 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6208
6209 /* Logical processor in IA-32e mode. */
6210 if (fCpuInLongMode)
6211 {
6212 if (fHostInLongMode)
6213 {
6214 /* PAE must be set. */
6215 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6219
6220 /* RIP must be canonical. */
6221 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6222 { /* likely */ }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6225 }
6226 else
6227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6228 }
6229 else
6230 {
6231 /* Logical processor is outside IA-32e mode. */
6232 if ( !fGstInLongMode
6233 && !fHostInLongMode)
6234 {
6235 /* PCIDE should not be set. */
6236 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6237 { /* likely */ }
6238 else
6239 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6240
6241 /* The high 32-bits of RIP MBZ. */
6242 if (!pVmcs->u64HostRip.s.Hi)
6243 { /* likely */ }
6244 else
6245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6246 }
6247 else
6248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6249 }
6250 }
6251 else
6252 {
6253 /* Host address-space size for 32-bit CPUs. */
6254 if ( !fGstInLongMode
6255 && !fHostInLongMode)
6256 { /* likely */ }
6257 else
6258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6259 }
6260
6261 NOREF(pszInstr);
6262 NOREF(pszFailure);
6263 return VINF_SUCCESS;
6264}
6265
6266
6267#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6268/**
6269 * Checks the EPT pointer VMCS field as part of VM-entry.
6270 *
6271 * @returns VBox status code.
6272 * @param pVCpu The cross context virtual CPU structure.
6273 * @param uEptPtr The EPT pointer to check.
6274 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6275 * updated on success). Optional, can be NULL.
6276 */
6277static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6278{
6279 VMXVDIAG enmVmxDiag;
6280
6281 /* Reserved bits. */
6282 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6283 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6284 if (uEptPtr & fValidMask)
6285 {
6286 /* Memory Type. */
6287 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6288 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6289 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6290 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6291 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6292 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6293 {
6294 /*
6295 * Page walk length (PML4).
6296 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6297 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6298 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6299 */
6300 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6301 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6302 {
6303 /* Access and dirty bits support in EPT structures. */
6304 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6305 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6306 return VINF_SUCCESS;
6307
6308 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6309 }
6310 else
6311 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6312 }
6313 else
6314 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6315 }
6316 else
6317 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6318
6319 if (penmVmxDiag)
6320 *penmVmxDiag = enmVmxDiag;
6321 return VERR_VMX_VMENTRY_FAILED;
6322}
6323#endif
6324
6325
6326/**
6327 * Checks VMCS controls fields as part of VM-entry.
6328 *
6329 * @returns VBox status code.
6330 * @param pVCpu The cross context virtual CPU structure.
6331 * @param pszInstr The VMX instruction name (for logging purposes).
6332 *
6333 * @remarks This may update secondary-processor based VM-execution control fields
6334 * in the current VMCS if necessary.
6335 */
6336static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6337{
6338 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6339 const char * const pszFailure = "VMFail";
6340 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6341
6342 /*
6343 * VM-execution controls.
6344 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6345 */
6346 {
6347 /* Pin-based VM-execution controls. */
6348 {
6349 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6350 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6351 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6352 { /* likely */ }
6353 else
6354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6355
6356 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6357 { /* likely */ }
6358 else
6359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6360 }
6361
6362 /* Processor-based VM-execution controls. */
6363 {
6364 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6365 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6366 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6367 { /* likely */ }
6368 else
6369 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6370
6371 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6372 { /* likely */ }
6373 else
6374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6375 }
6376
6377 /* Secondary processor-based VM-execution controls. */
6378 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6379 {
6380 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6381 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6382 { /* likely */ }
6383 else
6384 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6385
6386 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6387 { /* likely */ }
6388 else
6389 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6390 }
6391 else
6392 Assert(!pVmcs->u32ProcCtls2);
6393
6394 /* CR3-target count. */
6395 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6396 { /* likely */ }
6397 else
6398 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6399
6400 /* I/O bitmaps physical addresses. */
6401 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6402 {
6403 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6404 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6405 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6406 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6407 { /* likely */ }
6408 else
6409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6410
6411 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6412 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6413 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6414 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6415 { /* likely */ }
6416 else
6417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6418 }
6419
6420 /* MSR bitmap physical address. */
6421 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6422 {
6423 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6424 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6425 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6426 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6427 { /* likely */ }
6428 else
6429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6430 }
6431
6432 /* TPR shadow related controls. */
6433 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6434 {
6435 /* Virtual-APIC page physical address. */
6436 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6437 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6438 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6439 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6440 { /* likely */ }
6441 else
6442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6443
6444 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6445 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6446 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6447 { /* likely */ }
6448 else
6449 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6450
6451 /* The rest done XXX document */
6452 }
6453 else
6454 {
6455 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6456 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6457 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6458 { /* likely */ }
6459 else
6460 {
6461 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6463 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6464 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6465 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6467 }
6468 }
6469
6470 /* NMI exiting and virtual-NMIs. */
6471 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6472 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6473 { /* likely */ }
6474 else
6475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6476
6477 /* Virtual-NMIs and NMI-window exiting. */
6478 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6479 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6480 { /* likely */ }
6481 else
6482 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6483
6484 /* Virtualize APIC accesses. */
6485 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6486 {
6487 /* APIC-access physical address. */
6488 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6489 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6490 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6491 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6492 { /* likely */ }
6493 else
6494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6495
6496 /*
6497 * Disallow APIC-access page and virtual-APIC page from being the same address.
6498 * Note! This is not an Intel requirement, but one imposed by our implementation.
6499 */
6500 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6501 * redirecting accesses between the APIC-access page and the virtual-APIC
6502 * page. If any nested hypervisor requires this, we can implement it later. */
6503 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6504 {
6505 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6506 if (GCPhysVirtApic != GCPhysApicAccess)
6507 { /* likely */ }
6508 else
6509 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6510 }
6511 }
6512
6513 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6514 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6515 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6516 { /* likely */ }
6517 else
6518 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6519
6520 /* Virtual-interrupt delivery requires external interrupt exiting. */
6521 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6522 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6523 { /* likely */ }
6524 else
6525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6526
6527 /* VPID. */
6528 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6529 || pVmcs->u16Vpid != 0)
6530 { /* likely */ }
6531 else
6532 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6533
6534#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6535 /* Extended-Page-Table Pointer (EPTP). */
6536 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6537 {
6538 VMXVDIAG enmVmxDiag;
6539 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6540 if (RT_SUCCESS(rc))
6541 { /* likely */ }
6542 else
6543 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6544 }
6545#else
6546 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6547 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6548#endif
6549 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6550 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6551 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6552 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6553 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6554 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6555
6556 /* VMCS shadowing. */
6557 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6558 {
6559 /* VMREAD-bitmap physical address. */
6560 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6561 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6562 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6563 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6564 { /* likely */ }
6565 else
6566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6567
6568 /* VMWRITE-bitmap physical address. */
6569 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6570 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6571 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6572 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6573 { /* likely */ }
6574 else
6575 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6576 }
6577 }
6578
6579 /*
6580 * VM-exit controls.
6581 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6582 */
6583 {
6584 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6585 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6586 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6587 { /* likely */ }
6588 else
6589 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6590
6591 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6592 { /* likely */ }
6593 else
6594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6595
6596 /* Save preemption timer without activating it. */
6597 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6598 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6599 { /* likely */ }
6600 else
6601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6602
6603 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6604 if (pVmcs->u32ExitMsrStoreCount)
6605 {
6606 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6607 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6608 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6609 { /* likely */ }
6610 else
6611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6612 }
6613
6614 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6615 if (pVmcs->u32ExitMsrLoadCount)
6616 {
6617 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6618 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6619 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6620 { /* likely */ }
6621 else
6622 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6623 }
6624 }
6625
6626 /*
6627 * VM-entry controls.
6628 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6629 */
6630 {
6631 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6632 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6633 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6634 { /* likely */ }
6635 else
6636 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6637
6638 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6639 { /* likely */ }
6640 else
6641 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6642
6643 /* Event injection. */
6644 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6645 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6646 {
6647 /* Type and vector. */
6648 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6649 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6650 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6651 if ( !uRsvd
6652 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6653 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6654 { /* likely */ }
6655 else
6656 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6657
6658 /* Exception error code. */
6659 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6660 {
6661 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6662 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6663 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6664 { /* likely */ }
6665 else
6666 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6667
6668 /* Exceptions that provide an error code. */
6669 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6670 && ( uVector == X86_XCPT_DF
6671 || uVector == X86_XCPT_TS
6672 || uVector == X86_XCPT_NP
6673 || uVector == X86_XCPT_SS
6674 || uVector == X86_XCPT_GP
6675 || uVector == X86_XCPT_PF
6676 || uVector == X86_XCPT_AC))
6677 { /* likely */ }
6678 else
6679 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6680
6681 /* Exception error-code reserved bits. */
6682 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6683 { /* likely */ }
6684 else
6685 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6686
6687 /* Injecting a software interrupt, software exception or privileged software exception. */
6688 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6689 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6690 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6691 {
6692 /* Instruction length must be in the range 0-15. */
6693 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6694 { /* likely */ }
6695 else
6696 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6697
6698 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6699 if ( pVmcs->u32EntryInstrLen != 0
6700 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6701 { /* likely */ }
6702 else
6703 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6704 }
6705 }
6706 }
6707
6708 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6709 if (pVmcs->u32EntryMsrLoadCount)
6710 {
6711 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6712 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6713 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6714 { /* likely */ }
6715 else
6716 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6717 }
6718
6719 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6720 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6721 }
6722
6723 NOREF(pszInstr);
6724 NOREF(pszFailure);
6725 return VINF_SUCCESS;
6726}
6727
6728
6729/**
6730 * Loads the guest control registers, debug register and some MSRs as part of
6731 * VM-entry.
6732 *
6733 * @param pVCpu The cross context virtual CPU structure.
6734 */
6735static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6736{
6737 /*
6738 * Load guest control registers, debug registers and MSRs.
6739 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6740 */
6741 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6742
6743 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6744 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6745 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6746 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6747 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6748 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6749
6750 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6751 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6752
6753 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6754 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6755 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6756
6757 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6758 {
6759 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6760
6761 /* EFER MSR. */
6762 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6763 {
6764 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6765 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6766 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6767 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6768 if (fGstInLongMode)
6769 {
6770 /* If the nested-guest is in long mode, LMA and LME are both set. */
6771 Assert(fGstPaging);
6772 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6773 }
6774 else
6775 {
6776 /*
6777 * If the nested-guest is outside long mode:
6778 * - With paging: LMA is cleared, LME is cleared.
6779 * - Without paging: LMA is cleared, LME is left unmodified.
6780 */
6781 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6782 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6783 }
6784 }
6785 /* else: see below. */
6786 }
6787
6788 /* PAT MSR. */
6789 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6790 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6791
6792 /* EFER MSR. */
6793 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6794 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6795
6796 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6797 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6798
6799 /* We don't support IA32_BNDCFGS MSR yet. */
6800 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6801
6802 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6803}
6804
6805
6806/**
6807 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6808 *
6809 * @param pVCpu The cross context virtual CPU structure.
6810 */
6811static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6812{
6813 /*
6814 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6815 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6816 */
6817 /* CS, SS, ES, DS, FS, GS. */
6818 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6819 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6820 {
6821 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6822 CPUMSELREG VmcsSelReg;
6823 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6824 AssertRC(rc); NOREF(rc);
6825 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6826 {
6827 pGstSelReg->Sel = VmcsSelReg.Sel;
6828 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6829 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6830 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6831 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6832 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6833 }
6834 else
6835 {
6836 pGstSelReg->Sel = VmcsSelReg.Sel;
6837 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6838 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6839 switch (iSegReg)
6840 {
6841 case X86_SREG_CS:
6842 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6843 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6844 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6845 break;
6846
6847 case X86_SREG_SS:
6848 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6849 pGstSelReg->u32Limit = 0;
6850 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6851 break;
6852
6853 case X86_SREG_ES:
6854 case X86_SREG_DS:
6855 pGstSelReg->u64Base = 0;
6856 pGstSelReg->u32Limit = 0;
6857 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6858 break;
6859
6860 case X86_SREG_FS:
6861 case X86_SREG_GS:
6862 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6863 pGstSelReg->u32Limit = 0;
6864 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6865 break;
6866 }
6867 Assert(pGstSelReg->Attr.n.u1Unusable);
6868 }
6869 }
6870
6871 /* LDTR. */
6872 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6873 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6874 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6875 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6876 {
6877 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6878 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6879 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6880 }
6881 else
6882 {
6883 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6884 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6885 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6886 }
6887
6888 /* TR. */
6889 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6890 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6891 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6892 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6893 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6894 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6895 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6896
6897 /* GDTR. */
6898 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6899 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6900
6901 /* IDTR. */
6902 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6903 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6904}
6905
6906
6907/**
6908 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6909 *
6910 * @returns VBox status code.
6911 * @param pVCpu The cross context virtual CPU structure.
6912 * @param pszInstr The VMX instruction name (for logging purposes).
6913 */
6914static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6915{
6916 /*
6917 * Load guest MSRs.
6918 * See Intel spec. 26.4 "Loading MSRs".
6919 */
6920 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6921 const char *const pszFailure = "VM-exit";
6922
6923 /*
6924 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6925 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6926 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6927 */
6928 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6929 if (!cMsrs)
6930 return VINF_SUCCESS;
6931
6932 /*
6933 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6934 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6935 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6936 */
6937 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6938 if (fIsMsrCountValid)
6939 { /* likely */ }
6940 else
6941 {
6942 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6943 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6944 }
6945
6946 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6947 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6948 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6949 if (RT_SUCCESS(rc))
6950 {
6951 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6952 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6953 {
6954 if ( !pMsr->u32Reserved
6955 && pMsr->u32Msr != MSR_K8_FS_BASE
6956 && pMsr->u32Msr != MSR_K8_GS_BASE
6957 && pMsr->u32Msr != MSR_K6_EFER
6958 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6959 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6960 {
6961 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6962 if (rcStrict == VINF_SUCCESS)
6963 continue;
6964
6965 /*
6966 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6967 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6968 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6969 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6970 * MSR in ring-0 if possible, or come up with a better, generic solution.
6971 */
6972 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6973 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6974 ? kVmxVDiag_Vmentry_MsrLoadRing3
6975 : kVmxVDiag_Vmentry_MsrLoad;
6976 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6977 }
6978 else
6979 {
6980 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6981 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6982 }
6983 }
6984 }
6985 else
6986 {
6987 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6988 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6989 }
6990
6991 NOREF(pszInstr);
6992 NOREF(pszFailure);
6993 return VINF_SUCCESS;
6994}
6995
6996
6997/**
6998 * Loads the guest-state non-register state as part of VM-entry.
6999 *
7000 * @returns VBox status code.
7001 * @param pVCpu The cross context virtual CPU structure.
7002 * @param pszInstr The VMX instruction name (for logging purposes).
7003 *
7004 * @remarks This must be called only after loading the nested-guest register state
7005 * (especially nested-guest RIP).
7006 */
7007static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7008{
7009 /*
7010 * Load guest non-register state.
7011 * See Intel spec. 26.6 "Special Features of VM Entry"
7012 */
7013 const char *const pszFailure = "VM-exit";
7014 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7015
7016 /*
7017 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7018 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7019 *
7020 * See Intel spec. 26.6.1 "Interruptibility State".
7021 */
7022 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7023 if ( !fEntryVectoring
7024 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7025 CPUMSetInInterruptShadowEx(&pVCpu->cpum.GstCtx, pVmcs->u64GuestRip.u);
7026 else
7027 Assert(!CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx));
7028
7029 /* NMI blocking. */
7030 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7031 {
7032 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7033 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7034 else
7035 {
7036 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7037 CPUMSetInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
7038 }
7039 }
7040 else
7041 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7042
7043 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7044
7045 /*
7046 * Set PGM's copy of the EPT pointer.
7047 * The EPTP has already been validated while checking guest state.
7048 *
7049 * It is important to do this prior to mapping PAE PDPTEs (below).
7050 */
7051 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7052 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7053
7054 /*
7055 * Load the guest's PAE PDPTEs.
7056 */
7057 if (!iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7058 {
7059 /*
7060 * When PAE paging is not used we clear the PAE PDPTEs for safety
7061 * in case we might be switching from a PAE host to a non-PAE guest.
7062 */
7063 pVCpu->cpum.GstCtx.aPaePdpes[0].u = 0;
7064 pVCpu->cpum.GstCtx.aPaePdpes[1].u = 0;
7065 pVCpu->cpum.GstCtx.aPaePdpes[2].u = 0;
7066 pVCpu->cpum.GstCtx.aPaePdpes[3].u = 0;
7067 }
7068 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7069 {
7070 /*
7071 * With EPT and the nested-guest using PAE paging, we've already validated the PAE PDPTEs
7072 * while checking the guest state. We can load them into the nested-guest CPU state now.
7073 * They'll later be used while mapping CR3 and the PAE PDPTEs.
7074 */
7075 pVCpu->cpum.GstCtx.aPaePdpes[0].u = pVmcs->u64GuestPdpte0.u;
7076 pVCpu->cpum.GstCtx.aPaePdpes[1].u = pVmcs->u64GuestPdpte1.u;
7077 pVCpu->cpum.GstCtx.aPaePdpes[2].u = pVmcs->u64GuestPdpte2.u;
7078 pVCpu->cpum.GstCtx.aPaePdpes[3].u = pVmcs->u64GuestPdpte3.u;
7079 }
7080 else
7081 {
7082 /*
7083 * Without EPT and the nested-guest using PAE paging, we must load the PAE PDPTEs
7084 * referenced by CR3. This involves loading (and mapping) CR3 and validating them now.
7085 */
7086 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7087 if (RT_SUCCESS(rc))
7088 { /* likely */ }
7089 else
7090 {
7091 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7093 }
7094 }
7095
7096 /* VPID is irrelevant. We don't support VPID yet. */
7097
7098 /* Clear address-range monitoring. */
7099 EMMonitorWaitClear(pVCpu);
7100
7101 return VINF_SUCCESS;
7102}
7103
7104
7105/**
7106 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7107 *
7108 * @param pVCpu The cross context virtual CPU structure.
7109 * @param pszInstr The VMX instruction name (for logging purposes).
7110 *
7111 * @remarks This assumes various VMCS related data structure pointers have already
7112 * been verified prior to calling this function.
7113 */
7114static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7115{
7116 const char *const pszFailure = "VM-exit";
7117 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7118
7119 /*
7120 * Virtualize APIC accesses.
7121 */
7122 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7123 {
7124 /* APIC-access physical address. */
7125 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7126
7127 /*
7128 * Register the handler for the APIC-access page.
7129 *
7130 * We don't deregister the APIC-access page handler during the VM-exit as a different
7131 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7132 *
7133 * We leave the page registered until the first access that happens outside VMX non-root
7134 * mode. Guest software is allowed to access structures such as the APIC-access page
7135 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7136 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7137 *
7138 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7139 */
7140 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
7141 {
7142 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7143 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess | X86_PAGE_4K_OFFSET_MASK,
7144 pVM->iem.s.hVmxApicAccessPage, 0 /*uUser*/, NULL /*pszDesc*/);
7145 if (RT_SUCCESS(rc))
7146 { /* likely */ }
7147 else
7148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7149 }
7150 }
7151
7152 /*
7153 * VMCS shadowing.
7154 */
7155 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7156 {
7157 /* Read the VMREAD-bitmap. */
7158 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7159 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7160 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7161 if (RT_SUCCESS(rc))
7162 { /* likely */ }
7163 else
7164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7165
7166 /* Read the VMWRITE-bitmap. */
7167 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7168 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7169 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7170 if (RT_SUCCESS(rc))
7171 { /* likely */ }
7172 else
7173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7174 }
7175
7176 /*
7177 * I/O bitmaps.
7178 */
7179 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7180 {
7181 /* Read the IO bitmap A. */
7182 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7183 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7184 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7185 if (RT_SUCCESS(rc))
7186 { /* likely */ }
7187 else
7188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7189
7190 /* Read the IO bitmap B. */
7191 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7192 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7193 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7194 if (RT_SUCCESS(rc))
7195 { /* likely */ }
7196 else
7197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7198 }
7199
7200 /*
7201 * TPR shadow and Virtual-APIC page.
7202 */
7203 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7204 {
7205 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7206 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7207 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7208 {
7209 /* Read the VTPR from the virtual-APIC page. */
7210 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7211 uint8_t u8VTpr;
7212 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7213 if (RT_SUCCESS(rc))
7214 { /* likely */ }
7215 else
7216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7217
7218 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7219 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7220 { /* likely */ }
7221 else
7222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7223 }
7224 }
7225
7226 /*
7227 * VMCS link pointer.
7228 */
7229 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7230 {
7231 /* Read the VMCS-link pointer from guest memory. */
7232 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7233 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7234 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7235 if (RT_SUCCESS(rc))
7236 { /* likely */ }
7237 else
7238 {
7239 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7241 }
7242
7243 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7244 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7245 { /* likely */ }
7246 else
7247 {
7248 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7250 }
7251
7252 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7253 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7254 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7255 { /* likely */ }
7256 else
7257 {
7258 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7260 }
7261
7262 /* Update our cache of the guest physical address of the shadow VMCS. */
7263 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7264 }
7265
7266 /*
7267 * MSR bitmap.
7268 */
7269 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7270 {
7271 /* Read the MSR bitmap. */
7272 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7273 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7274 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7275 if (RT_SUCCESS(rc))
7276 { /* likely */ }
7277 else
7278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7279 }
7280
7281 NOREF(pszFailure);
7282 NOREF(pszInstr);
7283 return VINF_SUCCESS;
7284}
7285
7286
7287/**
7288 * Loads the guest-state as part of VM-entry.
7289 *
7290 * @returns VBox status code.
7291 * @param pVCpu The cross context virtual CPU structure.
7292 * @param pszInstr The VMX instruction name (for logging purposes).
7293 *
7294 * @remarks This must be done after all the necessary steps prior to loading of
7295 * guest-state (e.g. checking various VMCS state).
7296 */
7297static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7298{
7299 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7300 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7301
7302 /* Load guest segment registers. */
7303 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7304
7305 /*
7306 * Load guest RIP, RSP and RFLAGS.
7307 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7308 */
7309 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7310 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7311 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7312 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7313
7314 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7315 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7316 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7317
7318 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7319 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7320 if (rc == VINF_SUCCESS)
7321 { /* likely */ }
7322 else
7323 return rc;
7324
7325 /* Load VMX related structures and state referenced by the VMCS. */
7326 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7327 if (rc == VINF_SUCCESS)
7328 { /* likely */ }
7329 else
7330 return rc;
7331
7332 NOREF(pszInstr);
7333 return VINF_SUCCESS;
7334}
7335
7336
7337/**
7338 * Returns whether there are is a pending debug exception on VM-entry.
7339 *
7340 * @param pVCpu The cross context virtual CPU structure.
7341 * @param pszInstr The VMX instruction name (for logging purposes).
7342 */
7343static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7344{
7345 /*
7346 * Pending debug exceptions.
7347 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7348 */
7349 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7350 Assert(pVmcs);
7351
7352 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7353 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7354 if (fPendingDbgXcpt)
7355 {
7356 uint8_t uEntryIntInfoType;
7357 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7358 if (fEntryVectoring)
7359 {
7360 switch (uEntryIntInfoType)
7361 {
7362 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7363 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7364 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7365 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7366 fPendingDbgXcpt = false;
7367 break;
7368
7369 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7370 {
7371 /*
7372 * Whether the pending debug exception for software exceptions other than
7373 * #BP and #OF is delivered after injecting the exception or is discard
7374 * is CPU implementation specific. We will discard them (easier).
7375 */
7376 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7377 if ( uVector != X86_XCPT_BP
7378 && uVector != X86_XCPT_OF)
7379 fPendingDbgXcpt = false;
7380 RT_FALL_THRU();
7381 }
7382 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7383 {
7384 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7385 fPendingDbgXcpt = false;
7386 break;
7387 }
7388 }
7389 }
7390 else
7391 {
7392 /*
7393 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7394 * pending debug exception is held pending or is discarded is CPU implementation
7395 * specific. We will discard them (easier).
7396 */
7397 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7398 fPendingDbgXcpt = false;
7399
7400 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7401 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7402 fPendingDbgXcpt = false;
7403 }
7404 }
7405
7406 NOREF(pszInstr);
7407 return fPendingDbgXcpt;
7408}
7409
7410
7411/**
7412 * Set up the monitor-trap flag (MTF).
7413 *
7414 * @param pVCpu The cross context virtual CPU structure.
7415 * @param pszInstr The VMX instruction name (for logging purposes).
7416 */
7417static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7418{
7419 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7420 Assert(pVmcs);
7421 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7422 {
7423 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7424 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7425 }
7426 else
7427 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7428 NOREF(pszInstr);
7429}
7430
7431
7432/**
7433 * Sets up NMI-window exiting.
7434 *
7435 * @param pVCpu The cross context virtual CPU structure.
7436 * @param pszInstr The VMX instruction name (for logging purposes).
7437 */
7438static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7439{
7440 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7441 Assert(pVmcs);
7442 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7443 {
7444 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7445 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7446 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7447 }
7448 else
7449 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7450 NOREF(pszInstr);
7451}
7452
7453
7454/**
7455 * Sets up interrupt-window exiting.
7456 *
7457 * @param pVCpu The cross context virtual CPU structure.
7458 * @param pszInstr The VMX instruction name (for logging purposes).
7459 */
7460static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7461{
7462 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7463 Assert(pVmcs);
7464 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7465 {
7466 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7467 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7468 }
7469 else
7470 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7471 NOREF(pszInstr);
7472}
7473
7474
7475/**
7476 * Set up the VMX-preemption timer.
7477 *
7478 * @param pVCpu The cross context virtual CPU structure.
7479 * @param pszInstr The VMX instruction name (for logging purposes).
7480 */
7481static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7482{
7483 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7484 Assert(pVmcs);
7485 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7486 {
7487 /*
7488 * If the timer is 0, we must cause a VM-exit before executing the first
7489 * nested-guest instruction. So we can flag as though the timer has already
7490 * expired and we will check and cause a VM-exit at the right priority elsewhere
7491 * in the code.
7492 */
7493 uint64_t uEntryTick;
7494 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7495 if (uPreemptTimer)
7496 {
7497 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7498 AssertRC(rc);
7499 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7500 }
7501 else
7502 {
7503 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7504 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7505 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7506 }
7507
7508 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7509 }
7510 else
7511 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7512
7513 NOREF(pszInstr);
7514}
7515
7516
7517/**
7518 * Injects an event using TRPM given a VM-entry interruption info and related
7519 * fields.
7520 *
7521 * @param pVCpu The cross context virtual CPU structure.
7522 * @param pszInstr The VMX instruction name (for logging purposes).
7523 * @param uEntryIntInfo The VM-entry interruption info.
7524 * @param uErrCode The error code associated with the event if any.
7525 * @param cbInstr The VM-entry instruction length (for software
7526 * interrupts and software exceptions). Pass 0
7527 * otherwise.
7528 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7529 */
7530static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7531 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7532{
7533 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7534
7535 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7536 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7537 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7538
7539 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7540
7541 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7542 AssertRC(rc);
7543 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7544
7545 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7546 {
7547 TRPMSetErrorCode(pVCpu, uErrCode);
7548 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7549 }
7550
7551 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7552 {
7553 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7554 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7555 }
7556 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7557 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7558 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7559 {
7560 TRPMSetInstrLength(pVCpu, cbInstr);
7561 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7562 }
7563
7564 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7565 {
7566 TRPMSetTrapDueToIcebp(pVCpu);
7567 Log(("%s: Injecting: icebp\n", pszInstr));
7568 }
7569
7570 NOREF(pszInstr);
7571}
7572
7573
7574/**
7575 * Performs event injection (if any) as part of VM-entry.
7576 *
7577 * @param pVCpu The cross context virtual CPU structure.
7578 * @param pszInstr The VMX instruction name (for logging purposes).
7579 */
7580static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7581{
7582 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7583
7584 /*
7585 * Inject events.
7586 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7587 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7588 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7589 * the actually delivery of this event.
7590 *
7591 * See Intel spec. 26.5 "Event Injection".
7592 */
7593 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7594 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7595
7596 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7597 if (fEntryIntInfoValid)
7598 {
7599 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7600 {
7601 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7602 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7603 }
7604 else
7605 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7606 pVCpu->cpum.GstCtx.cr2);
7607
7608 /*
7609 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7610 *
7611 * However, we do it here on VM-entry as well because while it isn't visible to guest
7612 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7613 * execution using hardware-assisted VMX, it will not try to inject the event again.
7614 *
7615 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7616 */
7617 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7618 }
7619 else
7620 {
7621 /*
7622 * Inject any pending guest debug exception.
7623 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7624 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7625 */
7626 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7627 if (fPendingDbgXcpt)
7628 {
7629 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7630 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7631 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7632 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7633 0 /* GCPtrFaultAddress */);
7634 }
7635 }
7636
7637 NOREF(pszInstr);
7638}
7639
7640
7641/**
7642 * Initializes all read-only VMCS fields as part of VM-entry.
7643 *
7644 * @param pVCpu The cross context virtual CPU structure.
7645 */
7646static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7647{
7648 /*
7649 * Any VMCS field which we do not establish on every VM-exit but may potentially
7650 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7651 * specified to be undefined, needs to be initialized here.
7652 *
7653 * Thus, it is especially important to clear the Exit qualification field
7654 * since it must be zero for VM-exits where it is not used. Similarly, the
7655 * VM-exit interruption information field's valid bit needs to be cleared for
7656 * the same reasons.
7657 */
7658 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7659 Assert(pVmcs);
7660
7661 /* 16-bit (none currently). */
7662 /* 32-bit. */
7663 pVmcs->u32RoVmInstrError = 0;
7664 pVmcs->u32RoExitReason = 0;
7665 pVmcs->u32RoExitIntInfo = 0;
7666 pVmcs->u32RoExitIntErrCode = 0;
7667 pVmcs->u32RoIdtVectoringInfo = 0;
7668 pVmcs->u32RoIdtVectoringErrCode = 0;
7669 pVmcs->u32RoExitInstrLen = 0;
7670 pVmcs->u32RoExitInstrInfo = 0;
7671
7672 /* 64-bit. */
7673 pVmcs->u64RoGuestPhysAddr.u = 0;
7674
7675 /* Natural-width. */
7676 pVmcs->u64RoExitQual.u = 0;
7677 pVmcs->u64RoIoRcx.u = 0;
7678 pVmcs->u64RoIoRsi.u = 0;
7679 pVmcs->u64RoIoRdi.u = 0;
7680 pVmcs->u64RoIoRip.u = 0;
7681 pVmcs->u64RoGuestLinearAddr.u = 0;
7682}
7683
7684
7685/**
7686 * VMLAUNCH/VMRESUME instruction execution worker.
7687 *
7688 * @returns Strict VBox status code.
7689 * @param pVCpu The cross context virtual CPU structure.
7690 * @param cbInstr The instruction length in bytes.
7691 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7692 * VMXINSTRID_VMRESUME).
7693 *
7694 * @remarks Common VMX instruction checks are already expected to by the caller,
7695 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7696 */
7697static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7698{
7699# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7700 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7701 return VINF_EM_RAW_EMULATE_INSTR;
7702# else
7703 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7704 || uInstrId == VMXINSTRID_VMRESUME);
7705 const char * const pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7706
7707 /* Nested-guest intercept. */
7708 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7709 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7710
7711 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7712
7713 /*
7714 * Basic VM-entry checks.
7715 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7716 * The checks following that do not have to follow a specific order.
7717 *
7718 * See Intel spec. 26.1 "Basic VM-entry Checks".
7719 */
7720
7721 /* CPL. */
7722 if (pVCpu->iem.s.uCpl == 0)
7723 { /* likely */ }
7724 else
7725 {
7726 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7727 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7728 return iemRaiseGeneralProtectionFault0(pVCpu);
7729 }
7730
7731 /* Current VMCS valid. */
7732 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7733 { /* likely */ }
7734 else
7735 {
7736 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7737 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7738 iemVmxVmFailInvalid(pVCpu);
7739 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7740 }
7741
7742 /* Current VMCS is not a shadow VMCS. */
7743 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7744 { /* likely */ }
7745 else
7746 {
7747 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7748 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7749 iemVmxVmFailInvalid(pVCpu);
7750 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7751 }
7752
7753 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7754 * use block-by-STI here which is not quite correct. */
7755 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
7756 { /* likely */ }
7757 else
7758 {
7759 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7760 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7761 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7762 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7763 }
7764
7765 if (uInstrId == VMXINSTRID_VMLAUNCH)
7766 {
7767 /* VMLAUNCH with non-clear VMCS. */
7768 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7769 { /* likely */ }
7770 else
7771 {
7772 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7773 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7774 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7775 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7776 }
7777 }
7778 else
7779 {
7780 /* VMRESUME with non-launched VMCS. */
7781 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7782 { /* likely */ }
7783 else
7784 {
7785 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7786 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7787 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7788 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7789 }
7790 }
7791
7792 /*
7793 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7794 * while entering VMX non-root mode. We do some of this while checking VM-execution
7795 * controls. The nested hypervisor should not make assumptions and cannot expect
7796 * predictable behavior if changes to these structures are made in guest memory while
7797 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7798 * modify them anyway as we cache them in host memory.
7799 *
7800 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7801 */
7802 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7803 Assert(pVmcs);
7804 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7805
7806 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7807 if (RT_SUCCESS(rc))
7808 {
7809 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7810 if (RT_SUCCESS(rc))
7811 {
7812 /*
7813 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7814 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7815 * ones that may occur during VM-entry below).
7816 */
7817 iemVmxVmentryInitReadOnlyFields(pVCpu);
7818
7819 /*
7820 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7821 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7822 * VM-exit when required.
7823 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7824 */
7825 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7826
7827 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7828 if (RT_SUCCESS(rc))
7829 {
7830 /*
7831 * We've now entered nested-guest execution.
7832 *
7833 * It is important do this prior to loading the guest state because
7834 * as part of loading the guest state, PGM (and perhaps other components
7835 * in the future) relies on detecting whether VMX non-root mode has been
7836 * entered.
7837 */
7838 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7839
7840 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7841 if (RT_SUCCESS(rc))
7842 {
7843 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7844 if (RT_SUCCESS(rc))
7845 {
7846 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7847
7848 /* VMLAUNCH instruction must update the VMCS launch state. */
7849 if (uInstrId == VMXINSTRID_VMLAUNCH)
7850 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7851
7852 /* Perform the VMX transition (PGM updates). */
7853 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7854 if (rcStrict == VINF_SUCCESS)
7855 { /* likely */ }
7856 else if (RT_SUCCESS(rcStrict))
7857 {
7858 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7859 VBOXSTRICTRC_VAL(rcStrict)));
7860 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7861 }
7862 else
7863 {
7864 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7865 return rcStrict;
7866 }
7867
7868 /* Paranoia. */
7869 Assert(rcStrict == VINF_SUCCESS);
7870
7871 /*
7872 * The priority of potential VM-exits during VM-entry is important.
7873 * The priorities of VM-exits and events are listed from highest
7874 * to lowest as follows:
7875 *
7876 * 1. Event injection.
7877 * 2. Trap on task-switch (T flag set in TSS).
7878 * 3. TPR below threshold / APIC-write.
7879 * 4. SMI, INIT.
7880 * 5. MTF exit.
7881 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7882 * 7. VMX-preemption timer.
7883 * 9. NMI-window exit.
7884 * 10. NMI injection.
7885 * 11. Interrupt-window exit.
7886 * 12. Virtual-interrupt injection.
7887 * 13. Interrupt injection.
7888 * 14. Process next instruction (fetch, decode, execute).
7889 */
7890
7891 /* Setup VMX-preemption timer. */
7892 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7893
7894 /* Setup monitor-trap flag. */
7895 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7896
7897 /* Setup NMI-window exiting. */
7898 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7899
7900 /* Setup interrupt-window exiting. */
7901 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7902
7903 /*
7904 * Inject any event that the nested hypervisor wants to inject.
7905 * Note! We cannot immediately perform the event injection here as we may have
7906 * pending PGM operations to perform due to switching page tables and/or
7907 * mode.
7908 */
7909 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7910
7911# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7912 /* Reschedule to IEM-only execution of the nested-guest. */
7913 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7914 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7915 if (rcSched != VINF_SUCCESS)
7916 iemSetPassUpStatus(pVCpu, rcSched);
7917# endif
7918
7919 /* Finally, done. */
7920 Log2(("vmentry: %s: cs:rip=%04x:%08RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7921 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7922 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7923 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7924 return VINF_SUCCESS;
7925 }
7926 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7927 }
7928 }
7929 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7930 }
7931
7932 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7933 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7934 }
7935
7936 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7937 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7938# endif
7939}
7940
7941
7942/**
7943 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7944 *
7945 * @returns Strict VBox status code.
7946 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7947 * @param cbInstr The instruction length in bytes.
7948 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7949 * VMXINSTRID_VMRESUME).
7950 * @thread EMT(pVCpu)
7951 */
7952VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7953{
7954 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7955 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7956
7957 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7958 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7959 Assert(!pVCpu->iem.s.cActiveMappings);
7960 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
7961}
7962
7963
7964/**
7965 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7966 * (causes a VM-exit) or not.
7967 *
7968 * @returns @c true if the instruction is intercepted, @c false otherwise.
7969 * @param pVCpu The cross context virtual CPU structure.
7970 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7971 * VMX_EXIT_WRMSR).
7972 * @param idMsr The MSR.
7973 */
7974bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
7975{
7976 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7977 Assert( uExitReason == VMX_EXIT_RDMSR
7978 || uExitReason == VMX_EXIT_WRMSR);
7979
7980 /* Consult the MSR bitmap if the feature is supported. */
7981 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7982 Assert(pVmcs);
7983 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7984 {
7985 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7986 if (uExitReason == VMX_EXIT_RDMSR)
7987 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7988 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7989 }
7990
7991 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7992 return true;
7993}
7994
7995
7996/**
7997 * VMREAD instruction execution worker that does not perform any validation checks.
7998 *
7999 * Callers are expected to have performed the necessary checks and to ensure the
8000 * VMREAD will succeed.
8001 *
8002 * @param pVmcs Pointer to the virtual VMCS.
8003 * @param pu64Dst Where to write the VMCS value.
8004 * @param u64VmcsField The VMCS field.
8005 *
8006 * @remarks May be called with interrupts disabled.
8007 */
8008static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8009{
8010 VMXVMCSFIELD VmcsField;
8011 VmcsField.u = u64VmcsField;
8012 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8013 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8014 uint8_t const uWidthType = (uWidth << 2) | uType;
8015 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8016 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8017 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8018 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8019 uWidth, uType, uIndex, uIndex));
8020 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8021
8022 /*
8023 * Read the VMCS component based on the field's effective width.
8024 *
8025 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8026 * indicates high bits (little endian).
8027 *
8028 * Note! The caller is responsible to trim the result and update registers
8029 * or memory locations are required. Here we just zero-extend to the largest
8030 * type (i.e. 64-bits).
8031 */
8032 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8033 uint8_t const *pbField = pbVmcs + offField;
8034 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8035 switch (uEffWidth)
8036 {
8037 case VMX_VMCSFIELD_WIDTH_64BIT:
8038 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8039 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8040 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8041 }
8042}
8043
8044
8045/**
8046 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8047 *
8048 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8049 * are performed. Bounds checks are strict builds only.
8050 *
8051 * @param pVmcs Pointer to the virtual VMCS.
8052 * @param u64VmcsField The VMCS field.
8053 * @param pu64Dst Where to store the VMCS value.
8054 *
8055 * @remarks May be called with interrupts disabled.
8056 * @todo This should probably be moved to CPUM someday.
8057 */
8058VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8059{
8060 AssertPtr(pVmcs);
8061 AssertPtr(pu64Dst);
8062 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8063}
8064
8065
8066/**
8067 * VMREAD common (memory/register) instruction execution worker.
8068 *
8069 * @returns Strict VBox status code.
8070 * @param pVCpu The cross context virtual CPU structure.
8071 * @param cbInstr The instruction length in bytes.
8072 * @param pu64Dst Where to write the VMCS value (only updated when
8073 * VINF_SUCCESS is returned).
8074 * @param u64VmcsField The VMCS field.
8075 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8076 * NULL.
8077 */
8078static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8079 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8080{
8081 /* Nested-guest intercept. */
8082 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8083 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8084 {
8085 if (pExitInfo)
8086 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8087 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8088 }
8089
8090 /* CPL. */
8091 if (pVCpu->iem.s.uCpl == 0)
8092 { /* likely */ }
8093 else
8094 {
8095 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8096 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8097 return iemRaiseGeneralProtectionFault0(pVCpu);
8098 }
8099
8100 pVCpu->iem.s.cPotentialExits++;
8101
8102 /* VMCS pointer in root mode. */
8103 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8104 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8105 { /* likely */ }
8106 else
8107 {
8108 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8109 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8110 iemVmxVmFailInvalid(pVCpu);
8111 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8112 }
8113
8114 /* VMCS-link pointer in non-root mode. */
8115 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8116 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8117 { /* likely */ }
8118 else
8119 {
8120 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8121 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8122 iemVmxVmFailInvalid(pVCpu);
8123 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8124 }
8125
8126 /* Supported VMCS field. */
8127 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8128 { /* likely */ }
8129 else
8130 {
8131 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8132 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8133 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8134 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8135 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8136 }
8137
8138 /*
8139 * Reading from the current or shadow VMCS.
8140 */
8141 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8142 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8143 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8144 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8145 Log4(("vmread %#RX64 => %#RX64\n", u64VmcsField, *pu64Dst));
8146 return VINF_SUCCESS;
8147}
8148
8149
8150/**
8151 * VMREAD (64-bit register) instruction execution worker.
8152 *
8153 * @returns Strict VBox status code.
8154 * @param pVCpu The cross context virtual CPU structure.
8155 * @param cbInstr The instruction length in bytes.
8156 * @param pu64Dst Where to store the VMCS field's value.
8157 * @param u64VmcsField The VMCS field.
8158 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8159 * NULL.
8160 */
8161static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8162 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8163{
8164 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8165 if (rcStrict == VINF_SUCCESS)
8166 {
8167 iemVmxVmSucceed(pVCpu);
8168 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8169 }
8170
8171 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8172 return rcStrict;
8173}
8174
8175
8176/**
8177 * VMREAD (32-bit register) instruction execution worker.
8178 *
8179 * @returns Strict VBox status code.
8180 * @param pVCpu The cross context virtual CPU structure.
8181 * @param cbInstr The instruction length in bytes.
8182 * @param pu32Dst Where to store the VMCS field's value.
8183 * @param u32VmcsField The VMCS field.
8184 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8185 * NULL.
8186 */
8187static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8188 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8189{
8190 uint64_t u64Dst;
8191 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8192 if (rcStrict == VINF_SUCCESS)
8193 {
8194 *pu32Dst = u64Dst;
8195 iemVmxVmSucceed(pVCpu);
8196 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8197 }
8198
8199 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8200 return rcStrict;
8201}
8202
8203
8204/**
8205 * VMREAD (memory) instruction execution worker.
8206 *
8207 * @returns Strict VBox status code.
8208 * @param pVCpu The cross context virtual CPU structure.
8209 * @param cbInstr The instruction length in bytes.
8210 * @param iEffSeg The effective segment register to use with @a u64Val.
8211 * Pass UINT8_MAX if it is a register access.
8212 * @param GCPtrDst The guest linear address to store the VMCS field's
8213 * value.
8214 * @param u64VmcsField The VMCS field.
8215 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8216 * NULL.
8217 */
8218static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8219 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8220{
8221 uint64_t u64Dst;
8222 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8223 if (rcStrict == VINF_SUCCESS)
8224 {
8225 /*
8226 * Write the VMCS field's value to the location specified in guest-memory.
8227 */
8228 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8229 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8230 else
8231 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8232 if (rcStrict == VINF_SUCCESS)
8233 {
8234 iemVmxVmSucceed(pVCpu);
8235 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8236 }
8237
8238 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8239 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8240 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8241 return rcStrict;
8242 }
8243
8244 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8245 return rcStrict;
8246}
8247
8248
8249/**
8250 * Interface for HM and EM to emulate the VMREAD instruction.
8251 *
8252 * @returns Strict VBox status code.
8253 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8254 * @param pExitInfo Pointer to the VM-exit information.
8255 * @thread EMT(pVCpu)
8256 */
8257VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8258{
8259 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8260 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8261 Assert(pExitInfo);
8262
8263 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8264
8265 VBOXSTRICTRC rcStrict;
8266 uint8_t const cbInstr = pExitInfo->cbInstr;
8267 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8268 uint64_t const u64FieldEnc = fIs64BitMode
8269 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8270 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8271 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8272 {
8273 if (fIs64BitMode)
8274 {
8275 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8276 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8277 }
8278 else
8279 {
8280 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8281 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8282 }
8283 }
8284 else
8285 {
8286 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8287 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8288 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8289 }
8290 Assert(!pVCpu->iem.s.cActiveMappings);
8291 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8292}
8293
8294
8295/**
8296 * VMWRITE instruction execution worker that does not perform any validation
8297 * checks.
8298 *
8299 * Callers are expected to have performed the necessary checks and to ensure the
8300 * VMWRITE will succeed.
8301 *
8302 * @param pVmcs Pointer to the virtual VMCS.
8303 * @param u64Val The value to write.
8304 * @param u64VmcsField The VMCS field.
8305 *
8306 * @remarks May be called with interrupts disabled.
8307 */
8308static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8309{
8310 VMXVMCSFIELD VmcsField;
8311 VmcsField.u = u64VmcsField;
8312 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8313 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8314 uint8_t const uWidthType = (uWidth << 2) | uType;
8315 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8316 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8317 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8318 Assert(offField < VMX_V_VMCS_SIZE);
8319 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8320
8321 /*
8322 * Write the VMCS component based on the field's effective width.
8323 *
8324 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8325 * indicates high bits (little endian).
8326 */
8327 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8328 uint8_t *pbField = pbVmcs + offField;
8329 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8330 switch (uEffWidth)
8331 {
8332 case VMX_VMCSFIELD_WIDTH_64BIT:
8333 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8334 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8335 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8336 }
8337}
8338
8339
8340/**
8341 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8342 *
8343 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8344 * are performed. Bounds checks are strict builds only.
8345 *
8346 * @param pVmcs Pointer to the virtual VMCS.
8347 * @param u64VmcsField The VMCS field.
8348 * @param u64Val The value to write.
8349 *
8350 * @remarks May be called with interrupts disabled.
8351 * @todo This should probably be moved to CPUM someday.
8352 */
8353VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8354{
8355 AssertPtr(pVmcs);
8356 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8357}
8358
8359
8360/**
8361 * VMWRITE instruction execution worker.
8362 *
8363 * @returns Strict VBox status code.
8364 * @param pVCpu The cross context virtual CPU structure.
8365 * @param cbInstr The instruction length in bytes.
8366 * @param iEffSeg The effective segment register to use with @a u64Val.
8367 * Pass UINT8_MAX if it is a register access.
8368 * @param u64Val The value to write (or guest linear address to the
8369 * value), @a iEffSeg will indicate if it's a memory
8370 * operand.
8371 * @param u64VmcsField The VMCS field.
8372 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8373 * NULL.
8374 */
8375static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8376 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8377{
8378 /* Nested-guest intercept. */
8379 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8380 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8381 {
8382 if (pExitInfo)
8383 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8384 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8385 }
8386
8387 /* CPL. */
8388 if (pVCpu->iem.s.uCpl == 0)
8389 { /* likely */ }
8390 else
8391 {
8392 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8393 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8394 return iemRaiseGeneralProtectionFault0(pVCpu);
8395 }
8396
8397 pVCpu->iem.s.cPotentialExits++;
8398
8399 /* VMCS pointer in root mode. */
8400 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8401 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8402 { /* likely */ }
8403 else
8404 {
8405 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8406 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8407 iemVmxVmFailInvalid(pVCpu);
8408 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8409 }
8410
8411 /* VMCS-link pointer in non-root mode. */
8412 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8413 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8414 { /* likely */ }
8415 else
8416 {
8417 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8418 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8419 iemVmxVmFailInvalid(pVCpu);
8420 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8421 }
8422
8423 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8424 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8425 if (!fIsRegOperand)
8426 {
8427 /* Read the value from the specified guest memory location. */
8428 VBOXSTRICTRC rcStrict;
8429 RTGCPTR const GCPtrVal = u64Val;
8430 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8431 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8432 else
8433 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8434 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8435 {
8436 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8437 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8438 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8439 return rcStrict;
8440 }
8441 }
8442 else
8443 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8444
8445 /* Supported VMCS field. */
8446 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8447 { /* likely */ }
8448 else
8449 {
8450 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8451 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8452 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8453 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8454 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8455 }
8456
8457 /* Read-only VMCS field. */
8458 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8459 if ( !fIsFieldReadOnly
8460 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8461 { /* likely */ }
8462 else
8463 {
8464 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8465 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8466 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8467 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8468 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8469 }
8470
8471 /*
8472 * Write to the current or shadow VMCS.
8473 */
8474 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8475 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8476 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8477 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8478 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8479 Log4(("vmwrite %#RX64 <= %#RX64\n", u64VmcsField, u64Val));
8480
8481 if ( !fInVmxNonRootMode
8482 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8483 {
8484 /* Notify HM that the VMCS content might have changed. */
8485 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8486 }
8487
8488 iemVmxVmSucceed(pVCpu);
8489 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8490}
8491
8492
8493/**
8494 * Interface for HM and EM to emulate the VMWRITE instruction.
8495 *
8496 * @returns Strict VBox status code.
8497 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8498 * @param pExitInfo Pointer to the VM-exit information.
8499 * @thread EMT(pVCpu)
8500 */
8501VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8502{
8503 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8504 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8505 Assert(pExitInfo);
8506
8507 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8508
8509 uint64_t u64Val;
8510 uint8_t iEffSeg;
8511 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8512 {
8513 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8514 iEffSeg = UINT8_MAX;
8515 }
8516 else
8517 {
8518 u64Val = pExitInfo->GCPtrEffAddr;
8519 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8520 }
8521 uint8_t const cbInstr = pExitInfo->cbInstr;
8522 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8523 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8524 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8525 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8526 Assert(!pVCpu->iem.s.cActiveMappings);
8527 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8528}
8529
8530
8531/**
8532 * VMCLEAR instruction execution worker.
8533 *
8534 * @returns Strict VBox status code.
8535 * @param pVCpu The cross context virtual CPU structure.
8536 * @param cbInstr The instruction length in bytes.
8537 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8538 * @param GCPtrVmcs The linear address of the VMCS pointer.
8539 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8540 *
8541 * @remarks Common VMX instruction checks are already expected to by the caller,
8542 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8543 */
8544static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8545 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8546{
8547 /* Nested-guest intercept. */
8548 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8549 {
8550 if (pExitInfo)
8551 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8552 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8553 }
8554
8555 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8556
8557 /* CPL. */
8558 if (pVCpu->iem.s.uCpl == 0)
8559 { /* likely */ }
8560 else
8561 {
8562 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8564 return iemRaiseGeneralProtectionFault0(pVCpu);
8565 }
8566
8567 /* Get the VMCS pointer from the location specified by the source memory operand. */
8568 RTGCPHYS GCPhysVmcs;
8569 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8570 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8571 { /* likely */ }
8572 else
8573 {
8574 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8575 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8576 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8577 return rcStrict;
8578 }
8579
8580 /* VMCS pointer alignment. */
8581 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8582 { /* likely */ }
8583 else
8584 {
8585 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8586 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8587 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8588 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8589 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8590 }
8591
8592 /* VMCS physical-address width limits. */
8593 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8594 { /* likely */ }
8595 else
8596 {
8597 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8598 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8599 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8600 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8601 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8602 }
8603
8604 /* VMCS is not the VMXON region. */
8605 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8606 { /* likely */ }
8607 else
8608 {
8609 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8610 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8611 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8612 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8613 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8614 }
8615
8616 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8617 restriction imposed by our implementation. */
8618 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8619 { /* likely */ }
8620 else
8621 {
8622 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8623 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8624 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8625 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8626 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8627 }
8628
8629 /*
8630 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8631 *
8632 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8633 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8634 * to 'clear'.
8635 */
8636 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8637 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8638 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8639 {
8640 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8641 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8642 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8643 }
8644 else
8645 {
8646 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8647 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8648 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8649 if (RT_FAILURE(rcStrict))
8650 return rcStrict;
8651 }
8652
8653 iemVmxVmSucceed(pVCpu);
8654 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8655}
8656
8657
8658/**
8659 * Interface for HM and EM to emulate the VMCLEAR instruction.
8660 *
8661 * @returns Strict VBox status code.
8662 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8663 * @param pExitInfo Pointer to the VM-exit information.
8664 * @thread EMT(pVCpu)
8665 */
8666VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8667{
8668 Assert(pExitInfo);
8669 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8670 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8671
8672 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8673
8674 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8675 uint8_t const cbInstr = pExitInfo->cbInstr;
8676 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8677 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8678 Assert(!pVCpu->iem.s.cActiveMappings);
8679 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8680}
8681
8682
8683/**
8684 * VMPTRST instruction execution worker.
8685 *
8686 * @returns Strict VBox status code.
8687 * @param pVCpu The cross context virtual CPU structure.
8688 * @param cbInstr The instruction length in bytes.
8689 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8690 * @param GCPtrVmcs The linear address of where to store the current VMCS
8691 * pointer.
8692 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8693 *
8694 * @remarks Common VMX instruction checks are already expected to by the caller,
8695 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8696 */
8697static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8698 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8699{
8700 /* Nested-guest intercept. */
8701 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8702 {
8703 if (pExitInfo)
8704 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8705 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8706 }
8707
8708 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8709
8710 /* CPL. */
8711 if (pVCpu->iem.s.uCpl == 0)
8712 { /* likely */ }
8713 else
8714 {
8715 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8716 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8717 return iemRaiseGeneralProtectionFault0(pVCpu);
8718 }
8719
8720 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8721 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8722 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8723 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8724 {
8725 iemVmxVmSucceed(pVCpu);
8726 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8727 }
8728
8729 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8730 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8731 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8732 return rcStrict;
8733}
8734
8735
8736/**
8737 * Interface for HM and EM to emulate the VMPTRST instruction.
8738 *
8739 * @returns Strict VBox status code.
8740 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8741 * @param pExitInfo Pointer to the VM-exit information.
8742 * @thread EMT(pVCpu)
8743 */
8744VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8745{
8746 Assert(pExitInfo);
8747 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8748 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8749
8750 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8751
8752 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8753 uint8_t const cbInstr = pExitInfo->cbInstr;
8754 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8755 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8756 Assert(!pVCpu->iem.s.cActiveMappings);
8757 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8758}
8759
8760
8761/**
8762 * VMPTRLD instruction execution worker.
8763 *
8764 * @returns Strict VBox status code.
8765 * @param pVCpu The cross context virtual CPU structure.
8766 * @param cbInstr The instruction length in bytes.
8767 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8768 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8769 *
8770 * @remarks Common VMX instruction checks are already expected to by the caller,
8771 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8772 */
8773static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8774 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8775{
8776 /* Nested-guest intercept. */
8777 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8778 {
8779 if (pExitInfo)
8780 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8781 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8782 }
8783
8784 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8785
8786 /* CPL. */
8787 if (pVCpu->iem.s.uCpl == 0)
8788 { /* likely */ }
8789 else
8790 {
8791 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8792 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8793 return iemRaiseGeneralProtectionFault0(pVCpu);
8794 }
8795
8796 /* Get the VMCS pointer from the location specified by the source memory operand. */
8797 RTGCPHYS GCPhysVmcs;
8798 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8799 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8800 { /* likely */ }
8801 else
8802 {
8803 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8804 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8805 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8806 return rcStrict;
8807 }
8808
8809 /* VMCS pointer alignment. */
8810 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8811 { /* likely */ }
8812 else
8813 {
8814 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8815 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8816 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8817 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8818 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8819 }
8820
8821 /* VMCS physical-address width limits. */
8822 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8823 { /* likely */ }
8824 else
8825 {
8826 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8827 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8828 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8829 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8830 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8831 }
8832
8833 /* VMCS is not the VMXON region. */
8834 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8835 { /* likely */ }
8836 else
8837 {
8838 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8839 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8840 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8841 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8842 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8843 }
8844
8845 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8846 restriction imposed by our implementation. */
8847 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8848 { /* likely */ }
8849 else
8850 {
8851 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8852 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8853 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8854 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8855 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8856 }
8857
8858 /* Read just the VMCS revision from the VMCS. */
8859 VMXVMCSREVID VmcsRevId;
8860 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8861 if (RT_SUCCESS(rc))
8862 { /* likely */ }
8863 else
8864 {
8865 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8866 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8867 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8868 return rc;
8869 }
8870
8871 /*
8872 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8873 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8874 */
8875 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8876 && ( !VmcsRevId.n.fIsShadowVmcs
8877 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8878 { /* likely */ }
8879 else
8880 {
8881 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8882 {
8883 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8884 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8885 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8886 }
8887 else
8888 {
8889 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8890 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8891 }
8892 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8893 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8894 }
8895
8896 /*
8897 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8898 * the cache of an existing, current VMCS back to guest memory before loading a new,
8899 * different current VMCS.
8900 */
8901 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8902 {
8903 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8904 {
8905 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8906 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8907 }
8908
8909 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8910 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8911 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8912 if (RT_SUCCESS(rc))
8913 {
8914 /* Notify HM that a new, current VMCS is loaded. */
8915 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8916 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8917 }
8918 else
8919 {
8920 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8921 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8922 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8923 return rc;
8924 }
8925 }
8926
8927 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8928 iemVmxVmSucceed(pVCpu);
8929 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8930}
8931
8932
8933/**
8934 * Interface for HM and EM to emulate the VMPTRLD instruction.
8935 *
8936 * @returns Strict VBox status code.
8937 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8938 * @param pExitInfo Pointer to the VM-exit information.
8939 * @thread EMT(pVCpu)
8940 */
8941VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8942{
8943 Assert(pExitInfo);
8944 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8945 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8946
8947 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8948
8949 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8950 uint8_t const cbInstr = pExitInfo->cbInstr;
8951 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8952 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8953 Assert(!pVCpu->iem.s.cActiveMappings);
8954 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8955}
8956
8957
8958/**
8959 * INVVPID instruction execution worker.
8960 *
8961 * @returns Strict VBox status code.
8962 * @param pVCpu The cross context virtual CPU structure.
8963 * @param cbInstr The instruction length in bytes.
8964 * @param iEffSeg The segment of the invvpid descriptor.
8965 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8966 * @param u64InvvpidType The invalidation type.
8967 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8968 * NULL.
8969 *
8970 * @remarks Common VMX instruction checks are already expected to by the caller,
8971 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8972 */
8973VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8974 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8975{
8976 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8977 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8978 return iemRaiseUndefinedOpcode(pVCpu);
8979
8980 /* Nested-guest intercept. */
8981 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8982 {
8983 if (pExitInfo)
8984 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8985 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8986 }
8987
8988 /* CPL. */
8989 if (pVCpu->iem.s.uCpl != 0)
8990 {
8991 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8992 return iemRaiseGeneralProtectionFault0(pVCpu);
8993 }
8994
8995 /*
8996 * Validate INVVPID invalidation type.
8997 *
8998 * The instruction specifies exactly ONE of the supported invalidation types.
8999 *
9000 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9001 * supported. In theory, it's possible for a CPU to not support flushing individual
9002 * addresses but all the other types or any other combination. We do not take any
9003 * shortcuts here by assuming the types we currently expose to the guest.
9004 */
9005 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9006 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9007 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9008 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9009 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9010 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9011
9012 bool afSupportedTypes[4];
9013 afSupportedTypes[0] = fTypeIndivAddr;
9014 afSupportedTypes[1] = fTypeSingleCtx;
9015 afSupportedTypes[2] = fTypeAllCtx;
9016 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9017
9018 if ( fInvvpidSupported
9019 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9020 && afSupportedTypes[u64InvvpidType & 3])
9021 { /* likely */ }
9022 else
9023 {
9024 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9025 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9026 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9027 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9028 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9029 }
9030
9031 /*
9032 * Fetch the invvpid descriptor from guest memory.
9033 */
9034 RTUINT128U uDesc;
9035 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9036 if (rcStrict == VINF_SUCCESS)
9037 {
9038 /*
9039 * Validate the descriptor.
9040 */
9041 if (uDesc.s.Lo <= 0xffff)
9042 { /* likely */ }
9043 else
9044 {
9045 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9046 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9047 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9048 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9049 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9050 }
9051
9052 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9053 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9054 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
9055 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9056 switch (u64InvvpidType)
9057 {
9058 case VMXTLBFLUSHVPID_INDIV_ADDR:
9059 {
9060 if (uVpid != 0)
9061 {
9062 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9063 {
9064 /* Invalidate mappings for the linear address tagged with VPID. */
9065 /** @todo PGM support for VPID? Currently just flush everything. */
9066 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9067 iemVmxVmSucceed(pVCpu);
9068 }
9069 else
9070 {
9071 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9072 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9073 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9074 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9075 }
9076 }
9077 else
9078 {
9079 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9080 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9081 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9082 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9083 }
9084 break;
9085 }
9086
9087 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9088 {
9089 if (uVpid != 0)
9090 {
9091 /* Invalidate all mappings with VPID. */
9092 /** @todo PGM support for VPID? Currently just flush everything. */
9093 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9094 iemVmxVmSucceed(pVCpu);
9095 }
9096 else
9097 {
9098 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9099 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9100 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9101 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9102 }
9103 break;
9104 }
9105
9106 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9107 {
9108 /* Invalidate all mappings with non-zero VPIDs. */
9109 /** @todo PGM support for VPID? Currently just flush everything. */
9110 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9111 iemVmxVmSucceed(pVCpu);
9112 break;
9113 }
9114
9115 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9116 {
9117 if (uVpid != 0)
9118 {
9119 /* Invalidate all mappings with VPID except global translations. */
9120 /** @todo PGM support for VPID? Currently just flush everything. */
9121 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9122 iemVmxVmSucceed(pVCpu);
9123 }
9124 else
9125 {
9126 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9127 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9128 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9129 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9130 }
9131 break;
9132 }
9133 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9134 }
9135 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9136 }
9137 return rcStrict;
9138}
9139
9140
9141/**
9142 * Interface for HM and EM to emulate the INVVPID instruction.
9143 *
9144 * @returns Strict VBox status code.
9145 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9146 * @param pExitInfo Pointer to the VM-exit information.
9147 * @thread EMT(pVCpu)
9148 */
9149VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9150{
9151 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9152 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9153 Assert(pExitInfo);
9154
9155 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9156
9157 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9158 uint8_t const cbInstr = pExitInfo->cbInstr;
9159 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9160 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9161 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9162 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9163 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9164 Assert(!pVCpu->iem.s.cActiveMappings);
9165 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9166}
9167
9168#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9169
9170/**
9171 * INVEPT instruction execution worker.
9172 *
9173 * @returns Strict VBox status code.
9174 * @param pVCpu The cross context virtual CPU structure.
9175 * @param cbInstr The instruction length in bytes.
9176 * @param iEffSeg The segment of the invept descriptor.
9177 * @param GCPtrInveptDesc The address of invept descriptor.
9178 * @param u64InveptType The invalidation type.
9179 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9180 * NULL.
9181 *
9182 * @remarks Common VMX instruction checks are already expected to by the caller,
9183 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9184 */
9185static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9186 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9187{
9188 /* Check if EPT is supported, otherwise raise #UD. */
9189 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9190 return iemRaiseUndefinedOpcode(pVCpu);
9191
9192 /* Nested-guest intercept. */
9193 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9194 {
9195 if (pExitInfo)
9196 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9197 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9198 }
9199
9200 /* CPL. */
9201 if (pVCpu->iem.s.uCpl != 0)
9202 {
9203 Log(("invept: CPL != 0 -> #GP(0)\n"));
9204 return iemRaiseGeneralProtectionFault0(pVCpu);
9205 }
9206
9207 /*
9208 * Validate INVEPT invalidation type.
9209 *
9210 * The instruction specifies exactly ONE of the supported invalidation types.
9211 *
9212 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9213 * supported. In theory, it's possible for a CPU to not support flushing individual
9214 * addresses but all the other types or any other combination. We do not take any
9215 * shortcuts here by assuming the types we currently expose to the guest.
9216 */
9217 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9218 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9219 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9220 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9221
9222 bool afSupportedTypes[4];
9223 afSupportedTypes[0] = false;
9224 afSupportedTypes[1] = fTypeSingleCtx;
9225 afSupportedTypes[2] = fTypeAllCtx;
9226 afSupportedTypes[3] = false;
9227
9228 if ( fInveptSupported
9229 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9230 && afSupportedTypes[u64InveptType & 3])
9231 { /* likely */ }
9232 else
9233 {
9234 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9235 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9236 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9237 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9238 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9239 }
9240
9241 /*
9242 * Fetch the invept descriptor from guest memory.
9243 */
9244 RTUINT128U uDesc;
9245 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9246 if (rcStrict == VINF_SUCCESS)
9247 {
9248 /*
9249 * Validate the descriptor.
9250 *
9251 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9252 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9253 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9254 * better to be strict in our emulation until proven otherwise.
9255 */
9256 if (uDesc.s.Hi)
9257 {
9258 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9259 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9260 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9261 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9262 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9263 }
9264
9265 /*
9266 * Flush TLB mappings based on the EPT type.
9267 */
9268 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9269 {
9270 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9271 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9272 if (RT_SUCCESS(rc))
9273 { /* likely */ }
9274 else
9275 {
9276 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9277 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9278 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9279 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9280 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9281 }
9282 }
9283
9284 /** @todo PGM support for EPT tags? Currently just flush everything. */
9285 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9286 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9287 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9288
9289 iemVmxVmSucceed(pVCpu);
9290 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9291 }
9292
9293 return rcStrict;
9294}
9295
9296
9297/**
9298 * Interface for HM and EM to emulate the INVEPT instruction.
9299 *
9300 * @returns Strict VBox status code.
9301 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9302 * @param pExitInfo Pointer to the VM-exit information.
9303 * @thread EMT(pVCpu)
9304 */
9305VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9306{
9307 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9308 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9309 Assert(pExitInfo);
9310
9311 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9312
9313 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9314 uint8_t const cbInstr = pExitInfo->cbInstr;
9315 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9316 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9317 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9318 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9319 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9320 Assert(!pVCpu->iem.s.cActiveMappings);
9321 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9322}
9323
9324#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9325
9326/**
9327 * VMXON instruction execution worker.
9328 *
9329 * @returns Strict VBox status code.
9330 * @param pVCpu The cross context virtual CPU structure.
9331 * @param cbInstr The instruction length in bytes.
9332 * @param iEffSeg The effective segment register to use with @a
9333 * GCPtrVmxon.
9334 * @param GCPtrVmxon The linear address of the VMXON pointer.
9335 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9336 *
9337 * @remarks Common VMX instruction checks are already expected to by the caller,
9338 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9339 */
9340static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9341 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9342{
9343 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9344 {
9345 /* CPL. */
9346 if (pVCpu->iem.s.uCpl == 0)
9347 { /* likely */ }
9348 else
9349 {
9350 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9351 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9352 return iemRaiseGeneralProtectionFault0(pVCpu);
9353 }
9354
9355 /* A20M (A20 Masked) mode. */
9356 if (PGMPhysIsA20Enabled(pVCpu))
9357 { /* likely */ }
9358 else
9359 {
9360 Log(("vmxon: A20M mode -> #GP(0)\n"));
9361 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9362 return iemRaiseGeneralProtectionFault0(pVCpu);
9363 }
9364
9365 /* CR0. */
9366 {
9367 /*
9368 * CR0 MB1 bits.
9369 *
9370 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9371 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9372 * when the guest running in VMX non-root mode with unrestricted-guest control
9373 * enabled in the VMCS.
9374 */
9375 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9376 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9377 { /* likely */ }
9378 else
9379 {
9380 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9381 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9382 return iemRaiseGeneralProtectionFault0(pVCpu);
9383 }
9384
9385 /* CR0 MBZ bits. */
9386 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9387 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9388 { /* likely */ }
9389 else
9390 {
9391 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9392 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9393 return iemRaiseGeneralProtectionFault0(pVCpu);
9394 }
9395 }
9396
9397 /* CR4. */
9398 {
9399 /* CR4 MB1 bits. */
9400 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9401 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9402 { /* likely */ }
9403 else
9404 {
9405 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9406 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9407 return iemRaiseGeneralProtectionFault0(pVCpu);
9408 }
9409
9410 /* CR4 MBZ bits. */
9411 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9412 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9413 { /* likely */ }
9414 else
9415 {
9416 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9417 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9418 return iemRaiseGeneralProtectionFault0(pVCpu);
9419 }
9420 }
9421
9422 /* Feature control MSR's LOCK and VMXON bits. */
9423 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9424 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9425 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9426 { /* likely */ }
9427 else
9428 {
9429 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9430 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9431 return iemRaiseGeneralProtectionFault0(pVCpu);
9432 }
9433
9434 /* Get the VMXON pointer from the location specified by the source memory operand. */
9435 RTGCPHYS GCPhysVmxon;
9436 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9437 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9438 { /* likely */ }
9439 else
9440 {
9441 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9442 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9443 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9444 return rcStrict;
9445 }
9446
9447 /* VMXON region pointer alignment. */
9448 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9449 { /* likely */ }
9450 else
9451 {
9452 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9454 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9455 iemVmxVmFailInvalid(pVCpu);
9456 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9457 }
9458
9459 /* VMXON physical-address width limits. */
9460 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9461 { /* likely */ }
9462 else
9463 {
9464 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9465 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9466 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9467 iemVmxVmFailInvalid(pVCpu);
9468 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9469 }
9470
9471 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9472 restriction imposed by our implementation. */
9473 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9474 { /* likely */ }
9475 else
9476 {
9477 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9478 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9479 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9480 iemVmxVmFailInvalid(pVCpu);
9481 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9482 }
9483
9484 /* Read the VMCS revision ID from the VMXON region. */
9485 VMXVMCSREVID VmcsRevId;
9486 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9487 if (RT_SUCCESS(rc))
9488 { /* likely */ }
9489 else
9490 {
9491 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9492 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9493 return rc;
9494 }
9495
9496 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9497 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9498 { /* likely */ }
9499 else
9500 {
9501 /* Revision ID mismatch. */
9502 if (!VmcsRevId.n.fIsShadowVmcs)
9503 {
9504 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9505 VmcsRevId.n.u31RevisionId));
9506 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9507 iemVmxVmFailInvalid(pVCpu);
9508 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9509 }
9510
9511 /* Shadow VMCS disallowed. */
9512 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9513 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9514 iemVmxVmFailInvalid(pVCpu);
9515 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9516 }
9517
9518 /*
9519 * Record that we're in VMX operation, block INIT, block and disable A20M.
9520 */
9521 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9522 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9523 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9524
9525 /* Clear address-range monitoring. */
9526 EMMonitorWaitClear(pVCpu);
9527 /** @todo NSTVMX: Intel PT. */
9528
9529 iemVmxVmSucceed(pVCpu);
9530 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9531 }
9532 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9533 {
9534 /* Nested-guest intercept. */
9535 if (pExitInfo)
9536 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9537 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9538 }
9539
9540 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9541
9542 /* CPL. */
9543 if (pVCpu->iem.s.uCpl > 0)
9544 {
9545 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9546 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9547 return iemRaiseGeneralProtectionFault0(pVCpu);
9548 }
9549
9550 /* VMXON when already in VMX root mode. */
9551 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9552 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9553 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9554}
9555
9556
9557/**
9558 * Interface for HM and EM to emulate the VMXON instruction.
9559 *
9560 * @returns Strict VBox status code.
9561 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9562 * @param pExitInfo Pointer to the VM-exit information.
9563 * @thread EMT(pVCpu)
9564 */
9565VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9566{
9567 Assert(pExitInfo);
9568 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9569 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9570
9571 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9572
9573 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9574 uint8_t const cbInstr = pExitInfo->cbInstr;
9575 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9576 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9577 Assert(!pVCpu->iem.s.cActiveMappings);
9578 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9579}
9580
9581
9582/**
9583 * Implements 'VMXOFF'.
9584 *
9585 * @remarks Common VMX instruction checks are already expected to by the caller,
9586 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9587 */
9588IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9589{
9590 /* Nested-guest intercept. */
9591 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9592 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9593
9594 /* CPL. */
9595 if (pVCpu->iem.s.uCpl == 0)
9596 { /* likely */ }
9597 else
9598 {
9599 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9600 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9601 return iemRaiseGeneralProtectionFault0(pVCpu);
9602 }
9603
9604 /* Dual monitor treatment of SMIs and SMM. */
9605 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9606 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9607 { /* likely */ }
9608 else
9609 {
9610 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9611 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9612 }
9613
9614 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9615 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9616 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9617
9618 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9619 { /** @todo NSTVMX: Unblock SMI. */ }
9620
9621 EMMonitorWaitClear(pVCpu);
9622 /** @todo NSTVMX: Unblock and enable A20M. */
9623
9624 iemVmxVmSucceed(pVCpu);
9625 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9626}
9627
9628
9629/**
9630 * Interface for HM and EM to emulate the VMXOFF instruction.
9631 *
9632 * @returns Strict VBox status code.
9633 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9634 * @param cbInstr The instruction length in bytes.
9635 * @thread EMT(pVCpu)
9636 */
9637VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9638{
9639 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9640 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9641
9642 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9643 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9644 Assert(!pVCpu->iem.s.cActiveMappings);
9645 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9646}
9647
9648
9649/**
9650 * Implements 'VMXON'.
9651 */
9652IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9653{
9654 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9655}
9656
9657
9658/**
9659 * Implements 'VMLAUNCH'.
9660 */
9661IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9662{
9663 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9664}
9665
9666
9667/**
9668 * Implements 'VMRESUME'.
9669 */
9670IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9671{
9672 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9673}
9674
9675
9676/**
9677 * Implements 'VMPTRLD'.
9678 */
9679IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9680{
9681 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9682}
9683
9684
9685/**
9686 * Implements 'VMPTRST'.
9687 */
9688IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9689{
9690 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9691}
9692
9693
9694/**
9695 * Implements 'VMCLEAR'.
9696 */
9697IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9698{
9699 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9700}
9701
9702
9703/**
9704 * Implements 'VMWRITE' register.
9705 */
9706IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9707{
9708 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9709}
9710
9711
9712/**
9713 * Implements 'VMWRITE' memory.
9714 */
9715IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9716{
9717 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9718}
9719
9720
9721/**
9722 * Implements 'VMREAD' register (64-bit).
9723 */
9724IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9725{
9726 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9727}
9728
9729
9730/**
9731 * Implements 'VMREAD' register (32-bit).
9732 */
9733IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9734{
9735 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9736}
9737
9738
9739/**
9740 * Implements 'VMREAD' memory, 64-bit register.
9741 */
9742IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9743{
9744 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9745}
9746
9747
9748/**
9749 * Implements 'VMREAD' memory, 32-bit register.
9750 */
9751IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9752{
9753 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9754}
9755
9756
9757/**
9758 * Implements 'INVVPID'.
9759 */
9760IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9761{
9762 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9763}
9764
9765
9766#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9767/**
9768 * Implements 'INVEPT'.
9769 */
9770IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9771{
9772 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9773}
9774#endif
9775
9776
9777/**
9778 * Implements VMX's implementation of PAUSE.
9779 */
9780IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9781{
9782 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9783 {
9784 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9785 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9786 return rcStrict;
9787 }
9788
9789 /*
9790 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9791 * a VM-exit, the instruction operates normally.
9792 */
9793 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9794}
9795
9796#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9797
9798
9799/**
9800 * Implements 'VMCALL'.
9801 */
9802IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9803{
9804 pVCpu->iem.s.cPotentialExits++;
9805
9806#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9807 /* Nested-guest intercept. */
9808 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9809 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9810#endif
9811
9812 /* Join forces with vmmcall. */
9813 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9814}
9815
9816
9817#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9818
9819/**
9820 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9821 *
9822 * @remarks The @a uUser argument is currently unused.
9823 */
9824DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9825 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9826 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9827{
9828 RT_NOREF3(pvPhys, enmOrigin, uUser);
9829
9830 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9831 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9832 {
9833 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9834 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9835
9836 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9837 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9838
9839 LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9840 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9841 if (RT_FAILURE(rcStrict))
9842 return rcStrict;
9843
9844 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9845 return VINF_SUCCESS;
9846 }
9847
9848 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9849 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9850 if (RT_FAILURE(rc))
9851 return rc;
9852
9853 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9854 return VINF_PGM_HANDLER_DO_DEFAULT;
9855}
9856
9857
9858# ifndef IN_RING3
9859/**
9860 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9861 * \#PF access handler callback for guest VMX APIC-access page.}
9862 */
9863DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
9864 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9865
9866{
9867 RT_NOREF3(pVM, pCtx, uUser);
9868
9869 /*
9870 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9871 * Otherwise we must deregister the page and allow regular RAM access.
9872 * Failing to do so lands us with endless EPT VM-exits.
9873 */
9874 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9875 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9876 {
9877 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9878 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9879
9880 /*
9881 * Check if the access causes an APIC-access VM-exit.
9882 */
9883 uint32_t fAccess;
9884 if (uErr & X86_TRAP_PF_ID)
9885 fAccess = IEM_ACCESS_INSTRUCTION;
9886 else if (uErr & X86_TRAP_PF_RW)
9887 fAccess = IEM_ACCESS_DATA_W;
9888 else
9889 fAccess = IEM_ACCESS_DATA_R;
9890
9891 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9892 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9893 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9894 LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
9895 if (fIntercept)
9896 {
9897 /*
9898 * Query the source VM-exit (from the execution engine) that caused this access
9899 * within the APIC-access page. Currently only HM is supported.
9900 */
9901 AssertMsg(VM_IS_HM_ENABLED(pVM),
9902 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
9903
9904 HMEXITAUX HmExitAux;
9905 RT_ZERO(HmExitAux);
9906 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9907 | HMVMX_READ_EXIT_QUALIFICATION
9908 | HMVMX_READ_IDT_VECTORING_INFO
9909 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9910 AssertRC(rc);
9911
9912 /*
9913 * Verify the VM-exit reason must be an EPT violation.
9914 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9915 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9916 */
9917 AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9918 ("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
9919 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
9920
9921 /*
9922 * Construct the virtual APIC-access VM-exit.
9923 */
9924 VMXAPICACCESS enmAccess;
9925 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9926 {
9927 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9928 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9929 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9930 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9931 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9932 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9933 else
9934 enmAccess = VMXAPICACCESS_LINEAR_READ;
9935
9936 /* For linear-address accesss the instruction length must be valid. */
9937 AssertMsg(HmExitAux.Vmx.cbInstr > 0,
9938 ("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
9939 }
9940 else
9941 {
9942 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9943 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
9944 else
9945 {
9946 /** @todo How to distinguish between monitoring/trace vs other instructions
9947 * here? */
9948 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
9949 }
9950
9951 /* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
9952 HmExitAux.Vmx.cbInstr = 0;
9953 }
9954
9955 /*
9956 * Raise the APIC-access VM-exit.
9957 */
9958 LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
9959 VMXVEXITINFO const ExitInfo
9960 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_APIC_ACCESS,
9961 RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
9962 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess),
9963 HmExitAux.Vmx.cbInstr);
9964 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_IDT(HmExitAux.Vmx.uIdtVectoringInfo,
9965 HmExitAux.Vmx.uIdtVectoringErrCode);
9966 VBOXSTRICTRC const rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
9967 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
9968 }
9969
9970 /*
9971 * The access isn't intercepted, which means it needs to be virtualized.
9972 *
9973 * This requires emulating the instruction because we need the bytes being
9974 * read/written by the instruction not just the offset being accessed within
9975 * the APIC-access page (which we derive from the faulting address).
9976 */
9977 LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
9978 return VINF_EM_RAW_EMULATE_INSTR;
9979 }
9980
9981 /** @todo This isn't ideal but works for now as nested-hypervisors generally play
9982 * nice because the spec states that this page should be modified only when
9983 * no CPU refers to it VMX non-root mode. Nonetheless, we could use an atomic
9984 * reference counter to ensure the aforementioned condition before
9985 * de-registering the page. */
9986 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
9987 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
9988 if (RT_FAILURE(rc))
9989 return rc;
9990
9991 return VINF_SUCCESS;
9992}
9993# endif /* !IN_RING3 */
9994
9995#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9996
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