VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 97134

Last change on this file since 97134 was 97042, checked in by vboxsync, 2 years ago

VMM/IEM: Nested VMX: bugref:10092 Slightly shorten VMXVEXITINFO_INIT_WITH macro ("QUALIFIER" -> "QUAL").
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File size: 405.5 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp 97042 2022-10-07 08:48:58Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM_VMX
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/cpum.h>
36#include <VBox/vmm/apic.h>
37#include <VBox/vmm/pgm.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/hm.h>
40#include <VBox/vmm/gim.h>
41#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
42# include <VBox/vmm/hmvmxinline.h>
43#endif
44#include <VBox/vmm/tm.h>
45#include "IEMInternal.h"
46#include <VBox/vmm/vmcc.h>
47#include <VBox/log.h>
48#include <VBox/err.h>
49#include <VBox/param.h>
50#include <VBox/disopcode.h>
51#include <iprt/asm-math.h>
52#include <iprt/assert.h>
53#include <iprt/string.h>
54#include <iprt/x86.h>
55
56#include "IEMInline.h"
57
58
59/*********************************************************************************************************************************
60* Defined Constants And Macros *
61*********************************************************************************************************************************/
62#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
63/**
64 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
65 * relative offsets.
66 */
67# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
68# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
69# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
70# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
71# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# if 0
77# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
78# endif
79# else /* !IEM_WITH_CODE_TLB */
80# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
81 do \
82 { \
83 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
84 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
85 } while (0)
86
87# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
88
89# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
90 do \
91 { \
92 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
93 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
94 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
95 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
96 } while (0)
97
98# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
99 do \
100 { \
101 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
102 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
103 } while (0)
104
105# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
106 do \
107 { \
108 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
109 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
110 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
111 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
112 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
113 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
114 } while (0)
115
116# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
117 do \
118 { \
119 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
120 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
121 } while (0)
122
123# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
124 do \
125 { \
126 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
127 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
128 } while (0)
129
130# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
131 do \
132 { \
133 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
134 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
135 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
136 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
137 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
138 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
139 } while (0)
140# endif /* !IEM_WITH_CODE_TLB */
141
142/** Check for VMX instructions requiring to be in VMX operation.
143 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
144# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
145 do \
146 { \
147 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
148 { /* likely */ } \
149 else \
150 { \
151 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
152 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
153 return iemRaiseUndefinedOpcode(a_pVCpu); \
154 } \
155 } while (0)
156
157/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
158# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
159 do \
160 { \
161 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
162 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
163 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
164 return VERR_VMX_VMENTRY_FAILED; \
165 } while (0)
166
167/** Marks a VM-exit failure with a diagnostic reason and logs. */
168# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
169 do \
170 { \
171 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
172 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
173 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
174 } while (0)
175
176/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
177# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
178 do \
179 { \
180 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
181 return VERR_VMX_VMEXIT_FAILED; \
182 } while (0)
183
184
185/*********************************************************************************************************************************
186* Global Variables *
187*********************************************************************************************************************************/
188/** @todo NSTVMX: The following VM-exit intercepts are pending:
189 * VMX_EXIT_IO_SMI
190 * VMX_EXIT_SMI
191 * VMX_EXIT_GETSEC
192 * VMX_EXIT_RSM
193 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
194 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
195 * VMX_EXIT_RDRAND
196 * VMX_EXIT_VMFUNC
197 * VMX_EXIT_ENCLS
198 * VMX_EXIT_RDSEED
199 * VMX_EXIT_PML_FULL
200 * VMX_EXIT_XSAVES
201 * VMX_EXIT_XRSTORS
202 */
203/**
204 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
205 *
206 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
207 * second dimension is the Index, see VMXVMCSFIELD.
208 */
209uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
210{
211 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
212 {
213 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
214 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
215 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
216 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
217 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
218 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
219 /* 27 */ UINT16_MAX,
220 },
221 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
222 {
223 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
224 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
237 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
238 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
239 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
240 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
241 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
242 /* 26-27 */ UINT16_MAX, UINT16_MAX
243 },
244 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
245 {
246 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
247 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
248 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
249 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
250 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
251 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
252 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
253 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
254 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
255 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
256 },
257 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
258 {
259 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
260 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
261 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
262 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
263 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
264 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
265 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
266 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
267 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
268 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
269 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
270 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
271 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
272 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
273 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
274 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
275 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
276 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
277 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
278 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
279 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
280 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
281 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
282 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
283 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
284 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
285 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
286 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
287 },
288 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
289 {
290 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
291 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
292 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
293 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
294 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
295 },
296 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
297 {
298 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
299 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
300 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
301 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
302 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
303 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
304 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
305 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
306 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
307 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
308 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
309 /* 11 */ UINT16_MAX,
310 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
311 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
312 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
313 },
314 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
315 {
316 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
317 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
318 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
319 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
320 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
321 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
322 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
334 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
335 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
336 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
337 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
338 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
339 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
340 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
341 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
342 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
343 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
344 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
345 /* 26-27 */ UINT16_MAX, UINT16_MAX
346 },
347 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
348 {
349 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
350 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
351 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
352 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
353 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
354 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
355 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
356 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
357 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
358 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
359 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
360 },
361 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
362 {
363 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
364 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
365 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
366 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
367 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
368 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
369 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
370 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
371 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
372 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
373 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
374 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
375 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
376 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
377 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
378 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
379 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
380 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
381 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
382 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
383 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
384 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
385 /* 22 */ UINT16_MAX,
386 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
387 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
388 },
389 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
390 {
391 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
392 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
394 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
395 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
396 },
397 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
398 {
399 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
400 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
401 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
402 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
403 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
404 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
405 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
406 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
407 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
408 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
409 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
410 },
411 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
412 {
413 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
414 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
415 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
416 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
417 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
418 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
419 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
420 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
421 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
437 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
438 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
439 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
440 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
441 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
442 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
443 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
444 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
445 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
446 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
447 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
448 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
449 },
450 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
451 {
452 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
453 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
454 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
455 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
456 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
457 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
458 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
459 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
460 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
461 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
462 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
463 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
464 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
465 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
466 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
467 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
468 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
469 }
470};
471
472
473/**
474 * Gets a host selector from the VMCS.
475 *
476 * @param pVmcs Pointer to the virtual VMCS.
477 * @param iSelReg The index of the segment register (X86_SREG_XXX).
478 */
479DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
480{
481 Assert(iSegReg < X86_SREG_COUNT);
482 RTSEL HostSel;
483 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
484 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
485 uint8_t const uWidthType = (uWidth << 2) | uType;
486 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
487 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
488 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
489 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
490 uint8_t const *pbField = pbVmcs + offField;
491 HostSel = *(uint16_t *)pbField;
492 return HostSel;
493}
494
495
496/**
497 * Sets a guest segment register in the VMCS.
498 *
499 * @param pVmcs Pointer to the virtual VMCS.
500 * @param iSegReg The index of the segment register (X86_SREG_XXX).
501 * @param pSelReg Pointer to the segment register.
502 */
503static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
504{
505 Assert(pSelReg);
506 Assert(iSegReg < X86_SREG_COUNT);
507
508 /* Selector. */
509 {
510 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
511 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
512 uint8_t const uWidthType = (uWidth << 2) | uType;
513 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
514 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
515 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
516 uint8_t *pbVmcs = (uint8_t *)pVmcs;
517 uint8_t *pbField = pbVmcs + offField;
518 *(uint16_t *)pbField = pSelReg->Sel;
519 }
520
521 /* Limit. */
522 {
523 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
524 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
525 uint8_t const uWidthType = (uWidth << 2) | uType;
526 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
527 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
528 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
529 uint8_t *pbVmcs = (uint8_t *)pVmcs;
530 uint8_t *pbField = pbVmcs + offField;
531 *(uint32_t *)pbField = pSelReg->u32Limit;
532 }
533
534 /* Base. */
535 {
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t const *pbField = pbVmcs + offField;
544 *(uint64_t *)pbField = pSelReg->u64Base;
545 }
546
547 /* Attributes. */
548 {
549 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
550 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
551 | X86DESCATTR_UNUSABLE;
552 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
553 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
554 uint8_t const uWidthType = (uWidth << 2) | uType;
555 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
556 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
557 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
558 uint8_t *pbVmcs = (uint8_t *)pVmcs;
559 uint8_t *pbField = pbVmcs + offField;
560 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
561 }
562}
563
564
565/**
566 * Gets a guest segment register from the VMCS.
567 *
568 * @returns VBox status code.
569 * @param pVmcs Pointer to the virtual VMCS.
570 * @param iSegReg The index of the segment register (X86_SREG_XXX).
571 * @param pSelReg Where to store the segment register (only updated when
572 * VINF_SUCCESS is returned).
573 *
574 * @remarks Warning! This does not validate the contents of the retrieved segment
575 * register.
576 */
577static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
578{
579 Assert(pSelReg);
580 Assert(iSegReg < X86_SREG_COUNT);
581
582 /* Selector. */
583 uint16_t u16Sel;
584 {
585 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
586 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
587 uint8_t const uWidthType = (uWidth << 2) | uType;
588 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
589 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
590 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
591 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
592 uint8_t const *pbField = pbVmcs + offField;
593 u16Sel = *(uint16_t *)pbField;
594 }
595
596 /* Limit. */
597 uint32_t u32Limit;
598 {
599 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
600 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
601 uint8_t const uWidthType = (uWidth << 2) | uType;
602 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
603 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
604 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
605 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
606 uint8_t const *pbField = pbVmcs + offField;
607 u32Limit = *(uint32_t *)pbField;
608 }
609
610 /* Base. */
611 uint64_t u64Base;
612 {
613 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
614 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
615 uint8_t const uWidthType = (uWidth << 2) | uType;
616 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
617 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
618 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
619 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
620 uint8_t const *pbField = pbVmcs + offField;
621 u64Base = *(uint64_t *)pbField;
622 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
623 }
624
625 /* Attributes. */
626 uint32_t u32Attr;
627 {
628 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
629 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
630 uint8_t const uWidthType = (uWidth << 2) | uType;
631 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
632 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
633 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
634 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
635 uint8_t const *pbField = pbVmcs + offField;
636 u32Attr = *(uint32_t *)pbField;
637 }
638
639 pSelReg->Sel = u16Sel;
640 pSelReg->ValidSel = u16Sel;
641 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
642 pSelReg->u32Limit = u32Limit;
643 pSelReg->u64Base = u64Base;
644 pSelReg->Attr.u = u32Attr;
645 return VINF_SUCCESS;
646}
647
648
649/**
650 * Converts an IEM exception event type to a VMX event type.
651 *
652 * @returns The VMX event type.
653 * @param uVector The interrupt / exception vector.
654 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
655 */
656DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
657{
658 /* Paranoia (callers may use these interchangeably). */
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
660 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
661 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
662 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
663 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
664 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
665 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
666 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
667 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
668 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
669 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
670 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
671
672 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
673 {
674 if (uVector == X86_XCPT_NMI)
675 return VMX_EXIT_INT_INFO_TYPE_NMI;
676 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
677 }
678
679 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
680 {
681 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
682 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
683 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
684 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
685 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
686 }
687
688 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
689 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
690}
691
692
693/**
694 * Determines whether the guest is using PAE paging given the VMCS.
695 *
696 * @returns @c true if PAE paging mode is used, @c false otherwise.
697 * @param pVmcs Pointer to the virtual VMCS.
698 *
699 * @warning Only use this prior to switching the guest-CPU state with the
700 * nested-guest CPU state!
701 */
702DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
703{
704 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
705 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
706 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
707}
708
709
710/**
711 * Sets the Exit qualification VMCS field.
712 *
713 * @param pVCpu The cross context virtual CPU structure.
714 * @param u64ExitQual The Exit qualification.
715 */
716DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
717{
718 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
719}
720
721
722/**
723 * Sets the VM-exit interruption information field.
724 *
725 * @param pVCpu The cross context virtual CPU structure.
726 * @param uExitIntInfo The VM-exit interruption information.
727 */
728DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
729{
730 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
731}
732
733
734/**
735 * Sets the VM-exit interruption error code.
736 *
737 * @param pVCpu The cross context virtual CPU structure.
738 * @param uErrCode The error code.
739 */
740DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
741{
742 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
743}
744
745
746/**
747 * Sets the IDT-vectoring information field.
748 *
749 * @param pVCpu The cross context virtual CPU structure.
750 * @param uIdtVectorInfo The IDT-vectoring information.
751 */
752DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
753{
754 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
755}
756
757
758/**
759 * Sets the IDT-vectoring error code field.
760 *
761 * @param pVCpu The cross context virtual CPU structure.
762 * @param uErrCode The error code.
763 */
764DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
765{
766 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
767}
768
769
770/**
771 * Sets the VM-exit guest-linear address VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uGuestLinearAddr The VM-exit guest-linear address.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
777{
778 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
779 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
780 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
781}
782
783
784/**
785 * Sets the VM-exit guest-physical address VMCS field.
786 *
787 * @param pVCpu The cross context virtual CPU structure.
788 * @param uGuestPhysAddr The VM-exit guest-physical address.
789 */
790DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
791{
792 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
793}
794
795
796/**
797 * Sets the VM-exit instruction length VMCS field.
798 *
799 * @param pVCpu The cross context virtual CPU structure.
800 * @param cbInstr The VM-exit instruction length in bytes.
801 *
802 * @remarks Callers may clear this field to 0. Hence, this function does not check
803 * the validity of the instruction length.
804 */
805DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
806{
807 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
808}
809
810
811/**
812 * Sets the VM-exit instruction info. VMCS field.
813 *
814 * @param pVCpu The cross context virtual CPU structure.
815 * @param uExitInstrInfo The VM-exit instruction information.
816 */
817DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
818{
819 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
820}
821
822
823/**
824 * Sets the guest pending-debug exceptions field.
825 *
826 * @param pVCpu The cross context virtual CPU structure.
827 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
828 */
829DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
830{
831 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
832 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
833}
834
835
836/**
837 * Implements VMSucceed for VMX instruction success.
838 *
839 * @param pVCpu The cross context virtual CPU structure.
840 */
841DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
842{
843 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
844}
845
846
847/**
848 * Implements VMFailInvalid for VMX instruction failure.
849 *
850 * @param pVCpu The cross context virtual CPU structure.
851 */
852DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
853{
854 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
855}
856
857
858/**
859 * Implements VMFail for VMX instruction failure.
860 *
861 * @param pVCpu The cross context virtual CPU structure.
862 * @param enmInsErr The VM instruction error.
863 */
864DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
865{
866 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
867}
868
869
870/**
871 * Checks if the given auto-load/store MSR area count is valid for the
872 * implementation.
873 *
874 * @returns @c true if it's within the valid limit, @c false otherwise.
875 * @param pVCpu The cross context virtual CPU structure.
876 * @param uMsrCount The MSR area count to check.
877 */
878DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
879{
880 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
881 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
882 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
883 if (uMsrCount <= cMaxSupportedMsrs)
884 return true;
885 return false;
886}
887
888
889/**
890 * Flushes the current VMCS contents back to guest memory.
891 *
892 * @returns VBox status code.
893 * @param pVCpu The cross context virtual CPU structure.
894 */
895DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
896{
897 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
898 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
899 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
900 return rc;
901}
902
903
904/**
905 * Populates the current VMCS contents from guest memory.
906 *
907 * @returns VBox status code.
908 * @param pVCpu The cross context virtual CPU structure.
909 */
910DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
911{
912 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
913 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
914 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
915 return rc;
916}
917
918
919/**
920 * Gets the instruction diagnostic for segment base checks during VM-entry of a
921 * nested-guest.
922 *
923 * @param iSegReg The segment index (X86_SREG_XXX).
924 */
925static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
926{
927 switch (iSegReg)
928 {
929 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
930 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
931 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
932 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
933 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
934 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
935 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
936 }
937}
938
939
940/**
941 * Gets the instruction diagnostic for segment base checks during VM-entry of a
942 * nested-guest that is in Virtual-8086 mode.
943 *
944 * @param iSegReg The segment index (X86_SREG_XXX).
945 */
946static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
947{
948 switch (iSegReg)
949 {
950 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
951 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
952 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
953 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
954 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
955 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
956 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
957 }
958}
959
960
961/**
962 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
963 * nested-guest that is in Virtual-8086 mode.
964 *
965 * @param iSegReg The segment index (X86_SREG_XXX).
966 */
967static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
968{
969 switch (iSegReg)
970 {
971 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
972 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
973 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
974 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
975 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
976 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
977 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
978 }
979}
980
981
982/**
983 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
984 * nested-guest that is in Virtual-8086 mode.
985 *
986 * @param iSegReg The segment index (X86_SREG_XXX).
987 */
988static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
989{
990 switch (iSegReg)
991 {
992 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
993 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
994 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
995 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
996 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
997 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
998 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
999 }
1000}
1001
1002
1003/**
1004 * Gets the instruction diagnostic for segment attributes reserved bits failure
1005 * during VM-entry of a nested-guest.
1006 *
1007 * @param iSegReg The segment index (X86_SREG_XXX).
1008 */
1009static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1010{
1011 switch (iSegReg)
1012 {
1013 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1014 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1015 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1016 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1017 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1018 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1019 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1020 }
1021}
1022
1023
1024/**
1025 * Gets the instruction diagnostic for segment attributes descriptor-type
1026 * (code/segment or system) failure during VM-entry of a nested-guest.
1027 *
1028 * @param iSegReg The segment index (X86_SREG_XXX).
1029 */
1030static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1031{
1032 switch (iSegReg)
1033 {
1034 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1035 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1036 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1037 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1038 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1039 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1040 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1041 }
1042}
1043
1044
1045/**
1046 * Gets the instruction diagnostic for segment attributes descriptor-type
1047 * (code/segment or system) failure during VM-entry of a nested-guest.
1048 *
1049 * @param iSegReg The segment index (X86_SREG_XXX).
1050 */
1051static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1052{
1053 switch (iSegReg)
1054 {
1055 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1056 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1057 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1058 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1059 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1060 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1061 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1062 }
1063}
1064
1065
1066/**
1067 * Gets the instruction diagnostic for segment attribute granularity failure during
1068 * VM-entry of a nested-guest.
1069 *
1070 * @param iSegReg The segment index (X86_SREG_XXX).
1071 */
1072static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1073{
1074 switch (iSegReg)
1075 {
1076 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1077 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1078 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1079 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1080 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1081 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1082 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1083 }
1084}
1085
1086/**
1087 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1088 * VM-entry of a nested-guest.
1089 *
1090 * @param iSegReg The segment index (X86_SREG_XXX).
1091 */
1092static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1093{
1094 switch (iSegReg)
1095 {
1096 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1097 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1098 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1099 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1100 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1101 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1102 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1103 }
1104}
1105
1106
1107/**
1108 * Gets the instruction diagnostic for segment attribute type accessed failure
1109 * during VM-entry of a nested-guest.
1110 *
1111 * @param iSegReg The segment index (X86_SREG_XXX).
1112 */
1113static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1114{
1115 switch (iSegReg)
1116 {
1117 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1118 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1119 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1120 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1121 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1122 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1123 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1124 }
1125}
1126
1127
1128/**
1129 * Saves the guest control registers, debug registers and some MSRs are part of
1130 * VM-exit.
1131 *
1132 * @param pVCpu The cross context virtual CPU structure.
1133 */
1134static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1135{
1136 /*
1137 * Saves the guest control registers, debug registers and some MSRs.
1138 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1139 */
1140 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1141
1142 /* Save control registers. */
1143 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1144 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1145 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1146
1147 /* Save SYSENTER CS, ESP, EIP. */
1148 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1149 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1150 {
1151 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1152 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1153 }
1154 else
1155 {
1156 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1157 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1158 }
1159
1160 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1161 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1162 {
1163 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1164 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1165 }
1166
1167 /* Save PAT MSR. */
1168 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1169 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1170
1171 /* Save EFER MSR. */
1172 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1173 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1174
1175 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1176 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1177
1178 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1179}
1180
1181
1182/**
1183 * Saves the guest force-flags in preparation of entering the nested-guest.
1184 *
1185 * @param pVCpu The cross context virtual CPU structure.
1186 */
1187static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1188{
1189 /* We shouldn't be called multiple times during VM-entry. */
1190 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1191
1192 /* MTF should not be set outside VMX non-root mode. */
1193 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1194
1195 /*
1196 * Preserve the required force-flags.
1197 *
1198 * We cache and clear force-flags that would affect the execution of the
1199 * nested-guest. Cached flags are then restored while returning to the guest
1200 * if necessary.
1201 *
1202 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1203 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1204 * instruction. Interrupt inhibition for any nested-guest instruction
1205 * is supplied by the guest-interruptibility state VMCS field and will
1206 * be set up as part of loading the guest state. Technically
1207 * blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1208 * disallow it since we can't distinguish it from blocking-by-MovSS
1209 * and no nested-hypervisor we care about uses STI immediately
1210 * followed by VMLAUNCH/VMRESUME.
1211 *
1212 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1213 * successful VM-entry (due to invalid guest-state) need to continue
1214 * blocking NMIs if it was in effect before VM-entry.
1215 *
1216 * - MTF need not be preserved as it's used only in VMX non-root mode and
1217 * is supplied through the VM-execution controls.
1218 *
1219 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1220 * we will be able to generate interrupts that may cause VM-exits for
1221 * the nested-guest.
1222 */
1223 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1224}
1225
1226
1227/**
1228 * Restores the guest force-flags in preparation of exiting the nested-guest.
1229 *
1230 * @param pVCpu The cross context virtual CPU structure.
1231 */
1232static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1233{
1234 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1235 {
1236 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1237 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1238 }
1239}
1240
1241
1242/**
1243 * Performs the VMX transition to/from VMX non-root mode.
1244 *
1245 * @param pVCpu The cross context virtual CPU structure.
1246*/
1247static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1248{
1249 /*
1250 * Inform PGM about paging mode changes.
1251 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1252 * see comment in iemMemPageTranslateAndCheckAccess().
1253 */
1254 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1255 true /* fForce */);
1256 if (RT_SUCCESS(rc))
1257 { /* likely */ }
1258 else
1259 return rc;
1260
1261 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1262 IEMTlbInvalidateAll(pVCpu);
1263
1264 /* Inform CPUM (recompiler), can later be removed. */
1265 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1266
1267 /* Re-initialize IEM cache/state after the drastic mode switch. */
1268 iemReInitExec(pVCpu);
1269 return rc;
1270}
1271
1272
1273/**
1274 * Calculates the current VMX-preemption timer value.
1275 *
1276 * @returns The current VMX-preemption timer value.
1277 * @param pVCpu The cross context virtual CPU structure.
1278 */
1279static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1280{
1281 /*
1282 * Assume the following:
1283 * PreemptTimerShift = 5
1284 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1285 * EntryTick = 50000 (TSC at time of VM-entry)
1286 *
1287 * CurTick Delta PreemptTimerVal
1288 * ----------------------------------
1289 * 60000 10000 2
1290 * 80000 30000 1
1291 * 90000 40000 0 -> VM-exit.
1292 *
1293 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1294 * The saved VMX-preemption timer value is calculated as follows:
1295 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1296 * E.g.:
1297 * Delta = 10000
1298 * Tmp = 10000 / (2 * 10000) = 0.5
1299 * NewPt = 2 - 0.5 = 2
1300 * Delta = 30000
1301 * Tmp = 30000 / (2 * 10000) = 1.5
1302 * NewPt = 2 - 1.5 = 1
1303 * Delta = 40000
1304 * Tmp = 40000 / 20000 = 2
1305 * NewPt = 2 - 2 = 0
1306 */
1307 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1308 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1309 if (uVmcsPreemptVal > 0)
1310 {
1311 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1312 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1313 uint64_t const uDelta = uCurTick - uEntryTick;
1314 uint32_t const uPreemptTimer = uVmcsPreemptVal
1315 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1316 return uPreemptTimer;
1317 }
1318 return 0;
1319}
1320
1321
1322/**
1323 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1324 *
1325 * @param pVCpu The cross context virtual CPU structure.
1326 */
1327static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1328{
1329 /*
1330 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1331 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1332 */
1333 /* CS, SS, ES, DS, FS, GS. */
1334 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1335 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1336 {
1337 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1338 if (!pSelReg->Attr.n.u1Unusable)
1339 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1340 else
1341 {
1342 /*
1343 * For unusable segments the attributes are undefined except for CS and SS.
1344 * For the rest we don't bother preserving anything but the unusable bit.
1345 */
1346 switch (iSegReg)
1347 {
1348 case X86_SREG_CS:
1349 pVmcs->GuestCs = pSelReg->Sel;
1350 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1351 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1352 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1353 | X86DESCATTR_UNUSABLE);
1354 break;
1355
1356 case X86_SREG_SS:
1357 pVmcs->GuestSs = pSelReg->Sel;
1358 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1359 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1360 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1361 break;
1362
1363 case X86_SREG_DS:
1364 pVmcs->GuestDs = pSelReg->Sel;
1365 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1366 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1367 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1368 break;
1369
1370 case X86_SREG_ES:
1371 pVmcs->GuestEs = pSelReg->Sel;
1372 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1373 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1374 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1375 break;
1376
1377 case X86_SREG_FS:
1378 pVmcs->GuestFs = pSelReg->Sel;
1379 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1380 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1381 break;
1382
1383 case X86_SREG_GS:
1384 pVmcs->GuestGs = pSelReg->Sel;
1385 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1386 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1387 break;
1388 }
1389 }
1390 }
1391
1392 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1393 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1394 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1395 | X86DESCATTR_UNUSABLE;
1396 /* LDTR. */
1397 {
1398 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1399 pVmcs->GuestLdtr = pSelReg->Sel;
1400 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1401 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1402 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1403 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1404 }
1405
1406 /* TR. */
1407 {
1408 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1409 pVmcs->GuestTr = pSelReg->Sel;
1410 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1411 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1412 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1413 }
1414
1415 /* GDTR. */
1416 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1417 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1418
1419 /* IDTR. */
1420 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1421 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1422}
1423
1424
1425/**
1426 * Saves guest non-register state as part of VM-exit.
1427 *
1428 * @param pVCpu The cross context virtual CPU structure.
1429 * @param uExitReason The VM-exit reason.
1430 */
1431static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1432{
1433 /*
1434 * Save guest non-register state.
1435 * See Intel spec. 27.3.4 "Saving Non-Register State".
1436 */
1437 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1438
1439 /*
1440 * Activity state.
1441 * Most VM-exits will occur in the active state. However, if the first instruction
1442 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1443 * the VM-exit will be from the HLT activity state.
1444 *
1445 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1446 */
1447 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1448 * not? */
1449 EMSTATE const enmActivityState = EMGetState(pVCpu);
1450 switch (enmActivityState)
1451 {
1452 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1453 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1454 }
1455
1456 /*
1457 * Interruptibility-state.
1458 */
1459 /* NMI. */
1460 pVmcs->u32GuestIntrState = 0;
1461 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1462 {
1463 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1464 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1465 }
1466 else
1467 {
1468 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1469 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1470 }
1471
1472 /* Blocking-by-STI. */
1473 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1474 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1475 {
1476 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1477 * currently. */
1478 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1479
1480 /* Clear inhibition unconditionally since we've ensured it isn't set prior to executing VMLAUNCH/VMRESUME. */
1481 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1482 }
1483 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1484
1485 /*
1486 * Pending debug exceptions.
1487 *
1488 * For VM-exits where it is not applicable, we can safely zero out the field.
1489 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1490 */
1491 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1492 && uExitReason != VMX_EXIT_SMI
1493 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1494 && !VMXIsVmexitTrapLike(uExitReason))
1495 {
1496 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1497 * block-by-MovSS is in effect. */
1498 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1499 }
1500
1501 /*
1502 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1503 *
1504 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1505 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1506 */
1507 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1508 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1509 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1510
1511 /*
1512 * Save the guest PAE PDPTEs.
1513 */
1514 if ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1515 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
1516 {
1517 /*
1518 * Without EPT or when the nested-guest is not using PAE paging, the values saved
1519 * in the VMCS during VM-exit are undefined. We zero them here for consistency.
1520 */
1521 pVmcs->u64GuestPdpte0.u = 0;
1522 pVmcs->u64GuestPdpte1.u = 0;
1523 pVmcs->u64GuestPdpte2.u = 0;
1524 pVmcs->u64GuestPdpte3.u = 0;
1525 }
1526 else
1527 {
1528 /*
1529 * With EPT and when the nested-guest is using PAE paging, we update the PDPTEs from
1530 * the nested-guest CPU context. Both IEM (Mov CRx) and hardware-assisted execution
1531 * of the nested-guest is expected to have updated them.
1532 */
1533 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1534 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1535 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1536 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1537 }
1538
1539 /* Clear PGM's copy of the EPT pointer for added safety. */
1540 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1541 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1542}
1543
1544
1545/**
1546 * Saves the guest-state as part of VM-exit.
1547 *
1548 * @returns VBox status code.
1549 * @param pVCpu The cross context virtual CPU structure.
1550 * @param uExitReason The VM-exit reason.
1551 */
1552static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1553{
1554 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1555 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1556
1557 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1558 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1559 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1560
1561 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1562}
1563
1564
1565/**
1566 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1567 *
1568 * @returns VBox status code.
1569 * @param pVCpu The cross context virtual CPU structure.
1570 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1571 */
1572static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1573{
1574 /*
1575 * Save guest MSRs.
1576 * See Intel spec. 27.4 "Saving MSRs".
1577 */
1578 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1579 const char * const pszFailure = "VMX-abort";
1580
1581 /*
1582 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1583 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1584 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1585 */
1586 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1587 if (!cMsrs)
1588 return VINF_SUCCESS;
1589
1590 /*
1591 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1592 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1593 * implementation causes a VMX-abort followed by a triple-fault.
1594 */
1595 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1596 if (fIsMsrCountValid)
1597 { /* likely */ }
1598 else
1599 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1600
1601 /*
1602 * Optimization if the nested hypervisor is using the same guest-physical page for both
1603 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1604 */
1605 PVMXAUTOMSR pMsrArea;
1606 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1607 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1608 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1609 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1610 else
1611 {
1612 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1613 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1614 if (RT_SUCCESS(rc))
1615 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1616 else
1617 {
1618 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1619 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1620 }
1621 }
1622
1623 /*
1624 * Update VM-exit MSR store area.
1625 */
1626 PVMXAUTOMSR pMsr = pMsrArea;
1627 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1628 {
1629 if ( !pMsr->u32Reserved
1630 && pMsr->u32Msr != MSR_IA32_SMBASE
1631 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1632 {
1633 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1634 if (rcStrict == VINF_SUCCESS)
1635 continue;
1636
1637 /*
1638 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1639 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1640 * recording the MSR index in the auxiliary info. field and indicated further by our
1641 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1642 * if possible, or come up with a better, generic solution.
1643 */
1644 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1645 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1646 ? kVmxVDiag_Vmexit_MsrStoreRing3
1647 : kVmxVDiag_Vmexit_MsrStore;
1648 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1649 }
1650 else
1651 {
1652 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1653 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1654 }
1655 }
1656
1657 /*
1658 * Commit the VM-exit MSR store are to guest memory.
1659 */
1660 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1661 if (RT_SUCCESS(rc))
1662 return VINF_SUCCESS;
1663
1664 NOREF(uExitReason);
1665 NOREF(pszFailure);
1666
1667 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1668 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1669}
1670
1671
1672/**
1673 * Performs a VMX abort (due to an fatal error during VM-exit).
1674 *
1675 * @returns Strict VBox status code.
1676 * @param pVCpu The cross context virtual CPU structure.
1677 * @param enmAbort The VMX abort reason.
1678 */
1679static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1680{
1681 /*
1682 * Perform the VMX abort.
1683 * See Intel spec. 27.7 "VMX Aborts".
1684 */
1685 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1686
1687 /* We don't support SMX yet. */
1688 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1689 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1690 {
1691 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1692 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1693 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1694 }
1695
1696 return VINF_EM_TRIPLE_FAULT;
1697}
1698
1699
1700/**
1701 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1702 *
1703 * @param pVCpu The cross context virtual CPU structure.
1704 */
1705static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1706{
1707 /*
1708 * Load host control registers, debug registers and MSRs.
1709 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1710 */
1711 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1712 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1713
1714 /* CR0. */
1715 {
1716 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1717 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu);
1718 uint64_t const uCr0Mb0 = VMX_V_CR0_FIXED1;
1719 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1720 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1721 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1722 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1723
1724 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1725 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1726 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1727 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1728 }
1729
1730 /* CR4. */
1731 {
1732 /* CR4 fixed bits are not modified. */
1733 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1734 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1735 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1736 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1737 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1738 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1739 if (fHostInLongMode)
1740 uValidHostCr4 |= X86_CR4_PAE;
1741 else
1742 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1743
1744 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1745 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1746 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1747 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1748 }
1749
1750 /* CR3 (host value validated while checking host-state during VM-entry). */
1751 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1752
1753 /* DR7. */
1754 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1755
1756 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1757
1758 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1759 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1760 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1761 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1762
1763 /* FS, GS bases are loaded later while we load host segment registers. */
1764
1765 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1766 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1767 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1768 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1769 {
1770 if (fHostInLongMode)
1771 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1772 else
1773 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1774 }
1775
1776 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1777
1778 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1779 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1780 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1781
1782 /* We don't support IA32_BNDCFGS MSR yet. */
1783}
1784
1785
1786/**
1787 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1788 *
1789 * @param pVCpu The cross context virtual CPU structure.
1790 */
1791static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1792{
1793 /*
1794 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1795 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1796 *
1797 * Warning! Be careful to not touch fields that are reserved by VT-x,
1798 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1799 */
1800 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1801 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1802
1803 /* CS, SS, ES, DS, FS, GS. */
1804 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1805 {
1806 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1807 bool const fUnusable = RT_BOOL(HostSel == 0);
1808 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1809
1810 /* Selector. */
1811 pSelReg->Sel = HostSel;
1812 pSelReg->ValidSel = HostSel;
1813 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1814
1815 /* Limit. */
1816 pSelReg->u32Limit = 0xffffffff;
1817
1818 /* Base. */
1819 pSelReg->u64Base = 0;
1820
1821 /* Attributes. */
1822 if (iSegReg == X86_SREG_CS)
1823 {
1824 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1825 pSelReg->Attr.n.u1DescType = 1;
1826 pSelReg->Attr.n.u2Dpl = 0;
1827 pSelReg->Attr.n.u1Present = 1;
1828 pSelReg->Attr.n.u1Long = fHostInLongMode;
1829 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1830 pSelReg->Attr.n.u1Granularity = 1;
1831 Assert(!pSelReg->Attr.n.u1Unusable);
1832 Assert(!fUnusable);
1833 }
1834 else
1835 {
1836 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1837 pSelReg->Attr.n.u1DescType = 1;
1838 pSelReg->Attr.n.u2Dpl = 0;
1839 pSelReg->Attr.n.u1Present = 1;
1840 pSelReg->Attr.n.u1DefBig = 1;
1841 pSelReg->Attr.n.u1Granularity = 1;
1842 pSelReg->Attr.n.u1Unusable = fUnusable;
1843 }
1844 }
1845
1846 /* FS base. */
1847 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1848 || fHostInLongMode)
1849 {
1850 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1851 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1852 }
1853
1854 /* GS base. */
1855 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1856 || fHostInLongMode)
1857 {
1858 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1859 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1860 }
1861
1862 /* TR. */
1863 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1864 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1865 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1866 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1867 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1868 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1869 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1870 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1871 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1872 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1873 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1874 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1875 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1876
1877 /* LDTR (Warning! do not touch the base and limits here). */
1878 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1879 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1880 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1881 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1882
1883 /* GDTR. */
1884 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1885 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1886 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1887
1888 /* IDTR.*/
1889 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1890 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1891 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1892}
1893
1894
1895/**
1896 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1897 *
1898 * @returns VBox status code.
1899 * @param pVCpu The cross context virtual CPU structure.
1900 * @param uExitReason The VMX instruction name (for logging purposes).
1901 */
1902static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1903{
1904 /*
1905 * Load host MSRs.
1906 * See Intel spec. 27.6 "Loading MSRs".
1907 */
1908 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1909 const char * const pszFailure = "VMX-abort";
1910
1911 /*
1912 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1913 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1914 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1915 */
1916 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1917 if (!cMsrs)
1918 return VINF_SUCCESS;
1919
1920 /*
1921 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1922 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1923 * implementation causes a VMX-abort followed by a triple-fault.
1924 */
1925 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1926 if (fIsMsrCountValid)
1927 { /* likely */ }
1928 else
1929 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1930
1931 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1932 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1933 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1934 if (RT_SUCCESS(rc))
1935 {
1936 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1937 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1938 {
1939 if ( !pMsr->u32Reserved
1940 && pMsr->u32Msr != MSR_K8_FS_BASE
1941 && pMsr->u32Msr != MSR_K8_GS_BASE
1942 && pMsr->u32Msr != MSR_K6_EFER
1943 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1944 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1945 {
1946 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1947 if (rcStrict == VINF_SUCCESS)
1948 continue;
1949
1950 /*
1951 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1952 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1953 * recording the MSR index in the auxiliary info. field and indicated further by our
1954 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1955 * if possible, or come up with a better, generic solution.
1956 */
1957 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1958 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1959 ? kVmxVDiag_Vmexit_MsrLoadRing3
1960 : kVmxVDiag_Vmexit_MsrLoad;
1961 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1962 }
1963 else
1964 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1965 }
1966 }
1967 else
1968 {
1969 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1970 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1971 }
1972
1973 NOREF(uExitReason);
1974 NOREF(pszFailure);
1975 return VINF_SUCCESS;
1976}
1977
1978
1979/**
1980 * Loads the host state as part of VM-exit.
1981 *
1982 * @returns Strict VBox status code.
1983 * @param pVCpu The cross context virtual CPU structure.
1984 * @param uExitReason The VM-exit reason (for logging purposes).
1985 */
1986static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1987{
1988 /*
1989 * Load host state.
1990 * See Intel spec. 27.5 "Loading Host State".
1991 */
1992 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1993 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1994
1995 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1996 if ( CPUMIsGuestInLongMode(pVCpu)
1997 && !fHostInLongMode)
1998 {
1999 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2000 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2001 }
2002
2003 /*
2004 * Check host PAE PDPTEs prior to loading the host state.
2005 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2006 */
2007 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2008 && !fHostInLongMode
2009 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2010 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2011 {
2012 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2013 if (RT_SUCCESS(rc))
2014 { /* likely*/ }
2015 else
2016 {
2017 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2018 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2019 }
2020 }
2021
2022 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2023 iemVmxVmexitLoadHostSegRegs(pVCpu);
2024
2025 /*
2026 * Load host RIP, RSP and RFLAGS.
2027 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2028 */
2029 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2030 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2031 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2032
2033 /* Clear address range monitoring. */
2034 EMMonitorWaitClear(pVCpu);
2035
2036 /* Perform the VMX transition (PGM updates). */
2037 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2038 if (rcStrict == VINF_SUCCESS)
2039 { /* likely */ }
2040 else if (RT_SUCCESS(rcStrict))
2041 {
2042 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2043 uExitReason));
2044 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2045 }
2046 else
2047 {
2048 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2049 return VBOXSTRICTRC_VAL(rcStrict);
2050 }
2051
2052 Assert(rcStrict == VINF_SUCCESS);
2053
2054 /* Load MSRs from the VM-exit auto-load MSR area. */
2055 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2056 if (RT_FAILURE(rc))
2057 {
2058 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2059 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2060 }
2061 return VINF_SUCCESS;
2062}
2063
2064
2065/**
2066 * Gets VM-exit instruction information along with any displacement for an
2067 * instruction VM-exit.
2068 *
2069 * @returns The VM-exit instruction information.
2070 * @param pVCpu The cross context virtual CPU structure.
2071 * @param uExitReason The VM-exit reason.
2072 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2073 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2074 * NULL.
2075 */
2076static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2077{
2078 RTGCPTR GCPtrDisp;
2079 VMXEXITINSTRINFO ExitInstrInfo;
2080 ExitInstrInfo.u = 0;
2081
2082 /*
2083 * Get and parse the ModR/M byte from our decoded opcodes.
2084 */
2085 uint8_t bRm;
2086 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2087 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2088 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2089 {
2090 /*
2091 * ModR/M indicates register addressing.
2092 *
2093 * The primary/secondary register operands are reported in the iReg1 or iReg2
2094 * fields depending on whether it is a read/write form.
2095 */
2096 uint8_t idxReg1;
2097 uint8_t idxReg2;
2098 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2099 {
2100 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2101 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2102 }
2103 else
2104 {
2105 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2106 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2107 }
2108 ExitInstrInfo.All.u2Scaling = 0;
2109 ExitInstrInfo.All.iReg1 = idxReg1;
2110 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2111 ExitInstrInfo.All.fIsRegOperand = 1;
2112 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2113 ExitInstrInfo.All.iSegReg = 0;
2114 ExitInstrInfo.All.iIdxReg = 0;
2115 ExitInstrInfo.All.fIdxRegInvalid = 1;
2116 ExitInstrInfo.All.iBaseReg = 0;
2117 ExitInstrInfo.All.fBaseRegInvalid = 1;
2118 ExitInstrInfo.All.iReg2 = idxReg2;
2119
2120 /* Displacement not applicable for register addressing. */
2121 GCPtrDisp = 0;
2122 }
2123 else
2124 {
2125 /*
2126 * ModR/M indicates memory addressing.
2127 */
2128 uint8_t uScale = 0;
2129 bool fBaseRegValid = false;
2130 bool fIdxRegValid = false;
2131 uint8_t iBaseReg = 0;
2132 uint8_t iIdxReg = 0;
2133 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2134 {
2135 /*
2136 * Parse the ModR/M, displacement for 16-bit addressing mode.
2137 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2138 */
2139 uint16_t u16Disp = 0;
2140 uint8_t const offDisp = offModRm + sizeof(bRm);
2141 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2142 {
2143 /* Displacement without any registers. */
2144 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2145 }
2146 else
2147 {
2148 /* Register (index and base). */
2149 switch (bRm & X86_MODRM_RM_MASK)
2150 {
2151 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2152 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2153 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2154 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2155 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2156 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2157 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2158 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2159 }
2160
2161 /* Register + displacement. */
2162 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2163 {
2164 case 0: break;
2165 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2166 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2167 default:
2168 {
2169 /* Register addressing, handled at the beginning. */
2170 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2171 break;
2172 }
2173 }
2174 }
2175
2176 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2177 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2178 }
2179 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2180 {
2181 /*
2182 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2183 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2184 */
2185 uint32_t u32Disp = 0;
2186 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2187 {
2188 /* Displacement without any registers. */
2189 uint8_t const offDisp = offModRm + sizeof(bRm);
2190 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2191 }
2192 else
2193 {
2194 /* Register (and perhaps scale, index and base). */
2195 uint8_t offDisp = offModRm + sizeof(bRm);
2196 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2197 if (iBaseReg == 4)
2198 {
2199 /* An SIB byte follows the ModR/M byte, parse it. */
2200 uint8_t bSib;
2201 uint8_t const offSib = offModRm + sizeof(bRm);
2202 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2203
2204 /* A displacement may follow SIB, update its offset. */
2205 offDisp += sizeof(bSib);
2206
2207 /* Get the scale. */
2208 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2209
2210 /* Get the index register. */
2211 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2212 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2213
2214 /* Get the base register. */
2215 iBaseReg = bSib & X86_SIB_BASE_MASK;
2216 fBaseRegValid = true;
2217 if (iBaseReg == 5)
2218 {
2219 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2220 {
2221 /* Mod is 0 implies a 32-bit displacement with no base. */
2222 fBaseRegValid = false;
2223 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2224 }
2225 else
2226 {
2227 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2228 iBaseReg = X86_GREG_xBP;
2229 }
2230 }
2231 }
2232
2233 /* Register + displacement. */
2234 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2235 {
2236 case 0: /* Handled above */ break;
2237 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2238 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2239 default:
2240 {
2241 /* Register addressing, handled at the beginning. */
2242 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2243 break;
2244 }
2245 }
2246 }
2247
2248 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2249 }
2250 else
2251 {
2252 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2253
2254 /*
2255 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2256 * See Intel instruction spec. 2.2 "IA-32e Mode".
2257 */
2258 uint64_t u64Disp = 0;
2259 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2260 if (fRipRelativeAddr)
2261 {
2262 /*
2263 * RIP-relative addressing mode.
2264 *
2265 * The displacement is 32-bit signed implying an offset range of +/-2G.
2266 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2267 */
2268 uint8_t const offDisp = offModRm + sizeof(bRm);
2269 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2270 }
2271 else
2272 {
2273 uint8_t offDisp = offModRm + sizeof(bRm);
2274
2275 /*
2276 * Register (and perhaps scale, index and base).
2277 *
2278 * REX.B extends the most-significant bit of the base register. However, REX.B
2279 * is ignored while determining whether an SIB follows the opcode. Hence, we
2280 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2281 *
2282 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2283 */
2284 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2285 if (iBaseReg == 4)
2286 {
2287 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2288 uint8_t bSib;
2289 uint8_t const offSib = offModRm + sizeof(bRm);
2290 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2291
2292 /* Displacement may follow SIB, update its offset. */
2293 offDisp += sizeof(bSib);
2294
2295 /* Get the scale. */
2296 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2297
2298 /* Get the index. */
2299 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2300 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2301
2302 /* Get the base. */
2303 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2304 fBaseRegValid = true;
2305 if (iBaseReg == 5)
2306 {
2307 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2308 {
2309 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2310 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2311 }
2312 else
2313 {
2314 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2315 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2316 }
2317 }
2318 }
2319 iBaseReg |= pVCpu->iem.s.uRexB;
2320
2321 /* Register + displacement. */
2322 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2323 {
2324 case 0: /* Handled above */ break;
2325 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2326 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2327 default:
2328 {
2329 /* Register addressing, handled at the beginning. */
2330 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2331 break;
2332 }
2333 }
2334 }
2335
2336 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2337 }
2338
2339 /*
2340 * The primary or secondary register operand is reported in iReg2 depending
2341 * on whether the primary operand is in read/write form.
2342 */
2343 uint8_t idxReg2;
2344 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2345 {
2346 idxReg2 = bRm & X86_MODRM_RM_MASK;
2347 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2348 idxReg2 |= pVCpu->iem.s.uRexB;
2349 }
2350 else
2351 {
2352 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2353 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2354 idxReg2 |= pVCpu->iem.s.uRexReg;
2355 }
2356 ExitInstrInfo.All.u2Scaling = uScale;
2357 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2358 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2359 ExitInstrInfo.All.fIsRegOperand = 0;
2360 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2361 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2362 ExitInstrInfo.All.iIdxReg = iIdxReg;
2363 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2364 ExitInstrInfo.All.iBaseReg = iBaseReg;
2365 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2366 ExitInstrInfo.All.iReg2 = idxReg2;
2367 }
2368
2369 /*
2370 * Handle exceptions to the norm for certain instructions.
2371 * (e.g. some instructions convey an instruction identity in place of iReg2).
2372 */
2373 switch (uExitReason)
2374 {
2375 case VMX_EXIT_GDTR_IDTR_ACCESS:
2376 {
2377 Assert(VMXINSTRID_IS_VALID(uInstrId));
2378 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2379 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2380 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2381 break;
2382 }
2383
2384 case VMX_EXIT_LDTR_TR_ACCESS:
2385 {
2386 Assert(VMXINSTRID_IS_VALID(uInstrId));
2387 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2388 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2389 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2390 break;
2391 }
2392
2393 case VMX_EXIT_RDRAND:
2394 case VMX_EXIT_RDSEED:
2395 {
2396 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2397 break;
2398 }
2399 }
2400
2401 /* Update displacement and return the constructed VM-exit instruction information field. */
2402 if (pGCPtrDisp)
2403 *pGCPtrDisp = GCPtrDisp;
2404
2405 return ExitInstrInfo.u;
2406}
2407
2408
2409/**
2410 * VMX VM-exit handler.
2411 *
2412 * @returns Strict VBox status code.
2413 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2414 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2415 * triple-fault.
2416 *
2417 * @param pVCpu The cross context virtual CPU structure.
2418 * @param uExitReason The VM-exit reason.
2419 * @param u64ExitQual The Exit qualification.
2420 *
2421 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2422 * called. Failures during VM-entry can cause VM-exits as well, so we
2423 * -cannot- assert we're in VMX non-root mode here.
2424 */
2425VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2426{
2427# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2428 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2429 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2430 return VERR_IEM_IPE_7;
2431# else
2432 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2433
2434 /* Just count this as an exit and be done with that. */
2435 pVCpu->iem.s.cPotentialExits++;
2436
2437 /*
2438 * Import all the guest-CPU state.
2439 *
2440 * HM on returning to guest execution would have to reset up a whole lot of state
2441 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2442 * the state and flag reloading the entire state on re-entry. So import the entire
2443 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2444 */
2445 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2446
2447 /*
2448 * Ensure VM-entry interruption information valid bit is cleared.
2449 *
2450 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2451 * by invalid-guest state or machine-check exceptions) also clear this bit.
2452 *
2453 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2454 */
2455 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2456 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2457
2458 /*
2459 * Update the VM-exit reason and Exit qualification.
2460 * Other VMCS read-only data fields are expected to be updated by the caller already.
2461 */
2462 pVmcs->u32RoExitReason = uExitReason;
2463 pVmcs->u64RoExitQual.u = u64ExitQual;
2464
2465 Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2466 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2467 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u32));
2468
2469 /*
2470 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2471 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2472 */
2473 {
2474 uint8_t uVector;
2475 uint32_t fFlags;
2476 uint32_t uErrCode;
2477 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2478 if (fInEventDelivery)
2479 {
2480 /*
2481 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2482 * caused by a triple-fault or the original event results in a double-fault that
2483 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2484 * original event information into the IDT-vectoring information fields.
2485 *
2486 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2487 */
2488 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2489 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2490 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2491 {
2492 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2493 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2494 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2495 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2496 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2497 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2498 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2499 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2500 Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2501 pVCpu->cpum.GstCtx.cr2));
2502 }
2503 }
2504 }
2505
2506 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2507 Assert(pVmcs->u64RoIoRcx.u == 0);
2508 Assert(pVmcs->u64RoIoRsi.u == 0);
2509 Assert(pVmcs->u64RoIoRdi.u == 0);
2510 Assert(pVmcs->u64RoIoRip.u == 0);
2511
2512 /*
2513 * Save the guest state back into the VMCS.
2514 * We only need to save the state when the VM-entry was successful.
2515 */
2516 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2517 if (!fVmentryFailed)
2518 {
2519 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2520 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2521 {
2522 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2523 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2524 }
2525
2526 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2527 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2528
2529 /*
2530 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2531 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2532 *
2533 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2534 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2535 * as guest-CPU state would not been modified. Hence for now, we do this only when
2536 * the VM-entry succeeded.
2537 */
2538 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2539 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2540 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2541 {
2542 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2543 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2544 else
2545 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2546 }
2547
2548 /*
2549 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2550 * occurs in enclave mode/SMM which we don't support yet.
2551 *
2552 * If we ever add support for it, we can pass just the lower bits to the functions
2553 * below, till then an assert should suffice.
2554 */
2555 Assert(!RT_HI_U16(uExitReason));
2556
2557 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2558 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2559 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2560 if (RT_SUCCESS(rc))
2561 { /* likely */ }
2562 else
2563 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2564
2565 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2566 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2567 }
2568 else
2569 {
2570 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2571 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2572 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2573 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2574 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2575 }
2576
2577 /*
2578 * Stop any running VMX-preemption timer if necessary.
2579 */
2580 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2581 CPUMStopGuestVmxPremptTimer(pVCpu);
2582
2583 /*
2584 * Clear any pending VMX nested-guest force-flags.
2585 * These force-flags have no effect on (outer) guest execution and will
2586 * be re-evaluated and setup on the next nested-guest VM-entry.
2587 */
2588 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2589
2590 /*
2591 * We're no longer in nested-guest execution mode.
2592 *
2593 * It is important to do this prior to loading the host state because
2594 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2595 * second-level address translation while switching to host CR3.
2596 */
2597 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2598
2599 /* Restore the host (outer guest) state. */
2600 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2601 if (RT_SUCCESS(rcStrict))
2602 {
2603 Assert(rcStrict == VINF_SUCCESS);
2604 rcStrict = VINF_VMX_VMEXIT;
2605 }
2606 else
2607 Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2608
2609 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2610 {
2611 /* Notify HM that the current VMCS fields have been modified. */
2612 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2613
2614 /* Notify HM that we've completed the VM-exit. */
2615 HMNotifyVmxNstGstVmexit(pVCpu);
2616 }
2617
2618# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2619 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2620 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2621 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2622 if (rcSched != VINF_SUCCESS)
2623 iemSetPassUpStatus(pVCpu, rcSched);
2624# endif
2625 return rcStrict;
2626# endif
2627}
2628
2629
2630/**
2631 * VMX VM-exit handler for VM-exits due to instruction execution.
2632 *
2633 * This is intended for instructions where the caller provides all the relevant
2634 * VM-exit information.
2635 *
2636 * @returns Strict VBox status code.
2637 * @param pVCpu The cross context virtual CPU structure.
2638 * @param pExitInfo Pointer to the VM-exit information.
2639 */
2640static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2641{
2642 /*
2643 * For instructions where any of the following fields are not applicable:
2644 * - Exit qualification must be cleared.
2645 * - VM-exit instruction info. is undefined.
2646 * - Guest-linear address is undefined.
2647 * - Guest-physical address is undefined.
2648 *
2649 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2650 * instruction execution. For VM-exits that are not due to instruction execution this
2651 * field is undefined.
2652 *
2653 * In our implementation in IEM, all undefined fields are generally cleared. However,
2654 * if the caller supplies information (from say the physical CPU directly) it is
2655 * then possible that the undefined fields are not cleared.
2656 *
2657 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2658 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2659 */
2660 Assert(pExitInfo);
2661 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2662 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2663 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2664
2665 /* Update all the relevant fields from the VM-exit instruction information struct. */
2666 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2667 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2668 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2669 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2670
2671 /* Perform the VM-exit. */
2672 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2673}
2674
2675
2676/**
2677 * VMX VM-exit handler for VM-exits due to instruction execution.
2678 *
2679 * This is intended for instructions that only provide the VM-exit instruction
2680 * length.
2681 *
2682 * @param pVCpu The cross context virtual CPU structure.
2683 * @param uExitReason The VM-exit reason.
2684 * @param cbInstr The instruction length in bytes.
2685 */
2686VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2687{
2688#ifdef VBOX_STRICT
2689 /*
2690 * To prevent us from shooting ourselves in the foot.
2691 * The follow instructions should convey more than just the instruction length.
2692 */
2693 switch (uExitReason)
2694 {
2695 case VMX_EXIT_INVEPT:
2696 case VMX_EXIT_INVPCID:
2697 case VMX_EXIT_INVVPID:
2698 case VMX_EXIT_LDTR_TR_ACCESS:
2699 case VMX_EXIT_GDTR_IDTR_ACCESS:
2700 case VMX_EXIT_VMCLEAR:
2701 case VMX_EXIT_VMPTRLD:
2702 case VMX_EXIT_VMPTRST:
2703 case VMX_EXIT_VMREAD:
2704 case VMX_EXIT_VMWRITE:
2705 case VMX_EXIT_VMXON:
2706 case VMX_EXIT_XRSTORS:
2707 case VMX_EXIT_XSAVES:
2708 case VMX_EXIT_RDRAND:
2709 case VMX_EXIT_RDSEED:
2710 case VMX_EXIT_IO_INSTR:
2711 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2712 break;
2713 }
2714#endif
2715
2716 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_INSTR_LEN(uExitReason, cbInstr);
2717 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2718}
2719
2720
2721/**
2722 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2723 *
2724 * @returns Strict VBox status code.
2725 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2726 * @thread EMT(pVCpu)
2727 */
2728VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2729{
2730 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2731 Assert(!pVCpu->iem.s.cActiveMappings);
2732 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2733}
2734
2735
2736/**
2737 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2738 *
2739 * @returns Strict VBox status code.
2740 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2741 * @param uVector The SIPI vector.
2742 * @thread EMT(pVCpu)
2743 */
2744VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2745{
2746 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2747 Assert(!pVCpu->iem.s.cActiveMappings);
2748 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2749}
2750
2751
2752/**
2753 * Interface for HM and EM to emulate a VM-exit.
2754 *
2755 * If a specialized version of a VM-exit handler exists, that must be used instead.
2756 *
2757 * @returns Strict VBox status code.
2758 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2759 * @param uExitReason The VM-exit reason.
2760 * @param u64ExitQual The Exit qualification.
2761 * @thread EMT(pVCpu)
2762 */
2763VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2764{
2765 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2766 Assert(!pVCpu->iem.s.cActiveMappings);
2767 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2768}
2769
2770
2771/**
2772 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2773 *
2774 * This is meant to be used for those instructions that VMX provides additional
2775 * decoding information beyond just the instruction length!
2776 *
2777 * @returns Strict VBox status code.
2778 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2779 * @param pExitInfo Pointer to the VM-exit information.
2780 * @thread EMT(pVCpu)
2781 */
2782VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2783{
2784 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2785 Assert(!pVCpu->iem.s.cActiveMappings);
2786 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2787}
2788
2789
2790/**
2791 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2792 *
2793 * This is meant to be used for those instructions that VMX provides only the
2794 * instruction length.
2795 *
2796 * @returns Strict VBox status code.
2797 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2798 * @param pExitInfo Pointer to the VM-exit information.
2799 * @param cbInstr The instruction length in bytes.
2800 * @thread EMT(pVCpu)
2801 */
2802VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2803{
2804 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2805 Assert(!pVCpu->iem.s.cActiveMappings);
2806 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2807}
2808
2809
2810/**
2811 * VMX VM-exit handler for VM-exits due to instruction execution.
2812 *
2813 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2814 * instruction information and Exit qualification fields.
2815 *
2816 * @param pVCpu The cross context virtual CPU structure.
2817 * @param uExitReason The VM-exit reason.
2818 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2819 * @param cbInstr The instruction length in bytes.
2820 *
2821 * @remarks Do not use this for INS/OUTS instruction.
2822 */
2823VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2824{
2825#ifdef VBOX_STRICT
2826 /*
2827 * To prevent us from shooting ourselves in the foot.
2828 * The follow instructions convey specific info that require using their respective handlers.
2829 */
2830 switch (uExitReason)
2831 {
2832 case VMX_EXIT_INVEPT:
2833 case VMX_EXIT_INVPCID:
2834 case VMX_EXIT_INVVPID:
2835 case VMX_EXIT_LDTR_TR_ACCESS:
2836 case VMX_EXIT_GDTR_IDTR_ACCESS:
2837 case VMX_EXIT_VMCLEAR:
2838 case VMX_EXIT_VMPTRLD:
2839 case VMX_EXIT_VMPTRST:
2840 case VMX_EXIT_VMREAD:
2841 case VMX_EXIT_VMWRITE:
2842 case VMX_EXIT_VMXON:
2843 case VMX_EXIT_XRSTORS:
2844 case VMX_EXIT_XSAVES:
2845 case VMX_EXIT_RDRAND:
2846 case VMX_EXIT_RDSEED:
2847 break;
2848 default:
2849 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2850 break;
2851 }
2852#endif
2853
2854 /*
2855 * Update the Exit qualification field with displacement bytes.
2856 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2857 */
2858 /* Construct the VM-exit instruction information. */
2859 RTGCPTR GCPtrDisp;
2860 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2861
2862 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(uExitReason, GCPtrDisp, uInstrInfo, cbInstr);
2863 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2864}
2865
2866
2867/**
2868 * VMX VM-exit handler for VM-exits due to INVLPG.
2869 *
2870 * @returns Strict VBox status code.
2871 * @param pVCpu The cross context virtual CPU structure.
2872 * @param GCPtrPage The guest-linear address of the page being invalidated.
2873 * @param cbInstr The instruction length in bytes.
2874 */
2875VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2876{
2877 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_INVLPG, GCPtrPage, cbInstr);
2878 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2879 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2880}
2881
2882
2883/**
2884 * VMX VM-exit handler for VM-exits due to LMSW.
2885 *
2886 * @returns Strict VBox status code.
2887 * @param pVCpu The cross context virtual CPU structure.
2888 * @param uGuestCr0 The current guest CR0.
2889 * @param pu16NewMsw The machine-status word specified in LMSW's source
2890 * operand. This will be updated depending on the VMX
2891 * guest/host CR0 mask if LMSW is not intercepted.
2892 * @param GCPtrEffDst The guest-linear address of the source operand in case
2893 * of a memory operand. For register operand, pass
2894 * NIL_RTGCPTR.
2895 * @param cbInstr The instruction length in bytes.
2896 */
2897VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2898 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2899{
2900 Assert(pu16NewMsw);
2901
2902 uint16_t const uNewMsw = *pu16NewMsw;
2903 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2904 {
2905 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2906 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2907 VMXVEXITINFO ExitInfo
2908 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2909 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2910 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2911 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw)
2912 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW),
2913 cbInstr);
2914 if (fMemOperand)
2915 {
2916 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2917 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2918 }
2919 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2920 }
2921
2922 /*
2923 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2924 * CR0 guest/host mask must be left unmodified.
2925 *
2926 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2927 */
2928 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2929 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2930 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2931
2932 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2933}
2934
2935
2936/**
2937 * VMX VM-exit handler for VM-exits due to CLTS.
2938 *
2939 * @returns Strict VBox status code.
2940 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2941 * VM-exit but must not modify the guest CR0.TS bit.
2942 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2943 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2944 * CR0 fixed bits in VMX operation).
2945 * @param pVCpu The cross context virtual CPU structure.
2946 * @param cbInstr The instruction length in bytes.
2947 */
2948VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2949{
2950 /*
2951 * If CR0.TS is owned by the host:
2952 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2953 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2954 * CLTS instruction completes without clearing CR0.TS.
2955 *
2956 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2957 */
2958 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2959 if (fGstHostMask & X86_CR0_TS)
2960 {
2961 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u & X86_CR0_TS)
2962 {
2963 Log2(("clts: Guest intercept -> VM-exit\n"));
2964 VMXVEXITINFO const ExitInfo
2965 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2966 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2967 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
2968 VMX_EXIT_QUAL_CRX_ACCESS_CLTS),
2969 cbInstr);
2970 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2971 }
2972 return VINF_VMX_MODIFIES_BEHAVIOR;
2973 }
2974
2975 /*
2976 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2977 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2978 */
2979 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2980}
2981
2982
2983/**
2984 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2985 * (CR0/CR4 write).
2986 *
2987 * @returns Strict VBox status code.
2988 * @param pVCpu The cross context virtual CPU structure.
2989 * @param iCrReg The control register (either CR0 or CR4).
2990 * @param uGuestCrX The current guest CR0/CR4.
2991 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2992 * VM-exit is caused.
2993 * @param iGReg The general register from which the CR0/CR4 value is being
2994 * loaded.
2995 * @param cbInstr The instruction length in bytes.
2996 */
2997VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
2998 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
2999{
3000 Assert(puNewCrX);
3001 Assert(iCrReg == 0 || iCrReg == 4);
3002 Assert(iGReg < X86_GREG_COUNT);
3003
3004 uint64_t const uNewCrX = *puNewCrX;
3005 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3006 {
3007 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3008 VMXVEXITINFO const ExitInfo
3009 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3010 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3011 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3012 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3013 cbInstr);
3014 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3015 }
3016
3017 /*
3018 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3019 * must not be modified the instruction.
3020 *
3021 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3022 */
3023 uint64_t uGuestCrX;
3024 uint64_t fGstHostMask;
3025 if (iCrReg == 0)
3026 {
3027 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3028 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3029 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3030 }
3031 else
3032 {
3033 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3034 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3035 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3036 }
3037
3038 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3039 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3040}
3041
3042
3043/**
3044 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3045 *
3046 * @returns VBox strict status code.
3047 * @param pVCpu The cross context virtual CPU structure.
3048 * @param iGReg The general register to which the CR3 value is being stored.
3049 * @param cbInstr The instruction length in bytes.
3050 */
3051VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3052{
3053 Assert(iGReg < X86_GREG_COUNT);
3054 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3055
3056 /*
3057 * If the CR3-store exiting control is set, we must cause a VM-exit.
3058 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3059 */
3060 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3061 {
3062 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3063 VMXVEXITINFO const ExitInfo
3064 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3065 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3066 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3067 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3068 cbInstr);
3069 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3070 }
3071 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3072}
3073
3074
3075/**
3076 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3077 *
3078 * @returns VBox strict status code.
3079 * @param pVCpu The cross context virtual CPU structure.
3080 * @param uNewCr3 The new CR3 value.
3081 * @param iGReg The general register from which the CR3 value is being
3082 * loaded.
3083 * @param cbInstr The instruction length in bytes.
3084 */
3085VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3086{
3087 Assert(iGReg < X86_GREG_COUNT);
3088
3089 /*
3090 * If the CR3-load exiting control is set and the new CR3 value does not
3091 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3092 *
3093 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3094 */
3095 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3096 {
3097 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3098 VMXVEXITINFO const ExitInfo
3099 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3100 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3101 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3102 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3103 VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3104 cbInstr);
3105 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3106 }
3107 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3108}
3109
3110
3111/**
3112 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3113 *
3114 * @returns VBox strict status code.
3115 * @param pVCpu The cross context virtual CPU structure.
3116 * @param iGReg The general register to which the CR8 value is being stored.
3117 * @param cbInstr The instruction length in bytes.
3118 */
3119VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3120{
3121 Assert(iGReg < X86_GREG_COUNT);
3122
3123 /*
3124 * If the CR8-store exiting control is set, we must cause a VM-exit.
3125 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3126 */
3127 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3128 {
3129 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3130 VMXVEXITINFO const ExitInfo
3131 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3132 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3133 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3134 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3135 cbInstr);
3136 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3137 }
3138 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3139}
3140
3141
3142/**
3143 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3144 *
3145 * @returns VBox strict status code.
3146 * @param pVCpu The cross context virtual CPU structure.
3147 * @param iGReg The general register from which the CR8 value is being
3148 * loaded.
3149 * @param cbInstr The instruction length in bytes.
3150 */
3151VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3152{
3153 Assert(iGReg < X86_GREG_COUNT);
3154
3155 /*
3156 * If the CR8-load exiting control is set, we must cause a VM-exit.
3157 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3158 */
3159 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3160 {
3161 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3162 VMXVEXITINFO const ExitInfo
3163 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3164 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3165 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3166 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3167 cbInstr);
3168 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3169 }
3170 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3171}
3172
3173
3174/**
3175 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3176 * GReg,DRx' (DRx read).
3177 *
3178 * @returns VBox strict status code.
3179 * @param pVCpu The cross context virtual CPU structure.
3180 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3181 * VMXINSTRID_MOV_FROM_DRX).
3182 * @param iDrReg The debug register being accessed.
3183 * @param iGReg The general register to/from which the DRx value is being
3184 * store/loaded.
3185 * @param cbInstr The instruction length in bytes.
3186 */
3187VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3188 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3189{
3190 Assert(iDrReg <= 7);
3191 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3192 Assert(iGReg < X86_GREG_COUNT);
3193
3194 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3195 {
3196 VMXVEXITINFO const ExitInfo
3197 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_DRX,
3198 RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3199 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg)
3200 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION,
3201 uInstrId == VMXINSTRID_MOV_TO_DRX
3202 ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3203 : VMX_EXIT_QUAL_DRX_DIRECTION_READ),
3204 cbInstr);
3205 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3206 }
3207
3208 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3209}
3210
3211
3212/**
3213 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3214 *
3215 * @returns VBox strict status code.
3216 * @param pVCpu The cross context virtual CPU structure.
3217 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3218 * VMXINSTRID_IO_OUT).
3219 * @param u16Port The I/O port being accessed.
3220 * @param fImm Whether the I/O port was encoded using an immediate operand
3221 * or the implicit DX register.
3222 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3223 * @param cbInstr The instruction length in bytes.
3224 */
3225VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3226 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3227{
3228 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3229 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3230
3231 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3232 {
3233 VMXVEXITINFO const ExitInfo
3234 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_IO_INSTR,
3235 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3236 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3237 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port)
3238 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION,
3239 uInstrId == VMXINSTRID_IO_IN
3240 ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3241 : VMX_EXIT_QUAL_IO_DIRECTION_OUT),
3242 cbInstr);
3243 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3244 }
3245 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3246}
3247
3248
3249/**
3250 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3251 *
3252 * @returns VBox strict status code.
3253 * @param pVCpu The cross context virtual CPU structure.
3254 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3255 * VMXINSTRID_IO_OUTS).
3256 * @param u16Port The I/O port being accessed.
3257 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3258 * @param fRep Whether the instruction has a REP prefix or not.
3259 * @param ExitInstrInfo The VM-exit instruction info. field.
3260 * @param cbInstr The instruction length in bytes.
3261 */
3262VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3263 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3264{
3265 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3266 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3267 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3268 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3269 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3270
3271 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3272 {
3273 /*
3274 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3275 */
3276 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3277 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3278 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3279 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3280 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3281
3282 uint32_t uDirection;
3283 uint64_t uGuestLinearAddr;
3284 if (uInstrId == VMXINSTRID_IO_INS)
3285 {
3286 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3287 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3288 }
3289 else
3290 {
3291 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3292 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3293 }
3294
3295 /*
3296 * If the segment is unusable, the guest-linear address in undefined.
3297 * We shall clear it for consistency.
3298 *
3299 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3300 */
3301 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3302 uGuestLinearAddr = 0;
3303
3304 VMXVEXITINFO const ExitInfo
3305 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(VMX_EXIT_IO_INSTR,
3306 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3307 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3308 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3309 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3310 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING,
3311 VMX_EXIT_QUAL_IO_ENCODING_DX)
3312 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port),
3313 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo
3314 ? ExitInstrInfo.u : 0,
3315 cbInstr,
3316 uGuestLinearAddr);
3317 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3318 }
3319
3320 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3321}
3322
3323
3324/**
3325 * VMX VM-exit handler for VM-exits due to MWAIT.
3326 *
3327 * @returns VBox strict status code.
3328 * @param pVCpu The cross context virtual CPU structure.
3329 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3330 * @param cbInstr The instruction length in bytes.
3331 */
3332VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3333{
3334 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MWAIT, fMonitorHwArmed, cbInstr);
3335 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3336}
3337
3338
3339/**
3340 * VMX VM-exit handler for VM-exits due to PAUSE.
3341 *
3342 * @returns VBox strict status code.
3343 * @param pVCpu The cross context virtual CPU structure.
3344 * @param cbInstr The instruction length in bytes.
3345 */
3346static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3347{
3348 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3349
3350 /*
3351 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3352 * "PAUSE-loop exiting" control.
3353 *
3354 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3355 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3356 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3357 * a VM-exit.
3358 *
3359 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3360 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3361 */
3362 bool fIntercept = false;
3363 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3364 fIntercept = true;
3365 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3366 && pVCpu->iem.s.uCpl == 0)
3367 {
3368 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3369
3370 /*
3371 * A previous-PAUSE-tick value of 0 is used to identify the first time
3372 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3373 * consider this to be the first execution of PAUSE in a loop according
3374 * to the Intel.
3375 *
3376 * All subsequent records for the previous-PAUSE-tick we ensure that it
3377 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3378 */
3379 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3380 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3381 uint64_t const uTick = TMCpuTickGet(pVCpu);
3382 uint32_t const uPleGap = pVmcs->u32PleGap;
3383 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3384 if ( *puPrevPauseTick == 0
3385 || uTick - *puPrevPauseTick > uPleGap)
3386 *puFirstPauseLoopTick = uTick;
3387 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3388 fIntercept = true;
3389
3390 *puPrevPauseTick = uTick | 1;
3391 }
3392
3393 if (fIntercept)
3394 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3395
3396 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3397}
3398
3399
3400/**
3401 * VMX VM-exit handler for VM-exits due to task switches.
3402 *
3403 * @returns VBox strict status code.
3404 * @param pVCpu The cross context virtual CPU structure.
3405 * @param enmTaskSwitch The cause of the task switch.
3406 * @param SelNewTss The selector of the new TSS.
3407 * @param cbInstr The instruction length in bytes.
3408 */
3409VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3410{
3411 /*
3412 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3413 *
3414 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3415 * instruction or delivery of the exception generated by one of these instructions
3416 * lead to a task switch through a task gate in the IDT, we need to provide the
3417 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3418 * leaves the VM-exit instruction length field undefined.
3419 *
3420 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3421 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3422 */
3423 Assert(cbInstr <= 15);
3424
3425 uint8_t uType;
3426 switch (enmTaskSwitch)
3427 {
3428 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3429 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3430 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3431 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3432 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3433 }
3434
3435 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3436 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3437 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3438 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3439}
3440
3441
3442/**
3443 * VMX VM-exit handler for trap-like VM-exits.
3444 *
3445 * @returns VBox strict status code.
3446 * @param pVCpu The cross context virtual CPU structure.
3447 * @param pExitInfo Pointer to the VM-exit information.
3448 * @param pExitEventInfo Pointer to the VM-exit event information.
3449 */
3450static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3451{
3452 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3453 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3454 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3455}
3456
3457
3458/**
3459 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3460 * Virtualized-EOI, TPR-below threshold).
3461 *
3462 * @returns Strict VBox status code.
3463 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3464 * @param pExitInfo Pointer to the VM-exit information.
3465 * @thread EMT(pVCpu)
3466 */
3467VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3468{
3469 Assert(pExitInfo);
3470 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3471 Assert(!pVCpu->iem.s.cActiveMappings);
3472 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3473}
3474
3475
3476/**
3477 * VMX VM-exit handler for VM-exits due to task switches.
3478 *
3479 * This is intended for task switches where the caller provides all the relevant
3480 * VM-exit information.
3481 *
3482 * @returns VBox strict status code.
3483 * @param pVCpu The cross context virtual CPU structure.
3484 * @param pExitInfo Pointer to the VM-exit information.
3485 * @param pExitEventInfo Pointer to the VM-exit event information.
3486 */
3487static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3488 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3489{
3490 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3491 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3492 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3493 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3494 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3495}
3496
3497
3498/**
3499 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3500 *
3501 * @returns Strict VBox status code.
3502 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3503 * @param pExitInfo Pointer to the VM-exit information.
3504 * @param pExitEventInfo Pointer to the VM-exit event information.
3505 * @thread EMT(pVCpu)
3506 */
3507VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3508{
3509 Assert(pExitInfo);
3510 Assert(pExitEventInfo);
3511 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3512 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3513 Assert(!pVCpu->iem.s.cActiveMappings);
3514 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3515}
3516
3517
3518/**
3519 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3520 *
3521 * @returns VBox strict status code.
3522 * @param pVCpu The cross context virtual CPU structure.
3523 */
3524VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3525{
3526 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3527 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3528
3529 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3530 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3531
3532 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3533 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3534 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3535
3536 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3537 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3538}
3539
3540
3541/**
3542 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3543 *
3544 * @returns Strict VBox status code.
3545 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3546 * @thread EMT(pVCpu)
3547 */
3548VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3549{
3550 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3551 Assert(!pVCpu->iem.s.cActiveMappings);
3552 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3553}
3554
3555
3556/**
3557 * VMX VM-exit handler for VM-exits due to external interrupts.
3558 *
3559 * @returns VBox strict status code.
3560 * @param pVCpu The cross context virtual CPU structure.
3561 * @param uVector The external interrupt vector (pass 0 if the interrupt
3562 * is still pending since we typically won't know the
3563 * vector).
3564 * @param fIntPending Whether the external interrupt is pending or
3565 * acknowledged in the interrupt controller.
3566 */
3567static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3568{
3569 Assert(!fIntPending || uVector == 0);
3570
3571 /* The VM-exit is subject to "External interrupt exiting" being set. */
3572 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3573 {
3574 if (fIntPending)
3575 {
3576 /*
3577 * If the interrupt is pending and we don't need to acknowledge the
3578 * interrupt on VM-exit, cause the VM-exit immediately.
3579 *
3580 * See Intel spec 25.2 "Other Causes Of VM Exits".
3581 */
3582 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3583 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3584
3585 /*
3586 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3587 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3588 * acknowledged that the interrupt has been consumed. Callers would have to call
3589 * us again after getting the vector (and ofc, with fIntPending with false).
3590 */
3591 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3592 }
3593
3594 /*
3595 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3596 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3597 * all set, we need to record the vector of the external interrupt in the
3598 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3599 *
3600 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3601 */
3602 uint32_t uExitIntInfo;
3603 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3604 {
3605 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3606 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3607 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3608 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3609 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3610 }
3611 else
3612 uExitIntInfo = 0;
3613 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3614
3615 /*
3616 * Cause the VM-exit whether or not the vector has been stored
3617 * in the VM-exit interruption-information field.
3618 */
3619 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3620 }
3621
3622 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3623}
3624
3625
3626/**
3627 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3628 *
3629 * @returns Strict VBox status code.
3630 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3631 * @param uVector The external interrupt vector (pass 0 if the external
3632 * interrupt is still pending).
3633 * @param fIntPending Whether the external interrupt is pending or
3634 * acknowdledged in the interrupt controller.
3635 * @thread EMT(pVCpu)
3636 */
3637VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3638{
3639 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3640 Assert(!pVCpu->iem.s.cActiveMappings);
3641 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3642}
3643
3644
3645/**
3646 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3647 * an event.
3648 *
3649 * @returns VBox strict status code.
3650 * @param pVCpu The cross context virtual CPU structure.
3651 */
3652VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3653{
3654 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3655 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3656 {
3657 /*
3658 * The NMI-unblocking due to IRET field need not be set for double faults.
3659 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3660 */
3661 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3662 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3663 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3664 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3665 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3666 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3667 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3668 }
3669
3670 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3671}
3672
3673
3674/**
3675 * VMX VM-exit handler for VM-exit due to delivery of an events.
3676 *
3677 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3678 * all the relevant VM-exit information.
3679 *
3680 * @returns VBox strict status code.
3681 * @param pVCpu The cross context virtual CPU structure.
3682 * @param pExitInfo Pointer to the VM-exit information.
3683 * @param pExitEventInfo Pointer to the VM-exit event information.
3684 */
3685static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3686{
3687 Assert(pExitInfo);
3688 Assert(pExitEventInfo);
3689 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3690 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3691
3692 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3693 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3694 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3695 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3696 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3697 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3698}
3699
3700
3701/**
3702 * Interface for HM and EM to emulate VM-exit due to NMIs.
3703 *
3704 * @returns Strict VBox status code.
3705 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3706 * @thread EMT(pVCpu)
3707 */
3708VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3709{
3710 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_ONLY_REASON(VMX_EXIT_XCPT_OR_NMI);
3711 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_INT( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3712 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE,
3713 VMX_EXIT_INT_INFO_TYPE_NMI)
3714 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR,
3715 X86_XCPT_NMI),
3716 0);
3717 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3718 Assert(!pVCpu->iem.s.cActiveMappings);
3719 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3720}
3721
3722
3723/**
3724 * Interface for HM and EM to emulate VM-exit due to exceptions.
3725 *
3726 * Exception includes NMIs, software exceptions (those generated by INT3 or
3727 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3728 *
3729 * @returns Strict VBox status code.
3730 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3731 * @param pExitInfo Pointer to the VM-exit information.
3732 * @param pExitEventInfo Pointer to the VM-exit event information.
3733 * @thread EMT(pVCpu)
3734 */
3735VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3736{
3737 Assert(pExitInfo);
3738 Assert(pExitEventInfo);
3739 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3740 Assert(!pVCpu->iem.s.cActiveMappings);
3741 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3742}
3743
3744
3745/**
3746 * VMX VM-exit handler for VM-exits due to delivery of an event.
3747 *
3748 * @returns VBox strict status code.
3749 * @param pVCpu The cross context virtual CPU structure.
3750 * @param uVector The interrupt / exception vector.
3751 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3752 * @param uErrCode The error code associated with the event.
3753 * @param uCr2 The CR2 value in case of a \#PF exception.
3754 * @param cbInstr The instruction length in bytes.
3755 */
3756VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3757 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3758{
3759 /*
3760 * If the event is being injected as part of VM-entry, it is -not- subject to event
3761 * intercepts in the nested-guest. However, secondary exceptions that occur during
3762 * injection of any event -are- subject to event interception.
3763 *
3764 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3765 */
3766 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3767 {
3768 /*
3769 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3770 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3771 *
3772 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3773 */
3774 if ( uVector == X86_XCPT_NMI
3775 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3776 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3777 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3778 else
3779 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3780
3781 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3782 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3783 }
3784
3785 /*
3786 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3787 * If not, the caller will continue delivery of the external interrupt as it would
3788 * normally. The interrupt is no longer pending in the interrupt controller at this
3789 * point.
3790 */
3791 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3792 {
3793 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3794 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3795 }
3796
3797 /*
3798 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3799 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3800 * interrupts.
3801 */
3802 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3803 bool fIntercept;
3804 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3805 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3806 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3807 else
3808 {
3809 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3810 fIntercept = false;
3811 }
3812
3813 /*
3814 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3815 * relevant VM-exit information and cause the VM-exit.
3816 */
3817 if (fIntercept)
3818 {
3819 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3820
3821 /* Construct the rest of the event related information fields and cause the VM-exit. */
3822 uint64_t u64ExitQual;
3823 if (uVector == X86_XCPT_PF)
3824 {
3825 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3826 u64ExitQual = uCr2;
3827 }
3828 else if (uVector == X86_XCPT_DB)
3829 {
3830 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3831 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3832 }
3833 else
3834 u64ExitQual = 0;
3835
3836 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3837 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3838 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3839 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3840 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3841 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3842 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3843 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3844 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3845 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3846
3847 /*
3848 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3849 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3850 * length.
3851 */
3852 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3853 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3854 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3855 else
3856 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3857
3858 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3859 }
3860
3861 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3862}
3863
3864
3865/**
3866 * VMX VM-exit handler for EPT misconfiguration.
3867 *
3868 * @param pVCpu The cross context virtual CPU structure.
3869 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3870 * This need not be page aligned (e.g. nested-guest in real
3871 * mode).
3872 */
3873static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3874{
3875 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3876 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3877}
3878
3879
3880/**
3881 * VMX VM-exit handler for EPT misconfiguration.
3882 *
3883 * This is intended for EPT misconfigurations where the caller provides all the
3884 * relevant VM-exit information.
3885 *
3886 * @param pVCpu The cross context virtual CPU structure.
3887 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3888 * This need not be page aligned (e.g. nested-guest in real
3889 * mode).
3890 * @param pExitEventInfo Pointer to the VM-exit event information.
3891 */
3892static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3893{
3894 Assert(pExitEventInfo);
3895 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3896 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3897 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3898 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3899 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3900}
3901
3902
3903/**
3904 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3905 *
3906 * @returns Strict VBox status code.
3907 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3908 * @param GCPhysAddr The nested-guest physical address causing the EPT
3909 * misconfiguration.
3910 * @param pExitEventInfo Pointer to the VM-exit event information.
3911 * @thread EMT(pVCpu)
3912 */
3913VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3914{
3915 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3916
3917 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3918 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3919 Assert(!pVCpu->iem.s.cActiveMappings);
3920 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3921}
3922
3923
3924/**
3925 * VMX VM-exit handler for EPT violation.
3926 *
3927 * @param pVCpu The cross context virtual CPU structure.
3928 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3929 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3930 * @param fEptAccess The EPT paging structure bits.
3931 * @param GCPhysAddr The physical address causing the EPT violation. This
3932 * need not be page aligned (e.g. nested-guest in real
3933 * mode).
3934 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3935 * EPT violation. If @c false, GCPtrAddr must be 0.
3936 * @param GCPtrAddr The linear address causing the EPT violation.
3937 * @param cbInstr The VM-exit instruction length.
3938 */
3939static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3940 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3941 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3942{
3943 /*
3944 * If the linear address isn't valid (can happen when loading PDPTEs
3945 * as part of MOV CR execution) the linear address field is undefined.
3946 * While we can leave it this way, it's preferrable to zero it for consistency.
3947 */
3948 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
3949
3950 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3951 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
3952
3953 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
3954 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
3955 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
3956 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3957 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
3958 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
3959 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3960 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3961 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3962 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3963 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
3964
3965 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3966 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3967 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3968 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3969 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3970 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3971 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
3972 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
3973 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3974
3975#ifdef VBOX_STRICT
3976 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3977 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3978 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3979 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3980 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3981 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3982#endif
3983
3984 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3985 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3986 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3987
3988 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3989}
3990
3991
3992/**
3993 * VMX VM-exit handler for EPT violation.
3994 *
3995 * This is intended for EPT violations where the caller provides all the
3996 * relevant VM-exit information.
3997 *
3998 * @returns VBox strict status code.
3999 * @param pVCpu The cross context virtual CPU structure.
4000 * @param pExitInfo Pointer to the VM-exit information.
4001 * @param pExitEventInfo Pointer to the VM-exit event information.
4002 */
4003static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4004 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4005{
4006 Assert(pExitInfo);
4007 Assert(pExitEventInfo);
4008 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4009 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4010
4011 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4012 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4013
4014 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4015 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4016 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4017 else
4018 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4019 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4020 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4021}
4022
4023
4024/**
4025 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4026 *
4027 * @returns Strict VBox status code.
4028 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4029 * @param pExitInfo Pointer to the VM-exit information.
4030 * @param pExitEventInfo Pointer to the VM-exit event information.
4031 * @thread EMT(pVCpu)
4032 */
4033VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4034 PCVMXVEXITEVENTINFO pExitEventInfo)
4035{
4036 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4037
4038 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4039 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4040 Assert(!pVCpu->iem.s.cActiveMappings);
4041 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4042}
4043
4044
4045/**
4046 * VMX VM-exit handler for EPT-induced VM-exits.
4047 *
4048 * @param pVCpu The cross context virtual CPU structure.
4049 * @param pWalk The page walk info.
4050 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4051 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4052 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4053 * applicable.
4054 */
4055VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4056{
4057 Assert(pWalk->fIsSlat);
4058 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4059 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4060 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4061
4062 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4063 {
4064 LogFlow(("EptViolation: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4065 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4066 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4067 pWalk->GCPtr, cbInstr);
4068 }
4069
4070 LogFlow(("EptMisconfig: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4071 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4072 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4073}
4074
4075
4076/**
4077 * VMX VM-exit handler for APIC accesses.
4078 *
4079 * @param pVCpu The cross context virtual CPU structure.
4080 * @param offAccess The offset of the register being accessed.
4081 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4082 */
4083static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4084{
4085 VMXAPICACCESS enmAccess;
4086 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4087 if (fInEventDelivery)
4088 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4089 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4090 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4091 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4092 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4093 else
4094 enmAccess = VMXAPICACCESS_LINEAR_READ;
4095
4096 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4097 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4098 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4099}
4100
4101
4102/**
4103 * VMX VM-exit handler for APIC accesses.
4104 *
4105 * This is intended for APIC accesses where the caller provides all the
4106 * relevant VM-exit information.
4107 *
4108 * @returns VBox strict status code.
4109 * @param pVCpu The cross context virtual CPU structure.
4110 * @param pExitInfo Pointer to the VM-exit information.
4111 * @param pExitEventInfo Pointer to the VM-exit event information.
4112 */
4113static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4114 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4115{
4116 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4117 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4118 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4119 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4120 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4121 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4122 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4123 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4124 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4125}
4126
4127
4128/**
4129 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4130 *
4131 * @returns Strict VBox status code.
4132 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4133 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4134 *
4135 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4136 * @param pExitInfo Pointer to the VM-exit information.
4137 * @param pExitEventInfo Pointer to the VM-exit event information.
4138 * @thread EMT(pVCpu)
4139 */
4140VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4141{
4142 Assert(pExitInfo);
4143 Assert(pExitEventInfo);
4144 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4145 Assert(!pVCpu->iem.s.cActiveMappings);
4146 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4147}
4148
4149
4150/**
4151 * VMX VM-exit handler for APIC-write VM-exits.
4152 *
4153 * @param pVCpu The cross context virtual CPU structure.
4154 * @param offApic The write to the virtual-APIC page offset that caused this
4155 * VM-exit.
4156 */
4157static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4158{
4159 Assert(offApic < XAPIC_OFF_END + 4);
4160 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4161 offApic &= UINT16_C(0xfff);
4162 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4163}
4164
4165
4166/**
4167 * Clears any pending virtual-APIC write emulation.
4168 *
4169 * @returns The virtual-APIC offset that was written before clearing it.
4170 * @param pVCpu The cross context virtual CPU structure.
4171 */
4172DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4173{
4174 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4175 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4176 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4177 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4178 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4179 return offVirtApicWrite;
4180}
4181
4182
4183/**
4184 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4185 *
4186 * @returns The register from the virtual-APIC page.
4187 * @param pVCpu The cross context virtual CPU structure.
4188 * @param offReg The offset of the register being read.
4189 */
4190uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4191{
4192 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4193
4194 uint32_t uReg = 0;
4195 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4196 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4197 AssertMsgStmt(RT_SUCCESS(rc),
4198 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4199 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4200 uReg = 0);
4201 return uReg;
4202}
4203
4204
4205/**
4206 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4207 *
4208 * @returns The register from the virtual-APIC page.
4209 * @param pVCpu The cross context virtual CPU structure.
4210 * @param offReg The offset of the register being read.
4211 */
4212static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4213{
4214 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4215
4216 uint64_t uReg = 0;
4217 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4218 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4219 AssertMsgStmt(RT_SUCCESS(rc),
4220 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4221 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4222 uReg = 0);
4223 return uReg;
4224}
4225
4226
4227/**
4228 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4229 *
4230 * @param pVCpu The cross context virtual CPU structure.
4231 * @param offReg The offset of the register being written.
4232 * @param uReg The register value to write.
4233 */
4234void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4235{
4236 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4237
4238 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4239 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4240 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4241 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4242}
4243
4244
4245/**
4246 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4247 *
4248 * @param pVCpu The cross context virtual CPU structure.
4249 * @param offReg The offset of the register being written.
4250 * @param uReg The register value to write.
4251 */
4252static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4253{
4254 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4255
4256 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4257 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4258 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4259 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4260}
4261
4262
4263/**
4264 * Sets the vector in a virtual-APIC 256-bit sparse register.
4265 *
4266 * @param pVCpu The cross context virtual CPU structure.
4267 * @param offReg The offset of the 256-bit spare register.
4268 * @param uVector The vector to set.
4269 *
4270 * @remarks This is based on our APIC device code.
4271 */
4272static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4273{
4274 /* Determine the vector offset within the chunk. */
4275 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4276
4277 /* Read the chunk at the offset. */
4278 uint32_t uReg;
4279 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4280 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4281 if (RT_SUCCESS(rc))
4282 {
4283 /* Modify the chunk. */
4284 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4285 uReg |= RT_BIT(idxVectorBit);
4286
4287 /* Write the chunk. */
4288 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4289 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4290 uVector, offReg, GCPhysVirtApic, rc));
4291 }
4292 else
4293 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4294 uVector, offReg, GCPhysVirtApic, rc));
4295}
4296
4297
4298/**
4299 * Clears the vector in a virtual-APIC 256-bit sparse register.
4300 *
4301 * @param pVCpu The cross context virtual CPU structure.
4302 * @param offReg The offset of the 256-bit spare register.
4303 * @param uVector The vector to clear.
4304 *
4305 * @remarks This is based on our APIC device code.
4306 */
4307static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4308{
4309 /* Determine the vector offset within the chunk. */
4310 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4311
4312 /* Read the chunk at the offset. */
4313 uint32_t uReg;
4314 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4315 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4316 if (RT_SUCCESS(rc))
4317 {
4318 /* Modify the chunk. */
4319 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4320 uReg &= ~RT_BIT(idxVectorBit);
4321
4322 /* Write the chunk. */
4323 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4324 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4325 uVector, offReg, GCPhysVirtApic, rc));
4326 }
4327 else
4328 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4329 uVector, offReg, GCPhysVirtApic, rc));
4330}
4331
4332
4333/**
4334 * Checks if a memory access to the APIC-access page must causes an APIC-access
4335 * VM-exit.
4336 *
4337 * @param pVCpu The cross context virtual CPU structure.
4338 * @param offAccess The offset of the register being accessed.
4339 * @param cbAccess The size of the access in bytes.
4340 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4341 *
4342 * @remarks This must not be used for MSR-based APIC-access page accesses!
4343 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4344 */
4345static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4346{
4347 Assert(cbAccess > 0);
4348 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4349
4350 /*
4351 * We must cause a VM-exit if any of the following are true:
4352 * - TPR shadowing isn't active.
4353 * - The access size exceeds 32-bits.
4354 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4355 *
4356 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4357 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4358 */
4359 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4360 || cbAccess > sizeof(uint32_t)
4361 || ((offAccess + cbAccess - 1) & 0xc)
4362 || offAccess >= XAPIC_OFF_END + 4)
4363 return true;
4364
4365 /*
4366 * If the access is part of an operation where we have already
4367 * virtualized a virtual-APIC write, we must cause a VM-exit.
4368 */
4369 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4370 return true;
4371
4372 /*
4373 * Check write accesses to the APIC-access page that cause VM-exits.
4374 */
4375 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4376 {
4377 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4378 {
4379 /*
4380 * With APIC-register virtualization, a write access to any of the
4381 * following registers are virtualized. Accessing any other register
4382 * causes a VM-exit.
4383 */
4384 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4385 switch (offAlignedAccess)
4386 {
4387 case XAPIC_OFF_ID:
4388 case XAPIC_OFF_TPR:
4389 case XAPIC_OFF_EOI:
4390 case XAPIC_OFF_LDR:
4391 case XAPIC_OFF_DFR:
4392 case XAPIC_OFF_SVR:
4393 case XAPIC_OFF_ESR:
4394 case XAPIC_OFF_ICR_LO:
4395 case XAPIC_OFF_ICR_HI:
4396 case XAPIC_OFF_LVT_TIMER:
4397 case XAPIC_OFF_LVT_THERMAL:
4398 case XAPIC_OFF_LVT_PERF:
4399 case XAPIC_OFF_LVT_LINT0:
4400 case XAPIC_OFF_LVT_LINT1:
4401 case XAPIC_OFF_LVT_ERROR:
4402 case XAPIC_OFF_TIMER_ICR:
4403 case XAPIC_OFF_TIMER_DCR:
4404 break;
4405 default:
4406 return true;
4407 }
4408 }
4409 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4410 {
4411 /*
4412 * With virtual-interrupt delivery, a write access to any of the
4413 * following registers are virtualized. Accessing any other register
4414 * causes a VM-exit.
4415 *
4416 * Note! The specification does not allow writing to offsets in-between
4417 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4418 */
4419 switch (offAccess)
4420 {
4421 case XAPIC_OFF_TPR:
4422 case XAPIC_OFF_EOI:
4423 case XAPIC_OFF_ICR_LO:
4424 break;
4425 default:
4426 return true;
4427 }
4428 }
4429 else
4430 {
4431 /*
4432 * Without APIC-register virtualization or virtual-interrupt delivery,
4433 * only TPR accesses are virtualized.
4434 */
4435 if (offAccess == XAPIC_OFF_TPR)
4436 { /* likely */ }
4437 else
4438 return true;
4439 }
4440 }
4441 else
4442 {
4443 /*
4444 * Check read accesses to the APIC-access page that cause VM-exits.
4445 */
4446 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4447 {
4448 /*
4449 * With APIC-register virtualization, a read access to any of the
4450 * following registers are virtualized. Accessing any other register
4451 * causes a VM-exit.
4452 */
4453 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4454 switch (offAlignedAccess)
4455 {
4456 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4457 case XAPIC_OFF_ID:
4458 case XAPIC_OFF_VERSION:
4459 case XAPIC_OFF_TPR:
4460 case XAPIC_OFF_EOI:
4461 case XAPIC_OFF_LDR:
4462 case XAPIC_OFF_DFR:
4463 case XAPIC_OFF_SVR:
4464 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4465 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4466 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4467 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4468 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4469 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4470 case XAPIC_OFF_ESR:
4471 case XAPIC_OFF_ICR_LO:
4472 case XAPIC_OFF_ICR_HI:
4473 case XAPIC_OFF_LVT_TIMER:
4474 case XAPIC_OFF_LVT_THERMAL:
4475 case XAPIC_OFF_LVT_PERF:
4476 case XAPIC_OFF_LVT_LINT0:
4477 case XAPIC_OFF_LVT_LINT1:
4478 case XAPIC_OFF_LVT_ERROR:
4479 case XAPIC_OFF_TIMER_ICR:
4480 case XAPIC_OFF_TIMER_DCR:
4481 break;
4482 default:
4483 return true;
4484 }
4485 }
4486 else
4487 {
4488 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4489 if (offAccess == XAPIC_OFF_TPR)
4490 { /* likely */ }
4491 else
4492 return true;
4493 }
4494 }
4495
4496 /* The APIC access is virtualized, does not cause a VM-exit. */
4497 return false;
4498}
4499
4500
4501/**
4502 * Virtualizes a memory-based APIC access by certain instructions even though they
4503 * do not use the address to access memory.
4504 *
4505 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4506 * page-faults but do not use the address to access memory.
4507 *
4508 * @param pVCpu The cross context virtual CPU structure.
4509 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4510 * @param cbAccess The size of the access in bytes.
4511 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4512 */
4513VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4514{
4515 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4516 Assert(pGCPhysAccess);
4517
4518 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4519 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4520 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4521
4522 if (GCPhysAccess == GCPhysApic)
4523 {
4524 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4525 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4526 if (fIntercept)
4527 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4528
4529 *pGCPhysAccess = GCPhysApic | offAccess;
4530 return VINF_VMX_MODIFIES_BEHAVIOR;
4531 }
4532
4533 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4534}
4535
4536
4537/**
4538 * Virtualizes a memory-based APIC access.
4539 *
4540 * @returns VBox strict status code.
4541 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4542 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4543 *
4544 * @param pVCpu The cross context virtual CPU structure.
4545 * @param offAccess The offset of the register being accessed (within the
4546 * APIC-access page).
4547 * @param cbAccess The size of the access in bytes.
4548 * @param pvData Pointer to the data being written or where to store the data
4549 * being read.
4550 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4551 */
4552static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4553 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4554{
4555 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4556 Assert(pvData);
4557
4558 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4559 if (fIntercept)
4560 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4561
4562 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4563 {
4564 /*
4565 * A write access to the APIC-access page that is virtualized (rather than
4566 * causing a VM-exit) writes data to the virtual-APIC page.
4567 */
4568 uint32_t const u32Data = *(uint32_t *)pvData;
4569 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4570
4571 /*
4572 * Record the currently updated APIC offset, as we need this later for figuring
4573 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4574 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4575 *
4576 * After completion of the current operation, we need to perform TPR virtualization,
4577 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4578 *
4579 * The current operation may be a REP-prefixed string instruction, execution of any
4580 * other instruction, or delivery of an event through the IDT.
4581 *
4582 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4583 * performed now but later after completion of the current operation.
4584 *
4585 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4586 */
4587 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4588
4589 LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4590 }
4591 else
4592 {
4593 /*
4594 * A read access from the APIC-access page that is virtualized (rather than
4595 * causing a VM-exit) returns data from the virtual-APIC page.
4596 *
4597 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4598 */
4599 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4600
4601 Assert(cbAccess <= 4);
4602 Assert(offAccess < XAPIC_OFF_END + 4);
4603 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4604
4605 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4606 u32Data &= s_auAccessSizeMasks[cbAccess];
4607 *(uint32_t *)pvData = u32Data;
4608
4609 LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4610 }
4611
4612 return VINF_VMX_MODIFIES_BEHAVIOR;
4613}
4614
4615
4616/**
4617 * Virtualizes an MSR-based APIC read access.
4618 *
4619 * @returns VBox strict status code.
4620 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4621 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4622 * handled by the x2APIC device.
4623 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4624 * not within the range of valid MSRs, caller must raise \#GP(0).
4625 * @param pVCpu The cross context virtual CPU structure.
4626 * @param idMsr The x2APIC MSR being read.
4627 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4628 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4629 */
4630static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4631{
4632 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4633 Assert(pu64Value);
4634
4635 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4636 {
4637 if ( idMsr >= MSR_IA32_X2APIC_START
4638 && idMsr <= MSR_IA32_X2APIC_END)
4639 {
4640 uint16_t const offReg = (idMsr & 0xff) << 4;
4641 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4642 *pu64Value = u64Value;
4643 return VINF_VMX_MODIFIES_BEHAVIOR;
4644 }
4645 return VERR_OUT_OF_RANGE;
4646 }
4647
4648 if (idMsr == MSR_IA32_X2APIC_TPR)
4649 {
4650 uint16_t const offReg = (idMsr & 0xff) << 4;
4651 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4652 *pu64Value = u64Value;
4653 return VINF_VMX_MODIFIES_BEHAVIOR;
4654 }
4655
4656 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4657}
4658
4659
4660/**
4661 * Virtualizes an MSR-based APIC write access.
4662 *
4663 * @returns VBox strict status code.
4664 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4665 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4666 * not within the range of valid MSRs, caller must raise \#GP(0).
4667 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4668 *
4669 * @param pVCpu The cross context virtual CPU structure.
4670 * @param idMsr The x2APIC MSR being written.
4671 * @param u64Value The value of the x2APIC MSR being written.
4672 */
4673static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4674{
4675 /*
4676 * Check if the access is to be virtualized.
4677 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4678 */
4679 if ( idMsr == MSR_IA32_X2APIC_TPR
4680 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4681 && ( idMsr == MSR_IA32_X2APIC_EOI
4682 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4683 {
4684 /* Validate the MSR write depending on the register. */
4685 switch (idMsr)
4686 {
4687 case MSR_IA32_X2APIC_TPR:
4688 case MSR_IA32_X2APIC_SELF_IPI:
4689 {
4690 if (u64Value & UINT64_C(0xffffffffffffff00))
4691 return VERR_OUT_OF_RANGE;
4692 break;
4693 }
4694 case MSR_IA32_X2APIC_EOI:
4695 {
4696 if (u64Value != 0)
4697 return VERR_OUT_OF_RANGE;
4698 break;
4699 }
4700 }
4701
4702 /* Write the MSR to the virtual-APIC page. */
4703 uint16_t const offReg = (idMsr & 0xff) << 4;
4704 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4705
4706 /*
4707 * Record the currently updated APIC offset, as we need this later for figuring
4708 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4709 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4710 */
4711 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4712
4713 return VINF_VMX_MODIFIES_BEHAVIOR;
4714 }
4715
4716 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4717}
4718
4719
4720/**
4721 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4722 *
4723 * @returns Strict VBox status code.
4724 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4725 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4726 * the x2APIC device.
4727 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4728 *
4729 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4730 * @param idMsr The MSR being read.
4731 * @param pu64Value Pointer to the value being written or where to store the
4732 * value being read.
4733 * @param fWrite Whether this is an MSR write or read access.
4734 * @thread EMT(pVCpu)
4735 */
4736VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4737{
4738 Assert(pu64Value);
4739
4740 VBOXSTRICTRC rcStrict;
4741 if (fWrite)
4742 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4743 else
4744 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4745 Assert(!pVCpu->iem.s.cActiveMappings);
4746 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4747
4748}
4749
4750
4751/**
4752 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4753 *
4754 * @returns VBox status code.
4755 * @retval VINF_SUCCESS when the highest set bit is found.
4756 * @retval VERR_NOT_FOUND when no bit is set.
4757 *
4758 * @param pVCpu The cross context virtual CPU structure.
4759 * @param offReg The offset of the APIC 256-bit sparse register.
4760 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4761 * set in the register. Only valid when VINF_SUCCESS is
4762 * returned.
4763 *
4764 * @remarks The format of the 256-bit sparse register here mirrors that found in
4765 * real APIC hardware.
4766 */
4767static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4768{
4769 Assert(offReg < XAPIC_OFF_END + 4);
4770 Assert(pidxHighestBit);
4771
4772 /*
4773 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4774 * However, in each fragment only the first 4 bytes are used.
4775 */
4776 uint8_t const cFrags = 8;
4777 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4778 {
4779 uint16_t const offFrag = iFrag * 16;
4780 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4781 if (!u32Frag)
4782 continue;
4783
4784 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4785 Assert(idxHighestBit > 0);
4786 --idxHighestBit;
4787 Assert(idxHighestBit <= UINT8_MAX);
4788 *pidxHighestBit = idxHighestBit;
4789 return VINF_SUCCESS;
4790 }
4791 return VERR_NOT_FOUND;
4792}
4793
4794
4795/**
4796 * Evaluates pending virtual interrupts.
4797 *
4798 * @param pVCpu The cross context virtual CPU structure.
4799 */
4800static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4801{
4802 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4803
4804 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4805 {
4806 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4807 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4808
4809 if ((uRvi >> 4) > (uPpr >> 4))
4810 {
4811 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4812 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4813 }
4814 else
4815 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4816 }
4817}
4818
4819
4820/**
4821 * Performs PPR virtualization.
4822 *
4823 * @returns VBox strict status code.
4824 * @param pVCpu The cross context virtual CPU structure.
4825 */
4826static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4827{
4828 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4829 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4830
4831 /*
4832 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4833 * or EOI-virtualization.
4834 *
4835 * See Intel spec. 29.1.3 "PPR Virtualization".
4836 */
4837 uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4838 uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4839
4840 uint32_t uPpr;
4841 if ((uTpr & 0xf0) >= uSvi)
4842 uPpr = uTpr;
4843 else
4844 uPpr = uSvi;
4845
4846 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4847 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4848}
4849
4850
4851/**
4852 * Performs VMX TPR virtualization.
4853 *
4854 * @returns VBox strict status code.
4855 * @param pVCpu The cross context virtual CPU structure.
4856 */
4857static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4858{
4859 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4860
4861 /*
4862 * We should have already performed the virtual-APIC write to the TPR offset
4863 * in the virtual-APIC page. We now perform TPR virtualization.
4864 *
4865 * See Intel spec. 29.1.2 "TPR Virtualization".
4866 */
4867 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4868 {
4869 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4870 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4871
4872 /*
4873 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4874 * See Intel spec. 29.1.2 "TPR Virtualization".
4875 */
4876 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4877 {
4878 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4879 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4880 }
4881 }
4882 else
4883 {
4884 iemVmxPprVirtualization(pVCpu);
4885 iemVmxEvalPendingVirtIntrs(pVCpu);
4886 }
4887
4888 return VINF_SUCCESS;
4889}
4890
4891
4892/**
4893 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4894 * not.
4895 *
4896 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4897 * @param pVCpu The cross context virtual CPU structure.
4898 * @param uVector The interrupt that was acknowledged using an EOI.
4899 */
4900static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4901{
4902 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4903 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4904
4905 if (uVector < 64)
4906 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4907 if (uVector < 128)
4908 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4909 if (uVector < 192)
4910 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4911 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4912}
4913
4914
4915/**
4916 * Performs EOI virtualization.
4917 *
4918 * @returns VBox strict status code.
4919 * @param pVCpu The cross context virtual CPU structure.
4920 */
4921static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4922{
4923 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4924 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4925
4926 /*
4927 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4928 * and get the next guest-interrupt that's in-service (if any).
4929 *
4930 * See Intel spec. 29.1.4 "EOI Virtualization".
4931 */
4932 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4933 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4934 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4935
4936 uint8_t uVector = uSvi;
4937 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4938
4939 uVector = 0;
4940 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4941
4942 if (uVector)
4943 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4944 else
4945 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4946
4947 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4948 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4949
4950 iemVmxPprVirtualization(pVCpu);
4951 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4952 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4953 iemVmxEvalPendingVirtIntrs(pVCpu);
4954 return VINF_SUCCESS;
4955}
4956
4957
4958/**
4959 * Performs self-IPI virtualization.
4960 *
4961 * @returns VBox strict status code.
4962 * @param pVCpu The cross context virtual CPU structure.
4963 */
4964static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4965{
4966 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4967 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4968
4969 /*
4970 * We should have already performed the virtual-APIC write to the self-IPI offset
4971 * in the virtual-APIC page. We now perform self-IPI virtualization.
4972 *
4973 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4974 */
4975 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4976 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4977 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4978 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4979 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4980 if (uVector > uRvi)
4981 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4982 iemVmxEvalPendingVirtIntrs(pVCpu);
4983 return VINF_SUCCESS;
4984}
4985
4986
4987/**
4988 * Performs VMX APIC-write emulation.
4989 *
4990 * @returns VBox strict status code.
4991 * @param pVCpu The cross context virtual CPU structure.
4992 */
4993VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
4994{
4995 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4996
4997 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4998 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4999
5000 /*
5001 * Perform APIC-write emulation based on the virtual-APIC register written.
5002 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5003 */
5004 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5005 VBOXSTRICTRC rcStrict;
5006 switch (offApicWrite)
5007 {
5008 case XAPIC_OFF_TPR:
5009 {
5010 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5011 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5012 uTpr &= UINT32_C(0x000000ff);
5013 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5014 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5015 rcStrict = iemVmxTprVirtualization(pVCpu);
5016 break;
5017 }
5018
5019 case XAPIC_OFF_EOI:
5020 {
5021 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5022 {
5023 /* Clear VEOI and perform EOI virtualization. */
5024 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5025 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5026 rcStrict = iemVmxEoiVirtualization(pVCpu);
5027 }
5028 else
5029 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5030 break;
5031 }
5032
5033 case XAPIC_OFF_ICR_LO:
5034 {
5035 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5036 {
5037 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5038 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5039 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5040 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5041 if ( !(uIcrLo & fIcrLoMb0)
5042 && (uIcrLo & fIcrLoMb1))
5043 {
5044 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5045 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5046 }
5047 else
5048 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5049 }
5050 else
5051 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5052 break;
5053 }
5054
5055 case XAPIC_OFF_ICR_HI:
5056 {
5057 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5058 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5059 uIcrHi &= UINT32_C(0xff000000);
5060 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5061 rcStrict = VINF_SUCCESS;
5062 break;
5063 }
5064
5065 default:
5066 {
5067 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5068 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5069 break;
5070 }
5071 }
5072
5073 return rcStrict;
5074}
5075
5076
5077/**
5078 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5079 * VM-exit.
5080 *
5081 * @returns Strict VBox status code.
5082 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5083 * @thread EMT(pVCpu)
5084 */
5085VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5086{
5087 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5088 Assert(!pVCpu->iem.s.cActiveMappings);
5089 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5090}
5091
5092
5093/**
5094 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5095 *
5096 * @param pVCpu The cross context virtual CPU structure.
5097 * @param pszInstr The VMX instruction name (for logging purposes).
5098 */
5099DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5100{
5101 /*
5102 * Guest Control Registers, Debug Registers, and MSRs.
5103 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5104 */
5105 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5106 const char * const pszFailure = "VM-exit";
5107 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5108
5109 /* CR0 reserved bits. */
5110 {
5111 /* CR0 MB1 bits. */
5112 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
5113 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5114 { /* likely */ }
5115 else
5116 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5117
5118 /* CR0 MBZ bits. */
5119 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5120 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5121 { /* likely */ }
5122 else
5123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5124
5125 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5126 if ( !fUnrestrictedGuest
5127 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5128 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5130 }
5131
5132 /* CR4 reserved bits. */
5133 {
5134 /* CR4 MB1 bits. */
5135 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5136 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5137 { /* likely */ }
5138 else
5139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5140
5141 /* CR4 MBZ bits. */
5142 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5143 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5144 { /* likely */ }
5145 else
5146 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5147 }
5148
5149 /* DEBUGCTL MSR. */
5150 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5151 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5152 { /* likely */ }
5153 else
5154 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5155
5156 /* 64-bit CPU checks. */
5157 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5158 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5159 {
5160 if (fGstInLongMode)
5161 {
5162 /* PAE must be set. */
5163 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5164 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5165 { /* likely */ }
5166 else
5167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5168 }
5169 else
5170 {
5171 /* PCIDE should not be set. */
5172 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5173 { /* likely */ }
5174 else
5175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5176 }
5177
5178 /* CR3. */
5179 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5180 { /* likely */ }
5181 else
5182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5183
5184 /* DR7. */
5185 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5186 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5187 { /* likely */ }
5188 else
5189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5190
5191 /* SYSENTER ESP and SYSENTER EIP. */
5192 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5193 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5194 { /* likely */ }
5195 else
5196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5197 }
5198
5199 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5200 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5201
5202 /* PAT MSR. */
5203 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5204 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5205 { /* likely */ }
5206 else
5207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5208
5209 /* EFER MSR. */
5210 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5211 {
5212 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5213 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5214 { /* likely */ }
5215 else
5216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5217
5218 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5219 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5220 if ( fGstLma == fGstInLongMode
5221 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5222 || fGstLma == fGstLme))
5223 { /* likely */ }
5224 else
5225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5226 }
5227
5228 /* We don't support IA32_BNDCFGS MSR yet. */
5229 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5230
5231 NOREF(pszInstr);
5232 NOREF(pszFailure);
5233 return VINF_SUCCESS;
5234}
5235
5236
5237/**
5238 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5239 *
5240 * @param pVCpu The cross context virtual CPU structure.
5241 * @param pszInstr The VMX instruction name (for logging purposes).
5242 */
5243DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5244{
5245 /*
5246 * Segment registers.
5247 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5248 */
5249 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5250 const char * const pszFailure = "VM-exit";
5251 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5252 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5253 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5254
5255 /* Selectors. */
5256 if ( !fGstInV86Mode
5257 && !fUnrestrictedGuest
5258 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5260
5261 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5262 {
5263 CPUMSELREG SelReg;
5264 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5265 if (RT_LIKELY(rc == VINF_SUCCESS))
5266 { /* likely */ }
5267 else
5268 return rc;
5269
5270 /*
5271 * Virtual-8086 mode checks.
5272 */
5273 if (fGstInV86Mode)
5274 {
5275 /* Base address. */
5276 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5277 { /* likely */ }
5278 else
5279 {
5280 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5281 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5282 }
5283
5284 /* Limit. */
5285 if (SelReg.u32Limit == 0xffff)
5286 { /* likely */ }
5287 else
5288 {
5289 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5291 }
5292
5293 /* Attribute. */
5294 if (SelReg.Attr.u == 0xf3)
5295 { /* likely */ }
5296 else
5297 {
5298 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5300 }
5301
5302 /* We're done; move to checking the next segment. */
5303 continue;
5304 }
5305
5306 /* Checks done by 64-bit CPUs. */
5307 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5308 {
5309 /* Base address. */
5310 if ( iSegReg == X86_SREG_FS
5311 || iSegReg == X86_SREG_GS)
5312 {
5313 if (X86_IS_CANONICAL(SelReg.u64Base))
5314 { /* likely */ }
5315 else
5316 {
5317 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5318 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5319 }
5320 }
5321 else if (iSegReg == X86_SREG_CS)
5322 {
5323 if (!RT_HI_U32(SelReg.u64Base))
5324 { /* likely */ }
5325 else
5326 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5327 }
5328 else
5329 {
5330 if ( SelReg.Attr.n.u1Unusable
5331 || !RT_HI_U32(SelReg.u64Base))
5332 { /* likely */ }
5333 else
5334 {
5335 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5336 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5337 }
5338 }
5339 }
5340
5341 /*
5342 * Checks outside Virtual-8086 mode.
5343 */
5344 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5345 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5346 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5347 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5348 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5349 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5350 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5351 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5352
5353 /* Code or usable segment. */
5354 if ( iSegReg == X86_SREG_CS
5355 || fUsable)
5356 {
5357 /* Reserved bits (bits 31:17 and bits 11:8). */
5358 if (!(SelReg.Attr.u & 0xfffe0f00))
5359 { /* likely */ }
5360 else
5361 {
5362 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5363 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5364 }
5365
5366 /* Descriptor type. */
5367 if (fCodeDataSeg)
5368 { /* likely */ }
5369 else
5370 {
5371 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5373 }
5374
5375 /* Present. */
5376 if (fPresent)
5377 { /* likely */ }
5378 else
5379 {
5380 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5382 }
5383
5384 /* Granularity. */
5385 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5386 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5387 { /* likely */ }
5388 else
5389 {
5390 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5391 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5392 }
5393 }
5394
5395 if (iSegReg == X86_SREG_CS)
5396 {
5397 /* Segment Type and DPL. */
5398 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5399 && fUnrestrictedGuest)
5400 {
5401 if (uDpl == 0)
5402 { /* likely */ }
5403 else
5404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5405 }
5406 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5407 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5408 {
5409 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5410 if (uDpl == AttrSs.n.u2Dpl)
5411 { /* likely */ }
5412 else
5413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5414 }
5415 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5416 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5417 {
5418 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5419 if (uDpl <= AttrSs.n.u2Dpl)
5420 { /* likely */ }
5421 else
5422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5423 }
5424 else
5425 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5426
5427 /* Def/Big. */
5428 if ( fGstInLongMode
5429 && fSegLong)
5430 {
5431 if (uDefBig == 0)
5432 { /* likely */ }
5433 else
5434 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5435 }
5436 }
5437 else if (iSegReg == X86_SREG_SS)
5438 {
5439 /* Segment Type. */
5440 if ( !fUsable
5441 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5442 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5443 { /* likely */ }
5444 else
5445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5446
5447 /* DPL. */
5448 if (!fUnrestrictedGuest)
5449 {
5450 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5451 { /* likely */ }
5452 else
5453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5454 }
5455 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5456 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5457 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5458 {
5459 if (uDpl == 0)
5460 { /* likely */ }
5461 else
5462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5463 }
5464 }
5465 else
5466 {
5467 /* DS, ES, FS, GS. */
5468 if (fUsable)
5469 {
5470 /* Segment type. */
5471 if (uSegType & X86_SEL_TYPE_ACCESSED)
5472 { /* likely */ }
5473 else
5474 {
5475 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5477 }
5478
5479 if ( !(uSegType & X86_SEL_TYPE_CODE)
5480 || (uSegType & X86_SEL_TYPE_READ))
5481 { /* likely */ }
5482 else
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5484
5485 /* DPL. */
5486 if ( !fUnrestrictedGuest
5487 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5488 {
5489 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5490 { /* likely */ }
5491 else
5492 {
5493 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5495 }
5496 }
5497 }
5498 }
5499 }
5500
5501 /*
5502 * LDTR.
5503 */
5504 {
5505 CPUMSELREG Ldtr;
5506 Ldtr.Sel = pVmcs->GuestLdtr;
5507 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5508 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5509 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5510
5511 if (!Ldtr.Attr.n.u1Unusable)
5512 {
5513 /* Selector. */
5514 if (!(Ldtr.Sel & X86_SEL_LDT))
5515 { /* likely */ }
5516 else
5517 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5518
5519 /* Base. */
5520 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5521 {
5522 if (X86_IS_CANONICAL(Ldtr.u64Base))
5523 { /* likely */ }
5524 else
5525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5526 }
5527
5528 /* Attributes. */
5529 /* Reserved bits (bits 31:17 and bits 11:8). */
5530 if (!(Ldtr.Attr.u & 0xfffe0f00))
5531 { /* likely */ }
5532 else
5533 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5534
5535 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5536 { /* likely */ }
5537 else
5538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5539
5540 if (!Ldtr.Attr.n.u1DescType)
5541 { /* likely */ }
5542 else
5543 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5544
5545 if (Ldtr.Attr.n.u1Present)
5546 { /* likely */ }
5547 else
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5549
5550 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5551 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5552 { /* likely */ }
5553 else
5554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5555 }
5556 }
5557
5558 /*
5559 * TR.
5560 */
5561 {
5562 CPUMSELREG Tr;
5563 Tr.Sel = pVmcs->GuestTr;
5564 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5565 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5566 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5567
5568 /* Selector. */
5569 if (!(Tr.Sel & X86_SEL_LDT))
5570 { /* likely */ }
5571 else
5572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5573
5574 /* Base. */
5575 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5576 {
5577 if (X86_IS_CANONICAL(Tr.u64Base))
5578 { /* likely */ }
5579 else
5580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5581 }
5582
5583 /* Attributes. */
5584 /* Reserved bits (bits 31:17 and bits 11:8). */
5585 if (!(Tr.Attr.u & 0xfffe0f00))
5586 { /* likely */ }
5587 else
5588 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5589
5590 if (!Tr.Attr.n.u1Unusable)
5591 { /* likely */ }
5592 else
5593 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5594
5595 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5596 || ( !fGstInLongMode
5597 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5598 { /* likely */ }
5599 else
5600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5601
5602 if (!Tr.Attr.n.u1DescType)
5603 { /* likely */ }
5604 else
5605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5606
5607 if (Tr.Attr.n.u1Present)
5608 { /* likely */ }
5609 else
5610 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5611
5612 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5613 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5614 { /* likely */ }
5615 else
5616 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5617 }
5618
5619 NOREF(pszInstr);
5620 NOREF(pszFailure);
5621 return VINF_SUCCESS;
5622}
5623
5624
5625/**
5626 * Checks guest GDTR and IDTR as part of VM-entry.
5627 *
5628 * @param pVCpu The cross context virtual CPU structure.
5629 * @param pszInstr The VMX instruction name (for logging purposes).
5630 */
5631DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5632{
5633 /*
5634 * GDTR and IDTR.
5635 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5636 */
5637 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5638 const char *const pszFailure = "VM-exit";
5639
5640 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5641 {
5642 /* Base. */
5643 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5644 { /* likely */ }
5645 else
5646 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5647
5648 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5649 { /* likely */ }
5650 else
5651 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5652 }
5653
5654 /* Limit. */
5655 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5656 { /* likely */ }
5657 else
5658 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5659
5660 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5661 { /* likely */ }
5662 else
5663 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5664
5665 NOREF(pszInstr);
5666 NOREF(pszFailure);
5667 return VINF_SUCCESS;
5668}
5669
5670
5671/**
5672 * Checks guest RIP and RFLAGS as part of VM-entry.
5673 *
5674 * @param pVCpu The cross context virtual CPU structure.
5675 * @param pszInstr The VMX instruction name (for logging purposes).
5676 */
5677DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5678{
5679 /*
5680 * RIP and RFLAGS.
5681 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5682 */
5683 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5684 const char *const pszFailure = "VM-exit";
5685 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5686
5687 /* RIP. */
5688 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5689 {
5690 X86DESCATTR AttrCs;
5691 AttrCs.u = pVmcs->u32GuestCsAttr;
5692 if ( !fGstInLongMode
5693 || !AttrCs.n.u1Long)
5694 {
5695 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5696 { /* likely */ }
5697 else
5698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5699 }
5700
5701 if ( fGstInLongMode
5702 && AttrCs.n.u1Long)
5703 {
5704 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5705 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5706 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5707 { /* likely */ }
5708 else
5709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5710 }
5711 }
5712
5713 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5714 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5715 : pVmcs->u64GuestRFlags.s.Lo;
5716 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5717 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5718 { /* likely */ }
5719 else
5720 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5721
5722 if (!(uGuestRFlags & X86_EFL_VM))
5723 { /* likely */ }
5724 else
5725 {
5726 if ( fGstInLongMode
5727 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5728 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5729 }
5730
5731 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5732 {
5733 if (uGuestRFlags & X86_EFL_IF)
5734 { /* likely */ }
5735 else
5736 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5737 }
5738
5739 NOREF(pszInstr);
5740 NOREF(pszFailure);
5741 return VINF_SUCCESS;
5742}
5743
5744
5745/**
5746 * Checks guest non-register state as part of VM-entry.
5747 *
5748 * @param pVCpu The cross context virtual CPU structure.
5749 * @param pszInstr The VMX instruction name (for logging purposes).
5750 */
5751DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5752{
5753 /*
5754 * Guest non-register state.
5755 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5756 */
5757 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5758 const char *const pszFailure = "VM-exit";
5759
5760 /*
5761 * Activity state.
5762 */
5763 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5764 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5765 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5766 { /* likely */ }
5767 else
5768 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5769
5770 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5771 if ( !AttrSs.n.u2Dpl
5772 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5773 { /* likely */ }
5774 else
5775 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5776
5777 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5778 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5779 {
5780 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5781 { /* likely */ }
5782 else
5783 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5784 }
5785
5786 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5787 {
5788 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5789 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5790 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5791 switch (pVmcs->u32GuestActivityState)
5792 {
5793 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5794 {
5795 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5796 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5797 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5798 && ( uVector == X86_XCPT_DB
5799 || uVector == X86_XCPT_MC))
5800 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5801 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5802 { /* likely */ }
5803 else
5804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5805 break;
5806 }
5807
5808 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5809 {
5810 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5811 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5812 && uVector == X86_XCPT_MC))
5813 { /* likely */ }
5814 else
5815 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5816 break;
5817 }
5818
5819 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5820 default:
5821 break;
5822 }
5823 }
5824
5825 /*
5826 * Interruptibility state.
5827 */
5828 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5829 { /* likely */ }
5830 else
5831 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5832
5833 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5834 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5835 { /* likely */ }
5836 else
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5838
5839 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5840 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5841 { /* likely */ }
5842 else
5843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5844
5845 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5846 {
5847 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5848 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5849 {
5850 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5851 { /* likely */ }
5852 else
5853 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5854 }
5855 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5856 {
5857 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5858 { /* likely */ }
5859 else
5860 {
5861 /*
5862 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5863 * We update the Exit qualification only when blocking-by-STI is set
5864 * without blocking-by-MovSS being set. Although in practise it does not
5865 * make much difference since the order of checks are implementation defined.
5866 */
5867 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5868 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5870 }
5871
5872 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5873 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5874 { /* likely */ }
5875 else
5876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5877 }
5878 }
5879
5880 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5881 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5882 { /* likely */ }
5883 else
5884 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5885
5886 /* We don't support SGX yet. So enclave-interruption must not be set. */
5887 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5888 { /* likely */ }
5889 else
5890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5891
5892 /*
5893 * Pending debug exceptions.
5894 */
5895 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5896 ? pVmcs->u64GuestPendingDbgXcpts.u
5897 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5898 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5899 { /* likely */ }
5900 else
5901 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5902
5903 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5904 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5905 {
5906 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5907 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5908 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5909 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5910
5911 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5912 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5913 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5915 }
5916
5917 /* We don't support RTM (Real-time Transactional Memory) yet. */
5918 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5919 { /* likely */ }
5920 else
5921 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5922
5923 /*
5924 * VMCS link pointer.
5925 */
5926 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5927 {
5928 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5929 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5930 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5931 { /* likely */ }
5932 else
5933 {
5934 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5936 }
5937
5938 /* Validate the address. */
5939 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5940 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5941 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5942 { /* likely */ }
5943 else
5944 {
5945 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5946 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5947 }
5948 }
5949
5950 NOREF(pszInstr);
5951 NOREF(pszFailure);
5952 return VINF_SUCCESS;
5953}
5954
5955
5956#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5957/**
5958 * Checks guest PDPTEs as part of VM-entry.
5959 *
5960 * @param pVCpu The cross context virtual CPU structure.
5961 * @param pszInstr The VMX instruction name (for logging purposes).
5962 */
5963static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
5964{
5965 /*
5966 * Guest PDPTEs.
5967 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5968 */
5969 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5970 const char * const pszFailure = "VM-exit";
5971
5972 /*
5973 * When EPT is used, we need to validate the PAE PDPTEs provided in the VMCS.
5974 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
5975 */
5976 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
5977 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
5978 {
5979 /* Get PDPTEs from the VMCS. */
5980 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5981 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5982 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5983 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5984 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5985
5986 /* Check validity of the PDPTEs. */
5987 if (PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]))
5988 { /* likely */ }
5989 else
5990 {
5991 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5992 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5993 }
5994 }
5995
5996 NOREF(pszFailure);
5997 NOREF(pszInstr);
5998 return VINF_SUCCESS;
5999}
6000#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6001
6002
6003/**
6004 * Checks guest-state as part of VM-entry.
6005 *
6006 * @returns VBox status code.
6007 * @param pVCpu The cross context virtual CPU structure.
6008 * @param pszInstr The VMX instruction name (for logging purposes).
6009 */
6010static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6011{
6012 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6013 if (RT_SUCCESS(rc))
6014 {
6015 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6016 if (RT_SUCCESS(rc))
6017 {
6018 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6019 if (RT_SUCCESS(rc))
6020 {
6021 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6022 if (RT_SUCCESS(rc))
6023 {
6024 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6025#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6026 if (RT_SUCCESS(rc))
6027 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6028#endif
6029 }
6030 }
6031 }
6032 }
6033 return rc;
6034}
6035
6036
6037/**
6038 * Checks host-state as part of VM-entry.
6039 *
6040 * @returns VBox status code.
6041 * @param pVCpu The cross context virtual CPU structure.
6042 * @param pszInstr The VMX instruction name (for logging purposes).
6043 */
6044static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6045{
6046 /*
6047 * Host Control Registers and MSRs.
6048 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6049 */
6050 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6051 const char * const pszFailure = "VMFail";
6052
6053 /* CR0 reserved bits. */
6054 {
6055 /* CR0 MB1 bits. */
6056 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
6057 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6058 { /* likely */ }
6059 else
6060 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6061
6062 /* CR0 MBZ bits. */
6063 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6064 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6065 { /* likely */ }
6066 else
6067 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6068 }
6069
6070 /* CR4 reserved bits. */
6071 {
6072 /* CR4 MB1 bits. */
6073 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6074 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6075 { /* likely */ }
6076 else
6077 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6078
6079 /* CR4 MBZ bits. */
6080 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6081 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6082 { /* likely */ }
6083 else
6084 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6085 }
6086
6087 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6088 {
6089 /* CR3 reserved bits. */
6090 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6091 { /* likely */ }
6092 else
6093 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6094
6095 /* SYSENTER ESP and SYSENTER EIP. */
6096 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6097 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6098 { /* likely */ }
6099 else
6100 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6101 }
6102
6103 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6104 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6105
6106 /* PAT MSR. */
6107 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6108 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6109 { /* likely */ }
6110 else
6111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6112
6113 /* EFER MSR. */
6114 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6115 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6116 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6117 { /* likely */ }
6118 else
6119 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6120
6121 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6122 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6123 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6124 if ( fHostInLongMode == fHostLma
6125 && fHostInLongMode == fHostLme)
6126 { /* likely */ }
6127 else
6128 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6129
6130 /*
6131 * Host Segment and Descriptor-Table Registers.
6132 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6133 */
6134 /* Selector RPL and TI. */
6135 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6136 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6137 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6138 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6139 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6140 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6141 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6142 { /* likely */ }
6143 else
6144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6145
6146 /* CS and TR selectors cannot be 0. */
6147 if ( pVmcs->HostCs
6148 && pVmcs->HostTr)
6149 { /* likely */ }
6150 else
6151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6152
6153 /* SS cannot be 0 if 32-bit host. */
6154 if ( fHostInLongMode
6155 || pVmcs->HostSs)
6156 { /* likely */ }
6157 else
6158 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6159
6160 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6161 {
6162 /* FS, GS, GDTR, IDTR, TR base address. */
6163 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6164 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6165 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6166 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6167 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6168 { /* likely */ }
6169 else
6170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6171 }
6172
6173 /*
6174 * Host address-space size for 64-bit CPUs.
6175 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6176 */
6177 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6178 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6179 {
6180 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6181
6182 /* Logical processor in IA-32e mode. */
6183 if (fCpuInLongMode)
6184 {
6185 if (fHostInLongMode)
6186 {
6187 /* PAE must be set. */
6188 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6189 { /* likely */ }
6190 else
6191 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6192
6193 /* RIP must be canonical. */
6194 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6195 { /* likely */ }
6196 else
6197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6198 }
6199 else
6200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6201 }
6202 else
6203 {
6204 /* Logical processor is outside IA-32e mode. */
6205 if ( !fGstInLongMode
6206 && !fHostInLongMode)
6207 {
6208 /* PCIDE should not be set. */
6209 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6210 { /* likely */ }
6211 else
6212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6213
6214 /* The high 32-bits of RIP MBZ. */
6215 if (!pVmcs->u64HostRip.s.Hi)
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6219 }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6222 }
6223 }
6224 else
6225 {
6226 /* Host address-space size for 32-bit CPUs. */
6227 if ( !fGstInLongMode
6228 && !fHostInLongMode)
6229 { /* likely */ }
6230 else
6231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6232 }
6233
6234 NOREF(pszInstr);
6235 NOREF(pszFailure);
6236 return VINF_SUCCESS;
6237}
6238
6239
6240#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6241/**
6242 * Checks the EPT pointer VMCS field as part of VM-entry.
6243 *
6244 * @returns VBox status code.
6245 * @param pVCpu The cross context virtual CPU structure.
6246 * @param uEptPtr The EPT pointer to check.
6247 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6248 * updated on success). Optional, can be NULL.
6249 */
6250static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6251{
6252 VMXVDIAG enmVmxDiag;
6253
6254 /* Reserved bits. */
6255 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6256 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6257 if (uEptPtr & fValidMask)
6258 {
6259 /* Memory Type. */
6260 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6261 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6262 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6263 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6264 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6265 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6266 {
6267 /*
6268 * Page walk length (PML4).
6269 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6270 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6271 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6272 */
6273 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6274 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6275 {
6276 /* Access and dirty bits support in EPT structures. */
6277 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6278 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6279 return VINF_SUCCESS;
6280
6281 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6282 }
6283 else
6284 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6285 }
6286 else
6287 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6288 }
6289 else
6290 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6291
6292 if (penmVmxDiag)
6293 *penmVmxDiag = enmVmxDiag;
6294 return VERR_VMX_VMENTRY_FAILED;
6295}
6296#endif
6297
6298
6299/**
6300 * Checks VMCS controls fields as part of VM-entry.
6301 *
6302 * @returns VBox status code.
6303 * @param pVCpu The cross context virtual CPU structure.
6304 * @param pszInstr The VMX instruction name (for logging purposes).
6305 *
6306 * @remarks This may update secondary-processor based VM-execution control fields
6307 * in the current VMCS if necessary.
6308 */
6309static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6310{
6311 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6312 const char * const pszFailure = "VMFail";
6313 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6314
6315 /*
6316 * VM-execution controls.
6317 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6318 */
6319 {
6320 /* Pin-based VM-execution controls. */
6321 {
6322 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6323 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6324 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6325 { /* likely */ }
6326 else
6327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6328
6329 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6330 { /* likely */ }
6331 else
6332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6333 }
6334
6335 /* Processor-based VM-execution controls. */
6336 {
6337 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6338 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6339 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6340 { /* likely */ }
6341 else
6342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6343
6344 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6345 { /* likely */ }
6346 else
6347 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6348 }
6349
6350 /* Secondary processor-based VM-execution controls. */
6351 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6352 {
6353 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6354 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6355 { /* likely */ }
6356 else
6357 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6358
6359 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6360 { /* likely */ }
6361 else
6362 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6363 }
6364 else
6365 Assert(!pVmcs->u32ProcCtls2);
6366
6367 /* CR3-target count. */
6368 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6369 { /* likely */ }
6370 else
6371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6372
6373 /* I/O bitmaps physical addresses. */
6374 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6375 {
6376 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6377 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6378 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6379 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6380 { /* likely */ }
6381 else
6382 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6383
6384 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6385 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6386 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6387 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6388 { /* likely */ }
6389 else
6390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6391 }
6392
6393 /* MSR bitmap physical address. */
6394 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6395 {
6396 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6397 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6398 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6399 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6400 { /* likely */ }
6401 else
6402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6403 }
6404
6405 /* TPR shadow related controls. */
6406 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6407 {
6408 /* Virtual-APIC page physical address. */
6409 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6410 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6411 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6412 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6413 { /* likely */ }
6414 else
6415 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6416
6417 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6418 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6419 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6420 { /* likely */ }
6421 else
6422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6423
6424 /* The rest done XXX document */
6425 }
6426 else
6427 {
6428 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6429 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6430 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6431 { /* likely */ }
6432 else
6433 {
6434 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6436 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6437 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6438 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6440 }
6441 }
6442
6443 /* NMI exiting and virtual-NMIs. */
6444 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6445 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6446 { /* likely */ }
6447 else
6448 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6449
6450 /* Virtual-NMIs and NMI-window exiting. */
6451 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6452 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6453 { /* likely */ }
6454 else
6455 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6456
6457 /* Virtualize APIC accesses. */
6458 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6459 {
6460 /* APIC-access physical address. */
6461 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6462 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6463 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6464 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6465 { /* likely */ }
6466 else
6467 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6468
6469 /*
6470 * Disallow APIC-access page and virtual-APIC page from being the same address.
6471 * Note! This is not an Intel requirement, but one imposed by our implementation.
6472 */
6473 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6474 * redirecting accesses between the APIC-access page and the virtual-APIC
6475 * page. If any nested hypervisor requires this, we can implement it later. */
6476 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6477 {
6478 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6479 if (GCPhysVirtApic != GCPhysApicAccess)
6480 { /* likely */ }
6481 else
6482 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6483 }
6484 }
6485
6486 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6487 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6488 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6489 { /* likely */ }
6490 else
6491 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6492
6493 /* Virtual-interrupt delivery requires external interrupt exiting. */
6494 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6495 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6496 { /* likely */ }
6497 else
6498 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6499
6500 /* VPID. */
6501 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6502 || pVmcs->u16Vpid != 0)
6503 { /* likely */ }
6504 else
6505 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6506
6507#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6508 /* Extended-Page-Table Pointer (EPTP). */
6509 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6510 {
6511 VMXVDIAG enmVmxDiag;
6512 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6513 if (RT_SUCCESS(rc))
6514 { /* likely */ }
6515 else
6516 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6517 }
6518#else
6519 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6520 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6521#endif
6522 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6523 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6524 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6525 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6526 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6527 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6528
6529 /* VMCS shadowing. */
6530 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6531 {
6532 /* VMREAD-bitmap physical address. */
6533 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6534 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6535 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6536 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6537 { /* likely */ }
6538 else
6539 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6540
6541 /* VMWRITE-bitmap physical address. */
6542 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6543 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6544 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6545 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6546 { /* likely */ }
6547 else
6548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6549 }
6550 }
6551
6552 /*
6553 * VM-exit controls.
6554 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6555 */
6556 {
6557 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6558 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6559 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6560 { /* likely */ }
6561 else
6562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6563
6564 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6565 { /* likely */ }
6566 else
6567 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6568
6569 /* Save preemption timer without activating it. */
6570 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6571 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6572 { /* likely */ }
6573 else
6574 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6575
6576 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6577 if (pVmcs->u32ExitMsrStoreCount)
6578 {
6579 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6580 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6581 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6582 { /* likely */ }
6583 else
6584 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6585 }
6586
6587 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6588 if (pVmcs->u32ExitMsrLoadCount)
6589 {
6590 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6591 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6592 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6593 { /* likely */ }
6594 else
6595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6596 }
6597 }
6598
6599 /*
6600 * VM-entry controls.
6601 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6602 */
6603 {
6604 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6605 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6606 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6607 { /* likely */ }
6608 else
6609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6610
6611 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6612 { /* likely */ }
6613 else
6614 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6615
6616 /* Event injection. */
6617 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6618 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6619 {
6620 /* Type and vector. */
6621 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6622 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6623 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6624 if ( !uRsvd
6625 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6626 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6627 { /* likely */ }
6628 else
6629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6630
6631 /* Exception error code. */
6632 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6633 {
6634 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6635 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6636 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6637 { /* likely */ }
6638 else
6639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6640
6641 /* Exceptions that provide an error code. */
6642 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6643 && ( uVector == X86_XCPT_DF
6644 || uVector == X86_XCPT_TS
6645 || uVector == X86_XCPT_NP
6646 || uVector == X86_XCPT_SS
6647 || uVector == X86_XCPT_GP
6648 || uVector == X86_XCPT_PF
6649 || uVector == X86_XCPT_AC))
6650 { /* likely */ }
6651 else
6652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6653
6654 /* Exception error-code reserved bits. */
6655 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6656 { /* likely */ }
6657 else
6658 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6659
6660 /* Injecting a software interrupt, software exception or privileged software exception. */
6661 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6662 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6663 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6664 {
6665 /* Instruction length must be in the range 0-15. */
6666 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6667 { /* likely */ }
6668 else
6669 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6670
6671 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6672 if ( pVmcs->u32EntryInstrLen != 0
6673 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6674 { /* likely */ }
6675 else
6676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6677 }
6678 }
6679 }
6680
6681 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6682 if (pVmcs->u32EntryMsrLoadCount)
6683 {
6684 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6685 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6686 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6687 { /* likely */ }
6688 else
6689 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6690 }
6691
6692 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6693 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6694 }
6695
6696 NOREF(pszInstr);
6697 NOREF(pszFailure);
6698 return VINF_SUCCESS;
6699}
6700
6701
6702/**
6703 * Loads the guest control registers, debug register and some MSRs as part of
6704 * VM-entry.
6705 *
6706 * @param pVCpu The cross context virtual CPU structure.
6707 */
6708static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6709{
6710 /*
6711 * Load guest control registers, debug registers and MSRs.
6712 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6713 */
6714 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6715
6716 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6717 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6718 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6719 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6720 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6721 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6722
6723 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6724 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6725
6726 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6727 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6728 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6729
6730 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6731 {
6732 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6733
6734 /* EFER MSR. */
6735 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6736 {
6737 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6738 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6739 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6740 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6741 if (fGstInLongMode)
6742 {
6743 /* If the nested-guest is in long mode, LMA and LME are both set. */
6744 Assert(fGstPaging);
6745 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6746 }
6747 else
6748 {
6749 /*
6750 * If the nested-guest is outside long mode:
6751 * - With paging: LMA is cleared, LME is cleared.
6752 * - Without paging: LMA is cleared, LME is left unmodified.
6753 */
6754 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6755 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6756 }
6757 }
6758 /* else: see below. */
6759 }
6760
6761 /* PAT MSR. */
6762 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6763 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6764
6765 /* EFER MSR. */
6766 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6767 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6768
6769 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6770 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6771
6772 /* We don't support IA32_BNDCFGS MSR yet. */
6773 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6774
6775 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6776}
6777
6778
6779/**
6780 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6781 *
6782 * @param pVCpu The cross context virtual CPU structure.
6783 */
6784static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6785{
6786 /*
6787 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6788 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6789 */
6790 /* CS, SS, ES, DS, FS, GS. */
6791 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6792 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6793 {
6794 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6795 CPUMSELREG VmcsSelReg;
6796 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6797 AssertRC(rc); NOREF(rc);
6798 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6799 {
6800 pGstSelReg->Sel = VmcsSelReg.Sel;
6801 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6802 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6803 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6804 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6805 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6806 }
6807 else
6808 {
6809 pGstSelReg->Sel = VmcsSelReg.Sel;
6810 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6811 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6812 switch (iSegReg)
6813 {
6814 case X86_SREG_CS:
6815 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6816 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6817 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6818 break;
6819
6820 case X86_SREG_SS:
6821 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6822 pGstSelReg->u32Limit = 0;
6823 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6824 break;
6825
6826 case X86_SREG_ES:
6827 case X86_SREG_DS:
6828 pGstSelReg->u64Base = 0;
6829 pGstSelReg->u32Limit = 0;
6830 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6831 break;
6832
6833 case X86_SREG_FS:
6834 case X86_SREG_GS:
6835 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6836 pGstSelReg->u32Limit = 0;
6837 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6838 break;
6839 }
6840 Assert(pGstSelReg->Attr.n.u1Unusable);
6841 }
6842 }
6843
6844 /* LDTR. */
6845 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6846 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6847 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6848 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6849 {
6850 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6851 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6852 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6853 }
6854 else
6855 {
6856 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6857 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6858 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6859 }
6860
6861 /* TR. */
6862 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6863 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6864 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6865 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6866 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6867 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6868 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6869
6870 /* GDTR. */
6871 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6872 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6873
6874 /* IDTR. */
6875 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6876 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6877}
6878
6879
6880/**
6881 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6882 *
6883 * @returns VBox status code.
6884 * @param pVCpu The cross context virtual CPU structure.
6885 * @param pszInstr The VMX instruction name (for logging purposes).
6886 */
6887static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6888{
6889 /*
6890 * Load guest MSRs.
6891 * See Intel spec. 26.4 "Loading MSRs".
6892 */
6893 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6894 const char *const pszFailure = "VM-exit";
6895
6896 /*
6897 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6898 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6899 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6900 */
6901 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6902 if (!cMsrs)
6903 return VINF_SUCCESS;
6904
6905 /*
6906 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6907 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6908 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6909 */
6910 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6911 if (fIsMsrCountValid)
6912 { /* likely */ }
6913 else
6914 {
6915 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6916 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6917 }
6918
6919 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6920 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6921 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6922 if (RT_SUCCESS(rc))
6923 {
6924 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6925 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6926 {
6927 if ( !pMsr->u32Reserved
6928 && pMsr->u32Msr != MSR_K8_FS_BASE
6929 && pMsr->u32Msr != MSR_K8_GS_BASE
6930 && pMsr->u32Msr != MSR_K6_EFER
6931 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6932 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6933 {
6934 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6935 if (rcStrict == VINF_SUCCESS)
6936 continue;
6937
6938 /*
6939 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6940 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6941 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6942 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6943 * MSR in ring-0 if possible, or come up with a better, generic solution.
6944 */
6945 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6946 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6947 ? kVmxVDiag_Vmentry_MsrLoadRing3
6948 : kVmxVDiag_Vmentry_MsrLoad;
6949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6950 }
6951 else
6952 {
6953 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6954 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6955 }
6956 }
6957 }
6958 else
6959 {
6960 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6961 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6962 }
6963
6964 NOREF(pszInstr);
6965 NOREF(pszFailure);
6966 return VINF_SUCCESS;
6967}
6968
6969
6970/**
6971 * Loads the guest-state non-register state as part of VM-entry.
6972 *
6973 * @returns VBox status code.
6974 * @param pVCpu The cross context virtual CPU structure.
6975 * @param pszInstr The VMX instruction name (for logging purposes).
6976 *
6977 * @remarks This must be called only after loading the nested-guest register state
6978 * (especially nested-guest RIP).
6979 */
6980static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6981{
6982 /*
6983 * Load guest non-register state.
6984 * See Intel spec. 26.6 "Special Features of VM Entry"
6985 */
6986 const char *const pszFailure = "VM-exit";
6987 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6988
6989 /*
6990 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6991 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6992 *
6993 * See Intel spec. 26.6.1 "Interruptibility State".
6994 */
6995 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6996 if ( !fEntryVectoring
6997 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6998 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6999 else
7000 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
7001
7002 /* NMI blocking. */
7003 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7004 {
7005 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7006 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7007 else
7008 {
7009 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7010 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7011 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7012 }
7013 }
7014 else
7015 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7016
7017 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7018
7019 /*
7020 * Set PGM's copy of the EPT pointer.
7021 * The EPTP has already been validated while checking guest state.
7022 *
7023 * It is important to do this prior to mapping PAE PDPTEs (below).
7024 */
7025 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7026 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7027
7028 /*
7029 * Load the guest's PAE PDPTEs.
7030 */
7031 if (!iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7032 {
7033 /*
7034 * When PAE paging is not used we clear the PAE PDPTEs for safety
7035 * in case we might be switching from a PAE host to a non-PAE guest.
7036 */
7037 pVCpu->cpum.GstCtx.aPaePdpes[0].u = 0;
7038 pVCpu->cpum.GstCtx.aPaePdpes[1].u = 0;
7039 pVCpu->cpum.GstCtx.aPaePdpes[2].u = 0;
7040 pVCpu->cpum.GstCtx.aPaePdpes[3].u = 0;
7041 }
7042 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7043 {
7044 /*
7045 * With EPT and the nested-guest using PAE paging, we've already validated the PAE PDPTEs
7046 * while checking the guest state. We can load them into the nested-guest CPU state now.
7047 * They'll later be used while mapping CR3 and the PAE PDPTEs.
7048 */
7049 pVCpu->cpum.GstCtx.aPaePdpes[0].u = pVmcs->u64GuestPdpte0.u;
7050 pVCpu->cpum.GstCtx.aPaePdpes[1].u = pVmcs->u64GuestPdpte1.u;
7051 pVCpu->cpum.GstCtx.aPaePdpes[2].u = pVmcs->u64GuestPdpte2.u;
7052 pVCpu->cpum.GstCtx.aPaePdpes[3].u = pVmcs->u64GuestPdpte3.u;
7053 }
7054 else
7055 {
7056 /*
7057 * Without EPT and the nested-guest using PAE paging, we must load the PAE PDPTEs
7058 * referenced by CR3. This involves loading (and mapping) CR3 and validating them now.
7059 */
7060 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7061 if (RT_SUCCESS(rc))
7062 { /* likely */ }
7063 else
7064 {
7065 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7066 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7067 }
7068 }
7069
7070 /* VPID is irrelevant. We don't support VPID yet. */
7071
7072 /* Clear address-range monitoring. */
7073 EMMonitorWaitClear(pVCpu);
7074
7075 return VINF_SUCCESS;
7076}
7077
7078
7079/**
7080 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7081 *
7082 * @param pVCpu The cross context virtual CPU structure.
7083 * @param pszInstr The VMX instruction name (for logging purposes).
7084 *
7085 * @remarks This assumes various VMCS related data structure pointers have already
7086 * been verified prior to calling this function.
7087 */
7088static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7089{
7090 const char *const pszFailure = "VM-exit";
7091 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7092
7093 /*
7094 * Virtualize APIC accesses.
7095 */
7096 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7097 {
7098 /* APIC-access physical address. */
7099 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7100
7101 /*
7102 * Register the handler for the APIC-access page.
7103 *
7104 * We don't deregister the APIC-access page handler during the VM-exit as a different
7105 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7106 *
7107 * We leave the page registered until the first access that happens outside VMX non-root
7108 * mode. Guest software is allowed to access structures such as the APIC-access page
7109 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7110 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7111 *
7112 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7113 */
7114 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
7115 {
7116 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7117 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess | X86_PAGE_4K_OFFSET_MASK,
7118 pVM->iem.s.hVmxApicAccessPage, 0 /*uUser*/, NULL /*pszDesc*/);
7119 if (RT_SUCCESS(rc))
7120 { /* likely */ }
7121 else
7122 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7123 }
7124 }
7125
7126 /*
7127 * VMCS shadowing.
7128 */
7129 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7130 {
7131 /* Read the VMREAD-bitmap. */
7132 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7133 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7134 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7135 if (RT_SUCCESS(rc))
7136 { /* likely */ }
7137 else
7138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7139
7140 /* Read the VMWRITE-bitmap. */
7141 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7142 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7143 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7144 if (RT_SUCCESS(rc))
7145 { /* likely */ }
7146 else
7147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7148 }
7149
7150 /*
7151 * I/O bitmaps.
7152 */
7153 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7154 {
7155 /* Read the IO bitmap A. */
7156 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7157 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7158 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7159 if (RT_SUCCESS(rc))
7160 { /* likely */ }
7161 else
7162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7163
7164 /* Read the IO bitmap B. */
7165 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7166 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7167 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7168 if (RT_SUCCESS(rc))
7169 { /* likely */ }
7170 else
7171 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7172 }
7173
7174 /*
7175 * TPR shadow and Virtual-APIC page.
7176 */
7177 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7178 {
7179 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7180 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7181 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7182 {
7183 /* Read the VTPR from the virtual-APIC page. */
7184 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7185 uint8_t u8VTpr;
7186 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7187 if (RT_SUCCESS(rc))
7188 { /* likely */ }
7189 else
7190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7191
7192 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7193 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7194 { /* likely */ }
7195 else
7196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7197 }
7198 }
7199
7200 /*
7201 * VMCS link pointer.
7202 */
7203 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7204 {
7205 /* Read the VMCS-link pointer from guest memory. */
7206 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7207 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7208 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7209 if (RT_SUCCESS(rc))
7210 { /* likely */ }
7211 else
7212 {
7213 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7215 }
7216
7217 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7218 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7219 { /* likely */ }
7220 else
7221 {
7222 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7224 }
7225
7226 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7227 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7228 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7229 { /* likely */ }
7230 else
7231 {
7232 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7234 }
7235
7236 /* Update our cache of the guest physical address of the shadow VMCS. */
7237 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7238 }
7239
7240 /*
7241 * MSR bitmap.
7242 */
7243 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7244 {
7245 /* Read the MSR bitmap. */
7246 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7247 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7248 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7249 if (RT_SUCCESS(rc))
7250 { /* likely */ }
7251 else
7252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7253 }
7254
7255 NOREF(pszFailure);
7256 NOREF(pszInstr);
7257 return VINF_SUCCESS;
7258}
7259
7260
7261/**
7262 * Loads the guest-state as part of VM-entry.
7263 *
7264 * @returns VBox status code.
7265 * @param pVCpu The cross context virtual CPU structure.
7266 * @param pszInstr The VMX instruction name (for logging purposes).
7267 *
7268 * @remarks This must be done after all the necessary steps prior to loading of
7269 * guest-state (e.g. checking various VMCS state).
7270 */
7271static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7272{
7273 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7274 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7275
7276 /* Load guest segment registers. */
7277 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7278
7279 /*
7280 * Load guest RIP, RSP and RFLAGS.
7281 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7282 */
7283 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7284 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7285 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7286 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7287
7288 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7289 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7290 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7291
7292 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7293 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7294 if (rc == VINF_SUCCESS)
7295 { /* likely */ }
7296 else
7297 return rc;
7298
7299 /* Load VMX related structures and state referenced by the VMCS. */
7300 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7301 if (rc == VINF_SUCCESS)
7302 { /* likely */ }
7303 else
7304 return rc;
7305
7306 NOREF(pszInstr);
7307 return VINF_SUCCESS;
7308}
7309
7310
7311/**
7312 * Returns whether there are is a pending debug exception on VM-entry.
7313 *
7314 * @param pVCpu The cross context virtual CPU structure.
7315 * @param pszInstr The VMX instruction name (for logging purposes).
7316 */
7317static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7318{
7319 /*
7320 * Pending debug exceptions.
7321 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7322 */
7323 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7324 Assert(pVmcs);
7325
7326 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7327 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7328 if (fPendingDbgXcpt)
7329 {
7330 uint8_t uEntryIntInfoType;
7331 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7332 if (fEntryVectoring)
7333 {
7334 switch (uEntryIntInfoType)
7335 {
7336 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7337 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7338 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7339 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7340 fPendingDbgXcpt = false;
7341 break;
7342
7343 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7344 {
7345 /*
7346 * Whether the pending debug exception for software exceptions other than
7347 * #BP and #OF is delivered after injecting the exception or is discard
7348 * is CPU implementation specific. We will discard them (easier).
7349 */
7350 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7351 if ( uVector != X86_XCPT_BP
7352 && uVector != X86_XCPT_OF)
7353 fPendingDbgXcpt = false;
7354 RT_FALL_THRU();
7355 }
7356 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7357 {
7358 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7359 fPendingDbgXcpt = false;
7360 break;
7361 }
7362 }
7363 }
7364 else
7365 {
7366 /*
7367 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7368 * pending debug exception is held pending or is discarded is CPU implementation
7369 * specific. We will discard them (easier).
7370 */
7371 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7372 fPendingDbgXcpt = false;
7373
7374 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7375 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7376 fPendingDbgXcpt = false;
7377 }
7378 }
7379
7380 NOREF(pszInstr);
7381 return fPendingDbgXcpt;
7382}
7383
7384
7385/**
7386 * Set up the monitor-trap flag (MTF).
7387 *
7388 * @param pVCpu The cross context virtual CPU structure.
7389 * @param pszInstr The VMX instruction name (for logging purposes).
7390 */
7391static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7392{
7393 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7394 Assert(pVmcs);
7395 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7396 {
7397 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7398 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7399 }
7400 else
7401 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7402 NOREF(pszInstr);
7403}
7404
7405
7406/**
7407 * Sets up NMI-window exiting.
7408 *
7409 * @param pVCpu The cross context virtual CPU structure.
7410 * @param pszInstr The VMX instruction name (for logging purposes).
7411 */
7412static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7413{
7414 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7415 Assert(pVmcs);
7416 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7417 {
7418 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7419 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7420 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7421 }
7422 else
7423 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7424 NOREF(pszInstr);
7425}
7426
7427
7428/**
7429 * Sets up interrupt-window exiting.
7430 *
7431 * @param pVCpu The cross context virtual CPU structure.
7432 * @param pszInstr The VMX instruction name (for logging purposes).
7433 */
7434static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7435{
7436 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7437 Assert(pVmcs);
7438 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7439 {
7440 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7441 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7442 }
7443 else
7444 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7445 NOREF(pszInstr);
7446}
7447
7448
7449/**
7450 * Set up the VMX-preemption timer.
7451 *
7452 * @param pVCpu The cross context virtual CPU structure.
7453 * @param pszInstr The VMX instruction name (for logging purposes).
7454 */
7455static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7456{
7457 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7458 Assert(pVmcs);
7459 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7460 {
7461 /*
7462 * If the timer is 0, we must cause a VM-exit before executing the first
7463 * nested-guest instruction. So we can flag as though the timer has already
7464 * expired and we will check and cause a VM-exit at the right priority elsewhere
7465 * in the code.
7466 */
7467 uint64_t uEntryTick;
7468 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7469 if (uPreemptTimer)
7470 {
7471 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7472 AssertRC(rc);
7473 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7474 }
7475 else
7476 {
7477 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7478 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7479 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7480 }
7481
7482 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7483 }
7484 else
7485 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7486
7487 NOREF(pszInstr);
7488}
7489
7490
7491/**
7492 * Injects an event using TRPM given a VM-entry interruption info and related
7493 * fields.
7494 *
7495 * @param pVCpu The cross context virtual CPU structure.
7496 * @param pszInstr The VMX instruction name (for logging purposes).
7497 * @param uEntryIntInfo The VM-entry interruption info.
7498 * @param uErrCode The error code associated with the event if any.
7499 * @param cbInstr The VM-entry instruction length (for software
7500 * interrupts and software exceptions). Pass 0
7501 * otherwise.
7502 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7503 */
7504static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7505 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7506{
7507 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7508
7509 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7510 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7511 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7512
7513 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7514
7515 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7516 AssertRC(rc);
7517 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7518
7519 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7520 {
7521 TRPMSetErrorCode(pVCpu, uErrCode);
7522 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7523 }
7524
7525 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7526 {
7527 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7528 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7529 }
7530 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7531 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7532 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7533 {
7534 TRPMSetInstrLength(pVCpu, cbInstr);
7535 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7536 }
7537
7538 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7539 {
7540 TRPMSetTrapDueToIcebp(pVCpu);
7541 Log(("%s: Injecting: icebp\n", pszInstr));
7542 }
7543
7544 NOREF(pszInstr);
7545}
7546
7547
7548/**
7549 * Performs event injection (if any) as part of VM-entry.
7550 *
7551 * @param pVCpu The cross context virtual CPU structure.
7552 * @param pszInstr The VMX instruction name (for logging purposes).
7553 */
7554static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7555{
7556 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7557
7558 /*
7559 * Inject events.
7560 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7561 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7562 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7563 * the actually delivery of this event.
7564 *
7565 * See Intel spec. 26.5 "Event Injection".
7566 */
7567 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7568 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7569
7570 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7571 if (fEntryIntInfoValid)
7572 {
7573 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7574 {
7575 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7576 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7577 }
7578 else
7579 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7580 pVCpu->cpum.GstCtx.cr2);
7581
7582 /*
7583 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7584 *
7585 * However, we do it here on VM-entry as well because while it isn't visible to guest
7586 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7587 * execution using hardware-assisted VMX, it will not try to inject the event again.
7588 *
7589 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7590 */
7591 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7592 }
7593 else
7594 {
7595 /*
7596 * Inject any pending guest debug exception.
7597 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7598 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7599 */
7600 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7601 if (fPendingDbgXcpt)
7602 {
7603 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7604 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7605 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7606 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7607 0 /* GCPtrFaultAddress */);
7608 }
7609 }
7610
7611 NOREF(pszInstr);
7612}
7613
7614
7615/**
7616 * Initializes all read-only VMCS fields as part of VM-entry.
7617 *
7618 * @param pVCpu The cross context virtual CPU structure.
7619 */
7620static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7621{
7622 /*
7623 * Any VMCS field which we do not establish on every VM-exit but may potentially
7624 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7625 * specified to be undefined, needs to be initialized here.
7626 *
7627 * Thus, it is especially important to clear the Exit qualification field
7628 * since it must be zero for VM-exits where it is not used. Similarly, the
7629 * VM-exit interruption information field's valid bit needs to be cleared for
7630 * the same reasons.
7631 */
7632 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7633 Assert(pVmcs);
7634
7635 /* 16-bit (none currently). */
7636 /* 32-bit. */
7637 pVmcs->u32RoVmInstrError = 0;
7638 pVmcs->u32RoExitReason = 0;
7639 pVmcs->u32RoExitIntInfo = 0;
7640 pVmcs->u32RoExitIntErrCode = 0;
7641 pVmcs->u32RoIdtVectoringInfo = 0;
7642 pVmcs->u32RoIdtVectoringErrCode = 0;
7643 pVmcs->u32RoExitInstrLen = 0;
7644 pVmcs->u32RoExitInstrInfo = 0;
7645
7646 /* 64-bit. */
7647 pVmcs->u64RoGuestPhysAddr.u = 0;
7648
7649 /* Natural-width. */
7650 pVmcs->u64RoExitQual.u = 0;
7651 pVmcs->u64RoIoRcx.u = 0;
7652 pVmcs->u64RoIoRsi.u = 0;
7653 pVmcs->u64RoIoRdi.u = 0;
7654 pVmcs->u64RoIoRip.u = 0;
7655 pVmcs->u64RoGuestLinearAddr.u = 0;
7656}
7657
7658
7659/**
7660 * VMLAUNCH/VMRESUME instruction execution worker.
7661 *
7662 * @returns Strict VBox status code.
7663 * @param pVCpu The cross context virtual CPU structure.
7664 * @param cbInstr The instruction length in bytes.
7665 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7666 * VMXINSTRID_VMRESUME).
7667 *
7668 * @remarks Common VMX instruction checks are already expected to by the caller,
7669 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7670 */
7671static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7672{
7673# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7674 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7675 return VINF_EM_RAW_EMULATE_INSTR;
7676# else
7677 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7678 || uInstrId == VMXINSTRID_VMRESUME);
7679 const char * const pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7680
7681 /* Nested-guest intercept. */
7682 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7683 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7684
7685 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7686
7687 /*
7688 * Basic VM-entry checks.
7689 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7690 * The checks following that do not have to follow a specific order.
7691 *
7692 * See Intel spec. 26.1 "Basic VM-entry Checks".
7693 */
7694
7695 /* CPL. */
7696 if (pVCpu->iem.s.uCpl == 0)
7697 { /* likely */ }
7698 else
7699 {
7700 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7701 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7702 return iemRaiseGeneralProtectionFault0(pVCpu);
7703 }
7704
7705 /* Current VMCS valid. */
7706 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7707 { /* likely */ }
7708 else
7709 {
7710 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7711 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7712 iemVmxVmFailInvalid(pVCpu);
7713 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7714 return VINF_SUCCESS;
7715 }
7716
7717 /* Current VMCS is not a shadow VMCS. */
7718 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7719 { /* likely */ }
7720 else
7721 {
7722 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7723 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7724 iemVmxVmFailInvalid(pVCpu);
7725 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7726 return VINF_SUCCESS;
7727 }
7728
7729 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7730 * use block-by-STI here which is not quite correct. */
7731 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7732 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7733 { /* likely */ }
7734 else
7735 {
7736 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7737 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7738 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7739 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7740 return VINF_SUCCESS;
7741 }
7742
7743 if (uInstrId == VMXINSTRID_VMLAUNCH)
7744 {
7745 /* VMLAUNCH with non-clear VMCS. */
7746 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7747 { /* likely */ }
7748 else
7749 {
7750 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7751 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7752 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7753 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7754 return VINF_SUCCESS;
7755 }
7756 }
7757 else
7758 {
7759 /* VMRESUME with non-launched VMCS. */
7760 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7761 { /* likely */ }
7762 else
7763 {
7764 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7765 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7766 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7767 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7768 return VINF_SUCCESS;
7769 }
7770 }
7771
7772 /*
7773 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7774 * while entering VMX non-root mode. We do some of this while checking VM-execution
7775 * controls. The nested hypervisor should not make assumptions and cannot expect
7776 * predictable behavior if changes to these structures are made in guest memory while
7777 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7778 * modify them anyway as we cache them in host memory.
7779 *
7780 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7781 */
7782 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7783 Assert(pVmcs);
7784 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7785
7786 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7787 if (RT_SUCCESS(rc))
7788 {
7789 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7790 if (RT_SUCCESS(rc))
7791 {
7792 /*
7793 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7794 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7795 * ones that may occur during VM-entry below).
7796 */
7797 iemVmxVmentryInitReadOnlyFields(pVCpu);
7798
7799 /*
7800 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7801 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7802 * VM-exit when required.
7803 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7804 */
7805 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7806
7807 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7808 if (RT_SUCCESS(rc))
7809 {
7810 /*
7811 * We've now entered nested-guest execution.
7812 *
7813 * It is important do this prior to loading the guest state because
7814 * as part of loading the guest state, PGM (and perhaps other components
7815 * in the future) relies on detecting whether VMX non-root mode has been
7816 * entered.
7817 */
7818 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7819
7820 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7821 if (RT_SUCCESS(rc))
7822 {
7823 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7824 if (RT_SUCCESS(rc))
7825 {
7826 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7827
7828 /* VMLAUNCH instruction must update the VMCS launch state. */
7829 if (uInstrId == VMXINSTRID_VMLAUNCH)
7830 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7831
7832 /* Perform the VMX transition (PGM updates). */
7833 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7834 if (rcStrict == VINF_SUCCESS)
7835 { /* likely */ }
7836 else if (RT_SUCCESS(rcStrict))
7837 {
7838 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7839 VBOXSTRICTRC_VAL(rcStrict)));
7840 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7841 }
7842 else
7843 {
7844 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7845 return rcStrict;
7846 }
7847
7848 /* Paranoia. */
7849 Assert(rcStrict == VINF_SUCCESS);
7850
7851 /*
7852 * The priority of potential VM-exits during VM-entry is important.
7853 * The priorities of VM-exits and events are listed from highest
7854 * to lowest as follows:
7855 *
7856 * 1. Event injection.
7857 * 2. Trap on task-switch (T flag set in TSS).
7858 * 3. TPR below threshold / APIC-write.
7859 * 4. SMI, INIT.
7860 * 5. MTF exit.
7861 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7862 * 7. VMX-preemption timer.
7863 * 9. NMI-window exit.
7864 * 10. NMI injection.
7865 * 11. Interrupt-window exit.
7866 * 12. Virtual-interrupt injection.
7867 * 13. Interrupt injection.
7868 * 14. Process next instruction (fetch, decode, execute).
7869 */
7870
7871 /* Setup VMX-preemption timer. */
7872 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7873
7874 /* Setup monitor-trap flag. */
7875 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7876
7877 /* Setup NMI-window exiting. */
7878 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7879
7880 /* Setup interrupt-window exiting. */
7881 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7882
7883 /*
7884 * Inject any event that the nested hypervisor wants to inject.
7885 * Note! We cannot immediately perform the event injection here as we may have
7886 * pending PGM operations to perform due to switching page tables and/or
7887 * mode.
7888 */
7889 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7890
7891# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7892 /* Reschedule to IEM-only execution of the nested-guest. */
7893 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7894 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7895 if (rcSched != VINF_SUCCESS)
7896 iemSetPassUpStatus(pVCpu, rcSched);
7897# endif
7898
7899 /* Finally, done. */
7900 LogFlow(("%s: cs:rip=%04x:%08RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7901 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7902 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7903 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7904 return VINF_SUCCESS;
7905 }
7906 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7907 }
7908 }
7909 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7910 }
7911
7912 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7913 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7914 return VINF_SUCCESS;
7915 }
7916
7917 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7918 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7919 return VINF_SUCCESS;
7920# endif
7921}
7922
7923
7924/**
7925 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7926 *
7927 * @returns Strict VBox status code.
7928 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7929 * @param cbInstr The instruction length in bytes.
7930 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7931 * VMXINSTRID_VMRESUME).
7932 * @thread EMT(pVCpu)
7933 */
7934VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7935{
7936 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7937 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7938
7939 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7940 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7941 Assert(!pVCpu->iem.s.cActiveMappings);
7942 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
7943}
7944
7945
7946/**
7947 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7948 * (causes a VM-exit) or not.
7949 *
7950 * @returns @c true if the instruction is intercepted, @c false otherwise.
7951 * @param pVCpu The cross context virtual CPU structure.
7952 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7953 * VMX_EXIT_WRMSR).
7954 * @param idMsr The MSR.
7955 */
7956bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
7957{
7958 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7959 Assert( uExitReason == VMX_EXIT_RDMSR
7960 || uExitReason == VMX_EXIT_WRMSR);
7961
7962 /* Consult the MSR bitmap if the feature is supported. */
7963 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7964 Assert(pVmcs);
7965 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7966 {
7967 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7968 if (uExitReason == VMX_EXIT_RDMSR)
7969 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7970 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7971 }
7972
7973 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7974 return true;
7975}
7976
7977
7978/**
7979 * VMREAD instruction execution worker that does not perform any validation checks.
7980 *
7981 * Callers are expected to have performed the necessary checks and to ensure the
7982 * VMREAD will succeed.
7983 *
7984 * @param pVmcs Pointer to the virtual VMCS.
7985 * @param pu64Dst Where to write the VMCS value.
7986 * @param u64VmcsField The VMCS field.
7987 *
7988 * @remarks May be called with interrupts disabled.
7989 */
7990static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
7991{
7992 VMXVMCSFIELD VmcsField;
7993 VmcsField.u = u64VmcsField;
7994 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7995 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7996 uint8_t const uWidthType = (uWidth << 2) | uType;
7997 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7998 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7999 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8000 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8001 uWidth, uType, uIndex, uIndex));
8002 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8003
8004 /*
8005 * Read the VMCS component based on the field's effective width.
8006 *
8007 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8008 * indicates high bits (little endian).
8009 *
8010 * Note! The caller is responsible to trim the result and update registers
8011 * or memory locations are required. Here we just zero-extend to the largest
8012 * type (i.e. 64-bits).
8013 */
8014 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8015 uint8_t const *pbField = pbVmcs + offField;
8016 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8017 switch (uEffWidth)
8018 {
8019 case VMX_VMCSFIELD_WIDTH_64BIT:
8020 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8021 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8022 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8023 }
8024}
8025
8026
8027/**
8028 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8029 *
8030 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8031 * are performed. Bounds checks are strict builds only.
8032 *
8033 * @param pVmcs Pointer to the virtual VMCS.
8034 * @param u64VmcsField The VMCS field.
8035 * @param pu64Dst Where to store the VMCS value.
8036 *
8037 * @remarks May be called with interrupts disabled.
8038 * @todo This should probably be moved to CPUM someday.
8039 */
8040VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8041{
8042 AssertPtr(pVmcs);
8043 AssertPtr(pu64Dst);
8044 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8045}
8046
8047
8048/**
8049 * VMREAD common (memory/register) instruction execution worker.
8050 *
8051 * @returns Strict VBox status code.
8052 * @param pVCpu The cross context virtual CPU structure.
8053 * @param cbInstr The instruction length in bytes.
8054 * @param pu64Dst Where to write the VMCS value (only updated when
8055 * VINF_SUCCESS is returned).
8056 * @param u64VmcsField The VMCS field.
8057 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8058 * NULL.
8059 */
8060static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8061 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8062{
8063 /* Nested-guest intercept. */
8064 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8065 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8066 {
8067 if (pExitInfo)
8068 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8069 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8070 }
8071
8072 /* CPL. */
8073 if (pVCpu->iem.s.uCpl == 0)
8074 { /* likely */ }
8075 else
8076 {
8077 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8078 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8079 return iemRaiseGeneralProtectionFault0(pVCpu);
8080 }
8081
8082 pVCpu->iem.s.cPotentialExits++;
8083
8084 /* VMCS pointer in root mode. */
8085 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8086 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8087 { /* likely */ }
8088 else
8089 {
8090 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8091 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8092 iemVmxVmFailInvalid(pVCpu);
8093 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8094 return VINF_SUCCESS;
8095 }
8096
8097 /* VMCS-link pointer in non-root mode. */
8098 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8099 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8100 { /* likely */ }
8101 else
8102 {
8103 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8104 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8105 iemVmxVmFailInvalid(pVCpu);
8106 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8107 return VINF_SUCCESS;
8108 }
8109
8110 /* Supported VMCS field. */
8111 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8112 { /* likely */ }
8113 else
8114 {
8115 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8116 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8117 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8118 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8119 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8120 return VINF_SUCCESS;
8121 }
8122
8123 /*
8124 * Reading from the current or shadow VMCS.
8125 */
8126 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8127 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8128 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8129 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8130 Log4(("vmread %#RX64 => %#RX64\n", u64VmcsField, *pu64Dst));
8131 return VINF_SUCCESS;
8132}
8133
8134
8135/**
8136 * VMREAD (64-bit register) instruction execution worker.
8137 *
8138 * @returns Strict VBox status code.
8139 * @param pVCpu The cross context virtual CPU structure.
8140 * @param cbInstr The instruction length in bytes.
8141 * @param pu64Dst Where to store the VMCS field's value.
8142 * @param u64VmcsField The VMCS field.
8143 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8144 * NULL.
8145 */
8146static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8147 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8148{
8149 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8150 if (rcStrict == VINF_SUCCESS)
8151 {
8152 iemVmxVmSucceed(pVCpu);
8153 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8154 return VINF_SUCCESS;
8155 }
8156
8157 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8158 return rcStrict;
8159}
8160
8161
8162/**
8163 * VMREAD (32-bit register) instruction execution worker.
8164 *
8165 * @returns Strict VBox status code.
8166 * @param pVCpu The cross context virtual CPU structure.
8167 * @param cbInstr The instruction length in bytes.
8168 * @param pu32Dst Where to store the VMCS field's value.
8169 * @param u32VmcsField The VMCS field.
8170 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8171 * NULL.
8172 */
8173static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8174 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8175{
8176 uint64_t u64Dst;
8177 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8178 if (rcStrict == VINF_SUCCESS)
8179 {
8180 *pu32Dst = u64Dst;
8181 iemVmxVmSucceed(pVCpu);
8182 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8183 return VINF_SUCCESS;
8184 }
8185
8186 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8187 return rcStrict;
8188}
8189
8190
8191/**
8192 * VMREAD (memory) instruction execution worker.
8193 *
8194 * @returns Strict VBox status code.
8195 * @param pVCpu The cross context virtual CPU structure.
8196 * @param cbInstr The instruction length in bytes.
8197 * @param iEffSeg The effective segment register to use with @a u64Val.
8198 * Pass UINT8_MAX if it is a register access.
8199 * @param GCPtrDst The guest linear address to store the VMCS field's
8200 * value.
8201 * @param u64VmcsField The VMCS field.
8202 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8203 * NULL.
8204 */
8205static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8206 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8207{
8208 uint64_t u64Dst;
8209 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8210 if (rcStrict == VINF_SUCCESS)
8211 {
8212 /*
8213 * Write the VMCS field's value to the location specified in guest-memory.
8214 */
8215 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8216 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8217 else
8218 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8219 if (rcStrict == VINF_SUCCESS)
8220 {
8221 iemVmxVmSucceed(pVCpu);
8222 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8223 return VINF_SUCCESS;
8224 }
8225
8226 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8227 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8228 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8229 return rcStrict;
8230 }
8231
8232 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8233 return rcStrict;
8234}
8235
8236
8237/**
8238 * Interface for HM and EM to emulate the VMREAD instruction.
8239 *
8240 * @returns Strict VBox status code.
8241 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8242 * @param pExitInfo Pointer to the VM-exit information.
8243 * @thread EMT(pVCpu)
8244 */
8245VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8246{
8247 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8248 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8249 Assert(pExitInfo);
8250
8251 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8252
8253 VBOXSTRICTRC rcStrict;
8254 uint8_t const cbInstr = pExitInfo->cbInstr;
8255 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8256 uint64_t const u64FieldEnc = fIs64BitMode
8257 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8258 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8259 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8260 {
8261 if (fIs64BitMode)
8262 {
8263 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8264 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8265 }
8266 else
8267 {
8268 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8269 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8270 }
8271 }
8272 else
8273 {
8274 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8275 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8276 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8277 }
8278 Assert(!pVCpu->iem.s.cActiveMappings);
8279 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8280}
8281
8282
8283/**
8284 * VMWRITE instruction execution worker that does not perform any validation
8285 * checks.
8286 *
8287 * Callers are expected to have performed the necessary checks and to ensure the
8288 * VMWRITE will succeed.
8289 *
8290 * @param pVmcs Pointer to the virtual VMCS.
8291 * @param u64Val The value to write.
8292 * @param u64VmcsField The VMCS field.
8293 *
8294 * @remarks May be called with interrupts disabled.
8295 */
8296static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8297{
8298 VMXVMCSFIELD VmcsField;
8299 VmcsField.u = u64VmcsField;
8300 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8301 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8302 uint8_t const uWidthType = (uWidth << 2) | uType;
8303 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8304 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8305 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8306 Assert(offField < VMX_V_VMCS_SIZE);
8307 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8308
8309 /*
8310 * Write the VMCS component based on the field's effective width.
8311 *
8312 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8313 * indicates high bits (little endian).
8314 */
8315 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8316 uint8_t *pbField = pbVmcs + offField;
8317 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8318 switch (uEffWidth)
8319 {
8320 case VMX_VMCSFIELD_WIDTH_64BIT:
8321 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8322 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8323 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8324 }
8325}
8326
8327
8328/**
8329 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8330 *
8331 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8332 * are performed. Bounds checks are strict builds only.
8333 *
8334 * @param pVmcs Pointer to the virtual VMCS.
8335 * @param u64VmcsField The VMCS field.
8336 * @param u64Val The value to write.
8337 *
8338 * @remarks May be called with interrupts disabled.
8339 * @todo This should probably be moved to CPUM someday.
8340 */
8341VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8342{
8343 AssertPtr(pVmcs);
8344 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8345}
8346
8347
8348/**
8349 * VMWRITE instruction execution worker.
8350 *
8351 * @returns Strict VBox status code.
8352 * @param pVCpu The cross context virtual CPU structure.
8353 * @param cbInstr The instruction length in bytes.
8354 * @param iEffSeg The effective segment register to use with @a u64Val.
8355 * Pass UINT8_MAX if it is a register access.
8356 * @param u64Val The value to write (or guest linear address to the
8357 * value), @a iEffSeg will indicate if it's a memory
8358 * operand.
8359 * @param u64VmcsField The VMCS field.
8360 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8361 * NULL.
8362 */
8363static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8364 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8365{
8366 /* Nested-guest intercept. */
8367 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8368 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8369 {
8370 if (pExitInfo)
8371 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8372 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8373 }
8374
8375 /* CPL. */
8376 if (pVCpu->iem.s.uCpl == 0)
8377 { /* likely */ }
8378 else
8379 {
8380 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8381 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8382 return iemRaiseGeneralProtectionFault0(pVCpu);
8383 }
8384
8385 pVCpu->iem.s.cPotentialExits++;
8386
8387 /* VMCS pointer in root mode. */
8388 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8389 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8390 { /* likely */ }
8391 else
8392 {
8393 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8394 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8395 iemVmxVmFailInvalid(pVCpu);
8396 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8397 return VINF_SUCCESS;
8398 }
8399
8400 /* VMCS-link pointer in non-root mode. */
8401 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8402 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8403 { /* likely */ }
8404 else
8405 {
8406 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8407 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8408 iemVmxVmFailInvalid(pVCpu);
8409 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8410 return VINF_SUCCESS;
8411 }
8412
8413 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8414 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8415 if (!fIsRegOperand)
8416 {
8417 /* Read the value from the specified guest memory location. */
8418 VBOXSTRICTRC rcStrict;
8419 RTGCPTR const GCPtrVal = u64Val;
8420 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8421 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8422 else
8423 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8424 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8425 {
8426 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8427 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8428 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8429 return rcStrict;
8430 }
8431 }
8432 else
8433 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8434
8435 /* Supported VMCS field. */
8436 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8437 { /* likely */ }
8438 else
8439 {
8440 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8441 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8442 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8443 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8444 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8445 return VINF_SUCCESS;
8446 }
8447
8448 /* Read-only VMCS field. */
8449 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8450 if ( !fIsFieldReadOnly
8451 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8452 { /* likely */ }
8453 else
8454 {
8455 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8456 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8457 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8458 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8459 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8460 return VINF_SUCCESS;
8461 }
8462
8463 /*
8464 * Write to the current or shadow VMCS.
8465 */
8466 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8467 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8468 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8469 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8470 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8471 Log4(("vmwrite %#RX64 <= %#RX64\n", u64VmcsField, u64Val));
8472
8473 if ( !fInVmxNonRootMode
8474 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8475 {
8476 /* Notify HM that the VMCS content might have changed. */
8477 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8478 }
8479
8480 iemVmxVmSucceed(pVCpu);
8481 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8482 return VINF_SUCCESS;
8483}
8484
8485
8486/**
8487 * Interface for HM and EM to emulate the VMWRITE instruction.
8488 *
8489 * @returns Strict VBox status code.
8490 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8491 * @param pExitInfo Pointer to the VM-exit information.
8492 * @thread EMT(pVCpu)
8493 */
8494VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8495{
8496 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8497 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8498 Assert(pExitInfo);
8499
8500 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8501
8502 uint64_t u64Val;
8503 uint8_t iEffSeg;
8504 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8505 {
8506 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8507 iEffSeg = UINT8_MAX;
8508 }
8509 else
8510 {
8511 u64Val = pExitInfo->GCPtrEffAddr;
8512 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8513 }
8514 uint8_t const cbInstr = pExitInfo->cbInstr;
8515 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8516 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8517 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8518 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8519 Assert(!pVCpu->iem.s.cActiveMappings);
8520 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8521}
8522
8523
8524/**
8525 * VMCLEAR instruction execution worker.
8526 *
8527 * @returns Strict VBox status code.
8528 * @param pVCpu The cross context virtual CPU structure.
8529 * @param cbInstr The instruction length in bytes.
8530 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8531 * @param GCPtrVmcs The linear address of the VMCS pointer.
8532 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8533 *
8534 * @remarks Common VMX instruction checks are already expected to by the caller,
8535 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8536 */
8537static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8538 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8539{
8540 /* Nested-guest intercept. */
8541 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8542 {
8543 if (pExitInfo)
8544 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8545 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8546 }
8547
8548 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8549
8550 /* CPL. */
8551 if (pVCpu->iem.s.uCpl == 0)
8552 { /* likely */ }
8553 else
8554 {
8555 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8556 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8557 return iemRaiseGeneralProtectionFault0(pVCpu);
8558 }
8559
8560 /* Get the VMCS pointer from the location specified by the source memory operand. */
8561 RTGCPHYS GCPhysVmcs;
8562 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8563 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8564 { /* likely */ }
8565 else
8566 {
8567 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8568 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8569 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8570 return rcStrict;
8571 }
8572
8573 /* VMCS pointer alignment. */
8574 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8575 { /* likely */ }
8576 else
8577 {
8578 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8579 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8580 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8581 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8582 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8583 return VINF_SUCCESS;
8584 }
8585
8586 /* VMCS physical-address width limits. */
8587 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8588 { /* likely */ }
8589 else
8590 {
8591 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8592 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8593 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8594 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8595 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8596 return VINF_SUCCESS;
8597 }
8598
8599 /* VMCS is not the VMXON region. */
8600 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8601 { /* likely */ }
8602 else
8603 {
8604 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8605 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8606 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8607 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8608 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8609 return VINF_SUCCESS;
8610 }
8611
8612 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8613 restriction imposed by our implementation. */
8614 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8615 { /* likely */ }
8616 else
8617 {
8618 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8619 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8620 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8621 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8622 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8623 return VINF_SUCCESS;
8624 }
8625
8626 /*
8627 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8628 *
8629 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8630 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8631 * to 'clear'.
8632 */
8633 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8634 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8635 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8636 {
8637 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8638 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8639 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8640 }
8641 else
8642 {
8643 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8644 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8645 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8646 if (RT_FAILURE(rcStrict))
8647 return rcStrict;
8648 }
8649
8650 iemVmxVmSucceed(pVCpu);
8651 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8652 return VINF_SUCCESS;
8653}
8654
8655
8656/**
8657 * Interface for HM and EM to emulate the VMCLEAR instruction.
8658 *
8659 * @returns Strict VBox status code.
8660 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8661 * @param pExitInfo Pointer to the VM-exit information.
8662 * @thread EMT(pVCpu)
8663 */
8664VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8665{
8666 Assert(pExitInfo);
8667 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8668 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8669
8670 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8671
8672 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8673 uint8_t const cbInstr = pExitInfo->cbInstr;
8674 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8675 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8676 Assert(!pVCpu->iem.s.cActiveMappings);
8677 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8678}
8679
8680
8681/**
8682 * VMPTRST instruction execution worker.
8683 *
8684 * @returns Strict VBox status code.
8685 * @param pVCpu The cross context virtual CPU structure.
8686 * @param cbInstr The instruction length in bytes.
8687 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8688 * @param GCPtrVmcs The linear address of where to store the current VMCS
8689 * pointer.
8690 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8691 *
8692 * @remarks Common VMX instruction checks are already expected to by the caller,
8693 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8694 */
8695static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8696 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8697{
8698 /* Nested-guest intercept. */
8699 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8700 {
8701 if (pExitInfo)
8702 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8703 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8704 }
8705
8706 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8707
8708 /* CPL. */
8709 if (pVCpu->iem.s.uCpl == 0)
8710 { /* likely */ }
8711 else
8712 {
8713 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8714 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8715 return iemRaiseGeneralProtectionFault0(pVCpu);
8716 }
8717
8718 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8719 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8720 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8721 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8722 {
8723 iemVmxVmSucceed(pVCpu);
8724 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8725 return rcStrict;
8726 }
8727
8728 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8729 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8730 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8731 return rcStrict;
8732}
8733
8734
8735/**
8736 * Interface for HM and EM to emulate the VMPTRST instruction.
8737 *
8738 * @returns Strict VBox status code.
8739 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8740 * @param pExitInfo Pointer to the VM-exit information.
8741 * @thread EMT(pVCpu)
8742 */
8743VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8744{
8745 Assert(pExitInfo);
8746 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8747 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8748
8749 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8750
8751 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8752 uint8_t const cbInstr = pExitInfo->cbInstr;
8753 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8754 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8755 Assert(!pVCpu->iem.s.cActiveMappings);
8756 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8757}
8758
8759
8760/**
8761 * VMPTRLD instruction execution worker.
8762 *
8763 * @returns Strict VBox status code.
8764 * @param pVCpu The cross context virtual CPU structure.
8765 * @param cbInstr The instruction length in bytes.
8766 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8767 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8768 *
8769 * @remarks Common VMX instruction checks are already expected to by the caller,
8770 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8771 */
8772static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8773 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8774{
8775 /* Nested-guest intercept. */
8776 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8777 {
8778 if (pExitInfo)
8779 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8780 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8781 }
8782
8783 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8784
8785 /* CPL. */
8786 if (pVCpu->iem.s.uCpl == 0)
8787 { /* likely */ }
8788 else
8789 {
8790 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8791 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8792 return iemRaiseGeneralProtectionFault0(pVCpu);
8793 }
8794
8795 /* Get the VMCS pointer from the location specified by the source memory operand. */
8796 RTGCPHYS GCPhysVmcs;
8797 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8798 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8799 { /* likely */ }
8800 else
8801 {
8802 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8803 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8804 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8805 return rcStrict;
8806 }
8807
8808 /* VMCS pointer alignment. */
8809 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8810 { /* likely */ }
8811 else
8812 {
8813 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8814 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8815 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8816 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8817 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8818 return VINF_SUCCESS;
8819 }
8820
8821 /* VMCS physical-address width limits. */
8822 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8823 { /* likely */ }
8824 else
8825 {
8826 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8827 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8828 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8829 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8830 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8831 return VINF_SUCCESS;
8832 }
8833
8834 /* VMCS is not the VMXON region. */
8835 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8836 { /* likely */ }
8837 else
8838 {
8839 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8840 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8841 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8842 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8843 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8844 return VINF_SUCCESS;
8845 }
8846
8847 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8848 restriction imposed by our implementation. */
8849 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8850 { /* likely */ }
8851 else
8852 {
8853 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8854 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8855 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8856 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8857 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8858 return VINF_SUCCESS;
8859 }
8860
8861 /* Read just the VMCS revision from the VMCS. */
8862 VMXVMCSREVID VmcsRevId;
8863 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8864 if (RT_SUCCESS(rc))
8865 { /* likely */ }
8866 else
8867 {
8868 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8869 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8870 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8871 return rc;
8872 }
8873
8874 /*
8875 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8876 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8877 */
8878 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8879 && ( !VmcsRevId.n.fIsShadowVmcs
8880 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8881 { /* likely */ }
8882 else
8883 {
8884 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8885 {
8886 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8887 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8888 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8889 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8890 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8891 return VINF_SUCCESS;
8892 }
8893
8894 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8895 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8896 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8897 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8898 return VINF_SUCCESS;
8899 }
8900
8901 /*
8902 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8903 * the cache of an existing, current VMCS back to guest memory before loading a new,
8904 * different current VMCS.
8905 */
8906 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8907 {
8908 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8909 {
8910 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8911 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8912 }
8913
8914 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8915 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8916 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8917 if (RT_SUCCESS(rc))
8918 {
8919 /* Notify HM that a new, current VMCS is loaded. */
8920 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8921 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8922 }
8923 else
8924 {
8925 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8926 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8927 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8928 return rc;
8929 }
8930 }
8931
8932 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8933 iemVmxVmSucceed(pVCpu);
8934 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8935 return VINF_SUCCESS;
8936}
8937
8938
8939/**
8940 * Interface for HM and EM to emulate the VMPTRLD instruction.
8941 *
8942 * @returns Strict VBox status code.
8943 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8944 * @param pExitInfo Pointer to the VM-exit information.
8945 * @thread EMT(pVCpu)
8946 */
8947VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8948{
8949 Assert(pExitInfo);
8950 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8951 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8952
8953 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8954
8955 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8956 uint8_t const cbInstr = pExitInfo->cbInstr;
8957 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8958 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8959 Assert(!pVCpu->iem.s.cActiveMappings);
8960 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8961}
8962
8963
8964/**
8965 * INVVPID instruction execution worker.
8966 *
8967 * @returns Strict VBox status code.
8968 * @param pVCpu The cross context virtual CPU structure.
8969 * @param cbInstr The instruction length in bytes.
8970 * @param iEffSeg The segment of the invvpid descriptor.
8971 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8972 * @param u64InvvpidType The invalidation type.
8973 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8974 * NULL.
8975 *
8976 * @remarks Common VMX instruction checks are already expected to by the caller,
8977 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8978 */
8979VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8980 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8981{
8982 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8983 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8984 return iemRaiseUndefinedOpcode(pVCpu);
8985
8986 /* Nested-guest intercept. */
8987 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8988 {
8989 if (pExitInfo)
8990 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8991 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8992 }
8993
8994 /* CPL. */
8995 if (pVCpu->iem.s.uCpl != 0)
8996 {
8997 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8998 return iemRaiseGeneralProtectionFault0(pVCpu);
8999 }
9000
9001 /*
9002 * Validate INVVPID invalidation type.
9003 *
9004 * The instruction specifies exactly ONE of the supported invalidation types.
9005 *
9006 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9007 * supported. In theory, it's possible for a CPU to not support flushing individual
9008 * addresses but all the other types or any other combination. We do not take any
9009 * shortcuts here by assuming the types we currently expose to the guest.
9010 */
9011 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9012 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9013 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9014 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9015 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9016 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9017
9018 bool afSupportedTypes[4];
9019 afSupportedTypes[0] = fTypeIndivAddr;
9020 afSupportedTypes[1] = fTypeSingleCtx;
9021 afSupportedTypes[2] = fTypeAllCtx;
9022 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9023
9024 if ( fInvvpidSupported
9025 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9026 && afSupportedTypes[u64InvvpidType & 3])
9027 { /* likely */ }
9028 else
9029 {
9030 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9031 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9032 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9033 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9034 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9035 return VINF_SUCCESS;
9036 }
9037
9038 /*
9039 * Fetch the invvpid descriptor from guest memory.
9040 */
9041 RTUINT128U uDesc;
9042 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9043 if (rcStrict == VINF_SUCCESS)
9044 {
9045 /*
9046 * Validate the descriptor.
9047 */
9048 if (uDesc.s.Lo <= 0xffff)
9049 { /* likely */ }
9050 else
9051 {
9052 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9053 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9054 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9055 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9056 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9057 return VINF_SUCCESS;
9058 }
9059
9060 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9061 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9062 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
9063 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9064 switch (u64InvvpidType)
9065 {
9066 case VMXTLBFLUSHVPID_INDIV_ADDR:
9067 {
9068 if (uVpid != 0)
9069 {
9070 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9071 {
9072 /* Invalidate mappings for the linear address tagged with VPID. */
9073 /** @todo PGM support for VPID? Currently just flush everything. */
9074 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9075 iemVmxVmSucceed(pVCpu);
9076 }
9077 else
9078 {
9079 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9080 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9081 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9082 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9083 }
9084 }
9085 else
9086 {
9087 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9088 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9089 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9090 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9091 }
9092 break;
9093 }
9094
9095 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9096 {
9097 if (uVpid != 0)
9098 {
9099 /* Invalidate all mappings with VPID. */
9100 /** @todo PGM support for VPID? Currently just flush everything. */
9101 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9102 iemVmxVmSucceed(pVCpu);
9103 }
9104 else
9105 {
9106 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9107 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9108 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9109 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9110 }
9111 break;
9112 }
9113
9114 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9115 {
9116 /* Invalidate all mappings with non-zero VPIDs. */
9117 /** @todo PGM support for VPID? Currently just flush everything. */
9118 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9119 iemVmxVmSucceed(pVCpu);
9120 break;
9121 }
9122
9123 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9124 {
9125 if (uVpid != 0)
9126 {
9127 /* Invalidate all mappings with VPID except global translations. */
9128 /** @todo PGM support for VPID? Currently just flush everything. */
9129 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9130 iemVmxVmSucceed(pVCpu);
9131 }
9132 else
9133 {
9134 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9135 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9136 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9137 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9138 }
9139 break;
9140 }
9141 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9142 }
9143 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9144 }
9145 return rcStrict;
9146}
9147
9148
9149/**
9150 * Interface for HM and EM to emulate the INVVPID instruction.
9151 *
9152 * @returns Strict VBox status code.
9153 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9154 * @param pExitInfo Pointer to the VM-exit information.
9155 * @thread EMT(pVCpu)
9156 */
9157VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9158{
9159 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9160 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9161 Assert(pExitInfo);
9162
9163 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9164
9165 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9166 uint8_t const cbInstr = pExitInfo->cbInstr;
9167 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9168 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9169 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9170 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9171 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9172 Assert(!pVCpu->iem.s.cActiveMappings);
9173 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9174}
9175
9176#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9177
9178/**
9179 * INVEPT instruction execution worker.
9180 *
9181 * @returns Strict VBox status code.
9182 * @param pVCpu The cross context virtual CPU structure.
9183 * @param cbInstr The instruction length in bytes.
9184 * @param iEffSeg The segment of the invept descriptor.
9185 * @param GCPtrInveptDesc The address of invept descriptor.
9186 * @param u64InveptType The invalidation type.
9187 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9188 * NULL.
9189 *
9190 * @remarks Common VMX instruction checks are already expected to by the caller,
9191 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9192 */
9193static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9194 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9195{
9196 /* Check if EPT is supported, otherwise raise #UD. */
9197 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9198 return iemRaiseUndefinedOpcode(pVCpu);
9199
9200 /* Nested-guest intercept. */
9201 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9202 {
9203 if (pExitInfo)
9204 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9205 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9206 }
9207
9208 /* CPL. */
9209 if (pVCpu->iem.s.uCpl != 0)
9210 {
9211 Log(("invept: CPL != 0 -> #GP(0)\n"));
9212 return iemRaiseGeneralProtectionFault0(pVCpu);
9213 }
9214
9215 /*
9216 * Validate INVEPT invalidation type.
9217 *
9218 * The instruction specifies exactly ONE of the supported invalidation types.
9219 *
9220 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9221 * supported. In theory, it's possible for a CPU to not support flushing individual
9222 * addresses but all the other types or any other combination. We do not take any
9223 * shortcuts here by assuming the types we currently expose to the guest.
9224 */
9225 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9226 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9227 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9228 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9229
9230 bool afSupportedTypes[4];
9231 afSupportedTypes[0] = false;
9232 afSupportedTypes[1] = fTypeSingleCtx;
9233 afSupportedTypes[2] = fTypeAllCtx;
9234 afSupportedTypes[3] = false;
9235
9236 if ( fInveptSupported
9237 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9238 && afSupportedTypes[u64InveptType & 3])
9239 { /* likely */ }
9240 else
9241 {
9242 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9243 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9244 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9245 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9246 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9247 return VINF_SUCCESS;
9248 }
9249
9250 /*
9251 * Fetch the invept descriptor from guest memory.
9252 */
9253 RTUINT128U uDesc;
9254 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9255 if (rcStrict == VINF_SUCCESS)
9256 {
9257 /*
9258 * Validate the descriptor.
9259 *
9260 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9261 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9262 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9263 * better to be strict in our emulation until proven otherwise.
9264 */
9265 if (uDesc.s.Hi)
9266 {
9267 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9268 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9269 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9270 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9271 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9272 return VINF_SUCCESS;
9273 }
9274
9275 /*
9276 * Flush TLB mappings based on the EPT type.
9277 */
9278 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9279 {
9280 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9281 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9282 if (RT_SUCCESS(rc))
9283 { /* likely */ }
9284 else
9285 {
9286 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9287 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9288 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9289 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9290 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9291 return VINF_SUCCESS;
9292 }
9293 }
9294
9295 /** @todo PGM support for EPT tags? Currently just flush everything. */
9296 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9297 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9298 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9299
9300 iemVmxVmSucceed(pVCpu);
9301 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9302 }
9303
9304 return rcStrict;
9305}
9306
9307
9308/**
9309 * Interface for HM and EM to emulate the INVEPT instruction.
9310 *
9311 * @returns Strict VBox status code.
9312 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9313 * @param pExitInfo Pointer to the VM-exit information.
9314 * @thread EMT(pVCpu)
9315 */
9316VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9317{
9318 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9319 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9320 Assert(pExitInfo);
9321
9322 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9323
9324 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9325 uint8_t const cbInstr = pExitInfo->cbInstr;
9326 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9327 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9328 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9329 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9330 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9331 Assert(!pVCpu->iem.s.cActiveMappings);
9332 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9333}
9334
9335#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9336
9337/**
9338 * VMXON instruction execution worker.
9339 *
9340 * @returns Strict VBox status code.
9341 * @param pVCpu The cross context virtual CPU structure.
9342 * @param cbInstr The instruction length in bytes.
9343 * @param iEffSeg The effective segment register to use with @a
9344 * GCPtrVmxon.
9345 * @param GCPtrVmxon The linear address of the VMXON pointer.
9346 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9347 *
9348 * @remarks Common VMX instruction checks are already expected to by the caller,
9349 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9350 */
9351static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9352 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9353{
9354 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9355 {
9356 /* CPL. */
9357 if (pVCpu->iem.s.uCpl == 0)
9358 { /* likely */ }
9359 else
9360 {
9361 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9362 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9363 return iemRaiseGeneralProtectionFault0(pVCpu);
9364 }
9365
9366 /* A20M (A20 Masked) mode. */
9367 if (PGMPhysIsA20Enabled(pVCpu))
9368 { /* likely */ }
9369 else
9370 {
9371 Log(("vmxon: A20M mode -> #GP(0)\n"));
9372 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9373 return iemRaiseGeneralProtectionFault0(pVCpu);
9374 }
9375
9376 /* CR0. */
9377 {
9378 /*
9379 * CR0 MB1 bits.
9380 *
9381 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9382 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9383 * when the guest running in VMX non-root mode with unrestricted-guest control
9384 * enabled in the VMCS.
9385 */
9386 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9387 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9388 { /* likely */ }
9389 else
9390 {
9391 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9392 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9393 return iemRaiseGeneralProtectionFault0(pVCpu);
9394 }
9395
9396 /* CR0 MBZ bits. */
9397 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9398 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9399 { /* likely */ }
9400 else
9401 {
9402 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9403 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9404 return iemRaiseGeneralProtectionFault0(pVCpu);
9405 }
9406 }
9407
9408 /* CR4. */
9409 {
9410 /* CR4 MB1 bits. */
9411 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9412 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9413 { /* likely */ }
9414 else
9415 {
9416 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9417 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9418 return iemRaiseGeneralProtectionFault0(pVCpu);
9419 }
9420
9421 /* CR4 MBZ bits. */
9422 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9423 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9424 { /* likely */ }
9425 else
9426 {
9427 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9428 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9429 return iemRaiseGeneralProtectionFault0(pVCpu);
9430 }
9431 }
9432
9433 /* Feature control MSR's LOCK and VMXON bits. */
9434 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9435 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9436 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9437 { /* likely */ }
9438 else
9439 {
9440 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9441 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9442 return iemRaiseGeneralProtectionFault0(pVCpu);
9443 }
9444
9445 /* Get the VMXON pointer from the location specified by the source memory operand. */
9446 RTGCPHYS GCPhysVmxon;
9447 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9448 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9449 { /* likely */ }
9450 else
9451 {
9452 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9454 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9455 return rcStrict;
9456 }
9457
9458 /* VMXON region pointer alignment. */
9459 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9460 { /* likely */ }
9461 else
9462 {
9463 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9464 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9465 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9466 iemVmxVmFailInvalid(pVCpu);
9467 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9468 return VINF_SUCCESS;
9469 }
9470
9471 /* VMXON physical-address width limits. */
9472 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9473 { /* likely */ }
9474 else
9475 {
9476 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9477 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9478 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9479 iemVmxVmFailInvalid(pVCpu);
9480 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9481 return VINF_SUCCESS;
9482 }
9483
9484 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9485 restriction imposed by our implementation. */
9486 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9487 { /* likely */ }
9488 else
9489 {
9490 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9491 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9492 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9493 iemVmxVmFailInvalid(pVCpu);
9494 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9495 return VINF_SUCCESS;
9496 }
9497
9498 /* Read the VMCS revision ID from the VMXON region. */
9499 VMXVMCSREVID VmcsRevId;
9500 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9501 if (RT_SUCCESS(rc))
9502 { /* likely */ }
9503 else
9504 {
9505 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9506 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9507 return rc;
9508 }
9509
9510 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9511 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9512 { /* likely */ }
9513 else
9514 {
9515 /* Revision ID mismatch. */
9516 if (!VmcsRevId.n.fIsShadowVmcs)
9517 {
9518 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9519 VmcsRevId.n.u31RevisionId));
9520 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9521 iemVmxVmFailInvalid(pVCpu);
9522 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9523 return VINF_SUCCESS;
9524 }
9525
9526 /* Shadow VMCS disallowed. */
9527 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9528 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9529 iemVmxVmFailInvalid(pVCpu);
9530 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9531 return VINF_SUCCESS;
9532 }
9533
9534 /*
9535 * Record that we're in VMX operation, block INIT, block and disable A20M.
9536 */
9537 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9538 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9539 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9540
9541 /* Clear address-range monitoring. */
9542 EMMonitorWaitClear(pVCpu);
9543 /** @todo NSTVMX: Intel PT. */
9544
9545 iemVmxVmSucceed(pVCpu);
9546 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9547 return VINF_SUCCESS;
9548 }
9549 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9550 {
9551 /* Nested-guest intercept. */
9552 if (pExitInfo)
9553 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9554 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9555 }
9556
9557 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9558
9559 /* CPL. */
9560 if (pVCpu->iem.s.uCpl > 0)
9561 {
9562 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9564 return iemRaiseGeneralProtectionFault0(pVCpu);
9565 }
9566
9567 /* VMXON when already in VMX root mode. */
9568 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9569 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9570 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9571 return VINF_SUCCESS;
9572}
9573
9574
9575/**
9576 * Interface for HM and EM to emulate the VMXON instruction.
9577 *
9578 * @returns Strict VBox status code.
9579 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9580 * @param pExitInfo Pointer to the VM-exit information.
9581 * @thread EMT(pVCpu)
9582 */
9583VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9584{
9585 Assert(pExitInfo);
9586 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9587 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9588
9589 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9590
9591 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9592 uint8_t const cbInstr = pExitInfo->cbInstr;
9593 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9594 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9595 Assert(!pVCpu->iem.s.cActiveMappings);
9596 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9597}
9598
9599
9600/**
9601 * Implements 'VMXOFF'.
9602 *
9603 * @remarks Common VMX instruction checks are already expected to by the caller,
9604 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9605 */
9606IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9607{
9608 /* Nested-guest intercept. */
9609 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9610 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9611
9612 /* CPL. */
9613 if (pVCpu->iem.s.uCpl == 0)
9614 { /* likely */ }
9615 else
9616 {
9617 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9618 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9619 return iemRaiseGeneralProtectionFault0(pVCpu);
9620 }
9621
9622 /* Dual monitor treatment of SMIs and SMM. */
9623 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9624 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9625 { /* likely */ }
9626 else
9627 {
9628 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9629 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9630 return VINF_SUCCESS;
9631 }
9632
9633 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9634 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9635 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9636
9637 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9638 { /** @todo NSTVMX: Unblock SMI. */ }
9639
9640 EMMonitorWaitClear(pVCpu);
9641 /** @todo NSTVMX: Unblock and enable A20M. */
9642
9643 iemVmxVmSucceed(pVCpu);
9644 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9645 return VINF_SUCCESS;
9646}
9647
9648
9649/**
9650 * Interface for HM and EM to emulate the VMXOFF instruction.
9651 *
9652 * @returns Strict VBox status code.
9653 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9654 * @param cbInstr The instruction length in bytes.
9655 * @thread EMT(pVCpu)
9656 */
9657VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9658{
9659 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9660 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9661
9662 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9663 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9664 Assert(!pVCpu->iem.s.cActiveMappings);
9665 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9666}
9667
9668
9669/**
9670 * Implements 'VMXON'.
9671 */
9672IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9673{
9674 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9675}
9676
9677
9678/**
9679 * Implements 'VMLAUNCH'.
9680 */
9681IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9682{
9683 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9684}
9685
9686
9687/**
9688 * Implements 'VMRESUME'.
9689 */
9690IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9691{
9692 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9693}
9694
9695
9696/**
9697 * Implements 'VMPTRLD'.
9698 */
9699IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9700{
9701 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9702}
9703
9704
9705/**
9706 * Implements 'VMPTRST'.
9707 */
9708IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9709{
9710 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9711}
9712
9713
9714/**
9715 * Implements 'VMCLEAR'.
9716 */
9717IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9718{
9719 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9720}
9721
9722
9723/**
9724 * Implements 'VMWRITE' register.
9725 */
9726IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9727{
9728 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9729}
9730
9731
9732/**
9733 * Implements 'VMWRITE' memory.
9734 */
9735IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9736{
9737 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9738}
9739
9740
9741/**
9742 * Implements 'VMREAD' register (64-bit).
9743 */
9744IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9745{
9746 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9747}
9748
9749
9750/**
9751 * Implements 'VMREAD' register (32-bit).
9752 */
9753IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9754{
9755 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9756}
9757
9758
9759/**
9760 * Implements 'VMREAD' memory, 64-bit register.
9761 */
9762IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9763{
9764 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9765}
9766
9767
9768/**
9769 * Implements 'VMREAD' memory, 32-bit register.
9770 */
9771IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9772{
9773 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9774}
9775
9776
9777/**
9778 * Implements 'INVVPID'.
9779 */
9780IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9781{
9782 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9783}
9784
9785
9786#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9787/**
9788 * Implements 'INVEPT'.
9789 */
9790IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9791{
9792 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9793}
9794#endif
9795
9796
9797/**
9798 * Implements VMX's implementation of PAUSE.
9799 */
9800IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9801{
9802 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9803 {
9804 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9805 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9806 return rcStrict;
9807 }
9808
9809 /*
9810 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9811 * a VM-exit, the instruction operates normally.
9812 */
9813 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9814 return VINF_SUCCESS;
9815}
9816
9817#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9818
9819
9820/**
9821 * Implements 'VMCALL'.
9822 */
9823IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9824{
9825 pVCpu->iem.s.cPotentialExits++;
9826
9827#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9828 /* Nested-guest intercept. */
9829 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9830 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9831#endif
9832
9833 /* Join forces with vmmcall. */
9834 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9835}
9836
9837
9838#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9839
9840/**
9841 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9842 *
9843 * @remarks The @a uUser argument is currently unused.
9844 */
9845DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9846 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9847 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9848{
9849 RT_NOREF3(pvPhys, enmOrigin, uUser);
9850
9851 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9852 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9853 {
9854 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9855 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9856
9857 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9858 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9859
9860 LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9861 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9862 if (RT_FAILURE(rcStrict))
9863 return rcStrict;
9864
9865 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9866 return VINF_SUCCESS;
9867 }
9868
9869 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9870 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9871 if (RT_FAILURE(rc))
9872 return rc;
9873
9874 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9875 return VINF_PGM_HANDLER_DO_DEFAULT;
9876}
9877
9878
9879# ifndef IN_RING3
9880/**
9881 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9882 * \#PF access handler callback for guest VMX APIC-access page.}
9883 */
9884DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
9885 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9886
9887{
9888 RT_NOREF3(pVM, pRegFrame, uUser);
9889
9890 /*
9891 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9892 * Otherwise we must deregister the page and allow regular RAM access.
9893 * Failing to do so lands us with endless EPT VM-exits.
9894 */
9895 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9896 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9897 {
9898 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9899 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9900
9901 /*
9902 * Check if the access causes an APIC-access VM-exit.
9903 */
9904 uint32_t fAccess;
9905 if (uErr & X86_TRAP_PF_ID)
9906 fAccess = IEM_ACCESS_INSTRUCTION;
9907 else if (uErr & X86_TRAP_PF_RW)
9908 fAccess = IEM_ACCESS_DATA_W;
9909 else
9910 fAccess = IEM_ACCESS_DATA_R;
9911
9912 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9913 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9914 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9915 LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
9916 if (fIntercept)
9917 {
9918 /*
9919 * Query the source VM-exit (from the execution engine) that caused this access
9920 * within the APIC-access page. Currently only HM is supported.
9921 */
9922 AssertMsg(VM_IS_HM_ENABLED(pVM),
9923 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
9924
9925 HMEXITAUX HmExitAux;
9926 RT_ZERO(HmExitAux);
9927 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9928 | HMVMX_READ_EXIT_QUALIFICATION
9929 | HMVMX_READ_IDT_VECTORING_INFO
9930 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9931 AssertRC(rc);
9932
9933 /*
9934 * Verify the VM-exit reason must be an EPT violation.
9935 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9936 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9937 */
9938 AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9939 ("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
9940 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
9941
9942 /*
9943 * Construct the virtual APIC-access VM-exit.
9944 */
9945 VMXAPICACCESS enmAccess;
9946 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9947 {
9948 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9949 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9950 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9951 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9952 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9953 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9954 else
9955 enmAccess = VMXAPICACCESS_LINEAR_READ;
9956
9957 /* For linear-address accesss the instruction length must be valid. */
9958 AssertMsg(HmExitAux.Vmx.cbInstr > 0,
9959 ("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
9960 }
9961 else
9962 {
9963 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9964 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
9965 else
9966 {
9967 /** @todo How to distinguish between monitoring/trace vs other instructions
9968 * here? */
9969 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
9970 }
9971
9972 /* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
9973 HmExitAux.Vmx.cbInstr = 0;
9974 }
9975
9976 /*
9977 * Raise the APIC-access VM-exit.
9978 */
9979 LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
9980 VMXVEXITINFO const ExitInfo
9981 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_APIC_ACCESS,
9982 RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
9983 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess),
9984 HmExitAux.Vmx.cbInstr);
9985 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_IDT(HmExitAux.Vmx.uIdtVectoringInfo,
9986 HmExitAux.Vmx.uIdtVectoringErrCode);
9987 VBOXSTRICTRC const rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
9988 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
9989 }
9990
9991 /*
9992 * The access isn't intercepted, which means it needs to be virtualized.
9993 *
9994 * This requires emulating the instruction because we need the bytes being
9995 * read/written by the instruction not just the offset being accessed within
9996 * the APIC-access page (which we derive from the faulting address).
9997 */
9998 LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
9999 return VINF_EM_RAW_EMULATE_INSTR;
10000 }
10001
10002 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10003 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10004 if (RT_FAILURE(rc))
10005 return rc;
10006
10007 return VINF_SUCCESS;
10008}
10009# endif /* !IN_RING3 */
10010
10011#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10012
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