VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 95259

Last change on this file since 95259 was 95161, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 Fixes to VMX APIC-access page fault handler.
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File size: 401.3 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp 95161 2022-06-01 11:38:16Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_IEM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <VBox/vmm/iem.h>
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/em.h>
29#include <VBox/vmm/hm.h>
30#include <VBox/vmm/gim.h>
31#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
32# include <VBox/vmm/hmvmxinline.h>
33#endif
34#include <VBox/vmm/tm.h>
35#include "IEMInternal.h"
36#include <VBox/vmm/vmcc.h>
37#include <VBox/log.h>
38#include <VBox/err.h>
39#include <VBox/param.h>
40#include <VBox/disopcode.h>
41#include <iprt/asm-math.h>
42#include <iprt/assert.h>
43#include <iprt/string.h>
44#include <iprt/x86.h>
45
46#include "IEMInline.h"
47
48
49/*********************************************************************************************************************************
50* Defined Constants And Macros *
51*********************************************************************************************************************************/
52#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
53/**
54 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
55 * relative offsets.
56 */
57# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
58# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
59# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
60# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
61# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
62# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
63# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
64# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
65# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
66# if 0
67# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
68# endif
69# else /* !IEM_WITH_CODE_TLB */
70# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
71 do \
72 { \
73 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
74 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
75 } while (0)
76
77# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
78
79# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
80 do \
81 { \
82 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
83 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
84 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
85 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
86 } while (0)
87
88# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
92 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
93 } while (0)
94
95# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
96 do \
97 { \
98 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
99 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
100 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
101 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
102 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
103 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
104 } while (0)
105
106# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
107 do \
108 { \
109 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
110 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
111 } while (0)
112
113# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
114 do \
115 { \
116 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
117 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
118 } while (0)
119
120# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
121 do \
122 { \
123 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
124 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
125 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
126 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
127 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
128 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
129 } while (0)
130# endif /* !IEM_WITH_CODE_TLB */
131
132/** Check for VMX instructions requiring to be in VMX operation.
133 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
134# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
135 do \
136 { \
137 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
138 { /* likely */ } \
139 else \
140 { \
141 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
142 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
143 return iemRaiseUndefinedOpcode(a_pVCpu); \
144 } \
145 } while (0)
146
147/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
148# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
149 do \
150 { \
151 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
152 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
153 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
154 return VERR_VMX_VMENTRY_FAILED; \
155 } while (0)
156
157/** Marks a VM-exit failure with a diagnostic reason and logs. */
158# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
159 do \
160 { \
161 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
162 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
163 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
164 } while (0)
165
166/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
167# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
168 do \
169 { \
170 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
171 return VERR_VMX_VMEXIT_FAILED; \
172 } while (0)
173
174
175/*********************************************************************************************************************************
176* Global Variables *
177*********************************************************************************************************************************/
178/** @todo NSTVMX: The following VM-exit intercepts are pending:
179 * VMX_EXIT_IO_SMI
180 * VMX_EXIT_SMI
181 * VMX_EXIT_GETSEC
182 * VMX_EXIT_RSM
183 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
184 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
185 * VMX_EXIT_RDRAND
186 * VMX_EXIT_VMFUNC
187 * VMX_EXIT_ENCLS
188 * VMX_EXIT_RDSEED
189 * VMX_EXIT_PML_FULL
190 * VMX_EXIT_XSAVES
191 * VMX_EXIT_XRSTORS
192 */
193/**
194 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
195 *
196 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
197 * second dimension is the Index, see VMXVMCSFIELD.
198 */
199uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
200{
201 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
202 {
203 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
204 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
205 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
206 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
207 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 27 */ UINT16_MAX,
210 },
211 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
212 {
213 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
214 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
215 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
216 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
217 },
218 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
219 {
220 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
221 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
222 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
223 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
224 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
225 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
226 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
227 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
228 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
229 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
230 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
231 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
232 /* 26-27 */ UINT16_MAX, UINT16_MAX
233 },
234 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
235 {
236 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
237 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
238 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
239 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
240 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
241 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
242 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
243 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
246 },
247 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
248 {
249 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
250 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
251 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
252 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
253 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
254 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
255 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
256 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
257 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
258 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
259 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
260 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
261 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
262 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
263 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
264 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
265 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
266 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
267 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
268 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
269 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
270 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
271 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
272 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
273 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
274 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
275 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
276 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
277 },
278 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
279 {
280 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
281 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
282 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
283 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
284 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
285 },
286 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
287 {
288 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
289 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
290 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
291 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
292 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
293 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
294 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
295 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
296 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
297 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
298 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
299 /* 11 */ UINT16_MAX,
300 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
301 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
302 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
303 },
304 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
305 {
306 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
307 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
308 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
309 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
310 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
311 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
312 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
313 },
314 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
315 {
316 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
317 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
318 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
319 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
320 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
321 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
322 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
323 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
324 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
325 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
326 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
327 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
328 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
329 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
330 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
331 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
332 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
333 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
334 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 26-27 */ UINT16_MAX, UINT16_MAX
336 },
337 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
338 {
339 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
340 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
341 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
342 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
343 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
344 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
345 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
346 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
347 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
348 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
349 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
350 },
351 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
352 {
353 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
354 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
355 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
356 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
357 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
358 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
359 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
360 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
361 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
362 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
363 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
364 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
365 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
366 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
367 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
368 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
369 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
370 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
371 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
372 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
373 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
374 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
375 /* 22 */ UINT16_MAX,
376 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
377 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
378 },
379 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
380 {
381 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
382 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
383 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
395 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
396 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
397 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
398 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
399 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
400 },
401 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
402 {
403 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
404 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
405 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
406 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
407 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
408 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
409 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
410 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
411 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
412 },
413 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
414 {
415 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
416 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
417 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
418 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
419 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
420 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
421 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
422 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
423 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
424 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
425 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
426 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
427 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
428 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
429 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
430 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
431 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
432 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
433 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
434 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
435 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
436 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
437 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
438 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 },
440 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
441 {
442 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
443 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
444 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
445 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
446 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
447 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
448 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
449 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
450 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
451 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
452 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
453 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
454 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
455 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
456 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
457 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
458 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
459 }
460};
461
462
463/**
464 * Gets a host selector from the VMCS.
465 *
466 * @param pVmcs Pointer to the virtual VMCS.
467 * @param iSelReg The index of the segment register (X86_SREG_XXX).
468 */
469DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
470{
471 Assert(iSegReg < X86_SREG_COUNT);
472 RTSEL HostSel;
473 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
474 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
475 uint8_t const uWidthType = (uWidth << 2) | uType;
476 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
477 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
478 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
479 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
480 uint8_t const *pbField = pbVmcs + offField;
481 HostSel = *(uint16_t *)pbField;
482 return HostSel;
483}
484
485
486/**
487 * Sets a guest segment register in the VMCS.
488 *
489 * @param pVmcs Pointer to the virtual VMCS.
490 * @param iSegReg The index of the segment register (X86_SREG_XXX).
491 * @param pSelReg Pointer to the segment register.
492 */
493static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
494{
495 Assert(pSelReg);
496 Assert(iSegReg < X86_SREG_COUNT);
497
498 /* Selector. */
499 {
500 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
501 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
502 uint8_t const uWidthType = (uWidth << 2) | uType;
503 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
504 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
505 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
506 uint8_t *pbVmcs = (uint8_t *)pVmcs;
507 uint8_t *pbField = pbVmcs + offField;
508 *(uint16_t *)pbField = pSelReg->Sel;
509 }
510
511 /* Limit. */
512 {
513 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
514 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
515 uint8_t const uWidthType = (uWidth << 2) | uType;
516 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
517 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
518 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
519 uint8_t *pbVmcs = (uint8_t *)pVmcs;
520 uint8_t *pbField = pbVmcs + offField;
521 *(uint32_t *)pbField = pSelReg->u32Limit;
522 }
523
524 /* Base. */
525 {
526 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
527 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
528 uint8_t const uWidthType = (uWidth << 2) | uType;
529 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
530 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
531 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
532 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
533 uint8_t const *pbField = pbVmcs + offField;
534 *(uint64_t *)pbField = pSelReg->u64Base;
535 }
536
537 /* Attributes. */
538 {
539 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
540 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
541 | X86DESCATTR_UNUSABLE;
542 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
543 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
544 uint8_t const uWidthType = (uWidth << 2) | uType;
545 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
546 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
547 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
548 uint8_t *pbVmcs = (uint8_t *)pVmcs;
549 uint8_t *pbField = pbVmcs + offField;
550 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
551 }
552}
553
554
555/**
556 * Gets a guest segment register from the VMCS.
557 *
558 * @returns VBox status code.
559 * @param pVmcs Pointer to the virtual VMCS.
560 * @param iSegReg The index of the segment register (X86_SREG_XXX).
561 * @param pSelReg Where to store the segment register (only updated when
562 * VINF_SUCCESS is returned).
563 *
564 * @remarks Warning! This does not validate the contents of the retrieved segment
565 * register.
566 */
567static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
568{
569 Assert(pSelReg);
570 Assert(iSegReg < X86_SREG_COUNT);
571
572 /* Selector. */
573 uint16_t u16Sel;
574 {
575 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
576 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
577 uint8_t const uWidthType = (uWidth << 2) | uType;
578 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
579 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
580 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
581 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
582 uint8_t const *pbField = pbVmcs + offField;
583 u16Sel = *(uint16_t *)pbField;
584 }
585
586 /* Limit. */
587 uint32_t u32Limit;
588 {
589 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
590 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
591 uint8_t const uWidthType = (uWidth << 2) | uType;
592 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
593 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
594 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
595 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
596 uint8_t const *pbField = pbVmcs + offField;
597 u32Limit = *(uint32_t *)pbField;
598 }
599
600 /* Base. */
601 uint64_t u64Base;
602 {
603 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
604 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
605 uint8_t const uWidthType = (uWidth << 2) | uType;
606 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
607 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
608 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
609 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
610 uint8_t const *pbField = pbVmcs + offField;
611 u64Base = *(uint64_t *)pbField;
612 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
613 }
614
615 /* Attributes. */
616 uint32_t u32Attr;
617 {
618 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
619 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
620 uint8_t const uWidthType = (uWidth << 2) | uType;
621 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
622 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
623 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
624 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
625 uint8_t const *pbField = pbVmcs + offField;
626 u32Attr = *(uint32_t *)pbField;
627 }
628
629 pSelReg->Sel = u16Sel;
630 pSelReg->ValidSel = u16Sel;
631 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
632 pSelReg->u32Limit = u32Limit;
633 pSelReg->u64Base = u64Base;
634 pSelReg->Attr.u = u32Attr;
635 return VINF_SUCCESS;
636}
637
638
639/**
640 * Converts an IEM exception event type to a VMX event type.
641 *
642 * @returns The VMX event type.
643 * @param uVector The interrupt / exception vector.
644 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
645 */
646DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
647{
648 /* Paranoia (callers may use these interchangeably). */
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
655 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
656 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
657 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
658 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
660 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
661
662 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
663 {
664 if (uVector == X86_XCPT_NMI)
665 return VMX_EXIT_INT_INFO_TYPE_NMI;
666 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
667 }
668
669 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
670 {
671 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
672 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
673 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
674 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
675 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
676 }
677
678 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
679 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
680}
681
682
683/**
684 * Determines whether the guest is using PAE paging given the VMCS.
685 *
686 * @returns @c true if PAE paging mode is used, @c false otherwise.
687 * @param pVmcs Pointer to the virtual VMCS.
688 */
689DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
690{
691 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
692 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
693 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
694}
695
696
697/**
698 * Sets the Exit qualification VMCS field.
699 *
700 * @param pVCpu The cross context virtual CPU structure.
701 * @param u64ExitQual The Exit qualification.
702 */
703DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
704{
705 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
706}
707
708
709/**
710 * Sets the VM-exit interruption information field.
711 *
712 * @param pVCpu The cross context virtual CPU structure.
713 * @param uExitIntInfo The VM-exit interruption information.
714 */
715DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
716{
717 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
718}
719
720
721/**
722 * Sets the VM-exit interruption error code.
723 *
724 * @param pVCpu The cross context virtual CPU structure.
725 * @param uErrCode The error code.
726 */
727DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
728{
729 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
730}
731
732
733/**
734 * Sets the IDT-vectoring information field.
735 *
736 * @param pVCpu The cross context virtual CPU structure.
737 * @param uIdtVectorInfo The IDT-vectoring information.
738 */
739DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
740{
741 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
742}
743
744
745/**
746 * Sets the IDT-vectoring error code field.
747 *
748 * @param pVCpu The cross context virtual CPU structure.
749 * @param uErrCode The error code.
750 */
751DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
752{
753 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
754}
755
756
757/**
758 * Sets the VM-exit guest-linear address VMCS field.
759 *
760 * @param pVCpu The cross context virtual CPU structure.
761 * @param uGuestLinearAddr The VM-exit guest-linear address.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
764{
765 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
766 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
767 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
768}
769
770
771/**
772 * Sets the VM-exit guest-physical address VMCS field.
773 *
774 * @param pVCpu The cross context virtual CPU structure.
775 * @param uGuestPhysAddr The VM-exit guest-physical address.
776 */
777DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
778{
779 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
780}
781
782
783/**
784 * Sets the VM-exit instruction length VMCS field.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 * @param cbInstr The VM-exit instruction length in bytes.
788 *
789 * @remarks Callers may clear this field to 0. Hence, this function does not check
790 * the validity of the instruction length.
791 */
792DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
793{
794 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
795}
796
797
798/**
799 * Sets the VM-exit instruction info. VMCS field.
800 *
801 * @param pVCpu The cross context virtual CPU structure.
802 * @param uExitInstrInfo The VM-exit instruction information.
803 */
804DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
805{
806 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
807}
808
809
810/**
811 * Sets the guest pending-debug exceptions field.
812 *
813 * @param pVCpu The cross context virtual CPU structure.
814 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
815 */
816DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
817{
818 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
819 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
820}
821
822
823/**
824 * Implements VMSucceed for VMX instruction success.
825 *
826 * @param pVCpu The cross context virtual CPU structure.
827 */
828DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
829{
830 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
831}
832
833
834/**
835 * Implements VMFailInvalid for VMX instruction failure.
836 *
837 * @param pVCpu The cross context virtual CPU structure.
838 */
839DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
840{
841 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
842}
843
844
845/**
846 * Implements VMFail for VMX instruction failure.
847 *
848 * @param pVCpu The cross context virtual CPU structure.
849 * @param enmInsErr The VM instruction error.
850 */
851DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
852{
853 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
854}
855
856
857/**
858 * Checks if the given auto-load/store MSR area count is valid for the
859 * implementation.
860 *
861 * @returns @c true if it's within the valid limit, @c false otherwise.
862 * @param pVCpu The cross context virtual CPU structure.
863 * @param uMsrCount The MSR area count to check.
864 */
865DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
866{
867 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
868 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
869 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
870 if (uMsrCount <= cMaxSupportedMsrs)
871 return true;
872 return false;
873}
874
875
876/**
877 * Flushes the current VMCS contents back to guest memory.
878 *
879 * @returns VBox status code.
880 * @param pVCpu The cross context virtual CPU structure.
881 */
882DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
883{
884 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
885 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
886 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
887 return rc;
888}
889
890
891/**
892 * Populates the current VMCS contents from guest memory.
893 *
894 * @returns VBox status code.
895 * @param pVCpu The cross context virtual CPU structure.
896 */
897DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
898{
899 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
900 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
901 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
902 return rc;
903}
904
905
906/**
907 * Gets the instruction diagnostic for segment base checks during VM-entry of a
908 * nested-guest.
909 *
910 * @param iSegReg The segment index (X86_SREG_XXX).
911 */
912static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
913{
914 switch (iSegReg)
915 {
916 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
917 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
918 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
919 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
920 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
921 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
922 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
923 }
924}
925
926
927/**
928 * Gets the instruction diagnostic for segment base checks during VM-entry of a
929 * nested-guest that is in Virtual-8086 mode.
930 *
931 * @param iSegReg The segment index (X86_SREG_XXX).
932 */
933static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
934{
935 switch (iSegReg)
936 {
937 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
938 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
939 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
940 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
941 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
942 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
943 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
944 }
945}
946
947
948/**
949 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
950 * nested-guest that is in Virtual-8086 mode.
951 *
952 * @param iSegReg The segment index (X86_SREG_XXX).
953 */
954static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
955{
956 switch (iSegReg)
957 {
958 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
959 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
960 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
961 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
962 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
963 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
964 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
965 }
966}
967
968
969/**
970 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
971 * nested-guest that is in Virtual-8086 mode.
972 *
973 * @param iSegReg The segment index (X86_SREG_XXX).
974 */
975static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
976{
977 switch (iSegReg)
978 {
979 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
980 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
981 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
982 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
983 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
984 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
985 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
986 }
987}
988
989
990/**
991 * Gets the instruction diagnostic for segment attributes reserved bits failure
992 * during VM-entry of a nested-guest.
993 *
994 * @param iSegReg The segment index (X86_SREG_XXX).
995 */
996static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
997{
998 switch (iSegReg)
999 {
1000 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1001 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1002 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1003 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1004 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1005 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1006 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1007 }
1008}
1009
1010
1011/**
1012 * Gets the instruction diagnostic for segment attributes descriptor-type
1013 * (code/segment or system) failure during VM-entry of a nested-guest.
1014 *
1015 * @param iSegReg The segment index (X86_SREG_XXX).
1016 */
1017static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1018{
1019 switch (iSegReg)
1020 {
1021 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1022 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1023 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1024 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1025 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1026 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1027 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1028 }
1029}
1030
1031
1032/**
1033 * Gets the instruction diagnostic for segment attributes descriptor-type
1034 * (code/segment or system) failure during VM-entry of a nested-guest.
1035 *
1036 * @param iSegReg The segment index (X86_SREG_XXX).
1037 */
1038static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1039{
1040 switch (iSegReg)
1041 {
1042 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1043 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1044 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1045 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1046 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1047 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1048 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1049 }
1050}
1051
1052
1053/**
1054 * Gets the instruction diagnostic for segment attribute granularity failure during
1055 * VM-entry of a nested-guest.
1056 *
1057 * @param iSegReg The segment index (X86_SREG_XXX).
1058 */
1059static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1060{
1061 switch (iSegReg)
1062 {
1063 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1064 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1065 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1066 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1067 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1068 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1069 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1070 }
1071}
1072
1073/**
1074 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1075 * VM-entry of a nested-guest.
1076 *
1077 * @param iSegReg The segment index (X86_SREG_XXX).
1078 */
1079static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1080{
1081 switch (iSegReg)
1082 {
1083 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1084 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1085 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1086 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1087 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1088 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1089 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1090 }
1091}
1092
1093
1094/**
1095 * Gets the instruction diagnostic for segment attribute type accessed failure
1096 * during VM-entry of a nested-guest.
1097 *
1098 * @param iSegReg The segment index (X86_SREG_XXX).
1099 */
1100static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1101{
1102 switch (iSegReg)
1103 {
1104 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1105 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1106 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1107 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1108 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1109 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1110 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1111 }
1112}
1113
1114
1115/**
1116 * Saves the guest control registers, debug registers and some MSRs are part of
1117 * VM-exit.
1118 *
1119 * @param pVCpu The cross context virtual CPU structure.
1120 */
1121static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1122{
1123 /*
1124 * Saves the guest control registers, debug registers and some MSRs.
1125 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1126 */
1127 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1128
1129 /* Save control registers. */
1130 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1131 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1132 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1133
1134 /* Save SYSENTER CS, ESP, EIP. */
1135 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1136 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1137 {
1138 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1139 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1140 }
1141 else
1142 {
1143 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1144 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1145 }
1146
1147 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1148 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1149 {
1150 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1151 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1152 }
1153
1154 /* Save PAT MSR. */
1155 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1156 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1157
1158 /* Save EFER MSR. */
1159 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1160 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1161
1162 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1163 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1164
1165 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1166}
1167
1168
1169/**
1170 * Saves the guest force-flags in preparation of entering the nested-guest.
1171 *
1172 * @param pVCpu The cross context virtual CPU structure.
1173 */
1174static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1175{
1176 /* We shouldn't be called multiple times during VM-entry. */
1177 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1178
1179 /* MTF should not be set outside VMX non-root mode. */
1180 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1181
1182 /*
1183 * Preserve the required force-flags.
1184 *
1185 * We cache and clear force-flags that would affect the execution of the
1186 * nested-guest. Cached flags are then restored while returning to the guest
1187 * if necessary.
1188 *
1189 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1190 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1191 * instruction. Interrupt inhibition for any nested-guest instruction
1192 * is supplied by the guest-interruptibility state VMCS field and will
1193 * be set up as part of loading the guest state.
1194 *
1195 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1196 * successful VM-entry (due to invalid guest-state) need to continue
1197 * blocking NMIs if it was in effect before VM-entry.
1198 *
1199 * - MTF need not be preserved as it's used only in VMX non-root mode and
1200 * is supplied through the VM-execution controls.
1201 *
1202 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1203 * we will be able to generate interrupts that may cause VM-exits for
1204 * the nested-guest.
1205 */
1206 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1207}
1208
1209
1210/**
1211 * Restores the guest force-flags in preparation of exiting the nested-guest.
1212 *
1213 * @param pVCpu The cross context virtual CPU structure.
1214 */
1215static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1216{
1217 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1218 {
1219 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1220 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1221 }
1222}
1223
1224
1225/**
1226 * Performs the VMX transition to/from VMX non-root mode.
1227 *
1228 * @param pVCpu The cross context virtual CPU structure.
1229*/
1230static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1231{
1232 /*
1233 * Inform PGM about paging mode changes.
1234 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1235 * see comment in iemMemPageTranslateAndCheckAccess().
1236 */
1237 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1238 true /* fForce */);
1239 AssertRCReturn(rc, rc);
1240
1241 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1242 IEMTlbInvalidateAll(pVCpu);
1243
1244 /* Inform CPUM (recompiler), can later be removed. */
1245 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1246
1247 /* Re-initialize IEM cache/state after the drastic mode switch. */
1248 iemReInitExec(pVCpu);
1249 return rc;
1250}
1251
1252
1253/**
1254 * Calculates the current VMX-preemption timer value.
1255 *
1256 * @returns The current VMX-preemption timer value.
1257 * @param pVCpu The cross context virtual CPU structure.
1258 */
1259static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1260{
1261 /*
1262 * Assume the following:
1263 * PreemptTimerShift = 5
1264 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1265 * EntryTick = 50000 (TSC at time of VM-entry)
1266 *
1267 * CurTick Delta PreemptTimerVal
1268 * ----------------------------------
1269 * 60000 10000 2
1270 * 80000 30000 1
1271 * 90000 40000 0 -> VM-exit.
1272 *
1273 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1274 * The saved VMX-preemption timer value is calculated as follows:
1275 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1276 * E.g.:
1277 * Delta = 10000
1278 * Tmp = 10000 / (2 * 10000) = 0.5
1279 * NewPt = 2 - 0.5 = 2
1280 * Delta = 30000
1281 * Tmp = 30000 / (2 * 10000) = 1.5
1282 * NewPt = 2 - 1.5 = 1
1283 * Delta = 40000
1284 * Tmp = 40000 / 20000 = 2
1285 * NewPt = 2 - 2 = 0
1286 */
1287 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1288 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1289 if (uVmcsPreemptVal > 0)
1290 {
1291 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1292 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1293 uint64_t const uDelta = uCurTick - uEntryTick;
1294 uint32_t const uPreemptTimer = uVmcsPreemptVal
1295 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1296 return uPreemptTimer;
1297 }
1298 return 0;
1299}
1300
1301
1302/**
1303 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1304 *
1305 * @param pVCpu The cross context virtual CPU structure.
1306 */
1307static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1308{
1309 /*
1310 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1311 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1312 */
1313 /* CS, SS, ES, DS, FS, GS. */
1314 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1315 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1316 {
1317 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1318 if (!pSelReg->Attr.n.u1Unusable)
1319 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1320 else
1321 {
1322 /*
1323 * For unusable segments the attributes are undefined except for CS and SS.
1324 * For the rest we don't bother preserving anything but the unusable bit.
1325 */
1326 switch (iSegReg)
1327 {
1328 case X86_SREG_CS:
1329 pVmcs->GuestCs = pSelReg->Sel;
1330 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1331 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1332 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1333 | X86DESCATTR_UNUSABLE);
1334 break;
1335
1336 case X86_SREG_SS:
1337 pVmcs->GuestSs = pSelReg->Sel;
1338 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1339 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1340 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1341 break;
1342
1343 case X86_SREG_DS:
1344 pVmcs->GuestDs = pSelReg->Sel;
1345 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1346 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1347 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1348 break;
1349
1350 case X86_SREG_ES:
1351 pVmcs->GuestEs = pSelReg->Sel;
1352 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1353 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1354 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1355 break;
1356
1357 case X86_SREG_FS:
1358 pVmcs->GuestFs = pSelReg->Sel;
1359 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1360 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1361 break;
1362
1363 case X86_SREG_GS:
1364 pVmcs->GuestGs = pSelReg->Sel;
1365 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1366 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1367 break;
1368 }
1369 }
1370 }
1371
1372 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1373 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1374 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1375 | X86DESCATTR_UNUSABLE;
1376 /* LDTR. */
1377 {
1378 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1379 pVmcs->GuestLdtr = pSelReg->Sel;
1380 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1381 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1382 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1383 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1384 }
1385
1386 /* TR. */
1387 {
1388 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1389 pVmcs->GuestTr = pSelReg->Sel;
1390 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1391 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1392 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1393 }
1394
1395 /* GDTR. */
1396 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1397 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1398
1399 /* IDTR. */
1400 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1401 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1402}
1403
1404
1405/**
1406 * Saves guest non-register state as part of VM-exit.
1407 *
1408 * @param pVCpu The cross context virtual CPU structure.
1409 * @param uExitReason The VM-exit reason.
1410 */
1411static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1412{
1413 /*
1414 * Save guest non-register state.
1415 * See Intel spec. 27.3.4 "Saving Non-Register State".
1416 */
1417 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1418
1419 /*
1420 * Activity state.
1421 * Most VM-exits will occur in the active state. However, if the first instruction
1422 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1423 * the VM-exit will be from the HLT activity state.
1424 *
1425 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1426 */
1427 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1428 * not? */
1429 EMSTATE const enmActivityState = EMGetState(pVCpu);
1430 switch (enmActivityState)
1431 {
1432 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1433 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1434 }
1435
1436 /*
1437 * Interruptibility-state.
1438 */
1439 /* NMI. */
1440 pVmcs->u32GuestIntrState = 0;
1441 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1442 {
1443 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1444 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1445 }
1446 else
1447 {
1448 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1449 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1450 }
1451
1452 /* Blocking-by-STI. */
1453 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1454 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1455 {
1456 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1457 * currently. */
1458 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1459 }
1460 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1461
1462 /*
1463 * Pending debug exceptions.
1464 *
1465 * For VM-exits where it is not applicable, we can safely zero out the field.
1466 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1467 */
1468 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1469 && uExitReason != VMX_EXIT_SMI
1470 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1471 && !VMXIsVmexitTrapLike(uExitReason))
1472 {
1473 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1474 * block-by-MovSS is in effect. */
1475 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1476 }
1477
1478 /*
1479 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1480 *
1481 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1482 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1483 */
1484 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1485 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1486 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1487
1488 /*
1489 * PAE PDPTEs.
1490 *
1491 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1492 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1493 * we zero them for consistency.
1494 */
1495 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1496 {
1497 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1498 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1499 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1500 {
1501 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1502 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1503 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1504 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1505 }
1506 else
1507 {
1508 pVmcs->u64GuestPdpte0.u = 0;
1509 pVmcs->u64GuestPdpte1.u = 0;
1510 pVmcs->u64GuestPdpte2.u = 0;
1511 pVmcs->u64GuestPdpte3.u = 0;
1512 }
1513
1514 /* Clear PGM's copy of the EPT pointer for added safety. */
1515 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1516 }
1517 else
1518 {
1519 pVmcs->u64GuestPdpte0.u = 0;
1520 pVmcs->u64GuestPdpte1.u = 0;
1521 pVmcs->u64GuestPdpte2.u = 0;
1522 pVmcs->u64GuestPdpte3.u = 0;
1523 }
1524}
1525
1526
1527/**
1528 * Saves the guest-state as part of VM-exit.
1529 *
1530 * @returns VBox status code.
1531 * @param pVCpu The cross context virtual CPU structure.
1532 * @param uExitReason The VM-exit reason.
1533 */
1534static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1535{
1536 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1537 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1538
1539 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1540 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1541 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1542
1543 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1544}
1545
1546
1547/**
1548 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1549 *
1550 * @returns VBox status code.
1551 * @param pVCpu The cross context virtual CPU structure.
1552 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1553 */
1554static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1555{
1556 /*
1557 * Save guest MSRs.
1558 * See Intel spec. 27.4 "Saving MSRs".
1559 */
1560 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1561 const char * const pszFailure = "VMX-abort";
1562
1563 /*
1564 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1565 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1566 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1567 */
1568 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1569 if (!cMsrs)
1570 return VINF_SUCCESS;
1571
1572 /*
1573 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1574 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1575 * implementation causes a VMX-abort followed by a triple-fault.
1576 */
1577 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1578 if (fIsMsrCountValid)
1579 { /* likely */ }
1580 else
1581 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1582
1583 /*
1584 * Optimization if the nested hypervisor is using the same guest-physical page for both
1585 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1586 */
1587 PVMXAUTOMSR pMsrArea;
1588 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1589 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1590 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1591 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1592 else
1593 {
1594 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1595 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1596 if (RT_SUCCESS(rc))
1597 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1598 else
1599 {
1600 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1601 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1602 }
1603 }
1604
1605 /*
1606 * Update VM-exit MSR store area.
1607 */
1608 PVMXAUTOMSR pMsr = pMsrArea;
1609 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1610 {
1611 if ( !pMsr->u32Reserved
1612 && pMsr->u32Msr != MSR_IA32_SMBASE
1613 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1614 {
1615 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1616 if (rcStrict == VINF_SUCCESS)
1617 continue;
1618
1619 /*
1620 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1621 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1622 * recording the MSR index in the auxiliary info. field and indicated further by our
1623 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1624 * if possible, or come up with a better, generic solution.
1625 */
1626 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1627 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1628 ? kVmxVDiag_Vmexit_MsrStoreRing3
1629 : kVmxVDiag_Vmexit_MsrStore;
1630 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1631 }
1632 else
1633 {
1634 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1635 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1636 }
1637 }
1638
1639 /*
1640 * Commit the VM-exit MSR store are to guest memory.
1641 */
1642 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1643 if (RT_SUCCESS(rc))
1644 return VINF_SUCCESS;
1645
1646 NOREF(uExitReason);
1647 NOREF(pszFailure);
1648
1649 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1650 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1651}
1652
1653
1654/**
1655 * Performs a VMX abort (due to an fatal error during VM-exit).
1656 *
1657 * @returns Strict VBox status code.
1658 * @param pVCpu The cross context virtual CPU structure.
1659 * @param enmAbort The VMX abort reason.
1660 */
1661static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1662{
1663 /*
1664 * Perform the VMX abort.
1665 * See Intel spec. 27.7 "VMX Aborts".
1666 */
1667 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1668
1669 /* We don't support SMX yet. */
1670 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1671 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1672 {
1673 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1674 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1675 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1676 }
1677
1678 return VINF_EM_TRIPLE_FAULT;
1679}
1680
1681
1682/**
1683 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1684 *
1685 * @param pVCpu The cross context virtual CPU structure.
1686 */
1687static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1688{
1689 /*
1690 * Load host control registers, debug registers and MSRs.
1691 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1692 */
1693 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1694 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1695
1696 /* CR0. */
1697 {
1698 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1699 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu);
1700 uint64_t const uCr0Mb0 = VMX_V_CR0_FIXED1;
1701 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1702 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1703 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1704 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1705
1706 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1707 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1708 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1709 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1710 }
1711
1712 /* CR4. */
1713 {
1714 /* CR4 fixed bits are not modified. */
1715 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1716 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1717 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1718 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1719 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1720 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1721 if (fHostInLongMode)
1722 uValidHostCr4 |= X86_CR4_PAE;
1723 else
1724 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1725
1726 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1727 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1728 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1729 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1730 }
1731
1732 /* CR3 (host value validated while checking host-state during VM-entry). */
1733 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1734
1735 /* DR7. */
1736 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1737
1738 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1739
1740 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1741 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1742 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1743 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1744
1745 /* FS, GS bases are loaded later while we load host segment registers. */
1746
1747 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1748 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1749 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1750 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1751 {
1752 if (fHostInLongMode)
1753 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1754 else
1755 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1756 }
1757
1758 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1759
1760 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1761 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1762 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1763
1764 /* We don't support IA32_BNDCFGS MSR yet. */
1765}
1766
1767
1768/**
1769 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1770 *
1771 * @param pVCpu The cross context virtual CPU structure.
1772 */
1773static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1774{
1775 /*
1776 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1777 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1778 *
1779 * Warning! Be careful to not touch fields that are reserved by VT-x,
1780 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1781 */
1782 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1783 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1784
1785 /* CS, SS, ES, DS, FS, GS. */
1786 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1787 {
1788 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1789 bool const fUnusable = RT_BOOL(HostSel == 0);
1790 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1791
1792 /* Selector. */
1793 pSelReg->Sel = HostSel;
1794 pSelReg->ValidSel = HostSel;
1795 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1796
1797 /* Limit. */
1798 pSelReg->u32Limit = 0xffffffff;
1799
1800 /* Base. */
1801 pSelReg->u64Base = 0;
1802
1803 /* Attributes. */
1804 if (iSegReg == X86_SREG_CS)
1805 {
1806 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1807 pSelReg->Attr.n.u1DescType = 1;
1808 pSelReg->Attr.n.u2Dpl = 0;
1809 pSelReg->Attr.n.u1Present = 1;
1810 pSelReg->Attr.n.u1Long = fHostInLongMode;
1811 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1812 pSelReg->Attr.n.u1Granularity = 1;
1813 Assert(!pSelReg->Attr.n.u1Unusable);
1814 Assert(!fUnusable);
1815 }
1816 else
1817 {
1818 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1819 pSelReg->Attr.n.u1DescType = 1;
1820 pSelReg->Attr.n.u2Dpl = 0;
1821 pSelReg->Attr.n.u1Present = 1;
1822 pSelReg->Attr.n.u1DefBig = 1;
1823 pSelReg->Attr.n.u1Granularity = 1;
1824 pSelReg->Attr.n.u1Unusable = fUnusable;
1825 }
1826 }
1827
1828 /* FS base. */
1829 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1830 || fHostInLongMode)
1831 {
1832 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1833 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1834 }
1835
1836 /* GS base. */
1837 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1838 || fHostInLongMode)
1839 {
1840 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1841 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1842 }
1843
1844 /* TR. */
1845 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1846 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1847 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1848 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1849 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1850 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1851 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1852 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1853 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1854 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1855 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1856 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1857 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1858
1859 /* LDTR (Warning! do not touch the base and limits here). */
1860 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1861 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1862 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1863 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1864
1865 /* GDTR. */
1866 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1867 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1868 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1869
1870 /* IDTR.*/
1871 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1872 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1873 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1874}
1875
1876
1877/**
1878 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1879 *
1880 * @returns VBox status code.
1881 * @param pVCpu The cross context virtual CPU structure.
1882 * @param uExitReason The VMX instruction name (for logging purposes).
1883 */
1884static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1885{
1886 /*
1887 * Load host MSRs.
1888 * See Intel spec. 27.6 "Loading MSRs".
1889 */
1890 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1891 const char * const pszFailure = "VMX-abort";
1892
1893 /*
1894 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1895 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1896 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1897 */
1898 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1899 if (!cMsrs)
1900 return VINF_SUCCESS;
1901
1902 /*
1903 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1904 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1905 * implementation causes a VMX-abort followed by a triple-fault.
1906 */
1907 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1908 if (fIsMsrCountValid)
1909 { /* likely */ }
1910 else
1911 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1912
1913 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1914 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1915 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1916 if (RT_SUCCESS(rc))
1917 {
1918 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1919 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1920 {
1921 if ( !pMsr->u32Reserved
1922 && pMsr->u32Msr != MSR_K8_FS_BASE
1923 && pMsr->u32Msr != MSR_K8_GS_BASE
1924 && pMsr->u32Msr != MSR_K6_EFER
1925 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1926 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1927 {
1928 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1929 if (rcStrict == VINF_SUCCESS)
1930 continue;
1931
1932 /*
1933 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1934 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1935 * recording the MSR index in the auxiliary info. field and indicated further by our
1936 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1937 * if possible, or come up with a better, generic solution.
1938 */
1939 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1940 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1941 ? kVmxVDiag_Vmexit_MsrLoadRing3
1942 : kVmxVDiag_Vmexit_MsrLoad;
1943 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1944 }
1945 else
1946 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1947 }
1948 }
1949 else
1950 {
1951 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1952 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1953 }
1954
1955 NOREF(uExitReason);
1956 NOREF(pszFailure);
1957 return VINF_SUCCESS;
1958}
1959
1960
1961/**
1962 * Loads the host state as part of VM-exit.
1963 *
1964 * @returns Strict VBox status code.
1965 * @param pVCpu The cross context virtual CPU structure.
1966 * @param uExitReason The VM-exit reason (for logging purposes).
1967 */
1968static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1969{
1970 /*
1971 * Load host state.
1972 * See Intel spec. 27.5 "Loading Host State".
1973 */
1974 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1975 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1976
1977 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1978 if ( CPUMIsGuestInLongMode(pVCpu)
1979 && !fHostInLongMode)
1980 {
1981 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
1982 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
1983 }
1984
1985 /*
1986 * Check host PAE PDPTEs prior to loading the host state.
1987 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1988 */
1989 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
1990 && !fHostInLongMode
1991 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1992 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
1993 {
1994 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
1995 if (RT_SUCCESS(rc))
1996 { /* likely*/ }
1997 else
1998 {
1999 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2000 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2001 }
2002 }
2003
2004 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2005 iemVmxVmexitLoadHostSegRegs(pVCpu);
2006
2007 /*
2008 * Load host RIP, RSP and RFLAGS.
2009 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2010 */
2011 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2012 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2013 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2014
2015 /* Clear address range monitoring. */
2016 EMMonitorWaitClear(pVCpu);
2017
2018 /* Perform the VMX transition (PGM updates). */
2019 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2020 if (rcStrict == VINF_SUCCESS)
2021 { /* likely */ }
2022 else if (RT_SUCCESS(rcStrict))
2023 {
2024 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2025 uExitReason));
2026 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2027 }
2028 else
2029 {
2030 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2031 return VBOXSTRICTRC_VAL(rcStrict);
2032 }
2033
2034 Assert(rcStrict == VINF_SUCCESS);
2035
2036 /* Load MSRs from the VM-exit auto-load MSR area. */
2037 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2038 if (RT_FAILURE(rc))
2039 {
2040 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2041 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2042 }
2043 return VINF_SUCCESS;
2044}
2045
2046
2047/**
2048 * Gets VM-exit instruction information along with any displacement for an
2049 * instruction VM-exit.
2050 *
2051 * @returns The VM-exit instruction information.
2052 * @param pVCpu The cross context virtual CPU structure.
2053 * @param uExitReason The VM-exit reason.
2054 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2055 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2056 * NULL.
2057 */
2058static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2059{
2060 RTGCPTR GCPtrDisp;
2061 VMXEXITINSTRINFO ExitInstrInfo;
2062 ExitInstrInfo.u = 0;
2063
2064 /*
2065 * Get and parse the ModR/M byte from our decoded opcodes.
2066 */
2067 uint8_t bRm;
2068 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2069 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2070 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2071 {
2072 /*
2073 * ModR/M indicates register addressing.
2074 *
2075 * The primary/secondary register operands are reported in the iReg1 or iReg2
2076 * fields depending on whether it is a read/write form.
2077 */
2078 uint8_t idxReg1;
2079 uint8_t idxReg2;
2080 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2081 {
2082 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2083 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2084 }
2085 else
2086 {
2087 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2088 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2089 }
2090 ExitInstrInfo.All.u2Scaling = 0;
2091 ExitInstrInfo.All.iReg1 = idxReg1;
2092 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2093 ExitInstrInfo.All.fIsRegOperand = 1;
2094 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2095 ExitInstrInfo.All.iSegReg = 0;
2096 ExitInstrInfo.All.iIdxReg = 0;
2097 ExitInstrInfo.All.fIdxRegInvalid = 1;
2098 ExitInstrInfo.All.iBaseReg = 0;
2099 ExitInstrInfo.All.fBaseRegInvalid = 1;
2100 ExitInstrInfo.All.iReg2 = idxReg2;
2101
2102 /* Displacement not applicable for register addressing. */
2103 GCPtrDisp = 0;
2104 }
2105 else
2106 {
2107 /*
2108 * ModR/M indicates memory addressing.
2109 */
2110 uint8_t uScale = 0;
2111 bool fBaseRegValid = false;
2112 bool fIdxRegValid = false;
2113 uint8_t iBaseReg = 0;
2114 uint8_t iIdxReg = 0;
2115 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2116 {
2117 /*
2118 * Parse the ModR/M, displacement for 16-bit addressing mode.
2119 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2120 */
2121 uint16_t u16Disp = 0;
2122 uint8_t const offDisp = offModRm + sizeof(bRm);
2123 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2124 {
2125 /* Displacement without any registers. */
2126 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2127 }
2128 else
2129 {
2130 /* Register (index and base). */
2131 switch (bRm & X86_MODRM_RM_MASK)
2132 {
2133 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2134 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2135 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2136 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2137 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2138 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2139 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2140 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2141 }
2142
2143 /* Register + displacement. */
2144 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2145 {
2146 case 0: break;
2147 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2148 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2149 default:
2150 {
2151 /* Register addressing, handled at the beginning. */
2152 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2153 break;
2154 }
2155 }
2156 }
2157
2158 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2159 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2160 }
2161 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2162 {
2163 /*
2164 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2165 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2166 */
2167 uint32_t u32Disp = 0;
2168 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2169 {
2170 /* Displacement without any registers. */
2171 uint8_t const offDisp = offModRm + sizeof(bRm);
2172 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2173 }
2174 else
2175 {
2176 /* Register (and perhaps scale, index and base). */
2177 uint8_t offDisp = offModRm + sizeof(bRm);
2178 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2179 if (iBaseReg == 4)
2180 {
2181 /* An SIB byte follows the ModR/M byte, parse it. */
2182 uint8_t bSib;
2183 uint8_t const offSib = offModRm + sizeof(bRm);
2184 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2185
2186 /* A displacement may follow SIB, update its offset. */
2187 offDisp += sizeof(bSib);
2188
2189 /* Get the scale. */
2190 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2191
2192 /* Get the index register. */
2193 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2194 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2195
2196 /* Get the base register. */
2197 iBaseReg = bSib & X86_SIB_BASE_MASK;
2198 fBaseRegValid = true;
2199 if (iBaseReg == 5)
2200 {
2201 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2202 {
2203 /* Mod is 0 implies a 32-bit displacement with no base. */
2204 fBaseRegValid = false;
2205 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2206 }
2207 else
2208 {
2209 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2210 iBaseReg = X86_GREG_xBP;
2211 }
2212 }
2213 }
2214
2215 /* Register + displacement. */
2216 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2217 {
2218 case 0: /* Handled above */ break;
2219 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2220 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2221 default:
2222 {
2223 /* Register addressing, handled at the beginning. */
2224 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2225 break;
2226 }
2227 }
2228 }
2229
2230 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2231 }
2232 else
2233 {
2234 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2235
2236 /*
2237 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2238 * See Intel instruction spec. 2.2 "IA-32e Mode".
2239 */
2240 uint64_t u64Disp = 0;
2241 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2242 if (fRipRelativeAddr)
2243 {
2244 /*
2245 * RIP-relative addressing mode.
2246 *
2247 * The displacement is 32-bit signed implying an offset range of +/-2G.
2248 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2249 */
2250 uint8_t const offDisp = offModRm + sizeof(bRm);
2251 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2252 }
2253 else
2254 {
2255 uint8_t offDisp = offModRm + sizeof(bRm);
2256
2257 /*
2258 * Register (and perhaps scale, index and base).
2259 *
2260 * REX.B extends the most-significant bit of the base register. However, REX.B
2261 * is ignored while determining whether an SIB follows the opcode. Hence, we
2262 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2263 *
2264 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2265 */
2266 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2267 if (iBaseReg == 4)
2268 {
2269 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2270 uint8_t bSib;
2271 uint8_t const offSib = offModRm + sizeof(bRm);
2272 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2273
2274 /* Displacement may follow SIB, update its offset. */
2275 offDisp += sizeof(bSib);
2276
2277 /* Get the scale. */
2278 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2279
2280 /* Get the index. */
2281 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2282 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2283
2284 /* Get the base. */
2285 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2286 fBaseRegValid = true;
2287 if (iBaseReg == 5)
2288 {
2289 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2290 {
2291 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2292 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2293 }
2294 else
2295 {
2296 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2297 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2298 }
2299 }
2300 }
2301 iBaseReg |= pVCpu->iem.s.uRexB;
2302
2303 /* Register + displacement. */
2304 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2305 {
2306 case 0: /* Handled above */ break;
2307 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2308 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2309 default:
2310 {
2311 /* Register addressing, handled at the beginning. */
2312 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2313 break;
2314 }
2315 }
2316 }
2317
2318 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2319 }
2320
2321 /*
2322 * The primary or secondary register operand is reported in iReg2 depending
2323 * on whether the primary operand is in read/write form.
2324 */
2325 uint8_t idxReg2;
2326 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2327 {
2328 idxReg2 = bRm & X86_MODRM_RM_MASK;
2329 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2330 idxReg2 |= pVCpu->iem.s.uRexB;
2331 }
2332 else
2333 {
2334 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2335 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2336 idxReg2 |= pVCpu->iem.s.uRexReg;
2337 }
2338 ExitInstrInfo.All.u2Scaling = uScale;
2339 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2340 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2341 ExitInstrInfo.All.fIsRegOperand = 0;
2342 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2343 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2344 ExitInstrInfo.All.iIdxReg = iIdxReg;
2345 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2346 ExitInstrInfo.All.iBaseReg = iBaseReg;
2347 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2348 ExitInstrInfo.All.iReg2 = idxReg2;
2349 }
2350
2351 /*
2352 * Handle exceptions to the norm for certain instructions.
2353 * (e.g. some instructions convey an instruction identity in place of iReg2).
2354 */
2355 switch (uExitReason)
2356 {
2357 case VMX_EXIT_GDTR_IDTR_ACCESS:
2358 {
2359 Assert(VMXINSTRID_IS_VALID(uInstrId));
2360 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2361 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2362 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2363 break;
2364 }
2365
2366 case VMX_EXIT_LDTR_TR_ACCESS:
2367 {
2368 Assert(VMXINSTRID_IS_VALID(uInstrId));
2369 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2370 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2371 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2372 break;
2373 }
2374
2375 case VMX_EXIT_RDRAND:
2376 case VMX_EXIT_RDSEED:
2377 {
2378 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2379 break;
2380 }
2381 }
2382
2383 /* Update displacement and return the constructed VM-exit instruction information field. */
2384 if (pGCPtrDisp)
2385 *pGCPtrDisp = GCPtrDisp;
2386
2387 return ExitInstrInfo.u;
2388}
2389
2390
2391/**
2392 * VMX VM-exit handler.
2393 *
2394 * @returns Strict VBox status code.
2395 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2396 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2397 * triple-fault.
2398 *
2399 * @param pVCpu The cross context virtual CPU structure.
2400 * @param uExitReason The VM-exit reason.
2401 * @param u64ExitQual The Exit qualification.
2402 *
2403 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2404 * called. Failures during VM-entry can cause VM-exits as well, so we
2405 * -cannot- assert we're in VMX non-root mode here.
2406 */
2407VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2408{
2409# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2410 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2411 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2412 return VERR_IEM_IPE_7;
2413# else
2414 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2415
2416 /*
2417 * Import all the guest-CPU state.
2418 *
2419 * HM on returning to guest execution would have to reset up a whole lot of state
2420 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2421 * the state and flag reloading the entire state on re-entry. So import the entire
2422 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2423 */
2424 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2425
2426 /*
2427 * Ensure VM-entry interruption information valid bit is cleared.
2428 *
2429 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2430 * by invalid-guest state or machine-check exceptions) also clear this bit.
2431 *
2432 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2433 */
2434 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2435 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2436
2437 /*
2438 * Update the VM-exit reason and Exit qualification.
2439 * Other VMCS read-only data fields are expected to be updated by the caller already.
2440 */
2441 pVmcs->u32RoExitReason = uExitReason;
2442 pVmcs->u64RoExitQual.u = u64ExitQual;
2443
2444 LogFlow(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2445 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2446 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2447
2448 /*
2449 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2450 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2451 */
2452 {
2453 uint8_t uVector;
2454 uint32_t fFlags;
2455 uint32_t uErrCode;
2456 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2457 if (fInEventDelivery)
2458 {
2459 /*
2460 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2461 * caused by a triple-fault or the original event results in a double-fault that
2462 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2463 * original event information into the IDT-vectoring information fields.
2464 *
2465 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2466 */
2467 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2468 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2469 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2470 {
2471 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2472 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2473 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2474 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2475 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2476 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2477 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2478 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2479 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2480 pVCpu->cpum.GstCtx.cr2));
2481 }
2482 }
2483 }
2484
2485 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2486 Assert(pVmcs->u64RoIoRcx.u == 0);
2487 Assert(pVmcs->u64RoIoRsi.u == 0);
2488 Assert(pVmcs->u64RoIoRdi.u == 0);
2489 Assert(pVmcs->u64RoIoRip.u == 0);
2490
2491 /*
2492 * Save the guest state back into the VMCS.
2493 * We only need to save the state when the VM-entry was successful.
2494 */
2495 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2496 if (!fVmentryFailed)
2497 {
2498 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2499 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2500 {
2501 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2502 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2503 }
2504
2505 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2506 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2507
2508 /*
2509 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2510 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2511 *
2512 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2513 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2514 * as guest-CPU state would not been modified. Hence for now, we do this only when
2515 * the VM-entry succeeded.
2516 */
2517 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2518 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2519 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2520 {
2521 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2522 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2523 else
2524 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2525 }
2526
2527 /*
2528 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2529 * occurs in enclave mode/SMM which we don't support yet.
2530 *
2531 * If we ever add support for it, we can pass just the lower bits to the functions
2532 * below, till then an assert should suffice.
2533 */
2534 Assert(!RT_HI_U16(uExitReason));
2535
2536 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2537 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2538 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2539 if (RT_SUCCESS(rc))
2540 { /* likely */ }
2541 else
2542 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2543
2544 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2545 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2546 }
2547 else
2548 {
2549 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2550 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2551 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2552 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2553 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2554 }
2555
2556 /*
2557 * Stop any running VMX-preemption timer if necessary.
2558 */
2559 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2560 CPUMStopGuestVmxPremptTimer(pVCpu);
2561
2562 /*
2563 * Clear any pending VMX nested-guest force-flags.
2564 * These force-flags have no effect on (outer) guest execution and will
2565 * be re-evaluated and setup on the next nested-guest VM-entry.
2566 */
2567 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2568
2569 /*
2570 * We're no longer in nested-guest execution mode.
2571 *
2572 * It is important to do this prior to loading the host state because
2573 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2574 * second-level address translation while switching to host CR3.
2575 */
2576 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2577
2578 /* Restore the host (outer guest) state. */
2579 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2580 if (RT_SUCCESS(rcStrict))
2581 {
2582 Assert(rcStrict == VINF_SUCCESS);
2583 rcStrict = VINF_VMX_VMEXIT;
2584 }
2585 else
2586 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2587
2588 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2589 {
2590 /* Notify HM that the current VMCS fields have been modified. */
2591 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2592
2593 /* Notify HM that we've completed the VM-exit. */
2594 HMNotifyVmxNstGstVmexit(pVCpu);
2595 }
2596
2597# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2598 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2599 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2600 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2601 if (rcSched != VINF_SUCCESS)
2602 iemSetPassUpStatus(pVCpu, rcSched);
2603# endif
2604 return rcStrict;
2605# endif
2606}
2607
2608
2609/**
2610 * VMX VM-exit handler for VM-exits due to instruction execution.
2611 *
2612 * This is intended for instructions where the caller provides all the relevant
2613 * VM-exit information.
2614 *
2615 * @returns Strict VBox status code.
2616 * @param pVCpu The cross context virtual CPU structure.
2617 * @param pExitInfo Pointer to the VM-exit information.
2618 */
2619static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2620{
2621 /*
2622 * For instructions where any of the following fields are not applicable:
2623 * - Exit qualification must be cleared.
2624 * - VM-exit instruction info. is undefined.
2625 * - Guest-linear address is undefined.
2626 * - Guest-physical address is undefined.
2627 *
2628 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2629 * instruction execution. For VM-exits that are not due to instruction execution this
2630 * field is undefined.
2631 *
2632 * In our implementation in IEM, all undefined fields are generally cleared. However,
2633 * if the caller supplies information (from say the physical CPU directly) it is
2634 * then possible that the undefined fields are not cleared.
2635 *
2636 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2637 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2638 */
2639 Assert(pExitInfo);
2640 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2641 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2642 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2643
2644 /* Update all the relevant fields from the VM-exit instruction information struct. */
2645 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2646 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2647 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2648 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2649
2650 /* Perform the VM-exit. */
2651 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2652}
2653
2654
2655/**
2656 * VMX VM-exit handler for VM-exits due to instruction execution.
2657 *
2658 * This is intended for instructions that only provide the VM-exit instruction
2659 * length.
2660 *
2661 * @param pVCpu The cross context virtual CPU structure.
2662 * @param uExitReason The VM-exit reason.
2663 * @param cbInstr The instruction length in bytes.
2664 */
2665VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2666{
2667 VMXVEXITINFO ExitInfo;
2668 RT_ZERO(ExitInfo);
2669 ExitInfo.uReason = uExitReason;
2670 ExitInfo.cbInstr = cbInstr;
2671
2672#ifdef VBOX_STRICT
2673 /*
2674 * To prevent us from shooting ourselves in the foot.
2675 * The follow instructions should convey more than just the instruction length.
2676 */
2677 switch (uExitReason)
2678 {
2679 case VMX_EXIT_INVEPT:
2680 case VMX_EXIT_INVPCID:
2681 case VMX_EXIT_INVVPID:
2682 case VMX_EXIT_LDTR_TR_ACCESS:
2683 case VMX_EXIT_GDTR_IDTR_ACCESS:
2684 case VMX_EXIT_VMCLEAR:
2685 case VMX_EXIT_VMPTRLD:
2686 case VMX_EXIT_VMPTRST:
2687 case VMX_EXIT_VMREAD:
2688 case VMX_EXIT_VMWRITE:
2689 case VMX_EXIT_VMXON:
2690 case VMX_EXIT_XRSTORS:
2691 case VMX_EXIT_XSAVES:
2692 case VMX_EXIT_RDRAND:
2693 case VMX_EXIT_RDSEED:
2694 case VMX_EXIT_IO_INSTR:
2695 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2696 break;
2697 }
2698#endif
2699
2700 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2701}
2702
2703
2704/**
2705 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2706 *
2707 * @returns Strict VBox status code.
2708 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2709 * @thread EMT(pVCpu)
2710 */
2711VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2712{
2713 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2714 Assert(!pVCpu->iem.s.cActiveMappings);
2715 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2716}
2717
2718
2719/**
2720 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2721 *
2722 * @returns Strict VBox status code.
2723 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2724 * @param uVector The SIPI vector.
2725 * @thread EMT(pVCpu)
2726 */
2727VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2728{
2729 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2730 Assert(!pVCpu->iem.s.cActiveMappings);
2731 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2732}
2733
2734
2735/**
2736 * Interface for HM and EM to emulate a VM-exit.
2737 *
2738 * If a specialized version of a VM-exit handler exists, that must be used instead.
2739 *
2740 * @returns Strict VBox status code.
2741 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2742 * @param uExitReason The VM-exit reason.
2743 * @param u64ExitQual The Exit qualification.
2744 * @thread EMT(pVCpu)
2745 */
2746VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2747{
2748 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2749 Assert(!pVCpu->iem.s.cActiveMappings);
2750 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2751}
2752
2753
2754/**
2755 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2756 *
2757 * This is meant to be used for those instructions that VMX provides additional
2758 * decoding information beyond just the instruction length!
2759 *
2760 * @returns Strict VBox status code.
2761 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2762 * @param pExitInfo Pointer to the VM-exit information.
2763 * @thread EMT(pVCpu)
2764 */
2765VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2766{
2767 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2768 Assert(!pVCpu->iem.s.cActiveMappings);
2769 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2770}
2771
2772
2773/**
2774 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2775 *
2776 * This is meant to be used for those instructions that VMX provides only the
2777 * instruction length.
2778 *
2779 * @returns Strict VBox status code.
2780 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2781 * @param pExitInfo Pointer to the VM-exit information.
2782 * @param cbInstr The instruction length in bytes.
2783 * @thread EMT(pVCpu)
2784 */
2785VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2786{
2787 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2788 Assert(!pVCpu->iem.s.cActiveMappings);
2789 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2790}
2791
2792
2793/**
2794 * VMX VM-exit handler for VM-exits due to instruction execution.
2795 *
2796 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2797 * instruction information and Exit qualification fields.
2798 *
2799 * @param pVCpu The cross context virtual CPU structure.
2800 * @param uExitReason The VM-exit reason.
2801 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2802 * @param cbInstr The instruction length in bytes.
2803 *
2804 * @remarks Do not use this for INS/OUTS instruction.
2805 */
2806VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2807{
2808 VMXVEXITINFO ExitInfo;
2809 RT_ZERO(ExitInfo);
2810 ExitInfo.uReason = uExitReason;
2811 ExitInfo.cbInstr = cbInstr;
2812
2813 /*
2814 * Update the Exit qualification field with displacement bytes.
2815 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2816 */
2817 switch (uExitReason)
2818 {
2819 case VMX_EXIT_INVEPT:
2820 case VMX_EXIT_INVPCID:
2821 case VMX_EXIT_INVVPID:
2822 case VMX_EXIT_LDTR_TR_ACCESS:
2823 case VMX_EXIT_GDTR_IDTR_ACCESS:
2824 case VMX_EXIT_VMCLEAR:
2825 case VMX_EXIT_VMPTRLD:
2826 case VMX_EXIT_VMPTRST:
2827 case VMX_EXIT_VMREAD:
2828 case VMX_EXIT_VMWRITE:
2829 case VMX_EXIT_VMXON:
2830 case VMX_EXIT_XRSTORS:
2831 case VMX_EXIT_XSAVES:
2832 case VMX_EXIT_RDRAND:
2833 case VMX_EXIT_RDSEED:
2834 {
2835 /* Construct the VM-exit instruction information. */
2836 RTGCPTR GCPtrDisp;
2837 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2838
2839 /* Update the VM-exit instruction information. */
2840 ExitInfo.InstrInfo.u = uInstrInfo;
2841
2842 /* Update the Exit qualification. */
2843 ExitInfo.u64Qual = GCPtrDisp;
2844 break;
2845 }
2846
2847 default:
2848 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2849 break;
2850 }
2851
2852 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2853}
2854
2855
2856/**
2857 * VMX VM-exit handler for VM-exits due to INVLPG.
2858 *
2859 * @returns Strict VBox status code.
2860 * @param pVCpu The cross context virtual CPU structure.
2861 * @param GCPtrPage The guest-linear address of the page being invalidated.
2862 * @param cbInstr The instruction length in bytes.
2863 */
2864VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2865{
2866 VMXVEXITINFO ExitInfo;
2867 RT_ZERO(ExitInfo);
2868 ExitInfo.uReason = VMX_EXIT_INVLPG;
2869 ExitInfo.cbInstr = cbInstr;
2870 ExitInfo.u64Qual = GCPtrPage;
2871 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2872
2873 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2874}
2875
2876
2877/**
2878 * VMX VM-exit handler for VM-exits due to LMSW.
2879 *
2880 * @returns Strict VBox status code.
2881 * @param pVCpu The cross context virtual CPU structure.
2882 * @param uGuestCr0 The current guest CR0.
2883 * @param pu16NewMsw The machine-status word specified in LMSW's source
2884 * operand. This will be updated depending on the VMX
2885 * guest/host CR0 mask if LMSW is not intercepted.
2886 * @param GCPtrEffDst The guest-linear address of the source operand in case
2887 * of a memory operand. For register operand, pass
2888 * NIL_RTGCPTR.
2889 * @param cbInstr The instruction length in bytes.
2890 */
2891VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2892 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2893{
2894 Assert(pu16NewMsw);
2895
2896 uint16_t const uNewMsw = *pu16NewMsw;
2897 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2898 {
2899 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2900
2901 VMXVEXITINFO ExitInfo;
2902 RT_ZERO(ExitInfo);
2903 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2904 ExitInfo.cbInstr = cbInstr;
2905
2906 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2907 if (fMemOperand)
2908 {
2909 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2910 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2911 }
2912
2913 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2914 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2915 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2916 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2917
2918 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2919 }
2920
2921 /*
2922 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2923 * CR0 guest/host mask must be left unmodified.
2924 *
2925 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2926 */
2927 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2928 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2929 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2930
2931 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2932}
2933
2934
2935/**
2936 * VMX VM-exit handler for VM-exits due to CLTS.
2937 *
2938 * @returns Strict VBox status code.
2939 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2940 * VM-exit but must not modify the guest CR0.TS bit.
2941 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2942 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2943 * CR0 fixed bits in VMX operation).
2944 * @param pVCpu The cross context virtual CPU structure.
2945 * @param cbInstr The instruction length in bytes.
2946 */
2947VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2948{
2949 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2950 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2951
2952 /*
2953 * If CR0.TS is owned by the host:
2954 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2955 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2956 * CLTS instruction completes without clearing CR0.TS.
2957 *
2958 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2959 */
2960 if (fGstHostMask & X86_CR0_TS)
2961 {
2962 if (fReadShadow & X86_CR0_TS)
2963 {
2964 Log2(("clts: Guest intercept -> VM-exit\n"));
2965
2966 VMXVEXITINFO ExitInfo;
2967 RT_ZERO(ExitInfo);
2968 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2969 ExitInfo.cbInstr = cbInstr;
2970 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2971 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2972 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2973 }
2974
2975 return VINF_VMX_MODIFIES_BEHAVIOR;
2976 }
2977
2978 /*
2979 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2980 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2981 */
2982 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2983}
2984
2985
2986/**
2987 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2988 * (CR0/CR4 write).
2989 *
2990 * @returns Strict VBox status code.
2991 * @param pVCpu The cross context virtual CPU structure.
2992 * @param iCrReg The control register (either CR0 or CR4).
2993 * @param uGuestCrX The current guest CR0/CR4.
2994 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2995 * VM-exit is caused.
2996 * @param iGReg The general register from which the CR0/CR4 value is being
2997 * loaded.
2998 * @param cbInstr The instruction length in bytes.
2999 */
3000VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3001 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3002{
3003 Assert(puNewCrX);
3004 Assert(iCrReg == 0 || iCrReg == 4);
3005 Assert(iGReg < X86_GREG_COUNT);
3006
3007 uint64_t const uNewCrX = *puNewCrX;
3008 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3009 {
3010 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3011
3012 VMXVEXITINFO ExitInfo;
3013 RT_ZERO(ExitInfo);
3014 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3015 ExitInfo.cbInstr = cbInstr;
3016 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3017 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3018 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3019 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3020 }
3021
3022 /*
3023 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3024 * must not be modified the instruction.
3025 *
3026 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3027 */
3028 uint64_t uGuestCrX;
3029 uint64_t fGstHostMask;
3030 if (iCrReg == 0)
3031 {
3032 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3033 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3034 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3035 }
3036 else
3037 {
3038 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3039 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3040 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3041 }
3042
3043 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3044 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3045}
3046
3047
3048/**
3049 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3050 *
3051 * @returns VBox strict status code.
3052 * @param pVCpu The cross context virtual CPU structure.
3053 * @param iGReg The general register to which the CR3 value is being stored.
3054 * @param cbInstr The instruction length in bytes.
3055 */
3056VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3057{
3058 Assert(iGReg < X86_GREG_COUNT);
3059 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3060
3061 /*
3062 * If the CR3-store exiting control is set, we must cause a VM-exit.
3063 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3064 */
3065 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3066 {
3067 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3068
3069 VMXVEXITINFO ExitInfo;
3070 RT_ZERO(ExitInfo);
3071 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3072 ExitInfo.cbInstr = cbInstr;
3073 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3074 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3075 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3076 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3077 }
3078
3079 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3080}
3081
3082
3083/**
3084 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3085 *
3086 * @returns VBox strict status code.
3087 * @param pVCpu The cross context virtual CPU structure.
3088 * @param uNewCr3 The new CR3 value.
3089 * @param iGReg The general register from which the CR3 value is being
3090 * loaded.
3091 * @param cbInstr The instruction length in bytes.
3092 */
3093VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3094{
3095 Assert(iGReg < X86_GREG_COUNT);
3096
3097 /*
3098 * If the CR3-load exiting control is set and the new CR3 value does not
3099 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3100 *
3101 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3102 */
3103 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3104 {
3105 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3106
3107 VMXVEXITINFO ExitInfo;
3108 RT_ZERO(ExitInfo);
3109 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3110 ExitInfo.cbInstr = cbInstr;
3111 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3112 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3113 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3114 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3115 }
3116
3117 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3118}
3119
3120
3121/**
3122 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3123 *
3124 * @returns VBox strict status code.
3125 * @param pVCpu The cross context virtual CPU structure.
3126 * @param iGReg The general register to which the CR8 value is being stored.
3127 * @param cbInstr The instruction length in bytes.
3128 */
3129VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3130{
3131 Assert(iGReg < X86_GREG_COUNT);
3132
3133 /*
3134 * If the CR8-store exiting control is set, we must cause a VM-exit.
3135 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3136 */
3137 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3138 {
3139 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3140
3141 VMXVEXITINFO ExitInfo;
3142 RT_ZERO(ExitInfo);
3143 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3144 ExitInfo.cbInstr = cbInstr;
3145 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3146 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3147 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3148 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3149 }
3150
3151 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3152}
3153
3154
3155/**
3156 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3157 *
3158 * @returns VBox strict status code.
3159 * @param pVCpu The cross context virtual CPU structure.
3160 * @param iGReg The general register from which the CR8 value is being
3161 * loaded.
3162 * @param cbInstr The instruction length in bytes.
3163 */
3164VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3165{
3166 Assert(iGReg < X86_GREG_COUNT);
3167
3168 /*
3169 * If the CR8-load exiting control is set, we must cause a VM-exit.
3170 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3171 */
3172 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3173 {
3174 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3175
3176 VMXVEXITINFO ExitInfo;
3177 RT_ZERO(ExitInfo);
3178 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3179 ExitInfo.cbInstr = cbInstr;
3180 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3181 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3182 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3183 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3184 }
3185
3186 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3187}
3188
3189
3190/**
3191 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3192 * GReg,DRx' (DRx read).
3193 *
3194 * @returns VBox strict status code.
3195 * @param pVCpu The cross context virtual CPU structure.
3196 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3197 * VMXINSTRID_MOV_FROM_DRX).
3198 * @param iDrReg The debug register being accessed.
3199 * @param iGReg The general register to/from which the DRx value is being
3200 * store/loaded.
3201 * @param cbInstr The instruction length in bytes.
3202 */
3203VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3204 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3205{
3206 Assert(iDrReg <= 7);
3207 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3208 Assert(iGReg < X86_GREG_COUNT);
3209
3210 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3211 {
3212 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3213 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3214 VMXVEXITINFO ExitInfo;
3215 RT_ZERO(ExitInfo);
3216 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3217 ExitInfo.cbInstr = cbInstr;
3218 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3219 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3220 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3221 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3222 }
3223
3224 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3225}
3226
3227
3228/**
3229 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3230 *
3231 * @returns VBox strict status code.
3232 * @param pVCpu The cross context virtual CPU structure.
3233 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3234 * VMXINSTRID_IO_OUT).
3235 * @param u16Port The I/O port being accessed.
3236 * @param fImm Whether the I/O port was encoded using an immediate operand
3237 * or the implicit DX register.
3238 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3239 * @param cbInstr The instruction length in bytes.
3240 */
3241VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3242 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3243{
3244 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3245 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3246
3247 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3248 if (fIntercept)
3249 {
3250 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3251 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3252 VMXVEXITINFO ExitInfo;
3253 RT_ZERO(ExitInfo);
3254 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3255 ExitInfo.cbInstr = cbInstr;
3256 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3257 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3258 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3259 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3260 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3261 }
3262
3263 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3264}
3265
3266
3267/**
3268 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3269 *
3270 * @returns VBox strict status code.
3271 * @param pVCpu The cross context virtual CPU structure.
3272 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3273 * VMXINSTRID_IO_OUTS).
3274 * @param u16Port The I/O port being accessed.
3275 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3276 * @param fRep Whether the instruction has a REP prefix or not.
3277 * @param ExitInstrInfo The VM-exit instruction info. field.
3278 * @param cbInstr The instruction length in bytes.
3279 */
3280VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3281 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3282{
3283 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3284 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3285 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3286 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3287 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3288
3289 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3290 if (fIntercept)
3291 {
3292 /*
3293 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3294 */
3295 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3296 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3297 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3298 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3299 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3300
3301 uint32_t uDirection;
3302 uint64_t uGuestLinearAddr;
3303 if (uInstrId == VMXINSTRID_IO_INS)
3304 {
3305 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3306 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3307 }
3308 else
3309 {
3310 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3311 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3312 }
3313
3314 /*
3315 * If the segment is unusable, the guest-linear address in undefined.
3316 * We shall clear it for consistency.
3317 *
3318 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3319 */
3320 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3321 uGuestLinearAddr = 0;
3322
3323 VMXVEXITINFO ExitInfo;
3324 RT_ZERO(ExitInfo);
3325 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3326 ExitInfo.cbInstr = cbInstr;
3327 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3328 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3329 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3330 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3331 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3332 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3333 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3334 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3335 ExitInfo.InstrInfo = ExitInstrInfo;
3336 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3337 }
3338
3339 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3340}
3341
3342
3343/**
3344 * VMX VM-exit handler for VM-exits due to MWAIT.
3345 *
3346 * @returns VBox strict status code.
3347 * @param pVCpu The cross context virtual CPU structure.
3348 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3349 * @param cbInstr The instruction length in bytes.
3350 */
3351VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3352{
3353 VMXVEXITINFO ExitInfo;
3354 RT_ZERO(ExitInfo);
3355 ExitInfo.uReason = VMX_EXIT_MWAIT;
3356 ExitInfo.cbInstr = cbInstr;
3357 ExitInfo.u64Qual = fMonitorHwArmed;
3358 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3359}
3360
3361
3362/**
3363 * VMX VM-exit handler for VM-exits due to PAUSE.
3364 *
3365 * @returns VBox strict status code.
3366 * @param pVCpu The cross context virtual CPU structure.
3367 * @param cbInstr The instruction length in bytes.
3368 */
3369static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3370{
3371 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3372
3373 /*
3374 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3375 * "PAUSE-loop exiting" control.
3376 *
3377 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3378 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3379 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3380 * a VM-exit.
3381 *
3382 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3383 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3384 */
3385 bool fIntercept = false;
3386 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3387 fIntercept = true;
3388 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3389 && pVCpu->iem.s.uCpl == 0)
3390 {
3391 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3392
3393 /*
3394 * A previous-PAUSE-tick value of 0 is used to identify the first time
3395 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3396 * consider this to be the first execution of PAUSE in a loop according
3397 * to the Intel.
3398 *
3399 * All subsequent records for the previous-PAUSE-tick we ensure that it
3400 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3401 */
3402 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3403 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3404 uint64_t const uTick = TMCpuTickGet(pVCpu);
3405 uint32_t const uPleGap = pVmcs->u32PleGap;
3406 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3407 if ( *puPrevPauseTick == 0
3408 || uTick - *puPrevPauseTick > uPleGap)
3409 *puFirstPauseLoopTick = uTick;
3410 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3411 fIntercept = true;
3412
3413 *puPrevPauseTick = uTick | 1;
3414 }
3415
3416 if (fIntercept)
3417 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3418
3419 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3420}
3421
3422
3423/**
3424 * VMX VM-exit handler for VM-exits due to task switches.
3425 *
3426 * @returns VBox strict status code.
3427 * @param pVCpu The cross context virtual CPU structure.
3428 * @param enmTaskSwitch The cause of the task switch.
3429 * @param SelNewTss The selector of the new TSS.
3430 * @param cbInstr The instruction length in bytes.
3431 */
3432VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3433{
3434 /*
3435 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3436 *
3437 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3438 * instruction or delivery of the exception generated by one of these instructions
3439 * lead to a task switch through a task gate in the IDT, we need to provide the
3440 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3441 * leaves the VM-exit instruction length field undefined.
3442 *
3443 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3444 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3445 */
3446 Assert(cbInstr <= 15);
3447
3448 uint8_t uType;
3449 switch (enmTaskSwitch)
3450 {
3451 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3452 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3453 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3454 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3455 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3456 }
3457
3458 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3459 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3460 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3461 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3462}
3463
3464
3465/**
3466 * VMX VM-exit handler for trap-like VM-exits.
3467 *
3468 * @returns VBox strict status code.
3469 * @param pVCpu The cross context virtual CPU structure.
3470 * @param pExitInfo Pointer to the VM-exit information.
3471 * @param pExitEventInfo Pointer to the VM-exit event information.
3472 */
3473static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3474{
3475 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3476 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3477 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3478}
3479
3480
3481/**
3482 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3483 * Virtualized-EOI, TPR-below threshold).
3484 *
3485 * @returns Strict VBox status code.
3486 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3487 * @param pExitInfo Pointer to the VM-exit information.
3488 * @thread EMT(pVCpu)
3489 */
3490VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3491{
3492 Assert(pExitInfo);
3493 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3494 Assert(!pVCpu->iem.s.cActiveMappings);
3495 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3496}
3497
3498
3499/**
3500 * VMX VM-exit handler for VM-exits due to task switches.
3501 *
3502 * This is intended for task switches where the caller provides all the relevant
3503 * VM-exit information.
3504 *
3505 * @returns VBox strict status code.
3506 * @param pVCpu The cross context virtual CPU structure.
3507 * @param pExitInfo Pointer to the VM-exit information.
3508 * @param pExitEventInfo Pointer to the VM-exit event information.
3509 */
3510static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3511 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3512{
3513 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3514 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3515 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3516 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3517 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3518}
3519
3520
3521/**
3522 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3523 *
3524 * @returns Strict VBox status code.
3525 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3526 * @param pExitInfo Pointer to the VM-exit information.
3527 * @param pExitEventInfo Pointer to the VM-exit event information.
3528 * @thread EMT(pVCpu)
3529 */
3530VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3531{
3532 Assert(pExitInfo);
3533 Assert(pExitEventInfo);
3534 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3535 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3536 Assert(!pVCpu->iem.s.cActiveMappings);
3537 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3538}
3539
3540
3541/**
3542 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3543 *
3544 * @returns VBox strict status code.
3545 * @param pVCpu The cross context virtual CPU structure.
3546 */
3547VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3548{
3549 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3550 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3551
3552 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3553 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3554
3555 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3556 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3557 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3558
3559 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3560 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3561}
3562
3563
3564/**
3565 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3566 *
3567 * @returns Strict VBox status code.
3568 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3569 * @thread EMT(pVCpu)
3570 */
3571VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3572{
3573 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3574 Assert(!pVCpu->iem.s.cActiveMappings);
3575 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3576}
3577
3578
3579/**
3580 * VMX VM-exit handler for VM-exits due to external interrupts.
3581 *
3582 * @returns VBox strict status code.
3583 * @param pVCpu The cross context virtual CPU structure.
3584 * @param uVector The external interrupt vector (pass 0 if the interrupt
3585 * is still pending since we typically won't know the
3586 * vector).
3587 * @param fIntPending Whether the external interrupt is pending or
3588 * acknowledged in the interrupt controller.
3589 */
3590static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3591{
3592 Assert(!fIntPending || uVector == 0);
3593
3594 /* The VM-exit is subject to "External interrupt exiting" being set. */
3595 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3596 {
3597 if (fIntPending)
3598 {
3599 /*
3600 * If the interrupt is pending and we don't need to acknowledge the
3601 * interrupt on VM-exit, cause the VM-exit immediately.
3602 *
3603 * See Intel spec 25.2 "Other Causes Of VM Exits".
3604 */
3605 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3606 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3607
3608 /*
3609 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3610 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3611 * acknowledged that the interrupt has been consumed. Callers would have to call
3612 * us again after getting the vector (and ofc, with fIntPending with false).
3613 */
3614 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3615 }
3616
3617 /*
3618 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3619 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3620 * all set, we need to record the vector of the external interrupt in the
3621 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3622 *
3623 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3624 */
3625 uint32_t uExitIntInfo;
3626 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3627 {
3628 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3629 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3630 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3631 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3632 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3633 }
3634 else
3635 uExitIntInfo = 0;
3636 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3637
3638 /*
3639 * Cause the VM-exit whether or not the vector has been stored
3640 * in the VM-exit interruption-information field.
3641 */
3642 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3643 }
3644
3645 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3646}
3647
3648
3649/**
3650 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3651 *
3652 * @returns Strict VBox status code.
3653 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3654 * @param uVector The external interrupt vector (pass 0 if the external
3655 * interrupt is still pending).
3656 * @param fIntPending Whether the external interrupt is pending or
3657 * acknowdledged in the interrupt controller.
3658 * @thread EMT(pVCpu)
3659 */
3660VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3661{
3662 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3663 Assert(!pVCpu->iem.s.cActiveMappings);
3664 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3665}
3666
3667
3668/**
3669 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3670 * an event.
3671 *
3672 * @returns VBox strict status code.
3673 * @param pVCpu The cross context virtual CPU structure.
3674 */
3675VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3676{
3677 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3678 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3679 {
3680 /*
3681 * The NMI-unblocking due to IRET field need not be set for double faults.
3682 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3683 */
3684 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3685 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3686 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3687 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3688 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3689 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3690 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3691 }
3692
3693 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3694}
3695
3696
3697/**
3698 * VMX VM-exit handler for VM-exit due to delivery of an events.
3699 *
3700 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3701 * all the relevant VM-exit information.
3702 *
3703 * @returns VBox strict status code.
3704 * @param pVCpu The cross context virtual CPU structure.
3705 * @param pExitInfo Pointer to the VM-exit information.
3706 * @param pExitEventInfo Pointer to the VM-exit event information.
3707 */
3708static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3709{
3710 Assert(pExitInfo);
3711 Assert(pExitEventInfo);
3712 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3713 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3714
3715 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3716 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3717 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3718 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3719 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3720 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3721}
3722
3723
3724/**
3725 * Interface for HM and EM to emulate VM-exit due to NMIs.
3726 *
3727 * @returns Strict VBox status code.
3728 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3729 * @thread EMT(pVCpu)
3730 */
3731VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3732{
3733 VMXVEXITINFO ExitInfo;
3734 RT_ZERO(ExitInfo);
3735 ExitInfo.uReason = VMX_EXIT_XCPT_OR_NMI;
3736
3737 VMXVEXITEVENTINFO ExitEventInfo;
3738 RT_ZERO(ExitEventInfo);
3739 ExitEventInfo.uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3740 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI)
3741 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI);
3742
3743 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3744 Assert(!pVCpu->iem.s.cActiveMappings);
3745 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3746}
3747
3748
3749/**
3750 * Interface for HM and EM to emulate VM-exit due to exceptions.
3751 *
3752 * Exception includes NMIs, software exceptions (those generated by INT3 or
3753 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3754 *
3755 * @returns Strict VBox status code.
3756 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3757 * @param pExitInfo Pointer to the VM-exit information.
3758 * @param pExitEventInfo Pointer to the VM-exit event information.
3759 * @thread EMT(pVCpu)
3760 */
3761VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3762{
3763 Assert(pExitInfo);
3764 Assert(pExitEventInfo);
3765 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3766 Assert(!pVCpu->iem.s.cActiveMappings);
3767 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3768}
3769
3770
3771/**
3772 * VMX VM-exit handler for VM-exits due to delivery of an event.
3773 *
3774 * @returns VBox strict status code.
3775 * @param pVCpu The cross context virtual CPU structure.
3776 * @param uVector The interrupt / exception vector.
3777 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3778 * @param uErrCode The error code associated with the event.
3779 * @param uCr2 The CR2 value in case of a \#PF exception.
3780 * @param cbInstr The instruction length in bytes.
3781 */
3782VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3783 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3784{
3785 /*
3786 * If the event is being injected as part of VM-entry, it is -not- subject to event
3787 * intercepts in the nested-guest. However, secondary exceptions that occur during
3788 * injection of any event -are- subject to event interception.
3789 *
3790 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3791 */
3792 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3793 {
3794 /*
3795 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3796 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3797 *
3798 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3799 */
3800 if ( uVector == X86_XCPT_NMI
3801 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3802 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3803 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3804 else
3805 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3806
3807 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3808 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3809 }
3810
3811 /*
3812 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3813 * If not, the caller will continue delivery of the external interrupt as it would
3814 * normally. The interrupt is no longer pending in the interrupt controller at this
3815 * point.
3816 */
3817 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3818 {
3819 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3820 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3821 }
3822
3823 /*
3824 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3825 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3826 * interrupts.
3827 */
3828 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3829 bool fIntercept;
3830 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3831 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3832 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3833 else
3834 {
3835 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3836 fIntercept = false;
3837 }
3838
3839 /*
3840 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3841 * relevant VM-exit information and cause the VM-exit.
3842 */
3843 if (fIntercept)
3844 {
3845 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3846
3847 /* Construct the rest of the event related information fields and cause the VM-exit. */
3848 uint64_t u64ExitQual;
3849 if (uVector == X86_XCPT_PF)
3850 {
3851 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3852 u64ExitQual = uCr2;
3853 }
3854 else if (uVector == X86_XCPT_DB)
3855 {
3856 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3857 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3858 }
3859 else
3860 u64ExitQual = 0;
3861
3862 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3863 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3864 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3865 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3866 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3867 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3868 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3869 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3870 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3871 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3872
3873 /*
3874 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3875 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3876 * length.
3877 */
3878 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3879 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3880 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3881 else
3882 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3883
3884 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3885 }
3886
3887 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3888}
3889
3890
3891/**
3892 * VMX VM-exit handler for EPT misconfiguration.
3893 *
3894 * @param pVCpu The cross context virtual CPU structure.
3895 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3896 * This need not be page aligned (e.g. nested-guest in real
3897 * mode).
3898 */
3899static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3900{
3901 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3902 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3903}
3904
3905
3906/**
3907 * VMX VM-exit handler for EPT misconfiguration.
3908 *
3909 * This is intended for EPT misconfigurations where the caller provides all the
3910 * relevant VM-exit information.
3911 *
3912 * @param pVCpu The cross context virtual CPU structure.
3913 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3914 * This need not be page aligned (e.g. nested-guest in real
3915 * mode).
3916 * @param pExitEventInfo Pointer to the VM-exit event information.
3917 */
3918static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3919{
3920 Assert(pExitEventInfo);
3921 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3922 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3923 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3924 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3925 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3926}
3927
3928
3929/**
3930 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3931 *
3932 * @returns Strict VBox status code.
3933 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3934 * @param GCPhysAddr The nested-guest physical address causing the EPT
3935 * misconfiguration.
3936 * @param pExitEventInfo Pointer to the VM-exit event information.
3937 * @thread EMT(pVCpu)
3938 */
3939VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3940{
3941 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3942
3943 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3944 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3945 Assert(!pVCpu->iem.s.cActiveMappings);
3946 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3947}
3948
3949
3950/**
3951 * VMX VM-exit handler for EPT violation.
3952 *
3953 * @param pVCpu The cross context virtual CPU structure.
3954 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3955 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3956 * @param fEptAccess The EPT paging structure bits.
3957 * @param GCPhysAddr The physical address causing the EPT violation. This
3958 * need not be page aligned (e.g. nested-guest in real
3959 * mode).
3960 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3961 * EPT violation. If @c false, GCPtrAddr must be 0.
3962 * @param GCPtrAddr The linear address causing the EPT violation.
3963 * @param cbInstr The VM-exit instruction length.
3964 */
3965static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3966 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3967 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3968{
3969 /*
3970 * If the linear address isn't valid (can happen when loading PDPTEs
3971 * as part of MOV CR execution) the linear address field is undefined.
3972 * While we can leave it this way, it's preferrable to zero it for consistency.
3973 */
3974 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
3975
3976 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3977 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
3978
3979 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
3980 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
3981 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
3982 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3983 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
3984 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
3985 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3986 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3987 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3988 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3989 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
3990
3991 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3992 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3993 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3994 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3995 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3996 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3997 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
3998 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
3999 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4000
4001#ifdef VBOX_STRICT
4002 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4003 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4004 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4005 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4006 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4007 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4008#endif
4009
4010 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4011 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4012 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4013
4014 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4015}
4016
4017
4018/**
4019 * VMX VM-exit handler for EPT violation.
4020 *
4021 * This is intended for EPT violations where the caller provides all the
4022 * relevant VM-exit information.
4023 *
4024 * @returns VBox strict status code.
4025 * @param pVCpu The cross context virtual CPU structure.
4026 * @param pExitInfo Pointer to the VM-exit information.
4027 * @param pExitEventInfo Pointer to the VM-exit event information.
4028 */
4029static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4030 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4031{
4032 Assert(pExitInfo);
4033 Assert(pExitEventInfo);
4034 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4035 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4036
4037 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4038 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4039
4040 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4041 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4042 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4043 else
4044 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4045 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4046 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4047}
4048
4049
4050/**
4051 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4052 *
4053 * @returns Strict VBox status code.
4054 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4055 * @param pExitInfo Pointer to the VM-exit information.
4056 * @param pExitEventInfo Pointer to the VM-exit event information.
4057 * @thread EMT(pVCpu)
4058 */
4059VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4060 PCVMXVEXITEVENTINFO pExitEventInfo)
4061{
4062 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4063
4064 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4065 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4066 Assert(!pVCpu->iem.s.cActiveMappings);
4067 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4068}
4069
4070
4071/**
4072 * VMX VM-exit handler for EPT-induced VM-exits.
4073 *
4074 * @param pVCpu The cross context virtual CPU structure.
4075 * @param pWalk The page walk info.
4076 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4077 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4078 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4079 * applicable.
4080 */
4081VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4082{
4083 Assert(pWalk->fIsSlat);
4084 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4085 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4086 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4087
4088 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4089 {
4090 Log(("EptViolation: cs:rip=%x:%#RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4091 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4092 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4093 pWalk->GCPtr, cbInstr);
4094 }
4095
4096 Log(("EptMisconfig: cs:rip=%x:%#RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4097 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4098 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4099}
4100
4101
4102/**
4103 * VMX VM-exit handler for APIC accesses.
4104 *
4105 * @param pVCpu The cross context virtual CPU structure.
4106 * @param offAccess The offset of the register being accessed.
4107 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4108 */
4109static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4110{
4111 VMXAPICACCESS enmAccess;
4112 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4113 if (fInEventDelivery)
4114 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4115 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4116 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4117 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4118 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4119 else
4120 enmAccess = VMXAPICACCESS_LINEAR_READ;
4121
4122 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4123 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4124 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4125}
4126
4127
4128/**
4129 * VMX VM-exit handler for APIC accesses.
4130 *
4131 * This is intended for APIC accesses where the caller provides all the
4132 * relevant VM-exit information.
4133 *
4134 * @returns VBox strict status code.
4135 * @param pVCpu The cross context virtual CPU structure.
4136 * @param pExitInfo Pointer to the VM-exit information.
4137 * @param pExitEventInfo Pointer to the VM-exit event information.
4138 */
4139static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4140 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4141{
4142 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4143 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4144 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4145 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4146 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4147 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4148 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4149 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4150 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4151}
4152
4153
4154/**
4155 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4156 *
4157 * @returns Strict VBox status code.
4158 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4159 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4160 *
4161 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4162 * @param pExitInfo Pointer to the VM-exit information.
4163 * @param pExitEventInfo Pointer to the VM-exit event information.
4164 * @thread EMT(pVCpu)
4165 */
4166VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4167{
4168 Assert(pExitInfo);
4169 Assert(pExitEventInfo);
4170 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4171 Assert(!pVCpu->iem.s.cActiveMappings);
4172 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4173
4174}
4175
4176
4177/**
4178 * VMX VM-exit handler for APIC-write VM-exits.
4179 *
4180 * @param pVCpu The cross context virtual CPU structure.
4181 * @param offApic The write to the virtual-APIC page offset that caused this
4182 * VM-exit.
4183 */
4184static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4185{
4186 Assert(offApic < XAPIC_OFF_END + 4);
4187 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4188 offApic &= UINT16_C(0xfff);
4189 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4190}
4191
4192
4193/**
4194 * Clears any pending virtual-APIC write emulation.
4195 *
4196 * @returns The virtual-APIC offset that was written before clearing it.
4197 * @param pVCpu The cross context virtual CPU structure.
4198 */
4199DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4200{
4201 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4202 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4203 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4204 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4205 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4206 return offVirtApicWrite;
4207}
4208
4209
4210/**
4211 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4212 *
4213 * @returns The register from the virtual-APIC page.
4214 * @param pVCpu The cross context virtual CPU structure.
4215 * @param offReg The offset of the register being read.
4216 */
4217uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4218{
4219 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4220
4221 uint32_t uReg = 0;
4222 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4223 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4224 AssertMsgStmt(RT_SUCCESS(rc),
4225 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4226 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4227 uReg = 0);
4228 return uReg;
4229}
4230
4231
4232/**
4233 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4234 *
4235 * @returns The register from the virtual-APIC page.
4236 * @param pVCpu The cross context virtual CPU structure.
4237 * @param offReg The offset of the register being read.
4238 */
4239static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4240{
4241 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4242
4243 uint64_t uReg = 0;
4244 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4245 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4246 AssertMsgStmt(RT_SUCCESS(rc),
4247 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4248 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4249 uReg = 0);
4250 return uReg;
4251}
4252
4253
4254/**
4255 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4256 *
4257 * @param pVCpu The cross context virtual CPU structure.
4258 * @param offReg The offset of the register being written.
4259 * @param uReg The register value to write.
4260 */
4261void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4262{
4263 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4264
4265 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4266 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4267 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4268 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4269}
4270
4271
4272/**
4273 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4274 *
4275 * @param pVCpu The cross context virtual CPU structure.
4276 * @param offReg The offset of the register being written.
4277 * @param uReg The register value to write.
4278 */
4279static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4280{
4281 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4282
4283 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4284 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4285 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4286 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4287}
4288
4289
4290/**
4291 * Sets the vector in a virtual-APIC 256-bit sparse register.
4292 *
4293 * @param pVCpu The cross context virtual CPU structure.
4294 * @param offReg The offset of the 256-bit spare register.
4295 * @param uVector The vector to set.
4296 *
4297 * @remarks This is based on our APIC device code.
4298 */
4299static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4300{
4301 /* Determine the vector offset within the chunk. */
4302 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4303
4304 /* Read the chunk at the offset. */
4305 uint32_t uReg;
4306 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4307 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4308 if (RT_SUCCESS(rc))
4309 {
4310 /* Modify the chunk. */
4311 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4312 uReg |= RT_BIT(idxVectorBit);
4313
4314 /* Write the chunk. */
4315 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4316 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4317 uVector, offReg, GCPhysVirtApic, rc));
4318 }
4319 else
4320 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4321 uVector, offReg, GCPhysVirtApic, rc));
4322}
4323
4324
4325/**
4326 * Clears the vector in a virtual-APIC 256-bit sparse register.
4327 *
4328 * @param pVCpu The cross context virtual CPU structure.
4329 * @param offReg The offset of the 256-bit spare register.
4330 * @param uVector The vector to clear.
4331 *
4332 * @remarks This is based on our APIC device code.
4333 */
4334static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4335{
4336 /* Determine the vector offset within the chunk. */
4337 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4338
4339 /* Read the chunk at the offset. */
4340 uint32_t uReg;
4341 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4342 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4343 if (RT_SUCCESS(rc))
4344 {
4345 /* Modify the chunk. */
4346 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4347 uReg &= ~RT_BIT(idxVectorBit);
4348
4349 /* Write the chunk. */
4350 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4351 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4352 uVector, offReg, GCPhysVirtApic, rc));
4353 }
4354 else
4355 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4356 uVector, offReg, GCPhysVirtApic, rc));
4357}
4358
4359
4360/**
4361 * Checks if a memory access to the APIC-access page must causes an APIC-access
4362 * VM-exit.
4363 *
4364 * @param pVCpu The cross context virtual CPU structure.
4365 * @param offAccess The offset of the register being accessed.
4366 * @param cbAccess The size of the access in bytes.
4367 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4368 *
4369 * @remarks This must not be used for MSR-based APIC-access page accesses!
4370 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4371 */
4372static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4373{
4374 Assert(cbAccess > 0);
4375 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4376
4377 /*
4378 * We must cause a VM-exit if any of the following are true:
4379 * - TPR shadowing isn't active.
4380 * - The access size exceeds 32-bits.
4381 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4382 *
4383 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4384 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4385 */
4386 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4387 || cbAccess > sizeof(uint32_t)
4388 || ((offAccess + cbAccess - 1) & 0xc)
4389 || offAccess >= XAPIC_OFF_END + 4)
4390 return true;
4391
4392 /*
4393 * If the access is part of an operation where we have already
4394 * virtualized a virtual-APIC write, we must cause a VM-exit.
4395 */
4396 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4397 return true;
4398
4399 /*
4400 * Check write accesses to the APIC-access page that cause VM-exits.
4401 */
4402 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4403 {
4404 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4405 {
4406 /*
4407 * With APIC-register virtualization, a write access to any of the
4408 * following registers are virtualized. Accessing any other register
4409 * causes a VM-exit.
4410 */
4411 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4412 switch (offAlignedAccess)
4413 {
4414 case XAPIC_OFF_ID:
4415 case XAPIC_OFF_TPR:
4416 case XAPIC_OFF_EOI:
4417 case XAPIC_OFF_LDR:
4418 case XAPIC_OFF_DFR:
4419 case XAPIC_OFF_SVR:
4420 case XAPIC_OFF_ESR:
4421 case XAPIC_OFF_ICR_LO:
4422 case XAPIC_OFF_ICR_HI:
4423 case XAPIC_OFF_LVT_TIMER:
4424 case XAPIC_OFF_LVT_THERMAL:
4425 case XAPIC_OFF_LVT_PERF:
4426 case XAPIC_OFF_LVT_LINT0:
4427 case XAPIC_OFF_LVT_LINT1:
4428 case XAPIC_OFF_LVT_ERROR:
4429 case XAPIC_OFF_TIMER_ICR:
4430 case XAPIC_OFF_TIMER_DCR:
4431 break;
4432 default:
4433 return true;
4434 }
4435 }
4436 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4437 {
4438 /*
4439 * With virtual-interrupt delivery, a write access to any of the
4440 * following registers are virtualized. Accessing any other register
4441 * causes a VM-exit.
4442 *
4443 * Note! The specification does not allow writing to offsets in-between
4444 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4445 */
4446 switch (offAccess)
4447 {
4448 case XAPIC_OFF_TPR:
4449 case XAPIC_OFF_EOI:
4450 case XAPIC_OFF_ICR_LO:
4451 break;
4452 default:
4453 return true;
4454 }
4455 }
4456 else
4457 {
4458 /*
4459 * Without APIC-register virtualization or virtual-interrupt delivery,
4460 * only TPR accesses are virtualized.
4461 */
4462 if (offAccess == XAPIC_OFF_TPR)
4463 { /* likely */ }
4464 else
4465 return true;
4466 }
4467 }
4468 else
4469 {
4470 /*
4471 * Check read accesses to the APIC-access page that cause VM-exits.
4472 */
4473 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4474 {
4475 /*
4476 * With APIC-register virtualization, a read access to any of the
4477 * following registers are virtualized. Accessing any other register
4478 * causes a VM-exit.
4479 */
4480 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4481 switch (offAlignedAccess)
4482 {
4483 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4484 case XAPIC_OFF_ID:
4485 case XAPIC_OFF_VERSION:
4486 case XAPIC_OFF_TPR:
4487 case XAPIC_OFF_EOI:
4488 case XAPIC_OFF_LDR:
4489 case XAPIC_OFF_DFR:
4490 case XAPIC_OFF_SVR:
4491 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4492 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4493 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4494 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4495 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4496 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4497 case XAPIC_OFF_ESR:
4498 case XAPIC_OFF_ICR_LO:
4499 case XAPIC_OFF_ICR_HI:
4500 case XAPIC_OFF_LVT_TIMER:
4501 case XAPIC_OFF_LVT_THERMAL:
4502 case XAPIC_OFF_LVT_PERF:
4503 case XAPIC_OFF_LVT_LINT0:
4504 case XAPIC_OFF_LVT_LINT1:
4505 case XAPIC_OFF_LVT_ERROR:
4506 case XAPIC_OFF_TIMER_ICR:
4507 case XAPIC_OFF_TIMER_DCR:
4508 break;
4509 default:
4510 return true;
4511 }
4512 }
4513 else
4514 {
4515 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4516 if (offAccess == XAPIC_OFF_TPR)
4517 { /* likely */ }
4518 else
4519 return true;
4520 }
4521 }
4522
4523 /* The APIC access is virtualized, does not cause a VM-exit. */
4524 return false;
4525}
4526
4527
4528/**
4529 * Virtualizes a memory-based APIC access by certain instructions even though they
4530 * do not use the address to access memory.
4531 *
4532 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4533 * page-faults but do not use the address to access memory.
4534 *
4535 * @param pVCpu The cross context virtual CPU structure.
4536 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4537 * @param cbAccess The size of the access in bytes.
4538 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4539 */
4540VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4541{
4542 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4543 Assert(pGCPhysAccess);
4544
4545 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4546 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4547 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4548
4549 if (GCPhysAccess == GCPhysApic)
4550 {
4551 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4552 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4553 if (fIntercept)
4554 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4555
4556 *pGCPhysAccess = GCPhysApic | offAccess;
4557 return VINF_VMX_MODIFIES_BEHAVIOR;
4558 }
4559
4560 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4561}
4562
4563
4564/**
4565 * Virtualizes a memory-based APIC access.
4566 *
4567 * @returns VBox strict status code.
4568 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4569 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4570 *
4571 * @param pVCpu The cross context virtual CPU structure.
4572 * @param offAccess The offset of the register being accessed (within the
4573 * APIC-access page).
4574 * @param cbAccess The size of the access in bytes.
4575 * @param pvData Pointer to the data being written or where to store the data
4576 * being read.
4577 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4578 */
4579static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4580 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4581{
4582 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4583 Assert(pvData);
4584
4585 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4586 if (fIntercept)
4587 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4588
4589 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4590 {
4591 /*
4592 * A write access to the APIC-access page that is virtualized (rather than
4593 * causing a VM-exit) writes data to the virtual-APIC page.
4594 */
4595 uint32_t const u32Data = *(uint32_t *)pvData;
4596 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4597
4598 /*
4599 * Record the currently updated APIC offset, as we need this later for figuring
4600 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4601 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4602 *
4603 * After completion of the current operation, we need to perform TPR virtualization,
4604 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4605 *
4606 * The current operation may be a REP-prefixed string instruction, execution of any
4607 * other instruction, or delivery of an event through the IDT.
4608 *
4609 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4610 * performed now but later after completion of the current operation.
4611 *
4612 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4613 */
4614 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4615 }
4616 else
4617 {
4618 /*
4619 * A read access from the APIC-access page that is virtualized (rather than
4620 * causing a VM-exit) returns data from the virtual-APIC page.
4621 *
4622 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4623 */
4624 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4625
4626 Assert(cbAccess <= 4);
4627 Assert(offAccess < XAPIC_OFF_END + 4);
4628 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4629
4630 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4631 u32Data &= s_auAccessSizeMasks[cbAccess];
4632 *(uint32_t *)pvData = u32Data;
4633 }
4634
4635 return VINF_VMX_MODIFIES_BEHAVIOR;
4636}
4637
4638
4639/**
4640 * Virtualizes an MSR-based APIC read access.
4641 *
4642 * @returns VBox strict status code.
4643 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4644 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4645 * handled by the x2APIC device.
4646 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4647 * not within the range of valid MSRs, caller must raise \#GP(0).
4648 * @param pVCpu The cross context virtual CPU structure.
4649 * @param idMsr The x2APIC MSR being read.
4650 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4651 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4652 */
4653static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4654{
4655 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4656 Assert(pu64Value);
4657
4658 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4659 {
4660 if ( idMsr >= MSR_IA32_X2APIC_START
4661 && idMsr <= MSR_IA32_X2APIC_END)
4662 {
4663 uint16_t const offReg = (idMsr & 0xff) << 4;
4664 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4665 *pu64Value = u64Value;
4666 return VINF_VMX_MODIFIES_BEHAVIOR;
4667 }
4668 return VERR_OUT_OF_RANGE;
4669 }
4670
4671 if (idMsr == MSR_IA32_X2APIC_TPR)
4672 {
4673 uint16_t const offReg = (idMsr & 0xff) << 4;
4674 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4675 *pu64Value = u64Value;
4676 return VINF_VMX_MODIFIES_BEHAVIOR;
4677 }
4678
4679 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4680}
4681
4682
4683/**
4684 * Virtualizes an MSR-based APIC write access.
4685 *
4686 * @returns VBox strict status code.
4687 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4688 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4689 * not within the range of valid MSRs, caller must raise \#GP(0).
4690 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4691 *
4692 * @param pVCpu The cross context virtual CPU structure.
4693 * @param idMsr The x2APIC MSR being written.
4694 * @param u64Value The value of the x2APIC MSR being written.
4695 */
4696static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4697{
4698 /*
4699 * Check if the access is to be virtualized.
4700 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4701 */
4702 if ( idMsr == MSR_IA32_X2APIC_TPR
4703 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4704 && ( idMsr == MSR_IA32_X2APIC_EOI
4705 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4706 {
4707 /* Validate the MSR write depending on the register. */
4708 switch (idMsr)
4709 {
4710 case MSR_IA32_X2APIC_TPR:
4711 case MSR_IA32_X2APIC_SELF_IPI:
4712 {
4713 if (u64Value & UINT64_C(0xffffffffffffff00))
4714 return VERR_OUT_OF_RANGE;
4715 break;
4716 }
4717 case MSR_IA32_X2APIC_EOI:
4718 {
4719 if (u64Value != 0)
4720 return VERR_OUT_OF_RANGE;
4721 break;
4722 }
4723 }
4724
4725 /* Write the MSR to the virtual-APIC page. */
4726 uint16_t const offReg = (idMsr & 0xff) << 4;
4727 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4728
4729 /*
4730 * Record the currently updated APIC offset, as we need this later for figuring
4731 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4732 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4733 */
4734 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4735
4736 return VINF_VMX_MODIFIES_BEHAVIOR;
4737 }
4738
4739 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4740}
4741
4742
4743/**
4744 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4745 *
4746 * @returns Strict VBox status code.
4747 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4748 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4749 * the x2APIC device.
4750 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4751 *
4752 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4753 * @param idMsr The MSR being read.
4754 * @param pu64Value Pointer to the value being written or where to store the
4755 * value being read.
4756 * @param fWrite Whether this is an MSR write or read access.
4757 * @thread EMT(pVCpu)
4758 */
4759VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4760{
4761 Assert(pu64Value);
4762
4763 VBOXSTRICTRC rcStrict;
4764 if (fWrite)
4765 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4766 else
4767 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4768 Assert(!pVCpu->iem.s.cActiveMappings);
4769 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4770
4771}
4772
4773
4774/**
4775 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4776 *
4777 * @returns VBox status code.
4778 * @retval VINF_SUCCESS when the highest set bit is found.
4779 * @retval VERR_NOT_FOUND when no bit is set.
4780 *
4781 * @param pVCpu The cross context virtual CPU structure.
4782 * @param offReg The offset of the APIC 256-bit sparse register.
4783 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4784 * set in the register. Only valid when VINF_SUCCESS is
4785 * returned.
4786 *
4787 * @remarks The format of the 256-bit sparse register here mirrors that found in
4788 * real APIC hardware.
4789 */
4790static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4791{
4792 Assert(offReg < XAPIC_OFF_END + 4);
4793 Assert(pidxHighestBit);
4794
4795 /*
4796 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4797 * However, in each fragment only the first 4 bytes are used.
4798 */
4799 uint8_t const cFrags = 8;
4800 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4801 {
4802 uint16_t const offFrag = iFrag * 16;
4803 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4804 if (!u32Frag)
4805 continue;
4806
4807 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4808 Assert(idxHighestBit > 0);
4809 --idxHighestBit;
4810 Assert(idxHighestBit <= UINT8_MAX);
4811 *pidxHighestBit = idxHighestBit;
4812 return VINF_SUCCESS;
4813 }
4814 return VERR_NOT_FOUND;
4815}
4816
4817
4818/**
4819 * Evaluates pending virtual interrupts.
4820 *
4821 * @param pVCpu The cross context virtual CPU structure.
4822 */
4823static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4824{
4825 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4826
4827 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4828 {
4829 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4830 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4831
4832 if ((uRvi >> 4) > (uPpr >> 4))
4833 {
4834 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4835 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4836 }
4837 else
4838 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4839 }
4840}
4841
4842
4843/**
4844 * Performs PPR virtualization.
4845 *
4846 * @returns VBox strict status code.
4847 * @param pVCpu The cross context virtual CPU structure.
4848 */
4849static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4850{
4851 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4852 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4853
4854 /*
4855 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4856 * or EOI-virtualization.
4857 *
4858 * See Intel spec. 29.1.3 "PPR Virtualization".
4859 */
4860 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4861 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4862
4863 uint32_t uPpr;
4864 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4865 uPpr = uTpr & 0xff;
4866 else
4867 uPpr = uSvi & 0xf0;
4868
4869 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4870 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4871}
4872
4873
4874/**
4875 * Performs VMX TPR virtualization.
4876 *
4877 * @returns VBox strict status code.
4878 * @param pVCpu The cross context virtual CPU structure.
4879 */
4880static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4881{
4882 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4883
4884 /*
4885 * We should have already performed the virtual-APIC write to the TPR offset
4886 * in the virtual-APIC page. We now perform TPR virtualization.
4887 *
4888 * See Intel spec. 29.1.2 "TPR Virtualization".
4889 */
4890 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4891 {
4892 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4893 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4894
4895 /*
4896 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4897 * See Intel spec. 29.1.2 "TPR Virtualization".
4898 */
4899 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4900 {
4901 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4902 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4903 }
4904 }
4905 else
4906 {
4907 iemVmxPprVirtualization(pVCpu);
4908 iemVmxEvalPendingVirtIntrs(pVCpu);
4909 }
4910
4911 return VINF_SUCCESS;
4912}
4913
4914
4915/**
4916 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4917 * not.
4918 *
4919 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4920 * @param pVCpu The cross context virtual CPU structure.
4921 * @param uVector The interrupt that was acknowledged using an EOI.
4922 */
4923static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4924{
4925 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4926 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4927
4928 if (uVector < 64)
4929 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4930 if (uVector < 128)
4931 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4932 if (uVector < 192)
4933 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4934 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4935}
4936
4937
4938/**
4939 * Performs EOI virtualization.
4940 *
4941 * @returns VBox strict status code.
4942 * @param pVCpu The cross context virtual CPU structure.
4943 */
4944static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4945{
4946 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4947 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4948
4949 /*
4950 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4951 * and get the next guest-interrupt that's in-service (if any).
4952 *
4953 * See Intel spec. 29.1.4 "EOI Virtualization".
4954 */
4955 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4956 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4957 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4958
4959 uint8_t uVector = uSvi;
4960 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4961
4962 uVector = 0;
4963 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4964
4965 if (uVector)
4966 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4967 else
4968 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4969
4970 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4971 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4972
4973 iemVmxPprVirtualization(pVCpu);
4974 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4975 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4976 iemVmxEvalPendingVirtIntrs(pVCpu);
4977 return VINF_SUCCESS;
4978}
4979
4980
4981/**
4982 * Performs self-IPI virtualization.
4983 *
4984 * @returns VBox strict status code.
4985 * @param pVCpu The cross context virtual CPU structure.
4986 */
4987static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4988{
4989 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4990 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4991
4992 /*
4993 * We should have already performed the virtual-APIC write to the self-IPI offset
4994 * in the virtual-APIC page. We now perform self-IPI virtualization.
4995 *
4996 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4997 */
4998 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4999 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5000 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5001 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5002 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5003 if (uVector > uRvi)
5004 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5005 iemVmxEvalPendingVirtIntrs(pVCpu);
5006 return VINF_SUCCESS;
5007}
5008
5009
5010/**
5011 * Performs VMX APIC-write emulation.
5012 *
5013 * @returns VBox strict status code.
5014 * @param pVCpu The cross context virtual CPU structure.
5015 */
5016VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5017{
5018 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5019
5020 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5021 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5022
5023 /*
5024 * Perform APIC-write emulation based on the virtual-APIC register written.
5025 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5026 */
5027 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5028 VBOXSTRICTRC rcStrict;
5029 switch (offApicWrite)
5030 {
5031 case XAPIC_OFF_TPR:
5032 {
5033 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5034 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5035 uTpr &= UINT32_C(0x000000ff);
5036 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5037 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5038 rcStrict = iemVmxTprVirtualization(pVCpu);
5039 break;
5040 }
5041
5042 case XAPIC_OFF_EOI:
5043 {
5044 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5045 {
5046 /* Clear VEOI and perform EOI virtualization. */
5047 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5048 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5049 rcStrict = iemVmxEoiVirtualization(pVCpu);
5050 }
5051 else
5052 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5053 break;
5054 }
5055
5056 case XAPIC_OFF_ICR_LO:
5057 {
5058 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5059 {
5060 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5061 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5062 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5063 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5064 if ( !(uIcrLo & fIcrLoMb0)
5065 && (uIcrLo & fIcrLoMb1))
5066 {
5067 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5068 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5069 }
5070 else
5071 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5072 }
5073 else
5074 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5075 break;
5076 }
5077
5078 case XAPIC_OFF_ICR_HI:
5079 {
5080 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5081 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5082 uIcrHi &= UINT32_C(0xff000000);
5083 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5084 rcStrict = VINF_SUCCESS;
5085 break;
5086 }
5087
5088 default:
5089 {
5090 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5091 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5092 break;
5093 }
5094 }
5095
5096 return rcStrict;
5097}
5098
5099
5100/**
5101 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5102 * VM-exit.
5103 *
5104 * @returns Strict VBox status code.
5105 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5106 * @thread EMT(pVCpu)
5107 */
5108VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5109{
5110 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5111 Assert(!pVCpu->iem.s.cActiveMappings);
5112 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5113}
5114
5115
5116/**
5117 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5118 *
5119 * @param pVCpu The cross context virtual CPU structure.
5120 * @param pszInstr The VMX instruction name (for logging purposes).
5121 */
5122DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5123{
5124 /*
5125 * Guest Control Registers, Debug Registers, and MSRs.
5126 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5127 */
5128 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5129 const char * const pszFailure = "VM-exit";
5130 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5131
5132 /* CR0 reserved bits. */
5133 {
5134 /* CR0 MB1 bits. */
5135 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
5136 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5137 { /* likely */ }
5138 else
5139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5140
5141 /* CR0 MBZ bits. */
5142 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5143 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5144 { /* likely */ }
5145 else
5146 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5147
5148 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5149 if ( !fUnrestrictedGuest
5150 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5151 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5153 }
5154
5155 /* CR4 reserved bits. */
5156 {
5157 /* CR4 MB1 bits. */
5158 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5159 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5160 { /* likely */ }
5161 else
5162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5163
5164 /* CR4 MBZ bits. */
5165 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5166 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5167 { /* likely */ }
5168 else
5169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5170 }
5171
5172 /* DEBUGCTL MSR. */
5173 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5174 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5175 { /* likely */ }
5176 else
5177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5178
5179 /* 64-bit CPU checks. */
5180 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5181 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5182 {
5183 if (fGstInLongMode)
5184 {
5185 /* PAE must be set. */
5186 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5187 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5188 { /* likely */ }
5189 else
5190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5191 }
5192 else
5193 {
5194 /* PCIDE should not be set. */
5195 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5196 { /* likely */ }
5197 else
5198 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5199 }
5200
5201 /* CR3. */
5202 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5203 { /* likely */ }
5204 else
5205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5206
5207 /* DR7. */
5208 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5209 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5210 { /* likely */ }
5211 else
5212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5213
5214 /* SYSENTER ESP and SYSENTER EIP. */
5215 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5216 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5217 { /* likely */ }
5218 else
5219 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5220 }
5221
5222 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5223 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5224
5225 /* PAT MSR. */
5226 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5227 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5228 { /* likely */ }
5229 else
5230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5231
5232 /* EFER MSR. */
5233 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5234 {
5235 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5236 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5237 { /* likely */ }
5238 else
5239 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5240
5241 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5242 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5243 if ( fGstLma == fGstInLongMode
5244 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5245 || fGstLma == fGstLme))
5246 { /* likely */ }
5247 else
5248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5249 }
5250
5251 /* We don't support IA32_BNDCFGS MSR yet. */
5252 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5253
5254 NOREF(pszInstr);
5255 NOREF(pszFailure);
5256 return VINF_SUCCESS;
5257}
5258
5259
5260/**
5261 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5262 *
5263 * @param pVCpu The cross context virtual CPU structure.
5264 * @param pszInstr The VMX instruction name (for logging purposes).
5265 */
5266DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5267{
5268 /*
5269 * Segment registers.
5270 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5271 */
5272 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5273 const char * const pszFailure = "VM-exit";
5274 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5275 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5276 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5277
5278 /* Selectors. */
5279 if ( !fGstInV86Mode
5280 && !fUnrestrictedGuest
5281 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5283
5284 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5285 {
5286 CPUMSELREG SelReg;
5287 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5288 if (RT_LIKELY(rc == VINF_SUCCESS))
5289 { /* likely */ }
5290 else
5291 return rc;
5292
5293 /*
5294 * Virtual-8086 mode checks.
5295 */
5296 if (fGstInV86Mode)
5297 {
5298 /* Base address. */
5299 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5300 { /* likely */ }
5301 else
5302 {
5303 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5305 }
5306
5307 /* Limit. */
5308 if (SelReg.u32Limit == 0xffff)
5309 { /* likely */ }
5310 else
5311 {
5312 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5314 }
5315
5316 /* Attribute. */
5317 if (SelReg.Attr.u == 0xf3)
5318 { /* likely */ }
5319 else
5320 {
5321 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5323 }
5324
5325 /* We're done; move to checking the next segment. */
5326 continue;
5327 }
5328
5329 /* Checks done by 64-bit CPUs. */
5330 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5331 {
5332 /* Base address. */
5333 if ( iSegReg == X86_SREG_FS
5334 || iSegReg == X86_SREG_GS)
5335 {
5336 if (X86_IS_CANONICAL(SelReg.u64Base))
5337 { /* likely */ }
5338 else
5339 {
5340 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5341 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5342 }
5343 }
5344 else if (iSegReg == X86_SREG_CS)
5345 {
5346 if (!RT_HI_U32(SelReg.u64Base))
5347 { /* likely */ }
5348 else
5349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5350 }
5351 else
5352 {
5353 if ( SelReg.Attr.n.u1Unusable
5354 || !RT_HI_U32(SelReg.u64Base))
5355 { /* likely */ }
5356 else
5357 {
5358 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5360 }
5361 }
5362 }
5363
5364 /*
5365 * Checks outside Virtual-8086 mode.
5366 */
5367 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5368 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5369 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5370 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5371 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5372 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5373 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5374 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5375
5376 /* Code or usable segment. */
5377 if ( iSegReg == X86_SREG_CS
5378 || fUsable)
5379 {
5380 /* Reserved bits (bits 31:17 and bits 11:8). */
5381 if (!(SelReg.Attr.u & 0xfffe0f00))
5382 { /* likely */ }
5383 else
5384 {
5385 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5386 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5387 }
5388
5389 /* Descriptor type. */
5390 if (fCodeDataSeg)
5391 { /* likely */ }
5392 else
5393 {
5394 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5396 }
5397
5398 /* Present. */
5399 if (fPresent)
5400 { /* likely */ }
5401 else
5402 {
5403 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5405 }
5406
5407 /* Granularity. */
5408 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5409 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5410 { /* likely */ }
5411 else
5412 {
5413 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5415 }
5416 }
5417
5418 if (iSegReg == X86_SREG_CS)
5419 {
5420 /* Segment Type and DPL. */
5421 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5422 && fUnrestrictedGuest)
5423 {
5424 if (uDpl == 0)
5425 { /* likely */ }
5426 else
5427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5428 }
5429 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5430 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5431 {
5432 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5433 if (uDpl == AttrSs.n.u2Dpl)
5434 { /* likely */ }
5435 else
5436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5437 }
5438 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5439 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5440 {
5441 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5442 if (uDpl <= AttrSs.n.u2Dpl)
5443 { /* likely */ }
5444 else
5445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5446 }
5447 else
5448 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5449
5450 /* Def/Big. */
5451 if ( fGstInLongMode
5452 && fSegLong)
5453 {
5454 if (uDefBig == 0)
5455 { /* likely */ }
5456 else
5457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5458 }
5459 }
5460 else if (iSegReg == X86_SREG_SS)
5461 {
5462 /* Segment Type. */
5463 if ( !fUsable
5464 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5465 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5466 { /* likely */ }
5467 else
5468 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5469
5470 /* DPL. */
5471 if (!fUnrestrictedGuest)
5472 {
5473 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5474 { /* likely */ }
5475 else
5476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5477 }
5478 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5479 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5480 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5481 {
5482 if (uDpl == 0)
5483 { /* likely */ }
5484 else
5485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5486 }
5487 }
5488 else
5489 {
5490 /* DS, ES, FS, GS. */
5491 if (fUsable)
5492 {
5493 /* Segment type. */
5494 if (uSegType & X86_SEL_TYPE_ACCESSED)
5495 { /* likely */ }
5496 else
5497 {
5498 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5500 }
5501
5502 if ( !(uSegType & X86_SEL_TYPE_CODE)
5503 || (uSegType & X86_SEL_TYPE_READ))
5504 { /* likely */ }
5505 else
5506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5507
5508 /* DPL. */
5509 if ( !fUnrestrictedGuest
5510 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5511 {
5512 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5513 { /* likely */ }
5514 else
5515 {
5516 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5517 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5518 }
5519 }
5520 }
5521 }
5522 }
5523
5524 /*
5525 * LDTR.
5526 */
5527 {
5528 CPUMSELREG Ldtr;
5529 Ldtr.Sel = pVmcs->GuestLdtr;
5530 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5531 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5532 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5533
5534 if (!Ldtr.Attr.n.u1Unusable)
5535 {
5536 /* Selector. */
5537 if (!(Ldtr.Sel & X86_SEL_LDT))
5538 { /* likely */ }
5539 else
5540 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5541
5542 /* Base. */
5543 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5544 {
5545 if (X86_IS_CANONICAL(Ldtr.u64Base))
5546 { /* likely */ }
5547 else
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5549 }
5550
5551 /* Attributes. */
5552 /* Reserved bits (bits 31:17 and bits 11:8). */
5553 if (!(Ldtr.Attr.u & 0xfffe0f00))
5554 { /* likely */ }
5555 else
5556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5557
5558 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5559 { /* likely */ }
5560 else
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5562
5563 if (!Ldtr.Attr.n.u1DescType)
5564 { /* likely */ }
5565 else
5566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5567
5568 if (Ldtr.Attr.n.u1Present)
5569 { /* likely */ }
5570 else
5571 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5572
5573 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5574 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5575 { /* likely */ }
5576 else
5577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5578 }
5579 }
5580
5581 /*
5582 * TR.
5583 */
5584 {
5585 CPUMSELREG Tr;
5586 Tr.Sel = pVmcs->GuestTr;
5587 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5588 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5589 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5590
5591 /* Selector. */
5592 if (!(Tr.Sel & X86_SEL_LDT))
5593 { /* likely */ }
5594 else
5595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5596
5597 /* Base. */
5598 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5599 {
5600 if (X86_IS_CANONICAL(Tr.u64Base))
5601 { /* likely */ }
5602 else
5603 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5604 }
5605
5606 /* Attributes. */
5607 /* Reserved bits (bits 31:17 and bits 11:8). */
5608 if (!(Tr.Attr.u & 0xfffe0f00))
5609 { /* likely */ }
5610 else
5611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5612
5613 if (!Tr.Attr.n.u1Unusable)
5614 { /* likely */ }
5615 else
5616 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5617
5618 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5619 || ( !fGstInLongMode
5620 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5621 { /* likely */ }
5622 else
5623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5624
5625 if (!Tr.Attr.n.u1DescType)
5626 { /* likely */ }
5627 else
5628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5629
5630 if (Tr.Attr.n.u1Present)
5631 { /* likely */ }
5632 else
5633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5634
5635 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5636 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5637 { /* likely */ }
5638 else
5639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5640 }
5641
5642 NOREF(pszInstr);
5643 NOREF(pszFailure);
5644 return VINF_SUCCESS;
5645}
5646
5647
5648/**
5649 * Checks guest GDTR and IDTR as part of VM-entry.
5650 *
5651 * @param pVCpu The cross context virtual CPU structure.
5652 * @param pszInstr The VMX instruction name (for logging purposes).
5653 */
5654DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5655{
5656 /*
5657 * GDTR and IDTR.
5658 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5659 */
5660 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5661 const char *const pszFailure = "VM-exit";
5662
5663 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5664 {
5665 /* Base. */
5666 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5667 { /* likely */ }
5668 else
5669 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5670
5671 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5672 { /* likely */ }
5673 else
5674 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5675 }
5676
5677 /* Limit. */
5678 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5679 { /* likely */ }
5680 else
5681 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5682
5683 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5684 { /* likely */ }
5685 else
5686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5687
5688 NOREF(pszInstr);
5689 NOREF(pszFailure);
5690 return VINF_SUCCESS;
5691}
5692
5693
5694/**
5695 * Checks guest RIP and RFLAGS as part of VM-entry.
5696 *
5697 * @param pVCpu The cross context virtual CPU structure.
5698 * @param pszInstr The VMX instruction name (for logging purposes).
5699 */
5700DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5701{
5702 /*
5703 * RIP and RFLAGS.
5704 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5705 */
5706 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5707 const char *const pszFailure = "VM-exit";
5708 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5709
5710 /* RIP. */
5711 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5712 {
5713 X86DESCATTR AttrCs;
5714 AttrCs.u = pVmcs->u32GuestCsAttr;
5715 if ( !fGstInLongMode
5716 || !AttrCs.n.u1Long)
5717 {
5718 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5719 { /* likely */ }
5720 else
5721 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5722 }
5723
5724 if ( fGstInLongMode
5725 && AttrCs.n.u1Long)
5726 {
5727 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5728 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5729 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5730 { /* likely */ }
5731 else
5732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5733 }
5734 }
5735
5736 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5737 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5738 : pVmcs->u64GuestRFlags.s.Lo;
5739 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5740 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5741 { /* likely */ }
5742 else
5743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5744
5745 if (!(uGuestRFlags & X86_EFL_VM))
5746 { /* likely */ }
5747 else
5748 {
5749 if ( fGstInLongMode
5750 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5751 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5752 }
5753
5754 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5755 {
5756 if (uGuestRFlags & X86_EFL_IF)
5757 { /* likely */ }
5758 else
5759 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5760 }
5761
5762 NOREF(pszInstr);
5763 NOREF(pszFailure);
5764 return VINF_SUCCESS;
5765}
5766
5767
5768/**
5769 * Checks guest non-register state as part of VM-entry.
5770 *
5771 * @param pVCpu The cross context virtual CPU structure.
5772 * @param pszInstr The VMX instruction name (for logging purposes).
5773 */
5774DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5775{
5776 /*
5777 * Guest non-register state.
5778 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5779 */
5780 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5781 const char *const pszFailure = "VM-exit";
5782
5783 /*
5784 * Activity state.
5785 */
5786 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5787 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5788 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5789 { /* likely */ }
5790 else
5791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5792
5793 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5794 if ( !AttrSs.n.u2Dpl
5795 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5796 { /* likely */ }
5797 else
5798 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5799
5800 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5801 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5802 {
5803 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5804 { /* likely */ }
5805 else
5806 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5807 }
5808
5809 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5810 {
5811 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5812 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5813 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5814 switch (pVmcs->u32GuestActivityState)
5815 {
5816 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5817 {
5818 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5819 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5820 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5821 && ( uVector == X86_XCPT_DB
5822 || uVector == X86_XCPT_MC))
5823 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5824 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5825 { /* likely */ }
5826 else
5827 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5828 break;
5829 }
5830
5831 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5832 {
5833 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5834 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5835 && uVector == X86_XCPT_MC))
5836 { /* likely */ }
5837 else
5838 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5839 break;
5840 }
5841
5842 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5843 default:
5844 break;
5845 }
5846 }
5847
5848 /*
5849 * Interruptibility state.
5850 */
5851 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5852 { /* likely */ }
5853 else
5854 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5855
5856 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5857 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5858 { /* likely */ }
5859 else
5860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5861
5862 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5863 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5864 { /* likely */ }
5865 else
5866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5867
5868 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5869 {
5870 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5871 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5872 {
5873 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5874 { /* likely */ }
5875 else
5876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5877 }
5878 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5879 {
5880 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5881 { /* likely */ }
5882 else
5883 {
5884 /*
5885 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5886 * We update the Exit qualification only when blocking-by-STI is set
5887 * without blocking-by-MovSS being set. Although in practise it does not
5888 * make much difference since the order of checks are implementation defined.
5889 */
5890 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5891 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5892 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5893 }
5894
5895 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5896 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5897 { /* likely */ }
5898 else
5899 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5900 }
5901 }
5902
5903 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5904 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5905 { /* likely */ }
5906 else
5907 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5908
5909 /* We don't support SGX yet. So enclave-interruption must not be set. */
5910 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5911 { /* likely */ }
5912 else
5913 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5914
5915 /*
5916 * Pending debug exceptions.
5917 */
5918 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5919 ? pVmcs->u64GuestPendingDbgXcpts.u
5920 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5921 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5922 { /* likely */ }
5923 else
5924 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5925
5926 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5927 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5928 {
5929 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5930 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5931 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5933
5934 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5935 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5936 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5937 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5938 }
5939
5940 /* We don't support RTM (Real-time Transactional Memory) yet. */
5941 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5942 { /* likely */ }
5943 else
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5945
5946 /*
5947 * VMCS link pointer.
5948 */
5949 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5950 {
5951 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5952 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5953 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5954 { /* likely */ }
5955 else
5956 {
5957 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5958 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5959 }
5960
5961 /* Validate the address. */
5962 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5963 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5964 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5965 { /* likely */ }
5966 else
5967 {
5968 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5969 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5970 }
5971 }
5972
5973 NOREF(pszInstr);
5974 NOREF(pszFailure);
5975 return VINF_SUCCESS;
5976}
5977
5978
5979#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5980/**
5981 * Checks guest PDPTEs as part of VM-entry.
5982 *
5983 * @param pVCpu The cross context virtual CPU structure.
5984 * @param pszInstr The VMX instruction name (for logging purposes).
5985 */
5986static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
5987{
5988 /*
5989 * Guest PDPTEs.
5990 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5991 */
5992 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5993 const char * const pszFailure = "VM-exit";
5994
5995 /*
5996 * When EPT is used, we only validate the PAE PDPTEs provided in the VMCS.
5997 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
5998 */
5999 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6000 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6001 {
6002 /* Get PDPTEs from the VMCS. */
6003 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6004 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6005 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6006 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6007 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6008
6009 /* Check validity of the PDPTEs. */
6010 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
6011 if (fValid)
6012 { /* likely */ }
6013 else
6014 {
6015 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6017 }
6018 }
6019
6020 NOREF(pszFailure);
6021 NOREF(pszInstr);
6022 return VINF_SUCCESS;
6023}
6024#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6025
6026
6027/**
6028 * Checks guest-state as part of VM-entry.
6029 *
6030 * @returns VBox status code.
6031 * @param pVCpu The cross context virtual CPU structure.
6032 * @param pszInstr The VMX instruction name (for logging purposes).
6033 */
6034static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6035{
6036 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6037 if (RT_SUCCESS(rc))
6038 {
6039 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6040 if (RT_SUCCESS(rc))
6041 {
6042 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6043 if (RT_SUCCESS(rc))
6044 {
6045 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6046 if (RT_SUCCESS(rc))
6047 {
6048 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6049#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6050 if (RT_SUCCESS(rc))
6051 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6052#endif
6053 }
6054 }
6055 }
6056 }
6057 return rc;
6058}
6059
6060
6061/**
6062 * Checks host-state as part of VM-entry.
6063 *
6064 * @returns VBox status code.
6065 * @param pVCpu The cross context virtual CPU structure.
6066 * @param pszInstr The VMX instruction name (for logging purposes).
6067 */
6068static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6069{
6070 /*
6071 * Host Control Registers and MSRs.
6072 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6073 */
6074 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6075 const char * const pszFailure = "VMFail";
6076
6077 /* CR0 reserved bits. */
6078 {
6079 /* CR0 MB1 bits. */
6080 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
6081 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6082 { /* likely */ }
6083 else
6084 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6085
6086 /* CR0 MBZ bits. */
6087 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6088 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6089 { /* likely */ }
6090 else
6091 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6092 }
6093
6094 /* CR4 reserved bits. */
6095 {
6096 /* CR4 MB1 bits. */
6097 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6098 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6099 { /* likely */ }
6100 else
6101 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6102
6103 /* CR4 MBZ bits. */
6104 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6105 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6106 { /* likely */ }
6107 else
6108 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6109 }
6110
6111 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6112 {
6113 /* CR3 reserved bits. */
6114 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6115 { /* likely */ }
6116 else
6117 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6118
6119 /* SYSENTER ESP and SYSENTER EIP. */
6120 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6121 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6122 { /* likely */ }
6123 else
6124 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6125 }
6126
6127 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6128 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6129
6130 /* PAT MSR. */
6131 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6132 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6133 { /* likely */ }
6134 else
6135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6136
6137 /* EFER MSR. */
6138 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6139 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6140 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6141 { /* likely */ }
6142 else
6143 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6144
6145 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6146 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6147 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6148 if ( fHostInLongMode == fHostLma
6149 && fHostInLongMode == fHostLme)
6150 { /* likely */ }
6151 else
6152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6153
6154 /*
6155 * Host Segment and Descriptor-Table Registers.
6156 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6157 */
6158 /* Selector RPL and TI. */
6159 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6160 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6161 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6162 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6163 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6164 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6165 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6166 { /* likely */ }
6167 else
6168 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6169
6170 /* CS and TR selectors cannot be 0. */
6171 if ( pVmcs->HostCs
6172 && pVmcs->HostTr)
6173 { /* likely */ }
6174 else
6175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6176
6177 /* SS cannot be 0 if 32-bit host. */
6178 if ( fHostInLongMode
6179 || pVmcs->HostSs)
6180 { /* likely */ }
6181 else
6182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6183
6184 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6185 {
6186 /* FS, GS, GDTR, IDTR, TR base address. */
6187 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6188 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6189 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6190 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6191 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6192 { /* likely */ }
6193 else
6194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6195 }
6196
6197 /*
6198 * Host address-space size for 64-bit CPUs.
6199 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6200 */
6201 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6202 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6203 {
6204 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6205
6206 /* Logical processor in IA-32e mode. */
6207 if (fCpuInLongMode)
6208 {
6209 if (fHostInLongMode)
6210 {
6211 /* PAE must be set. */
6212 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6213 { /* likely */ }
6214 else
6215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6216
6217 /* RIP must be canonical. */
6218 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6222 }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6225 }
6226 else
6227 {
6228 /* Logical processor is outside IA-32e mode. */
6229 if ( !fGstInLongMode
6230 && !fHostInLongMode)
6231 {
6232 /* PCIDE should not be set. */
6233 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6234 { /* likely */ }
6235 else
6236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6237
6238 /* The high 32-bits of RIP MBZ. */
6239 if (!pVmcs->u64HostRip.s.Hi)
6240 { /* likely */ }
6241 else
6242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6243 }
6244 else
6245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6246 }
6247 }
6248 else
6249 {
6250 /* Host address-space size for 32-bit CPUs. */
6251 if ( !fGstInLongMode
6252 && !fHostInLongMode)
6253 { /* likely */ }
6254 else
6255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6256 }
6257
6258 NOREF(pszInstr);
6259 NOREF(pszFailure);
6260 return VINF_SUCCESS;
6261}
6262
6263
6264#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6265/**
6266 * Checks the EPT pointer VMCS field as part of VM-entry.
6267 *
6268 * @returns VBox status code.
6269 * @param pVCpu The cross context virtual CPU structure.
6270 * @param uEptPtr The EPT pointer to check.
6271 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6272 * updated on success). Optional, can be NULL.
6273 */
6274static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6275{
6276 VMXVDIAG enmVmxDiag;
6277
6278 /* Reserved bits. */
6279 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6280 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6281 if (uEptPtr & fValidMask)
6282 {
6283 /* Memory Type. */
6284 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6285 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6286 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6287 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6288 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6289 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6290 {
6291 /*
6292 * Page walk length (PML4).
6293 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6294 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6295 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6296 */
6297 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6298 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6299 {
6300 /* Access and dirty bits support in EPT structures. */
6301 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6302 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6303 return VINF_SUCCESS;
6304
6305 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6306 }
6307 else
6308 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6309 }
6310 else
6311 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6312 }
6313 else
6314 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6315
6316 if (penmVmxDiag)
6317 *penmVmxDiag = enmVmxDiag;
6318 return VERR_VMX_VMENTRY_FAILED;
6319}
6320#endif
6321
6322
6323/**
6324 * Checks VMCS controls fields as part of VM-entry.
6325 *
6326 * @returns VBox status code.
6327 * @param pVCpu The cross context virtual CPU structure.
6328 * @param pszInstr The VMX instruction name (for logging purposes).
6329 *
6330 * @remarks This may update secondary-processor based VM-execution control fields
6331 * in the current VMCS if necessary.
6332 */
6333static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6334{
6335 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6336 const char * const pszFailure = "VMFail";
6337 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6338
6339 /*
6340 * VM-execution controls.
6341 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6342 */
6343 {
6344 /* Pin-based VM-execution controls. */
6345 {
6346 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6347 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6348 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6349 { /* likely */ }
6350 else
6351 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6352
6353 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6354 { /* likely */ }
6355 else
6356 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6357 }
6358
6359 /* Processor-based VM-execution controls. */
6360 {
6361 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6362 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6363 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6364 { /* likely */ }
6365 else
6366 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6367
6368 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6369 { /* likely */ }
6370 else
6371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6372 }
6373
6374 /* Secondary processor-based VM-execution controls. */
6375 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6376 {
6377 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6378 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6379 { /* likely */ }
6380 else
6381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6382
6383 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6384 { /* likely */ }
6385 else
6386 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6387 }
6388 else
6389 Assert(!pVmcs->u32ProcCtls2);
6390
6391 /* CR3-target count. */
6392 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6393 { /* likely */ }
6394 else
6395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6396
6397 /* I/O bitmaps physical addresses. */
6398 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6399 {
6400 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6401 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6402 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6403 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6404 { /* likely */ }
6405 else
6406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6407
6408 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6409 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6410 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6411 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6412 { /* likely */ }
6413 else
6414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6415 }
6416
6417 /* MSR bitmap physical address. */
6418 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6419 {
6420 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6421 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6422 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6423 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6424 { /* likely */ }
6425 else
6426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6427 }
6428
6429 /* TPR shadow related controls. */
6430 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6431 {
6432 /* Virtual-APIC page physical address. */
6433 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6434 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6435 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6436 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6437 { /* likely */ }
6438 else
6439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6440
6441 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6442 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6443 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6444 { /* likely */ }
6445 else
6446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6447
6448 /* The rest done XXX document */
6449 }
6450 else
6451 {
6452 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6453 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6454 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6455 { /* likely */ }
6456 else
6457 {
6458 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6459 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6460 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6462 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6464 }
6465 }
6466
6467 /* NMI exiting and virtual-NMIs. */
6468 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6469 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6470 { /* likely */ }
6471 else
6472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6473
6474 /* Virtual-NMIs and NMI-window exiting. */
6475 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6476 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6477 { /* likely */ }
6478 else
6479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6480
6481 /* Virtualize APIC accesses. */
6482 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6483 {
6484 /* APIC-access physical address. */
6485 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6486 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6487 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6488 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6489 { /* likely */ }
6490 else
6491 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6492
6493 /*
6494 * Disallow APIC-access page and virtual-APIC page from being the same address.
6495 * Note! This is not an Intel requirement, but one imposed by our implementation.
6496 */
6497 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6498 * redirecting accesses between the APIC-access page and the virtual-APIC
6499 * page. If any nested hypervisor requires this, we can implement it later. */
6500 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6501 {
6502 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6503 if (GCPhysVirtApic != GCPhysApicAccess)
6504 { /* likely */ }
6505 else
6506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6507 }
6508 }
6509
6510 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6511 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6512 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6513 { /* likely */ }
6514 else
6515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6516
6517 /* Virtual-interrupt delivery requires external interrupt exiting. */
6518 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6519 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6520 { /* likely */ }
6521 else
6522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6523
6524 /* VPID. */
6525 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6526 || pVmcs->u16Vpid != 0)
6527 { /* likely */ }
6528 else
6529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6530
6531#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6532 /* Extended-Page-Table Pointer (EPTP). */
6533 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6534 {
6535 VMXVDIAG enmVmxDiag;
6536 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6537 if (RT_SUCCESS(rc))
6538 { /* likely */ }
6539 else
6540 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6541 }
6542#else
6543 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6544 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6545#endif
6546 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6547 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6548 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6549 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6550 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6551 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6552
6553 /* VMCS shadowing. */
6554 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6555 {
6556 /* VMREAD-bitmap physical address. */
6557 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6558 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6559 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6560 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6561 { /* likely */ }
6562 else
6563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6564
6565 /* VMWRITE-bitmap physical address. */
6566 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6567 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6568 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6569 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6570 { /* likely */ }
6571 else
6572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6573 }
6574 }
6575
6576 /*
6577 * VM-exit controls.
6578 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6579 */
6580 {
6581 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6582 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6583 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6584 { /* likely */ }
6585 else
6586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6587
6588 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6589 { /* likely */ }
6590 else
6591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6592
6593 /* Save preemption timer without activating it. */
6594 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6595 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6596 { /* likely */ }
6597 else
6598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6599
6600 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6601 if (pVmcs->u32ExitMsrStoreCount)
6602 {
6603 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6604 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6605 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6606 { /* likely */ }
6607 else
6608 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6609 }
6610
6611 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6612 if (pVmcs->u32ExitMsrLoadCount)
6613 {
6614 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6615 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6616 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6617 { /* likely */ }
6618 else
6619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6620 }
6621 }
6622
6623 /*
6624 * VM-entry controls.
6625 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6626 */
6627 {
6628 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6629 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6630 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6631 { /* likely */ }
6632 else
6633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6634
6635 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6636 { /* likely */ }
6637 else
6638 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6639
6640 /* Event injection. */
6641 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6642 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6643 {
6644 /* Type and vector. */
6645 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6646 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6647 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6648 if ( !uRsvd
6649 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6650 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6651 { /* likely */ }
6652 else
6653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6654
6655 /* Exception error code. */
6656 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6657 {
6658 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6659 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6660 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6661 { /* likely */ }
6662 else
6663 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6664
6665 /* Exceptions that provide an error code. */
6666 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6667 && ( uVector == X86_XCPT_DF
6668 || uVector == X86_XCPT_TS
6669 || uVector == X86_XCPT_NP
6670 || uVector == X86_XCPT_SS
6671 || uVector == X86_XCPT_GP
6672 || uVector == X86_XCPT_PF
6673 || uVector == X86_XCPT_AC))
6674 { /* likely */ }
6675 else
6676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6677
6678 /* Exception error-code reserved bits. */
6679 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6680 { /* likely */ }
6681 else
6682 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6683
6684 /* Injecting a software interrupt, software exception or privileged software exception. */
6685 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6686 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6687 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6688 {
6689 /* Instruction length must be in the range 0-15. */
6690 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6691 { /* likely */ }
6692 else
6693 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6694
6695 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6696 if ( pVmcs->u32EntryInstrLen != 0
6697 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6698 { /* likely */ }
6699 else
6700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6701 }
6702 }
6703 }
6704
6705 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6706 if (pVmcs->u32EntryMsrLoadCount)
6707 {
6708 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6709 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6710 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6711 { /* likely */ }
6712 else
6713 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6714 }
6715
6716 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6717 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6718 }
6719
6720 NOREF(pszInstr);
6721 NOREF(pszFailure);
6722 return VINF_SUCCESS;
6723}
6724
6725
6726/**
6727 * Loads the guest control registers, debug register and some MSRs as part of
6728 * VM-entry.
6729 *
6730 * @param pVCpu The cross context virtual CPU structure.
6731 */
6732static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6733{
6734 /*
6735 * Load guest control registers, debug registers and MSRs.
6736 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6737 */
6738 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6739
6740 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6741 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6742 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6743 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6744 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6745 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6746
6747 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6748 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6749
6750 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6751 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6752 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6753
6754 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6755 {
6756 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6757
6758 /* EFER MSR. */
6759 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6760 {
6761 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6762 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6763 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6764 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6765 if (fGstInLongMode)
6766 {
6767 /* If the nested-guest is in long mode, LMA and LME are both set. */
6768 Assert(fGstPaging);
6769 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6770 }
6771 else
6772 {
6773 /*
6774 * If the nested-guest is outside long mode:
6775 * - With paging: LMA is cleared, LME is cleared.
6776 * - Without paging: LMA is cleared, LME is left unmodified.
6777 */
6778 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6779 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6780 }
6781 }
6782 /* else: see below. */
6783 }
6784
6785 /* PAT MSR. */
6786 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6787 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6788
6789 /* EFER MSR. */
6790 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6791 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6792
6793 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6794 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6795
6796 /* We don't support IA32_BNDCFGS MSR yet. */
6797 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6798
6799 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6800}
6801
6802
6803/**
6804 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6805 *
6806 * @param pVCpu The cross context virtual CPU structure.
6807 */
6808static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6809{
6810 /*
6811 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6812 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6813 */
6814 /* CS, SS, ES, DS, FS, GS. */
6815 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6816 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6817 {
6818 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6819 CPUMSELREG VmcsSelReg;
6820 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6821 AssertRC(rc); NOREF(rc);
6822 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6823 {
6824 pGstSelReg->Sel = VmcsSelReg.Sel;
6825 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6826 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6827 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6828 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6829 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6830 }
6831 else
6832 {
6833 pGstSelReg->Sel = VmcsSelReg.Sel;
6834 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6835 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6836 switch (iSegReg)
6837 {
6838 case X86_SREG_CS:
6839 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6840 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6841 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6842 break;
6843
6844 case X86_SREG_SS:
6845 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6846 pGstSelReg->u32Limit = 0;
6847 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6848 break;
6849
6850 case X86_SREG_ES:
6851 case X86_SREG_DS:
6852 pGstSelReg->u64Base = 0;
6853 pGstSelReg->u32Limit = 0;
6854 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6855 break;
6856
6857 case X86_SREG_FS:
6858 case X86_SREG_GS:
6859 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6860 pGstSelReg->u32Limit = 0;
6861 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6862 break;
6863 }
6864 Assert(pGstSelReg->Attr.n.u1Unusable);
6865 }
6866 }
6867
6868 /* LDTR. */
6869 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6870 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6871 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6872 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6873 {
6874 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6875 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6876 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6877 }
6878 else
6879 {
6880 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6881 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6882 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6883 }
6884
6885 /* TR. */
6886 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6887 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6888 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6889 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6890 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6891 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6892 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6893
6894 /* GDTR. */
6895 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6896 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6897
6898 /* IDTR. */
6899 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6900 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6901}
6902
6903
6904/**
6905 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6906 *
6907 * @returns VBox status code.
6908 * @param pVCpu The cross context virtual CPU structure.
6909 * @param pszInstr The VMX instruction name (for logging purposes).
6910 */
6911static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6912{
6913 /*
6914 * Load guest MSRs.
6915 * See Intel spec. 26.4 "Loading MSRs".
6916 */
6917 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6918 const char *const pszFailure = "VM-exit";
6919
6920 /*
6921 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6922 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6923 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6924 */
6925 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6926 if (!cMsrs)
6927 return VINF_SUCCESS;
6928
6929 /*
6930 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6931 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6932 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6933 */
6934 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6935 if (fIsMsrCountValid)
6936 { /* likely */ }
6937 else
6938 {
6939 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6940 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6941 }
6942
6943 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6944 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6945 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6946 if (RT_SUCCESS(rc))
6947 {
6948 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6949 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6950 {
6951 if ( !pMsr->u32Reserved
6952 && pMsr->u32Msr != MSR_K8_FS_BASE
6953 && pMsr->u32Msr != MSR_K8_GS_BASE
6954 && pMsr->u32Msr != MSR_K6_EFER
6955 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6956 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6957 {
6958 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6959 if (rcStrict == VINF_SUCCESS)
6960 continue;
6961
6962 /*
6963 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6964 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6965 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6966 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6967 * MSR in ring-0 if possible, or come up with a better, generic solution.
6968 */
6969 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6970 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6971 ? kVmxVDiag_Vmentry_MsrLoadRing3
6972 : kVmxVDiag_Vmentry_MsrLoad;
6973 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6974 }
6975 else
6976 {
6977 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6978 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6979 }
6980 }
6981 }
6982 else
6983 {
6984 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6986 }
6987
6988 NOREF(pszInstr);
6989 NOREF(pszFailure);
6990 return VINF_SUCCESS;
6991}
6992
6993
6994/**
6995 * Loads the guest-state non-register state as part of VM-entry.
6996 *
6997 * @returns VBox status code.
6998 * @param pVCpu The cross context virtual CPU structure.
6999 * @param pszInstr The VMX instruction name (for logging purposes).
7000 *
7001 * @remarks This must be called only after loading the nested-guest register state
7002 * (especially nested-guest RIP).
7003 */
7004static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7005{
7006 /*
7007 * Load guest non-register state.
7008 * See Intel spec. 26.6 "Special Features of VM Entry"
7009 */
7010 const char *const pszFailure = "VM-exit";
7011 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7012
7013 /*
7014 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7015 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7016 *
7017 * See Intel spec. 26.6.1 "Interruptibility State".
7018 */
7019 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7020 if ( !fEntryVectoring
7021 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7022 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7023 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7024 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7025
7026 /* NMI blocking. */
7027 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7028 {
7029 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7030 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7031 else
7032 {
7033 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7034 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7035 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7036 }
7037 }
7038 else
7039 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7040
7041 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7042
7043 /*
7044 * Set PGM's copy of the EPT pointer.
7045 * The EPTP has already been validated while checking guest state.
7046 *
7047 * It is important to do this prior to mapping PAE PDPTEs (below).
7048 */
7049 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7050 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7051
7052 /*
7053 * Load the guest's PAE PDPTEs.
7054 */
7055 if (iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7056 {
7057 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7058 {
7059 /*
7060 * With EPT, we've already validated these while checking the guest state.
7061 * Just load them directly from the VMCS here.
7062 */
7063 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
7064 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
7065 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
7066 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
7067 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
7068 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
7069 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
7070 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
7071 }
7072 else
7073 {
7074 /*
7075 * Without EPT, we must load the PAE PDPTEs referenced by CR3.
7076 * This involves loading (and mapping) CR3 and validating them now.
7077 */
7078 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7079 if (RT_SUCCESS(rc))
7080 { /* likely */ }
7081 else
7082 {
7083 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7084 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7085 }
7086 }
7087 }
7088
7089 /* VPID is irrelevant. We don't support VPID yet. */
7090
7091 /* Clear address-range monitoring. */
7092 EMMonitorWaitClear(pVCpu);
7093
7094 return VINF_SUCCESS;
7095}
7096
7097
7098/**
7099 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7100 *
7101 * @param pVCpu The cross context virtual CPU structure.
7102 * @param pszInstr The VMX instruction name (for logging purposes).
7103 *
7104 * @remarks This assumes various VMCS related data structure pointers have already
7105 * been verified prior to calling this function.
7106 */
7107static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7108{
7109 const char *const pszFailure = "VM-exit";
7110 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7111
7112 /*
7113 * Virtualize APIC accesses.
7114 */
7115 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7116 {
7117 /* APIC-access physical address. */
7118 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7119
7120 /*
7121 * Register the handler for the APIC-access page.
7122 *
7123 * We don't deregister the APIC-access page handler during the VM-exit as a different
7124 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7125 *
7126 * We leave the page registered until the first access that happens outside VMX non-root
7127 * mode. Guest software is allowed to access structures such as the APIC-access page
7128 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7129 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7130 *
7131 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7132 */
7133 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
7134 {
7135 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7136 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
7137 pVM->iem.s.hVmxApicAccessPage, 0 /*uUser*/, NULL /*pszDesc*/);
7138 if (RT_SUCCESS(rc))
7139 { /* likely */ }
7140 else
7141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7142 }
7143 }
7144
7145 /*
7146 * VMCS shadowing.
7147 */
7148 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7149 {
7150 /* Read the VMREAD-bitmap. */
7151 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7152 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7153 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7154 if (RT_SUCCESS(rc))
7155 { /* likely */ }
7156 else
7157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7158
7159 /* Read the VMWRITE-bitmap. */
7160 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7161 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7162 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7163 if (RT_SUCCESS(rc))
7164 { /* likely */ }
7165 else
7166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7167 }
7168
7169 /*
7170 * I/O bitmaps.
7171 */
7172 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7173 {
7174 /* Read the IO bitmap A. */
7175 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7176 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7177 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7178 if (RT_SUCCESS(rc))
7179 { /* likely */ }
7180 else
7181 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7182
7183 /* Read the IO bitmap B. */
7184 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7185 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7186 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7187 if (RT_SUCCESS(rc))
7188 { /* likely */ }
7189 else
7190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7191 }
7192
7193 /*
7194 * TPR shadow and Virtual-APIC page.
7195 */
7196 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7197 {
7198 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7199 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7200 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7201 {
7202 /* Read the VTPR from the virtual-APIC page. */
7203 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7204 uint8_t u8VTpr;
7205 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7206 if (RT_SUCCESS(rc))
7207 { /* likely */ }
7208 else
7209 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7210
7211 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7212 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7213 { /* likely */ }
7214 else
7215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7216 }
7217 }
7218
7219 /*
7220 * VMCS link pointer.
7221 */
7222 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7223 {
7224 /* Read the VMCS-link pointer from guest memory. */
7225 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7226 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7227 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7228 if (RT_SUCCESS(rc))
7229 { /* likely */ }
7230 else
7231 {
7232 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7234 }
7235
7236 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7237 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7238 { /* likely */ }
7239 else
7240 {
7241 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7243 }
7244
7245 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7246 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7247 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7248 { /* likely */ }
7249 else
7250 {
7251 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7253 }
7254
7255 /* Update our cache of the guest physical address of the shadow VMCS. */
7256 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7257 }
7258
7259 /*
7260 * MSR bitmap.
7261 */
7262 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7263 {
7264 /* Read the MSR bitmap. */
7265 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7266 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7267 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7268 if (RT_SUCCESS(rc))
7269 { /* likely */ }
7270 else
7271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7272 }
7273
7274 NOREF(pszFailure);
7275 NOREF(pszInstr);
7276 return VINF_SUCCESS;
7277}
7278
7279
7280/**
7281 * Loads the guest-state as part of VM-entry.
7282 *
7283 * @returns VBox status code.
7284 * @param pVCpu The cross context virtual CPU structure.
7285 * @param pszInstr The VMX instruction name (for logging purposes).
7286 *
7287 * @remarks This must be done after all the necessary steps prior to loading of
7288 * guest-state (e.g. checking various VMCS state).
7289 */
7290static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7291{
7292 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7293 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7294
7295 /* Load guest segment registers. */
7296 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7297
7298 /*
7299 * Load guest RIP, RSP and RFLAGS.
7300 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7301 */
7302 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7303 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7304 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7305 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7306
7307 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7308 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7309 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7310
7311 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7312 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7313 if (rc == VINF_SUCCESS)
7314 { /* likely */ }
7315 else
7316 return rc;
7317
7318 /* Load VMX related structures and state referenced by the VMCS. */
7319 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7320 if (rc == VINF_SUCCESS)
7321 { /* likely */ }
7322 else
7323 return rc;
7324
7325 NOREF(pszInstr);
7326 return VINF_SUCCESS;
7327}
7328
7329
7330/**
7331 * Returns whether there are is a pending debug exception on VM-entry.
7332 *
7333 * @param pVCpu The cross context virtual CPU structure.
7334 * @param pszInstr The VMX instruction name (for logging purposes).
7335 */
7336static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7337{
7338 /*
7339 * Pending debug exceptions.
7340 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7341 */
7342 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7343 Assert(pVmcs);
7344
7345 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7346 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7347 if (fPendingDbgXcpt)
7348 {
7349 uint8_t uEntryIntInfoType;
7350 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7351 if (fEntryVectoring)
7352 {
7353 switch (uEntryIntInfoType)
7354 {
7355 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7356 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7357 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7358 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7359 fPendingDbgXcpt = false;
7360 break;
7361
7362 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7363 {
7364 /*
7365 * Whether the pending debug exception for software exceptions other than
7366 * #BP and #OF is delivered after injecting the exception or is discard
7367 * is CPU implementation specific. We will discard them (easier).
7368 */
7369 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7370 if ( uVector != X86_XCPT_BP
7371 && uVector != X86_XCPT_OF)
7372 fPendingDbgXcpt = false;
7373 RT_FALL_THRU();
7374 }
7375 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7376 {
7377 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7378 fPendingDbgXcpt = false;
7379 break;
7380 }
7381 }
7382 }
7383 else
7384 {
7385 /*
7386 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7387 * pending debug exception is held pending or is discarded is CPU implementation
7388 * specific. We will discard them (easier).
7389 */
7390 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7391 fPendingDbgXcpt = false;
7392
7393 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7394 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7395 fPendingDbgXcpt = false;
7396 }
7397 }
7398
7399 NOREF(pszInstr);
7400 return fPendingDbgXcpt;
7401}
7402
7403
7404/**
7405 * Set up the monitor-trap flag (MTF).
7406 *
7407 * @param pVCpu The cross context virtual CPU structure.
7408 * @param pszInstr The VMX instruction name (for logging purposes).
7409 */
7410static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7411{
7412 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7413 Assert(pVmcs);
7414 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7415 {
7416 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7417 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7418 }
7419 else
7420 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7421 NOREF(pszInstr);
7422}
7423
7424
7425/**
7426 * Sets up NMI-window exiting.
7427 *
7428 * @param pVCpu The cross context virtual CPU structure.
7429 * @param pszInstr The VMX instruction name (for logging purposes).
7430 */
7431static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7432{
7433 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7434 Assert(pVmcs);
7435 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7436 {
7437 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7438 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7439 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7440 }
7441 else
7442 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7443 NOREF(pszInstr);
7444}
7445
7446
7447/**
7448 * Sets up interrupt-window exiting.
7449 *
7450 * @param pVCpu The cross context virtual CPU structure.
7451 * @param pszInstr The VMX instruction name (for logging purposes).
7452 */
7453static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7454{
7455 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7456 Assert(pVmcs);
7457 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7458 {
7459 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7460 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7461 }
7462 else
7463 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7464 NOREF(pszInstr);
7465}
7466
7467
7468/**
7469 * Set up the VMX-preemption timer.
7470 *
7471 * @param pVCpu The cross context virtual CPU structure.
7472 * @param pszInstr The VMX instruction name (for logging purposes).
7473 */
7474static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7475{
7476 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7477 Assert(pVmcs);
7478 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7479 {
7480 /*
7481 * If the timer is 0, we must cause a VM-exit before executing the first
7482 * nested-guest instruction. So we can flag as though the timer has already
7483 * expired and we will check and cause a VM-exit at the right priority elsewhere
7484 * in the code.
7485 */
7486 uint64_t uEntryTick;
7487 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7488 if (uPreemptTimer)
7489 {
7490 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7491 AssertRC(rc);
7492 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7493 }
7494 else
7495 {
7496 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7497 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7498 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7499 }
7500
7501 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7502 }
7503 else
7504 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7505
7506 NOREF(pszInstr);
7507}
7508
7509
7510/**
7511 * Injects an event using TRPM given a VM-entry interruption info. and related
7512 * fields.
7513 *
7514 * @param pVCpu The cross context virtual CPU structure.
7515 * @param pszInstr The VMX instruction name (for logging purposes).
7516 * @param uEntryIntInfo The VM-entry interruption info.
7517 * @param uErrCode The error code associated with the event if any.
7518 * @param cbInstr The VM-entry instruction length (for software
7519 * interrupts and software exceptions). Pass 0
7520 * otherwise.
7521 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7522 */
7523static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7524 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7525{
7526 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7527
7528 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7529 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7530 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7531
7532 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7533
7534 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7535 AssertRC(rc);
7536 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7537
7538 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7539 {
7540 TRPMSetErrorCode(pVCpu, uErrCode);
7541 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7542 }
7543
7544 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7545 {
7546 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7547 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7548 }
7549 else
7550 {
7551 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7552 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7553 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7554 {
7555 TRPMSetInstrLength(pVCpu, cbInstr);
7556 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7557 }
7558 }
7559
7560 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7561 {
7562 TRPMSetTrapDueToIcebp(pVCpu);
7563 Log(("%s: Injecting: icebp\n", pszInstr));
7564 }
7565
7566 NOREF(pszInstr);
7567}
7568
7569
7570/**
7571 * Performs event injection (if any) as part of VM-entry.
7572 *
7573 * @param pVCpu The cross context virtual CPU structure.
7574 * @param pszInstr The VMX instruction name (for logging purposes).
7575 */
7576static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7577{
7578 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7579
7580 /*
7581 * Inject events.
7582 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7583 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7584 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7585 * the actually delivery of this event.
7586 *
7587 * See Intel spec. 26.5 "Event Injection".
7588 */
7589 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7590 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7591
7592 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7593 if (fEntryIntInfoValid)
7594 {
7595 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7596 {
7597 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7598 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7599 }
7600 else
7601 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7602 pVCpu->cpum.GstCtx.cr2);
7603
7604 /*
7605 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7606 *
7607 * However, we do it here on VM-entry as well because while it isn't visible to guest
7608 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7609 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7610 *
7611 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7612 */
7613 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7614 }
7615 else
7616 {
7617 /*
7618 * Inject any pending guest debug exception.
7619 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7620 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7621 */
7622 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7623 if (fPendingDbgXcpt)
7624 {
7625 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7626 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7627 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7628 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7629 0 /* GCPtrFaultAddress */);
7630 }
7631 }
7632
7633 NOREF(pszInstr);
7634}
7635
7636
7637/**
7638 * Initializes all read-only VMCS fields as part of VM-entry.
7639 *
7640 * @param pVCpu The cross context virtual CPU structure.
7641 */
7642static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7643{
7644 /*
7645 * Any VMCS field which we do not establish on every VM-exit but may potentially
7646 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7647 * specified to be undefined, needs to be initialized here.
7648 *
7649 * Thus, it is especially important to clear the Exit qualification field
7650 * since it must be zero for VM-exits where it is not used. Similarly, the
7651 * VM-exit interruption information field's valid bit needs to be cleared for
7652 * the same reasons.
7653 */
7654 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7655 Assert(pVmcs);
7656
7657 /* 16-bit (none currently). */
7658 /* 32-bit. */
7659 pVmcs->u32RoVmInstrError = 0;
7660 pVmcs->u32RoExitReason = 0;
7661 pVmcs->u32RoExitIntInfo = 0;
7662 pVmcs->u32RoExitIntErrCode = 0;
7663 pVmcs->u32RoIdtVectoringInfo = 0;
7664 pVmcs->u32RoIdtVectoringErrCode = 0;
7665 pVmcs->u32RoExitInstrLen = 0;
7666 pVmcs->u32RoExitInstrInfo = 0;
7667
7668 /* 64-bit. */
7669 pVmcs->u64RoGuestPhysAddr.u = 0;
7670
7671 /* Natural-width. */
7672 pVmcs->u64RoExitQual.u = 0;
7673 pVmcs->u64RoIoRcx.u = 0;
7674 pVmcs->u64RoIoRsi.u = 0;
7675 pVmcs->u64RoIoRdi.u = 0;
7676 pVmcs->u64RoIoRip.u = 0;
7677 pVmcs->u64RoGuestLinearAddr.u = 0;
7678}
7679
7680
7681/**
7682 * VMLAUNCH/VMRESUME instruction execution worker.
7683 *
7684 * @returns Strict VBox status code.
7685 * @param pVCpu The cross context virtual CPU structure.
7686 * @param cbInstr The instruction length in bytes.
7687 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7688 * VMXINSTRID_VMRESUME).
7689 *
7690 * @remarks Common VMX instruction checks are already expected to by the caller,
7691 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7692 */
7693static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7694{
7695# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7696 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7697 return VINF_EM_RAW_EMULATE_INSTR;
7698# else
7699 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7700 || uInstrId == VMXINSTRID_VMRESUME);
7701 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7702
7703 /* Nested-guest intercept. */
7704 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7705 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7706
7707 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7708
7709 /*
7710 * Basic VM-entry checks.
7711 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7712 * The checks following that do not have to follow a specific order.
7713 *
7714 * See Intel spec. 26.1 "Basic VM-entry Checks".
7715 */
7716
7717 /* CPL. */
7718 if (pVCpu->iem.s.uCpl == 0)
7719 { /* likely */ }
7720 else
7721 {
7722 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7723 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7724 return iemRaiseGeneralProtectionFault0(pVCpu);
7725 }
7726
7727 /* Current VMCS valid. */
7728 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7729 { /* likely */ }
7730 else
7731 {
7732 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7733 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7734 iemVmxVmFailInvalid(pVCpu);
7735 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7736 return VINF_SUCCESS;
7737 }
7738
7739 /* Current VMCS is not a shadow VMCS. */
7740 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7741 { /* likely */ }
7742 else
7743 {
7744 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7745 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7746 iemVmxVmFailInvalid(pVCpu);
7747 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7748 return VINF_SUCCESS;
7749 }
7750
7751 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7752 * use block-by-STI here which is not quite correct. */
7753 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7754 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7755 { /* likely */ }
7756 else
7757 {
7758 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7759 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7760 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7761 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7762 return VINF_SUCCESS;
7763 }
7764
7765 if (uInstrId == VMXINSTRID_VMLAUNCH)
7766 {
7767 /* VMLAUNCH with non-clear VMCS. */
7768 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7769 { /* likely */ }
7770 else
7771 {
7772 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7773 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7774 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7775 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7776 return VINF_SUCCESS;
7777 }
7778 }
7779 else
7780 {
7781 /* VMRESUME with non-launched VMCS. */
7782 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7783 { /* likely */ }
7784 else
7785 {
7786 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7787 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7788 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7789 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7790 return VINF_SUCCESS;
7791 }
7792 }
7793
7794 /*
7795 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7796 * while entering VMX non-root mode. We do some of this while checking VM-execution
7797 * controls. The nested hypervisor should not make assumptions and cannot expect
7798 * predictable behavior if changes to these structures are made in guest memory while
7799 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7800 * modify them anyway as we cache them in host memory.
7801 *
7802 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7803 */
7804 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7805 Assert(pVmcs);
7806 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7807
7808 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7809 if (RT_SUCCESS(rc))
7810 {
7811 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7812 if (RT_SUCCESS(rc))
7813 {
7814 /*
7815 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7816 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7817 * ones that may occur during VM-entry below).
7818 */
7819 iemVmxVmentryInitReadOnlyFields(pVCpu);
7820
7821 /*
7822 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7823 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7824 * VM-exit when required.
7825 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7826 */
7827 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7828
7829 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7830 if (RT_SUCCESS(rc))
7831 {
7832 /*
7833 * We've now entered nested-guest execution.
7834 *
7835 * It is important do this prior to loading the guest state because
7836 * as part of loading the guest state, PGM (and perhaps other components
7837 * in the future) relies on detecting whether VMX non-root mode has been
7838 * entered.
7839 */
7840 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7841
7842 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7843 if (RT_SUCCESS(rc))
7844 {
7845 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7846 if (RT_SUCCESS(rc))
7847 {
7848 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7849
7850 /* VMLAUNCH instruction must update the VMCS launch state. */
7851 if (uInstrId == VMXINSTRID_VMLAUNCH)
7852 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7853
7854 /* Perform the VMX transition (PGM updates). */
7855 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7856 if (rcStrict == VINF_SUCCESS)
7857 { /* likely */ }
7858 else if (RT_SUCCESS(rcStrict))
7859 {
7860 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7861 VBOXSTRICTRC_VAL(rcStrict)));
7862 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7863 }
7864 else
7865 {
7866 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7867 return rcStrict;
7868 }
7869
7870 /* Paranoia. */
7871 Assert(rcStrict == VINF_SUCCESS);
7872
7873 /*
7874 * The priority of potential VM-exits during VM-entry is important.
7875 * The priorities of VM-exits and events are listed from highest
7876 * to lowest as follows:
7877 *
7878 * 1. Event injection.
7879 * 2. Trap on task-switch (T flag set in TSS).
7880 * 3. TPR below threshold / APIC-write.
7881 * 4. SMI, INIT.
7882 * 5. MTF exit.
7883 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7884 * 7. VMX-preemption timer.
7885 * 9. NMI-window exit.
7886 * 10. NMI injection.
7887 * 11. Interrupt-window exit.
7888 * 12. Virtual-interrupt injection.
7889 * 13. Interrupt injection.
7890 * 14. Process next instruction (fetch, decode, execute).
7891 */
7892
7893 /* Setup VMX-preemption timer. */
7894 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7895
7896 /* Setup monitor-trap flag. */
7897 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7898
7899 /* Setup NMI-window exiting. */
7900 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7901
7902 /* Setup interrupt-window exiting. */
7903 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7904
7905 /*
7906 * Inject any event that the nested hypervisor wants to inject.
7907 * Note! We cannot immediately perform the event injection here as we may have
7908 * pending PGM operations to perform due to switching page tables and/or
7909 * mode.
7910 */
7911 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7912
7913# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7914 /* Reschedule to IEM-only execution of the nested-guest. */
7915 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7916 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7917 if (rcSched != VINF_SUCCESS)
7918 iemSetPassUpStatus(pVCpu, rcSched);
7919# endif
7920
7921 /* Finally, done. */
7922 LogFlow(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7923 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7924 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7925 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7926 return VINF_SUCCESS;
7927 }
7928 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7929 }
7930 }
7931 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7932 }
7933
7934 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7935 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7936 return VINF_SUCCESS;
7937 }
7938
7939 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7940 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7941 return VINF_SUCCESS;
7942# endif
7943}
7944
7945
7946/**
7947 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7948 *
7949 * @returns Strict VBox status code.
7950 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7951 * @param cbInstr The instruction length in bytes.
7952 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7953 * VMXINSTRID_VMRESUME).
7954 * @thread EMT(pVCpu)
7955 */
7956VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7957{
7958 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7959 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7960
7961 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7962 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7963 Assert(!pVCpu->iem.s.cActiveMappings);
7964 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
7965}
7966
7967
7968/**
7969 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7970 * (causes a VM-exit) or not.
7971 *
7972 * @returns @c true if the instruction is intercepted, @c false otherwise.
7973 * @param pVCpu The cross context virtual CPU structure.
7974 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7975 * VMX_EXIT_WRMSR).
7976 * @param idMsr The MSR.
7977 */
7978bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
7979{
7980 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7981 Assert( uExitReason == VMX_EXIT_RDMSR
7982 || uExitReason == VMX_EXIT_WRMSR);
7983
7984 /* Consult the MSR bitmap if the feature is supported. */
7985 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7986 Assert(pVmcs);
7987 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7988 {
7989 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7990 if (uExitReason == VMX_EXIT_RDMSR)
7991 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7992 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7993 }
7994
7995 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7996 return true;
7997}
7998
7999
8000/**
8001 * VMREAD instruction execution worker that does not perform any validation checks.
8002 *
8003 * Callers are expected to have performed the necessary checks and to ensure the
8004 * VMREAD will succeed.
8005 *
8006 * @param pVmcs Pointer to the virtual VMCS.
8007 * @param pu64Dst Where to write the VMCS value.
8008 * @param u64VmcsField The VMCS field.
8009 *
8010 * @remarks May be called with interrupts disabled.
8011 */
8012static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8013{
8014 VMXVMCSFIELD VmcsField;
8015 VmcsField.u = u64VmcsField;
8016 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8017 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8018 uint8_t const uWidthType = (uWidth << 2) | uType;
8019 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8020 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8021 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8022 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8023 uWidth, uType, uIndex, uIndex));
8024 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8025
8026 /*
8027 * Read the VMCS component based on the field's effective width.
8028 *
8029 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8030 * indicates high bits (little endian).
8031 *
8032 * Note! The caller is responsible to trim the result and update registers
8033 * or memory locations are required. Here we just zero-extend to the largest
8034 * type (i.e. 64-bits).
8035 */
8036 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8037 uint8_t const *pbField = pbVmcs + offField;
8038 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8039 switch (uEffWidth)
8040 {
8041 case VMX_VMCSFIELD_WIDTH_64BIT:
8042 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8043 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8044 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8045 }
8046}
8047
8048/**
8049 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8050 *
8051 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8052 * are performed. Bounds checks are strict builds only.
8053 *
8054 * @param pVmcs Pointer to the virtual VMCS.
8055 * @param u64VmcsField The VMCS field.
8056 * @param pu64Dst Where to store the VMCS value.
8057 *
8058 * @remarks May be called with interrupts disabled.
8059 * @todo This should probably be moved to CPUM someday.
8060 */
8061VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8062{
8063 AssertPtr(pVmcs);
8064 AssertPtr(pu64Dst);
8065 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8066}
8067
8068
8069/**
8070 * VMREAD common (memory/register) instruction execution worker.
8071 *
8072 * @returns Strict VBox status code.
8073 * @param pVCpu The cross context virtual CPU structure.
8074 * @param cbInstr The instruction length in bytes.
8075 * @param pu64Dst Where to write the VMCS value (only updated when
8076 * VINF_SUCCESS is returned).
8077 * @param u64VmcsField The VMCS field.
8078 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8079 * NULL.
8080 */
8081static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8082 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8083{
8084 /* Nested-guest intercept. */
8085 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8086 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8087 {
8088 if (pExitInfo)
8089 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8090 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8091 }
8092
8093 /* CPL. */
8094 if (pVCpu->iem.s.uCpl == 0)
8095 { /* likely */ }
8096 else
8097 {
8098 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8099 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8100 return iemRaiseGeneralProtectionFault0(pVCpu);
8101 }
8102
8103 /* VMCS pointer in root mode. */
8104 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8105 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8106 { /* likely */ }
8107 else
8108 {
8109 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8110 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8111 iemVmxVmFailInvalid(pVCpu);
8112 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8113 return VINF_SUCCESS;
8114 }
8115
8116 /* VMCS-link pointer in non-root mode. */
8117 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8118 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8119 { /* likely */ }
8120 else
8121 {
8122 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8123 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8124 iemVmxVmFailInvalid(pVCpu);
8125 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8126 return VINF_SUCCESS;
8127 }
8128
8129 /* Supported VMCS field. */
8130 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8131 { /* likely */ }
8132 else
8133 {
8134 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8135 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8136 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8137 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8138 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8139 return VINF_SUCCESS;
8140 }
8141
8142 /*
8143 * Reading from the current or shadow VMCS.
8144 */
8145 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8146 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8147 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8148 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8149 return VINF_SUCCESS;
8150}
8151
8152
8153/**
8154 * VMREAD (64-bit register) instruction execution worker.
8155 *
8156 * @returns Strict VBox status code.
8157 * @param pVCpu The cross context virtual CPU structure.
8158 * @param cbInstr The instruction length in bytes.
8159 * @param pu64Dst Where to store the VMCS field's value.
8160 * @param u64VmcsField The VMCS field.
8161 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8162 * NULL.
8163 */
8164static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8165 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8166{
8167 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8168 if (rcStrict == VINF_SUCCESS)
8169 {
8170 iemVmxVmSucceed(pVCpu);
8171 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8172 return VINF_SUCCESS;
8173 }
8174
8175 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8176 return rcStrict;
8177}
8178
8179
8180/**
8181 * VMREAD (32-bit register) instruction execution worker.
8182 *
8183 * @returns Strict VBox status code.
8184 * @param pVCpu The cross context virtual CPU structure.
8185 * @param cbInstr The instruction length in bytes.
8186 * @param pu32Dst Where to store the VMCS field's value.
8187 * @param u32VmcsField The VMCS field.
8188 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8189 * NULL.
8190 */
8191static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8192 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8193{
8194 uint64_t u64Dst;
8195 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8196 if (rcStrict == VINF_SUCCESS)
8197 {
8198 *pu32Dst = u64Dst;
8199 iemVmxVmSucceed(pVCpu);
8200 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8201 return VINF_SUCCESS;
8202 }
8203
8204 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8205 return rcStrict;
8206}
8207
8208
8209/**
8210 * VMREAD (memory) instruction execution worker.
8211 *
8212 * @returns Strict VBox status code.
8213 * @param pVCpu The cross context virtual CPU structure.
8214 * @param cbInstr The instruction length in bytes.
8215 * @param iEffSeg The effective segment register to use with @a u64Val.
8216 * Pass UINT8_MAX if it is a register access.
8217 * @param GCPtrDst The guest linear address to store the VMCS field's
8218 * value.
8219 * @param u64VmcsField The VMCS field.
8220 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8221 * NULL.
8222 */
8223static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8224 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8225{
8226 uint64_t u64Dst;
8227 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8228 if (rcStrict == VINF_SUCCESS)
8229 {
8230 /*
8231 * Write the VMCS field's value to the location specified in guest-memory.
8232 */
8233 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8234 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8235 else
8236 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8237 if (rcStrict == VINF_SUCCESS)
8238 {
8239 iemVmxVmSucceed(pVCpu);
8240 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8241 return VINF_SUCCESS;
8242 }
8243
8244 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8245 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8246 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8247 return rcStrict;
8248 }
8249
8250 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8251 return rcStrict;
8252}
8253
8254
8255/**
8256 * Interface for HM and EM to emulate the VMREAD instruction.
8257 *
8258 * @returns Strict VBox status code.
8259 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8260 * @param pExitInfo Pointer to the VM-exit information.
8261 * @thread EMT(pVCpu)
8262 */
8263VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8264{
8265 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8266 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8267 Assert(pExitInfo);
8268
8269 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8270
8271 VBOXSTRICTRC rcStrict;
8272 uint8_t const cbInstr = pExitInfo->cbInstr;
8273 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8274 uint64_t const u64FieldEnc = fIs64BitMode
8275 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8276 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8277 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8278 {
8279 if (fIs64BitMode)
8280 {
8281 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8282 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8283 }
8284 else
8285 {
8286 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8287 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8288 }
8289 }
8290 else
8291 {
8292 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8293 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8294 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8295 }
8296 Assert(!pVCpu->iem.s.cActiveMappings);
8297 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8298}
8299
8300
8301/**
8302 * VMWRITE instruction execution worker that does not perform any validation
8303 * checks.
8304 *
8305 * Callers are expected to have performed the necessary checks and to ensure the
8306 * VMWRITE will succeed.
8307 *
8308 * @param pVmcs Pointer to the virtual VMCS.
8309 * @param u64Val The value to write.
8310 * @param u64VmcsField The VMCS field.
8311 *
8312 * @remarks May be called with interrupts disabled.
8313 */
8314static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8315{
8316 VMXVMCSFIELD VmcsField;
8317 VmcsField.u = u64VmcsField;
8318 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8319 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8320 uint8_t const uWidthType = (uWidth << 2) | uType;
8321 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8322 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8323 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8324 Assert(offField < VMX_V_VMCS_SIZE);
8325 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8326
8327 /*
8328 * Write the VMCS component based on the field's effective width.
8329 *
8330 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8331 * indicates high bits (little endian).
8332 */
8333 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8334 uint8_t *pbField = pbVmcs + offField;
8335 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8336 switch (uEffWidth)
8337 {
8338 case VMX_VMCSFIELD_WIDTH_64BIT:
8339 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8340 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8341 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8342 }
8343}
8344
8345
8346/**
8347 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8348 *
8349 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8350 * are performed. Bounds checks are strict builds only.
8351 *
8352 * @param pVmcs Pointer to the virtual VMCS.
8353 * @param u64VmcsField The VMCS field.
8354 * @param u64Val The value to write.
8355 *
8356 * @remarks May be called with interrupts disabled.
8357 * @todo This should probably be moved to CPUM someday.
8358 */
8359VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8360{
8361 AssertPtr(pVmcs);
8362 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8363}
8364
8365
8366/**
8367 * VMWRITE instruction execution worker.
8368 *
8369 * @returns Strict VBox status code.
8370 * @param pVCpu The cross context virtual CPU structure.
8371 * @param cbInstr The instruction length in bytes.
8372 * @param iEffSeg The effective segment register to use with @a u64Val.
8373 * Pass UINT8_MAX if it is a register access.
8374 * @param u64Val The value to write (or guest linear address to the
8375 * value), @a iEffSeg will indicate if it's a memory
8376 * operand.
8377 * @param u64VmcsField The VMCS field.
8378 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8379 * NULL.
8380 */
8381static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8382 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8383{
8384 /* Nested-guest intercept. */
8385 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8386 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8387 {
8388 if (pExitInfo)
8389 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8390 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8391 }
8392
8393 /* CPL. */
8394 if (pVCpu->iem.s.uCpl == 0)
8395 { /* likely */ }
8396 else
8397 {
8398 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8399 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8400 return iemRaiseGeneralProtectionFault0(pVCpu);
8401 }
8402
8403 /* VMCS pointer in root mode. */
8404 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8405 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8406 { /* likely */ }
8407 else
8408 {
8409 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8410 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8411 iemVmxVmFailInvalid(pVCpu);
8412 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8413 return VINF_SUCCESS;
8414 }
8415
8416 /* VMCS-link pointer in non-root mode. */
8417 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8418 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8419 { /* likely */ }
8420 else
8421 {
8422 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8423 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8424 iemVmxVmFailInvalid(pVCpu);
8425 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8426 return VINF_SUCCESS;
8427 }
8428
8429 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8430 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8431 if (!fIsRegOperand)
8432 {
8433 /* Read the value from the specified guest memory location. */
8434 VBOXSTRICTRC rcStrict;
8435 RTGCPTR const GCPtrVal = u64Val;
8436 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8437 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8438 else
8439 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8440 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8441 {
8442 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8443 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8444 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8445 return rcStrict;
8446 }
8447 }
8448 else
8449 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8450
8451 /* Supported VMCS field. */
8452 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8453 { /* likely */ }
8454 else
8455 {
8456 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8457 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8458 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8459 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8460 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8461 return VINF_SUCCESS;
8462 }
8463
8464 /* Read-only VMCS field. */
8465 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8466 if ( !fIsFieldReadOnly
8467 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8468 { /* likely */ }
8469 else
8470 {
8471 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8472 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8473 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8474 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8475 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8476 return VINF_SUCCESS;
8477 }
8478
8479 /*
8480 * Write to the current or shadow VMCS.
8481 */
8482 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8483 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8484 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8485 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8486 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8487
8488 if ( !fInVmxNonRootMode
8489 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8490 {
8491 /* Notify HM that the VMCS content might have changed. */
8492 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8493 }
8494
8495 iemVmxVmSucceed(pVCpu);
8496 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8497 return VINF_SUCCESS;
8498}
8499
8500
8501/**
8502 * Interface for HM and EM to emulate the VMWRITE instruction.
8503 *
8504 * @returns Strict VBox status code.
8505 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8506 * @param pExitInfo Pointer to the VM-exit information.
8507 * @thread EMT(pVCpu)
8508 */
8509VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8510{
8511 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8512 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8513 Assert(pExitInfo);
8514
8515 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8516
8517 uint64_t u64Val;
8518 uint8_t iEffSeg;
8519 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8520 {
8521 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8522 iEffSeg = UINT8_MAX;
8523 }
8524 else
8525 {
8526 u64Val = pExitInfo->GCPtrEffAddr;
8527 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8528 }
8529 uint8_t const cbInstr = pExitInfo->cbInstr;
8530 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8531 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8532 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8533 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8534 Assert(!pVCpu->iem.s.cActiveMappings);
8535 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8536}
8537
8538
8539/**
8540 * VMCLEAR instruction execution worker.
8541 *
8542 * @returns Strict VBox status code.
8543 * @param pVCpu The cross context virtual CPU structure.
8544 * @param cbInstr The instruction length in bytes.
8545 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8546 * @param GCPtrVmcs The linear address of the VMCS pointer.
8547 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8548 *
8549 * @remarks Common VMX instruction checks are already expected to by the caller,
8550 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8551 */
8552static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8553 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8554{
8555 /* Nested-guest intercept. */
8556 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8557 {
8558 if (pExitInfo)
8559 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8560 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8561 }
8562
8563 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8564
8565 /* CPL. */
8566 if (pVCpu->iem.s.uCpl == 0)
8567 { /* likely */ }
8568 else
8569 {
8570 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8571 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8572 return iemRaiseGeneralProtectionFault0(pVCpu);
8573 }
8574
8575 /* Get the VMCS pointer from the location specified by the source memory operand. */
8576 RTGCPHYS GCPhysVmcs;
8577 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8578 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8579 { /* likely */ }
8580 else
8581 {
8582 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8583 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8584 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8585 return rcStrict;
8586 }
8587
8588 /* VMCS pointer alignment. */
8589 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8590 { /* likely */ }
8591 else
8592 {
8593 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8594 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8595 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8596 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8597 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8598 return VINF_SUCCESS;
8599 }
8600
8601 /* VMCS physical-address width limits. */
8602 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8603 { /* likely */ }
8604 else
8605 {
8606 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8607 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8608 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8609 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8610 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8611 return VINF_SUCCESS;
8612 }
8613
8614 /* VMCS is not the VMXON region. */
8615 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8616 { /* likely */ }
8617 else
8618 {
8619 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8620 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8621 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8622 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8623 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8624 return VINF_SUCCESS;
8625 }
8626
8627 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8628 restriction imposed by our implementation. */
8629 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8630 { /* likely */ }
8631 else
8632 {
8633 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8634 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8635 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8636 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8637 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8638 return VINF_SUCCESS;
8639 }
8640
8641 /*
8642 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8643 *
8644 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8645 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8646 * to 'clear'.
8647 */
8648 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8649 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8650 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8651 {
8652 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8653 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8654 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8655 }
8656 else
8657 {
8658 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8659 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8660 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8661 if (RT_FAILURE(rcStrict))
8662 return rcStrict;
8663 }
8664
8665 iemVmxVmSucceed(pVCpu);
8666 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8667 return VINF_SUCCESS;
8668}
8669
8670
8671/**
8672 * Interface for HM and EM to emulate the VMCLEAR instruction.
8673 *
8674 * @returns Strict VBox status code.
8675 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8676 * @param pExitInfo Pointer to the VM-exit information.
8677 * @thread EMT(pVCpu)
8678 */
8679VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8680{
8681 Assert(pExitInfo);
8682 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8683 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8684
8685 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8686
8687 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8688 uint8_t const cbInstr = pExitInfo->cbInstr;
8689 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8690 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8691 Assert(!pVCpu->iem.s.cActiveMappings);
8692 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8693}
8694
8695
8696/**
8697 * VMPTRST instruction execution worker.
8698 *
8699 * @returns Strict VBox status code.
8700 * @param pVCpu The cross context virtual CPU structure.
8701 * @param cbInstr The instruction length in bytes.
8702 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8703 * @param GCPtrVmcs The linear address of where to store the current VMCS
8704 * pointer.
8705 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8706 *
8707 * @remarks Common VMX instruction checks are already expected to by the caller,
8708 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8709 */
8710static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8711 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8712{
8713 /* Nested-guest intercept. */
8714 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8715 {
8716 if (pExitInfo)
8717 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8718 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8719 }
8720
8721 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8722
8723 /* CPL. */
8724 if (pVCpu->iem.s.uCpl == 0)
8725 { /* likely */ }
8726 else
8727 {
8728 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8729 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8730 return iemRaiseGeneralProtectionFault0(pVCpu);
8731 }
8732
8733 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8734 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8735 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8736 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8737 {
8738 iemVmxVmSucceed(pVCpu);
8739 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8740 return rcStrict;
8741 }
8742
8743 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8744 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8745 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8746 return rcStrict;
8747}
8748
8749
8750/**
8751 * Interface for HM and EM to emulate the VMPTRST instruction.
8752 *
8753 * @returns Strict VBox status code.
8754 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8755 * @param pExitInfo Pointer to the VM-exit information.
8756 * @thread EMT(pVCpu)
8757 */
8758VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8759{
8760 Assert(pExitInfo);
8761 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8762 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8763
8764 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8765
8766 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8767 uint8_t const cbInstr = pExitInfo->cbInstr;
8768 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8769 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8770 Assert(!pVCpu->iem.s.cActiveMappings);
8771 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8772}
8773
8774
8775/**
8776 * VMPTRLD instruction execution worker.
8777 *
8778 * @returns Strict VBox status code.
8779 * @param pVCpu The cross context virtual CPU structure.
8780 * @param cbInstr The instruction length in bytes.
8781 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8782 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8783 *
8784 * @remarks Common VMX instruction checks are already expected to by the caller,
8785 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8786 */
8787static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8788 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8789{
8790 /* Nested-guest intercept. */
8791 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8792 {
8793 if (pExitInfo)
8794 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8795 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8796 }
8797
8798 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8799
8800 /* CPL. */
8801 if (pVCpu->iem.s.uCpl == 0)
8802 { /* likely */ }
8803 else
8804 {
8805 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8806 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8807 return iemRaiseGeneralProtectionFault0(pVCpu);
8808 }
8809
8810 /* Get the VMCS pointer from the location specified by the source memory operand. */
8811 RTGCPHYS GCPhysVmcs;
8812 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8813 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8814 { /* likely */ }
8815 else
8816 {
8817 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8818 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8819 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8820 return rcStrict;
8821 }
8822
8823 /* VMCS pointer alignment. */
8824 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8825 { /* likely */ }
8826 else
8827 {
8828 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8829 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8830 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8831 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8832 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8833 return VINF_SUCCESS;
8834 }
8835
8836 /* VMCS physical-address width limits. */
8837 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8838 { /* likely */ }
8839 else
8840 {
8841 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8842 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8843 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8844 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8845 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8846 return VINF_SUCCESS;
8847 }
8848
8849 /* VMCS is not the VMXON region. */
8850 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8851 { /* likely */ }
8852 else
8853 {
8854 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8855 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8856 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8857 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8858 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8859 return VINF_SUCCESS;
8860 }
8861
8862 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8863 restriction imposed by our implementation. */
8864 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8865 { /* likely */ }
8866 else
8867 {
8868 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8869 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8870 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8871 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8872 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8873 return VINF_SUCCESS;
8874 }
8875
8876 /* Read just the VMCS revision from the VMCS. */
8877 VMXVMCSREVID VmcsRevId;
8878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8879 if (RT_SUCCESS(rc))
8880 { /* likely */ }
8881 else
8882 {
8883 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8884 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8885 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8886 return rc;
8887 }
8888
8889 /*
8890 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8891 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8892 */
8893 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8894 && ( !VmcsRevId.n.fIsShadowVmcs
8895 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8896 { /* likely */ }
8897 else
8898 {
8899 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8900 {
8901 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8902 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8903 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8904 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8905 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8906 return VINF_SUCCESS;
8907 }
8908
8909 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8910 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8911 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8912 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8913 return VINF_SUCCESS;
8914 }
8915
8916 /*
8917 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8918 * the cache of an existing, current VMCS back to guest memory before loading a new,
8919 * different current VMCS.
8920 */
8921 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8922 {
8923 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8924 {
8925 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8926 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8927 }
8928
8929 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8930 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8931 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8932 if (RT_SUCCESS(rc))
8933 {
8934 /* Notify HM that a new, current VMCS is loaded. */
8935 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8936 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8937 }
8938 else
8939 {
8940 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8941 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8942 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8943 return rc;
8944 }
8945 }
8946
8947 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8948 iemVmxVmSucceed(pVCpu);
8949 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8950 return VINF_SUCCESS;
8951}
8952
8953
8954/**
8955 * Interface for HM and EM to emulate the VMPTRLD instruction.
8956 *
8957 * @returns Strict VBox status code.
8958 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8959 * @param pExitInfo Pointer to the VM-exit information.
8960 * @thread EMT(pVCpu)
8961 */
8962VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8963{
8964 Assert(pExitInfo);
8965 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8966 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8967
8968 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8969
8970 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8971 uint8_t const cbInstr = pExitInfo->cbInstr;
8972 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8973 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8974 Assert(!pVCpu->iem.s.cActiveMappings);
8975 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8976}
8977
8978
8979/**
8980 * INVVPID instruction execution worker.
8981 *
8982 * @returns Strict VBox status code.
8983 * @param pVCpu The cross context virtual CPU structure.
8984 * @param cbInstr The instruction length in bytes.
8985 * @param iEffSeg The segment of the invvpid descriptor.
8986 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8987 * @param u64InvvpidType The invalidation type.
8988 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8989 * NULL.
8990 *
8991 * @remarks Common VMX instruction checks are already expected to by the caller,
8992 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8993 */
8994VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8995 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8996{
8997 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8998 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8999 return iemRaiseUndefinedOpcode(pVCpu);
9000
9001 /* Nested-guest intercept. */
9002 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9003 {
9004 if (pExitInfo)
9005 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9006 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
9007 }
9008
9009 /* CPL. */
9010 if (pVCpu->iem.s.uCpl != 0)
9011 {
9012 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9013 return iemRaiseGeneralProtectionFault0(pVCpu);
9014 }
9015
9016 /*
9017 * Validate INVVPID invalidation type.
9018 *
9019 * The instruction specifies exactly ONE of the supported invalidation types.
9020 *
9021 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9022 * supported. In theory, it's possible for a CPU to not support flushing individual
9023 * addresses but all the other types or any other combination. We do not take any
9024 * shortcuts here by assuming the types we currently expose to the guest.
9025 */
9026 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9027 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9028 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9029 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9030 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9031 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9032
9033 bool afSupportedTypes[4];
9034 afSupportedTypes[0] = fTypeIndivAddr;
9035 afSupportedTypes[1] = fTypeSingleCtx;
9036 afSupportedTypes[2] = fTypeAllCtx;
9037 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9038
9039 if ( fInvvpidSupported
9040 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9041 && afSupportedTypes[u64InvvpidType & 3])
9042 { /* likely */ }
9043 else
9044 {
9045 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9046 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9047 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9048 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9049 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9050 return VINF_SUCCESS;
9051 }
9052
9053 /*
9054 * Fetch the invvpid descriptor from guest memory.
9055 */
9056 RTUINT128U uDesc;
9057 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9058 if (rcStrict == VINF_SUCCESS)
9059 {
9060 /*
9061 * Validate the descriptor.
9062 */
9063 if (uDesc.s.Lo <= 0xffff)
9064 { /* likely */ }
9065 else
9066 {
9067 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9068 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9069 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9070 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9071 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9072 return VINF_SUCCESS;
9073 }
9074
9075 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9076 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9077 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
9078 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9079 switch (u64InvvpidType)
9080 {
9081 case VMXTLBFLUSHVPID_INDIV_ADDR:
9082 {
9083 if (uVpid != 0)
9084 {
9085 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9086 {
9087 /* Invalidate mappings for the linear address tagged with VPID. */
9088 /** @todo PGM support for VPID? Currently just flush everything. */
9089 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9090 iemVmxVmSucceed(pVCpu);
9091 }
9092 else
9093 {
9094 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9095 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9096 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9097 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9098 }
9099 }
9100 else
9101 {
9102 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9103 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9104 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9105 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9106 }
9107 break;
9108 }
9109
9110 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9111 {
9112 if (uVpid != 0)
9113 {
9114 /* Invalidate all mappings with VPID. */
9115 /** @todo PGM support for VPID? Currently just flush everything. */
9116 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9117 iemVmxVmSucceed(pVCpu);
9118 }
9119 else
9120 {
9121 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9122 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9123 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9124 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9125 }
9126 break;
9127 }
9128
9129 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9130 {
9131 /* Invalidate all mappings with non-zero VPIDs. */
9132 /** @todo PGM support for VPID? Currently just flush everything. */
9133 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9134 iemVmxVmSucceed(pVCpu);
9135 break;
9136 }
9137
9138 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9139 {
9140 if (uVpid != 0)
9141 {
9142 /* Invalidate all mappings with VPID except global translations. */
9143 /** @todo PGM support for VPID? Currently just flush everything. */
9144 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9145 iemVmxVmSucceed(pVCpu);
9146 }
9147 else
9148 {
9149 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9150 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9151 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9152 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9153 }
9154 break;
9155 }
9156 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9157 }
9158 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9159 }
9160 return rcStrict;
9161}
9162
9163
9164/**
9165 * Interface for HM and EM to emulate the INVVPID instruction.
9166 *
9167 * @returns Strict VBox status code.
9168 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9169 * @param pExitInfo Pointer to the VM-exit information.
9170 * @thread EMT(pVCpu)
9171 */
9172VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9173{
9174 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9175 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9176 Assert(pExitInfo);
9177
9178 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9179
9180 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9181 uint8_t const cbInstr = pExitInfo->cbInstr;
9182 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9183 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9184 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9185 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9186 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9187 Assert(!pVCpu->iem.s.cActiveMappings);
9188 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9189}
9190
9191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9192
9193/**
9194 * INVEPT instruction execution worker.
9195 *
9196 * @returns Strict VBox status code.
9197 * @param pVCpu The cross context virtual CPU structure.
9198 * @param cbInstr The instruction length in bytes.
9199 * @param iEffSeg The segment of the invept descriptor.
9200 * @param GCPtrInveptDesc The address of invept descriptor.
9201 * @param u64InveptType The invalidation type.
9202 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9203 * NULL.
9204 *
9205 * @remarks Common VMX instruction checks are already expected to by the caller,
9206 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9207 */
9208static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9209 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9210{
9211 /* Check if EPT is supported, otherwise raise #UD. */
9212 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9213 return iemRaiseUndefinedOpcode(pVCpu);
9214
9215 /* Nested-guest intercept. */
9216 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9217 {
9218 if (pExitInfo)
9219 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9220 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9221 }
9222
9223 /* CPL. */
9224 if (pVCpu->iem.s.uCpl != 0)
9225 {
9226 Log(("invept: CPL != 0 -> #GP(0)\n"));
9227 return iemRaiseGeneralProtectionFault0(pVCpu);
9228 }
9229
9230 /*
9231 * Validate INVEPT invalidation type.
9232 *
9233 * The instruction specifies exactly ONE of the supported invalidation types.
9234 *
9235 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9236 * supported. In theory, it's possible for a CPU to not support flushing individual
9237 * addresses but all the other types or any other combination. We do not take any
9238 * shortcuts here by assuming the types we currently expose to the guest.
9239 */
9240 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9241 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9242 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9243 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9244
9245 bool afSupportedTypes[4];
9246 afSupportedTypes[0] = false;
9247 afSupportedTypes[1] = fTypeSingleCtx;
9248 afSupportedTypes[2] = fTypeAllCtx;
9249 afSupportedTypes[3] = false;
9250
9251 if ( fInveptSupported
9252 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9253 && afSupportedTypes[u64InveptType & 3])
9254 { /* likely */ }
9255 else
9256 {
9257 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9258 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9259 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9260 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9261 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9262 return VINF_SUCCESS;
9263 }
9264
9265 /*
9266 * Fetch the invept descriptor from guest memory.
9267 */
9268 RTUINT128U uDesc;
9269 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9270 if (rcStrict == VINF_SUCCESS)
9271 {
9272 /*
9273 * Validate the descriptor.
9274 *
9275 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9276 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9277 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9278 * better to be strict in our emulation until proven otherwise.
9279 */
9280 if (uDesc.s.Hi)
9281 {
9282 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9283 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9284 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9285 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9286 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9287 return VINF_SUCCESS;
9288 }
9289
9290 /*
9291 * Flush TLB mappings based on the EPT type.
9292 */
9293 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9294 {
9295 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9296 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9297 if (RT_SUCCESS(rc))
9298 { /* likely */ }
9299 else
9300 {
9301 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9302 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9303 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9304 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9305 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9306 return VINF_SUCCESS;
9307 }
9308 }
9309
9310 /** @todo PGM support for EPT tags? Currently just flush everything. */
9311 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9312 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9313 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9314
9315 iemVmxVmSucceed(pVCpu);
9316 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9317 }
9318
9319 return rcStrict;
9320}
9321
9322
9323/**
9324 * Interface for HM and EM to emulate the INVEPT instruction.
9325 *
9326 * @returns Strict VBox status code.
9327 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9328 * @param pExitInfo Pointer to the VM-exit information.
9329 * @thread EMT(pVCpu)
9330 */
9331VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9332{
9333 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9334 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9335 Assert(pExitInfo);
9336
9337 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9338
9339 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9340 uint8_t const cbInstr = pExitInfo->cbInstr;
9341 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9342 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9343 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9344 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9345 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9346 Assert(!pVCpu->iem.s.cActiveMappings);
9347 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9348}
9349
9350#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9351
9352/**
9353 * VMXON instruction execution worker.
9354 *
9355 * @returns Strict VBox status code.
9356 * @param pVCpu The cross context virtual CPU structure.
9357 * @param cbInstr The instruction length in bytes.
9358 * @param iEffSeg The effective segment register to use with @a
9359 * GCPtrVmxon.
9360 * @param GCPtrVmxon The linear address of the VMXON pointer.
9361 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9362 *
9363 * @remarks Common VMX instruction checks are already expected to by the caller,
9364 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9365 */
9366static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9367 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9368{
9369 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9370 {
9371 /* CPL. */
9372 if (pVCpu->iem.s.uCpl == 0)
9373 { /* likely */ }
9374 else
9375 {
9376 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9377 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9378 return iemRaiseGeneralProtectionFault0(pVCpu);
9379 }
9380
9381 /* A20M (A20 Masked) mode. */
9382 if (PGMPhysIsA20Enabled(pVCpu))
9383 { /* likely */ }
9384 else
9385 {
9386 Log(("vmxon: A20M mode -> #GP(0)\n"));
9387 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9388 return iemRaiseGeneralProtectionFault0(pVCpu);
9389 }
9390
9391 /* CR0. */
9392 {
9393 /*
9394 * CR0 MB1 bits.
9395 *
9396 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9397 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9398 * when the guest running in VMX non-root mode with unrestricted-guest control
9399 * enabled in the VMCS.
9400 */
9401 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9402 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9403 { /* likely */ }
9404 else
9405 {
9406 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9407 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9408 return iemRaiseGeneralProtectionFault0(pVCpu);
9409 }
9410
9411 /* CR0 MBZ bits. */
9412 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9413 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9414 { /* likely */ }
9415 else
9416 {
9417 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9418 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9419 return iemRaiseGeneralProtectionFault0(pVCpu);
9420 }
9421 }
9422
9423 /* CR4. */
9424 {
9425 /* CR4 MB1 bits. */
9426 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9427 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9428 { /* likely */ }
9429 else
9430 {
9431 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9432 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9433 return iemRaiseGeneralProtectionFault0(pVCpu);
9434 }
9435
9436 /* CR4 MBZ bits. */
9437 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9438 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9439 { /* likely */ }
9440 else
9441 {
9442 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9443 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9444 return iemRaiseGeneralProtectionFault0(pVCpu);
9445 }
9446 }
9447
9448 /* Feature control MSR's LOCK and VMXON bits. */
9449 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9450 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9451 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9452 { /* likely */ }
9453 else
9454 {
9455 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9456 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9457 return iemRaiseGeneralProtectionFault0(pVCpu);
9458 }
9459
9460 /* Get the VMXON pointer from the location specified by the source memory operand. */
9461 RTGCPHYS GCPhysVmxon;
9462 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9463 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9464 { /* likely */ }
9465 else
9466 {
9467 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9468 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9469 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9470 return rcStrict;
9471 }
9472
9473 /* VMXON region pointer alignment. */
9474 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9475 { /* likely */ }
9476 else
9477 {
9478 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9479 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9480 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9481 iemVmxVmFailInvalid(pVCpu);
9482 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9483 return VINF_SUCCESS;
9484 }
9485
9486 /* VMXON physical-address width limits. */
9487 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9488 { /* likely */ }
9489 else
9490 {
9491 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9492 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9493 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9494 iemVmxVmFailInvalid(pVCpu);
9495 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9496 return VINF_SUCCESS;
9497 }
9498
9499 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9500 restriction imposed by our implementation. */
9501 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9502 { /* likely */ }
9503 else
9504 {
9505 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9506 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9507 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9508 iemVmxVmFailInvalid(pVCpu);
9509 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9510 return VINF_SUCCESS;
9511 }
9512
9513 /* Read the VMCS revision ID from the VMXON region. */
9514 VMXVMCSREVID VmcsRevId;
9515 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9516 if (RT_SUCCESS(rc))
9517 { /* likely */ }
9518 else
9519 {
9520 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9521 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9522 return rc;
9523 }
9524
9525 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9526 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9527 { /* likely */ }
9528 else
9529 {
9530 /* Revision ID mismatch. */
9531 if (!VmcsRevId.n.fIsShadowVmcs)
9532 {
9533 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9534 VmcsRevId.n.u31RevisionId));
9535 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9536 iemVmxVmFailInvalid(pVCpu);
9537 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9538 return VINF_SUCCESS;
9539 }
9540
9541 /* Shadow VMCS disallowed. */
9542 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9543 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9544 iemVmxVmFailInvalid(pVCpu);
9545 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9546 return VINF_SUCCESS;
9547 }
9548
9549 /*
9550 * Record that we're in VMX operation, block INIT, block and disable A20M.
9551 */
9552 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9553 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9554 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9555
9556 /* Clear address-range monitoring. */
9557 EMMonitorWaitClear(pVCpu);
9558 /** @todo NSTVMX: Intel PT. */
9559
9560 iemVmxVmSucceed(pVCpu);
9561 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9562 return VINF_SUCCESS;
9563 }
9564 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9565 {
9566 /* Nested-guest intercept. */
9567 if (pExitInfo)
9568 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9569 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9570 }
9571
9572 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9573
9574 /* CPL. */
9575 if (pVCpu->iem.s.uCpl > 0)
9576 {
9577 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9578 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9579 return iemRaiseGeneralProtectionFault0(pVCpu);
9580 }
9581
9582 /* VMXON when already in VMX root mode. */
9583 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9584 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9585 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9586 return VINF_SUCCESS;
9587}
9588
9589
9590/**
9591 * Interface for HM and EM to emulate the VMXON instruction.
9592 *
9593 * @returns Strict VBox status code.
9594 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9595 * @param pExitInfo Pointer to the VM-exit information.
9596 * @thread EMT(pVCpu)
9597 */
9598VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9599{
9600 Assert(pExitInfo);
9601 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9602 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9603
9604 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9605
9606 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9607 uint8_t const cbInstr = pExitInfo->cbInstr;
9608 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9609 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9610 Assert(!pVCpu->iem.s.cActiveMappings);
9611 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9612}
9613
9614
9615/**
9616 * Implements 'VMXOFF'.
9617 *
9618 * @remarks Common VMX instruction checks are already expected to by the caller,
9619 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9620 */
9621IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9622{
9623 /* Nested-guest intercept. */
9624 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9625 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9626
9627 /* CPL. */
9628 if (pVCpu->iem.s.uCpl == 0)
9629 { /* likely */ }
9630 else
9631 {
9632 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9633 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9634 return iemRaiseGeneralProtectionFault0(pVCpu);
9635 }
9636
9637 /* Dual monitor treatment of SMIs and SMM. */
9638 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9639 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9640 { /* likely */ }
9641 else
9642 {
9643 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9644 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9645 return VINF_SUCCESS;
9646 }
9647
9648 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9649 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9650 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9651
9652 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9653 { /** @todo NSTVMX: Unblock SMI. */ }
9654
9655 EMMonitorWaitClear(pVCpu);
9656 /** @todo NSTVMX: Unblock and enable A20M. */
9657
9658 iemVmxVmSucceed(pVCpu);
9659 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9660 return VINF_SUCCESS;
9661}
9662
9663
9664/**
9665 * Interface for HM and EM to emulate the VMXOFF instruction.
9666 *
9667 * @returns Strict VBox status code.
9668 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9669 * @param cbInstr The instruction length in bytes.
9670 * @thread EMT(pVCpu)
9671 */
9672VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9673{
9674 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9675 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9676
9677 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9678 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9679 Assert(!pVCpu->iem.s.cActiveMappings);
9680 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9681}
9682
9683
9684/**
9685 * Implements 'VMXON'.
9686 */
9687IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9688{
9689 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9690}
9691
9692
9693/**
9694 * Implements 'VMLAUNCH'.
9695 */
9696IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9697{
9698 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9699}
9700
9701
9702/**
9703 * Implements 'VMRESUME'.
9704 */
9705IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9706{
9707 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9708}
9709
9710
9711/**
9712 * Implements 'VMPTRLD'.
9713 */
9714IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9715{
9716 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9717}
9718
9719
9720/**
9721 * Implements 'VMPTRST'.
9722 */
9723IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9724{
9725 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9726}
9727
9728
9729/**
9730 * Implements 'VMCLEAR'.
9731 */
9732IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9733{
9734 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9735}
9736
9737
9738/**
9739 * Implements 'VMWRITE' register.
9740 */
9741IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9742{
9743 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9744}
9745
9746
9747/**
9748 * Implements 'VMWRITE' memory.
9749 */
9750IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9751{
9752 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9753}
9754
9755
9756/**
9757 * Implements 'VMREAD' register (64-bit).
9758 */
9759IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9760{
9761 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9762}
9763
9764
9765/**
9766 * Implements 'VMREAD' register (32-bit).
9767 */
9768IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9769{
9770 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9771}
9772
9773
9774/**
9775 * Implements 'VMREAD' memory, 64-bit register.
9776 */
9777IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9778{
9779 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9780}
9781
9782
9783/**
9784 * Implements 'VMREAD' memory, 32-bit register.
9785 */
9786IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9787{
9788 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9789}
9790
9791
9792/**
9793 * Implements 'INVVPID'.
9794 */
9795IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9796{
9797 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9798}
9799
9800
9801#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9802/**
9803 * Implements 'INVEPT'.
9804 */
9805IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9806{
9807 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9808}
9809#endif
9810
9811
9812/**
9813 * Implements VMX's implementation of PAUSE.
9814 */
9815IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9816{
9817 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9818 {
9819 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9820 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9821 return rcStrict;
9822 }
9823
9824 /*
9825 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9826 * a VM-exit, the instruction operates normally.
9827 */
9828 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9829 return VINF_SUCCESS;
9830}
9831
9832#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9833
9834
9835/**
9836 * Implements 'VMCALL'.
9837 */
9838IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9839{
9840#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9841 /* Nested-guest intercept. */
9842 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9843 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9844#endif
9845
9846 /* Join forces with vmmcall. */
9847 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9848}
9849
9850
9851#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9852
9853/**
9854 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9855 *
9856 * @remarks The @a uUser argument is currently unused.
9857 */
9858DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9859 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9860 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9861{
9862 RT_NOREF3(pvPhys, enmOrigin, uUser);
9863
9864 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9865 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9866 {
9867 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9868 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9869
9870 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9871 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9872 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9873 if (RT_FAILURE(rcStrict))
9874 return rcStrict;
9875
9876 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9877 return VINF_SUCCESS;
9878 }
9879
9880 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9881 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9882 if (RT_FAILURE(rc))
9883 return rc;
9884
9885 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9886 return VINF_PGM_HANDLER_DO_DEFAULT;
9887}
9888
9889
9890# ifndef IN_RING3
9891/**
9892 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9893 * \#PF access handler callback for guest VMX APIC-access page.}
9894 */
9895DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
9896 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9897
9898{
9899 RT_NOREF3(pVM, pRegFrame, uUser);
9900
9901 /*
9902 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9903 * Otherwise we must deregister the page and allow regular RAM access.
9904 * Failing to do so lands us with endless EPT misconfiguration VM-exits.
9905 */
9906 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9907 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9908 {
9909 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9910 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9911
9912 /*
9913 * Check if the access causes an APIC-access VM-exit.
9914 */
9915 uint32_t fAccess;
9916 if (uErr & X86_TRAP_PF_ID)
9917 fAccess = IEM_ACCESS_INSTRUCTION;
9918 else if (uErr & X86_TRAP_PF_RW)
9919 fAccess = IEM_ACCESS_DATA_W;
9920 else
9921 fAccess = IEM_ACCESS_DATA_R;
9922
9923 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9924 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9925 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9926 if (fIntercept)
9927 {
9928 /*
9929 * Query the source VM-exit (from the execution engine) that caused this access
9930 * within the APIC-access page. Currently only HM is supported.
9931 */
9932 AssertMsgReturn(VM_IS_HM_ENABLED(pVM),
9933 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n",
9934 pVM->bMainExecutionEngine), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
9935 HMEXITAUX HmExitAux;
9936 RT_ZERO(HmExitAux);
9937 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9938 | HMVMX_READ_EXIT_QUALIFICATION
9939 | HMVMX_READ_IDT_VECTORING_INFO
9940 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9941 AssertRCReturn(rc, rc);
9942
9943 /*
9944 * Verify the VM-exit reason must be an EPT violation.
9945 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9946 */
9947 AssertLogRelMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9948 ("Unexpected call to the VMX APIC-access page #PF handler for %#RGp (Nested=%#RGp, GCPhysAddr%#RGp) off=%u uReason=%u\n",
9949 GCPhysPage, GCPhysNestedFault, HmExitAux.Vmx.u64GuestPhysAddr, offAccess, HmExitAux.Vmx.uReason), VERR_IEM_IPE_9);
9950
9951 /*
9952 * Construct the virtual APIC-access VM-exit.
9953 */
9954 VMXAPICACCESS enmAccess;
9955 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9956 {
9957 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9958 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9959 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9960 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9961 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9962 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9963 else
9964 enmAccess = VMXAPICACCESS_LINEAR_READ;
9965 }
9966 else
9967 {
9968 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9969 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
9970 else
9971 {
9972 /** @todo How to distinguish between monitoring/trace vs other instructions
9973 * here? */
9974 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
9975 }
9976 }
9977
9978 VMXVEXITINFO ExitInfo;
9979 RT_ZERO(ExitInfo);
9980 ExitInfo.uReason = VMX_EXIT_APIC_ACCESS;
9981 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
9982 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
9983 ExitInfo.cbInstr = HmExitAux.Vmx.cbInstr;
9984
9985 VMXVEXITEVENTINFO ExitEventInfo;
9986 RT_ZERO(ExitEventInfo);
9987 ExitEventInfo.uIdtVectoringInfo = HmExitAux.Vmx.uIdtVectoringInfo;
9988 ExitEventInfo.uIdtVectoringErrCode = HmExitAux.Vmx.uIdtVectoringErrCode;
9989
9990 /*
9991 * Raise the APIC-access VM-exit.
9992 */
9993 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
9994 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
9995 }
9996
9997 /*
9998 * The access isn't intercepted, which means it needs to be virtualized.
9999 *
10000 * This requires emulating the instruction because we need the bytes being
10001 * read/written by the instruction not just the offset being accessed within
10002 * the APIC-access (which we derive from the faulting address).
10003 */
10004 return VINF_EM_RAW_EMULATE_INSTR;
10005 }
10006
10007 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10008 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10009 if (RT_FAILURE(rc))
10010 return rc;
10011
10012 return VINF_SUCCESS;
10013}
10014# endif /* !IN_RING3 */
10015
10016#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10017
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