VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 76855

Last change on this file since 76855 was 76850, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Rescheduling fixes. Don't clear the host LDTR base and limit while restoring host state on VM-exit, the spec only mentions clearing the selector and marking it unusable.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 76850 2019-01-17 11:23:47Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165/** Enables/disables IEM-only EM execution policy in and from ring-3. */
166# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
167# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcRet) \
168 do { \
169 Log(("%s: Enabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
170 return EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true); \
171 } while (0)
172
173# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcRet) \
174 do { \
175 Log(("%s: Disabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
176 return EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false); \
177 } while (0)
178# else
179# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcRet) do { return (a_rcRet); } while (0)
180# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcRet) do { return (a_rcRet); } while (0)
181# endif
182
183
184/*********************************************************************************************************************************
185* Global Variables *
186*********************************************************************************************************************************/
187/** @todo NSTVMX: The following VM-exit intercepts are pending:
188 * VMX_EXIT_IO_SMI
189 * VMX_EXIT_SMI
190 * VMX_EXIT_INT_WINDOW
191 * VMX_EXIT_NMI_WINDOW
192 * VMX_EXIT_GETSEC
193 * VMX_EXIT_RSM
194 * VMX_EXIT_MTF
195 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
196 * VMX_EXIT_ERR_MACHINE_CHECK
197 * VMX_EXIT_TPR_BELOW_THRESHOLD
198 * VMX_EXIT_APIC_ACCESS
199 * VMX_EXIT_VIRTUALIZED_EOI
200 * VMX_EXIT_EPT_VIOLATION
201 * VMX_EXIT_EPT_MISCONFIG
202 * VMX_EXIT_INVEPT
203 * VMX_EXIT_PREEMPT_TIMER
204 * VMX_EXIT_INVVPID
205 * VMX_EXIT_APIC_WRITE
206 * VMX_EXIT_RDRAND
207 * VMX_EXIT_VMFUNC
208 * VMX_EXIT_ENCLS
209 * VMX_EXIT_RDSEED
210 * VMX_EXIT_PML_FULL
211 * VMX_EXIT_XSAVES
212 * VMX_EXIT_XRSTORS
213 */
214/**
215 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
216 *
217 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
218 * second dimension is the Index, see VMXVMCSFIELDENC.
219 */
220uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
221{
222 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
223 {
224 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
225 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
226 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
227 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
230 },
231 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
232 {
233 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
234 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
235 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
236 /* 24-25 */ UINT16_MAX, UINT16_MAX
237 },
238 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
239 {
240 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
241 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
242 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
243 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
244 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
245 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
246 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
247 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
248 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
249 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
250 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
251 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
252 },
253 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
254 {
255 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
256 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
257 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
258 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
259 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
260 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
261 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
262 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
263 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
264 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
265 },
266 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
267 {
268 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
269 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
270 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
271 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
272 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
273 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
274 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
275 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
276 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
277 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
278 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
279 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
280 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
281 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
282 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
283 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
284 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
285 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
286 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
287 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
288 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
289 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
290 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
291 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
292 /* 24 */ UINT16_MAX,
293 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
294 },
295 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
296 {
297 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
298 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
301 /* 25 */ UINT16_MAX
302 },
303 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
304 {
305 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
306 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
307 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
308 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
309 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
310 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
311 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
312 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
313 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
314 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
315 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
316 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
317 },
318 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
319 {
320 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
321 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
322 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
323 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
324 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
325 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
326 },
327 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
328 {
329 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
330 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
331 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
332 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
333 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
334 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
335 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
336 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
337 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
338 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
339 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
340 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
341 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
342 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
343 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
344 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
345 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
346 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
347 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
348 },
349 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
350 {
351 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
352 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
353 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
354 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
355 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
356 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
357 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
358 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
359 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
360 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
361 /* 24-25 */ UINT16_MAX, UINT16_MAX
362 },
363 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
364 {
365 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
366 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
367 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
368 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
369 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
370 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
371 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
372 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
373 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
374 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
375 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
376 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
377 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
378 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
379 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
380 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
381 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
382 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
383 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
384 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
385 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
386 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
387 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
388 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
389 },
390 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
391 {
392 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
393 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
394 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
395 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 25 */ UINT16_MAX
397 },
398 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
399 {
400 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
401 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
402 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
403 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
404 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
405 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
406 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
407 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
408 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
409 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
410 /* 24-25 */ UINT16_MAX, UINT16_MAX
411 },
412 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
413 {
414 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
415 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
416 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
417 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
418 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
419 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
420 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
421 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
422 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
423 },
424 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
425 {
426 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
427 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
428 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
429 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
430 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
431 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
432 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
433 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
434 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
435 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
436 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
437 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
438 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
439 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
440 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
441 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
442 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
443 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
444 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
445 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
446 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
447 },
448 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
449 {
450 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
451 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
452 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
453 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
454 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
455 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
456 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
457 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
458 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
459 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
460 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
461 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
462 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
463 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
464 }
465};
466
467
468/**
469 * Returns whether the given VMCS field is valid and supported by our emulation.
470 *
471 * @param pVCpu The cross context virtual CPU structure.
472 * @param u64FieldEnc The VMCS field encoding.
473 *
474 * @remarks This takes into account the CPU features exposed to the guest.
475 */
476IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
477{
478 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
479 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
480 if (!uFieldEncHi)
481 { /* likely */ }
482 else
483 return false;
484
485 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
486 switch (uFieldEncLo)
487 {
488 /*
489 * 16-bit fields.
490 */
491 /* Control fields. */
492 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
493 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
494 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
495
496 /* Guest-state fields. */
497 case VMX_VMCS16_GUEST_ES_SEL:
498 case VMX_VMCS16_GUEST_CS_SEL:
499 case VMX_VMCS16_GUEST_SS_SEL:
500 case VMX_VMCS16_GUEST_DS_SEL:
501 case VMX_VMCS16_GUEST_FS_SEL:
502 case VMX_VMCS16_GUEST_GS_SEL:
503 case VMX_VMCS16_GUEST_LDTR_SEL:
504 case VMX_VMCS16_GUEST_TR_SEL: return true;
505 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
506 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
507
508 /* Host-state fields. */
509 case VMX_VMCS16_HOST_ES_SEL:
510 case VMX_VMCS16_HOST_CS_SEL:
511 case VMX_VMCS16_HOST_SS_SEL:
512 case VMX_VMCS16_HOST_DS_SEL:
513 case VMX_VMCS16_HOST_FS_SEL:
514 case VMX_VMCS16_HOST_GS_SEL:
515 case VMX_VMCS16_HOST_TR_SEL: return true;
516
517 /*
518 * 64-bit fields.
519 */
520 /* Control fields. */
521 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
522 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
523 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
524 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
525 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
526 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
527 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
528 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
529 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
530 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
531 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
532 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
533 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
534 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
535 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
536 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
537 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
538 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
539 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
540 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
541 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
542 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
543 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
544 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
545 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
546 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
547 case VMX_VMCS64_CTRL_EPTP_FULL:
548 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
549 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
550 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
551 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
552 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
553 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
554 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
555 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
556 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
557 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
558 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
559 {
560 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
561 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
562 }
563 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
564 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
565 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
566 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
567 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
568 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
569 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
570 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
571 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
572 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
573 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
574 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
575
576 /* Read-only data fields. */
577 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
578 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
579
580 /* Guest-state fields. */
581 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
582 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
583 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
584 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
585 case VMX_VMCS64_GUEST_PAT_FULL:
586 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
587 case VMX_VMCS64_GUEST_EFER_FULL:
588 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
589 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
590 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
591 case VMX_VMCS64_GUEST_PDPTE0_FULL:
592 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
593 case VMX_VMCS64_GUEST_PDPTE1_FULL:
594 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
595 case VMX_VMCS64_GUEST_PDPTE2_FULL:
596 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
597 case VMX_VMCS64_GUEST_PDPTE3_FULL:
598 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
599 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
600 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
601
602 /* Host-state fields. */
603 case VMX_VMCS64_HOST_PAT_FULL:
604 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
605 case VMX_VMCS64_HOST_EFER_FULL:
606 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
607 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
608 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
609
610 /*
611 * 32-bit fields.
612 */
613 /* Control fields. */
614 case VMX_VMCS32_CTRL_PIN_EXEC:
615 case VMX_VMCS32_CTRL_PROC_EXEC:
616 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
617 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
618 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
619 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
620 case VMX_VMCS32_CTRL_EXIT:
621 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
622 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
623 case VMX_VMCS32_CTRL_ENTRY:
624 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
625 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
626 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
627 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
628 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
629 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
630 case VMX_VMCS32_CTRL_PLE_GAP:
631 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
632
633 /* Read-only data fields. */
634 case VMX_VMCS32_RO_VM_INSTR_ERROR:
635 case VMX_VMCS32_RO_EXIT_REASON:
636 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
637 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
638 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
639 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
640 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
641 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
642
643 /* Guest-state fields. */
644 case VMX_VMCS32_GUEST_ES_LIMIT:
645 case VMX_VMCS32_GUEST_CS_LIMIT:
646 case VMX_VMCS32_GUEST_SS_LIMIT:
647 case VMX_VMCS32_GUEST_DS_LIMIT:
648 case VMX_VMCS32_GUEST_FS_LIMIT:
649 case VMX_VMCS32_GUEST_GS_LIMIT:
650 case VMX_VMCS32_GUEST_LDTR_LIMIT:
651 case VMX_VMCS32_GUEST_TR_LIMIT:
652 case VMX_VMCS32_GUEST_GDTR_LIMIT:
653 case VMX_VMCS32_GUEST_IDTR_LIMIT:
654 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
655 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
656 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
657 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
658 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
659 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
660 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
661 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
662 case VMX_VMCS32_GUEST_INT_STATE:
663 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
664 case VMX_VMCS32_GUEST_SMBASE:
665 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
666 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
667
668 /* Host-state fields. */
669 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
670
671 /*
672 * Natural-width fields.
673 */
674 /* Control fields. */
675 case VMX_VMCS_CTRL_CR0_MASK:
676 case VMX_VMCS_CTRL_CR4_MASK:
677 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
678 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
679 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
680 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
681 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
682 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
683
684 /* Read-only data fields. */
685 case VMX_VMCS_RO_EXIT_QUALIFICATION:
686 case VMX_VMCS_RO_IO_RCX:
687 case VMX_VMCS_RO_IO_RSX:
688 case VMX_VMCS_RO_IO_RDI:
689 case VMX_VMCS_RO_IO_RIP:
690 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
691
692 /* Guest-state fields. */
693 case VMX_VMCS_GUEST_CR0:
694 case VMX_VMCS_GUEST_CR3:
695 case VMX_VMCS_GUEST_CR4:
696 case VMX_VMCS_GUEST_ES_BASE:
697 case VMX_VMCS_GUEST_CS_BASE:
698 case VMX_VMCS_GUEST_SS_BASE:
699 case VMX_VMCS_GUEST_DS_BASE:
700 case VMX_VMCS_GUEST_FS_BASE:
701 case VMX_VMCS_GUEST_GS_BASE:
702 case VMX_VMCS_GUEST_LDTR_BASE:
703 case VMX_VMCS_GUEST_TR_BASE:
704 case VMX_VMCS_GUEST_GDTR_BASE:
705 case VMX_VMCS_GUEST_IDTR_BASE:
706 case VMX_VMCS_GUEST_DR7:
707 case VMX_VMCS_GUEST_RSP:
708 case VMX_VMCS_GUEST_RIP:
709 case VMX_VMCS_GUEST_RFLAGS:
710 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
711 case VMX_VMCS_GUEST_SYSENTER_ESP:
712 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
713
714 /* Host-state fields. */
715 case VMX_VMCS_HOST_CR0:
716 case VMX_VMCS_HOST_CR3:
717 case VMX_VMCS_HOST_CR4:
718 case VMX_VMCS_HOST_FS_BASE:
719 case VMX_VMCS_HOST_GS_BASE:
720 case VMX_VMCS_HOST_TR_BASE:
721 case VMX_VMCS_HOST_GDTR_BASE:
722 case VMX_VMCS_HOST_IDTR_BASE:
723 case VMX_VMCS_HOST_SYSENTER_ESP:
724 case VMX_VMCS_HOST_SYSENTER_EIP:
725 case VMX_VMCS_HOST_RSP:
726 case VMX_VMCS_HOST_RIP: return true;
727 }
728
729 return false;
730}
731
732
733/**
734 * Gets a host selector from the VMCS.
735 *
736 * @param pVmcs Pointer to the virtual VMCS.
737 * @param iSelReg The index of the segment register (X86_SREG_XXX).
738 */
739DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
740{
741 Assert(iSegReg < X86_SREG_COUNT);
742 RTSEL HostSel;
743 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
744 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
745 uint8_t const uWidthType = (uWidth << 2) | uType;
746 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
747 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
748 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
749 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
750 uint8_t const *pbField = pbVmcs + offField;
751 HostSel = *(uint16_t *)pbField;
752 return HostSel;
753}
754
755
756/**
757 * Sets a guest segment register in the VMCS.
758 *
759 * @param pVmcs Pointer to the virtual VMCS.
760 * @param iSegReg The index of the segment register (X86_SREG_XXX).
761 * @param pSelReg Pointer to the segment register.
762 */
763IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
764{
765 Assert(pSelReg);
766 Assert(iSegReg < X86_SREG_COUNT);
767
768 /* Selector. */
769 {
770 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
771 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
772 uint8_t const uWidthType = (uWidth << 2) | uType;
773 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
774 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
775 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
776 uint8_t *pbVmcs = (uint8_t *)pVmcs;
777 uint8_t *pbField = pbVmcs + offField;
778 *(uint16_t *)pbField = pSelReg->Sel;
779 }
780
781 /* Limit. */
782 {
783 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
784 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
785 uint8_t const uWidthType = (uWidth << 2) | uType;
786 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
787 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
788 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
789 uint8_t *pbVmcs = (uint8_t *)pVmcs;
790 uint8_t *pbField = pbVmcs + offField;
791 *(uint32_t *)pbField = pSelReg->u32Limit;
792 }
793
794 /* Base. */
795 {
796 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
797 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
798 uint8_t const uWidthType = (uWidth << 2) | uType;
799 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
800 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
801 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
802 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
803 uint8_t const *pbField = pbVmcs + offField;
804 *(uint64_t *)pbField = pSelReg->u64Base;
805 }
806
807 /* Attributes. */
808 {
809 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
810 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
811 | X86DESCATTR_UNUSABLE;
812 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
813 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
814 uint8_t const uWidthType = (uWidth << 2) | uType;
815 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
816 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
817 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
818 uint8_t *pbVmcs = (uint8_t *)pVmcs;
819 uint8_t *pbField = pbVmcs + offField;
820 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
821 }
822}
823
824
825/**
826 * Gets a guest segment register from the VMCS.
827 *
828 * @returns VBox status code.
829 * @param pVmcs Pointer to the virtual VMCS.
830 * @param iSegReg The index of the segment register (X86_SREG_XXX).
831 * @param pSelReg Where to store the segment register (only updated when
832 * VINF_SUCCESS is returned).
833 *
834 * @remarks Warning! This does not validate the contents of the retrieved segment
835 * register.
836 */
837IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
838{
839 Assert(pSelReg);
840 Assert(iSegReg < X86_SREG_COUNT);
841
842 /* Selector. */
843 uint16_t u16Sel;
844 {
845 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
846 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
847 uint8_t const uWidthType = (uWidth << 2) | uType;
848 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
849 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
850 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
851 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
852 uint8_t const *pbField = pbVmcs + offField;
853 u16Sel = *(uint16_t *)pbField;
854 }
855
856 /* Limit. */
857 uint32_t u32Limit;
858 {
859 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
860 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
861 uint8_t const uWidthType = (uWidth << 2) | uType;
862 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
863 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
864 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
865 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
866 uint8_t const *pbField = pbVmcs + offField;
867 u32Limit = *(uint32_t *)pbField;
868 }
869
870 /* Base. */
871 uint64_t u64Base;
872 {
873 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
874 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
875 uint8_t const uWidthType = (uWidth << 2) | uType;
876 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
877 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
878 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
879 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
880 uint8_t const *pbField = pbVmcs + offField;
881 u64Base = *(uint64_t *)pbField;
882 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
883 }
884
885 /* Attributes. */
886 uint32_t u32Attr;
887 {
888 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
889 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
890 uint8_t const uWidthType = (uWidth << 2) | uType;
891 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
892 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
893 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
894 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
895 uint8_t const *pbField = pbVmcs + offField;
896 u32Attr = *(uint32_t *)pbField;
897 }
898
899 pSelReg->Sel = u16Sel;
900 pSelReg->ValidSel = u16Sel;
901 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
902 pSelReg->u32Limit = u32Limit;
903 pSelReg->u64Base = u64Base;
904 pSelReg->Attr.u = u32Attr;
905 return VINF_SUCCESS;
906}
907
908
909/**
910 * Gets a CR3 target value from the VMCS.
911 *
912 * @returns VBox status code.
913 * @param pVmcs Pointer to the virtual VMCS.
914 * @param idxCr3Target The index of the CR3-target value to retrieve.
915 * @param puValue Where to store the CR3-target value.
916 */
917DECLINLINE(uint64_t) iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
918{
919 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
920 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
921 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
922 uint8_t const uWidthType = (uWidth << 2) | uType;
923 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
924 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
925 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
926 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
927 uint8_t const *pbField = pbVmcs + offField;
928 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
929
930 return uCr3TargetValue;
931}
932
933
934/**
935 * Converts an IEM exception event type to a VMX event type.
936 *
937 * @returns The VMX event type.
938 * @param uVector The interrupt / exception vector.
939 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
940 */
941DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
942{
943 /* Paranoia (callers may use these interchangeably). */
944 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
945 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
946 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
947 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
948 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
949 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
950 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
951 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
952 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
953 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
954 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
955 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
956
957 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
958 {
959 if (uVector == X86_XCPT_NMI)
960 return VMX_EXIT_INT_INFO_TYPE_NMI;
961 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
962 }
963
964 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
965 {
966 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
967 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
968 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
969 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
970 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
971 }
972
973 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
974 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
975}
976
977
978/**
979 * Sets the VM-instruction error VMCS field.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param enmInsErr The VM-instruction error.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetVmInstrErr(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoVmInstrError = enmInsErr;
988}
989
990
991/**
992 * Sets the VM-exit qualification VMCS field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uExitQual The VM-exit qualification.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u64RoExitQual.u = uExitQual;
1001}
1002
1003
1004/**
1005 * Sets the VM-exit interruption information field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uExitQual The VM-exit interruption information.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit interruption error code.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uErrCode The error code.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u32RoExitIntErrCode = uErrCode;
1027}
1028
1029
1030/**
1031 * Sets the IDT-vectoring information field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uIdtVectorInfo The IDT-vectoring information.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1040}
1041
1042
1043/**
1044 * Sets the IDT-vectoring error code field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param uErrCode The error code.
1048 */
1049DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1050{
1051 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1052 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1053}
1054
1055
1056/**
1057 * Sets the VM-exit guest-linear address VMCS field.
1058 *
1059 * @param pVCpu The cross context virtual CPU structure.
1060 * @param uGuestLinearAddr The VM-exit guest-linear address.
1061 */
1062DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1063{
1064 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1065 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1066}
1067
1068
1069/**
1070 * Sets the VM-exit guest-physical address VMCS field.
1071 *
1072 * @param pVCpu The cross context virtual CPU structure.
1073 * @param uGuestPhysAddr The VM-exit guest-physical address.
1074 */
1075DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1076{
1077 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1078 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1079}
1080
1081
1082/**
1083 * Sets the VM-exit instruction length VMCS field.
1084 *
1085 * @param pVCpu The cross context virtual CPU structure.
1086 * @param cbInstr The VM-exit instruction length in bytes.
1087 *
1088 * @remarks Callers may clear this field to 0. Hence, this function does not check
1089 * the validity of the instruction length.
1090 */
1091DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1092{
1093 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1094 pVmcs->u32RoExitInstrLen = cbInstr;
1095}
1096
1097
1098/**
1099 * Sets the VM-exit instruction info. VMCS field.
1100 *
1101 * @param pVCpu The cross context virtual CPU structure.
1102 * @param uExitInstrInfo The VM-exit instruction information.
1103 */
1104DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1105{
1106 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1107 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1108}
1109
1110
1111/**
1112 * Implements VMSucceed for VMX instruction success.
1113 *
1114 * @param pVCpu The cross context virtual CPU structure.
1115 */
1116DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1117{
1118 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1119}
1120
1121
1122/**
1123 * Implements VMFailInvalid for VMX instruction failure.
1124 *
1125 * @param pVCpu The cross context virtual CPU structure.
1126 */
1127DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1128{
1129 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1130 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_CF;
1131}
1132
1133
1134/**
1135 * Implements VMFailValid for VMX instruction failure.
1136 *
1137 * @param pVCpu The cross context virtual CPU structure.
1138 * @param enmInsErr The VM instruction error.
1139 */
1140DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1141{
1142 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1143 {
1144 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1145 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_ZF;
1146 iemVmxVmcsSetVmInstrErr(pVCpu, enmInsErr);
1147 }
1148}
1149
1150
1151/**
1152 * Implements VMFail for VMX instruction failure.
1153 *
1154 * @param pVCpu The cross context virtual CPU structure.
1155 * @param enmInsErr The VM instruction error.
1156 */
1157DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1158{
1159 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1160 iemVmxVmFailValid(pVCpu, enmInsErr);
1161 else
1162 iemVmxVmFailInvalid(pVCpu);
1163}
1164
1165
1166/**
1167 * Checks if the given auto-load/store MSR area count is valid for the
1168 * implementation.
1169 *
1170 * @returns @c true if it's within the valid limit, @c false otherwise.
1171 * @param pVCpu The cross context virtual CPU structure.
1172 * @param uMsrCount The MSR area count to check.
1173 */
1174DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1175{
1176 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1177 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1178 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1179 if (uMsrCount <= cMaxSupportedMsrs)
1180 return true;
1181 return false;
1182}
1183
1184
1185/**
1186 * Flushes the current VMCS contents back to guest memory.
1187 *
1188 * @returns VBox status code.
1189 * @param pVCpu The cross context virtual CPU structure.
1190 */
1191DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1192{
1193 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1194 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1195 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1196 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1197 return rc;
1198}
1199
1200
1201/**
1202 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1203 *
1204 * @param pVCpu The cross context virtual CPU structure.
1205 */
1206DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1207{
1208 iemVmxVmSucceed(pVCpu);
1209 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1210}
1211
1212
1213/**
1214 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1215 * nested-guest.
1216 *
1217 * @param iSegReg The segment index (X86_SREG_XXX).
1218 */
1219IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1220{
1221 switch (iSegReg)
1222 {
1223 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1224 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1225 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1226 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1227 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1228 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1229 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1230 }
1231}
1232
1233
1234/**
1235 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1236 * nested-guest that is in Virtual-8086 mode.
1237 *
1238 * @param iSegReg The segment index (X86_SREG_XXX).
1239 */
1240IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1241{
1242 switch (iSegReg)
1243 {
1244 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1245 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1246 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1247 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1248 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1249 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1250 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1251 }
1252}
1253
1254
1255/**
1256 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1257 * nested-guest that is in Virtual-8086 mode.
1258 *
1259 * @param iSegReg The segment index (X86_SREG_XXX).
1260 */
1261IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1262{
1263 switch (iSegReg)
1264 {
1265 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1266 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1267 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1268 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1269 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1270 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1271 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1272 }
1273}
1274
1275
1276/**
1277 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1278 * nested-guest that is in Virtual-8086 mode.
1279 *
1280 * @param iSegReg The segment index (X86_SREG_XXX).
1281 */
1282IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1283{
1284 switch (iSegReg)
1285 {
1286 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1287 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1288 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1289 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1290 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1291 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1292 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1293 }
1294}
1295
1296
1297/**
1298 * Gets the instruction diagnostic for segment attributes reserved bits failure
1299 * during VM-entry of a nested-guest.
1300 *
1301 * @param iSegReg The segment index (X86_SREG_XXX).
1302 */
1303IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1304{
1305 switch (iSegReg)
1306 {
1307 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1308 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1309 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1310 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1311 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1312 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1313 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1314 }
1315}
1316
1317
1318/**
1319 * Gets the instruction diagnostic for segment attributes descriptor-type
1320 * (code/segment or system) failure during VM-entry of a nested-guest.
1321 *
1322 * @param iSegReg The segment index (X86_SREG_XXX).
1323 */
1324IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1325{
1326 switch (iSegReg)
1327 {
1328 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1329 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1330 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1331 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1332 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1333 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1334 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1335 }
1336}
1337
1338
1339/**
1340 * Gets the instruction diagnostic for segment attributes descriptor-type
1341 * (code/segment or system) failure during VM-entry of a nested-guest.
1342 *
1343 * @param iSegReg The segment index (X86_SREG_XXX).
1344 */
1345IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1346{
1347 switch (iSegReg)
1348 {
1349 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1350 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1351 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1352 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1353 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1354 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1355 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1356 }
1357}
1358
1359
1360/**
1361 * Gets the instruction diagnostic for segment attribute granularity failure during
1362 * VM-entry of a nested-guest.
1363 *
1364 * @param iSegReg The segment index (X86_SREG_XXX).
1365 */
1366IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1367{
1368 switch (iSegReg)
1369 {
1370 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1371 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1372 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1373 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1374 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1375 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1376 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1377 }
1378}
1379
1380/**
1381 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1382 * VM-entry of a nested-guest.
1383 *
1384 * @param iSegReg The segment index (X86_SREG_XXX).
1385 */
1386IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1387{
1388 switch (iSegReg)
1389 {
1390 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1391 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1392 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1393 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1394 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1395 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1396 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1397 }
1398}
1399
1400
1401/**
1402 * Gets the instruction diagnostic for segment attribute type accessed failure
1403 * during VM-entry of a nested-guest.
1404 *
1405 * @param iSegReg The segment index (X86_SREG_XXX).
1406 */
1407IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1408{
1409 switch (iSegReg)
1410 {
1411 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1412 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1413 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1414 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1415 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1416 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1417 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1418 }
1419}
1420
1421
1422/**
1423 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1424 * failure during VM-entry of a nested-guest.
1425 *
1426 * @param iSegReg The PDPTE entry index.
1427 */
1428IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1429{
1430 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1431 switch (iPdpte)
1432 {
1433 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1434 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1435 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1436 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1437 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1438 }
1439}
1440
1441
1442/**
1443 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1444 * failure during VM-exit of a nested-guest.
1445 *
1446 * @param iSegReg The PDPTE entry index.
1447 */
1448IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1449{
1450 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1451 switch (iPdpte)
1452 {
1453 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1454 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1455 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1456 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1457 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1458 }
1459}
1460
1461
1462/**
1463 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1464 * mask and the read-shadow (CR0/CR4 read).
1465 *
1466 * @returns The masked CR0/CR4.
1467 * @param pVCpu The cross context virtual CPU structure.
1468 * @param iCrReg The control register (either CR0 or CR4).
1469 * @param uGuestCrX The current guest CR0 or guest CR4.
1470 */
1471IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1472{
1473 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1474 Assert(iCrReg == 0 || iCrReg == 4);
1475
1476 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1477 Assert(pVmcs);
1478
1479 /*
1480 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1481 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1482 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1483 *
1484 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1485 */
1486 uint64_t fGstHostMask;
1487 uint64_t fReadShadow;
1488 if (iCrReg == 0)
1489 {
1490 fGstHostMask = pVmcs->u64Cr0Mask.u;
1491 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1492 }
1493 else
1494 {
1495 fGstHostMask = pVmcs->u64Cr4Mask.u;
1496 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1497 }
1498
1499 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1500 return fMaskedCrX;
1501}
1502
1503
1504/**
1505 * Saves the guest control registers, debug registers and some MSRs are part of
1506 * VM-exit.
1507 *
1508 * @param pVCpu The cross context virtual CPU structure.
1509 */
1510IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1511{
1512 /*
1513 * Saves the guest control registers, debug registers and some MSRs.
1514 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1515 */
1516 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1517
1518 /* Save control registers. */
1519 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1520 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1521 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1522
1523 /* Save SYSENTER CS, ESP, EIP. */
1524 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1525 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1526 {
1527 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1528 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1529 }
1530 else
1531 {
1532 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1533 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1534 }
1535
1536 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1537 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1538 {
1539 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1540 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1541 }
1542
1543 /* Save PAT MSR. */
1544 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1545 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1546
1547 /* Save EFER MSR. */
1548 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1549 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1550
1551 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1552 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1553
1554 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1555}
1556
1557
1558/**
1559 * Saves the guest force-flags in preparation of entering the nested-guest.
1560 *
1561 * @param pVCpu The cross context virtual CPU structure.
1562 */
1563IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1564{
1565 /* We shouldn't be called multiple times during VM-entry. */
1566 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1567
1568 /* MTF should not be set outside VMX non-root mode. */
1569 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1570
1571 /*
1572 * Preserve the required force-flags.
1573 *
1574 * We cache and clear force-flags that would affect the execution of the
1575 * nested-guest. Cached flags are then restored while returning to the guest
1576 * if necessary.
1577 *
1578 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1579 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1580 * instruction. Interrupt inhibition for any nested-guest instruction
1581 * is supplied by the guest-interruptibility state VMCS field and will
1582 * be set up as part of loading the guest state.
1583 *
1584 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1585 * successful VM-entry (due to invalid guest-state) need to continue
1586 * blocking NMIs if it was in effect before VM-entry.
1587 *
1588 * - MTF need not be preserved as it's used only in VMX non-root mode and
1589 * is supplied through the VM-execution controls.
1590 *
1591 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1592 * we will be able to generate interrupts that may cause VM-exits for
1593 * the nested-guest.
1594 */
1595 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1596}
1597
1598
1599/**
1600 * Restores the guest force-flags in preparation of exiting the nested-guest.
1601 *
1602 * @param pVCpu The cross context virtual CPU structure.
1603 */
1604IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1605{
1606 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1607 {
1608 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1609 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1610 }
1611}
1612
1613
1614/**
1615 * Perform a VMX transition updated PGM, IEM and CPUM.
1616 *
1617 * @param pVCpu The cross context virtual CPU structure.
1618 */
1619IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1620{
1621 /*
1622 * Inform PGM about paging mode changes.
1623 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1624 * see comment in iemMemPageTranslateAndCheckAccess().
1625 */
1626 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1627# ifdef IN_RING3
1628 Assert(rc != VINF_PGM_CHANGE_MODE);
1629# endif
1630 AssertRCReturn(rc, rc);
1631
1632 /* Inform CPUM (recompiler), can later be removed. */
1633 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1634
1635 /*
1636 * Flush the TLB with new CR3. This is required in case the PGM mode change
1637 * above doesn't actually change anything.
1638 */
1639 if (rc == VINF_SUCCESS)
1640 {
1641 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1642 AssertRCReturn(rc, rc);
1643 }
1644
1645 /* Re-initialize IEM cache/state after the drastic mode switch. */
1646 iemReInitExec(pVCpu);
1647 return rc;
1648}
1649
1650
1651/**
1652 * Calculates the current VMX-preemption timer value.
1653 *
1654 * @param pVCpu The cross context virtual CPU structure.
1655 */
1656IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1657{
1658 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1659 Assert(pVmcs);
1660
1661 /*
1662 * Assume the following:
1663 * PreemptTimerShift = 5
1664 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1665 * VmentryTick = 50000 (TSC at time of VM-entry)
1666 *
1667 * CurTick Delta PreemptTimerVal
1668 * ----------------------------------
1669 * 60000 10000 2
1670 * 80000 30000 1
1671 * 90000 40000 0 -> VM-exit.
1672 *
1673 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1674 * The saved VMX-preemption timer value is calculated as follows:
1675 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1676 * E.g.:
1677 * Delta = 10000
1678 * Tmp = 10000 / (2 * 10000) = 0.5
1679 * NewPt = 2 - 0.5 = 2
1680 * Delta = 30000
1681 * Tmp = 30000 / (2 * 10000) = 1.5
1682 * NewPt = 2 - 1.5 = 1
1683 * Delta = 40000
1684 * Tmp = 40000 / 20000 = 2
1685 * NewPt = 2 - 2 = 0
1686 */
1687 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1688 uint64_t const uVmentryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
1689 uint64_t const uDelta = uCurTick - uVmentryTick;
1690 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1691 uint32_t const uPreemptTimer = uVmcsPreemptVal
1692 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1693 return uPreemptTimer;
1694}
1695
1696
1697/**
1698 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1699 *
1700 * @param pVCpu The cross context virtual CPU structure.
1701 */
1702IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1703{
1704 /*
1705 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1706 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1707 */
1708 /* CS, SS, ES, DS, FS, GS. */
1709 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1710 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1711 {
1712 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1713 if (!pSelReg->Attr.n.u1Unusable)
1714 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1715 else
1716 {
1717 /*
1718 * For unusable segments the attributes are undefined except for CS and SS.
1719 * For the rest we don't bother preserving anything but the unusable bit.
1720 */
1721 switch (iSegReg)
1722 {
1723 case X86_SREG_CS:
1724 pVmcs->GuestCs = pSelReg->Sel;
1725 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1726 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1727 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1728 | X86DESCATTR_UNUSABLE);
1729 break;
1730
1731 case X86_SREG_SS:
1732 pVmcs->GuestSs = pSelReg->Sel;
1733 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1734 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1735 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1736 break;
1737
1738 case X86_SREG_DS:
1739 pVmcs->GuestDs = pSelReg->Sel;
1740 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1741 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1742 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1743 break;
1744
1745 case X86_SREG_ES:
1746 pVmcs->GuestEs = pSelReg->Sel;
1747 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1748 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1749 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1750 break;
1751
1752 case X86_SREG_FS:
1753 pVmcs->GuestFs = pSelReg->Sel;
1754 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1755 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1756 break;
1757
1758 case X86_SREG_GS:
1759 pVmcs->GuestGs = pSelReg->Sel;
1760 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1761 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1762 break;
1763 }
1764 }
1765 }
1766
1767 /* Segment attribute bits 31:7 and 11:8 MBZ. */
1768 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1769 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_UNUSABLE;
1770 /* LDTR. */
1771 {
1772 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1773 pVmcs->GuestLdtr = pSelReg->Sel;
1774 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1775 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1776 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1777 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1778 }
1779
1780 /* TR. */
1781 {
1782 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1783 pVmcs->GuestTr = pSelReg->Sel;
1784 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1785 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1786 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1787 }
1788
1789 /* GDTR. */
1790 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1791 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1792
1793 /* IDTR. */
1794 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1795 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1796}
1797
1798
1799/**
1800 * Saves guest non-register state as part of VM-exit.
1801 *
1802 * @param pVCpu The cross context virtual CPU structure.
1803 * @param uExitReason The VM-exit reason.
1804 */
1805IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1806{
1807 /*
1808 * Save guest non-register state.
1809 * See Intel spec. 27.3.4 "Saving Non-Register State".
1810 */
1811 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1812
1813 /*
1814 * Activity state.
1815 * Most VM-exits will occur in the active state. However, if the first instruction
1816 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1817 * the VM-exit will be from the HLT activity state.
1818 *
1819 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1820 */
1821 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1822 * not? */
1823 EMSTATE enmActivityState = EMGetState(pVCpu);
1824 switch (enmActivityState)
1825 {
1826 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1827 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1828 }
1829
1830 /* Interruptibility-state. */
1831 pVmcs->u32GuestIntrState = 0;
1832 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1833 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1834
1835 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1836 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1837 {
1838 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1839 * currently. */
1840 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1841 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1842 }
1843 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1844
1845 /*
1846 * Pending debug exceptions.
1847 */
1848 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1849 && uExitReason != VMX_EXIT_SMI
1850 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1851 && !HMVmxIsVmexitTrapLike(uExitReason))
1852 {
1853 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1854 * block-by-MovSS is in effect. */
1855 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1856 }
1857 else
1858 {
1859 /*
1860 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1861 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1862 *
1863 * See Intel spec. 24.4.2 "Guest Non-Register State".
1864 */
1865 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1866 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1867 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1868 if (fPendingDbgMask & fBpHitMask)
1869 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1870 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1871 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1872 }
1873
1874 /*
1875 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1876 *
1877 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1878 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1879 */
1880 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1881 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1882 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1883
1884 /* PDPTEs. */
1885 /* We don't support EPT yet. */
1886 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1887 pVmcs->u64GuestPdpte0.u = 0;
1888 pVmcs->u64GuestPdpte1.u = 0;
1889 pVmcs->u64GuestPdpte2.u = 0;
1890 pVmcs->u64GuestPdpte3.u = 0;
1891}
1892
1893
1894/**
1895 * Saves the guest-state as part of VM-exit.
1896 *
1897 * @returns VBox status code.
1898 * @param pVCpu The cross context virtual CPU structure.
1899 * @param uExitReason The VM-exit reason.
1900 */
1901IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1902{
1903 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1904 Assert(pVmcs);
1905
1906 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1907 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1908
1909 /** @todo r=ramshankar: The below hack is no longer necessary because we invoke the
1910 * VM-exit after updating RIP. I'm leaving it in-place temporarily in case
1911 * we need to fix missing exit information or callers still setting
1912 * instruction-length field when it is not necessary. */
1913#if 0
1914 /*
1915 * Save guest RIP, RSP and RFLAGS.
1916 * See Intel spec. 27.3.3 "Saving RIP, RSP and RFLAGS".
1917 *
1918 * For trap-like VM-exits we must advance the RIP by the length of the instruction.
1919 * Callers must pass the instruction length in the VM-exit instruction length
1920 * field though it is undefined for such VM-exits. After updating RIP here, we clear
1921 * the VM-exit instruction length field.
1922 *
1923 * See Intel spec. 27.1 "Architectural State Before A VM Exit"
1924 */
1925 if (HMVmxIsTrapLikeVmexit(uExitReason))
1926 {
1927 uint8_t const cbInstr = pVmcs->u32RoExitInstrLen;
1928 AssertMsg(cbInstr >= 1 && cbInstr <= 15, ("uReason=%u cbInstr=%u\n", uExitReason, cbInstr));
1929 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1930 iemVmxVmcsSetExitInstrLen(pVCpu, 0 /* cbInstr */);
1931 }
1932#endif
1933
1934 /* We don't support enclave mode yet. */
1935 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1936 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1937 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1938
1939 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1940}
1941
1942
1943/**
1944 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
1945 *
1946 * @returns VBox status code.
1947 * @param pVCpu The cross context virtual CPU structure.
1948 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1949 */
1950IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1951{
1952 /*
1953 * Save guest MSRs.
1954 * See Intel spec. 27.4 "Saving MSRs".
1955 */
1956 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1957 const char *const pszFailure = "VMX-abort";
1958
1959 /*
1960 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1961 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1962 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1963 */
1964 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1965 if (!cMsrs)
1966 return VINF_SUCCESS;
1967
1968 /*
1969 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1970 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1971 * implementation causes a VMX-abort followed by a triple-fault.
1972 */
1973 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1974 if (fIsMsrCountValid)
1975 { /* likely */ }
1976 else
1977 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1978
1979 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
1980 Assert(pMsr);
1981 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1982 {
1983 if ( !pMsr->u32Reserved
1984 && pMsr->u32Msr != MSR_IA32_SMBASE
1985 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1986 {
1987 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1988 if (rcStrict == VINF_SUCCESS)
1989 continue;
1990
1991 /*
1992 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1993 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1994 * recording the MSR index in the auxiliary info. field and indicated further by our
1995 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1996 * if possible, or come up with a better, generic solution.
1997 */
1998 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1999 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
2000 ? kVmxVDiag_Vmexit_MsrStoreRing3
2001 : kVmxVDiag_Vmexit_MsrStore;
2002 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2003 }
2004 else
2005 {
2006 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2007 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
2008 }
2009 }
2010
2011 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
2012 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
2013 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), cMsrs * sizeof(VMXAUTOMSR));
2014 if (RT_SUCCESS(rc))
2015 { /* likely */ }
2016 else
2017 {
2018 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2019 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
2020 }
2021
2022 NOREF(uExitReason);
2023 NOREF(pszFailure);
2024 return VINF_SUCCESS;
2025}
2026
2027
2028/**
2029 * Performs a VMX abort (due to an fatal error during VM-exit).
2030 *
2031 * @returns Strict VBox status code.
2032 * @param pVCpu The cross context virtual CPU structure.
2033 * @param enmAbort The VMX abort reason.
2034 */
2035IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
2036{
2037 /*
2038 * Perform the VMX abort.
2039 * See Intel spec. 27.7 "VMX Aborts".
2040 */
2041 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMVmxGetAbortDesc(enmAbort)));
2042
2043 /* We don't support SMX yet. */
2044 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2045 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2046 {
2047 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2048 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
2049 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2050 }
2051
2052 return VINF_EM_TRIPLE_FAULT;
2053}
2054
2055
2056/**
2057 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2058 *
2059 * @param pVCpu The cross context virtual CPU structure.
2060 */
2061IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2062{
2063 /*
2064 * Load host control registers, debug registers and MSRs.
2065 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2066 */
2067 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2068 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2069
2070 /* CR0. */
2071 {
2072 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2073 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2074 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2075 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2076 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2077 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2078 CPUMSetGuestCR0(pVCpu, uValidCr0);
2079 }
2080
2081 /* CR4. */
2082 {
2083 /* CR4 MB1 bits are not modified. */
2084 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2085 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2086 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2087 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2088 if (fHostInLongMode)
2089 uValidCr4 |= X86_CR4_PAE;
2090 else
2091 uValidCr4 &= ~X86_CR4_PCIDE;
2092 CPUMSetGuestCR4(pVCpu, uValidCr4);
2093 }
2094
2095 /* CR3 (host value validated while checking host-state during VM-entry). */
2096 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2097
2098 /* DR7. */
2099 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2100
2101 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2102
2103 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2104 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2105 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2106 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2107
2108 /* FS, GS bases are loaded later while we load host segment registers. */
2109
2110 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2111 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2112 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2113 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2114 {
2115 if (fHostInLongMode)
2116 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2117 else
2118 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2119 }
2120
2121 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2122
2123 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2124 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2125 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2126
2127 /* We don't support IA32_BNDCFGS MSR yet. */
2128}
2129
2130
2131/**
2132 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2133 *
2134 * @param pVCpu The cross context virtual CPU structure.
2135 */
2136IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2137{
2138 /*
2139 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2140 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2141 *
2142 * Warning! Be careful to not touch fields that are reserved by VT-x,
2143 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2144 */
2145 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2146 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2147
2148 /* CS, SS, ES, DS, FS, GS. */
2149 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2150 {
2151 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2152 bool const fUnusable = RT_BOOL(HostSel == 0);
2153 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2154
2155 /* Selector. */
2156 pSelReg->Sel = HostSel;
2157 pSelReg->ValidSel = HostSel;
2158 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2159
2160 /* Limit. */
2161 pSelReg->u32Limit = 0xffffffff;
2162
2163 /* Base. */
2164 pSelReg->u64Base = 0;
2165
2166 /* Attributes. */
2167 if (iSegReg == X86_SREG_CS)
2168 {
2169 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2170 pSelReg->Attr.n.u1DescType = 1;
2171 pSelReg->Attr.n.u2Dpl = 0;
2172 pSelReg->Attr.n.u1Present = 1;
2173 pSelReg->Attr.n.u1Long = fHostInLongMode;
2174 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2175 pSelReg->Attr.n.u1Granularity = 1;
2176 Assert(!pSelReg->Attr.n.u1Unusable);
2177 Assert(!fUnusable);
2178 }
2179 else
2180 {
2181 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2182 pSelReg->Attr.n.u1DescType = 1;
2183 pSelReg->Attr.n.u2Dpl = 0;
2184 pSelReg->Attr.n.u1Present = 1;
2185 pSelReg->Attr.n.u1DefBig = 1;
2186 pSelReg->Attr.n.u1Granularity = 1;
2187 pSelReg->Attr.n.u1Unusable = fUnusable;
2188 }
2189 }
2190
2191 /* FS base. */
2192 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2193 || fHostInLongMode)
2194 {
2195 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2196 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2197 }
2198
2199 /* GS base. */
2200 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2201 || fHostInLongMode)
2202 {
2203 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2204 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2205 }
2206
2207 /* TR. */
2208 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2209 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2210 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2211 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2212 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2213 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2214 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2215 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2216 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2217 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2218 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2219 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2220 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2221
2222 /* LDTR (Warning! do not touch the base and limits here). */
2223 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2224 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2225 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2226 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2227
2228 /* GDTR. */
2229 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2230 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2231 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2232
2233 /* IDTR.*/
2234 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2235 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2236 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2237}
2238
2239
2240/**
2241 * Checks host PDPTes as part of VM-exit.
2242 *
2243 * @param pVCpu The cross context virtual CPU structure.
2244 * @param uExitReason The VM-exit reason (for logging purposes).
2245 */
2246IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2247{
2248 /*
2249 * Check host PDPTEs.
2250 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2251 */
2252 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2253 const char *const pszFailure = "VMX-abort";
2254 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2255
2256 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2257 && !fHostInLongMode)
2258 {
2259 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2260 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2261 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2262 if (RT_SUCCESS(rc))
2263 {
2264 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2265 {
2266 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2267 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2268 { /* likely */ }
2269 else
2270 {
2271 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2272 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2273 }
2274 }
2275 }
2276 else
2277 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2278 }
2279
2280 NOREF(pszFailure);
2281 NOREF(uExitReason);
2282 return VINF_SUCCESS;
2283}
2284
2285
2286/**
2287 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2288 *
2289 * @returns VBox status code.
2290 * @param pVCpu The cross context virtual CPU structure.
2291 * @param pszInstr The VMX instruction name (for logging purposes).
2292 */
2293IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2294{
2295 /*
2296 * Load host MSRs.
2297 * See Intel spec. 27.6 "Loading MSRs".
2298 */
2299 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2300 const char *const pszFailure = "VMX-abort";
2301
2302 /*
2303 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2304 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2305 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2306 */
2307 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2308 if (!cMsrs)
2309 return VINF_SUCCESS;
2310
2311 /*
2312 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2313 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2314 * implementation causes a VMX-abort followed by a triple-fault.
2315 */
2316 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2317 if (fIsMsrCountValid)
2318 { /* likely */ }
2319 else
2320 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2321
2322 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea));
2323 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2324 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2325 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
2326 if (RT_SUCCESS(rc))
2327 {
2328 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2329 Assert(pMsr);
2330 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2331 {
2332 if ( !pMsr->u32Reserved
2333 && pMsr->u32Msr != MSR_K8_FS_BASE
2334 && pMsr->u32Msr != MSR_K8_GS_BASE
2335 && pMsr->u32Msr != MSR_K6_EFER
2336 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2337 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2338 {
2339 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2340 if (rcStrict == VINF_SUCCESS)
2341 continue;
2342
2343 /*
2344 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2345 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2346 * recording the MSR index in the auxiliary info. field and indicated further by our
2347 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2348 * if possible, or come up with a better, generic solution.
2349 */
2350 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2351 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2352 ? kVmxVDiag_Vmexit_MsrLoadRing3
2353 : kVmxVDiag_Vmexit_MsrLoad;
2354 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2355 }
2356 else
2357 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2358 }
2359 }
2360 else
2361 {
2362 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2363 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2364 }
2365
2366 NOREF(uExitReason);
2367 NOREF(pszFailure);
2368 return VINF_SUCCESS;
2369}
2370
2371
2372/**
2373 * Loads the host state as part of VM-exit.
2374 *
2375 * @returns Strict VBox status code.
2376 * @param pVCpu The cross context virtual CPU structure.
2377 * @param uExitReason The VM-exit reason (for logging purposes).
2378 */
2379IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2380{
2381 /*
2382 * Load host state.
2383 * See Intel spec. 27.5 "Loading Host State".
2384 */
2385 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2386 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2387
2388 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2389 if ( CPUMIsGuestInLongMode(pVCpu)
2390 && !fHostInLongMode)
2391 {
2392 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2393 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2394 }
2395
2396 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2397 iemVmxVmexitLoadHostSegRegs(pVCpu);
2398
2399 /*
2400 * Load host RIP, RSP and RFLAGS.
2401 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2402 */
2403 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2404 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2405 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2406
2407 /* Clear address range monitoring. */
2408 EMMonitorWaitClear(pVCpu);
2409
2410 /* Perform the VMX transition (PGM updates). */
2411 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2412 if (rcStrict == VINF_SUCCESS)
2413 {
2414 /* Check host PDPTEs (only when we've fully switched page tables_. */
2415 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2416 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2417 if (RT_FAILURE(rc))
2418 {
2419 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2420 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2421 }
2422 }
2423 else if (RT_SUCCESS(rcStrict))
2424 {
2425 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2426 uExitReason));
2427 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2428 }
2429 else
2430 {
2431 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2432 return VBOXSTRICTRC_VAL(rcStrict);
2433 }
2434
2435 Assert(rcStrict == VINF_SUCCESS);
2436
2437 /* Load MSRs from the VM-exit auto-load MSR area. */
2438 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2439 if (RT_FAILURE(rc))
2440 {
2441 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2442 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2443 }
2444 return VINF_SUCCESS;
2445}
2446
2447
2448/**
2449 * Gets VM-exit instruction information along with any displacement for an
2450 * instruction VM-exit.
2451 *
2452 * @returns The VM-exit instruction information.
2453 * @param pVCpu The cross context virtual CPU structure.
2454 * @param uExitReason The VM-exit reason.
2455 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2456 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2457 * NULL.
2458 */
2459IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2460{
2461 RTGCPTR GCPtrDisp;
2462 VMXEXITINSTRINFO ExitInstrInfo;
2463 ExitInstrInfo.u = 0;
2464
2465 /*
2466 * Get and parse the ModR/M byte from our decoded opcodes.
2467 */
2468 uint8_t bRm;
2469 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2470 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2471 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2472 {
2473 /*
2474 * ModR/M indicates register addressing.
2475 *
2476 * The primary/secondary register operands are reported in the iReg1 or iReg2
2477 * fields depending on whether it is a read/write form.
2478 */
2479 uint8_t idxReg1;
2480 uint8_t idxReg2;
2481 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2482 {
2483 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2484 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2485 }
2486 else
2487 {
2488 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2489 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2490 }
2491 ExitInstrInfo.All.u2Scaling = 0;
2492 ExitInstrInfo.All.iReg1 = idxReg1;
2493 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2494 ExitInstrInfo.All.fIsRegOperand = 1;
2495 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2496 ExitInstrInfo.All.iSegReg = 0;
2497 ExitInstrInfo.All.iIdxReg = 0;
2498 ExitInstrInfo.All.fIdxRegInvalid = 1;
2499 ExitInstrInfo.All.iBaseReg = 0;
2500 ExitInstrInfo.All.fBaseRegInvalid = 1;
2501 ExitInstrInfo.All.iReg2 = idxReg2;
2502
2503 /* Displacement not applicable for register addressing. */
2504 GCPtrDisp = 0;
2505 }
2506 else
2507 {
2508 /*
2509 * ModR/M indicates memory addressing.
2510 */
2511 uint8_t uScale = 0;
2512 bool fBaseRegValid = false;
2513 bool fIdxRegValid = false;
2514 uint8_t iBaseReg = 0;
2515 uint8_t iIdxReg = 0;
2516 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2517 {
2518 /*
2519 * Parse the ModR/M, displacement for 16-bit addressing mode.
2520 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2521 */
2522 uint16_t u16Disp = 0;
2523 uint8_t const offDisp = offModRm + sizeof(bRm);
2524 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2525 {
2526 /* Displacement without any registers. */
2527 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2528 }
2529 else
2530 {
2531 /* Register (index and base). */
2532 switch (bRm & X86_MODRM_RM_MASK)
2533 {
2534 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2535 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2536 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2537 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2538 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2539 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2540 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2541 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2542 }
2543
2544 /* Register + displacement. */
2545 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2546 {
2547 case 0: break;
2548 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2549 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2550 default:
2551 {
2552 /* Register addressing, handled at the beginning. */
2553 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2554 break;
2555 }
2556 }
2557 }
2558
2559 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2560 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2561 }
2562 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2563 {
2564 /*
2565 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2566 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2567 */
2568 uint32_t u32Disp = 0;
2569 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2570 {
2571 /* Displacement without any registers. */
2572 uint8_t const offDisp = offModRm + sizeof(bRm);
2573 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2574 }
2575 else
2576 {
2577 /* Register (and perhaps scale, index and base). */
2578 uint8_t offDisp = offModRm + sizeof(bRm);
2579 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2580 if (iBaseReg == 4)
2581 {
2582 /* An SIB byte follows the ModR/M byte, parse it. */
2583 uint8_t bSib;
2584 uint8_t const offSib = offModRm + sizeof(bRm);
2585 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2586
2587 /* A displacement may follow SIB, update its offset. */
2588 offDisp += sizeof(bSib);
2589
2590 /* Get the scale. */
2591 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2592
2593 /* Get the index register. */
2594 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2595 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2596
2597 /* Get the base register. */
2598 iBaseReg = bSib & X86_SIB_BASE_MASK;
2599 fBaseRegValid = true;
2600 if (iBaseReg == 5)
2601 {
2602 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2603 {
2604 /* Mod is 0 implies a 32-bit displacement with no base. */
2605 fBaseRegValid = false;
2606 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2607 }
2608 else
2609 {
2610 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2611 iBaseReg = X86_GREG_xBP;
2612 }
2613 }
2614 }
2615
2616 /* Register + displacement. */
2617 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2618 {
2619 case 0: /* Handled above */ break;
2620 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2621 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2622 default:
2623 {
2624 /* Register addressing, handled at the beginning. */
2625 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2626 break;
2627 }
2628 }
2629 }
2630
2631 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2632 }
2633 else
2634 {
2635 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2636
2637 /*
2638 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2639 * See Intel instruction spec. 2.2 "IA-32e Mode".
2640 */
2641 uint64_t u64Disp = 0;
2642 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2643 if (fRipRelativeAddr)
2644 {
2645 /*
2646 * RIP-relative addressing mode.
2647 *
2648 * The displacement is 32-bit signed implying an offset range of +/-2G.
2649 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2650 */
2651 uint8_t const offDisp = offModRm + sizeof(bRm);
2652 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2653 }
2654 else
2655 {
2656 uint8_t offDisp = offModRm + sizeof(bRm);
2657
2658 /*
2659 * Register (and perhaps scale, index and base).
2660 *
2661 * REX.B extends the most-significant bit of the base register. However, REX.B
2662 * is ignored while determining whether an SIB follows the opcode. Hence, we
2663 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2664 *
2665 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2666 */
2667 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2668 if (iBaseReg == 4)
2669 {
2670 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2671 uint8_t bSib;
2672 uint8_t const offSib = offModRm + sizeof(bRm);
2673 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2674
2675 /* Displacement may follow SIB, update its offset. */
2676 offDisp += sizeof(bSib);
2677
2678 /* Get the scale. */
2679 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2680
2681 /* Get the index. */
2682 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2683 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2684
2685 /* Get the base. */
2686 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2687 fBaseRegValid = true;
2688 if (iBaseReg == 5)
2689 {
2690 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2691 {
2692 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2693 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2694 }
2695 else
2696 {
2697 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2698 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2699 }
2700 }
2701 }
2702 iBaseReg |= pVCpu->iem.s.uRexB;
2703
2704 /* Register + displacement. */
2705 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2706 {
2707 case 0: /* Handled above */ break;
2708 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2709 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2710 default:
2711 {
2712 /* Register addressing, handled at the beginning. */
2713 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2714 break;
2715 }
2716 }
2717 }
2718
2719 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2720 }
2721
2722 /*
2723 * The primary or secondary register operand is reported in iReg2 depending
2724 * on whether the primary operand is in read/write form.
2725 */
2726 uint8_t idxReg2;
2727 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2728 {
2729 idxReg2 = bRm & X86_MODRM_RM_MASK;
2730 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2731 idxReg2 |= pVCpu->iem.s.uRexB;
2732 }
2733 else
2734 {
2735 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2736 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2737 idxReg2 |= pVCpu->iem.s.uRexReg;
2738 }
2739 ExitInstrInfo.All.u2Scaling = uScale;
2740 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2741 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2742 ExitInstrInfo.All.fIsRegOperand = 0;
2743 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2744 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2745 ExitInstrInfo.All.iIdxReg = iIdxReg;
2746 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2747 ExitInstrInfo.All.iBaseReg = iBaseReg;
2748 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2749 ExitInstrInfo.All.iReg2 = idxReg2;
2750 }
2751
2752 /*
2753 * Handle exceptions to the norm for certain instructions.
2754 * (e.g. some instructions convey an instruction identity in place of iReg2).
2755 */
2756 switch (uExitReason)
2757 {
2758 case VMX_EXIT_GDTR_IDTR_ACCESS:
2759 {
2760 Assert(VMXINSTRID_IS_VALID(uInstrId));
2761 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2762 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2763 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2764 break;
2765 }
2766
2767 case VMX_EXIT_LDTR_TR_ACCESS:
2768 {
2769 Assert(VMXINSTRID_IS_VALID(uInstrId));
2770 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2771 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2772 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2773 break;
2774 }
2775
2776 case VMX_EXIT_RDRAND:
2777 case VMX_EXIT_RDSEED:
2778 {
2779 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2780 break;
2781 }
2782 }
2783
2784 /* Update displacement and return the constructed VM-exit instruction information field. */
2785 if (pGCPtrDisp)
2786 *pGCPtrDisp = GCPtrDisp;
2787
2788 return ExitInstrInfo.u;
2789}
2790
2791
2792/**
2793 * VMX VM-exit handler.
2794 *
2795 * @returns Strict VBox status code.
2796 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2797 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2798 * triple-fault.
2799 *
2800 * @param pVCpu The cross context virtual CPU structure.
2801 * @param uExitReason The VM-exit reason.
2802 *
2803 * @remarks Make sure VM-exit qualification is updated before calling this
2804 * function!
2805 */
2806IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2807{
2808# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2809 RT_NOREF2(pVCpu, uExitReason);
2810 return VINF_EM_RAW_EMULATE_INSTR;
2811# else
2812 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
2813
2814 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2815 Assert(pVmcs);
2816
2817 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2818 pVmcs->u32RoExitReason = uExitReason;
2819 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64\n", uExitReason, pVmcs->u64RoExitQual));
2820
2821 /*
2822 * Save the guest state back into the VMCS.
2823 * We only need to save the state when the VM-entry was successful.
2824 */
2825 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2826 if (!fVmentryFailed)
2827 {
2828 /*
2829 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2830 * occurs in enclave mode/SMM which we don't support yet.
2831 *
2832 * If we ever add support for it, we can pass just the lower bits to the functions
2833 * below, till then an assert should suffice.
2834 */
2835 Assert(!RT_HI_U16(uExitReason));
2836
2837 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2838 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2839 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2840 if (RT_SUCCESS(rc))
2841 { /* likely */ }
2842 else
2843 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2844
2845 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2846 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2847 }
2848 else
2849 {
2850 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2851 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2852 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2853 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2854 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2855 }
2856
2857 /* Restore the host (outer guest) state. */
2858 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2859 if (RT_SUCCESS(rcStrict))
2860 {
2861 Assert(rcStrict == VINF_SUCCESS);
2862 rcStrict = VINF_VMX_VMEXIT;
2863 }
2864 else
2865 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2866
2867 /* We're no longer in nested-guest execution mode. */
2868 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2869
2870#ifdef IN_RING3
2871 LogRel(("vmexit: uExitReason=%s\n", HMR3GetVmxExitName(uExitReason)));
2872#endif
2873
2874 /* Revert any IEM-only nested-guest execution policy if it was set earlier, otherwise return rcStrict. */
2875 IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(pVCpu, "VM-exit", rcStrict);
2876# endif
2877}
2878
2879
2880/**
2881 * VMX VM-exit handler for VM-exits due to instruction execution.
2882 *
2883 * This is intended for instructions where the caller provides all the relevant
2884 * VM-exit information.
2885 *
2886 * @returns Strict VBox status code.
2887 * @param pVCpu The cross context virtual CPU structure.
2888 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2889 */
2890DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2891{
2892 /*
2893 * For instructions where any of the following fields are not applicable:
2894 * - VM-exit instruction info. is undefined.
2895 * - VM-exit qualification must be cleared.
2896 * - VM-exit guest-linear address is undefined.
2897 * - VM-exit guest-physical address is undefined.
2898 *
2899 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2900 * instruction execution. For VM-exits that are not due to instruction execution this
2901 * field is undefined.
2902 *
2903 * In our implementation in IEM, all undefined fields are generally cleared. However,
2904 * if the caller supplies information (from say the physical CPU directly) it is
2905 * then possible that the undefined fields are not cleared.
2906 *
2907 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2908 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2909 */
2910 Assert(pExitInfo);
2911 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2912 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2913 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2914
2915 /* Update all the relevant fields from the VM-exit instruction information struct. */
2916 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2917 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2918 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2919 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2920 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2921
2922 /* Perform the VM-exit. */
2923 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2924}
2925
2926
2927/**
2928 * VMX VM-exit handler for VM-exits due to instruction execution.
2929 *
2930 * This is intended for instructions that only provide the VM-exit instruction
2931 * length.
2932 *
2933 * @param pVCpu The cross context virtual CPU structure.
2934 * @param uExitReason The VM-exit reason.
2935 * @param cbInstr The instruction length in bytes.
2936 */
2937IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2938{
2939 VMXVEXITINFO ExitInfo;
2940 RT_ZERO(ExitInfo);
2941 ExitInfo.uReason = uExitReason;
2942 ExitInfo.cbInstr = cbInstr;
2943
2944#ifdef VBOX_STRICT
2945 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2946 switch (uExitReason)
2947 {
2948 case VMX_EXIT_INVEPT:
2949 case VMX_EXIT_INVPCID:
2950 case VMX_EXIT_LDTR_TR_ACCESS:
2951 case VMX_EXIT_GDTR_IDTR_ACCESS:
2952 case VMX_EXIT_VMCLEAR:
2953 case VMX_EXIT_VMPTRLD:
2954 case VMX_EXIT_VMPTRST:
2955 case VMX_EXIT_VMREAD:
2956 case VMX_EXIT_VMWRITE:
2957 case VMX_EXIT_VMXON:
2958 case VMX_EXIT_XRSTORS:
2959 case VMX_EXIT_XSAVES:
2960 case VMX_EXIT_RDRAND:
2961 case VMX_EXIT_RDSEED:
2962 case VMX_EXIT_IO_INSTR:
2963 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2964 break;
2965 }
2966#endif
2967
2968 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2969}
2970
2971
2972/**
2973 * VMX VM-exit handler for VM-exits due to instruction execution.
2974 *
2975 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2976 * instruction information and VM-exit qualification fields.
2977 *
2978 * @param pVCpu The cross context virtual CPU structure.
2979 * @param uExitReason The VM-exit reason.
2980 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2981 * @param cbInstr The instruction length in bytes.
2982 *
2983 * @remarks Do not use this for INS/OUTS instruction.
2984 */
2985IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2986{
2987 VMXVEXITINFO ExitInfo;
2988 RT_ZERO(ExitInfo);
2989 ExitInfo.uReason = uExitReason;
2990 ExitInfo.cbInstr = cbInstr;
2991
2992 /*
2993 * Update the VM-exit qualification field with displacement bytes.
2994 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2995 */
2996 switch (uExitReason)
2997 {
2998 case VMX_EXIT_INVEPT:
2999 case VMX_EXIT_INVPCID:
3000 case VMX_EXIT_LDTR_TR_ACCESS:
3001 case VMX_EXIT_GDTR_IDTR_ACCESS:
3002 case VMX_EXIT_VMCLEAR:
3003 case VMX_EXIT_VMPTRLD:
3004 case VMX_EXIT_VMPTRST:
3005 case VMX_EXIT_VMREAD:
3006 case VMX_EXIT_VMWRITE:
3007 case VMX_EXIT_VMXON:
3008 case VMX_EXIT_XRSTORS:
3009 case VMX_EXIT_XSAVES:
3010 case VMX_EXIT_RDRAND:
3011 case VMX_EXIT_RDSEED:
3012 {
3013 /* Construct the VM-exit instruction information. */
3014 RTGCPTR GCPtrDisp;
3015 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3016
3017 /* Update the VM-exit instruction information. */
3018 ExitInfo.InstrInfo.u = uInstrInfo;
3019
3020 /* Update the VM-exit qualification. */
3021 ExitInfo.u64Qual = GCPtrDisp;
3022 break;
3023 }
3024
3025 default:
3026 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3027 break;
3028 }
3029
3030 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3031}
3032
3033
3034/**
3035 * Checks whether an I/O instruction for the given port is intercepted (causes a
3036 * VM-exit) or not.
3037 *
3038 * @returns @c true if the instruction is intercepted, @c false otherwise.
3039 * @param pVCpu The cross context virtual CPU structure.
3040 * @param u16Port The I/O port being accessed by the instruction.
3041 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3042 */
3043IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3044{
3045 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3046 Assert(pVmcs);
3047
3048 /*
3049 * Check whether the I/O instruction must cause a VM-exit or not.
3050 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3051 */
3052 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3053 return true;
3054
3055 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3056 {
3057 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3058 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3059 Assert(pbIoBitmapA);
3060 Assert(pbIoBitmapB);
3061 return HMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3062 }
3063
3064 return false;
3065}
3066
3067
3068/**
3069 * VMX VM-exit handler for VM-exits due to Monitor-Trap Flag (MTF).
3070 *
3071 * @returns Strict VBox status code.
3072 * @param pVCpu The cross context virtual CPU structure.
3073 */
3074IEM_STATIC VBOXSTRICTRC iemVmxVmexitMtf(PVMCPU pVCpu)
3075{
3076 /*
3077 * The MTF VM-exit can occur even when the MTF VM-execution control is
3078 * not set (e.g. when VM-entry injects an MTF pending event), so do not
3079 * check for it here.
3080 */
3081
3082 /* Clear the force-flag indicating that monitor-trap flag is no longer active. */
3083 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
3084
3085 /* Cause the MTF VM-exit. The VM-exit qualification MBZ. */
3086 return iemVmxVmexit(pVCpu, VMX_EXIT_MTF);
3087}
3088
3089
3090/**
3091 * VMX VM-exit handler for VM-exits due to INVLPG.
3092 *
3093 * @returns Strict VBox status code.
3094 * @param pVCpu The cross context virtual CPU structure.
3095 * @param GCPtrPage The guest-linear address of the page being invalidated.
3096 * @param cbInstr The instruction length in bytes.
3097 */
3098IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3099{
3100 VMXVEXITINFO ExitInfo;
3101 RT_ZERO(ExitInfo);
3102 ExitInfo.uReason = VMX_EXIT_INVLPG;
3103 ExitInfo.cbInstr = cbInstr;
3104 ExitInfo.u64Qual = GCPtrPage;
3105 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3106
3107 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3108}
3109
3110
3111/**
3112 * VMX VM-exit handler for VM-exits due to LMSW.
3113 *
3114 * @returns Strict VBox status code.
3115 * @param pVCpu The cross context virtual CPU structure.
3116 * @param uGuestCr0 The current guest CR0.
3117 * @param pu16NewMsw The machine-status word specified in LMSW's source
3118 * operand. This will be updated depending on the VMX
3119 * guest/host CR0 mask if LMSW is not intercepted.
3120 * @param GCPtrEffDst The guest-linear address of the source operand in case
3121 * of a memory operand. For register operand, pass
3122 * NIL_RTGCPTR.
3123 * @param cbInstr The instruction length in bytes.
3124 */
3125IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3126 uint8_t cbInstr)
3127{
3128 /*
3129 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3130 *
3131 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3132 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3133 */
3134 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3135 Assert(pVmcs);
3136 Assert(pu16NewMsw);
3137
3138 bool fIntercept = false;
3139 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3140 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3141
3142 /*
3143 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3144 * CR0.PE case first, before the rest of the bits in the MSW.
3145 *
3146 * If CR0.PE is owned by the host and CR0.PE differs between the
3147 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3148 */
3149 if ( (fGstHostMask & X86_CR0_PE)
3150 && (*pu16NewMsw & X86_CR0_PE)
3151 && !(fReadShadow & X86_CR0_PE))
3152 fIntercept = true;
3153
3154 /*
3155 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3156 * bits differ between the MSW (source operand) and the read-shadow, we must
3157 * cause a VM-exit.
3158 */
3159 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3160 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3161 fIntercept = true;
3162
3163 if (fIntercept)
3164 {
3165 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3166
3167 VMXVEXITINFO ExitInfo;
3168 RT_ZERO(ExitInfo);
3169 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3170 ExitInfo.cbInstr = cbInstr;
3171
3172 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3173 if (fMemOperand)
3174 {
3175 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3176 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3177 }
3178
3179 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3180 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3181 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3182 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3183
3184 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3185 }
3186
3187 /*
3188 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3189 * CR0 guest/host mask must be left unmodified.
3190 *
3191 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3192 */
3193 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3194 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3195
3196 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3197}
3198
3199
3200/**
3201 * VMX VM-exit handler for VM-exits due to CLTS.
3202 *
3203 * @returns Strict VBox status code.
3204 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3205 * VM-exit but must not modify the guest CR0.TS bit.
3206 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3207 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3208 * CR0 fixed bits in VMX operation).
3209 * @param pVCpu The cross context virtual CPU structure.
3210 * @param cbInstr The instruction length in bytes.
3211 */
3212IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3213{
3214 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3215 Assert(pVmcs);
3216
3217 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3218 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3219
3220 /*
3221 * If CR0.TS is owned by the host:
3222 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3223 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3224 * CLTS instruction completes without clearing CR0.TS.
3225 *
3226 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3227 */
3228 if (fGstHostMask & X86_CR0_TS)
3229 {
3230 if (fReadShadow & X86_CR0_TS)
3231 {
3232 Log2(("clts: Guest intercept -> VM-exit\n"));
3233
3234 VMXVEXITINFO ExitInfo;
3235 RT_ZERO(ExitInfo);
3236 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3237 ExitInfo.cbInstr = cbInstr;
3238
3239 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3240 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3241 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3242 }
3243
3244 return VINF_VMX_MODIFIES_BEHAVIOR;
3245 }
3246
3247 /*
3248 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3249 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3250 */
3251 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3252}
3253
3254
3255/**
3256 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3257 * (CR0/CR4 write).
3258 *
3259 * @returns Strict VBox status code.
3260 * @param pVCpu The cross context virtual CPU structure.
3261 * @param iCrReg The control register (either CR0 or CR4).
3262 * @param uGuestCrX The current guest CR0/CR4.
3263 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3264 * if no VM-exit is caused.
3265 * @param iGReg The general register from which the CR0/CR4 value is
3266 * being loaded.
3267 * @param cbInstr The instruction length in bytes.
3268 */
3269IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3270 uint8_t cbInstr)
3271{
3272 Assert(puNewCrX);
3273 Assert(iCrReg == 0 || iCrReg == 4);
3274
3275 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3276 Assert(pVmcs);
3277
3278 uint64_t uGuestCrX;
3279 uint64_t fGstHostMask;
3280 uint64_t fReadShadow;
3281 if (iCrReg == 0)
3282 {
3283 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3284 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3285 fGstHostMask = pVmcs->u64Cr0Mask.u;
3286 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3287 }
3288 else
3289 {
3290 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3291 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3292 fGstHostMask = pVmcs->u64Cr4Mask.u;
3293 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3294 }
3295
3296 /*
3297 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3298 * corresponding bits differ between the source operand and the read-shadow,
3299 * we must cause a VM-exit.
3300 *
3301 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3302 */
3303 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3304 {
3305 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3306
3307 VMXVEXITINFO ExitInfo;
3308 RT_ZERO(ExitInfo);
3309 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3310 ExitInfo.cbInstr = cbInstr;
3311
3312 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3313 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3314 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3315 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3316 }
3317
3318 /*
3319 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3320 * must not be modified the instruction.
3321 *
3322 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3323 */
3324 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3325
3326 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3327}
3328
3329
3330/**
3331 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3332 *
3333 * @returns VBox strict status code.
3334 * @param pVCpu The cross context virtual CPU structure.
3335 * @param iGReg The general register to which the CR3 value is being stored.
3336 * @param cbInstr The instruction length in bytes.
3337 */
3338IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3339{
3340 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3341 Assert(pVmcs);
3342 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3343
3344 /*
3345 * If the CR3-store exiting control is set, we must cause a VM-exit.
3346 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3347 */
3348 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3349 {
3350 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3351
3352 VMXVEXITINFO ExitInfo;
3353 RT_ZERO(ExitInfo);
3354 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3355 ExitInfo.cbInstr = cbInstr;
3356
3357 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3358 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3359 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3360 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3361 }
3362
3363 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3364}
3365
3366
3367/**
3368 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3369 *
3370 * @returns VBox strict status code.
3371 * @param pVCpu The cross context virtual CPU structure.
3372 * @param uNewCr3 The new CR3 value.
3373 * @param iGReg The general register from which the CR3 value is being
3374 * loaded.
3375 * @param cbInstr The instruction length in bytes.
3376 */
3377IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3378{
3379 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3380 Assert(pVmcs);
3381
3382 /*
3383 * If the CR3-load exiting control is set and the new CR3 value does not
3384 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3385 *
3386 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3387 */
3388 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3389 {
3390 uint32_t uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3391 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3392
3393 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3394 {
3395 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3396 if (uNewCr3 != uCr3TargetValue)
3397 {
3398 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3399
3400 VMXVEXITINFO ExitInfo;
3401 RT_ZERO(ExitInfo);
3402 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3403 ExitInfo.cbInstr = cbInstr;
3404
3405 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3406 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3407 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3408 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3409 }
3410 }
3411 }
3412
3413 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3414}
3415
3416
3417/**
3418 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3419 *
3420 * @returns VBox strict status code.
3421 * @param pVCpu The cross context virtual CPU structure.
3422 * @param iGReg The general register to which the CR8 value is being stored.
3423 * @param cbInstr The instruction length in bytes.
3424 */
3425IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3426{
3427 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3428 Assert(pVmcs);
3429
3430 /*
3431 * If the CR8-store exiting control is set, we must cause a VM-exit.
3432 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3433 */
3434 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3435 {
3436 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3437
3438 VMXVEXITINFO ExitInfo;
3439 RT_ZERO(ExitInfo);
3440 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3441 ExitInfo.cbInstr = cbInstr;
3442
3443 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3444 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3445 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3446 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3447 }
3448
3449 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3450}
3451
3452
3453/**
3454 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3455 *
3456 * @returns VBox strict status code.
3457 * @param pVCpu The cross context virtual CPU structure.
3458 * @param iGReg The general register from which the CR8 value is being
3459 * loaded.
3460 * @param cbInstr The instruction length in bytes.
3461 */
3462IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3463{
3464 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3465 Assert(pVmcs);
3466
3467 /*
3468 * If the CR8-load exiting control is set, we must cause a VM-exit.
3469 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3470 */
3471 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3472 {
3473 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3474
3475 VMXVEXITINFO ExitInfo;
3476 RT_ZERO(ExitInfo);
3477 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3478 ExitInfo.cbInstr = cbInstr;
3479
3480 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3481 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3482 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3483 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3484 }
3485
3486 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3487}
3488
3489
3490/**
3491 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3492 * GReg,DRx' (DRx read).
3493 *
3494 * @returns VBox strict status code.
3495 * @param pVCpu The cross context virtual CPU structure.
3496 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3497 * VMXINSTRID_MOV_FROM_DRX).
3498 * @param iDrReg The debug register being accessed.
3499 * @param iGReg The general register to/from which the DRx value is being
3500 * store/loaded.
3501 * @param cbInstr The instruction length in bytes.
3502 */
3503IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3504 uint8_t cbInstr)
3505{
3506 Assert(iDrReg <= 7);
3507 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3508
3509 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3510 Assert(pVmcs);
3511
3512 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3513 {
3514 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3515 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3516 VMXVEXITINFO ExitInfo;
3517 RT_ZERO(ExitInfo);
3518 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3519 ExitInfo.cbInstr = cbInstr;
3520 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3521 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3522 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3523 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3524 }
3525
3526 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3527}
3528
3529
3530/**
3531 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3532 *
3533 * @returns VBox strict status code.
3534 * @param pVCpu The cross context virtual CPU structure.
3535 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3536 * VMXINSTRID_IO_OUT).
3537 * @param u16Port The I/O port being accessed.
3538 * @param fImm Whether the I/O port was encoded using an immediate operand
3539 * or the implicit DX register.
3540 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3541 * @param cbInstr The instruction length in bytes.
3542 */
3543IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3544 uint8_t cbInstr)
3545{
3546 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3547 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3548
3549 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3550 if (fIntercept)
3551 {
3552 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3553 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3554 VMXVEXITINFO ExitInfo;
3555 RT_ZERO(ExitInfo);
3556 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3557 ExitInfo.cbInstr = cbInstr;
3558 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3559 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3560 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3561 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3562 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3563 }
3564
3565 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3566}
3567
3568
3569/**
3570 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3571 *
3572 * @returns VBox strict status code.
3573 * @param pVCpu The cross context virtual CPU structure.
3574 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3575 * VMXINSTRID_IO_OUTS).
3576 * @param u16Port The I/O port being accessed.
3577 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3578 * @param fRep Whether the instruction has a REP prefix or not.
3579 * @param ExitInstrInfo The VM-exit instruction info. field.
3580 * @param cbInstr The instruction length in bytes.
3581 */
3582IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3583 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3584{
3585 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3586 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3587 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3588 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3589 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3590
3591 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3592 if (fIntercept)
3593 {
3594 /*
3595 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3596 */
3597 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3598 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3599 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3600 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3601 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3602
3603 uint32_t uDirection;
3604 uint64_t uGuestLinearAddr;
3605 if (uInstrId == VMXINSTRID_IO_INS)
3606 {
3607 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3608 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3609 }
3610 else
3611 {
3612 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3613 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3614 }
3615
3616 /*
3617 * If the segment is ununsable, the guest-linear address in undefined.
3618 * We shall clear it for consistency.
3619 *
3620 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3621 */
3622 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3623 uGuestLinearAddr = 0;
3624
3625 VMXVEXITINFO ExitInfo;
3626 RT_ZERO(ExitInfo);
3627 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3628 ExitInfo.cbInstr = cbInstr;
3629 ExitInfo.InstrInfo = ExitInstrInfo;
3630 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3631 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3632 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3633 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3634 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3635 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3636 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3637 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3638 }
3639
3640 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3641}
3642
3643
3644/**
3645 * VMX VM-exit handler for VM-exits due to MWAIT.
3646 *
3647 * @returns VBox strict status code.
3648 * @param pVCpu The cross context virtual CPU structure.
3649 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3650 * @param cbInstr The instruction length in bytes.
3651 */
3652IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3653{
3654 VMXVEXITINFO ExitInfo;
3655 RT_ZERO(ExitInfo);
3656 ExitInfo.uReason = VMX_EXIT_MWAIT;
3657 ExitInfo.cbInstr = cbInstr;
3658 ExitInfo.u64Qual = fMonitorHwArmed;
3659 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3660}
3661
3662
3663/**
3664 * VMX VM-exit handler for VM-exits due to PAUSE.
3665 *
3666 * @returns VBox strict status code.
3667 * @param pVCpu The cross context virtual CPU structure.
3668 * @param cbInstr The instruction length in bytes.
3669 */
3670IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3671{
3672 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3673 Assert(pVmcs);
3674
3675 /*
3676 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3677 * "PAUSE-loop exiting" control.
3678 *
3679 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3680 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3681 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3682 * a VM-exit.
3683 *
3684 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3685 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3686 */
3687 bool fIntercept = false;
3688 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3689 fIntercept = true;
3690 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3691 && pVCpu->iem.s.uCpl == 0)
3692 {
3693 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3694
3695 /*
3696 * A previous-PAUSE-tick value of 0 is used to identify the first time
3697 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3698 * consider this to be the first execution of PAUSE in a loop according
3699 * to the Intel.
3700 *
3701 * All subsequent records for the previous-PAUSE-tick we ensure that it
3702 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3703 */
3704 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3705 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3706 uint64_t const uTick = TMCpuTickGet(pVCpu);
3707 uint32_t const uPleGap = pVmcs->u32PleGap;
3708 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3709 if ( *puPrevPauseTick == 0
3710 || uTick - *puPrevPauseTick > uPleGap)
3711 *puFirstPauseLoopTick = uTick;
3712 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3713 fIntercept = true;
3714
3715 *puPrevPauseTick = uTick | 1;
3716 }
3717
3718 if (fIntercept)
3719 {
3720 VMXVEXITINFO ExitInfo;
3721 RT_ZERO(ExitInfo);
3722 ExitInfo.uReason = VMX_EXIT_PAUSE;
3723 ExitInfo.cbInstr = cbInstr;
3724 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3725 }
3726
3727 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3728}
3729
3730
3731/**
3732 * VMX VM-exit handler for VM-exits due to task switches.
3733 *
3734 * @returns VBox strict status code.
3735 * @param pVCpu The cross context virtual CPU structure.
3736 * @param enmTaskSwitch The cause of the task switch.
3737 * @param SelNewTss The selector of the new TSS.
3738 * @param cbInstr The instruction length in bytes.
3739 */
3740IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3741{
3742 /*
3743 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3744 *
3745 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3746 * instruction or delivery of the exception generated by one of these instructions
3747 * lead to a task switch through a task gate in the IDT, we need to provide the
3748 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3749 * leaves the VM-exit instruction length field undefined.
3750 *
3751 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3752 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3753 */
3754 Assert(cbInstr <= 15);
3755
3756 uint8_t uType;
3757 switch (enmTaskSwitch)
3758 {
3759 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3760 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3761 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3762 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3763 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3764 }
3765
3766 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3767 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3768 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3769 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3770 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3771}
3772
3773
3774/**
3775 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3776 *
3777 * @returns VBox strict status code.
3778 * @param pVCpu The cross context virtual CPU structure.
3779 */
3780IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3781{
3782 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3783 Assert(pVmcs);
3784
3785 /* Check if the guest has enabled VMX-preemption timers in the first place. */
3786 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3787 {
3788 /*
3789 * Calculate the current VMX-preemption timer value.
3790 * Only if the value has reached zero, we cause the VM-exit.
3791 */
3792 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3793 if (!uPreemptTimer)
3794 {
3795 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3796 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3797 pVmcs->u32PreemptTimer = 0;
3798
3799 /* Clear the force-flag indicating the VMX-preemption timer no longer active. */
3800 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
3801
3802 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3803 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3804 }
3805 }
3806
3807 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3808}
3809
3810
3811/**
3812 * VMX VM-exit handler for VM-exits due to external interrupts.
3813 *
3814 * @returns VBox strict status code.
3815 * @param pVCpu The cross context virtual CPU structure.
3816 * @param uVector The external interrupt vector.
3817 * @param fIntPending Whether the external interrupt is pending or
3818 * acknowledged in the interrupt controller.
3819 */
3820IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3821{
3822 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3823 Assert(pVmcs);
3824
3825 /* The VM-exit is subject to "External interrupt exiting" is being set. */
3826 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3827 {
3828 if (fIntPending)
3829 {
3830 /*
3831 * If the interrupt is pending and we don't need to acknowledge the
3832 * interrupt on VM-exit, cause the VM-exit immediately.
3833 *
3834 * See Intel spec 25.2 "Other Causes Of VM Exits".
3835 */
3836 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3837 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3838
3839 /*
3840 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3841 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3842 * acknowledged that the interrupt has been consumed.
3843 */
3844 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3845 }
3846
3847 /*
3848 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3849 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3850 * all set, we cause the VM-exit now. We need to record the external interrupt that
3851 * just occurred in the VM-exit interruption information field.
3852 *
3853 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3854 */
3855 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3856 {
3857 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3858 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3859 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3860 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3861 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3862 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3863 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3864 }
3865 }
3866
3867 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3868}
3869
3870
3871/**
3872 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3873 *
3874 * @returns VBox strict status code.
3875 * @param pVCpu The cross context virtual CPU structure.
3876 * @param uVector The SIPI vector.
3877 */
3878IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3879{
3880 iemVmxVmcsSetExitQual(pVCpu, uVector);
3881 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3882}
3883
3884
3885/**
3886 * VMX VM-exit handler for VM-exits due to init-IPIs (INIT).
3887 *
3888 * @returns VBox strict status code.
3889 * @param pVCpu The cross context virtual CPU structure.
3890 */
3891IEM_STATIC VBOXSTRICTRC iemVmxVmexitInitIpi(PVMCPU pVCpu)
3892{
3893 return iemVmxVmexit(pVCpu, VMX_EXIT_INIT_SIGNAL);
3894}
3895
3896
3897/**
3898 * VMX VM-exit handler for interrupt-window VM-exits.
3899 *
3900 * @returns VBox strict status code.
3901 * @param pVCpu The cross context virtual CPU structure.
3902 */
3903IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3904{
3905 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3906}
3907
3908
3909/**
3910 * VMX VM-exit handler for VM-exits due to delivery of an event.
3911 *
3912 * @returns VBox strict status code.
3913 * @param pVCpu The cross context virtual CPU structure.
3914 * @param uVector The interrupt / exception vector.
3915 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3916 * @param uErrCode The error code associated with the event.
3917 * @param uCr2 The CR2 value in case of a \#PF exception.
3918 * @param cbInstr The instruction length in bytes.
3919 */
3920IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3921 uint8_t cbInstr)
3922{
3923 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3924 Assert(pVmcs);
3925
3926 /*
3927 * If the event is being injected as part of VM-entry, it isn't subject to event
3928 * intercepts in the nested-guest. However, secondary exceptions that occur during
3929 * injection of any event -are- subject to event interception.
3930 *
3931 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3932 */
3933 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3934 {
3935 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3936 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3937 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3938 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3939 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3940 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3941 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3942 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3943 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3944
3945 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3946 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3947 }
3948
3949 /*
3950 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3951 * If not, the caller will continue delivery of the external interrupt as it would
3952 * normally.
3953 */
3954 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3955 {
3956 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3957 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3958 }
3959
3960 /*
3961 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3962 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3963 */
3964 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3965 bool fIntercept = false;
3966 bool fIsHwXcpt = false;
3967 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3968 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3969 {
3970 fIsHwXcpt = true;
3971 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
3972 if (uVector == X86_XCPT_NMI)
3973 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3974 else
3975 {
3976 /* Page-faults are subject to masking using its error code. */
3977 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
3978 if (uVector == X86_XCPT_PF)
3979 {
3980 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
3981 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
3982 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
3983 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
3984 }
3985
3986 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
3987 if (fXcptBitmap & RT_BIT(uVector))
3988 fIntercept = true;
3989 }
3990 }
3991 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3992
3993 /*
3994 * Now that we've determined whether the software interrupt or hardware exception
3995 * causes a VM-exit, we need to construct the relevant VM-exit information and
3996 * cause the VM-exit.
3997 */
3998 if (fIntercept)
3999 {
4000 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4001
4002 /* Construct the rest of the event related information fields and cause the VM-exit. */
4003 uint64_t uExitQual = 0;
4004 if (fIsHwXcpt)
4005 {
4006 if (uVector == X86_XCPT_PF)
4007 {
4008 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4009 uExitQual = uCr2;
4010 }
4011 else if (uVector == X86_XCPT_DB)
4012 {
4013 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
4014 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4015 }
4016 }
4017
4018 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4019 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
4020 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4021 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4022 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4023 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4024 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4025 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4026 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4027 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4028 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4029
4030 /*
4031 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4032 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4033 * length.
4034 */
4035 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4036 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4037 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4038 else
4039 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4040
4041 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4042 }
4043
4044 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4045}
4046
4047
4048/**
4049 * VMX VM-exit handler for VM-exits due to a triple fault.
4050 *
4051 * @returns VBox strict status code.
4052 * @param pVCpu The cross context virtual CPU structure.
4053 */
4054IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4055{
4056 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4057}
4058
4059
4060/**
4061 * VMX VM-exit handler for APIC-accesses.
4062 *
4063 * @param pVCpu The cross context virtual CPU structure.
4064 * @param offAccess The offset of the register being accessed.
4065 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4066 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4067 */
4068IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4069{
4070 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4071
4072 VMXAPICACCESS enmAccess;
4073 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4074 if (fInEventDelivery)
4075 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4076 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4077 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4078 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4079 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4080 else
4081 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4082
4083 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4084 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4085 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4086 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4087}
4088
4089
4090/**
4091 * VMX VM-exit handler for APIC-write VM-exits.
4092 *
4093 * @param pVCpu The cross context virtual CPU structure.
4094 * @param offApic The write to the virtual-APIC page offset that caused this
4095 * VM-exit.
4096 */
4097IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4098{
4099 Assert(offApic < XAPIC_OFF_END + 4);
4100
4101 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4102 offApic &= UINT16_C(0xfff);
4103 iemVmxVmcsSetExitQual(pVCpu, offApic);
4104 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4105}
4106
4107
4108/**
4109 * VMX VM-exit handler for virtualized-EOIs.
4110 *
4111 * @param pVCpu The cross context virtual CPU structure.
4112 */
4113IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4114{
4115 iemVmxVmcsSetExitQual(pVCpu, uVector);
4116 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4117}
4118
4119
4120/**
4121 * Sets virtual-APIC write emulation as pending.
4122 *
4123 * @param pVCpu The cross context virtual CPU structure.
4124 * @param offApic The offset in the virtual-APIC page that was written.
4125 */
4126DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4127{
4128 Assert(offApic < XAPIC_OFF_END + 4);
4129
4130 /*
4131 * Record the currently updated APIC offset, as we need this later for figuring
4132 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4133 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4134 */
4135 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4136
4137 /*
4138 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4139 * virtualization or APIC-write emulation).
4140 */
4141 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4142 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4143}
4144
4145
4146/**
4147 * Clears any pending virtual-APIC write emulation.
4148 *
4149 * @returns The virtual-APIC offset that was written before clearing it.
4150 * @param pVCpu The cross context virtual CPU structure.
4151 */
4152DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4153{
4154 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4155 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4156 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4157 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4158 return offVirtApicWrite;
4159}
4160
4161
4162/**
4163 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4164 *
4165 * @returns The register from the virtual-APIC page.
4166 * @param pVCpu The cross context virtual CPU structure.
4167 * @param offReg The offset of the register being read.
4168 */
4169DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4170{
4171 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4172 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4173 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4174 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
4175 return uReg;
4176}
4177
4178
4179/**
4180 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4181 *
4182 * @returns The register from the virtual-APIC page.
4183 * @param pVCpu The cross context virtual CPU structure.
4184 * @param offReg The offset of the register being read.
4185 */
4186DECLINLINE(uint64_t) iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4187{
4188 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4189 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4190 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4191 uint64_t const uReg = *(const uint64_t *)(pbVirtApic + offReg);
4192 return uReg;
4193}
4194
4195
4196/**
4197 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4198 *
4199 * @param pVCpu The cross context virtual CPU structure.
4200 * @param offReg The offset of the register being written.
4201 * @param uReg The register value to write.
4202 */
4203DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4204{
4205 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4206 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4207 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4208 *(uint32_t *)(pbVirtApic + offReg) = uReg;
4209}
4210
4211
4212/**
4213 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4214 *
4215 * @param pVCpu The cross context virtual CPU structure.
4216 * @param offReg The offset of the register being written.
4217 * @param uReg The register value to write.
4218 */
4219DECLINLINE(void) iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4220{
4221 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4222 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4223 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4224 *(uint64_t *)(pbVirtApic + offReg) = uReg;
4225}
4226
4227
4228/**
4229 * Sets the vector in a virtual-APIC 256-bit sparse register.
4230 *
4231 * @param pVCpu The cross context virtual CPU structure.
4232 * @param offReg The offset of the 256-bit spare register.
4233 * @param uVector The vector to set.
4234 *
4235 * @remarks This is based on our APIC device code.
4236 */
4237DECLINLINE(void) iemVmxVirtApicSetVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4238{
4239 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4240 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4241 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4242 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4243 ASMAtomicBitSet(pbBitmap + offVector, idxVectorBit);
4244}
4245
4246
4247/**
4248 * Clears the vector in a virtual-APIC 256-bit sparse register.
4249 *
4250 * @param pVCpu The cross context virtual CPU structure.
4251 * @param offReg The offset of the 256-bit spare register.
4252 * @param uVector The vector to clear.
4253 *
4254 * @remarks This is based on our APIC device code.
4255 */
4256DECLINLINE(void) iemVmxVirtApicClearVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4257{
4258 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4259 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4260 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4261 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4262 ASMAtomicBitClear(pbBitmap + offVector, idxVectorBit);
4263}
4264
4265
4266/**
4267 * Checks if a memory access to the APIC-access page must causes an APIC-access
4268 * VM-exit.
4269 *
4270 * @param pVCpu The cross context virtual CPU structure.
4271 * @param offAccess The offset of the register being accessed.
4272 * @param cbAccess The size of the access in bytes.
4273 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4274 * IEM_ACCESS_TYPE_WRITE).
4275 *
4276 * @remarks This must not be used for MSR-based APIC-access page accesses!
4277 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4278 */
4279IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4280{
4281 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4282 Assert(pVmcs);
4283 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4284
4285 /*
4286 * We must cause a VM-exit if any of the following are true:
4287 * - TPR shadowing isn't active.
4288 * - The access size exceeds 32-bits.
4289 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4290 *
4291 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4292 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4293 */
4294 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4295 || cbAccess > sizeof(uint32_t)
4296 || ((offAccess + cbAccess - 1) & 0xc)
4297 || offAccess >= XAPIC_OFF_END + 4)
4298 return true;
4299
4300 /*
4301 * If the access is part of an operation where we have already
4302 * virtualized a virtual-APIC write, we must cause a VM-exit.
4303 */
4304 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4305 return true;
4306
4307 /*
4308 * Check write accesses to the APIC-access page that cause VM-exits.
4309 */
4310 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4311 {
4312 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4313 {
4314 /*
4315 * With APIC-register virtualization, a write access to any of the
4316 * following registers are virtualized. Accessing any other register
4317 * causes a VM-exit.
4318 */
4319 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4320 switch (offAlignedAccess)
4321 {
4322 case XAPIC_OFF_ID:
4323 case XAPIC_OFF_TPR:
4324 case XAPIC_OFF_EOI:
4325 case XAPIC_OFF_LDR:
4326 case XAPIC_OFF_DFR:
4327 case XAPIC_OFF_SVR:
4328 case XAPIC_OFF_ESR:
4329 case XAPIC_OFF_ICR_LO:
4330 case XAPIC_OFF_ICR_HI:
4331 case XAPIC_OFF_LVT_TIMER:
4332 case XAPIC_OFF_LVT_THERMAL:
4333 case XAPIC_OFF_LVT_PERF:
4334 case XAPIC_OFF_LVT_LINT0:
4335 case XAPIC_OFF_LVT_LINT1:
4336 case XAPIC_OFF_LVT_ERROR:
4337 case XAPIC_OFF_TIMER_ICR:
4338 case XAPIC_OFF_TIMER_DCR:
4339 break;
4340 default:
4341 return true;
4342 }
4343 }
4344 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4345 {
4346 /*
4347 * With virtual-interrupt delivery, a write access to any of the
4348 * following registers are virtualized. Accessing any other register
4349 * causes a VM-exit.
4350 *
4351 * Note! The specification does not allow writing to offsets in-between
4352 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4353 */
4354 switch (offAccess)
4355 {
4356 case XAPIC_OFF_TPR:
4357 case XAPIC_OFF_EOI:
4358 case XAPIC_OFF_ICR_LO:
4359 break;
4360 default:
4361 return true;
4362 }
4363 }
4364 else
4365 {
4366 /*
4367 * Without APIC-register virtualization or virtual-interrupt delivery,
4368 * only TPR accesses are virtualized.
4369 */
4370 if (offAccess == XAPIC_OFF_TPR)
4371 { /* likely */ }
4372 else
4373 return true;
4374 }
4375 }
4376 else
4377 {
4378 /*
4379 * Check read accesses to the APIC-access page that cause VM-exits.
4380 */
4381 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4382 {
4383 /*
4384 * With APIC-register virtualization, a read access to any of the
4385 * following registers are virtualized. Accessing any other register
4386 * causes a VM-exit.
4387 */
4388 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4389 switch (offAlignedAccess)
4390 {
4391 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4392 case XAPIC_OFF_ID:
4393 case XAPIC_OFF_VERSION:
4394 case XAPIC_OFF_TPR:
4395 case XAPIC_OFF_EOI:
4396 case XAPIC_OFF_LDR:
4397 case XAPIC_OFF_DFR:
4398 case XAPIC_OFF_SVR:
4399 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4400 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4401 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4402 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4403 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4404 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4405 case XAPIC_OFF_ESR:
4406 case XAPIC_OFF_ICR_LO:
4407 case XAPIC_OFF_ICR_HI:
4408 case XAPIC_OFF_LVT_TIMER:
4409 case XAPIC_OFF_LVT_THERMAL:
4410 case XAPIC_OFF_LVT_PERF:
4411 case XAPIC_OFF_LVT_LINT0:
4412 case XAPIC_OFF_LVT_LINT1:
4413 case XAPIC_OFF_LVT_ERROR:
4414 case XAPIC_OFF_TIMER_ICR:
4415 case XAPIC_OFF_TIMER_DCR:
4416 break;
4417 default:
4418 return true;
4419 }
4420 }
4421 else
4422 {
4423 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4424 if (offAccess == XAPIC_OFF_TPR)
4425 { /* likely */ }
4426 else
4427 return true;
4428 }
4429 }
4430
4431 /* The APIC-access is virtualized, does not cause a VM-exit. */
4432 return false;
4433}
4434
4435
4436/**
4437 * Virtualizes a memory-based APIC-access where the address is not used to access
4438 * memory.
4439 *
4440 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4441 * page-faults but do not use the address to access memory.
4442 *
4443 * @param pVCpu The cross context virtual CPU structure.
4444 * @param pGCPhysAccess Pointer to the guest-physical address used.
4445 */
4446IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4447{
4448 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4449 Assert(pVmcs);
4450 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4451 Assert(pGCPhysAccess);
4452
4453 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4454 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4455 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4456
4457 if (GCPhysAccess == GCPhysApic)
4458 {
4459 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4460 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4461 uint16_t const cbAccess = 1;
4462 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4463 if (fIntercept)
4464 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4465
4466 *pGCPhysAccess = GCPhysApic | offAccess;
4467 return VINF_VMX_MODIFIES_BEHAVIOR;
4468 }
4469
4470 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4471}
4472
4473
4474/**
4475 * Virtualizes a memory-based APIC-access.
4476 *
4477 * @returns VBox strict status code.
4478 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4479 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4480 *
4481 * @param pVCpu The cross context virtual CPU structure.
4482 * @param offAccess The offset of the register being accessed (within the
4483 * APIC-access page).
4484 * @param cbAccess The size of the access in bytes.
4485 * @param pvData Pointer to the data being written or where to store the data
4486 * being read.
4487 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4488 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4489 */
4490IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4491 uint32_t fAccess)
4492{
4493 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4494 Assert(pVmcs);
4495 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4496 Assert(pvData);
4497 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4498 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4499 || (fAccess & IEM_ACCESS_INSTRUCTION));
4500
4501 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4502 if (fIntercept)
4503 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4504
4505 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4506 {
4507 /*
4508 * A write access to the APIC-access page that is virtualized (rather than
4509 * causing a VM-exit) writes data to the virtual-APIC page.
4510 */
4511 uint32_t const u32Data = *(uint32_t *)pvData;
4512 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4513
4514 /*
4515 * Record the currently updated APIC offset, as we need this later for figuring
4516 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4517 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4518 *
4519 * After completion of the current operation, we need to perform TPR virtualization,
4520 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4521 *
4522 * The current operation may be a REP-prefixed string instruction, execution of any
4523 * other instruction, or delivery of an event through the IDT.
4524 *
4525 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4526 * performed now but later after completion of the current operation.
4527 *
4528 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4529 */
4530 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4531 }
4532 else
4533 {
4534 /*
4535 * A read access from the APIC-access page that is virtualized (rather than
4536 * causing a VM-exit) returns data from the virtual-APIC page.
4537 *
4538 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4539 */
4540 Assert(cbAccess <= 4);
4541 Assert(offAccess < XAPIC_OFF_END + 4);
4542 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4543
4544 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4545 u32Data &= s_auAccessSizeMasks[cbAccess];
4546 *(uint32_t *)pvData = u32Data;
4547 }
4548
4549 return VINF_VMX_MODIFIES_BEHAVIOR;
4550}
4551
4552
4553/**
4554 * Virtualizes an MSR-based APIC read access.
4555 *
4556 * @returns VBox strict status code.
4557 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4558 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4559 * handled by the x2APIC device.
4560 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4561 * not within the range of valid MSRs, caller must raise \#GP(0).
4562 * @param pVCpu The cross context virtual CPU structure.
4563 * @param idMsr The x2APIC MSR being read.
4564 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4565 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4566 */
4567IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4568{
4569 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4570 Assert(pVmcs);
4571 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4572 Assert(pu64Value);
4573
4574 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4575 {
4576 /*
4577 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4578 * what the end of the valid x2APIC MSR range is. Hence the use of different
4579 * macros here.
4580 *
4581 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4582 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4583 */
4584 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4585 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4586 {
4587 uint16_t const offReg = (idMsr & 0xff) << 4;
4588 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4589 *pu64Value = u64Value;
4590 return VINF_VMX_MODIFIES_BEHAVIOR;
4591 }
4592 return VERR_OUT_OF_RANGE;
4593 }
4594
4595 if (idMsr == MSR_IA32_X2APIC_TPR)
4596 {
4597 uint16_t const offReg = (idMsr & 0xff) << 4;
4598 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4599 *pu64Value = u64Value;
4600 return VINF_VMX_MODIFIES_BEHAVIOR;
4601 }
4602
4603 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4604}
4605
4606
4607/**
4608 * Virtualizes an MSR-based APIC write access.
4609 *
4610 * @returns VBox strict status code.
4611 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4612 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4613 * not within the range of valid MSRs, caller must raise \#GP(0).
4614 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4615 *
4616 * @param pVCpu The cross context virtual CPU structure.
4617 * @param idMsr The x2APIC MSR being written.
4618 * @param u64Value The value of the x2APIC MSR being written.
4619 */
4620IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4621{
4622 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4623 Assert(pVmcs);
4624
4625 /*
4626 * Check if the access is to be virtualized.
4627 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4628 */
4629 if ( idMsr == MSR_IA32_X2APIC_TPR
4630 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4631 && ( idMsr == MSR_IA32_X2APIC_EOI
4632 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4633 {
4634 /* Validate the MSR write depending on the register. */
4635 switch (idMsr)
4636 {
4637 case MSR_IA32_X2APIC_TPR:
4638 case MSR_IA32_X2APIC_SELF_IPI:
4639 {
4640 if (u64Value & UINT64_C(0xffffffffffffff00))
4641 return VERR_OUT_OF_RANGE;
4642 break;
4643 }
4644 case MSR_IA32_X2APIC_EOI:
4645 {
4646 if (u64Value != 0)
4647 return VERR_OUT_OF_RANGE;
4648 break;
4649 }
4650 }
4651
4652 /* Write the MSR to the virtual-APIC page. */
4653 uint16_t const offReg = (idMsr & 0xff) << 4;
4654 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4655
4656 /*
4657 * Record the currently updated APIC offset, as we need this later for figuring
4658 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4659 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4660 */
4661 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4662
4663 return VINF_VMX_MODIFIES_BEHAVIOR;
4664 }
4665
4666 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4667}
4668
4669
4670/**
4671 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4672 *
4673 * @returns VBox status code.
4674 * @retval VINF_SUCCES when the highest set bit is found.
4675 * @retval VERR_NOT_FOUND when no bit is set.
4676 *
4677 * @param pVCpu The cross context virtual CPU structure.
4678 * @param offReg The offset of the APIC 256-bit sparse register.
4679 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4680 * set in the register. Only valid when VINF_SUCCESS is
4681 * returned.
4682 *
4683 * @remarks The format of the 256-bit sparse register here mirrors that found in
4684 * real APIC hardware.
4685 */
4686static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4687{
4688 Assert(offReg < XAPIC_OFF_END + 4);
4689 Assert(pidxHighestBit);
4690
4691 /*
4692 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4693 * However, in each fragment only the first 4 bytes are used.
4694 */
4695 uint8_t const cFrags = 8;
4696 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4697 {
4698 uint16_t const offFrag = iFrag * 16;
4699 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4700 if (!u32Frag)
4701 continue;
4702
4703 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4704 Assert(idxHighestBit > 0);
4705 --idxHighestBit;
4706 Assert(idxHighestBit <= UINT8_MAX);
4707 *pidxHighestBit = idxHighestBit;
4708 return VINF_SUCCESS;
4709 }
4710 return VERR_NOT_FOUND;
4711}
4712
4713
4714/**
4715 * Evaluates pending virtual interrupts.
4716 *
4717 * @param pVCpu The cross context virtual CPU structure.
4718 */
4719IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4720{
4721 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4722 Assert(pVmcs);
4723 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4724
4725 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4726 {
4727 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4728 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4729
4730 if ((uRvi >> 4) > (uPpr >> 4))
4731 {
4732 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4733 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4734 }
4735 else
4736 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4737 }
4738}
4739
4740
4741/**
4742 * Performs PPR virtualization.
4743 *
4744 * @returns VBox strict status code.
4745 * @param pVCpu The cross context virtual CPU structure.
4746 */
4747IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4748{
4749 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4750 Assert(pVmcs);
4751 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4752 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4753
4754 /*
4755 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4756 * or EOI-virtualization.
4757 *
4758 * See Intel spec. 29.1.3 "PPR Virtualization".
4759 */
4760 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4761 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4762
4763 uint32_t uPpr;
4764 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4765 uPpr = uTpr & 0xff;
4766 else
4767 uPpr = uSvi & 0xf0;
4768
4769 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4770 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4771}
4772
4773
4774/**
4775 * Performs VMX TPR virtualization.
4776 *
4777 * @returns VBox strict status code.
4778 * @param pVCpu The cross context virtual CPU structure.
4779 */
4780IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4781{
4782 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4783 Assert(pVmcs);
4784 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4785
4786 /*
4787 * We should have already performed the virtual-APIC write to the TPR offset
4788 * in the virtual-APIC page. We now perform TPR virtualization.
4789 *
4790 * See Intel spec. 29.1.2 "TPR Virtualization".
4791 */
4792 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4793 {
4794 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4795 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4796
4797 /*
4798 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4799 * See Intel spec. 29.1.2 "TPR Virtualization".
4800 */
4801 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4802 {
4803 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4804 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4805 }
4806 }
4807 else
4808 {
4809 iemVmxPprVirtualization(pVCpu);
4810 iemVmxEvalPendingVirtIntrs(pVCpu);
4811 }
4812
4813 return VINF_SUCCESS;
4814}
4815
4816
4817/**
4818 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4819 * not.
4820 *
4821 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4822 * @param pVCpu The cross context virtual CPU structure.
4823 * @param uVector The interrupt that was acknowledged using an EOI.
4824 */
4825IEM_STATIC bool iemVmxIsEoiInterceptSet(PVMCPU pVCpu, uint8_t uVector)
4826{
4827 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4828 Assert(pVmcs);
4829 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4830
4831 if (uVector < 64)
4832 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4833 if (uVector < 128)
4834 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4835 if (uVector < 192)
4836 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4837 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4838}
4839
4840
4841/**
4842 * Performs EOI virtualization.
4843 *
4844 * @returns VBox strict status code.
4845 * @param pVCpu The cross context virtual CPU structure.
4846 */
4847IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4848{
4849 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4850 Assert(pVmcs);
4851 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4852
4853 /*
4854 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4855 * and get the next guest-interrupt that's in-service (if any).
4856 *
4857 * See Intel spec. 29.1.4 "EOI Virtualization".
4858 */
4859 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4860 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4861 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4862
4863 uint8_t uVector = uSvi;
4864 iemVmxVirtApicClearVector(pVCpu, XAPIC_OFF_ISR0, uVector);
4865
4866 uVector = 0;
4867 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4868
4869 if (uVector)
4870 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4871 else
4872 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4873
4874 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4875 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4876
4877 iemVmxPprVirtualization(pVCpu);
4878 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4879 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4880 iemVmxEvalPendingVirtIntrs(pVCpu);
4881 return VINF_SUCCESS;
4882}
4883
4884
4885/**
4886 * Performs self-IPI virtualization.
4887 *
4888 * @returns VBox strict status code.
4889 * @param pVCpu The cross context virtual CPU structure.
4890 */
4891IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4892{
4893 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4894 Assert(pVmcs);
4895 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4896
4897 /*
4898 * We should have already performed the virtual-APIC write to the self-IPI offset
4899 * in the virtual-APIC page. We now perform self-IPI virtualization.
4900 *
4901 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4902 */
4903 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4904 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4905 iemVmxVirtApicSetVector(pVCpu, XAPIC_OFF_IRR0, uVector);
4906 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4907 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4908 if (uVector > uRvi)
4909 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4910 iemVmxEvalPendingVirtIntrs(pVCpu);
4911 return VINF_SUCCESS;
4912}
4913
4914
4915/**
4916 * Performs VMX APIC-write emulation.
4917 *
4918 * @returns VBox strict status code.
4919 * @param pVCpu The cross context virtual CPU structure.
4920 */
4921IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
4922{
4923 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4924 Assert(pVmcs);
4925
4926 /*
4927 * Perform APIC-write emulation based on the virtual-APIC register written.
4928 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4929 */
4930 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4931 VBOXSTRICTRC rcStrict;
4932 switch (offApicWrite)
4933 {
4934 case XAPIC_OFF_TPR:
4935 {
4936 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4937 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4938 uTpr &= UINT32_C(0x000000ff);
4939 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4940 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4941 rcStrict = iemVmxTprVirtualization(pVCpu);
4942 break;
4943 }
4944
4945 case XAPIC_OFF_EOI:
4946 {
4947 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4948 {
4949 /* Clear VEOI and perform EOI virtualization. */
4950 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4951 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4952 rcStrict = iemVmxEoiVirtualization(pVCpu);
4953 }
4954 else
4955 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4956 break;
4957 }
4958
4959 case XAPIC_OFF_ICR_LO:
4960 {
4961 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4962 {
4963 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4964 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4965 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4966 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4967 if ( !(uIcrLo & fIcrLoMb0)
4968 && (uIcrLo & fIcrLoMb1))
4969 {
4970 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4971 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4972 }
4973 else
4974 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4975 }
4976 else
4977 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4978 break;
4979 }
4980
4981 case XAPIC_OFF_ICR_HI:
4982 {
4983 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4984 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4985 uIcrHi &= UINT32_C(0xff000000);
4986 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4987 rcStrict = VINF_SUCCESS;
4988 break;
4989 }
4990
4991 default:
4992 {
4993 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4994 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4995 break;
4996 }
4997 }
4998
4999 return rcStrict;
5000}
5001
5002
5003/**
5004 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5005 *
5006 * @param pVCpu The cross context virtual CPU structure.
5007 * @param pszInstr The VMX instruction name (for logging purposes).
5008 */
5009IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5010{
5011 /*
5012 * Guest Control Registers, Debug Registers, and MSRs.
5013 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5014 */
5015 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5016 const char *const pszFailure = "VM-exit";
5017 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5018
5019 /* CR0 reserved bits. */
5020 {
5021 /* CR0 MB1 bits. */
5022 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5023 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5024 if (fUnrestrictedGuest)
5025 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5026 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
5027 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5028
5029 /* CR0 MBZ bits. */
5030 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5031 if (pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1)
5032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5033
5034 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5035 if ( !fUnrestrictedGuest
5036 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5037 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5038 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5039 }
5040
5041 /* CR4 reserved bits. */
5042 {
5043 /* CR4 MB1 bits. */
5044 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5045 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
5046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5047
5048 /* CR4 MBZ bits. */
5049 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5050 if (pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1)
5051 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5052 }
5053
5054 /* DEBUGCTL MSR. */
5055 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5056 && (pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5057 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5058
5059 /* 64-bit CPU checks. */
5060 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5061 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5062 {
5063 if (fGstInLongMode)
5064 {
5065 /* PAE must be set. */
5066 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5067 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5068 { /* likely */ }
5069 else
5070 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5071 }
5072 else
5073 {
5074 /* PCIDE should not be set. */
5075 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5076 { /* likely */ }
5077 else
5078 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5079 }
5080
5081 /* CR3. */
5082 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5083 { /* likely */ }
5084 else
5085 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5086
5087 /* DR7. */
5088 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5089 && (pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5090 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5091
5092 /* SYSENTER ESP and SYSENTER EIP. */
5093 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5094 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5095 { /* likely */ }
5096 else
5097 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5098 }
5099
5100 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5101 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5102
5103 /* PAT MSR. */
5104 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5105 && !CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5106 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5107
5108 /* EFER MSR. */
5109 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5110 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5111 && (pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5112 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5113
5114 bool const fGstLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
5115 bool const fGstLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
5116 if ( fGstInLongMode == fGstLma
5117 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5118 || fGstLma == fGstLme))
5119 { /* likely */ }
5120 else
5121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5122
5123 /* We don't support IA32_BNDCFGS MSR yet. */
5124 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5125
5126 NOREF(pszInstr);
5127 NOREF(pszFailure);
5128 return VINF_SUCCESS;
5129}
5130
5131
5132/**
5133 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5134 *
5135 * @param pVCpu The cross context virtual CPU structure.
5136 * @param pszInstr The VMX instruction name (for logging purposes).
5137 */
5138IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5139{
5140 /*
5141 * Segment registers.
5142 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5143 */
5144 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5145 const char *const pszFailure = "VM-exit";
5146 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5147 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5148 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5149
5150 /* Selectors. */
5151 if ( !fGstInV86Mode
5152 && !fUnrestrictedGuest
5153 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5154 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5155
5156 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5157 {
5158 CPUMSELREG SelReg;
5159 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5160 if (RT_LIKELY(rc == VINF_SUCCESS))
5161 { /* likely */ }
5162 else
5163 return rc;
5164
5165 /*
5166 * Virtual-8086 mode checks.
5167 */
5168 if (fGstInV86Mode)
5169 {
5170 /* Base address. */
5171 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5172 { /* likely */ }
5173 else
5174 {
5175 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5177 }
5178
5179 /* Limit. */
5180 if (SelReg.u32Limit == 0xffff)
5181 { /* likely */ }
5182 else
5183 {
5184 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5186 }
5187
5188 /* Attribute. */
5189 if (SelReg.Attr.u == 0xf3)
5190 { /* likely */ }
5191 else
5192 {
5193 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5195 }
5196
5197 /* We're done; move to checking the next segment. */
5198 continue;
5199 }
5200
5201 /* Checks done by 64-bit CPUs. */
5202 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5203 {
5204 /* Base address. */
5205 if ( iSegReg == X86_SREG_FS
5206 || iSegReg == X86_SREG_GS)
5207 {
5208 if (X86_IS_CANONICAL(SelReg.u64Base))
5209 { /* likely */ }
5210 else
5211 {
5212 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5213 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5214 }
5215 }
5216 else if (iSegReg == X86_SREG_CS)
5217 {
5218 if (!RT_HI_U32(SelReg.u64Base))
5219 { /* likely */ }
5220 else
5221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5222 }
5223 else
5224 {
5225 if ( SelReg.Attr.n.u1Unusable
5226 || !RT_HI_U32(SelReg.u64Base))
5227 { /* likely */ }
5228 else
5229 {
5230 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5232 }
5233 }
5234 }
5235
5236 /*
5237 * Checks outside Virtual-8086 mode.
5238 */
5239 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5240 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5241 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5242 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5243 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5244 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5245 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5246 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5247
5248 /* Code or usable segment. */
5249 if ( iSegReg == X86_SREG_CS
5250 || fUsable)
5251 {
5252 /* Reserved bits (bits 31:17 and bits 11:8). */
5253 if (!(SelReg.Attr.u & 0xfffe0f00))
5254 { /* likely */ }
5255 else
5256 {
5257 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5259 }
5260
5261 /* Descriptor type. */
5262 if (fCodeDataSeg)
5263 { /* likely */ }
5264 else
5265 {
5266 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5268 }
5269
5270 /* Present. */
5271 if (fPresent)
5272 { /* likely */ }
5273 else
5274 {
5275 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5276 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5277 }
5278
5279 /* Granularity. */
5280 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5281 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5282 { /* likely */ }
5283 else
5284 {
5285 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5287 }
5288 }
5289
5290 if (iSegReg == X86_SREG_CS)
5291 {
5292 /* Segment Type and DPL. */
5293 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5294 && fUnrestrictedGuest)
5295 {
5296 if (uDpl == 0)
5297 { /* likely */ }
5298 else
5299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5300 }
5301 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5302 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5303 {
5304 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5305 if (uDpl == AttrSs.n.u2Dpl)
5306 { /* likely */ }
5307 else
5308 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5309 }
5310 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5311 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5312 {
5313 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5314 if (uDpl <= AttrSs.n.u2Dpl)
5315 { /* likely */ }
5316 else
5317 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5318 }
5319 else
5320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5321
5322 /* Def/Big. */
5323 if ( fGstInLongMode
5324 && fSegLong)
5325 {
5326 if (uDefBig == 0)
5327 { /* likely */ }
5328 else
5329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5330 }
5331 }
5332 else if (iSegReg == X86_SREG_SS)
5333 {
5334 /* Segment Type. */
5335 if ( !fUsable
5336 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5337 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5338 { /* likely */ }
5339 else
5340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5341
5342 /* DPL. */
5343 if (fUnrestrictedGuest)
5344 {
5345 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5346 { /* likely */ }
5347 else
5348 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5349 }
5350 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5351 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5352 || (pVmcs->u64GuestCr0.u & X86_CR0_PE))
5353 {
5354 if (uDpl == 0)
5355 { /* likely */ }
5356 else
5357 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5358 }
5359 }
5360 else
5361 {
5362 /* DS, ES, FS, GS. */
5363 if (fUsable)
5364 {
5365 /* Segment type. */
5366 if (uSegType & X86_SEL_TYPE_ACCESSED)
5367 { /* likely */ }
5368 else
5369 {
5370 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5372 }
5373
5374 if ( !(uSegType & X86_SEL_TYPE_CODE)
5375 || (uSegType & X86_SEL_TYPE_READ))
5376 { /* likely */ }
5377 else
5378 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5379
5380 /* DPL. */
5381 if ( !fUnrestrictedGuest
5382 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5383 {
5384 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5385 { /* likely */ }
5386 else
5387 {
5388 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5389 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5390 }
5391 }
5392 }
5393 }
5394 }
5395
5396 /*
5397 * LDTR.
5398 */
5399 {
5400 CPUMSELREG Ldtr;
5401 Ldtr.Sel = pVmcs->GuestLdtr;
5402 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5403 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5404 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5405
5406 if (!Ldtr.Attr.n.u1Unusable)
5407 {
5408 /* Selector. */
5409 if (!(Ldtr.Sel & X86_SEL_LDT))
5410 { /* likely */ }
5411 else
5412 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5413
5414 /* Base. */
5415 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5416 {
5417 if (X86_IS_CANONICAL(Ldtr.u64Base))
5418 { /* likely */ }
5419 else
5420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5421 }
5422
5423 /* Attributes. */
5424 /* Reserved bits (bits 31:17 and bits 11:8). */
5425 if (!(Ldtr.Attr.u & 0xfffe0f00))
5426 { /* likely */ }
5427 else
5428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5429
5430 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5431 { /* likely */ }
5432 else
5433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5434
5435 if (!Ldtr.Attr.n.u1DescType)
5436 { /* likely */ }
5437 else
5438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5439
5440 if (Ldtr.Attr.n.u1Present)
5441 { /* likely */ }
5442 else
5443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5444
5445 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5446 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5447 { /* likely */ }
5448 else
5449 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5450 }
5451 }
5452
5453 /*
5454 * TR.
5455 */
5456 {
5457 CPUMSELREG Tr;
5458 Tr.Sel = pVmcs->GuestTr;
5459 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5460 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5461 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5462
5463 /* Selector. */
5464 if (!(Tr.Sel & X86_SEL_LDT))
5465 { /* likely */ }
5466 else
5467 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5468
5469 /* Base. */
5470 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5471 {
5472 if (X86_IS_CANONICAL(Tr.u64Base))
5473 { /* likely */ }
5474 else
5475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5476 }
5477
5478 /* Attributes. */
5479 /* Reserved bits (bits 31:17 and bits 11:8). */
5480 if (!(Tr.Attr.u & 0xfffe0f00))
5481 { /* likely */ }
5482 else
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5484
5485 if (!Tr.Attr.n.u1Unusable)
5486 { /* likely */ }
5487 else
5488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5489
5490 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5491 || ( !fGstInLongMode
5492 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5493 { /* likely */ }
5494 else
5495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5496
5497 if (!Tr.Attr.n.u1DescType)
5498 { /* likely */ }
5499 else
5500 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5501
5502 if (Tr.Attr.n.u1Present)
5503 { /* likely */ }
5504 else
5505 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5506
5507 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5508 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5509 { /* likely */ }
5510 else
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5512 }
5513
5514 NOREF(pszInstr);
5515 NOREF(pszFailure);
5516 return VINF_SUCCESS;
5517}
5518
5519
5520/**
5521 * Checks guest GDTR and IDTR as part of VM-entry.
5522 *
5523 * @param pVCpu The cross context virtual CPU structure.
5524 * @param pszInstr The VMX instruction name (for logging purposes).
5525 */
5526IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5527{
5528 /*
5529 * GDTR and IDTR.
5530 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5531 */
5532 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5533 const char *const pszFailure = "VM-exit";
5534
5535 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5536 {
5537 /* Base. */
5538 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5539 { /* likely */ }
5540 else
5541 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5542
5543 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5544 { /* likely */ }
5545 else
5546 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5547 }
5548
5549 /* Limit. */
5550 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5551 { /* likely */ }
5552 else
5553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5554
5555 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5556 { /* likely */ }
5557 else
5558 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5559
5560 NOREF(pszInstr);
5561 NOREF(pszFailure);
5562 return VINF_SUCCESS;
5563}
5564
5565
5566/**
5567 * Checks guest RIP and RFLAGS as part of VM-entry.
5568 *
5569 * @param pVCpu The cross context virtual CPU structure.
5570 * @param pszInstr The VMX instruction name (for logging purposes).
5571 */
5572IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5573{
5574 /*
5575 * RIP and RFLAGS.
5576 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5577 */
5578 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5579 const char *const pszFailure = "VM-exit";
5580 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5581
5582 /* RIP. */
5583 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5584 {
5585 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5586 if ( !fGstInLongMode
5587 || !AttrCs.n.u1Long)
5588 {
5589 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5590 { /* likely */ }
5591 else
5592 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5593 }
5594
5595 if ( fGstInLongMode
5596 && AttrCs.n.u1Long)
5597 {
5598 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5599 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5600 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5601 { /* likely */ }
5602 else
5603 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5604 }
5605 }
5606
5607 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5608 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5609 : pVmcs->u64GuestRFlags.s.Lo;
5610 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5611 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5612 { /* likely */ }
5613 else
5614 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5615
5616 if ( fGstInLongMode
5617 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5618 {
5619 if (!(uGuestRFlags & X86_EFL_VM))
5620 { /* likely */ }
5621 else
5622 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5623 }
5624
5625 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5626 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5627 {
5628 if (uGuestRFlags & X86_EFL_IF)
5629 { /* likely */ }
5630 else
5631 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5632 }
5633
5634 NOREF(pszInstr);
5635 NOREF(pszFailure);
5636 return VINF_SUCCESS;
5637}
5638
5639
5640/**
5641 * Checks guest non-register state as part of VM-entry.
5642 *
5643 * @param pVCpu The cross context virtual CPU structure.
5644 * @param pszInstr The VMX instruction name (for logging purposes).
5645 */
5646IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5647{
5648 /*
5649 * Guest non-register state.
5650 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5651 */
5652 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5653 const char *const pszFailure = "VM-exit";
5654
5655 /*
5656 * Activity state.
5657 */
5658 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5659 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5660 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5661 { /* likely */ }
5662 else
5663 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5664
5665 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5666 if ( !AttrSs.n.u2Dpl
5667 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5668 { /* likely */ }
5669 else
5670 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5671
5672 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5673 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5674 {
5675 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5676 { /* likely */ }
5677 else
5678 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5679 }
5680
5681 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5682 {
5683 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5684 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5685 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5686 switch (pVmcs->u32GuestActivityState)
5687 {
5688 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5689 {
5690 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5691 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5692 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5693 && ( uVector == X86_XCPT_DB
5694 || uVector == X86_XCPT_MC))
5695 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5696 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5697 { /* likely */ }
5698 else
5699 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5700 break;
5701 }
5702
5703 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5704 {
5705 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5706 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5707 && uVector == X86_XCPT_MC))
5708 { /* likely */ }
5709 else
5710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5711 break;
5712 }
5713
5714 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5715 default:
5716 break;
5717 }
5718 }
5719
5720 /*
5721 * Interruptibility state.
5722 */
5723 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5724 { /* likely */ }
5725 else
5726 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5727
5728 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5729 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5730 { /* likely */ }
5731 else
5732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5733
5734 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5735 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5736 { /* likely */ }
5737 else
5738 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5739
5740 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5741 {
5742 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5743 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5744 {
5745 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5746 { /* likely */ }
5747 else
5748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5749 }
5750 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5751 {
5752 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5753 { /* likely */ }
5754 else
5755 {
5756 /*
5757 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5758 * We update the VM-exit qualification only when blocking-by-STI is set
5759 * without blocking-by-MovSS being set. Although in practise it does not
5760 * make much difference since the order of checks are implementation defined.
5761 */
5762 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5763 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5764 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5765 }
5766
5767 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5768 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5769 { /* likely */ }
5770 else
5771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5772 }
5773 }
5774
5775 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5776 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5777 { /* likely */ }
5778 else
5779 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5780
5781 /* We don't support SGX yet. So enclave-interruption must not be set. */
5782 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5783 { /* likely */ }
5784 else
5785 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5786
5787 /*
5788 * Pending debug exceptions.
5789 */
5790 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5791 ? pVmcs->u64GuestPendingDbgXcpt.u
5792 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5793 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5794 { /* likely */ }
5795 else
5796 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5797
5798 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5799 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5800 {
5801 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5802 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5803 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5805
5806 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5807 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5808 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5809 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5810 }
5811
5812 /* We don't support RTM (Real-time Transactional Memory) yet. */
5813 if (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
5814 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5815
5816 /*
5817 * VMCS link pointer.
5818 */
5819 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5820 {
5821 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5822 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5823 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5824 { /* likely */ }
5825 else
5826 {
5827 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5828 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5829 }
5830
5831 /* Validate the address. */
5832 if ( (GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5833 || (GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5834 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5835 {
5836 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5838 }
5839
5840 /* Read the VMCS-link pointer from guest memory. */
5841 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5842 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5843 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5844 if (RT_FAILURE(rc))
5845 {
5846 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5847 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5848 }
5849
5850 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5851 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5852 { /* likely */ }
5853 else
5854 {
5855 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5857 }
5858
5859 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5860 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5861 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5862 { /* likely */ }
5863 else
5864 {
5865 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5867 }
5868
5869 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5870 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5871 }
5872
5873 NOREF(pszInstr);
5874 NOREF(pszFailure);
5875 return VINF_SUCCESS;
5876}
5877
5878
5879/**
5880 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5881 * VM-entry.
5882 *
5883 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5884 * @param pVCpu The cross context virtual CPU structure.
5885 * @param pszInstr The VMX instruction name (for logging purposes).
5886 * @param pVmcs Pointer to the virtual VMCS.
5887 */
5888IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5889{
5890 /*
5891 * Check PDPTEs.
5892 * See Intel spec. 4.4.1 "PDPTE Registers".
5893 */
5894 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5895 const char *const pszFailure = "VM-exit";
5896
5897 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5898 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5899 if (RT_SUCCESS(rc))
5900 {
5901 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5902 {
5903 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5904 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5905 { /* likely */ }
5906 else
5907 {
5908 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5909 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5910 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5911 }
5912 }
5913 }
5914 else
5915 {
5916 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5917 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5918 }
5919
5920 NOREF(pszFailure);
5921 NOREF(pszInstr);
5922 return rc;
5923}
5924
5925
5926/**
5927 * Checks guest PDPTEs as part of VM-entry.
5928 *
5929 * @param pVCpu The cross context virtual CPU structure.
5930 * @param pszInstr The VMX instruction name (for logging purposes).
5931 */
5932IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
5933{
5934 /*
5935 * Guest PDPTEs.
5936 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5937 */
5938 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5939 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5940
5941 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5942 int rc;
5943 if ( !fGstInLongMode
5944 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5945 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5946 {
5947 /*
5948 * We don't support nested-paging for nested-guests yet.
5949 *
5950 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5951 * rather we need to check the PDPTEs referenced by the guest CR3.
5952 */
5953 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5954 }
5955 else
5956 rc = VINF_SUCCESS;
5957 return rc;
5958}
5959
5960
5961/**
5962 * Checks guest-state as part of VM-entry.
5963 *
5964 * @returns VBox status code.
5965 * @param pVCpu The cross context virtual CPU structure.
5966 * @param pszInstr The VMX instruction name (for logging purposes).
5967 */
5968IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
5969{
5970 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5971 if (RT_SUCCESS(rc))
5972 {
5973 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5974 if (RT_SUCCESS(rc))
5975 {
5976 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5977 if (RT_SUCCESS(rc))
5978 {
5979 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5980 if (RT_SUCCESS(rc))
5981 {
5982 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5983 if (RT_SUCCESS(rc))
5984 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5985 }
5986 }
5987 }
5988 }
5989 return rc;
5990}
5991
5992
5993/**
5994 * Checks host-state as part of VM-entry.
5995 *
5996 * @returns VBox status code.
5997 * @param pVCpu The cross context virtual CPU structure.
5998 * @param pszInstr The VMX instruction name (for logging purposes).
5999 */
6000IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6001{
6002 /*
6003 * Host Control Registers and MSRs.
6004 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6005 */
6006 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6007 const char * const pszFailure = "VMFail";
6008
6009 /* CR0 reserved bits. */
6010 {
6011 /* CR0 MB1 bits. */
6012 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6013 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
6014 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6015
6016 /* CR0 MBZ bits. */
6017 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6018 if (pVmcs->u64HostCr0.u & ~u64Cr0Fixed1)
6019 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6020 }
6021
6022 /* CR4 reserved bits. */
6023 {
6024 /* CR4 MB1 bits. */
6025 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6026 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
6027 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6028
6029 /* CR4 MBZ bits. */
6030 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6031 if (pVmcs->u64HostCr4.u & ~u64Cr4Fixed1)
6032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6033 }
6034
6035 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6036 {
6037 /* CR3 reserved bits. */
6038 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6039 { /* likely */ }
6040 else
6041 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6042
6043 /* SYSENTER ESP and SYSENTER EIP. */
6044 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6045 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6046 { /* likely */ }
6047 else
6048 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6049 }
6050
6051 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6052 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6053
6054 /* PAT MSR. */
6055 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6056 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6057 { /* likely */ }
6058 else
6059 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6060
6061 /* EFER MSR. */
6062 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6063 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6064 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6065 { /* likely */ }
6066 else
6067 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6068
6069 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6070 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6071 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6072 if ( fHostInLongMode == fHostLma
6073 && fHostInLongMode == fHostLme)
6074 { /* likely */ }
6075 else
6076 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6077
6078 /*
6079 * Host Segment and Descriptor-Table Registers.
6080 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6081 */
6082 /* Selector RPL and TI. */
6083 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6084 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6085 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6086 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6087 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6088 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6089 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6090 { /* likely */ }
6091 else
6092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6093
6094 /* CS and TR selectors cannot be 0. */
6095 if ( pVmcs->HostCs
6096 && pVmcs->HostTr)
6097 { /* likely */ }
6098 else
6099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6100
6101 /* SS cannot be 0 if 32-bit host. */
6102 if ( fHostInLongMode
6103 || pVmcs->HostSs)
6104 { /* likely */ }
6105 else
6106 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6107
6108 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6109 {
6110 /* FS, GS, GDTR, IDTR, TR base address. */
6111 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6112 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6113 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6114 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6115 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6116 { /* likely */ }
6117 else
6118 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6119 }
6120
6121 /*
6122 * Host address-space size for 64-bit CPUs.
6123 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6124 */
6125 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6126 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6127 {
6128 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6129
6130 /* Logical processor in IA-32e mode. */
6131 if (fCpuInLongMode)
6132 {
6133 if (fHostInLongMode)
6134 {
6135 /* PAE must be set. */
6136 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6137 { /* likely */ }
6138 else
6139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6140
6141 /* RIP must be canonical. */
6142 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6143 { /* likely */ }
6144 else
6145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6146 }
6147 else
6148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6149 }
6150 else
6151 {
6152 /* Logical processor is outside IA-32e mode. */
6153 if ( !fGstInLongMode
6154 && !fHostInLongMode)
6155 {
6156 /* PCIDE should not be set. */
6157 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6158 { /* likely */ }
6159 else
6160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6161
6162 /* The high 32-bits of RIP MBZ. */
6163 if (!pVmcs->u64HostRip.s.Hi)
6164 { /* likely */ }
6165 else
6166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6167 }
6168 else
6169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6170 }
6171 }
6172 else
6173 {
6174 /* Host address-space size for 32-bit CPUs. */
6175 if ( !fGstInLongMode
6176 && !fHostInLongMode)
6177 { /* likely */ }
6178 else
6179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6180 }
6181
6182 NOREF(pszInstr);
6183 NOREF(pszFailure);
6184 return VINF_SUCCESS;
6185}
6186
6187
6188/**
6189 * Checks VM-entry controls fields as part of VM-entry.
6190 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6191 *
6192 * @returns VBox status code.
6193 * @param pVCpu The cross context virtual CPU structure.
6194 * @param pszInstr The VMX instruction name (for logging purposes).
6195 */
6196IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6197{
6198 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6199 const char * const pszFailure = "VMFail";
6200
6201 /* VM-entry controls. */
6202 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6203 if (~pVmcs->u32EntryCtls & EntryCtls.n.allowed0)
6204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6205
6206 if (pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1)
6207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6208
6209 /* Event injection. */
6210 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6211 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6212 {
6213 /* Type and vector. */
6214 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6215 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6216 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6217 if ( !uRsvd
6218 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6219 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6220 { /* likely */ }
6221 else
6222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6223
6224 /* Exception error code. */
6225 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6226 {
6227 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6228 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6229 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6230 { /* likely */ }
6231 else
6232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6233
6234 /* Exceptions that provide an error code. */
6235 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6236 && ( uVector == X86_XCPT_DF
6237 || uVector == X86_XCPT_TS
6238 || uVector == X86_XCPT_NP
6239 || uVector == X86_XCPT_SS
6240 || uVector == X86_XCPT_GP
6241 || uVector == X86_XCPT_PF
6242 || uVector == X86_XCPT_AC))
6243 { /* likely */ }
6244 else
6245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6246
6247 /* Exception error-code reserved bits. */
6248 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6249 { /* likely */ }
6250 else
6251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6252
6253 /* Injecting a software interrupt, software exception or privileged software exception. */
6254 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6255 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6256 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6257 {
6258 /* Instruction length must be in the range 0-15. */
6259 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6260 { /* likely */ }
6261 else
6262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6263
6264 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6265 if ( pVmcs->u32EntryInstrLen == 0
6266 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6268 }
6269 }
6270 }
6271
6272 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6273 if (pVmcs->u32EntryMsrLoadCount)
6274 {
6275 if ( (pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6276 || (pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6277 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6279 }
6280
6281 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6282 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6283
6284 NOREF(pszInstr);
6285 NOREF(pszFailure);
6286 return VINF_SUCCESS;
6287}
6288
6289
6290/**
6291 * Checks VM-exit controls fields as part of VM-entry.
6292 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6293 *
6294 * @returns VBox status code.
6295 * @param pVCpu The cross context virtual CPU structure.
6296 * @param pszInstr The VMX instruction name (for logging purposes).
6297 */
6298IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6299{
6300 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6301 const char * const pszFailure = "VMFail";
6302
6303 /* VM-exit controls. */
6304 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6305 if (~pVmcs->u32ExitCtls & ExitCtls.n.allowed0)
6306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6307
6308 if (pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1)
6309 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6310
6311 /* Save preemption timer without activating it. */
6312 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6313 && (pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6315
6316 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6317 if (pVmcs->u32ExitMsrStoreCount)
6318 {
6319 if ( (pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6320 || (pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6321 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6323 }
6324
6325 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6326 if (pVmcs->u32ExitMsrLoadCount)
6327 {
6328 if ( (pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6329 || (pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6330 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6332 }
6333
6334 NOREF(pszInstr);
6335 NOREF(pszFailure);
6336 return VINF_SUCCESS;
6337}
6338
6339
6340/**
6341 * Checks VM-execution controls fields as part of VM-entry.
6342 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6343 *
6344 * @returns VBox status code.
6345 * @param pVCpu The cross context virtual CPU structure.
6346 * @param pszInstr The VMX instruction name (for logging purposes).
6347 *
6348 * @remarks This may update secondary-processor based VM-execution control fields
6349 * in the current VMCS if necessary.
6350 */
6351IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6352{
6353 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6354 const char * const pszFailure = "VMFail";
6355
6356 /* Pin-based VM-execution controls. */
6357 {
6358 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6359 if (~pVmcs->u32PinCtls & PinCtls.n.allowed0)
6360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6361
6362 if (pVmcs->u32PinCtls & ~PinCtls.n.allowed1)
6363 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6364 }
6365
6366 /* Processor-based VM-execution controls. */
6367 {
6368 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6369 if (~pVmcs->u32ProcCtls & ProcCtls.n.allowed0)
6370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6371
6372 if (pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1)
6373 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6374 }
6375
6376 /* Secondary processor-based VM-execution controls. */
6377 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6378 {
6379 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6380 if (~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0)
6381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6382
6383 if (pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1)
6384 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6385 }
6386 else
6387 Assert(!pVmcs->u32ProcCtls2);
6388
6389 /* CR3-target count. */
6390 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6391 { /* likely */ }
6392 else
6393 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6394
6395 /* I/O bitmaps physical addresses. */
6396 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6397 {
6398 if ( (pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6399 || (pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6400 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6401 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6402
6403 if ( (pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6404 || (pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6405 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6407 }
6408
6409 /* MSR bitmap physical address. */
6410 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6411 {
6412 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6413 if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6414 || (GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6415 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6417
6418 /* Read the MSR bitmap. */
6419 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6420 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6421 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6422 if (RT_FAILURE(rc))
6423 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6424 }
6425
6426 /* TPR shadow related controls. */
6427 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6428 {
6429 /* Virtual-APIC page physical address. */
6430 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6431 if ( (GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6432 || (GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6433 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6434 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6435
6436 /* Read the Virtual-APIC page. */
6437 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
6438 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
6439 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
6440 if (RT_FAILURE(rc))
6441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6442
6443 /* TPR threshold without virtual-interrupt delivery. */
6444 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6445 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6447
6448 /* TPR threshold and VTPR. */
6449 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
6450 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
6451 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6452 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6453 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
6454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6455 }
6456 else
6457 {
6458 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6459 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6460 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6461 { /* likely */ }
6462 else
6463 {
6464 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6465 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6466 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6467 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6468 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6469 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6470 }
6471 }
6472
6473 /* NMI exiting and virtual-NMIs. */
6474 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6475 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6477
6478 /* Virtual-NMIs and NMI-window exiting. */
6479 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6480 && (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6481 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6482
6483 /* Virtualize APIC accesses. */
6484 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6485 {
6486 /* APIC-access physical address. */
6487 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6488 if ( (GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6489 || (GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6490 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6491 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6492
6493 /*
6494 * Disallow APIC-access page and virtual-APIC page from being the same address.
6495 * Note! This is not an Intel requirement, but one imposed by our implementation.
6496 */
6497 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6498 * redirecting accesses between the APIC-access page and the virtual-APIC
6499 * page. If any nested hypervisor requires this, we can implement it later. */
6500 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6501 {
6502 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6503 if (GCPhysVirtApic == GCPhysApicAccess)
6504 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6505 }
6506
6507 /*
6508 * Register the handler for the APIC-access page.
6509 *
6510 * We don't deregister the APIC-access page handler during the VM-exit as a different
6511 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6512 *
6513 * We leave the page registered until the first access that happens outside VMX non-root
6514 * mode. Guest software is allowed to access structures such as the APIC-access page
6515 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6516 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6517 *
6518 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6519 */
6520 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6521 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6522 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6523 if (RT_FAILURE(rc))
6524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6525 }
6526
6527 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6528 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6529 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6531
6532 /* Virtual-interrupt delivery requires external interrupt exiting. */
6533 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6534 && !(pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6536
6537 /* VPID. */
6538 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6539 || pVmcs->u16Vpid != 0)
6540 { /* likely */ }
6541 else
6542 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6543
6544 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6545 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6546 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6547 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6548 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6549 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6550 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6551
6552 /* VMCS shadowing. */
6553 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6554 {
6555 /* VMREAD-bitmap physical address. */
6556 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6557 if ( ( GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6558 || ( GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6559 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6560 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6561
6562 /* VMWRITE-bitmap physical address. */
6563 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6564 if ( ( GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6565 || ( GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6566 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6567 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6568
6569 /* Read the VMREAD-bitmap. */
6570 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6571 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6572 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6573 if (RT_FAILURE(rc))
6574 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6575
6576 /* Read the VMWRITE-bitmap. */
6577 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6578 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6579 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6580 if (RT_FAILURE(rc))
6581 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6582 }
6583
6584 NOREF(pszInstr);
6585 NOREF(pszFailure);
6586 return VINF_SUCCESS;
6587}
6588
6589
6590/**
6591 * Loads the guest control registers, debug register and some MSRs as part of
6592 * VM-entry.
6593 *
6594 * @param pVCpu The cross context virtual CPU structure.
6595 */
6596IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6597{
6598 /*
6599 * Load guest control registers, debug registers and MSRs.
6600 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6601 */
6602 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6603 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6604 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6605 CPUMSetGuestCR0(pVCpu, uGstCr0);
6606 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6607 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6608
6609 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6610 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6611
6612 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6613 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6614 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6615
6616 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6617 {
6618 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6619
6620 /* EFER MSR. */
6621 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6622 {
6623 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6624 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6625 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6626 if (fGstInLongMode)
6627 {
6628 /* If the nested-guest is in long mode, LMA and LME are both set. */
6629 Assert(fGstPaging);
6630 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6631 }
6632 else
6633 {
6634 /*
6635 * If the nested-guest is outside long mode:
6636 * - With paging: LMA is cleared, LME is cleared.
6637 * - Without paging: LMA is cleared, LME is left unmodified.
6638 */
6639 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6640 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6641 }
6642 }
6643 /* else: see below. */
6644 }
6645
6646 /* PAT MSR. */
6647 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6648 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6649
6650 /* EFER MSR. */
6651 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6652 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6653
6654 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6655 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6656
6657 /* We don't support IA32_BNDCFGS MSR yet. */
6658 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6659
6660 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6661}
6662
6663
6664/**
6665 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6666 *
6667 * @param pVCpu The cross context virtual CPU structure.
6668 */
6669IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6670{
6671 /*
6672 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6673 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6674 */
6675 /* CS, SS, ES, DS, FS, GS. */
6676 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6677 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6678 {
6679 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6680 CPUMSELREG VmcsSelReg;
6681 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6682 AssertRC(rc); NOREF(rc);
6683 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6684 {
6685 pGstSelReg->Sel = VmcsSelReg.Sel;
6686 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6687 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6688 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6689 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6690 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6691 }
6692 else
6693 {
6694 pGstSelReg->Sel = VmcsSelReg.Sel;
6695 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6696 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6697 switch (iSegReg)
6698 {
6699 case X86_SREG_CS:
6700 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6701 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6702 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6703 break;
6704
6705 case X86_SREG_SS:
6706 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6707 pGstSelReg->u32Limit = 0;
6708 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6709 break;
6710
6711 case X86_SREG_ES:
6712 case X86_SREG_DS:
6713 pGstSelReg->u64Base = 0;
6714 pGstSelReg->u32Limit = 0;
6715 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6716 break;
6717
6718 case X86_SREG_FS:
6719 case X86_SREG_GS:
6720 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6721 pGstSelReg->u32Limit = 0;
6722 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6723 break;
6724 }
6725 Assert(pGstSelReg->Attr.n.u1Unusable);
6726 }
6727 }
6728
6729 /* LDTR. */
6730 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6731 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6732 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6733 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6734 {
6735 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6736 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6737 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6738 }
6739 else
6740 {
6741 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6742 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6743 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6744 }
6745
6746 /* TR. */
6747 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6748 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6749 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6750 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6751 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6752 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6753 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6754
6755 /* GDTR. */
6756 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6757 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6758
6759 /* IDTR. */
6760 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6761 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6762}
6763
6764
6765/**
6766 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
6767 *
6768 * @returns VBox status code.
6769 * @param pVCpu The cross context virtual CPU structure.
6770 * @param pszInstr The VMX instruction name (for logging purposes).
6771 */
6772IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6773{
6774 /*
6775 * Load guest MSRs.
6776 * See Intel spec. 26.4 "Loading MSRs".
6777 */
6778 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6779 const char *const pszFailure = "VM-exit";
6780
6781 /*
6782 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6783 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6784 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6785 */
6786 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6787 if (!cMsrs)
6788 return VINF_SUCCESS;
6789
6790 /*
6791 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6792 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6793 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6794 */
6795 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6796 if (fIsMsrCountValid)
6797 { /* likely */ }
6798 else
6799 {
6800 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6801 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6802 }
6803
6804 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
6805 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
6806 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
6807 if (RT_SUCCESS(rc))
6808 {
6809 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
6810 Assert(pMsr);
6811 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6812 {
6813 if ( !pMsr->u32Reserved
6814 && pMsr->u32Msr != MSR_K8_FS_BASE
6815 && pMsr->u32Msr != MSR_K8_GS_BASE
6816 && pMsr->u32Msr != MSR_K6_EFER
6817 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6818 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6819 {
6820 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6821 if (rcStrict == VINF_SUCCESS)
6822 continue;
6823
6824 /*
6825 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6826 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6827 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
6828 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6829 * MSR in ring-0 if possible, or come up with a better, generic solution.
6830 */
6831 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6832 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6833 ? kVmxVDiag_Vmentry_MsrLoadRing3
6834 : kVmxVDiag_Vmentry_MsrLoad;
6835 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6836 }
6837 else
6838 {
6839 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6841 }
6842 }
6843 }
6844 else
6845 {
6846 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
6847 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6848 }
6849
6850 NOREF(pszInstr);
6851 NOREF(pszFailure);
6852 return VINF_SUCCESS;
6853}
6854
6855
6856/**
6857 * Loads the guest-state non-register state as part of VM-entry.
6858 *
6859 * @returns VBox status code.
6860 * @param pVCpu The cross context virtual CPU structure.
6861 *
6862 * @remarks This must be called only after loading the nested-guest register state
6863 * (especially nested-guest RIP).
6864 */
6865IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
6866{
6867 /*
6868 * Load guest non-register state.
6869 * See Intel spec. 26.6 "Special Features of VM Entry"
6870 */
6871 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6872 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6873 if (!fEntryVectoring)
6874 {
6875 if (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6876 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
6877 else
6878 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
6879
6880 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6881 }
6882 else
6883 {
6884 /* When the VM-entry is not vectoring, there is no blocking by STI or Mov-SS. */
6885 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6886 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6887 }
6888
6889 /* NMI blocking. */
6890 if ( (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6891 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6892 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6893
6894 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6895 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6896
6897 /* VPID is irrelevant. We don't support VPID yet. */
6898
6899 /* Clear address-range monitoring. */
6900 EMMonitorWaitClear(pVCpu);
6901}
6902
6903
6904/**
6905 * Loads the guest-state as part of VM-entry.
6906 *
6907 * @returns VBox status code.
6908 * @param pVCpu The cross context virtual CPU structure.
6909 * @param pszInstr The VMX instruction name (for logging purposes).
6910 *
6911 * @remarks This must be done after all the necessary steps prior to loading of
6912 * guest-state (e.g. checking various VMCS state).
6913 */
6914IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
6915{
6916 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6917 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6918
6919 /*
6920 * Load guest RIP, RSP and RFLAGS.
6921 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6922 */
6923 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6924 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6925 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6926 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6927
6928 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6929 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6930 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6931
6932 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6933
6934 NOREF(pszInstr);
6935 return VINF_SUCCESS;
6936}
6937
6938
6939/**
6940 * Returns whether there are is a pending debug exception on VM-entry.
6941 *
6942 * @param pVCpu The cross context virtual CPU structure.
6943 * @param pszInstr The VMX instruction name (for logging purposes).
6944 */
6945IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
6946{
6947 /*
6948 * Pending debug exceptions.
6949 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6950 */
6951 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6952 Assert(pVmcs);
6953
6954 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6955 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6956 if (fPendingDbgXcpt)
6957 {
6958 uint8_t uEntryIntInfoType;
6959 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6960 if (fEntryVectoring)
6961 {
6962 switch (uEntryIntInfoType)
6963 {
6964 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6965 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6966 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6967 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6968 fPendingDbgXcpt = false;
6969 break;
6970
6971 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6972 {
6973 /*
6974 * Whether the pending debug exception for software exceptions other than
6975 * #BP and #OF is delivered after injecting the exception or is discard
6976 * is CPU implementation specific. We will discard them (easier).
6977 */
6978 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6979 if ( uVector != X86_XCPT_BP
6980 && uVector != X86_XCPT_OF)
6981 fPendingDbgXcpt = false;
6982 RT_FALL_THRU();
6983 }
6984 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6985 {
6986 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6987 fPendingDbgXcpt = false;
6988 break;
6989 }
6990 }
6991 }
6992 else
6993 {
6994 /*
6995 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6996 * pending debug exception is held pending or is discarded is CPU implementation
6997 * specific. We will discard them (easier).
6998 */
6999 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7000 fPendingDbgXcpt = false;
7001
7002 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7003 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7004 fPendingDbgXcpt = false;
7005 }
7006 }
7007
7008 NOREF(pszInstr);
7009 return fPendingDbgXcpt;
7010}
7011
7012
7013/**
7014 * Set up the monitor-trap flag (MTF).
7015 *
7016 * @param pVCpu The cross context virtual CPU structure.
7017 * @param pszInstr The VMX instruction name (for logging purposes).
7018 */
7019IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7020{
7021 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7022 Assert(pVmcs);
7023 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7024 {
7025 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7026 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7027 }
7028 else
7029 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7030 NOREF(pszInstr);
7031}
7032
7033
7034/**
7035 * Set up the VMX-preemption timer.
7036 *
7037 * @param pVCpu The cross context virtual CPU structure.
7038 * @param pszInstr The VMX instruction name (for logging purposes).
7039 */
7040IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7041{
7042 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7043 Assert(pVmcs);
7044 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7045 {
7046 uint64_t const uVmentryTick = TMCpuTickGetNoCheck(pVCpu);
7047 pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick = uVmentryTick;
7048 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7049
7050 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uVmentryTick));
7051 }
7052 else
7053 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7054
7055 NOREF(pszInstr);
7056}
7057
7058
7059/**
7060 * Injects an event using TRPM given a VM-entry interruption info. and related
7061 * fields.
7062 *
7063 * @returns VBox status code.
7064 * @param pVCpu The cross context virtual CPU structure.
7065 * @param uEntryIntInfo The VM-entry interruption info.
7066 * @param uErrCode The error code associated with the event if any.
7067 * @param cbInstr The VM-entry instruction length (for software
7068 * interrupts and software exceptions). Pass 0
7069 * otherwise.
7070 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7071 */
7072IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7073 RTGCUINTPTR GCPtrFaultAddress)
7074{
7075 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7076
7077 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7078 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7079 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7080
7081 TRPMEVENT enmTrapType;
7082 switch (uType)
7083 {
7084 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7085 enmTrapType = TRPM_HARDWARE_INT;
7086 break;
7087
7088 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7089 enmTrapType = TRPM_SOFTWARE_INT;
7090 break;
7091
7092 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7093 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
7094 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7095 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7096 enmTrapType = TRPM_TRAP;
7097 break;
7098
7099 default:
7100 /* Shouldn't really happen. */
7101 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7102 break;
7103 }
7104
7105 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7106 AssertRCReturn(rc, rc);
7107
7108 if (fErrCodeValid)
7109 TRPMSetErrorCode(pVCpu, uErrCode);
7110
7111 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
7112 && uVector == X86_XCPT_PF)
7113 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7114 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7115 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7116 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7117 {
7118 AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7119 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7120 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
7121 TRPMSetInstrLength(pVCpu, cbInstr);
7122 }
7123
7124 return VINF_SUCCESS;
7125}
7126
7127
7128/**
7129 * Performs event injection (if any) as part of VM-entry.
7130 *
7131 * @param pVCpu The cross context virtual CPU structure.
7132 * @param pszInstr The VMX instruction name (for logging purposes).
7133 */
7134IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7135{
7136 /*
7137 * Inject events.
7138 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7139 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7140 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7141 * the actually delivery of this event.
7142 *
7143 * See Intel spec. 26.5 "Event Injection".
7144 */
7145 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7146 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7147 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7148
7149 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7150 if (fEntryIntInfoValid)
7151 {
7152 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7153 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7154 {
7155 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7156 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7157 return VINF_SUCCESS;
7158 }
7159
7160 return iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7161 pVCpu->cpum.GstCtx.cr2);
7162 }
7163
7164 /*
7165 * Inject any pending guest debug exception.
7166 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7167 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7168 */
7169 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7170 if (fPendingDbgXcpt)
7171 {
7172 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7173 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7174 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7175 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7176 0 /* GCPtrFaultAddress */);
7177 }
7178
7179 NOREF(pszInstr);
7180 return VINF_SUCCESS;
7181}
7182
7183
7184/**
7185 * Initializes all read-only VMCS fields as part of VM-entry.
7186 *
7187 * @param pVCpu The cross context virtual CPU structure.
7188 */
7189IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7190{
7191 /*
7192 * Any VMCS field which we do not establish on every VM-exit but may potentially
7193 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7194 * specified to be undefined needs to be initialized here.
7195 *
7196 * Thus, it is especially important to clear the VM-exit qualification field
7197 * since it must be zero for VM-exits where it is not used. Similarly, the
7198 * VM-exit interruption information field's valid bit needs to be cleared for
7199 * the same reasons.
7200 */
7201 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7202 Assert(pVmcs);
7203
7204 /* 16-bit (none currently). */
7205 /* 32-bit. */
7206 pVmcs->u32RoVmInstrError = 0;
7207 pVmcs->u32RoExitReason = 0;
7208 pVmcs->u32RoExitIntInfo = 0;
7209 pVmcs->u32RoExitIntErrCode = 0;
7210 pVmcs->u32RoIdtVectoringInfo = 0;
7211 pVmcs->u32RoIdtVectoringErrCode = 0;
7212 pVmcs->u32RoExitInstrLen = 0;
7213 pVmcs->u32RoExitInstrInfo = 0;
7214
7215 /* 64-bit. */
7216 pVmcs->u64RoGuestPhysAddr.u = 0;
7217
7218 /* Natural-width. */
7219 pVmcs->u64RoExitQual.u = 0;
7220 pVmcs->u64RoIoRcx.u = 0;
7221 pVmcs->u64RoIoRsi.u = 0;
7222 pVmcs->u64RoIoRdi.u = 0;
7223 pVmcs->u64RoIoRip.u = 0;
7224 pVmcs->u64RoGuestLinearAddr.u = 0;
7225}
7226
7227
7228/**
7229 * VMLAUNCH/VMRESUME instruction execution worker.
7230 *
7231 * @returns Strict VBox status code.
7232 * @param pVCpu The cross context virtual CPU structure.
7233 * @param cbInstr The instruction length in bytes.
7234 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7235 * VMXINSTRID_VMRESUME).
7236 *
7237 * @remarks Common VMX instruction checks are already expected to by the caller,
7238 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7239 */
7240IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7241{
7242# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7243 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7244 return VINF_EM_RAW_EMULATE_INSTR;
7245# else
7246 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7247 || uInstrId == VMXINSTRID_VMRESUME);
7248 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7249
7250 /* Nested-guest intercept. */
7251 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7252 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7253
7254 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7255
7256 /* CPL. */
7257 if (pVCpu->iem.s.uCpl == 0)
7258 { /* likely */ }
7259 else
7260 {
7261 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7262 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7263 return iemRaiseGeneralProtectionFault0(pVCpu);
7264 }
7265
7266 /* Current VMCS valid. */
7267 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7268 { /* likely */ }
7269 else
7270 {
7271 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7272 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7273 iemVmxVmFailInvalid(pVCpu);
7274 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7275 return VINF_SUCCESS;
7276 }
7277
7278 /** @todo Distinguish block-by-MOV-SS from block-by-STI. Currently we
7279 * use block-by-STI here which is not quite correct. */
7280 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7281 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
7282 {
7283 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7284 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7285 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7286 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7287 return VINF_SUCCESS;
7288 }
7289
7290 if (uInstrId == VMXINSTRID_VMLAUNCH)
7291 {
7292 /* VMLAUNCH with non-clear VMCS. */
7293 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
7294 { /* likely */ }
7295 else
7296 {
7297 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7298 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7299 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7300 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7301 return VINF_SUCCESS;
7302 }
7303 }
7304 else
7305 {
7306 /* VMRESUME with non-launched VMCS. */
7307 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
7308 { /* likely */ }
7309 else
7310 {
7311 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7313 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7314 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7315 return VINF_SUCCESS;
7316 }
7317 }
7318
7319 /*
7320 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7321 * while entering VMX non-root mode. We do some of this while checking VM-execution
7322 * controls. The guest hypervisor should not make assumptions and cannot expect
7323 * predictable behavior if changes to these structures are made in guest memory while
7324 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7325 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7326 *
7327 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7328 */
7329 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7330 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7331 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7332 if (RT_SUCCESS(rc))
7333 {
7334 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7335 if (RT_SUCCESS(rc))
7336 {
7337 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7338 if (RT_SUCCESS(rc))
7339 {
7340 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7341 if (RT_SUCCESS(rc))
7342 {
7343 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7344 iemVmxVmentryInitReadOnlyFields(pVCpu);
7345
7346 /*
7347 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7348 * So we save the the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7349 * VM-exit when required.
7350 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7351 */
7352 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7353
7354 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7355 if (RT_SUCCESS(rc))
7356 {
7357 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7358 if (RT_SUCCESS(rc))
7359 {
7360 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7361 if (RT_SUCCESS(rc))
7362 {
7363 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7364
7365 /* VMLAUNCH instruction must update the VMCS launch state. */
7366 if (uInstrId == VMXINSTRID_VMLAUNCH)
7367 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
7368
7369 /* Perform the VMX transition (PGM updates). */
7370 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7371 if (rcStrict == VINF_SUCCESS)
7372 { /* likely */ }
7373 else if (RT_SUCCESS(rcStrict))
7374 {
7375 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7376 VBOXSTRICTRC_VAL(rcStrict)));
7377 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7378 }
7379 else
7380 {
7381 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7382 return rcStrict;
7383 }
7384
7385 /* We've now entered nested-guest execution. */
7386 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7387
7388 /*
7389 * The priority of potential VM-exits during VM-entry is important.
7390 * The priorities of VM-exits and events are listed from highest
7391 * to lowest as follows:
7392 *
7393 * 1. Event injection.
7394 * 2. Trap on task-switch (T flag set in TSS).
7395 * 3. TPR below threshold / APIC-write.
7396 * 4. SMI, INIT.
7397 * 5. MTF exit.
7398 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7399 * 7. VMX-preemption timer.
7400 * 9. NMI-window exit.
7401 * 10. NMI injection.
7402 * 11. Interrupt-window exit.
7403 * 12. Virtual-interrupt injection.
7404 * 13. Interrupt injection.
7405 * 14. Process next instruction (fetch, decode, execute).
7406 */
7407
7408 /* Setup the VMX-preemption timer. */
7409 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7410
7411 /* Setup monitor-trap flag. */
7412 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7413
7414 /* Now that we've switched page tables, we can go ahead and inject any event. */
7415 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7416 if (RT_SUCCESS(rcStrict))
7417 {
7418 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7419 IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(pVCpu, pszInstr, VINF_SUCCESS);
7420 }
7421
7422 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7423 return rcStrict;
7424 }
7425 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7426 }
7427 }
7428 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7429 }
7430
7431 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7432 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7433 return VINF_SUCCESS;
7434 }
7435 }
7436 }
7437
7438 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7439 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7440 return VINF_SUCCESS;
7441# endif
7442}
7443
7444
7445/**
7446 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7447 * (causes a VM-exit) or not.
7448 *
7449 * @returns @c true if the instruction is intercepted, @c false otherwise.
7450 * @param pVCpu The cross context virtual CPU structure.
7451 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7452 * VMX_EXIT_WRMSR).
7453 * @param idMsr The MSR.
7454 */
7455IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7456{
7457 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7458 Assert( uExitReason == VMX_EXIT_RDMSR
7459 || uExitReason == VMX_EXIT_WRMSR);
7460
7461 /* Consult the MSR bitmap if the feature is supported. */
7462 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7463 Assert(pVmcs);
7464 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7465 {
7466 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7467 if (uExitReason == VMX_EXIT_RDMSR)
7468 {
7469 VMXMSREXITREAD enmRead;
7470 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
7471 NULL /* penmWrite */);
7472 AssertRC(rc);
7473 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
7474 return true;
7475 }
7476 else
7477 {
7478 VMXMSREXITWRITE enmWrite;
7479 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
7480 &enmWrite);
7481 AssertRC(rc);
7482 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
7483 return true;
7484 }
7485 return false;
7486 }
7487
7488 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7489 return true;
7490}
7491
7492
7493/**
7494 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7495 * intercepted (causes a VM-exit) or not.
7496 *
7497 * @returns @c true if the instruction is intercepted, @c false otherwise.
7498 * @param pVCpu The cross context virtual CPU structure.
7499 * @param u64FieldEnc The VMCS field encoding.
7500 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7501 * VMX_EXIT_VMREAD).
7502 */
7503IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7504{
7505 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7506 Assert( uExitReason == VMX_EXIT_VMREAD
7507 || uExitReason == VMX_EXIT_VMWRITE);
7508
7509 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7510 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7511 return true;
7512
7513 /*
7514 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7515 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7516 */
7517 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7518 return true;
7519
7520 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7521 uint32_t u32FieldEnc = RT_LO_U32(u64FieldEnc);
7522 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7523 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7524 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7525 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7526 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7527 pbBitmap += (u32FieldEnc >> 3);
7528 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7529 return true;
7530
7531 return false;
7532}
7533
7534
7535/**
7536 * VMREAD common (memory/register) instruction execution worker
7537 *
7538 * @returns Strict VBox status code.
7539 * @param pVCpu The cross context virtual CPU structure.
7540 * @param cbInstr The instruction length in bytes.
7541 * @param pu64Dst Where to write the VMCS value (only updated when
7542 * VINF_SUCCESS is returned).
7543 * @param u64FieldEnc The VMCS field encoding.
7544 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7545 * be NULL.
7546 */
7547IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7548 PCVMXVEXITINFO pExitInfo)
7549{
7550 /* Nested-guest intercept. */
7551 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7552 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7553 {
7554 if (pExitInfo)
7555 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7556 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7557 }
7558
7559 /* CPL. */
7560 if (pVCpu->iem.s.uCpl == 0)
7561 { /* likely */ }
7562 else
7563 {
7564 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7565 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7566 return iemRaiseGeneralProtectionFault0(pVCpu);
7567 }
7568
7569 /* VMCS pointer in root mode. */
7570 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
7571 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7572 {
7573 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7574 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7575 iemVmxVmFailInvalid(pVCpu);
7576 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7577 return VINF_SUCCESS;
7578 }
7579
7580 /* VMCS-link pointer in non-root mode. */
7581 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7582 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7583 {
7584 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7585 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7586 iemVmxVmFailInvalid(pVCpu);
7587 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7588 return VINF_SUCCESS;
7589 }
7590
7591 /* Supported VMCS field. */
7592 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7593 { /* likely */ }
7594 else
7595 {
7596 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7597 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7598 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7599 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7600 return VINF_SUCCESS;
7601 }
7602
7603 /*
7604 * Setup reading from the current or shadow VMCS.
7605 */
7606 uint8_t *pbVmcs;
7607 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7608 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7609 else
7610 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7611 Assert(pbVmcs);
7612
7613 VMXVMCSFIELDENC FieldEnc;
7614 FieldEnc.u = u64FieldEnc;
7615 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7616 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7617 uint8_t const uWidthType = (uWidth << 2) | uType;
7618 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7619 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7620 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7621 Assert(offField < VMX_V_VMCS_SIZE);
7622
7623 /*
7624 * Read the VMCS component based on the field's effective width.
7625 *
7626 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7627 * indicates high bits (little endian).
7628 *
7629 * Note! The caller is responsible to trim the result and update registers
7630 * or memory locations are required. Here we just zero-extend to the largest
7631 * type (i.e. 64-bits).
7632 */
7633 uint8_t *pbField = pbVmcs + offField;
7634 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7635 switch (uEffWidth)
7636 {
7637 case VMX_VMCS_ENC_WIDTH_64BIT:
7638 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7639 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7640 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7641 }
7642 return VINF_SUCCESS;
7643}
7644
7645
7646/**
7647 * VMREAD (64-bit register) instruction execution worker.
7648 *
7649 * @returns Strict VBox status code.
7650 * @param pVCpu The cross context virtual CPU structure.
7651 * @param cbInstr The instruction length in bytes.
7652 * @param pu64Dst Where to store the VMCS field's value.
7653 * @param u64FieldEnc The VMCS field encoding.
7654 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7655 * be NULL.
7656 */
7657IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7658 PCVMXVEXITINFO pExitInfo)
7659{
7660 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7661 if (rcStrict == VINF_SUCCESS)
7662 {
7663 iemVmxVmreadSuccess(pVCpu, cbInstr);
7664 return VINF_SUCCESS;
7665 }
7666
7667 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7668 return rcStrict;
7669}
7670
7671
7672/**
7673 * VMREAD (32-bit register) instruction execution worker.
7674 *
7675 * @returns Strict VBox status code.
7676 * @param pVCpu The cross context virtual CPU structure.
7677 * @param cbInstr The instruction length in bytes.
7678 * @param pu32Dst Where to store the VMCS field's value.
7679 * @param u32FieldEnc The VMCS field encoding.
7680 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7681 * be NULL.
7682 */
7683IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7684 PCVMXVEXITINFO pExitInfo)
7685{
7686 uint64_t u64Dst;
7687 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7688 if (rcStrict == VINF_SUCCESS)
7689 {
7690 *pu32Dst = u64Dst;
7691 iemVmxVmreadSuccess(pVCpu, cbInstr);
7692 return VINF_SUCCESS;
7693 }
7694
7695 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7696 return rcStrict;
7697}
7698
7699
7700/**
7701 * VMREAD (memory) instruction execution worker.
7702 *
7703 * @returns Strict VBox status code.
7704 * @param pVCpu The cross context virtual CPU structure.
7705 * @param cbInstr The instruction length in bytes.
7706 * @param iEffSeg The effective segment register to use with @a u64Val.
7707 * Pass UINT8_MAX if it is a register access.
7708 * @param enmEffAddrMode The effective addressing mode (only used with memory
7709 * operand).
7710 * @param GCPtrDst The guest linear address to store the VMCS field's
7711 * value.
7712 * @param u64FieldEnc The VMCS field encoding.
7713 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7714 * be NULL.
7715 */
7716IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
7717 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7718{
7719 uint64_t u64Dst;
7720 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7721 if (rcStrict == VINF_SUCCESS)
7722 {
7723 /*
7724 * Write the VMCS field's value to the location specified in guest-memory.
7725 *
7726 * The pointer size depends on the address size (address-size prefix allowed).
7727 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
7728 */
7729 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7730 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7731 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
7732
7733 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7734 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7735 else
7736 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7737 if (rcStrict == VINF_SUCCESS)
7738 {
7739 iemVmxVmreadSuccess(pVCpu, cbInstr);
7740 return VINF_SUCCESS;
7741 }
7742
7743 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7744 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7745 return rcStrict;
7746 }
7747
7748 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7749 return rcStrict;
7750}
7751
7752
7753/**
7754 * VMWRITE instruction execution worker.
7755 *
7756 * @returns Strict VBox status code.
7757 * @param pVCpu The cross context virtual CPU structure.
7758 * @param cbInstr The instruction length in bytes.
7759 * @param iEffSeg The effective segment register to use with @a u64Val.
7760 * Pass UINT8_MAX if it is a register access.
7761 * @param enmEffAddrMode The effective addressing mode (only used with memory
7762 * operand).
7763 * @param u64Val The value to write (or guest linear address to the
7764 * value), @a iEffSeg will indicate if it's a memory
7765 * operand.
7766 * @param u64FieldEnc The VMCS field encoding.
7767 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7768 * be NULL.
7769 */
7770IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
7771 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7772{
7773 /* Nested-guest intercept. */
7774 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7775 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
7776 {
7777 if (pExitInfo)
7778 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7779 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7780 }
7781
7782 /* CPL. */
7783 if (pVCpu->iem.s.uCpl == 0)
7784 { /* likely */ }
7785 else
7786 {
7787 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7788 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7789 return iemRaiseGeneralProtectionFault0(pVCpu);
7790 }
7791
7792 /* VMCS pointer in root mode. */
7793 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
7794 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7795 {
7796 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7797 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7798 iemVmxVmFailInvalid(pVCpu);
7799 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7800 return VINF_SUCCESS;
7801 }
7802
7803 /* VMCS-link pointer in non-root mode. */
7804 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7805 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7806 {
7807 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7808 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7809 iemVmxVmFailInvalid(pVCpu);
7810 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7811 return VINF_SUCCESS;
7812 }
7813
7814 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7815 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7816 if (!fIsRegOperand)
7817 {
7818 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7819 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7820 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
7821
7822 /* Read the value from the specified guest memory location. */
7823 VBOXSTRICTRC rcStrict;
7824 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7825 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7826 else
7827 {
7828 uint32_t u32Val;
7829 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7830 u64Val = u32Val;
7831 }
7832 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7833 {
7834 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7835 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7836 return rcStrict;
7837 }
7838 }
7839 else
7840 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7841
7842 /* Supported VMCS field. */
7843 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7844 { /* likely */ }
7845 else
7846 {
7847 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7848 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7849 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7850 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7851 return VINF_SUCCESS;
7852 }
7853
7854 /* Read-only VMCS field. */
7855 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
7856 if ( fIsFieldReadOnly
7857 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7858 {
7859 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
7860 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7861 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7862 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7863 return VINF_SUCCESS;
7864 }
7865
7866 /*
7867 * Setup writing to the current or shadow VMCS.
7868 */
7869 uint8_t *pbVmcs;
7870 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7871 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7872 else
7873 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7874 Assert(pbVmcs);
7875
7876 VMXVMCSFIELDENC FieldEnc;
7877 FieldEnc.u = u64FieldEnc;
7878 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7879 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7880 uint8_t const uWidthType = (uWidth << 2) | uType;
7881 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7882 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7883 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7884 Assert(offField < VMX_V_VMCS_SIZE);
7885
7886 /*
7887 * Write the VMCS component based on the field's effective width.
7888 *
7889 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7890 * indicates high bits (little endian).
7891 */
7892 uint8_t *pbField = pbVmcs + offField;
7893 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7894 switch (uEffWidth)
7895 {
7896 case VMX_VMCS_ENC_WIDTH_64BIT:
7897 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7898 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7899 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7900 }
7901
7902 iemVmxVmSucceed(pVCpu);
7903 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7904 return VINF_SUCCESS;
7905}
7906
7907
7908/**
7909 * VMCLEAR instruction execution worker.
7910 *
7911 * @returns Strict VBox status code.
7912 * @param pVCpu The cross context virtual CPU structure.
7913 * @param cbInstr The instruction length in bytes.
7914 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7915 * @param GCPtrVmcs The linear address of the VMCS pointer.
7916 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7917 * be NULL.
7918 *
7919 * @remarks Common VMX instruction checks are already expected to by the caller,
7920 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7921 */
7922IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7923 PCVMXVEXITINFO pExitInfo)
7924{
7925 /* Nested-guest intercept. */
7926 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7927 {
7928 if (pExitInfo)
7929 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7930 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7931 }
7932
7933 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7934
7935 /* CPL. */
7936 if (pVCpu->iem.s.uCpl == 0)
7937 { /* likely */ }
7938 else
7939 {
7940 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7941 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7942 return iemRaiseGeneralProtectionFault0(pVCpu);
7943 }
7944
7945 /* Get the VMCS pointer from the location specified by the source memory operand. */
7946 RTGCPHYS GCPhysVmcs;
7947 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7948 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7949 {
7950 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7951 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7952 return rcStrict;
7953 }
7954
7955 /* VMCS pointer alignment. */
7956 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
7957 {
7958 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7959 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7960 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7961 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7962 return VINF_SUCCESS;
7963 }
7964
7965 /* VMCS physical-address width limits. */
7966 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
7967 {
7968 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7969 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7970 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7971 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7972 return VINF_SUCCESS;
7973 }
7974
7975 /* VMCS is not the VMXON region. */
7976 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7977 {
7978 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7979 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7980 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7981 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7982 return VINF_SUCCESS;
7983 }
7984
7985 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7986 restriction imposed by our implementation. */
7987 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7988 {
7989 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7990 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7991 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7992 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7993 return VINF_SUCCESS;
7994 }
7995
7996 /*
7997 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7998 *
7999 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8000 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8001 * to 'clear'.
8002 */
8003 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
8004 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8005 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8006 {
8007 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8008 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8009 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
8010 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8011 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8012 }
8013 else
8014 {
8015 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsStateClear));
8016 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8017 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
8018 if (RT_FAILURE(rcStrict))
8019 return rcStrict;
8020 }
8021
8022 iemVmxVmSucceed(pVCpu);
8023 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8024 return VINF_SUCCESS;
8025}
8026
8027
8028/**
8029 * VMPTRST instruction execution worker.
8030 *
8031 * @returns Strict VBox status code.
8032 * @param pVCpu The cross context virtual CPU structure.
8033 * @param cbInstr The instruction length in bytes.
8034 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8035 * @param GCPtrVmcs The linear address of where to store the current VMCS
8036 * pointer.
8037 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8038 * be NULL.
8039 *
8040 * @remarks Common VMX instruction checks are already expected to by the caller,
8041 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8042 */
8043IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8044 PCVMXVEXITINFO pExitInfo)
8045{
8046 /* Nested-guest intercept. */
8047 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8048 {
8049 if (pExitInfo)
8050 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8051 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8052 }
8053
8054 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8055
8056 /* CPL. */
8057 if (pVCpu->iem.s.uCpl == 0)
8058 { /* likely */ }
8059 else
8060 {
8061 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8062 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8063 return iemRaiseGeneralProtectionFault0(pVCpu);
8064 }
8065
8066 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8067 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8068 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8069 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8070 {
8071 iemVmxVmSucceed(pVCpu);
8072 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8073 return rcStrict;
8074 }
8075
8076 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8077 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8078 return rcStrict;
8079}
8080
8081
8082/**
8083 * VMPTRLD instruction execution worker.
8084 *
8085 * @returns Strict VBox status code.
8086 * @param pVCpu The cross context virtual CPU structure.
8087 * @param cbInstr The instruction length in bytes.
8088 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8089 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8090 * be NULL.
8091 *
8092 * @remarks Common VMX instruction checks are already expected to by the caller,
8093 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8094 */
8095IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8096 PCVMXVEXITINFO pExitInfo)
8097{
8098 /* Nested-guest intercept. */
8099 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8100 {
8101 if (pExitInfo)
8102 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8103 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8104 }
8105
8106 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8107
8108 /* CPL. */
8109 if (pVCpu->iem.s.uCpl == 0)
8110 { /* likely */ }
8111 else
8112 {
8113 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8114 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8115 return iemRaiseGeneralProtectionFault0(pVCpu);
8116 }
8117
8118 /* Get the VMCS pointer from the location specified by the source memory operand. */
8119 RTGCPHYS GCPhysVmcs;
8120 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8121 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8122 {
8123 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8124 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8125 return rcStrict;
8126 }
8127
8128 /* VMCS pointer alignment. */
8129 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
8130 {
8131 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8132 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8133 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8134 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8135 return VINF_SUCCESS;
8136 }
8137
8138 /* VMCS physical-address width limits. */
8139 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
8140 {
8141 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8142 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8143 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8144 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8145 return VINF_SUCCESS;
8146 }
8147
8148 /* VMCS is not the VMXON region. */
8149 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8150 {
8151 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8152 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8153 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8154 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8155 return VINF_SUCCESS;
8156 }
8157
8158 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8159 restriction imposed by our implementation. */
8160 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8161 {
8162 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8163 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8164 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8165 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8166 return VINF_SUCCESS;
8167 }
8168
8169 /* Read just the VMCS revision from the VMCS. */
8170 VMXVMCSREVID VmcsRevId;
8171 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8172 if (RT_FAILURE(rc))
8173 {
8174 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8175 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8176 return rc;
8177 }
8178
8179 /*
8180 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8181 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8182 */
8183 if ( VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID
8184 || ( VmcsRevId.n.fIsShadowVmcs
8185 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8186 {
8187 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8188 {
8189 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8190 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8191 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8192 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8193 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8194 return VINF_SUCCESS;
8195 }
8196
8197 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8198 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8199 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8200 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8201 return VINF_SUCCESS;
8202 }
8203
8204 /*
8205 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8206 * the cache of an existing, current VMCS back to guest memory before loading a new,
8207 * different current VMCS.
8208 */
8209 bool fLoadVmcsFromMem;
8210 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8211 {
8212 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8213 {
8214 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8215 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8216 fLoadVmcsFromMem = true;
8217 }
8218 else
8219 fLoadVmcsFromMem = false;
8220 }
8221 else
8222 fLoadVmcsFromMem = true;
8223
8224 if (fLoadVmcsFromMem)
8225 {
8226 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8227 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8228 sizeof(VMXVVMCS));
8229 if (RT_FAILURE(rc))
8230 {
8231 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8232 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8233 return rc;
8234 }
8235 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8236 }
8237
8238 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8239 iemVmxVmSucceed(pVCpu);
8240 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8241 return VINF_SUCCESS;
8242}
8243
8244
8245/**
8246 * VMXON instruction execution worker.
8247 *
8248 * @returns Strict VBox status code.
8249 * @param pVCpu The cross context virtual CPU structure.
8250 * @param cbInstr The instruction length in bytes.
8251 * @param iEffSeg The effective segment register to use with @a
8252 * GCPtrVmxon.
8253 * @param GCPtrVmxon The linear address of the VMXON pointer.
8254 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8255 * Optional, can be NULL.
8256 *
8257 * @remarks Common VMX instruction checks are already expected to by the caller,
8258 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8259 */
8260IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8261 PCVMXVEXITINFO pExitInfo)
8262{
8263 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8264 {
8265 /* CPL. */
8266 if (pVCpu->iem.s.uCpl == 0)
8267 { /* likely */ }
8268 else
8269 {
8270 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8271 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8272 return iemRaiseGeneralProtectionFault0(pVCpu);
8273 }
8274
8275 /* A20M (A20 Masked) mode. */
8276 if (PGMPhysIsA20Enabled(pVCpu))
8277 { /* likely */ }
8278 else
8279 {
8280 Log(("vmxon: A20M mode -> #GP(0)\n"));
8281 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8282 return iemRaiseGeneralProtectionFault0(pVCpu);
8283 }
8284
8285 /* CR0. */
8286 {
8287 /* CR0 MB1 bits. */
8288 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8289 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) != uCr0Fixed0)
8290 {
8291 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8292 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8293 return iemRaiseGeneralProtectionFault0(pVCpu);
8294 }
8295
8296 /* CR0 MBZ bits. */
8297 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8298 if (pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1)
8299 {
8300 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8301 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8302 return iemRaiseGeneralProtectionFault0(pVCpu);
8303 }
8304 }
8305
8306 /* CR4. */
8307 {
8308 /* CR4 MB1 bits. */
8309 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8310 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) != uCr4Fixed0)
8311 {
8312 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8313 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8314 return iemRaiseGeneralProtectionFault0(pVCpu);
8315 }
8316
8317 /* CR4 MBZ bits. */
8318 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8319 if (pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1)
8320 {
8321 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8322 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8323 return iemRaiseGeneralProtectionFault0(pVCpu);
8324 }
8325 }
8326
8327 /* Feature control MSR's LOCK and VMXON bits. */
8328 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8329 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8330 != (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8331 {
8332 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8333 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8334 return iemRaiseGeneralProtectionFault0(pVCpu);
8335 }
8336
8337 /* Get the VMXON pointer from the location specified by the source memory operand. */
8338 RTGCPHYS GCPhysVmxon;
8339 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8340 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8341 {
8342 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8343 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8344 return rcStrict;
8345 }
8346
8347 /* VMXON region pointer alignment. */
8348 if (GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK)
8349 {
8350 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8351 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8352 iemVmxVmFailInvalid(pVCpu);
8353 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8354 return VINF_SUCCESS;
8355 }
8356
8357 /* VMXON physical-address width limits. */
8358 if (GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
8359 {
8360 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8361 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8362 iemVmxVmFailInvalid(pVCpu);
8363 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8364 return VINF_SUCCESS;
8365 }
8366
8367 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8368 restriction imposed by our implementation. */
8369 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8370 {
8371 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8372 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8373 iemVmxVmFailInvalid(pVCpu);
8374 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8375 return VINF_SUCCESS;
8376 }
8377
8378 /* Read the VMCS revision ID from the VMXON region. */
8379 VMXVMCSREVID VmcsRevId;
8380 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8381 if (RT_FAILURE(rc))
8382 {
8383 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8384 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8385 return rc;
8386 }
8387
8388 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8389 if (RT_UNLIKELY(VmcsRevId.u != VMX_V_VMCS_REVISION_ID))
8390 {
8391 /* Revision ID mismatch. */
8392 if (!VmcsRevId.n.fIsShadowVmcs)
8393 {
8394 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8395 VmcsRevId.n.u31RevisionId));
8396 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8397 iemVmxVmFailInvalid(pVCpu);
8398 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8399 return VINF_SUCCESS;
8400 }
8401
8402 /* Shadow VMCS disallowed. */
8403 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8405 iemVmxVmFailInvalid(pVCpu);
8406 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8407 return VINF_SUCCESS;
8408 }
8409
8410 /*
8411 * Record that we're in VMX operation, block INIT, block and disable A20M.
8412 */
8413 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8414 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8415 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8416
8417 /* Clear address-range monitoring. */
8418 EMMonitorWaitClear(pVCpu);
8419 /** @todo NSTVMX: Intel PT. */
8420
8421 iemVmxVmSucceed(pVCpu);
8422 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8423 return VINF_SUCCESS;
8424 }
8425 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8426 {
8427 /* Nested-guest intercept. */
8428 if (pExitInfo)
8429 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8430 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8431 }
8432
8433 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8434
8435 /* CPL. */
8436 if (pVCpu->iem.s.uCpl > 0)
8437 {
8438 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8439 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8440 return iemRaiseGeneralProtectionFault0(pVCpu);
8441 }
8442
8443 /* VMXON when already in VMX root mode. */
8444 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8445 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8446 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8447 return VINF_SUCCESS;
8448}
8449
8450
8451/**
8452 * Implements 'VMXOFF'.
8453 *
8454 * @remarks Common VMX instruction checks are already expected to by the caller,
8455 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8456 */
8457IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8458{
8459 /* Nested-guest intercept. */
8460 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8461 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8462
8463 /* CPL. */
8464 if (pVCpu->iem.s.uCpl == 0)
8465 { /* likely */ }
8466 else
8467 {
8468 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8469 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8470 return iemRaiseGeneralProtectionFault0(pVCpu);
8471 }
8472
8473 /* Dual monitor treatment of SMIs and SMM. */
8474 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8475 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID)
8476 {
8477 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8478 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8479 return VINF_SUCCESS;
8480 }
8481
8482 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8483 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8484 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8485
8486 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8487 { /** @todo NSTVMX: Unblock SMI. */ }
8488
8489 EMMonitorWaitClear(pVCpu);
8490 /** @todo NSTVMX: Unblock and enable A20M. */
8491
8492 iemVmxVmSucceed(pVCpu);
8493 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8494 return VINF_SUCCESS;
8495}
8496
8497
8498/**
8499 * Implements 'VMXON'.
8500 */
8501IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8502{
8503 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8504}
8505
8506
8507/**
8508 * Implements 'VMLAUNCH'.
8509 */
8510IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8511{
8512 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8513}
8514
8515
8516/**
8517 * Implements 'VMRESUME'.
8518 */
8519IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8520{
8521 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8522}
8523
8524
8525/**
8526 * Implements 'VMPTRLD'.
8527 */
8528IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8529{
8530 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8531}
8532
8533
8534/**
8535 * Implements 'VMPTRST'.
8536 */
8537IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8538{
8539 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8540}
8541
8542
8543/**
8544 * Implements 'VMCLEAR'.
8545 */
8546IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8547{
8548 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8549}
8550
8551
8552/**
8553 * Implements 'VMWRITE' register.
8554 */
8555IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8556{
8557 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8558 NULL /* pExitInfo */);
8559}
8560
8561
8562/**
8563 * Implements 'VMWRITE' memory.
8564 */
8565IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8566{
8567 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8568}
8569
8570
8571/**
8572 * Implements 'VMREAD' register (64-bit).
8573 */
8574IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8575{
8576 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8577}
8578
8579
8580/**
8581 * Implements 'VMREAD' register (32-bit).
8582 */
8583IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8584{
8585 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8586}
8587
8588
8589/**
8590 * Implements 'VMREAD' memory, 64-bit register.
8591 */
8592IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8593{
8594 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8595}
8596
8597
8598/**
8599 * Implements 'VMREAD' memory, 32-bit register.
8600 */
8601IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
8602{
8603 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
8604}
8605
8606
8607/**
8608 * Implements VMX's implementation of PAUSE.
8609 */
8610IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8611{
8612 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8613 {
8614 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8615 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8616 return rcStrict;
8617 }
8618
8619 /*
8620 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8621 * a VM-exit, the instruction operates normally.
8622 */
8623 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8624 return VINF_SUCCESS;
8625}
8626
8627#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8628
8629
8630/**
8631 * Implements 'VMCALL'.
8632 */
8633IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8634{
8635#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8636 /* Nested-guest intercept. */
8637 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8638 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8639#endif
8640
8641 /* Join forces with vmmcall. */
8642 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8643}
8644
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