IEMAllCImplSvmInstr.cpp@ 97370

Last change on this file since 97370 was 97370, checked in by vboxsync, 2 years ago
VMM/IEM: iemRegAddToRipAndClearRF -> iemRegUpdateRipAndFinishClearingRF and made callers use the return code. bugref:9898
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1	/* $Id: IEMAllCImplSvmInstr.cpp 97370 2022-11-02 00:53:30Z vboxsync $ */
2	/** @file
3	* IEM - AMD-V (Secure Virtual Machine) instruction implementation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_IEM_SVM
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/iem.h>
35	#include <VBox/vmm/cpum.h>
36	#include <VBox/vmm/apic.h>
37	#include <VBox/vmm/pgm.h>
38	#include <VBox/vmm/em.h>
39	#include <VBox/vmm/hm.h>
40	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
41	# include <VBox/vmm/hm_svm.h>
42	#endif
43	#include <VBox/vmm/gim.h>
44	#include <VBox/vmm/tm.h>
45	#include "IEMInternal.h"
46	#include <VBox/vmm/vmcc.h>
47	#include <VBox/log.h>
48	#include <VBox/disopcode.h> /* for OP_VMMCALL */
49	#include <VBox/err.h>
50	#include <VBox/param.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53	#include <iprt/x86.h>
54
55	#include "IEMInline.h"
56
57
58	/*********************************************************************************************************************************
59	* Defined Constants And Macros *
60	*********************************************************************************************************************************/
61	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
62	/**
63	* Check the common SVM instruction preconditions.
64	*/
65	# define IEM_SVM_INSTR_COMMON_CHECKS(a_pVCpu, a_Instr) \
66	do { \
67	if (!CPUMIsGuestSvmEnabled(IEM_GET_CTX(a_pVCpu))) \
68	{ \
69	Log((RT_STR(a_Instr) ": EFER.SVME not enabled -> #UD\n")); \
70	return iemRaiseUndefinedOpcode(a_pVCpu); \
71	} \
72	if (IEM_IS_REAL_OR_V86_MODE(a_pVCpu)) \
73	{ \
74	Log((RT_STR(a_Instr) ": Real or v8086 mode -> #UD\n")); \
75	return iemRaiseUndefinedOpcode(a_pVCpu); \
76	} \
77	if ((a_pVCpu)->iem.s.uCpl != 0) \
78	{ \
79	Log((RT_STR(a_Instr) ": CPL != 0 -> #GP(0)\n")); \
80	return iemRaiseGeneralProtectionFault0(a_pVCpu); \
81	} \
82	} while (0)
83
84
85	/**
86	* Converts an IEM exception event type to an SVM event type.
87	*
88	* @returns The SVM event type.
89	* @retval UINT8_MAX if the specified type of event isn't among the set
90	* of recognized IEM event types.
91	*
92	* @param uVector The vector of the event.
93	* @param fIemXcptFlags The IEM exception / interrupt flags.
94	*/
95	IEM_STATIC uint8_t iemGetSvmEventType(uint32_t uVector, uint32_t fIemXcptFlags)
96	{
97	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
98	{
99	if (uVector != X86_XCPT_NMI)
100	return SVM_EVENT_EXCEPTION;
101	return SVM_EVENT_NMI;
102	}
103
104	/* See AMD spec. Table 15-1. "Guest Exception or Interrupt Types". */
105	if (fIemXcptFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
106	return SVM_EVENT_EXCEPTION;
107
108	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_EXT_INT)
109	return SVM_EVENT_EXTERNAL_IRQ;
110
111	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
112	return SVM_EVENT_SOFTWARE_INT;
113
114	AssertMsgFailed(("iemGetSvmEventType: Invalid IEM xcpt/int. type %#x, uVector=%#x\n", fIemXcptFlags, uVector));
115	return UINT8_MAX;
116	}
117
118
119	/**
120	* Performs an SVM world-switch (VMRUN, \#VMEXIT) updating PGM and IEM internals.
121	*
122	* @returns Strict VBox status code from PGMChangeMode.
123	* @param pVCpu The cross context virtual CPU structure.
124	*/
125	DECLINLINE(VBOXSTRICTRC) iemSvmWorldSwitch(PVMCPUCC pVCpu)
126	{
127	/*
128	* Inform PGM about paging mode changes.
129	* We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
130	* see comment in iemMemPageTranslateAndCheckAccess().
131	*/
132	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 \| X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
133	true /* fForce */);
134	AssertRCReturn(rc, rc);
135
136	/* Invalidate IEM TLBs now that we've forced a PGM mode change. */
137	IEMTlbInvalidateAll(pVCpu);
138
139	/* Inform CPUM (recompiler), can later be removed. */
140	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
141
142	/* Re-initialize IEM cache/state after the drastic mode switch. */
143	iemReInitExec(pVCpu);
144	return rc;
145	}
146
147
148	/**
149	* SVM \#VMEXIT handler.
150	*
151	* @returns Strict VBox status code.
152	* @retval VINF_SVM_VMEXIT when the \#VMEXIT is successful.
153	* @retval VERR_SVM_VMEXIT_FAILED when the \#VMEXIT failed restoring the guest's
154	* "host state" and a shutdown is required.
155	*
156	* @param pVCpu The cross context virtual CPU structure.
157	* @param uExitCode The exit code.
158	* @param uExitInfo1 The exit info. 1 field.
159	* @param uExitInfo2 The exit info. 2 field.
160	*/
161	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT
162	{
163	VBOXSTRICTRC rcStrict;
164	if ( CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu))
165	\|\| uExitCode == SVM_EXIT_INVALID)
166	{
167	Log2(("iemSvmVmexit: CS:RIP=%04x:%08RX64 uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n",
168	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uExitCode, uExitInfo1, uExitInfo2));
169
170	/*
171	* Disable the global-interrupt flag to prevent interrupts during the 'atomic' world switch.
172	*/
173	CPUMSetGuestGif(&pVCpu->cpum.GstCtx, false);
174
175	/*
176	* Map the nested-guest VMCB from its location in guest memory.
177	* Write exactly what the CPU does on #VMEXIT thereby preserving most other bits in the
178	* guest's VMCB in memory, see @bugref{7243#c113} and related comment on iemSvmVmrun().
179	*/
180	PSVMVMCB pVmcbMem;
181	PGMPAGEMAPLOCK PgLockMem;
182	PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
183	rcStrict = iemMemPageMap(pVCpu, pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, IEM_ACCESS_DATA_RW, (void **)&pVmcbMem,
184	&PgLockMem);
185	if (rcStrict == VINF_SUCCESS)
186	{
187	/*
188	* Notify HM in case the nested-guest was executed using hardware-assisted SVM (which
189	* would have modified some VMCB state) that might need to be restored on #VMEXIT before
190	* writing the VMCB back to guest memory.
191	*/
192	HMNotifySvmNstGstVmexit(pVCpu, IEM_GET_CTX(pVCpu));
193
194	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.es));
195	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.cs));
196	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
197	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ds));
198
199	/*
200	* Save the nested-guest state into the VMCB state-save area.
201	*/
202	PSVMVMCBSTATESAVE pVmcbMemState = &pVmcbMem->guest;
203	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, ES, es);
204	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, CS, cs);
205	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, SS, ss);
206	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, DS, ds);
207	pVmcbMemState->GDTR.u32Limit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
208	pVmcbMemState->GDTR.u64Base = pVCpu->cpum.GstCtx.gdtr.pGdt;
209	pVmcbMemState->IDTR.u32Limit = pVCpu->cpum.GstCtx.idtr.cbIdt;
210	pVmcbMemState->IDTR.u64Base = pVCpu->cpum.GstCtx.idtr.pIdt;
211	pVmcbMemState->u64EFER = pVCpu->cpum.GstCtx.msrEFER;
212	pVmcbMemState->u64CR4 = pVCpu->cpum.GstCtx.cr4;
213	pVmcbMemState->u64CR3 = pVCpu->cpum.GstCtx.cr3;
214	pVmcbMemState->u64CR2 = pVCpu->cpum.GstCtx.cr2;
215	pVmcbMemState->u64CR0 = pVCpu->cpum.GstCtx.cr0;
216	/** @todo Nested paging. */
217	pVmcbMemState->u64RFlags = pVCpu->cpum.GstCtx.rflags.u;
218	pVmcbMemState->u64RIP = pVCpu->cpum.GstCtx.rip;
219	pVmcbMemState->u64RSP = pVCpu->cpum.GstCtx.rsp;
220	pVmcbMemState->u64RAX = pVCpu->cpum.GstCtx.rax;
221	pVmcbMemState->u64DR7 = pVCpu->cpum.GstCtx.dr[7];
222	pVmcbMemState->u64DR6 = pVCpu->cpum.GstCtx.dr[6];
223	pVmcbMemState->u8CPL = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl; /* See comment in CPUMGetGuestCPL(). */
224	Assert(CPUMGetGuestCPL(pVCpu) == pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl);
225	if (CPUMIsGuestSvmNestedPagingEnabled(pVCpu, IEM_GET_CTX(pVCpu)))
226	pVmcbMemState->u64PAT = pVCpu->cpum.GstCtx.msrPAT;
227
228	/*
229	* Save additional state and intercept information.
230	*
231	* - V_IRQ: Tracked using VMCPU_FF_INTERRUPT_NESTED_GUEST force-flag and updated below.
232	* - V_TPR: Updated by iemCImpl_load_CrX or by the physical CPU for hardware-assisted
233	* SVM execution.
234	* - Interrupt shadow: Tracked using VMCPU_FF_INHIBIT_INTERRUPTS and RIP.
235	*/
236	PSVMVMCBCTRL pVmcbMemCtrl = &pVmcbMem->ctrl;
237	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)) /* V_IRQ. */
238	pVmcbMemCtrl->IntCtrl.n.u1VIrqPending = 0;
239	else
240	{
241	Assert(pVmcbCtrl->IntCtrl.n.u1VIrqPending);
242	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
243	}
244
245	pVmcbMemCtrl->IntCtrl.n.u8VTPR = pVmcbCtrl->IntCtrl.n.u8VTPR; /* V_TPR. */
246
247	if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx)) /* Interrupt shadow. */
248	pVmcbMemCtrl->IntShadow.n.u1IntShadow = 0;
249	else
250	{
251	pVmcbMemCtrl->IntShadow.n.u1IntShadow = 1;
252	LogFlow(("iemSvmVmexit: Interrupt shadow till %#RX64\n", pVCpu->cpum.GstCtx.rip));
253	CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
254	}
255
256	/*
257	* Save nRIP, instruction length and byte fields.
258	*/
259	pVmcbMemCtrl->u64NextRIP = pVmcbCtrl->u64NextRIP;
260	pVmcbMemCtrl->cbInstrFetched = pVmcbCtrl->cbInstrFetched;
261	memcpy(&pVmcbMemCtrl->abInstr[0], &pVmcbCtrl->abInstr[0], sizeof(pVmcbMemCtrl->abInstr));
262
263	/*
264	* Save exit information.
265	*/
266	pVmcbMemCtrl->u64ExitCode = uExitCode;
267	pVmcbMemCtrl->u64ExitInfo1 = uExitInfo1;
268	pVmcbMemCtrl->u64ExitInfo2 = uExitInfo2;
269
270	/*
271	* Update the exit interrupt-information field if this #VMEXIT happened as a result
272	* of delivering an event through IEM.
273	*
274	* Don't update the exit interrupt-information field if the event wasn't being injected
275	* through IEM, as it would have been updated by real hardware if the nested-guest was
276	* executed using hardware-assisted SVM.
277	*/
278	{
279	uint8_t uExitIntVector;
280	uint32_t uExitIntErr;
281	uint32_t fExitIntFlags;
282	bool const fRaisingEvent = IEMGetCurrentXcpt(pVCpu, &uExitIntVector, &fExitIntFlags, &uExitIntErr,
283	NULL /* uExitIntCr2 */);
284	if (fRaisingEvent)
285	{
286	pVmcbCtrl->ExitIntInfo.n.u1Valid = 1;
287	pVmcbCtrl->ExitIntInfo.n.u8Vector = uExitIntVector;
288	pVmcbCtrl->ExitIntInfo.n.u3Type = iemGetSvmEventType(uExitIntVector, fExitIntFlags);
289	if (fExitIntFlags & IEM_XCPT_FLAGS_ERR)
290	{
291	pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid = true;
292	pVmcbCtrl->ExitIntInfo.n.u32ErrorCode = uExitIntErr;
293	}
294	}
295	}
296
297	/*
298	* Save the exit interrupt-information field.
299	*
300	* We write the whole field including overwriting reserved bits as it was observed on an
301	* AMD Ryzen 5 Pro 1500 that the CPU does not preserve reserved bits in EXITINTINFO.
302	*/
303	pVmcbMemCtrl->ExitIntInfo = pVmcbCtrl->ExitIntInfo;
304
305	/*
306	* Clear event injection.
307	*/
308	pVmcbMemCtrl->EventInject.n.u1Valid = 0;
309
310	iemMemPageUnmap(pVCpu, pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, IEM_ACCESS_DATA_RW, pVmcbMem, &PgLockMem);
311	}
312
313	/*
314	* Prepare for guest's "host mode" by clearing internal processor state bits.
315	*
316	* We don't need to zero out the state-save area, just the controls should be
317	* sufficient because it has the critical bit of indicating whether we're inside
318	* the nested-guest or not.
319	*/
320	memset(pVmcbCtrl, 0, sizeof(*pVmcbCtrl));
321	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
322
323	/*
324	* Restore the subset of the inhibit flags that were preserved.
325	*/
326	pVCpu->cpum.GstCtx.eflags.uBoth \|= pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit;
327
328	if (rcStrict == VINF_SUCCESS)
329	{
330	/** @todo Nested paging. */
331	/** @todo ASID. */
332
333	/*
334	* If we are switching to PAE mode host, validate the PDPEs first.
335	* Any invalid PDPEs here causes a VCPU shutdown.
336	*/
337	PCSVMHOSTSTATE pHostState = &pVCpu->cpum.GstCtx.hwvirt.svm.HostState;
338	bool const fHostInPaeMode = CPUMIsPaePagingEnabled(pHostState->uCr0, pHostState->uCr4, pHostState->uEferMsr);
339	if (fHostInPaeMode)
340	rcStrict = PGMGstMapPaePdpesAtCr3(pVCpu, pHostState->uCr3);
341	if (RT_SUCCESS(rcStrict))
342	{
343	/*
344	* Reload the host state.
345	*/
346	CPUMSvmVmExitRestoreHostState(pVCpu, IEM_GET_CTX(pVCpu));
347
348	/*
349	* Update PGM, IEM and others of a world-switch.
350	*/
351	rcStrict = iemSvmWorldSwitch(pVCpu);
352	if (rcStrict == VINF_SUCCESS)
353	rcStrict = VINF_SVM_VMEXIT;
354	else if (RT_SUCCESS(rcStrict))
355	{
356	LogFlow(("iemSvmVmexit: Setting passup status from iemSvmWorldSwitch %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
357	iemSetPassUpStatus(pVCpu, rcStrict);
358	rcStrict = VINF_SVM_VMEXIT;
359	}
360	else
361	LogFlow(("iemSvmVmexit: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
362	}
363	else
364	{
365	Log(("iemSvmVmexit: PAE PDPEs invalid while restoring host state. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
366	rcStrict = VINF_EM_TRIPLE_FAULT;
367	}
368	}
369	else
370	{
371	AssertMsgFailed(("iemSvmVmexit: Mapping VMCB at %#RGp failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, VBOXSTRICTRC_VAL(rcStrict)));
372	rcStrict = VINF_EM_TRIPLE_FAULT;
373	}
374	}
375	else
376	{
377	AssertMsgFailed(("iemSvmVmexit: Not in SVM guest mode! uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uExitCode, uExitInfo1, uExitInfo2));
378	rcStrict = VERR_SVM_IPE_3;
379	}
380
381	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
382	/* CLGI/STGI may not have been intercepted and thus not executed in IEM. */
383	if ( HMIsEnabled(pVCpu->CTX_SUFF(pVM))
384	&& HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM)))
385	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
386	# endif
387	return rcStrict;
388	}
389
390
391	/**
392	* Interface for HM and EM to emulate \#VMEXIT.
393	*
394	* @returns Strict VBox status code.
395	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
396	* @param uExitCode The exit code.
397	* @param uExitInfo1 The exit info. 1 field.
398	* @param uExitInfo2 The exit info. 2 field.
399	* @thread EMT(pVCpu)
400	*/
401	VMM_INT_DECL(VBOXSTRICTRC) IEMExecSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2)
402	{
403	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK);
404	VBOXSTRICTRC rcStrict = iemSvmVmexit(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
405	if (pVCpu->iem.s.cActiveMappings)
406	iemMemRollback(pVCpu);
407	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
408	}
409
410
411	/**
412	* Performs the operations necessary that are part of the vmrun instruction
413	* execution in the guest.
414	*
415	* @returns Strict VBox status code (i.e. informational status codes too).
416	* @retval VINF_SUCCESS successfully executed VMRUN and entered nested-guest
417	* code execution.
418	* @retval VINF_SVM_VMEXIT when executing VMRUN causes a \#VMEXIT
419	* (SVM_EXIT_INVALID most likely).
420	*
421	* @param pVCpu The cross context virtual CPU structure.
422	* @param cbInstr The length of the VMRUN instruction.
423	* @param GCPhysVmcb Guest physical address of the VMCB to run.
424	*/
425	static VBOXSTRICTRC iemSvmVmrun(PVMCPUCC pVCpu, uint8_t cbInstr, RTGCPHYS GCPhysVmcb) RT_NOEXCEPT
426	{
427	LogFlow(("iemSvmVmrun\n"));
428
429	/*
430	* Cache the physical address of the VMCB for #VMEXIT exceptions.
431	*/
432	pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb = GCPhysVmcb;
433
434	/*
435	* Save the host state.
436	*/
437	CPUMSvmVmRunSaveHostState(IEM_GET_CTX(pVCpu), cbInstr);
438
439	/*
440	* Read the guest VMCB.
441	*/
442	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
443	int rc = PGMPhysSimpleReadGCPhys(pVM, &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb, GCPhysVmcb, sizeof(SVMVMCB));
444	if (RT_SUCCESS(rc))
445	{
446	/*
447	* AMD-V seems to preserve reserved fields and only writes back selected, recognized
448	* fields on #VMEXIT. However, not all reserved bits are preserved (e.g, EXITINTINFO)
449	* but in our implementation we try to preserve as much as we possibly can.
450	*
451	* We could read the entire page here and only write back the relevant fields on
452	* #VMEXIT but since our internal VMCB is also being used by HM during hardware-assisted
453	* SVM execution, it creates a potential for a nested-hypervisor to set bits that are
454	* currently reserved but may be recognized as features bits in future CPUs causing
455	* unexpected & undesired results. Hence, we zero out unrecognized fields here as we
456	* typically enter hardware-assisted SVM soon anyway, see @bugref{7243#c113}.
457	*/
458	PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
459	PSVMVMCBSTATESAVE pVmcbNstGst = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.guest;
460
461	RT_ZERO(pVmcbCtrl->u8Reserved0);
462	RT_ZERO(pVmcbCtrl->u8Reserved1);
463	RT_ZERO(pVmcbCtrl->u8Reserved2);
464	RT_ZERO(pVmcbNstGst->u8Reserved0);
465	RT_ZERO(pVmcbNstGst->u8Reserved1);
466	RT_ZERO(pVmcbNstGst->u8Reserved2);
467	RT_ZERO(pVmcbNstGst->u8Reserved3);
468	RT_ZERO(pVmcbNstGst->u8Reserved4);
469	RT_ZERO(pVmcbNstGst->u8Reserved5);
470	pVmcbCtrl->u32Reserved0 = 0;
471	pVmcbCtrl->TLBCtrl.n.u24Reserved = 0;
472	pVmcbCtrl->IntCtrl.n.u6Reserved = 0;
473	pVmcbCtrl->IntCtrl.n.u3Reserved = 0;
474	pVmcbCtrl->IntCtrl.n.u5Reserved = 0;
475	pVmcbCtrl->IntCtrl.n.u24Reserved = 0;
476	pVmcbCtrl->IntShadow.n.u30Reserved = 0;
477	pVmcbCtrl->ExitIntInfo.n.u19Reserved = 0;
478	pVmcbCtrl->NestedPagingCtrl.n.u29Reserved = 0;
479	pVmcbCtrl->EventInject.n.u19Reserved = 0;
480	pVmcbCtrl->LbrVirt.n.u30Reserved = 0;
481
482	/*
483	* Validate guest-state and controls.
484	*/
485	/* VMRUN must always be intercepted. */
486	if (!CPUMIsGuestSvmCtrlInterceptSet(pVCpu, IEM_GET_CTX(pVCpu), SVM_CTRL_INTERCEPT_VMRUN))
487	{
488	Log(("iemSvmVmrun: VMRUN instruction not intercepted -> #VMEXIT\n"));
489	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
490	}
491
492	/* Nested paging. */
493	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
494	&& !pVM->cpum.ro.GuestFeatures.fSvmNestedPaging)
495	{
496	Log(("iemSvmVmrun: Nested paging not supported -> Disabling\n"));
497	pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging = 0;
498	}
499
500	/* AVIC. */
501	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
502	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
503	{
504	Log(("iemSvmVmrun: AVIC not supported -> Disabling\n"));
505	pVmcbCtrl->IntCtrl.n.u1AvicEnable = 0;
506	}
507
508	/* Last branch record (LBR) virtualization. */
509	if ( pVmcbCtrl->LbrVirt.n.u1LbrVirt
510	&& !pVM->cpum.ro.GuestFeatures.fSvmLbrVirt)
511	{
512	Log(("iemSvmVmrun: LBR virtualization not supported -> Disabling\n"));
513	pVmcbCtrl->LbrVirt.n.u1LbrVirt = 0;
514	}
515
516	/* Virtualized VMSAVE/VMLOAD. */
517	if ( pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload
518	&& !pVM->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
519	{
520	Log(("iemSvmVmrun: Virtualized VMSAVE/VMLOAD not supported -> Disabling\n"));
521	pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload = 0;
522	}
523
524	/* Virtual GIF. */
525	if ( pVmcbCtrl->IntCtrl.n.u1VGifEnable
526	&& !pVM->cpum.ro.GuestFeatures.fSvmVGif)
527	{
528	Log(("iemSvmVmrun: Virtual GIF not supported -> Disabling\n"));
529	pVmcbCtrl->IntCtrl.n.u1VGifEnable = 0;
530	}
531
532	/* Guest ASID. */
533	if (!pVmcbCtrl->TLBCtrl.n.u32ASID)
534	{
535	Log(("iemSvmVmrun: Guest ASID is invalid -> #VMEXIT\n"));
536	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
537	}
538
539	/* Guest AVIC. */
540	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
541	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
542	{
543	Log(("iemSvmVmrun: AVIC not supported -> Disabling\n"));
544	pVmcbCtrl->IntCtrl.n.u1AvicEnable = 0;
545	}
546
547	/* Guest Secure Encrypted Virtualization. */
548	if ( ( pVmcbCtrl->NestedPagingCtrl.n.u1Sev
549	\|\| pVmcbCtrl->NestedPagingCtrl.n.u1SevEs)
550	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
551	{
552	Log(("iemSvmVmrun: SEV not supported -> Disabling\n"));
553	pVmcbCtrl->NestedPagingCtrl.n.u1Sev = 0;
554	pVmcbCtrl->NestedPagingCtrl.n.u1SevEs = 0;
555	}
556
557	/* Flush by ASID. */
558	if ( !pVM->cpum.ro.GuestFeatures.fSvmFlusbByAsid
559	&& pVmcbCtrl->TLBCtrl.n.u8TLBFlush != SVM_TLB_FLUSH_NOTHING
560	&& pVmcbCtrl->TLBCtrl.n.u8TLBFlush != SVM_TLB_FLUSH_ENTIRE)
561	{
562	Log(("iemSvmVmrun: Flush-by-ASID not supported -> #VMEXIT\n"));
563	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
564	}
565
566	/* IO permission bitmap. */
567	RTGCPHYS const GCPhysIOBitmap = pVmcbCtrl->u64IOPMPhysAddr;
568	if ( (GCPhysIOBitmap & X86_PAGE_4K_OFFSET_MASK)
569	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap)
570	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + X86_PAGE_4K_SIZE)
571	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + (X86_PAGE_4K_SIZE << 1)))
572	{
573	Log(("iemSvmVmrun: IO bitmap physaddr invalid. GCPhysIOBitmap=%#RX64 -> #VMEXIT\n", GCPhysIOBitmap));
574	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
575	}
576
577	/* MSR permission bitmap. */
578	RTGCPHYS const GCPhysMsrBitmap = pVmcbCtrl->u64MSRPMPhysAddr;
579	if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
580	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap)
581	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap + X86_PAGE_4K_SIZE))
582	{
583	Log(("iemSvmVmrun: MSR bitmap physaddr invalid. GCPhysMsrBitmap=%#RX64 -> #VMEXIT\n", GCPhysMsrBitmap));
584	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
585	}
586
587	/* CR0. */
588	if ( !(pVmcbNstGst->u64CR0 & X86_CR0_CD)
589	&& (pVmcbNstGst->u64CR0 & X86_CR0_NW))
590	{
591	Log(("iemSvmVmrun: CR0 no-write through with cache disabled. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
592	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
593	}
594	if (pVmcbNstGst->u64CR0 >> 32)
595	{
596	Log(("iemSvmVmrun: CR0 reserved bits set. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
597	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
598	}
599	/** @todo Implement all reserved bits/illegal combinations for CR3, CR4. */
600
601	/* DR6 and DR7. */
602	if ( pVmcbNstGst->u64DR6 >> 32
603	\|\| pVmcbNstGst->u64DR7 >> 32)
604	{
605	Log(("iemSvmVmrun: DR6 and/or DR7 reserved bits set. DR6=%#RX64 DR7=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64DR6,
606	pVmcbNstGst->u64DR6));
607	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
608	}
609
610	/*
611	* PAT (Page Attribute Table) MSR.
612	*
613	* The CPU only validates and loads it when nested-paging is enabled.
614	* See AMD spec. "15.25.4 Nested Paging and VMRUN/#VMEXIT".
615	*/
616	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
617	&& !CPUMIsPatMsrValid(pVmcbNstGst->u64PAT))
618	{
619	Log(("iemSvmVmrun: PAT invalid. u64PAT=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64PAT));
620	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
621	}
622
623	/*
624	* Copy the IO permission bitmap into the cache.
625	*/
626	AssertCompile(sizeof(pVCpu->cpum.GstCtx.hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_4K_SIZE);
627	rc = PGMPhysSimpleReadGCPhys(pVM, pVCpu->cpum.GstCtx.hwvirt.svm.abIoBitmap, GCPhysIOBitmap,
628	sizeof(pVCpu->cpum.GstCtx.hwvirt.svm.abIoBitmap));
629	if (RT_FAILURE(rc))
630	{
631	Log(("iemSvmVmrun: Failed reading the IO permission bitmap at %#RGp. rc=%Rrc\n", GCPhysIOBitmap, rc));
632	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
633	}
634
635	/*
636	* Copy the MSR permission bitmap into the cache.
637	*/
638	AssertCompile(sizeof(pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_4K_SIZE);
639	rc = PGMPhysSimpleReadGCPhys(pVM, pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap, GCPhysMsrBitmap,
640	sizeof(pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap));
641	if (RT_FAILURE(rc))
642	{
643	Log(("iemSvmVmrun: Failed reading the MSR permission bitmap at %#RGp. rc=%Rrc\n", GCPhysMsrBitmap, rc));
644	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
645	}
646
647	/*
648	* Copy segments from nested-guest VMCB state to the guest-CPU state.
649	*
650	* We do this here as we need to use the CS attributes and it's easier this way
651	* then using the VMCB format selectors. It doesn't really matter where we copy
652	* the state, we restore the guest-CPU context state on the \#VMEXIT anyway.
653	*/
654	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, ES, es);
655	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, CS, cs);
656	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, SS, ss);
657	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, DS, ds);
658
659	/** @todo Segment attribute overrides by VMRUN. */
660
661	/*
662	* CPL adjustments and overrides.
663	*
664	* SS.DPL is apparently the CPU's CPL, see comment in CPUMGetGuestCPL().
665	* We shall thus adjust both CS.DPL and SS.DPL here.
666	*/
667	pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = pVmcbNstGst->u8CPL;
668	if (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(pVCpu)))
669	pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = 3;
670	if (CPUMIsGuestInRealModeEx(IEM_GET_CTX(pVCpu)))
671	pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = 0;
672	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
673
674	/*
675	* Continue validating guest-state and controls.
676	*
677	* We pass CR0 as 0 to CPUMIsGuestEferMsrWriteValid() below to skip the illegal
678	* EFER.LME bit transition check. We pass the nested-guest's EFER as both the
679	* old and new EFER value to not have any guest EFER bits influence the new
680	* nested-guest EFER.
681	*/
682	uint64_t uValidEfer;
683	rc = CPUMIsGuestEferMsrWriteValid(pVM, 0 /* CR0 */, pVmcbNstGst->u64EFER, pVmcbNstGst->u64EFER, &uValidEfer);
684	if (RT_FAILURE(rc))
685	{
686	Log(("iemSvmVmrun: EFER invalid uOldEfer=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64EFER));
687	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
688	}
689
690	/* Validate paging and CPU mode bits. */
691	bool const fSvm = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
692	bool const fLongModeSupported = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
693	bool const fLongModeEnabled = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
694	bool const fPaging = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PG);
695	bool const fPae = RT_BOOL(pVmcbNstGst->u64CR4 & X86_CR4_PAE);
696	bool const fProtMode = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PE);
697	bool const fLongModeWithPaging = fLongModeEnabled && fPaging;
698	bool const fLongModeConformCS = pVCpu->cpum.GstCtx.cs.Attr.n.u1Long && pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig;
699	/* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
700	if (fLongModeWithPaging)
701	uValidEfer \|= MSR_K6_EFER_LMA;
702	bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME \| MSR_K6_EFER_LMA));
703	if ( !fSvm
704	\|\| (!fLongModeSupported && fLongModeActiveOrEnabled)
705	\|\| (fLongModeWithPaging && !fPae)
706	\|\| (fLongModeWithPaging && !fProtMode)
707	\|\| ( fLongModeEnabled
708	&& fPaging
709	&& fPae
710	&& fLongModeConformCS))
711	{
712	Log(("iemSvmVmrun: EFER invalid. uValidEfer=%#RX64 -> #VMEXIT\n", uValidEfer));
713	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
714	}
715
716	/*
717	* Preserve the required force-flags.
718	*
719	* We only preserve the force-flags that would affect the execution of the
720	* nested-guest (or the guest).
721	*
722	* - VMCPU_FF_BLOCK_NMIS needs to be preserved as it blocks NMI until the
723	* execution of a subsequent IRET instruction in the guest.
724	*
725	* The remaining FFs (e.g. timers) can stay in place so that we will be able to
726	* generate interrupts that should cause #VMEXITs for the nested-guest.
727	*
728	* VMRUN has implicit GIF (Global Interrupt Flag) handling, we don't need to
729	* preserve VMCPU_FF_INHIBIT_INTERRUPTS.
730	*/
731	pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_INHIBIT_NMI;
732	pVCpu->cpum.GstCtx.eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
733
734	/*
735	* Pause filter.
736	*/
737	if (pVM->cpum.ro.GuestFeatures.fSvmPauseFilter)
738	{
739	pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter = pVmcbCtrl->u16PauseFilterCount;
740	if (pVM->cpum.ro.GuestFeatures.fSvmPauseFilterThreshold)
741	pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold = pVmcbCtrl->u16PauseFilterCount;
742	}
743
744	/*
745	* Interrupt shadow.
746	*/
747	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
748	{
749	LogFlow(("iemSvmVmrun: setting interrupt shadow. inhibit PC=%#RX64\n", pVmcbNstGst->u64RIP));
750	/** @todo will this cause trouble if the nested-guest is 64-bit but the guest is 32-bit? */
751	CPUMSetInInterruptShadowEx(&pVCpu->cpum.GstCtx, pVmcbNstGst->u64RIP);
752	}
753
754	/*
755	* TLB flush control.
756	* Currently disabled since it's redundant as we unconditionally flush the TLB
757	* in iemSvmWorldSwitch() below.
758	*/
759	# if 0
760	/** @todo @bugref{7243}: ASID based PGM TLB flushes. */
761	if ( pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE
762	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
763	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
764	PGMFlushTLB(pVCpu, pVmcbNstGst->u64CR3, true /* fGlobal */);
765	# endif
766
767	/*
768	* Validate and map PAE PDPEs if the guest will be using PAE paging.
769	* Invalid PAE PDPEs here causes a #VMEXIT.
770	*/
771	if ( !pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
772	&& CPUMIsPaePagingEnabled(pVmcbNstGst->u64CR0, pVmcbNstGst->u64CR4, uValidEfer))
773	{
774	rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcbNstGst->u64CR3);
775	if (RT_SUCCESS(rc))
776	{ /* likely */ }
777	else
778	{
779	Log(("iemSvmVmrun: PAE PDPEs invalid -> #VMEXIT\n"));
780	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
781	}
782	}
783
784	/*
785	* Copy the remaining guest state from the VMCB to the guest-CPU context.
786	*/
787	pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcbNstGst->GDTR.u32Limit;
788	pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcbNstGst->GDTR.u64Base;
789	pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcbNstGst->IDTR.u32Limit;
790	pVCpu->cpum.GstCtx.idtr.pIdt = pVmcbNstGst->IDTR.u64Base;
791	CPUMSetGuestCR0(pVCpu, pVmcbNstGst->u64CR0);
792	CPUMSetGuestCR4(pVCpu, pVmcbNstGst->u64CR4);
793	pVCpu->cpum.GstCtx.cr3 = pVmcbNstGst->u64CR3;
794	pVCpu->cpum.GstCtx.cr2 = pVmcbNstGst->u64CR2;
795	pVCpu->cpum.GstCtx.dr[6] = pVmcbNstGst->u64DR6;
796	pVCpu->cpum.GstCtx.dr[7] = pVmcbNstGst->u64DR7;
797	pVCpu->cpum.GstCtx.rflags.u = pVmcbNstGst->u64RFlags;
798	pVCpu->cpum.GstCtx.rax = pVmcbNstGst->u64RAX;
799	pVCpu->cpum.GstCtx.rsp = pVmcbNstGst->u64RSP;
800	pVCpu->cpum.GstCtx.rip = pVmcbNstGst->u64RIP;
801	CPUMSetGuestEferMsrNoChecks(pVCpu, pVCpu->cpum.GstCtx.msrEFER, uValidEfer);
802	if (pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging)
803	pVCpu->cpum.GstCtx.msrPAT = pVmcbNstGst->u64PAT;
804
805	/* Mask DR6, DR7 bits mandatory set/clear bits. */
806	pVCpu->cpum.GstCtx.dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
807	pVCpu->cpum.GstCtx.dr[6] \|= X86_DR6_RA1_MASK;
808	pVCpu->cpum.GstCtx.dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
809	pVCpu->cpum.GstCtx.dr[7] \|= X86_DR7_RA1_MASK;
810
811	/*
812	* Check for pending virtual interrupts.
813	*/
814	if (pVmcbCtrl->IntCtrl.n.u1VIrqPending)
815	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
816	else
817	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
818
819	/*
820	* Update PGM, IEM and others of a world-switch.
821	*/
822	VBOXSTRICTRC rcStrict = iemSvmWorldSwitch(pVCpu);
823	if (rcStrict == VINF_SUCCESS)
824	{ /* likely */ }
825	else if (RT_SUCCESS(rcStrict))
826	{
827	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch returned %Rrc, setting passup status\n", VBOXSTRICTRC_VAL(rcStrict)));
828	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
829	}
830	else
831	{
832	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
833	return rcStrict;
834	}
835
836	/*
837	* Set the global-interrupt flag to allow interrupts in the guest.
838	*/
839	CPUMSetGuestGif(&pVCpu->cpum.GstCtx, true);
840
841	/*
842	* Event injection.
843	*/
844	PCSVMEVENT pEventInject = &pVmcbCtrl->EventInject;
845	pVCpu->cpum.GstCtx.hwvirt.svm.fInterceptEvents = !pEventInject->n.u1Valid;
846	if (pEventInject->n.u1Valid)
847	{
848	uint8_t const uVector = pEventInject->n.u8Vector;
849	TRPMEVENT const enmType = HMSvmEventToTrpmEventType(pEventInject, uVector);
850	uint16_t const uErrorCode = pEventInject->n.u1ErrorCodeValid ? pEventInject->n.u32ErrorCode : 0;
851
852	/* Validate vectors for hardware exceptions, see AMD spec. 15.20 "Event Injection". */
853	if (RT_UNLIKELY(enmType == TRPM_32BIT_HACK))
854	{
855	Log(("iemSvmVmrun: Invalid event type =%#x -> #VMEXIT\n", (uint8_t)pEventInject->n.u3Type));
856	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
857	}
858	if (pEventInject->n.u3Type == SVM_EVENT_EXCEPTION)
859	{
860	if ( uVector == X86_XCPT_NMI
861	\|\| uVector > X86_XCPT_LAST)
862	{
863	Log(("iemSvmVmrun: Invalid vector for hardware exception. uVector=%#x -> #VMEXIT\n", uVector));
864	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
865	}
866	if ( uVector == X86_XCPT_BR
867	&& CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
868	{
869	Log(("iemSvmVmrun: Cannot inject #BR when not in long mode -> #VMEXIT\n"));
870	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
871	}
872	/** @todo any others? */
873	}
874
875	/*
876	* Invalidate the exit interrupt-information field here. This field is fully updated
877	* on #VMEXIT as events other than the one below can also cause intercepts during
878	* their injection (e.g. exceptions).
879	*/
880	pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
881
882	/*
883	* Clear the event injection valid bit here. While the AMD spec. mentions that the CPU
884	* clears this bit from the VMCB unconditionally on #VMEXIT, internally the CPU could be
885	* clearing it at any time, most likely before/after injecting the event. Since VirtualBox
886	* doesn't have any virtual-CPU internal representation of this bit, we clear/update the
887	* VMCB here. This also has the added benefit that we avoid the risk of injecting the event
888	* twice if we fallback to executing the nested-guest using hardware-assisted SVM after
889	* injecting the event through IEM here.
890	*/
891	pVmcbCtrl->EventInject.n.u1Valid = 0;
892
893	/** @todo NRIP: Software interrupts can only be pushed properly if we support
894	* NRIP for the nested-guest to calculate the instruction length
895	* below. */
896	LogFlow(("iemSvmVmrun: Injecting event: %04x:%08RX64 vec=%#x type=%d uErr=%u cr2=%#RX64 cr3=%#RX64 efer=%#RX64\n",
897	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uVector, enmType, uErrorCode, pVCpu->cpum.GstCtx.cr2,
898	pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.msrEFER));
899
900	/*
901	* We shall not inject the event here right away. There may be paging mode related updates
902	* as a result of the world-switch above that are yet to be honored. Instead flag the event
903	* as pending for injection.
904	*/
905	TRPMAssertTrap(pVCpu, uVector, enmType);
906	if (pEventInject->n.u1ErrorCodeValid)
907	TRPMSetErrorCode(pVCpu, uErrorCode);
908	if ( enmType == TRPM_TRAP
909	&& uVector == X86_XCPT_PF)
910	TRPMSetFaultAddress(pVCpu, pVCpu->cpum.GstCtx.cr2);
911	}
912	else
913	LogFlow(("iemSvmVmrun: Entering nested-guest: %04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 efer=%#RX64 efl=%#x\n",
914	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3,
915	pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER, pVCpu->cpum.GstCtx.eflags.u));
916
917	LogFlow(("iemSvmVmrun: returns %d\n", VBOXSTRICTRC_VAL(rcStrict)));
918
919	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
920	/* If CLGI/STGI isn't intercepted we force IEM-only nested-guest execution here. */
921	if ( HMIsEnabled(pVM)
922	&& HMIsSvmVGifActive(pVM))
923	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
924	# endif
925
926	return rcStrict;
927	}
928
929	/* Shouldn't really happen as the caller should've validated the physical address already. */
930	Log(("iemSvmVmrun: Failed to read nested-guest VMCB at %#RGp (rc=%Rrc) -> #VMEXIT\n", GCPhysVmcb, rc));
931	return rc;
932	}
933
934
935	/**
936	* Checks if the event intercepts and performs the \#VMEXIT if the corresponding
937	* intercept is active.
938	*
939	* @returns Strict VBox status code.
940	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
941	* we're not executing a nested-guest.
942	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
943	* successfully.
944	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
945	* failed and a shutdown needs to be initiated for the guest.
946	*
947	* @returns VBox strict status code.
948	* @param pVCpu The cross context virtual CPU structure of the calling thread.
949	* @param u8Vector The interrupt or exception vector.
950	* @param fFlags The exception flags (see IEM_XCPT_FLAGS_XXX).
951	* @param uErr The error-code associated with the exception.
952	* @param uCr2 The CR2 value in case of a \#PF exception.
953	*/
954	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT
955	{
956	Assert(CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
957
958	/*
959	* Handle SVM exception and software interrupt intercepts, see AMD spec. 15.12 "Exception Intercepts".
960	*
961	* - NMI intercepts have their own exit code and do not cause SVM_EXIT_XCPT_2 #VMEXITs.
962	* - External interrupts and software interrupts (INTn instruction) do not check the exception intercepts
963	* even when they use a vector in the range 0 to 31.
964	* - ICEBP should not trigger #DB intercept, but its own intercept.
965	* - For #PF exceptions, its intercept is checked before CR2 is written by the exception.
966	*/
967	/* Check NMI intercept */
968	if ( u8Vector == X86_XCPT_NMI
969	&& (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
970	&& IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_NMI))
971	{
972	Log2(("iemHandleSvmNstGstEventIntercept: NMI intercept -> #VMEXIT\n"));
973	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_NMI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
974	}
975
976	/* Check ICEBP intercept. */
977	if ( (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
978	&& IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_ICEBP))
979	{
980	Log2(("iemHandleSvmNstGstEventIntercept: ICEBP intercept -> #VMEXIT\n"));
981	IEM_SVM_UPDATE_NRIP(pVCpu);
982	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_ICEBP, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
983	}
984
985	/* Check CPU exception intercepts. */
986	if ( (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
987	&& IEM_SVM_IS_XCPT_INTERCEPT_SET(pVCpu, u8Vector))
988	{
989	Assert(u8Vector <= X86_XCPT_LAST);
990	uint64_t const uExitInfo1 = fFlags & IEM_XCPT_FLAGS_ERR ? uErr : 0;
991	uint64_t const uExitInfo2 = fFlags & IEM_XCPT_FLAGS_CR2 ? uCr2 : 0;
992	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists
993	&& u8Vector == X86_XCPT_PF
994	&& !(uErr & X86_TRAP_PF_ID))
995	{
996	PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
997	# ifdef IEM_WITH_CODE_TLB
998	uint8_t const *pbInstrBuf = pVCpu->iem.s.pbInstrBuf;
999	uint8_t const cbInstrBuf = pVCpu->iem.s.cbInstrBuf;
1000	pVmcbCtrl->cbInstrFetched = RT_MIN(cbInstrBuf, SVM_CTRL_GUEST_INSTR_BYTES_MAX);
1001	if ( pbInstrBuf
1002	&& cbInstrBuf > 0)
1003	memcpy(&pVmcbCtrl->abInstr[0], pbInstrBuf, pVmcbCtrl->cbInstrFetched);
1004	# else
1005	uint8_t const cbOpcode = pVCpu->iem.s.cbOpcode;
1006	pVmcbCtrl->cbInstrFetched = RT_MIN(cbOpcode, SVM_CTRL_GUEST_INSTR_BYTES_MAX);
1007	if (cbOpcode > 0)
1008	memcpy(&pVmcbCtrl->abInstr[0], &pVCpu->iem.s.abOpcode[0], pVmcbCtrl->cbInstrFetched);
1009	# endif
1010	}
1011	if (u8Vector == X86_XCPT_BR)
1012	IEM_SVM_UPDATE_NRIP(pVCpu);
1013	Log2(("iemHandleSvmNstGstEventIntercept: Xcpt intercept u32InterceptXcpt=%#RX32 u8Vector=%#x "
1014	"uExitInfo1=%#RX64 uExitInfo2=%#RX64 -> #VMEXIT\n", pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl.u32InterceptXcpt,
1015	u8Vector, uExitInfo1, uExitInfo2));
1016	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_XCPT_0 + u8Vector, uExitInfo1, uExitInfo2);
1017	}
1018
1019	/* Check software interrupt (INTn) intercepts. */
1020	if ( (fFlags & ( IEM_XCPT_FLAGS_T_SOFT_INT
1021	\| IEM_XCPT_FLAGS_BP_INSTR
1022	\| IEM_XCPT_FLAGS_ICEBP_INSTR
1023	\| IEM_XCPT_FLAGS_OF_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
1024	&& IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INTN))
1025	{
1026	uint64_t const uExitInfo1 = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? u8Vector : 0;
1027	Log2(("iemHandleSvmNstGstEventIntercept: Software INT intercept (u8Vector=%#x) -> #VMEXIT\n", u8Vector));
1028	IEM_SVM_UPDATE_NRIP(pVCpu);
1029	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_SWINT, uExitInfo1, 0 /* uExitInfo2 */);
1030	}
1031
1032	return VINF_SVM_INTERCEPT_NOT_ACTIVE;
1033	}
1034
1035
1036	/**
1037	* Checks the SVM IO permission bitmap and performs the \#VMEXIT if the
1038	* corresponding intercept is active.
1039	*
1040	* @returns Strict VBox status code.
1041	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
1042	* we're not executing a nested-guest.
1043	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1044	* successfully.
1045	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1046	* failed and a shutdown needs to be initiated for the guest.
1047	*
1048	* @returns VBox strict status code.
1049	* @param pVCpu The cross context virtual CPU structure of the calling thread.
1050	* @param u16Port The IO port being accessed.
1051	* @param enmIoType The type of IO access.
1052	* @param cbReg The IO operand size in bytes.
1053	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
1054	* @param iEffSeg The effective segment number.
1055	* @param fRep Whether this is a repeating IO instruction (REP prefix).
1056	* @param fStrIo Whether this is a string IO instruction.
1057	* @param cbInstr The length of the IO instruction in bytes.
1058	*/
1059	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1060	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT
1061	{
1062	Assert(IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT));
1063	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
1064	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
1065
1066	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u)\n", u16Port, u16Port));
1067
1068	SVMIOIOEXITINFO IoExitInfo;
1069	bool const fIntercept = CPUMIsSvmIoInterceptSet(pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap, u16Port, enmIoType, cbReg,
1070	cAddrSizeBits, iEffSeg, fRep, fStrIo, &IoExitInfo);
1071	if (fIntercept)
1072	{
1073	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u) -> #VMEXIT\n", u16Port, u16Port));
1074	IEM_SVM_UPDATE_NRIP(pVCpu);
1075	return iemSvmVmexit(pVCpu, SVM_EXIT_IOIO, IoExitInfo.u, pVCpu->cpum.GstCtx.rip + cbInstr);
1076	}
1077
1078	/** @todo remove later (for debugging as VirtualBox always traps all IO
1079	* intercepts). */
1080	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
1081	return VINF_SVM_INTERCEPT_NOT_ACTIVE;
1082	}
1083
1084
1085	/**
1086	* Checks the SVM MSR permission bitmap and performs the \#VMEXIT if the
1087	* corresponding intercept is active.
1088	*
1089	* @returns Strict VBox status code.
1090	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the MSR permission bitmap does not
1091	* specify interception of the accessed MSR @a idMsr.
1092	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1093	* successfully.
1094	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1095	* failed and a shutdown needs to be initiated for the guest.
1096	*
1097	* @param pVCpu The cross context virtual CPU structure.
1098	* @param idMsr The MSR being accessed in the nested-guest.
1099	* @param fWrite Whether this is an MSR write access, @c false implies an
1100	* MSR read.
1101	* @param cbInstr The length of the MSR read/write instruction in bytes.
1102	*/
1103	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT
1104	{
1105	/*
1106	* Check if any MSRs are being intercepted.
1107	*/
1108	Assert(CPUMIsGuestSvmCtrlInterceptSet(pVCpu, IEM_GET_CTX(pVCpu), SVM_CTRL_INTERCEPT_MSR_PROT));
1109	Assert(CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
1110
1111	uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ;
1112
1113	/*
1114	* Get the byte and bit offset of the permission bits corresponding to the MSR.
1115	*/
1116	uint16_t offMsrpm;
1117	uint8_t uMsrpmBit;
1118	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
1119	if (RT_SUCCESS(rc))
1120	{
1121	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
1122	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1123	if (fWrite)
1124	++uMsrpmBit;
1125
1126	/*
1127	* Check if the bit is set, if so, trigger a #VMEXIT.
1128	*/
1129	if (pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap[offMsrpm] & RT_BIT(uMsrpmBit))
1130	{
1131	IEM_SVM_UPDATE_NRIP(pVCpu);
1132	return iemSvmVmexit(pVCpu, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1133	}
1134	}
1135	else
1136	{
1137	/*
1138	* This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (nested hypervisor) deal with it.
1139	*/
1140	Log(("iemSvmHandleMsrIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool -> #VMEXIT\n", idMsr, fWrite));
1141	return iemSvmVmexit(pVCpu, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1142	}
1143	return VINF_SVM_INTERCEPT_NOT_ACTIVE;
1144	}
1145
1146
1147
1148	/**
1149	* Implements 'VMRUN'.
1150	*/
1151	IEM_CIMPL_DEF_0(iemCImpl_vmrun)
1152	{
1153	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1154	RT_NOREF2(pVCpu, cbInstr);
1155	return VINF_EM_RAW_EMULATE_INSTR;
1156	# else
1157	LogFlow(("iemCImpl_vmrun\n"));
1158	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmrun);
1159
1160	/** @todo Check effective address size using address size prefix. */
1161	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1162	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1163	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1164	{
1165	Log(("vmrun: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1166	return iemRaiseGeneralProtectionFault0(pVCpu);
1167	}
1168
1169	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
1170	{
1171	Log(("vmrun: Guest intercept -> #VMEXIT\n"));
1172	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_VMRUN, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1173	}
1174
1175	VBOXSTRICTRC rcStrict = iemSvmVmrun(pVCpu, cbInstr, GCPhysVmcb);
1176	if (rcStrict == VERR_SVM_VMEXIT_FAILED)
1177	{
1178	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
1179	rcStrict = VINF_EM_TRIPLE_FAULT;
1180	}
1181	return rcStrict;
1182	# endif
1183	}
1184
1185
1186	/**
1187	* Interface for HM and EM to emulate the VMRUN instruction.
1188	*
1189	* @returns Strict VBox status code.
1190	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1191	* @param cbInstr The instruction length in bytes.
1192	* @thread EMT(pVCpu)
1193	*/
1194	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmrun(PVMCPUCC pVCpu, uint8_t cbInstr)
1195	{
1196	IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
1197	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_SVM_VMRUN_MASK);
1198
1199	iemInitExec(pVCpu, false /fBypassHandlers/);
1200	VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmrun);
1201	Assert(!pVCpu->iem.s.cActiveMappings);
1202	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
1203	}
1204
1205
1206	/**
1207	* Implements 'VMLOAD'.
1208	*/
1209	IEM_CIMPL_DEF_0(iemCImpl_vmload)
1210	{
1211	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1212	RT_NOREF2(pVCpu, cbInstr);
1213	return VINF_EM_RAW_EMULATE_INSTR;
1214	# else
1215	LogFlow(("iemCImpl_vmload\n"));
1216	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmload);
1217
1218	/** @todo Check effective address size using address size prefix. */
1219	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1220	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1221	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1222	{
1223	Log(("vmload: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1224	return iemRaiseGeneralProtectionFault0(pVCpu);
1225	}
1226
1227	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
1228	{
1229	Log(("vmload: Guest intercept -> #VMEXIT\n"));
1230	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_VMLOAD, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1231	}
1232
1233	SVMVMCBSTATESAVE VmcbNstGst;
1234	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_UOFFSETOF(SVMVMCB, guest),
1235	sizeof(SVMVMCBSTATESAVE));
1236	if (rcStrict == VINF_SUCCESS)
1237	{
1238	LogFlow(("vmload: Loading VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1239	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, FS, fs);
1240	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, GS, gs);
1241	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, TR, tr);
1242	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, LDTR, ldtr);
1243
1244	pVCpu->cpum.GstCtx.msrKERNELGSBASE = VmcbNstGst.u64KernelGSBase;
1245	pVCpu->cpum.GstCtx.msrSTAR = VmcbNstGst.u64STAR;
1246	pVCpu->cpum.GstCtx.msrLSTAR = VmcbNstGst.u64LSTAR;
1247	pVCpu->cpum.GstCtx.msrCSTAR = VmcbNstGst.u64CSTAR;
1248	pVCpu->cpum.GstCtx.msrSFMASK = VmcbNstGst.u64SFMASK;
1249
1250	pVCpu->cpum.GstCtx.SysEnter.cs = VmcbNstGst.u64SysEnterCS;
1251	pVCpu->cpum.GstCtx.SysEnter.esp = VmcbNstGst.u64SysEnterESP;
1252	pVCpu->cpum.GstCtx.SysEnter.eip = VmcbNstGst.u64SysEnterEIP;
1253
1254	rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1255	}
1256	return rcStrict;
1257	# endif
1258	}
1259
1260
1261	/**
1262	* Interface for HM and EM to emulate the VMLOAD instruction.
1263	*
1264	* @returns Strict VBox status code.
1265	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1266	* @param cbInstr The instruction length in bytes.
1267	* @thread EMT(pVCpu)
1268	*/
1269	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmload(PVMCPUCC pVCpu, uint8_t cbInstr)
1270	{
1271	IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
1272
1273	iemInitExec(pVCpu, false /fBypassHandlers/);
1274	VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmload);
1275	Assert(!pVCpu->iem.s.cActiveMappings);
1276	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
1277	}
1278
1279
1280	/**
1281	* Implements 'VMSAVE'.
1282	*/
1283	IEM_CIMPL_DEF_0(iemCImpl_vmsave)
1284	{
1285	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1286	RT_NOREF2(pVCpu, cbInstr);
1287	return VINF_EM_RAW_EMULATE_INSTR;
1288	# else
1289	LogFlow(("iemCImpl_vmsave\n"));
1290	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmsave);
1291
1292	/** @todo Check effective address size using address size prefix. */
1293	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1294	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1295	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1296	{
1297	Log(("vmsave: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1298	return iemRaiseGeneralProtectionFault0(pVCpu);
1299	}
1300
1301	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
1302	{
1303	Log(("vmsave: Guest intercept -> #VMEXIT\n"));
1304	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_VMSAVE, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1305	}
1306
1307	SVMVMCBSTATESAVE VmcbNstGst;
1308	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_UOFFSETOF(SVMVMCB, guest),
1309	sizeof(SVMVMCBSTATESAVE));
1310	if (rcStrict == VINF_SUCCESS)
1311	{
1312	LogFlow(("vmsave: Saving VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1313	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR
1314	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \| CPUMCTX_EXTRN_SYSENTER_MSRS);
1315
1316	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, FS, fs);
1317	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, GS, gs);
1318	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, TR, tr);
1319	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, LDTR, ldtr);
1320
1321	VmcbNstGst.u64KernelGSBase = pVCpu->cpum.GstCtx.msrKERNELGSBASE;
1322	VmcbNstGst.u64STAR = pVCpu->cpum.GstCtx.msrSTAR;
1323	VmcbNstGst.u64LSTAR = pVCpu->cpum.GstCtx.msrLSTAR;
1324	VmcbNstGst.u64CSTAR = pVCpu->cpum.GstCtx.msrCSTAR;
1325	VmcbNstGst.u64SFMASK = pVCpu->cpum.GstCtx.msrSFMASK;
1326
1327	VmcbNstGst.u64SysEnterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1328	VmcbNstGst.u64SysEnterESP = pVCpu->cpum.GstCtx.SysEnter.esp;
1329	VmcbNstGst.u64SysEnterEIP = pVCpu->cpum.GstCtx.SysEnter.eip;
1330
1331	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcb + RT_UOFFSETOF(SVMVMCB, guest), &VmcbNstGst,
1332	sizeof(SVMVMCBSTATESAVE));
1333	if (rcStrict == VINF_SUCCESS)
1334	rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1335	}
1336	return rcStrict;
1337	# endif
1338	}
1339
1340
1341	/**
1342	* Interface for HM and EM to emulate the VMSAVE instruction.
1343	*
1344	* @returns Strict VBox status code.
1345	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1346	* @param cbInstr The instruction length in bytes.
1347	* @thread EMT(pVCpu)
1348	*/
1349	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmsave(PVMCPUCC pVCpu, uint8_t cbInstr)
1350	{
1351	IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
1352
1353	iemInitExec(pVCpu, false /fBypassHandlers/);
1354	VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmsave);
1355	Assert(!pVCpu->iem.s.cActiveMappings);
1356	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
1357	}
1358
1359
1360	/**
1361	* Implements 'CLGI'.
1362	*/
1363	IEM_CIMPL_DEF_0(iemCImpl_clgi)
1364	{
1365	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1366	RT_NOREF2(pVCpu, cbInstr);
1367	return VINF_EM_RAW_EMULATE_INSTR;
1368	# else
1369	LogFlow(("iemCImpl_clgi\n"));
1370	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, clgi);
1371	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
1372	{
1373	Log(("clgi: Guest intercept -> #VMEXIT\n"));
1374	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_CLGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1375	}
1376
1377	CPUMSetGuestGif(&pVCpu->cpum.GstCtx, false);
1378
1379	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1380	iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1381	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
1382	# else
1383	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1384	# endif
1385	# endif
1386	}
1387
1388
1389	/**
1390	* Interface for HM and EM to emulate the CLGI instruction.
1391	*
1392	* @returns Strict VBox status code.
1393	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1394	* @param cbInstr The instruction length in bytes.
1395	* @thread EMT(pVCpu)
1396	*/
1397	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClgi(PVMCPUCC pVCpu, uint8_t cbInstr)
1398	{
1399	IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
1400
1401	iemInitExec(pVCpu, false /fBypassHandlers/);
1402	VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_clgi);
1403	Assert(!pVCpu->iem.s.cActiveMappings);
1404	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
1405	}
1406
1407
1408	/**
1409	* Implements 'STGI'.
1410	*/
1411	IEM_CIMPL_DEF_0(iemCImpl_stgi)
1412	{
1413	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1414	RT_NOREF2(pVCpu, cbInstr);
1415	return VINF_EM_RAW_EMULATE_INSTR;
1416	# else
1417	LogFlow(("iemCImpl_stgi\n"));
1418	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, stgi);
1419	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_STGI))
1420	{
1421	Log2(("stgi: Guest intercept -> #VMEXIT\n"));
1422	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_STGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1423	}
1424
1425	CPUMSetGuestGif(&pVCpu->cpum.GstCtx, true);
1426
1427	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1428	iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1429	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
1430	# else
1431	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1432	# endif
1433	# endif
1434	}
1435
1436
1437	/**
1438	* Interface for HM and EM to emulate the STGI instruction.
1439	*
1440	* @returns Strict VBox status code.
1441	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1442	* @param cbInstr The instruction length in bytes.
1443	* @thread EMT(pVCpu)
1444	*/
1445	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedStgi(PVMCPUCC pVCpu, uint8_t cbInstr)
1446	{
1447	IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
1448
1449	iemInitExec(pVCpu, false /fBypassHandlers/);
1450	VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_stgi);
1451	Assert(!pVCpu->iem.s.cActiveMappings);
1452	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
1453	}
1454
1455
1456	/**
1457	* Implements 'INVLPGA'.
1458	*/
1459	IEM_CIMPL_DEF_0(iemCImpl_invlpga)
1460	{
1461	/** @todo Check effective address size using address size prefix. */
1462	RTGCPTR const GCPtrPage = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1463	/** @todo PGM needs virtual ASID support. */
1464	# if 0
1465	uint32_t const uAsid = pVCpu->cpum.GstCtx.ecx;
1466	# endif
1467
1468	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1469	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
1470	{
1471	Log2(("invlpga: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
1472	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_INVLPGA, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1473	}
1474
1475	PGMInvalidatePage(pVCpu, GCPtrPage);
1476	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1477	}
1478
1479
1480	/**
1481	* Interface for HM and EM to emulate the INVLPGA instruction.
1482	*
1483	* @returns Strict VBox status code.
1484	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1485	* @param cbInstr The instruction length in bytes.
1486	* @thread EMT(pVCpu)
1487	*/
1488	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpga(PVMCPUCC pVCpu, uint8_t cbInstr)
1489	{
1490	IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
1491
1492	iemInitExec(pVCpu, false /fBypassHandlers/);
1493	VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_invlpga);
1494	Assert(!pVCpu->iem.s.cActiveMappings);
1495	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
1496	}
1497
1498
1499	/**
1500	* Implements 'SKINIT'.
1501	*/
1502	IEM_CIMPL_DEF_0(iemCImpl_skinit)
1503	{
1504	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1505
1506	uint32_t uIgnore;
1507	uint32_t fFeaturesECX;
1508	CPUMGetGuestCpuId(pVCpu, 0x80000001, 0 /* iSubLeaf /, -1 /f64BitMode*/, &uIgnore, &uIgnore, &fFeaturesECX, &uIgnore);
1509	if (!(fFeaturesECX & X86_CPUID_AMD_FEATURE_ECX_SKINIT))
1510	return iemRaiseUndefinedOpcode(pVCpu);
1511
1512	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
1513	{
1514	Log2(("skinit: Guest intercept -> #VMEXIT\n"));
1515	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_SKINIT, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1516	}
1517
1518	RT_NOREF(cbInstr);
1519	return VERR_IEM_INSTR_NOT_IMPLEMENTED;
1520	}
1521
1522
1523	/**
1524	* Implements SVM's implementation of PAUSE.
1525	*/
1526	IEM_CIMPL_DEF_0(iemCImpl_svm_pause)
1527	{
1528	bool fCheckIntercept = true;
1529	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmPauseFilter)
1530	{
1531	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1532
1533	/* TSC based pause-filter thresholding. */
1534	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmPauseFilterThreshold
1535	&& pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold > 0)
1536	{
1537	uint64_t const uTick = TMCpuTickGet(pVCpu);
1538	if (uTick - pVCpu->cpum.GstCtx.hwvirt.svm.uPrevPauseTick > pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold)
1539	pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter = CPUMGetGuestSvmPauseFilterCount(pVCpu, IEM_GET_CTX(pVCpu));
1540	pVCpu->cpum.GstCtx.hwvirt.svm.uPrevPauseTick = uTick;
1541	}
1542
1543	/* Simple pause-filter counter. */
1544	if (pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter > 0)
1545	{
1546	--pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter;
1547	fCheckIntercept = false;
1548	}
1549	}
1550
1551	if (fCheckIntercept)
1552	IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_PAUSE, SVM_EXIT_PAUSE, 0, 0);
1553
1554	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1555	}
1556
1557	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
1558
1559	/**
1560	* Common code for iemCImpl_vmmcall and iemCImpl_vmcall (latter in IEMAllCImplVmxInstr.cpp.h).
1561	*/
1562	IEM_CIMPL_DEF_1(iemCImpl_Hypercall, uint16_t, uDisOpcode)
1563	{
1564	if (EMAreHypercallInstructionsEnabled(pVCpu))
1565	{
1566	NOREF(uDisOpcode);
1567	VBOXSTRICTRC rcStrict = GIMHypercallEx(pVCpu, IEM_GET_CTX(pVCpu), uDisOpcode, cbInstr);
1568	if (RT_SUCCESS(rcStrict))
1569	{
1570	/** @todo finish: Sort out assertion here when iemRegAddToRipAndFinishingClearingRF
1571	* starts returning non-VINF_SUCCESS statuses. */
1572	if (rcStrict == VINF_SUCCESS)
1573	rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
1574	if ( rcStrict == VINF_SUCCESS
1575	\|\| rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
1576	return VINF_SUCCESS;
1577	AssertMsgReturn(rcStrict == VINF_GIM_R3_HYPERCALL, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IEM_IPE_4);
1578	return rcStrict;
1579	}
1580	AssertMsgReturn( rcStrict == VERR_GIM_HYPERCALL_ACCESS_DENIED
1581	\|\| rcStrict == VERR_GIM_HYPERCALLS_NOT_AVAILABLE
1582	\|\| rcStrict == VERR_GIM_NOT_ENABLED
1583	\|\| rcStrict == VERR_GIM_HYPERCALL_MEMORY_READ_FAILED
1584	\|\| rcStrict == VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED,
1585	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IEM_IPE_4);
1586
1587	/* Raise #UD on all failures. */
1588	}
1589	return iemRaiseUndefinedOpcode(pVCpu);
1590	}
1591
1592
1593	/**
1594	* Implements 'VMMCALL'.
1595	*/
1596	IEM_CIMPL_DEF_0(iemCImpl_vmmcall)
1597	{
1598	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
1599	{
1600	Log(("vmmcall: Guest intercept -> #VMEXIT\n"));
1601	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_VMMCALL, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1602	}
1603
1604	/* This is a little bit more complicated than the VT-x version because HM/SVM may
1605	patch MOV CR8 instructions to speed up APIC.TPR access for 32-bit windows guests. */
1606	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1607	if (VM_IS_HM_ENABLED(pVM))
1608	{
1609	int rc = HMHCMaybeMovTprSvmHypercall(pVM, pVCpu);
1610	if (RT_SUCCESS(rc))
1611	{
1612	Log(("vmmcall: MovTpr\n"));
1613	return VINF_SUCCESS;
1614	}
1615	}
1616
1617	/* Join forces with vmcall. */
1618	return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMMCALL);
1619	}
1620

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp@ 97370

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