IEMAllCImplSvmInstr.cpp.h@ 69120

Last change on this file since 69120 was 69111, checked in by vboxsync, 7 years ago
(C) year
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 56.3 KB

Line
1	/* $Id: IEMAllCImplSvmInstr.cpp.h 69111 2017-10-17 14:26:02Z vboxsync $ */
2	/** @file
3	* IEM - AMD-V (Secure Virtual Machine) instruction implementation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/**
20	* Converts an IEM exception event type to an SVM event type.
21	*
22	* @returns The SVM event type.
23	* @retval UINT8_MAX if the specified type of event isn't among the set
24	* of recognized IEM event types.
25	*
26	* @param uVector The vector of the event.
27	* @param fIemXcptFlags The IEM exception / interrupt flags.
28	*/
29	IEM_STATIC uint8_t iemGetSvmEventType(uint32_t uVector, uint32_t fIemXcptFlags)
30	{
31	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
32	{
33	if (uVector != X86_XCPT_NMI)
34	return SVM_EVENT_EXCEPTION;
35	return SVM_EVENT_NMI;
36	}
37
38	/* See AMD spec. Table 15-1. "Guest Exception or Interrupt Types". */
39	if (fIemXcptFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
40	return SVM_EVENT_EXCEPTION;
41
42	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_EXT_INT)
43	return SVM_EVENT_EXTERNAL_IRQ;
44
45	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
46	return SVM_EVENT_SOFTWARE_INT;
47
48	AssertMsgFailed(("iemGetSvmEventType: Invalid IEM xcpt/int. type %#x, uVector=%#x\n", fIemXcptFlags, uVector));
49	return UINT8_MAX;
50	}
51
52
53	/**
54	* Performs an SVM world-switch (VMRUN, \#VMEXIT) updating PGM and IEM internals.
55	*
56	* @returns Strict VBox status code.
57	* @param pVCpu The cross context virtual CPU structure.
58	* @param pCtx The guest-CPU context.
59	*/
60	DECLINLINE(VBOXSTRICTRC) iemSvmWorldSwitch(PVMCPU pVCpu, PCPUMCTX pCtx)
61	{
62	/*
63	* Flush the TLB with new CR3. This is required in case the PGM mode change
64	* below doesn't actually change anything.
65	*/
66	PGMFlushTLB(pVCpu, pCtx->cr3, true);
67
68	/*
69	* Inform PGM about paging mode changes.
70	* We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
71	* see comment in iemMemPageTranslateAndCheckAccess().
72	*/
73	int rc = PGMChangeMode(pVCpu, pCtx->cr0 \| X86_CR0_PE, pCtx->cr4, pCtx->msrEFER);
74	AssertRCReturn(rc, rc);
75
76	/* Inform CPUM (recompiler), can later be removed. */
77	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
78
79	/* Re-initialize IEM cache/state after the drastic mode switch. */
80	iemReInitExec(pVCpu);
81	return rc;
82	}
83
84
85	/**
86	* SVM \#VMEXIT handler.
87	*
88	* @returns Strict VBox status code.
89	* @retval VINF_SVM_VMEXIT when the \#VMEXIT is successful.
90	* @retval VERR_SVM_VMEXIT_FAILED when the \#VMEXIT failed restoring the guest's
91	* "host state" and a shutdown is required.
92	*
93	* @param pVCpu The cross context virtual CPU structure.
94	* @param pCtx The guest-CPU context.
95	* @param uExitCode The exit code.
96	* @param uExitInfo1 The exit info. 1 field.
97	* @param uExitInfo2 The exit info. 2 field.
98	*/
99	IEM_STATIC VBOXSTRICTRC iemSvmVmexit(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2)
100	{
101	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
102	\|\| uExitCode == SVM_EXIT_INVALID)
103	{
104	LogFlow(("iemSvmVmexit: CS:RIP=%04x:%08RX64 uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pCtx->cs.Sel,
105	pCtx->rip, uExitCode, uExitInfo1, uExitInfo2));
106
107	/*
108	* Disable the global interrupt flag to prevent interrupts during the 'atomic' world switch.
109	*/
110	pCtx->hwvirt.svm.fGif = false;
111
112	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->es));
113	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
114	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
115	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ds));
116
117	/*
118	* Save the nested-guest state into the VMCB state-save area.
119	*/
120	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
121	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
122	PSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
123
124	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, ES, es);
125	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, CS, cs);
126	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, SS, ss);
127	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, DS, ds);
128	pVmcbNstGstState->GDTR.u32Limit = pCtx->gdtr.cbGdt;
129	pVmcbNstGstState->GDTR.u64Base = pCtx->gdtr.pGdt;
130	pVmcbNstGstState->IDTR.u32Limit = pCtx->idtr.cbIdt;
131	pVmcbNstGstState->IDTR.u64Base = pCtx->idtr.pIdt;
132	pVmcbNstGstState->u64EFER = pCtx->msrEFER;
133	pVmcbNstGstState->u64CR4 = pCtx->cr4;
134	pVmcbNstGstState->u64CR3 = pCtx->cr3;
135	pVmcbNstGstState->u64CR2 = pCtx->cr2;
136	pVmcbNstGstState->u64CR0 = pCtx->cr0;
137	/** @todo Nested paging. */
138	pVmcbNstGstState->u64RFlags = pCtx->rflags.u64;
139	pVmcbNstGstState->u64RIP = pCtx->rip;
140	pVmcbNstGstState->u64RSP = pCtx->rsp;
141	pVmcbNstGstState->u64RAX = pCtx->rax;
142	pVmcbNstGstState->u64DR7 = pCtx->dr[7];
143	pVmcbNstGstState->u64DR6 = pCtx->dr[6];
144	pVmcbNstGstState->u8CPL = pCtx->ss.Attr.n.u2Dpl; /* See comment in CPUMGetGuestCPL(). */
145	Assert(CPUMGetGuestCPL(pVCpu) == pCtx->ss.Attr.n.u2Dpl);
146
147	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
148	/* Save interrupt shadow of the nested-guest instruction if any. */
149	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
150	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
151	{
152	LogFlow(("iemSvmVmexit: Interrupt shadow till %#RX64\n", pCtx->rip));
153	pVmcbCtrl->u64IntShadow \|= SVM_INTERRUPT_SHADOW_ACTIVE;
154	}
155
156	/*
157	* Save additional state and intercept information.
158	*/
159	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
160	{
161	Assert(pVmcbCtrl->IntCtrl.n.u1VIrqPending);
162	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
163	}
164	else
165	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
166
167	/** @todo Save V_TPR, V_IRQ. */
168	/** @todo NRIP. */
169
170	/* Save exit information. */
171	pVmcbCtrl->u64ExitCode = uExitCode;
172	pVmcbCtrl->u64ExitInfo1 = uExitInfo1;
173	pVmcbCtrl->u64ExitInfo2 = uExitInfo2;
174
175	/*
176	* Update the exit interrupt information field if this #VMEXIT happened as a result
177	* of delivering an event.
178	*/
179	{
180	uint8_t uExitIntVector;
181	uint32_t uExitIntErr;
182	uint32_t fExitIntFlags;
183	bool const fRaisingEvent = IEMGetCurrentXcpt(pVCpu, &uExitIntVector, &fExitIntFlags, &uExitIntErr,
184	NULL /* uExitIntCr2 */);
185	pVmcbCtrl->ExitIntInfo.n.u1Valid = fRaisingEvent;
186	if (fRaisingEvent)
187	{
188	pVmcbCtrl->ExitIntInfo.n.u8Vector = uExitIntVector;
189	pVmcbCtrl->ExitIntInfo.n.u3Type = iemGetSvmEventType(uExitIntVector, fExitIntFlags);
190	if (fExitIntFlags & IEM_XCPT_FLAGS_ERR)
191	{
192	pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid = true;
193	pVmcbCtrl->ExitIntInfo.n.u32ErrorCode = uExitIntErr;
194	}
195	}
196	}
197
198	/*
199	* Clear event injection in the VMCB.
200	*/
201	pVmcbCtrl->EventInject.n.u1Valid = 0;
202
203	/*
204	* Notify HM in case the VMRUN was executed using SVM R0, HM would have modified some VMCB
205	* state that we need to restore on #VMEXIT before writing it back to guest memory.
206	*/
207	HMSvmNstGstVmExitNotify(pVCpu, pVmcbNstGst);
208
209	/*
210	* Write back the nested-guest's VMCB to its guest physical memory location.
211	*/
212	VBOXSTRICTRC rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->hwvirt.svm.GCPhysVmcb, pVmcbNstGst,
213	sizeof(*pVmcbNstGst));
214	/*
215	* Prepare for guest's "host mode" by clearing internal processor state bits.
216	*
217	* We don't need to zero out the state-save area, just the controls should be
218	* sufficient because it has the critical bit of indicating whether we're inside
219	* the nested-guest or not.
220	*/
221	memset(pVmcbNstGstCtrl, 0, sizeof(*pVmcbNstGstCtrl));
222	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
223
224	/*
225	* Restore the subset of force-flags that were preserved.
226	*/
227	if (pCtx->hwvirt.fLocalForcedActions)
228	{
229	VMCPU_FF_SET(pVCpu, pCtx->hwvirt.fLocalForcedActions);
230	pCtx->hwvirt.fLocalForcedActions = 0;
231	}
232
233	if (RT_SUCCESS(rcStrict))
234	{
235	/** @todo Nested paging. */
236	/** @todo ASID. */
237
238	/*
239	* Reload the guest's "host state".
240	*/
241	CPUMSvmVmExitRestoreHostState(pCtx);
242
243	/*
244	* Update PGM, IEM and others of a world-switch.
245	*/
246	rcStrict = iemSvmWorldSwitch(pVCpu, pCtx);
247	if (rcStrict == VINF_SUCCESS)
248	return VINF_SVM_VMEXIT;
249
250	if (RT_SUCCESS(rcStrict))
251	{
252	LogFlow(("iemSvmVmexit: Setting passup status from iemSvmWorldSwitch %Rrc\n", rcStrict));
253	iemSetPassUpStatus(pVCpu, rcStrict);
254	return VINF_SVM_VMEXIT;
255	}
256
257	LogFlow(("iemSvmVmexit: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
258	}
259	else
260	LogFlow(("iemSvmVmexit: Writing VMCB at %#RGp failed. rc=%Rrc\n", pCtx->hwvirt.svm.GCPhysVmcb,
261	VBOXSTRICTRC_VAL(rcStrict)));
262
263	return VERR_SVM_VMEXIT_FAILED;
264	}
265
266	Log(("iemSvmVmexit: Not in SVM guest mode! uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uExitCode,
267	uExitInfo1, uExitInfo2));
268	AssertMsgFailed(("iemSvmVmexit: Unexpected SVM-exit failure uExitCode=%#RX64\n", uExitCode));
269	return VERR_SVM_IPE_5;
270	}
271
272
273	/**
274	* Performs the operations necessary that are part of the vmrun instruction
275	* execution in the guest.
276	*
277	* @returns Strict VBox status code (i.e. informational status codes too).
278	* @retval VINF_SUCCESS successully executed VMRUN and entered nested-guest
279	* code execution.
280	* @retval VINF_SVM_VMEXIT when executing VMRUN causes a \#VMEXIT
281	* (SVM_EXIT_INVALID most likely).
282	*
283	* @param pVCpu The cross context virtual CPU structure.
284	* @param pCtx Pointer to the guest-CPU context.
285	* @param cbInstr The length of the VMRUN instruction.
286	* @param GCPhysVmcb Guest physical address of the VMCB to run.
287	*/
288	IEM_STATIC VBOXSTRICTRC iemSvmVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr, RTGCPHYS GCPhysVmcb)
289	{
290	PVM pVM = pVCpu->CTX_SUFF(pVM);
291	LogFlow(("iemSvmVmrun\n"));
292
293	/*
294	* Cache the physical address of the VMCB for #VMEXIT exceptions.
295	*/
296	pCtx->hwvirt.svm.GCPhysVmcb = GCPhysVmcb;
297
298	/*
299	* Save the host state.
300	*/
301	CPUMSvmVmRunSaveHostState(pCtx, cbInstr);
302
303	/*
304	* Read the guest VMCB state.
305	*/
306	int rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pVmcb), GCPhysVmcb, sizeof(SVMVMCB));
307	if (RT_SUCCESS(rc))
308	{
309	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
310	PSVMVMCBSTATESAVE pVmcbNstGst = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->guest;
311
312	/*
313	* Validate guest-state and controls.
314	*/
315	/* VMRUN must always be intercepted. */
316	if (!CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_VMRUN))
317	{
318	Log(("iemSvmVmrun: VMRUN instruction not intercepted -> #VMEXIT\n"));
319	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
320	}
321
322	/* Nested paging. */
323	if ( pVmcbCtrl->NestedPaging.n.u1NestedPaging
324	&& !pVM->cpum.ro.GuestFeatures.fSvmNestedPaging)
325	{
326	Log(("iemSvmVmrun: Nested paging not supported -> #VMEXIT\n"));
327	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
328	}
329
330	/* AVIC. */
331	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
332	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
333	{
334	Log(("iemSvmVmrun: AVIC not supported -> #VMEXIT\n"));
335	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
336	}
337
338	/* Last branch record (LBR) virtualization. */
339	if ( (pVmcbCtrl->u64LBRVirt & SVM_LBR_VIRT_ENABLE)
340	&& !pVM->cpum.ro.GuestFeatures.fSvmLbrVirt)
341	{
342	Log(("iemSvmVmrun: LBR virtualization not supported -> #VMEXIT\n"));
343	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
344	}
345
346	/* Guest ASID. */
347	if (!pVmcbCtrl->TLBCtrl.n.u32ASID)
348	{
349	Log(("iemSvmVmrun: Guest ASID is invalid -> #VMEXIT\n"));
350	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
351	}
352
353	/* IO permission bitmap. */
354	RTGCPHYS const GCPhysIOBitmap = pVmcbCtrl->u64IOPMPhysAddr;
355	if ( (GCPhysIOBitmap & X86_PAGE_4K_OFFSET_MASK)
356	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap)
357	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + X86_PAGE_4K_SIZE)
358	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + (X86_PAGE_4K_SIZE << 1)))
359	{
360	Log(("iemSvmVmrun: IO bitmap physaddr invalid. GCPhysIOBitmap=%#RX64 -> #VMEXIT\n", GCPhysIOBitmap));
361	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
362	}
363
364	/* MSR permission bitmap. */
365	RTGCPHYS const GCPhysMsrBitmap = pVmcbCtrl->u64MSRPMPhysAddr;
366	if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
367	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap)
368	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap + X86_PAGE_4K_SIZE))
369	{
370	Log(("iemSvmVmrun: MSR bitmap physaddr invalid. GCPhysMsrBitmap=%#RX64 -> #VMEXIT\n", GCPhysMsrBitmap));
371	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
372	}
373
374	/* CR0. */
375	if ( !(pVmcbNstGst->u64CR0 & X86_CR0_CD)
376	&& (pVmcbNstGst->u64CR0 & X86_CR0_NW))
377	{
378	Log(("iemSvmVmrun: CR0 no-write through with cache disabled. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
379	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
380	}
381	if (pVmcbNstGst->u64CR0 >> 32)
382	{
383	Log(("iemSvmVmrun: CR0 reserved bits set. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
384	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
385	}
386	/** @todo Implement all reserved bits/illegal combinations for CR3, CR4. */
387
388	/* DR6 and DR7. */
389	if ( pVmcbNstGst->u64DR6 >> 32
390	\|\| pVmcbNstGst->u64DR7 >> 32)
391	{
392	Log(("iemSvmVmrun: DR6 and/or DR7 reserved bits set. DR6=%#RX64 DR7=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64DR6,
393	pVmcbNstGst->u64DR6));
394	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
395	}
396
397	/** @todo gPAT MSR validation? */
398
399	/*
400	* Copy the IO permission bitmap into the cache.
401	*/
402	Assert(pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap));
403	rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap), GCPhysIOBitmap,
404	SVM_IOPM_PAGES * X86_PAGE_4K_SIZE);
405	if (RT_FAILURE(rc))
406	{
407	Log(("iemSvmVmrun: Failed reading the IO permission bitmap at %#RGp. rc=%Rrc\n", GCPhysIOBitmap, rc));
408	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
409	}
410
411	/*
412	* Copy the MSR permission bitmap into the cache.
413	*/
414	Assert(pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap));
415	rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap), GCPhysMsrBitmap,
416	SVM_MSRPM_PAGES * X86_PAGE_4K_SIZE);
417	if (RT_FAILURE(rc))
418	{
419	Log(("iemSvmVmrun: Failed reading the MSR permission bitmap at %#RGp. rc=%Rrc\n", GCPhysMsrBitmap, rc));
420	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
421	}
422
423	/*
424	* Copy segments from nested-guest VMCB state to the guest-CPU state.
425	*
426	* We do this here as we need to use the CS attributes and it's easier this way
427	* then using the VMCB format selectors. It doesn't really matter where we copy
428	* the state, we restore the guest-CPU context state on the \#VMEXIT anyway.
429	*/
430	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, ES, es);
431	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, CS, cs);
432	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, SS, ss);
433	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, DS, ds);
434
435	/** @todo Segment attribute overrides by VMRUN. */
436
437	/*
438	* CPL adjustments and overrides.
439	*
440	* SS.DPL is apparently the CPU's CPL, see comment in CPUMGetGuestCPL().
441	* We shall thus adjust both CS.DPL and SS.DPL here.
442	*/
443	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = pVmcbNstGst->u8CPL;
444	if (CPUMIsGuestInV86ModeEx(pCtx))
445	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 3;
446	if (CPUMIsGuestInRealModeEx(pCtx))
447	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 0;
448
449	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
450
451	/*
452	* Continue validating guest-state and controls.
453	*/
454	/* EFER, CR0 and CR4. */
455	uint64_t uValidEfer;
456	rc = CPUMQueryValidatedGuestEfer(pVM, pVmcbNstGst->u64CR0, pVmcbNstGst->u64EFER, pVmcbNstGst->u64EFER, &uValidEfer);
457	if (RT_FAILURE(rc))
458	{
459	Log(("iemSvmVmrun: EFER invalid uOldEfer=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64EFER));
460	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
461	}
462	bool const fSvm = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
463	bool const fLongModeSupported = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
464	bool const fLongModeEnabled = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
465	bool const fPaging = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PG);
466	bool const fPae = RT_BOOL(pVmcbNstGst->u64CR4 & X86_CR4_PAE);
467	bool const fProtMode = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PE);
468	bool const fLongModeWithPaging = fLongModeEnabled && fPaging;
469	bool const fLongModeConformCS = pCtx->cs.Attr.n.u1Long && pCtx->cs.Attr.n.u1DefBig;
470	/* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
471	if (fLongModeWithPaging)
472	uValidEfer \|= MSR_K6_EFER_LMA;
473	bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME \| MSR_K6_EFER_LMA));
474	if ( !fSvm
475	\|\| (!fLongModeSupported && fLongModeActiveOrEnabled)
476	\|\| (fLongModeWithPaging && !fPae)
477	\|\| (fLongModeWithPaging && !fProtMode)
478	\|\| ( fLongModeEnabled
479	&& fPaging
480	&& fPae
481	&& fLongModeConformCS))
482	{
483	Log(("iemSvmVmrun: EFER invalid. uValidEfer=%#RX64 -> #VMEXIT\n", uValidEfer));
484	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
485	}
486
487	/*
488	* Preserve the required force-flags.
489	*
490	* We only preserve the force-flags that would affect the execution of the
491	* nested-guest (or the guest).
492	*
493	* - VMCPU_FF_INHIBIT_INTERRUPTS need -not- be preserved as it's for a single
494	* instruction which is this VMRUN instruction itself.
495	*
496	* - VMCPU_FF_BLOCK_NMIS needs to be preserved as it blocks NMI until the
497	* execution of a subsequent IRET instruction in the guest.
498	*
499	* - The remaining FFs (e.g. timers) can stay in place so that we will be
500	* able to generate interrupts that should cause #VMEXITs for the
501	* nested-guest.
502	*/
503	pCtx->hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
504	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
505
506	/*
507	* Interrupt shadow.
508	*/
509	if (pVmcbCtrl->u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
510	{
511	LogFlow(("iemSvmVmrun: setting interrupt shadow. inhibit PC=%#RX64\n", pVmcbNstGst->u64RIP));
512	/** @todo will this cause trouble if the nested-guest is 64-bit but the guest is 32-bit? */
513	EMSetInhibitInterruptsPC(pVCpu, pVmcbNstGst->u64RIP);
514	}
515
516	/*
517	* TLB flush control.
518	* Currently disabled since it's redundant as we unconditionally flush the TLB
519	* in iemSvmWorldSwitch() below.
520	*/
521	#if 0
522	/** @todo @bugref{7243}: ASID based PGM TLB flushes. */
523	if ( pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE
524	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
525	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
526	PGMFlushTLB(pVCpu, pVmcbNstGst->u64CR3, true /* fGlobal */);
527	#endif
528
529	/** @todo @bugref{7243}: SVM TSC offset, see tmCpuTickGetInternal. */
530
531	/*
532	* Copy the remaining guest state from the VMCB to the guest-CPU context.
533	*/
534	pCtx->gdtr.cbGdt = pVmcbNstGst->GDTR.u32Limit;
535	pCtx->gdtr.pGdt = pVmcbNstGst->GDTR.u64Base;
536	pCtx->idtr.cbIdt = pVmcbNstGst->IDTR.u32Limit;
537	pCtx->idtr.pIdt = pVmcbNstGst->IDTR.u64Base;
538	CPUMSetGuestCR0(pVCpu, pVmcbNstGst->u64CR0);
539	CPUMSetGuestCR4(pVCpu, pVmcbNstGst->u64CR4);
540	pCtx->cr3 = pVmcbNstGst->u64CR3;
541	pCtx->cr2 = pVmcbNstGst->u64CR2;
542	pCtx->dr[6] = pVmcbNstGst->u64DR6;
543	pCtx->dr[7] = pVmcbNstGst->u64DR7;
544	pCtx->rflags.u64 = pVmcbNstGst->u64RFlags;
545	pCtx->rax = pVmcbNstGst->u64RAX;
546	pCtx->rsp = pVmcbNstGst->u64RSP;
547	pCtx->rip = pVmcbNstGst->u64RIP;
548	pCtx->msrEFER = uValidEfer;
549
550	/* Mask DR6, DR7 bits mandatory set/clear bits. */
551	pCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
552	pCtx->dr[6] \|= X86_DR6_RA1_MASK;
553	pCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
554	pCtx->dr[7] \|= X86_DR7_RA1_MASK;
555
556	/*
557	* Check for pending virtual interrupts.
558	*/
559	if (pVmcbCtrl->IntCtrl.n.u1VIrqPending)
560	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
561	else
562	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
563
564	/*
565	* Update PGM, IEM and others of a world-switch.
566	*/
567	VBOXSTRICTRC rcStrict = iemSvmWorldSwitch(pVCpu, pCtx);
568	if (rcStrict == VINF_SUCCESS)
569	{ /* likely */ }
570	else if (RT_SUCCESS(rcStrict))
571	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
572	else
573	{
574	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
575	return rcStrict;
576	}
577
578	/*
579	* Clear global interrupt flags to allow interrupts in the guest.
580	*/
581	pCtx->hwvirt.svm.fGif = true;
582
583	/*
584	* Event injection.
585	*/
586	PCSVMEVENT pEventInject = &pVmcbCtrl->EventInject;
587	pCtx->hwvirt.svm.fInterceptEvents = !pEventInject->n.u1Valid;
588	if (pEventInject->n.u1Valid)
589	{
590	uint8_t const uVector = pEventInject->n.u8Vector;
591	TRPMEVENT const enmType = HMSvmEventToTrpmEventType(pEventInject);
592	uint16_t const uErrorCode = pEventInject->n.u1ErrorCodeValid ? pEventInject->n.u32ErrorCode : 0;
593
594	/* Validate vectors for hardware exceptions, see AMD spec. 15.20 "Event Injection". */
595	if (RT_UNLIKELY(enmType == TRPM_32BIT_HACK))
596	{
597	Log(("iemSvmVmrun: Invalid event type =%#x -> #VMEXIT\n", (uint8_t)pEventInject->n.u3Type));
598	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
599	}
600	if (pEventInject->n.u3Type == SVM_EVENT_EXCEPTION)
601	{
602	if ( uVector == X86_XCPT_NMI
603	\|\| uVector > X86_XCPT_LAST)
604	{
605	Log(("iemSvmVmrun: Invalid vector for hardware exception. uVector=%#x -> #VMEXIT\n", uVector));
606	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
607	}
608	if ( uVector == X86_XCPT_BR
609	&& CPUMIsGuestInLongModeEx(pCtx))
610	{
611	Log(("iemSvmVmrun: Cannot inject #BR when not in long mode -> #VMEXIT\n"));
612	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
613	}
614	/** @todo any others? */
615	}
616
617	/*
618	* Update the exit interruption info field so that if an exception occurs
619	* while delivering the event causing a #VMEXIT, we only need to update
620	* the valid bit while the rest is already in place.
621	*/
622	pVmcbCtrl->ExitIntInfo.u = pVmcbCtrl->EventInject.u;
623	pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
624
625	/** @todo NRIP: Software interrupts can only be pushed properly if we support
626	* NRIP for the nested-guest to calculate the instruction length
627	* below. */
628	LogFlow(("iemSvmVmrun: Injecting event: %04x:%08RX64 uVector=%#x enmType=%d uErrorCode=%u cr2=%#RX64\n",
629	pCtx->cs.Sel, pCtx->rip, uVector, enmType, uErrorCode, pCtx->cr2));
630	rcStrict = IEMInjectTrap(pVCpu, uVector, enmType, uErrorCode, pCtx->cr2, 0 /* cbInstr */);
631	}
632	else
633	LogFlow(("iemSvmVmrun: Entering nested-guest: %04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 efer=%#RX64 efl=%#x\n",
634	pCtx->cs.Sel, pCtx->rip, pCtx->cr0, pCtx->cr3, pCtx->cr4, pCtx->msrEFER, pCtx->rflags.u64));
635
636	return rcStrict;
637	}
638
639	/* Shouldn't really happen as the caller should've validated the physical address already. */
640	Log(("iemSvmVmrun: Failed to read nested-guest VMCB at %#RGp (rc=%Rrc) -> #VMEXIT\n", GCPhysVmcb, rc));
641	return rc;
642	}
643
644
645	#if 0
646	/**
647	* Handles nested-guest SVM control intercepts and performs the \#VMEXIT if the
648	* intercept is active.
649	*
650	* @returns Strict VBox status code.
651	* @retval VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
652	* we're not executing a nested-guest.
653	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
654	* successfully.
655	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
656	* failed and a shutdown needs to be initiated for the geust.
657	*
658	* @param pVCpu The cross context virtual CPU structure.
659	* @param pCtx The guest-CPU context.
660	* @param uExitCode The SVM exit code (see SVM_EXIT_XXX).
661	* @param uExitInfo1 The exit info. 1 field.
662	* @param uExitInfo2 The exit info. 2 field.
663	*/
664	VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,
665	uint64_t uExitInfo2)
666	{
667	#define HMSVM_CTRL_INTERCEPT_VMEXIT(a_Intercept) \
668	do { \
669	if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, (a_Intercept))) \
670	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2); \
671	break; \
672	} while (0)
673
674	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
675	return VINF_HM_INTERCEPT_NOT_ACTIVE;
676
677	switch (uExitCode)
678	{
679	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
680	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
681	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
682	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15:
683	case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
684	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
685	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27:
686	case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
687	{
688	if (CPUMIsGuestSvmXcptInterceptSet(pCtx, (X86XCPT)(uExitCode - SVM_EXIT_EXCEPTION_0)))
689	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
690	break;
691	}
692
693	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
694	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
695	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
696	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
697	{
698	if (CPUMIsGuestSvmWriteCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_CR0))
699	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
700	break;
701	}
702
703	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
704	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
705	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
706	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
707	{
708	if (CPUMIsGuestSvmReadCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_CR0))
709	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
710	break;
711	}
712
713	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
714	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
715	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
716	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
717	{
718	if (CPUMIsGuestSvmReadDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_DR0))
719	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
720	break;
721	}
722
723	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
724	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
725	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
726	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
727	{
728	if (CPUMIsGuestSvmWriteDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_DR0))
729	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
730	break;
731	}
732
733	case SVM_EXIT_INTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTR);
734	case SVM_EXIT_NMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_NMI);
735	case SVM_EXIT_SMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SMI);
736	case SVM_EXIT_INIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INIT);
737	case SVM_EXIT_VINTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VINTR);
738	case SVM_EXIT_CR0_SEL_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CR0_SEL_WRITES);
739	case SVM_EXIT_IDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_READS);
740	case SVM_EXIT_GDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_READS);
741	case SVM_EXIT_LDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_READS);
742	case SVM_EXIT_TR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_READS);
743	case SVM_EXIT_IDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_WRITES);
744	case SVM_EXIT_GDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_WRITES);
745	case SVM_EXIT_LDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_WRITES);
746	case SVM_EXIT_TR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_WRITES);
747	case SVM_EXIT_RDTSC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSC);
748	case SVM_EXIT_RDPMC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDPMC);
749	case SVM_EXIT_PUSHF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PUSHF);
750	case SVM_EXIT_POPF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_POPF);
751	case SVM_EXIT_CPUID: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CPUID);
752	case SVM_EXIT_RSM: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RSM);
753	case SVM_EXIT_IRET: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IRET);
754	case SVM_EXIT_SWINT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTN);
755	case SVM_EXIT_INVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVD);
756	case SVM_EXIT_PAUSE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PAUSE);
757	case SVM_EXIT_HLT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_HLT);
758	case SVM_EXIT_INVLPG: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPG);
759	case SVM_EXIT_INVLPGA: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPGA);
760	case SVM_EXIT_TASK_SWITCH: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TASK_SWITCH);
761	case SVM_EXIT_FERR_FREEZE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_FERR_FREEZE);
762	case SVM_EXIT_SHUTDOWN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SHUTDOWN);
763	case SVM_EXIT_VMRUN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMRUN);
764	case SVM_EXIT_VMMCALL: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMMCALL);
765	case SVM_EXIT_VMLOAD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMLOAD);
766	case SVM_EXIT_VMSAVE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMSAVE);
767	case SVM_EXIT_STGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_STGI);
768	case SVM_EXIT_CLGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CLGI);
769	case SVM_EXIT_SKINIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SKINIT);
770	case SVM_EXIT_RDTSCP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSCP);
771	case SVM_EXIT_ICEBP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_ICEBP);
772	case SVM_EXIT_WBINVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_WBINVD);
773	case SVM_EXIT_MONITOR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MONITOR);
774	case SVM_EXIT_MWAIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT);
775	case SVM_EXIT_MWAIT_ARMED: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT_ARMED);
776	case SVM_EXIT_XSETBV: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_XSETBV);
777
778	case SVM_EXIT_IOIO:
779	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
780	return VERR_SVM_IPE_1;
781
782	case SVM_EXIT_MSR:
783	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
784	return VERR_SVM_IPE_1;
785
786	case SVM_EXIT_NPF:
787	case SVM_EXIT_AVIC_INCOMPLETE_IPI:
788	case SVM_EXIT_AVIC_NOACCEL:
789	AssertMsgFailed(("Todo Implement.\n"));
790	return VERR_SVM_IPE_1;
791
792	default:
793	AssertMsgFailed(("Unsupported SVM exit code %#RX64\n", uExitCode));
794	return VERR_SVM_IPE_1;
795	}
796
797	return VINF_HM_INTERCEPT_NOT_ACTIVE;
798
799	#undef HMSVM_CTRL_INTERCEPT_VMEXIT
800	}
801	#endif
802
803
804	/**
805	* Checks if the event intercepts and performs the \#VMEXIT if the corresponding
806	* intercept is active.
807	*
808	* @returns Strict VBox status code.
809	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
810	* we're not executing a nested-guest.
811	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
812	* successfully.
813	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
814	* failed and a shutdown needs to be initiated for the geust.
815	*
816	* @returns VBox strict status code.
817	* @param pVCpu The cross context virtual CPU structure of the calling thread.
818	* @param u16Port The IO port being accessed.
819	* @param enmIoType The type of IO access.
820	* @param cbReg The IO operand size in bytes.
821	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
822	* @param iEffSeg The effective segment number.
823	* @param fRep Whether this is a repeating IO instruction (REP prefix).
824	* @param fStrIo Whether this is a string IO instruction.
825	* @param cbInstr The length of the IO instruction in bytes.
826	*/
827	IEM_STATIC VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr,
828	uint64_t uCr2)
829	{
830	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
831
832	/*
833	* Handle SVM exception and software interrupt intercepts, see AMD spec. 15.12 "Exception Intercepts".
834	*
835	* - NMI intercepts have their own exit code and do not cause SVM_EXIT_EXCEPTION_2 #VMEXITs.
836	* - External interrupts and software interrupts (INTn instruction) do not check the exception intercepts
837	* even when they use a vector in the range 0 to 31.
838	* - ICEBP should not trigger #DB intercept, but its own intercept.
839	* - For #PF exceptions, its intercept is checked before CR2 is written by the exception.
840	*/
841	/* Check NMI intercept */
842	if ( u8Vector == X86_XCPT_NMI
843	&& (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
844	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_NMI))
845	{
846	Log2(("iemHandleSvmNstGstEventIntercept: NMI intercept -> #VMEXIT\n"));
847	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_NMI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
848	}
849
850	/* Check ICEBP intercept. */
851	if ( (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
852	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_ICEBP))
853	{
854	Log2(("iemHandleSvmNstGstEventIntercept: ICEBP intercept -> #VMEXIT\n"));
855	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_ICEBP, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
856	}
857
858	/* Check CPU exception intercepts. */
859	if ( (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
860	&& IEM_IS_SVM_XCPT_INTERCEPT_SET(pVCpu, u8Vector))
861	{
862	Assert(u8Vector <= X86_XCPT_LAST);
863	uint64_t const uExitInfo1 = fFlags & IEM_XCPT_FLAGS_ERR ? uErr : 0;
864	uint64_t const uExitInfo2 = fFlags & IEM_XCPT_FLAGS_CR2 ? uCr2 : 0;
865	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssist
866	&& u8Vector == X86_XCPT_PF
867	&& !(uErr & X86_TRAP_PF_ID))
868	{
869	/** @todo Nested-guest SVM - figure out fetching op-code bytes from IEM. */
870	#ifdef IEM_WITH_CODE_TLB
871	AssertReleaseFailedReturn(VERR_IEM_IPE_5);
872	#else
873	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
874	uint8_t const offOpCode = pVCpu->iem.s.offOpcode;
875	uint8_t const cbCurrent = pVCpu->iem.s.cbOpcode - pVCpu->iem.s.offOpcode;
876	if ( cbCurrent > 0
877	&& cbCurrent < sizeof(pVmcbCtrl->abInstr))
878	{
879	Assert(cbCurrent <= sizeof(pVCpu->iem.s.abOpcode));
880	memcpy(&pVmcbCtrl->abInstr[0], &pVCpu->iem.s.abOpcode[offOpCode], cbCurrent);
881	}
882	#endif
883	}
884	Log2(("iemHandleSvmNstGstEventIntercept: Xcpt intercept u32InterceptXcpt=%#RX32 u8Vector=%#x "
885	"uExitInfo1=%#RX64 uExitInfo2=%#RX64 -> #VMEXIT\n", pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl.u32InterceptXcpt,
886	u8Vector, uExitInfo1, uExitInfo2));
887	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_EXCEPTION_0 + u8Vector, uExitInfo1, uExitInfo2);
888	}
889
890	/* Check software interrupt (INTn) intercepts. */
891	if ( (fFlags & ( IEM_XCPT_FLAGS_T_SOFT_INT
892	\| IEM_XCPT_FLAGS_BP_INSTR
893	\| IEM_XCPT_FLAGS_ICEBP_INSTR
894	\| IEM_XCPT_FLAGS_OF_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
895	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INTN))
896	{
897	uint64_t const uExitInfo1 = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssist ? u8Vector : 0;
898	Log2(("iemHandleSvmNstGstEventIntercept: Software INT intercept (u8Vector=%#x) -> #VMEXIT\n", u8Vector));
899	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SWINT, uExitInfo1, 0 /* uExitInfo2 */);
900	}
901
902	return VINF_HM_INTERCEPT_NOT_ACTIVE;
903	}
904
905
906	/**
907	* Checks the SVM IO permission bitmap and performs the \#VMEXIT if the
908	* corresponding intercept is active.
909	*
910	* @returns Strict VBox status code.
911	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
912	* we're not executing a nested-guest.
913	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
914	* successfully.
915	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
916	* failed and a shutdown needs to be initiated for the geust.
917	*
918	* @returns VBox strict status code.
919	* @param pVCpu The cross context virtual CPU structure of the calling thread.
920	* @param u16Port The IO port being accessed.
921	* @param enmIoType The type of IO access.
922	* @param cbReg The IO operand size in bytes.
923	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
924	* @param iEffSeg The effective segment number.
925	* @param fRep Whether this is a repeating IO instruction (REP prefix).
926	* @param fStrIo Whether this is a string IO instruction.
927	* @param cbInstr The length of the IO instruction in bytes.
928	*/
929	IEM_STATIC VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPU pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
930	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr)
931	{
932	Assert(IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT));
933	Assert(cAddrSizeBits == 0 \|\| cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
934	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
935
936	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u)\n", u16Port, u16Port));
937
938	SVMIOIOEXITINFO IoExitInfo;
939	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
940	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
941	bool const fIntercept = HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
942	&IoExitInfo);
943	if (fIntercept)
944	{
945	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u) -> #VMEXIT\n", u16Port, u16Port));
946	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_IOIO, IoExitInfo.u, pCtx->rip + cbInstr);
947	}
948
949	/** @todo remove later (for debugging as VirtualBox always traps all IO
950	* intercepts). */
951	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
952	return VINF_HM_INTERCEPT_NOT_ACTIVE;
953	}
954
955
956	/**
957	* Checks the SVM MSR permission bitmap and performs the \#VMEXIT if the
958	* corresponding intercept is active.
959	*
960	* @returns Strict VBox status code.
961	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the MSR permission bitmap does not
962	* specify interception of the accessed MSR @a idMsr.
963	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
964	* successfully.
965	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
966	* failed and a shutdown needs to be initiated for the geust.
967	*
968	* @param pVCpu The cross context virtual CPU structure.
969	* @param pCtx The guest-CPU context.
970	* @param idMsr The MSR being accessed in the nested-guest.
971	* @param fWrite Whether this is an MSR write access, @c false implies an
972	* MSR read.
973	*/
974	IEM_STATIC VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite)
975	{
976	/*
977	* Check if any MSRs are being intercepted.
978	*/
979	Assert(CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_MSR_PROT));
980	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
981
982	uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ;
983
984	/*
985	* Get the byte and bit offset of the permission bits corresponding to the MSR.
986	*/
987	uint16_t offMsrpm;
988	uint32_t uMsrpmBit;
989	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
990	if (RT_SUCCESS(rc))
991	{
992	Assert(uMsrpmBit < 0x3fff);
993	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
994	if (fWrite)
995	++uMsrpmBit;
996
997	/*
998	* Check if the bit is set, if so, trigger a #VMEXIT.
999	*/
1000	uint8_t pbMsrpm = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
1001	pbMsrpm += offMsrpm;
1002	if (ASMBitTest(pbMsrpm, uMsrpmBit))
1003	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1004	}
1005	else
1006	{
1007	/*
1008	* This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (guest hypervisor) deal with it.
1009	*/
1010	Log(("iemSvmHandleMsrIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool -> #VMEXIT\n", idMsr, fWrite));
1011	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1012	}
1013	return VINF_HM_INTERCEPT_NOT_ACTIVE;
1014	}
1015
1016
1017
1018	/**
1019	* Implements 'VMRUN'.
1020	*/
1021	IEM_CIMPL_DEF_0(iemCImpl_vmrun)
1022	{
1023	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1024	RT_NOREF2(pVCpu, cbInstr);
1025	return VINF_EM_RAW_EMULATE_INSTR;
1026	#else
1027	LogFlow(("iemCImpl_vmrun\n"));
1028	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1029	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmrun);
1030
1031	/** @todo Check effective address size using address size prefix. */
1032	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1033	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1034	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1035	{
1036	Log(("vmrun: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1037	return iemRaiseGeneralProtectionFault0(pVCpu);
1038	}
1039
1040	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
1041	{
1042	Log(("vmrun: Guest intercept -> #VMEXIT\n"));
1043	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMRUN, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1044	}
1045
1046	VBOXSTRICTRC rcStrict = iemSvmVmrun(pVCpu, pCtx, cbInstr, GCPhysVmcb);
1047	if (rcStrict == VERR_SVM_VMEXIT_FAILED)
1048	{
1049	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1050	rcStrict = VINF_EM_TRIPLE_FAULT;
1051	}
1052	return rcStrict;
1053	#endif
1054	}
1055
1056
1057	/**
1058	* Implements 'VMMCALL'.
1059	*/
1060	IEM_CIMPL_DEF_0(iemCImpl_vmmcall)
1061	{
1062	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1063	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
1064	{
1065	Log(("vmmcall: Guest intercept -> #VMEXIT\n"));
1066	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMMCALL, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1067	}
1068
1069	bool fUpdatedRipAndRF;
1070	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fUpdatedRipAndRF);
1071	if (RT_SUCCESS(rcStrict))
1072	{
1073	if (!fUpdatedRipAndRF)
1074	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1075	return rcStrict;
1076	}
1077
1078	return iemRaiseUndefinedOpcode(pVCpu);
1079	}
1080
1081
1082	/**
1083	* Implements 'VMLOAD'.
1084	*/
1085	IEM_CIMPL_DEF_0(iemCImpl_vmload)
1086	{
1087	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1088	RT_NOREF2(pVCpu, cbInstr);
1089	return VINF_EM_RAW_EMULATE_INSTR;
1090	#else
1091	LogFlow(("iemCImpl_vmload\n"));
1092	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1093	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmload);
1094
1095	/** @todo Check effective address size using address size prefix. */
1096	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1097	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1098	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1099	{
1100	Log(("vmload: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1101	return iemRaiseGeneralProtectionFault0(pVCpu);
1102	}
1103
1104	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
1105	{
1106	Log(("vmload: Guest intercept -> #VMEXIT\n"));
1107	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMLOAD, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1108	}
1109
1110	SVMVMCBSTATESAVE VmcbNstGst;
1111	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1112	sizeof(SVMVMCBSTATESAVE));
1113	if (rcStrict == VINF_SUCCESS)
1114	{
1115	LogFlow(("vmload: Loading VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1116	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, FS, fs);
1117	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, GS, gs);
1118	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, TR, tr);
1119	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, LDTR, ldtr);
1120
1121	pCtx->msrKERNELGSBASE = VmcbNstGst.u64KernelGSBase;
1122	pCtx->msrSTAR = VmcbNstGst.u64STAR;
1123	pCtx->msrLSTAR = VmcbNstGst.u64LSTAR;
1124	pCtx->msrCSTAR = VmcbNstGst.u64CSTAR;
1125	pCtx->msrSFMASK = VmcbNstGst.u64SFMASK;
1126
1127	pCtx->SysEnter.cs = VmcbNstGst.u64SysEnterCS;
1128	pCtx->SysEnter.esp = VmcbNstGst.u64SysEnterESP;
1129	pCtx->SysEnter.eip = VmcbNstGst.u64SysEnterEIP;
1130
1131	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1132	}
1133	return rcStrict;
1134	#endif
1135	}
1136
1137
1138	/**
1139	* Implements 'VMSAVE'.
1140	*/
1141	IEM_CIMPL_DEF_0(iemCImpl_vmsave)
1142	{
1143	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1144	RT_NOREF2(pVCpu, cbInstr);
1145	return VINF_EM_RAW_EMULATE_INSTR;
1146	#else
1147	LogFlow(("iemCImpl_vmsave\n"));
1148	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1149	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmsave);
1150
1151	/** @todo Check effective address size using address size prefix. */
1152	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1153	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1154	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1155	{
1156	Log(("vmsave: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1157	return iemRaiseGeneralProtectionFault0(pVCpu);
1158	}
1159
1160	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
1161	{
1162	Log(("vmsave: Guest intercept -> #VMEXIT\n"));
1163	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMSAVE, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1164	}
1165
1166	SVMVMCBSTATESAVE VmcbNstGst;
1167	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1168	sizeof(SVMVMCBSTATESAVE));
1169	if (rcStrict == VINF_SUCCESS)
1170	{
1171	LogFlow(("vmsave: Saving VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1172	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, FS, fs);
1173	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, GS, gs);
1174	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, TR, tr);
1175	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, LDTR, ldtr);
1176
1177	VmcbNstGst.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1178	VmcbNstGst.u64STAR = pCtx->msrSTAR;
1179	VmcbNstGst.u64LSTAR = pCtx->msrLSTAR;
1180	VmcbNstGst.u64CSTAR = pCtx->msrCSTAR;
1181	VmcbNstGst.u64SFMASK = pCtx->msrSFMASK;
1182
1183	VmcbNstGst.u64SysEnterCS = pCtx->SysEnter.cs;
1184	VmcbNstGst.u64SysEnterESP = pCtx->SysEnter.esp;
1185	VmcbNstGst.u64SysEnterEIP = pCtx->SysEnter.eip;
1186
1187	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest), &VmcbNstGst,
1188	sizeof(SVMVMCBSTATESAVE));
1189	if (rcStrict == VINF_SUCCESS)
1190	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1191	}
1192	return rcStrict;
1193	#endif
1194	}
1195
1196
1197	/**
1198	* Implements 'CLGI'.
1199	*/
1200	IEM_CIMPL_DEF_0(iemCImpl_clgi)
1201	{
1202	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1203	RT_NOREF2(pVCpu, cbInstr);
1204	return VINF_EM_RAW_EMULATE_INSTR;
1205	#else
1206	LogFlow(("iemCImpl_clgi\n"));
1207	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1208	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, clgi);
1209	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
1210	{
1211	Log(("clgi: Guest intercept -> #VMEXIT\n"));
1212	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_CLGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1213	}
1214
1215	pCtx->hwvirt.svm.fGif = false;
1216	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1217
1218	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1219	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
1220	# else
1221	return VINF_SUCCESS;
1222	# endif
1223	#endif
1224	}
1225
1226
1227	/**
1228	* Implements 'STGI'.
1229	*/
1230	IEM_CIMPL_DEF_0(iemCImpl_stgi)
1231	{
1232	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1233	RT_NOREF2(pVCpu, cbInstr);
1234	return VINF_EM_RAW_EMULATE_INSTR;
1235	#else
1236	LogFlow(("iemCImpl_stgi\n"));
1237	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1238	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, stgi);
1239	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_STGI))
1240	{
1241	Log2(("stgi: Guest intercept -> #VMEXIT\n"));
1242	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_STGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1243	}
1244
1245	pCtx->hwvirt.svm.fGif = true;
1246	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1247
1248	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1249	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
1250	# else
1251	return VINF_SUCCESS;
1252	# endif
1253	#endif
1254	}
1255
1256
1257	/**
1258	* Implements 'INVLPGA'.
1259	*/
1260	IEM_CIMPL_DEF_0(iemCImpl_invlpga)
1261	{
1262	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1263	/** @todo Check effective address size using address size prefix. */
1264	RTGCPTR const GCPtrPage = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1265	/** @todo PGM needs virtual ASID support. */
1266	#if 0
1267	uint32_t const uAsid = pCtx->ecx;
1268	#endif
1269
1270	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1271	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
1272	{
1273	Log2(("invlpga: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
1274	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_INVLPGA, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1275	}
1276
1277	PGMInvalidatePage(pVCpu, GCPtrPage);
1278	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1279	return VINF_SUCCESS;
1280	}
1281
1282
1283	/**
1284	* Implements 'SKINIT'.
1285	*/
1286	IEM_CIMPL_DEF_0(iemCImpl_skinit)
1287	{
1288	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1289
1290	uint32_t uIgnore;
1291	uint32_t fFeaturesECX;
1292	CPUMGetGuestCpuId(pVCpu, 0x80000001, 0 /* iSubLeaf */, &uIgnore, &uIgnore, &fFeaturesECX, &uIgnore);
1293	if (!(fFeaturesECX & X86_CPUID_AMD_FEATURE_ECX_SKINIT))
1294	return iemRaiseUndefinedOpcode(pVCpu);
1295
1296	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
1297	{
1298	Log2(("skinit: Guest intercept -> #VMEXIT\n"));
1299	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SKINIT, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1300	}
1301
1302	RT_NOREF(cbInstr);
1303	return VERR_IEM_INSTR_NOT_IMPLEMENTED;
1304	}
1305

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h@ 69120

Download in other formats: