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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp@ 97134

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1/* $Id: IEMAllCImpl.cpp 97126 2022-10-13 09:02:59Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in C/C++ (code include).
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/cpum.h>
36#include <VBox/vmm/apic.h>
37#include <VBox/vmm/pdm.h>
38#include <VBox/vmm/pgm.h>
39#include <VBox/vmm/iom.h>
40#include <VBox/vmm/em.h>
41#include <VBox/vmm/hm.h>
42#include <VBox/vmm/nem.h>
43#include <VBox/vmm/gim.h>
44#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
45# include <VBox/vmm/em.h>
46# include <VBox/vmm/hm_svm.h>
47#endif
48#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
49# include <VBox/vmm/hmvmxinline.h>
50#endif
51#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
52# include <VBox/vmm/cpuidcall.h>
53#endif
54#include <VBox/vmm/tm.h>
55#include <VBox/vmm/dbgf.h>
56#include <VBox/vmm/dbgftrace.h>
57#include "IEMInternal.h"
58#include <VBox/vmm/vmcc.h>
59#include <VBox/log.h>
60#include <VBox/err.h>
61#include <VBox/param.h>
62#include <VBox/dis.h>
63#include <VBox/disopcode.h>
64#include <iprt/asm-math.h>
65#include <iprt/assert.h>
66#include <iprt/string.h>
67#include <iprt/x86.h>
68
69#include "IEMInline.h"
70
71
72/** @name Misc Helpers
73 * @{
74 */
75
76
77/**
78 * Worker function for iemHlpCheckPortIOPermission, don't call directly.
79 *
80 * @returns Strict VBox status code.
81 *
82 * @param pVCpu The cross context virtual CPU structure of the calling thread.
83 * @param u16Port The port number.
84 * @param cbOperand The operand size.
85 */
86static VBOXSTRICTRC iemHlpCheckPortIOPermissionBitmap(PVMCPUCC pVCpu, uint16_t u16Port, uint8_t cbOperand)
87{
88 /* The TSS bits we're interested in are the same on 386 and AMD64. */
89 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_BUSY == X86_SEL_TYPE_SYS_386_TSS_BUSY);
90 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_AVAIL == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
91 AssertCompileMembersAtSameOffset(X86TSS32, offIoBitmap, X86TSS64, offIoBitmap);
92 AssertCompile(sizeof(X86TSS32) == sizeof(X86TSS64));
93
94 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
95
96 /*
97 * Check the TSS type, 16-bit TSSes doesn't have any I/O permission bitmap.
98 */
99 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
100 if (RT_UNLIKELY( pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_BUSY
101 && pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_AVAIL))
102 {
103 Log(("iemHlpCheckPortIOPermissionBitmap: Port=%#x cb=%d - TSS type %#x (attr=%#x) has no I/O bitmap -> #GP(0)\n",
104 u16Port, cbOperand, pVCpu->cpum.GstCtx.tr.Attr.n.u4Type, pVCpu->cpum.GstCtx.tr.Attr.u));
105 return iemRaiseGeneralProtectionFault0(pVCpu);
106 }
107
108 /*
109 * Read the bitmap offset (may #PF).
110 */
111 uint16_t offBitmap;
112 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &offBitmap, UINT8_MAX,
113 pVCpu->cpum.GstCtx.tr.u64Base + RT_UOFFSETOF(X86TSS64, offIoBitmap));
114 if (rcStrict != VINF_SUCCESS)
115 {
116 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading offIoBitmap (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
117 return rcStrict;
118 }
119
120 /*
121 * The bit range from u16Port to (u16Port + cbOperand - 1), however intel
122 * describes the CPU actually reading two bytes regardless of whether the
123 * bit range crosses a byte boundrary. Thus the + 1 in the test below.
124 */
125 uint32_t offFirstBit = (uint32_t)u16Port / 8 + offBitmap;
126 /** @todo check if real CPUs ensures that offBitmap has a minimum value of
127 * for instance sizeof(X86TSS32). */
128 if (offFirstBit + 1 > pVCpu->cpum.GstCtx.tr.u32Limit) /* the limit is inclusive */
129 {
130 Log(("iemHlpCheckPortIOPermissionBitmap: offFirstBit=%#x + 1 is beyond u32Limit=%#x -> #GP(0)\n",
131 offFirstBit, pVCpu->cpum.GstCtx.tr.u32Limit));
132 return iemRaiseGeneralProtectionFault0(pVCpu);
133 }
134
135 /*
136 * Read the necessary bits.
137 */
138 /** @todo Test the assertion in the intel manual that the CPU reads two
139 * bytes. The question is how this works wrt to \#PF and \#GP on the
140 * 2nd byte when it's not required. */
141 uint16_t bmBytes = UINT16_MAX;
142 rcStrict = iemMemFetchSysU16(pVCpu, &bmBytes, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base + offFirstBit);
143 if (rcStrict != VINF_SUCCESS)
144 {
145 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading I/O bitmap @%#x (%Rrc)\n", offFirstBit, VBOXSTRICTRC_VAL(rcStrict)));
146 return rcStrict;
147 }
148
149 /*
150 * Perform the check.
151 */
152 uint16_t fPortMask = (1 << cbOperand) - 1;
153 bmBytes >>= (u16Port & 7);
154 if (bmBytes & fPortMask)
155 {
156 Log(("iemHlpCheckPortIOPermissionBitmap: u16Port=%#x LB %u - access denied (bm=%#x mask=%#x) -> #GP(0)\n",
157 u16Port, cbOperand, bmBytes, fPortMask));
158 return iemRaiseGeneralProtectionFault0(pVCpu);
159 }
160
161 return VINF_SUCCESS;
162}
163
164
165/**
166 * Checks if we are allowed to access the given I/O port, raising the
167 * appropriate exceptions if we aren't (or if the I/O bitmap is not
168 * accessible).
169 *
170 * @returns Strict VBox status code.
171 *
172 * @param pVCpu The cross context virtual CPU structure of the calling thread.
173 * @param u16Port The port number.
174 * @param cbOperand The operand size.
175 */
176DECLINLINE(VBOXSTRICTRC) iemHlpCheckPortIOPermission(PVMCPUCC pVCpu, uint16_t u16Port, uint8_t cbOperand)
177{
178 X86EFLAGS Efl;
179 Efl.u = IEMMISC_GET_EFL(pVCpu);
180 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
181 && ( pVCpu->iem.s.uCpl > Efl.Bits.u2IOPL
182 || Efl.Bits.u1VM) )
183 return iemHlpCheckPortIOPermissionBitmap(pVCpu, u16Port, cbOperand);
184 return VINF_SUCCESS;
185}
186
187
188#if 0
189/**
190 * Calculates the parity bit.
191 *
192 * @returns true if the bit is set, false if not.
193 * @param u8Result The least significant byte of the result.
194 */
195static bool iemHlpCalcParityFlag(uint8_t u8Result)
196{
197 /*
198 * Parity is set if the number of bits in the least significant byte of
199 * the result is even.
200 */
201 uint8_t cBits;
202 cBits = u8Result & 1; /* 0 */
203 u8Result >>= 1;
204 cBits += u8Result & 1;
205 u8Result >>= 1;
206 cBits += u8Result & 1;
207 u8Result >>= 1;
208 cBits += u8Result & 1;
209 u8Result >>= 1;
210 cBits += u8Result & 1; /* 4 */
211 u8Result >>= 1;
212 cBits += u8Result & 1;
213 u8Result >>= 1;
214 cBits += u8Result & 1;
215 u8Result >>= 1;
216 cBits += u8Result & 1;
217 return !(cBits & 1);
218}
219#endif /* not used */
220
221
222/**
223 * Updates the specified flags according to a 8-bit result.
224 *
225 * @param pVCpu The cross context virtual CPU structure of the calling thread.
226 * @param u8Result The result to set the flags according to.
227 * @param fToUpdate The flags to update.
228 * @param fUndefined The flags that are specified as undefined.
229 */
230static void iemHlpUpdateArithEFlagsU8(PVMCPUCC pVCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
231{
232 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
233 iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
234 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
235 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
236}
237
238
239/**
240 * Updates the specified flags according to a 16-bit result.
241 *
242 * @param pVCpu The cross context virtual CPU structure of the calling thread.
243 * @param u16Result The result to set the flags according to.
244 * @param fToUpdate The flags to update.
245 * @param fUndefined The flags that are specified as undefined.
246 */
247static void iemHlpUpdateArithEFlagsU16(PVMCPUCC pVCpu, uint16_t u16Result, uint32_t fToUpdate, uint32_t fUndefined)
248{
249 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
250 iemAImpl_test_u16(&u16Result, u16Result, &fEFlags);
251 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
252 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
253}
254
255
256/**
257 * Helper used by iret.
258 *
259 * @param pVCpu The cross context virtual CPU structure of the calling thread.
260 * @param uCpl The new CPL.
261 * @param pSReg Pointer to the segment register.
262 */
263static void iemHlpAdjustSelectorForNewCpl(PVMCPUCC pVCpu, uint8_t uCpl, PCPUMSELREG pSReg)
264{
265 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
266 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
267
268 if ( uCpl > pSReg->Attr.n.u2Dpl
269 && pSReg->Attr.n.u1DescType /* code or data, not system */
270 && (pSReg->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
271 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
272 iemHlpLoadNullDataSelectorProt(pVCpu, pSReg, 0);
273}
274
275
276/**
277 * Indicates that we have modified the FPU state.
278 *
279 * @param pVCpu The cross context virtual CPU structure of the calling thread.
280 */
281DECLINLINE(void) iemHlpUsedFpu(PVMCPUCC pVCpu)
282{
283 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
284}
285
286/** @} */
287
288/** @name C Implementations
289 * @{
290 */
291
292/**
293 * Implements a 16-bit popa.
294 */
295IEM_CIMPL_DEF_0(iemCImpl_popa_16)
296{
297 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
298 RTGCPTR GCPtrLast = GCPtrStart + 15;
299 VBOXSTRICTRC rcStrict;
300
301 /*
302 * The docs are a bit hard to comprehend here, but it looks like we wrap
303 * around in real mode as long as none of the individual "popa" crosses the
304 * end of the stack segment. In protected mode we check the whole access
305 * in one go. For efficiency, only do the word-by-word thing if we're in
306 * danger of wrapping around.
307 */
308 /** @todo do popa boundary / wrap-around checks. */
309 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
310 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
311 {
312 /* word-by-word */
313 RTUINT64U TmpRsp;
314 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
315 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.di, &TmpRsp);
316 if (rcStrict == VINF_SUCCESS)
317 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.si, &TmpRsp);
318 if (rcStrict == VINF_SUCCESS)
319 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bp, &TmpRsp);
320 if (rcStrict == VINF_SUCCESS)
321 {
322 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
323 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bx, &TmpRsp);
324 }
325 if (rcStrict == VINF_SUCCESS)
326 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.dx, &TmpRsp);
327 if (rcStrict == VINF_SUCCESS)
328 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.cx, &TmpRsp);
329 if (rcStrict == VINF_SUCCESS)
330 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.ax, &TmpRsp);
331 if (rcStrict == VINF_SUCCESS)
332 {
333 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
334 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
335 }
336 }
337 else
338 {
339 uint16_t const *pa16Mem = NULL;
340 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R, sizeof(*pa16Mem) - 1);
341 if (rcStrict == VINF_SUCCESS)
342 {
343 pVCpu->cpum.GstCtx.di = pa16Mem[7 - X86_GREG_xDI];
344 pVCpu->cpum.GstCtx.si = pa16Mem[7 - X86_GREG_xSI];
345 pVCpu->cpum.GstCtx.bp = pa16Mem[7 - X86_GREG_xBP];
346 /* skip sp */
347 pVCpu->cpum.GstCtx.bx = pa16Mem[7 - X86_GREG_xBX];
348 pVCpu->cpum.GstCtx.dx = pa16Mem[7 - X86_GREG_xDX];
349 pVCpu->cpum.GstCtx.cx = pa16Mem[7 - X86_GREG_xCX];
350 pVCpu->cpum.GstCtx.ax = pa16Mem[7 - X86_GREG_xAX];
351 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_R);
352 if (rcStrict == VINF_SUCCESS)
353 {
354 iemRegAddToRsp(pVCpu, 16);
355 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
356 }
357 }
358 }
359 return rcStrict;
360}
361
362
363/**
364 * Implements a 32-bit popa.
365 */
366IEM_CIMPL_DEF_0(iemCImpl_popa_32)
367{
368 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
369 RTGCPTR GCPtrLast = GCPtrStart + 31;
370 VBOXSTRICTRC rcStrict;
371
372 /*
373 * The docs are a bit hard to comprehend here, but it looks like we wrap
374 * around in real mode as long as none of the individual "popa" crosses the
375 * end of the stack segment. In protected mode we check the whole access
376 * in one go. For efficiency, only do the word-by-word thing if we're in
377 * danger of wrapping around.
378 */
379 /** @todo do popa boundary / wrap-around checks. */
380 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
381 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
382 {
383 /* word-by-word */
384 RTUINT64U TmpRsp;
385 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
386 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edi, &TmpRsp);
387 if (rcStrict == VINF_SUCCESS)
388 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.esi, &TmpRsp);
389 if (rcStrict == VINF_SUCCESS)
390 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebp, &TmpRsp);
391 if (rcStrict == VINF_SUCCESS)
392 {
393 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
394 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebx, &TmpRsp);
395 }
396 if (rcStrict == VINF_SUCCESS)
397 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edx, &TmpRsp);
398 if (rcStrict == VINF_SUCCESS)
399 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ecx, &TmpRsp);
400 if (rcStrict == VINF_SUCCESS)
401 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.eax, &TmpRsp);
402 if (rcStrict == VINF_SUCCESS)
403 {
404#if 1 /** @todo what actually happens with the high bits when we're in 16-bit mode? */
405 pVCpu->cpum.GstCtx.rdi &= UINT32_MAX;
406 pVCpu->cpum.GstCtx.rsi &= UINT32_MAX;
407 pVCpu->cpum.GstCtx.rbp &= UINT32_MAX;
408 pVCpu->cpum.GstCtx.rbx &= UINT32_MAX;
409 pVCpu->cpum.GstCtx.rdx &= UINT32_MAX;
410 pVCpu->cpum.GstCtx.rcx &= UINT32_MAX;
411 pVCpu->cpum.GstCtx.rax &= UINT32_MAX;
412#endif
413 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
414 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
415 }
416 }
417 else
418 {
419 uint32_t const *pa32Mem;
420 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R, sizeof(*pa32Mem) - 1);
421 if (rcStrict == VINF_SUCCESS)
422 {
423 pVCpu->cpum.GstCtx.rdi = pa32Mem[7 - X86_GREG_xDI];
424 pVCpu->cpum.GstCtx.rsi = pa32Mem[7 - X86_GREG_xSI];
425 pVCpu->cpum.GstCtx.rbp = pa32Mem[7 - X86_GREG_xBP];
426 /* skip esp */
427 pVCpu->cpum.GstCtx.rbx = pa32Mem[7 - X86_GREG_xBX];
428 pVCpu->cpum.GstCtx.rdx = pa32Mem[7 - X86_GREG_xDX];
429 pVCpu->cpum.GstCtx.rcx = pa32Mem[7 - X86_GREG_xCX];
430 pVCpu->cpum.GstCtx.rax = pa32Mem[7 - X86_GREG_xAX];
431 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa32Mem, IEM_ACCESS_STACK_R);
432 if (rcStrict == VINF_SUCCESS)
433 {
434 iemRegAddToRsp(pVCpu, 32);
435 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
436 }
437 }
438 }
439 return rcStrict;
440}
441
442
443/**
444 * Implements a 16-bit pusha.
445 */
446IEM_CIMPL_DEF_0(iemCImpl_pusha_16)
447{
448 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
449 RTGCPTR GCPtrBottom = GCPtrTop - 15;
450 VBOXSTRICTRC rcStrict;
451
452 /*
453 * The docs are a bit hard to comprehend here, but it looks like we wrap
454 * around in real mode as long as none of the individual "pushd" crosses the
455 * end of the stack segment. In protected mode we check the whole access
456 * in one go. For efficiency, only do the word-by-word thing if we're in
457 * danger of wrapping around.
458 */
459 /** @todo do pusha boundary / wrap-around checks. */
460 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
461 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
462 {
463 /* word-by-word */
464 RTUINT64U TmpRsp;
465 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
466 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.ax, &TmpRsp);
467 if (rcStrict == VINF_SUCCESS)
468 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.cx, &TmpRsp);
469 if (rcStrict == VINF_SUCCESS)
470 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.dx, &TmpRsp);
471 if (rcStrict == VINF_SUCCESS)
472 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bx, &TmpRsp);
473 if (rcStrict == VINF_SUCCESS)
474 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.sp, &TmpRsp);
475 if (rcStrict == VINF_SUCCESS)
476 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bp, &TmpRsp);
477 if (rcStrict == VINF_SUCCESS)
478 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.si, &TmpRsp);
479 if (rcStrict == VINF_SUCCESS)
480 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.di, &TmpRsp);
481 if (rcStrict == VINF_SUCCESS)
482 {
483 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
484 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
485 }
486 }
487 else
488 {
489 GCPtrBottom--;
490 uint16_t *pa16Mem = NULL;
491 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W, sizeof(*pa16Mem) - 1);
492 if (rcStrict == VINF_SUCCESS)
493 {
494 pa16Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.di;
495 pa16Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.si;
496 pa16Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.bp;
497 pa16Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.sp;
498 pa16Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.bx;
499 pa16Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.dx;
500 pa16Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.cx;
501 pa16Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.ax;
502 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_W);
503 if (rcStrict == VINF_SUCCESS)
504 {
505 iemRegSubFromRsp(pVCpu, 16);
506 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
507 }
508 }
509 }
510 return rcStrict;
511}
512
513
514/**
515 * Implements a 32-bit pusha.
516 */
517IEM_CIMPL_DEF_0(iemCImpl_pusha_32)
518{
519 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
520 RTGCPTR GCPtrBottom = GCPtrTop - 31;
521 VBOXSTRICTRC rcStrict;
522
523 /*
524 * The docs are a bit hard to comprehend here, but it looks like we wrap
525 * around in real mode as long as none of the individual "pusha" crosses the
526 * end of the stack segment. In protected mode we check the whole access
527 * in one go. For efficiency, only do the word-by-word thing if we're in
528 * danger of wrapping around.
529 */
530 /** @todo do pusha boundary / wrap-around checks. */
531 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
532 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
533 {
534 /* word-by-word */
535 RTUINT64U TmpRsp;
536 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
537 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.eax, &TmpRsp);
538 if (rcStrict == VINF_SUCCESS)
539 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ecx, &TmpRsp);
540 if (rcStrict == VINF_SUCCESS)
541 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edx, &TmpRsp);
542 if (rcStrict == VINF_SUCCESS)
543 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebx, &TmpRsp);
544 if (rcStrict == VINF_SUCCESS)
545 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esp, &TmpRsp);
546 if (rcStrict == VINF_SUCCESS)
547 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebp, &TmpRsp);
548 if (rcStrict == VINF_SUCCESS)
549 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esi, &TmpRsp);
550 if (rcStrict == VINF_SUCCESS)
551 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edi, &TmpRsp);
552 if (rcStrict == VINF_SUCCESS)
553 {
554 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
555 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
556 }
557 }
558 else
559 {
560 GCPtrBottom--;
561 uint32_t *pa32Mem;
562 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W, sizeof(*pa32Mem) - 1);
563 if (rcStrict == VINF_SUCCESS)
564 {
565 pa32Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.edi;
566 pa32Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.esi;
567 pa32Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.ebp;
568 pa32Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.esp;
569 pa32Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.ebx;
570 pa32Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.edx;
571 pa32Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.ecx;
572 pa32Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.eax;
573 rcStrict = iemMemCommitAndUnmap(pVCpu, pa32Mem, IEM_ACCESS_STACK_W);
574 if (rcStrict == VINF_SUCCESS)
575 {
576 iemRegSubFromRsp(pVCpu, 32);
577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
578 }
579 }
580 }
581 return rcStrict;
582}
583
584
585/**
586 * Implements pushf.
587 *
588 *
589 * @param enmEffOpSize The effective operand size.
590 */
591IEM_CIMPL_DEF_1(iemCImpl_pushf, IEMMODE, enmEffOpSize)
592{
593 VBOXSTRICTRC rcStrict;
594
595 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_PUSHF))
596 {
597 Log2(("pushf: Guest intercept -> #VMEXIT\n"));
598 IEM_SVM_UPDATE_NRIP(pVCpu);
599 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_PUSHF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
600 }
601
602 /*
603 * If we're in V8086 mode some care is required (which is why we're in
604 * doing this in a C implementation).
605 */
606 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
607 if ( (fEfl & X86_EFL_VM)
608 && X86_EFL_GET_IOPL(fEfl) != 3 )
609 {
610 Assert(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE);
611 if ( enmEffOpSize != IEMMODE_16BIT
612 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
613 return iemRaiseGeneralProtectionFault0(pVCpu);
614 fEfl &= ~X86_EFL_IF; /* (RF and VM are out of range) */
615 fEfl |= (fEfl & X86_EFL_VIF) >> (19 - 9);
616 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
617 }
618 else
619 {
620
621 /*
622 * Ok, clear RF and VM, adjust for ancient CPUs, and push the flags.
623 */
624 fEfl &= ~(X86_EFL_RF | X86_EFL_VM);
625
626 switch (enmEffOpSize)
627 {
628 case IEMMODE_16BIT:
629 AssertCompile(IEMTARGETCPU_8086 <= IEMTARGETCPU_186 && IEMTARGETCPU_V20 <= IEMTARGETCPU_186 && IEMTARGETCPU_286 > IEMTARGETCPU_186);
630 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_186)
631 fEfl |= UINT16_C(0xf000);
632 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
633 break;
634 case IEMMODE_32BIT:
635 rcStrict = iemMemStackPushU32(pVCpu, fEfl);
636 break;
637 case IEMMODE_64BIT:
638 rcStrict = iemMemStackPushU64(pVCpu, fEfl);
639 break;
640 IEM_NOT_REACHED_DEFAULT_CASE_RET();
641 }
642 }
643 if (rcStrict != VINF_SUCCESS)
644 return rcStrict;
645
646 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
647 return VINF_SUCCESS;
648}
649
650
651/**
652 * Implements popf.
653 *
654 * @param enmEffOpSize The effective operand size.
655 */
656IEM_CIMPL_DEF_1(iemCImpl_popf, IEMMODE, enmEffOpSize)
657{
658 uint32_t const fEflOld = IEMMISC_GET_EFL(pVCpu);
659 VBOXSTRICTRC rcStrict;
660 uint32_t fEflNew;
661
662 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_POPF))
663 {
664 Log2(("popf: Guest intercept -> #VMEXIT\n"));
665 IEM_SVM_UPDATE_NRIP(pVCpu);
666 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_POPF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
667 }
668
669 /*
670 * V8086 is special as usual.
671 */
672 if (fEflOld & X86_EFL_VM)
673 {
674 /*
675 * Almost anything goes if IOPL is 3.
676 */
677 if (X86_EFL_GET_IOPL(fEflOld) == 3)
678 {
679 switch (enmEffOpSize)
680 {
681 case IEMMODE_16BIT:
682 {
683 uint16_t u16Value;
684 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
685 if (rcStrict != VINF_SUCCESS)
686 return rcStrict;
687 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
688 break;
689 }
690 case IEMMODE_32BIT:
691 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
692 if (rcStrict != VINF_SUCCESS)
693 return rcStrict;
694 break;
695 IEM_NOT_REACHED_DEFAULT_CASE_RET();
696 }
697
698 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
699 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
700 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
701 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
702 }
703 /*
704 * Interrupt flag virtualization with CR4.VME=1.
705 */
706 else if ( enmEffOpSize == IEMMODE_16BIT
707 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
708 {
709 uint16_t u16Value;
710 RTUINT64U TmpRsp;
711 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
712 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Value, &TmpRsp);
713 if (rcStrict != VINF_SUCCESS)
714 return rcStrict;
715
716 /** @todo Is the popf VME \#GP(0) delivered after updating RSP+RIP
717 * or before? */
718 if ( ( (u16Value & X86_EFL_IF)
719 && (fEflOld & X86_EFL_VIP))
720 || (u16Value & X86_EFL_TF) )
721 return iemRaiseGeneralProtectionFault0(pVCpu);
722
723 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000) & ~X86_EFL_VIF);
724 fEflNew |= (fEflNew & X86_EFL_IF) << (19 - 9);
725 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
726 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
727
728 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
729 }
730 else
731 return iemRaiseGeneralProtectionFault0(pVCpu);
732
733 }
734 /*
735 * Not in V8086 mode.
736 */
737 else
738 {
739 /* Pop the flags. */
740 switch (enmEffOpSize)
741 {
742 case IEMMODE_16BIT:
743 {
744 uint16_t u16Value;
745 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
746 if (rcStrict != VINF_SUCCESS)
747 return rcStrict;
748 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
749
750 /*
751 * Ancient CPU adjustments:
752 * - 8086, 80186, V20/30:
753 * Fixed bits 15:12 bits are not kept correctly internally, mostly for
754 * practical reasons (masking below). We add them when pushing flags.
755 * - 80286:
756 * The NT and IOPL flags cannot be popped from real mode and are
757 * therefore always zero (since a 286 can never exit from PM and
758 * their initial value is zero). This changed on a 386 and can
759 * therefore be used to detect 286 or 386 CPU in real mode.
760 */
761 if ( IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286
762 && !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE) )
763 fEflNew &= ~(X86_EFL_NT | X86_EFL_IOPL);
764 break;
765 }
766 case IEMMODE_32BIT:
767 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
768 if (rcStrict != VINF_SUCCESS)
769 return rcStrict;
770 break;
771 case IEMMODE_64BIT:
772 {
773 uint64_t u64Value;
774 rcStrict = iemMemStackPopU64(pVCpu, &u64Value);
775 if (rcStrict != VINF_SUCCESS)
776 return rcStrict;
777 fEflNew = u64Value; /** @todo testcase: Check exactly what happens if high bits are set. */
778 break;
779 }
780 IEM_NOT_REACHED_DEFAULT_CASE_RET();
781 }
782
783 /* Merge them with the current flags. */
784 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
785 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
786 if ( (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
787 || pVCpu->iem.s.uCpl == 0)
788 {
789 fEflNew &= fPopfBits;
790 fEflNew |= ~fPopfBits & fEflOld;
791 }
792 else if (pVCpu->iem.s.uCpl <= X86_EFL_GET_IOPL(fEflOld))
793 {
794 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
795 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
796 }
797 else
798 {
799 fEflNew &= fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF);
800 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
801 }
802 }
803
804 /*
805 * Commit the flags.
806 */
807 Assert(fEflNew & RT_BIT_32(1));
808 IEMMISC_SET_EFL(pVCpu, fEflNew);
809 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
810
811 return VINF_SUCCESS;
812}
813
814
815/**
816 * Implements an indirect call.
817 *
818 * @param uNewPC The new program counter (RIP) value (loaded from the
819 * operand).
820 */
821IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
822{
823 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
824 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
825 return iemRaiseGeneralProtectionFault0(pVCpu);
826
827 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
828 if (rcStrict != VINF_SUCCESS)
829 return rcStrict;
830
831 pVCpu->cpum.GstCtx.rip = uNewPC;
832 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
833
834#ifndef IEM_WITH_CODE_TLB
835 /* Flush the prefetch buffer. */
836 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
837#endif
838 return VINF_SUCCESS;
839}
840
841
842/**
843 * Implements a 16-bit relative call.
844 *
845 * @param offDisp The displacment offset.
846 */
847IEM_CIMPL_DEF_1(iemCImpl_call_rel_16, int16_t, offDisp)
848{
849 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
850 uint16_t uNewPC = uOldPC + offDisp;
851 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
852 return iemRaiseGeneralProtectionFault0(pVCpu);
853
854 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
855 if (rcStrict != VINF_SUCCESS)
856 return rcStrict;
857
858 pVCpu->cpum.GstCtx.rip = uNewPC;
859 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
860
861#ifndef IEM_WITH_CODE_TLB
862 /* Flush the prefetch buffer. */
863 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
864#endif
865 return VINF_SUCCESS;
866}
867
868
869/**
870 * Implements a 32-bit indirect call.
871 *
872 * @param uNewPC The new program counter (RIP) value (loaded from the
873 * operand).
874 */
875IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
876{
877 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
878 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
879 return iemRaiseGeneralProtectionFault0(pVCpu);
880
881 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
882 if (rcStrict != VINF_SUCCESS)
883 return rcStrict;
884
885 pVCpu->cpum.GstCtx.rip = uNewPC;
886 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
887
888#ifndef IEM_WITH_CODE_TLB
889 /* Flush the prefetch buffer. */
890 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
891#endif
892 return VINF_SUCCESS;
893}
894
895
896/**
897 * Implements a 32-bit relative call.
898 *
899 * @param offDisp The displacment offset.
900 */
901IEM_CIMPL_DEF_1(iemCImpl_call_rel_32, int32_t, offDisp)
902{
903 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
904 uint32_t uNewPC = uOldPC + offDisp;
905 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
906 return iemRaiseGeneralProtectionFault0(pVCpu);
907
908 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
909 if (rcStrict != VINF_SUCCESS)
910 return rcStrict;
911
912 pVCpu->cpum.GstCtx.rip = uNewPC;
913 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
914
915#ifndef IEM_WITH_CODE_TLB
916 /* Flush the prefetch buffer. */
917 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
918#endif
919 return VINF_SUCCESS;
920}
921
922
923/**
924 * Implements a 64-bit indirect call.
925 *
926 * @param uNewPC The new program counter (RIP) value (loaded from the
927 * operand).
928 */
929IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
930{
931 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
932 if (!IEM_IS_CANONICAL(uNewPC))
933 return iemRaiseGeneralProtectionFault0(pVCpu);
934
935 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
936 if (rcStrict != VINF_SUCCESS)
937 return rcStrict;
938
939 pVCpu->cpum.GstCtx.rip = uNewPC;
940 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
941
942#ifndef IEM_WITH_CODE_TLB
943 /* Flush the prefetch buffer. */
944 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
945#endif
946 return VINF_SUCCESS;
947}
948
949
950/**
951 * Implements a 64-bit relative call.
952 *
953 * @param offDisp The displacment offset.
954 */
955IEM_CIMPL_DEF_1(iemCImpl_call_rel_64, int64_t, offDisp)
956{
957 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
958 uint64_t uNewPC = uOldPC + offDisp;
959 if (!IEM_IS_CANONICAL(uNewPC))
960 return iemRaiseNotCanonical(pVCpu);
961
962 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
963 if (rcStrict != VINF_SUCCESS)
964 return rcStrict;
965
966 pVCpu->cpum.GstCtx.rip = uNewPC;
967 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
968
969#ifndef IEM_WITH_CODE_TLB
970 /* Flush the prefetch buffer. */
971 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
972#endif
973
974 return VINF_SUCCESS;
975}
976
977
978/**
979 * Implements far jumps and calls thru task segments (TSS).
980 *
981 * @param uSel The selector.
982 * @param enmBranch The kind of branching we're performing.
983 * @param enmEffOpSize The effective operand size.
984 * @param pDesc The descriptor corresponding to @a uSel. The type is
985 * task gate.
986 */
987IEM_CIMPL_DEF_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
988{
989#ifndef IEM_IMPLEMENTS_TASKSWITCH
990 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
991#else
992 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
993 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL
994 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
995 RT_NOREF_PV(enmEffOpSize);
996 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
997
998 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
999 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1000 {
1001 Log(("BranchTaskSegment invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1002 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1003 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1004 }
1005
1006 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1007 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1008 * checked here, need testcases. */
1009 if (!pDesc->Legacy.Gen.u1Present)
1010 {
1011 Log(("BranchTaskSegment TSS not present uSel=%04x -> #NP\n", uSel));
1012 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1013 }
1014
1015 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
1016 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1017 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSel, pDesc);
1018#endif
1019}
1020
1021
1022/**
1023 * Implements far jumps and calls thru task gates.
1024 *
1025 * @param uSel The selector.
1026 * @param enmBranch The kind of branching we're performing.
1027 * @param enmEffOpSize The effective operand size.
1028 * @param pDesc The descriptor corresponding to @a uSel. The type is
1029 * task gate.
1030 */
1031IEM_CIMPL_DEF_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1032{
1033#ifndef IEM_IMPLEMENTS_TASKSWITCH
1034 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1035#else
1036 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1037 RT_NOREF_PV(enmEffOpSize);
1038 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1039
1040 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1041 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1042 {
1043 Log(("BranchTaskGate invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1044 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1045 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1046 }
1047
1048 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1049 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1050 * checked here, need testcases. */
1051 if (!pDesc->Legacy.Gen.u1Present)
1052 {
1053 Log(("BranchTaskSegment segment not present uSel=%04x -> #NP\n", uSel));
1054 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1055 }
1056
1057 /*
1058 * Fetch the new TSS descriptor from the GDT.
1059 */
1060 RTSEL uSelTss = pDesc->Legacy.Gate.u16Sel;
1061 if (uSelTss & X86_SEL_LDT)
1062 {
1063 Log(("BranchTaskGate TSS is in LDT. uSel=%04x uSelTss=%04x -> #GP\n", uSel, uSelTss));
1064 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1065 }
1066
1067 IEMSELDESC TssDesc;
1068 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelTss, X86_XCPT_GP);
1069 if (rcStrict != VINF_SUCCESS)
1070 return rcStrict;
1071
1072 if (TssDesc.Legacy.Gate.u4Type & X86_SEL_TYPE_SYS_TSS_BUSY_MASK)
1073 {
1074 Log(("BranchTaskGate TSS is busy. uSel=%04x uSelTss=%04x DescType=%#x -> #GP\n", uSel, uSelTss,
1075 TssDesc.Legacy.Gate.u4Type));
1076 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1077 }
1078
1079 if (!TssDesc.Legacy.Gate.u1Present)
1080 {
1081 Log(("BranchTaskGate TSS is not present. uSel=%04x uSelTss=%04x -> #NP\n", uSel, uSelTss));
1082 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelTss & X86_SEL_MASK_OFF_RPL);
1083 }
1084
1085 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
1086 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1087 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSelTss, &TssDesc);
1088#endif
1089}
1090
1091
1092/**
1093 * Implements far jumps and calls thru call gates.
1094 *
1095 * @param uSel The selector.
1096 * @param enmBranch The kind of branching we're performing.
1097 * @param enmEffOpSize The effective operand size.
1098 * @param pDesc The descriptor corresponding to @a uSel. The type is
1099 * call gate.
1100 */
1101IEM_CIMPL_DEF_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1102{
1103#define IEM_IMPLEMENTS_CALLGATE
1104#ifndef IEM_IMPLEMENTS_CALLGATE
1105 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1106#else
1107 RT_NOREF_PV(enmEffOpSize);
1108 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1109
1110 /* NB: Far jumps can only do intra-privilege transfers. Far calls support
1111 * inter-privilege calls and are much more complex.
1112 *
1113 * NB: 64-bit call gate has the same type as a 32-bit call gate! If
1114 * EFER.LMA=1, the gate must be 64-bit. Conversely if EFER.LMA=0, the gate
1115 * must be 16-bit or 32-bit.
1116 */
1117 /** @todo effective operand size is probably irrelevant here, only the
1118 * call gate bitness matters??
1119 */
1120 VBOXSTRICTRC rcStrict;
1121 RTPTRUNION uPtrRet;
1122 uint64_t uNewRsp;
1123 uint64_t uNewRip;
1124 uint64_t u64Base;
1125 uint32_t cbLimit;
1126 RTSEL uNewCS;
1127 IEMSELDESC DescCS;
1128
1129 AssertCompile(X86_SEL_TYPE_SYS_386_CALL_GATE == AMD64_SEL_TYPE_SYS_CALL_GATE);
1130 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1131 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE
1132 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE);
1133
1134 /* Determine the new instruction pointer from the gate descriptor. */
1135 uNewRip = pDesc->Legacy.Gate.u16OffsetLow
1136 | ((uint32_t)pDesc->Legacy.Gate.u16OffsetHigh << 16)
1137 | ((uint64_t)pDesc->Long.Gate.u32OffsetTop << 32);
1138
1139 /* Perform DPL checks on the gate descriptor. */
1140 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1141 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1142 {
1143 Log(("BranchCallGate invalid priv. uSel=%04x Gate DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1144 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1145 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1146 }
1147
1148 /** @todo does this catch NULL selectors, too? */
1149 if (!pDesc->Legacy.Gen.u1Present)
1150 {
1151 Log(("BranchCallGate Gate not present uSel=%04x -> #NP\n", uSel));
1152 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1153 }
1154
1155 /*
1156 * Fetch the target CS descriptor from the GDT or LDT.
1157 */
1158 uNewCS = pDesc->Legacy.Gate.u16Sel;
1159 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCS, X86_XCPT_GP);
1160 if (rcStrict != VINF_SUCCESS)
1161 return rcStrict;
1162
1163 /* Target CS must be a code selector. */
1164 if ( !DescCS.Legacy.Gen.u1DescType
1165 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
1166 {
1167 Log(("BranchCallGate %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
1168 uNewCS, uNewRip, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
1169 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1170 }
1171
1172 /* Privilege checks on target CS. */
1173 if (enmBranch == IEMBRANCH_JUMP)
1174 {
1175 if (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1176 {
1177 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1178 {
1179 Log(("BranchCallGate jump (conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1180 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1181 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1182 }
1183 }
1184 else
1185 {
1186 if (DescCS.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
1187 {
1188 Log(("BranchCallGate jump (non-conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1189 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1190 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1191 }
1192 }
1193 }
1194 else
1195 {
1196 Assert(enmBranch == IEMBRANCH_CALL);
1197 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1198 {
1199 Log(("BranchCallGate call invalid priv. uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1200 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1201 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
1202 }
1203 }
1204
1205 /* Additional long mode checks. */
1206 if (IEM_IS_LONG_MODE(pVCpu))
1207 {
1208 if (!DescCS.Legacy.Gen.u1Long)
1209 {
1210 Log(("BranchCallGate uNewCS %04x -> not a 64-bit code segment.\n", uNewCS));
1211 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1212 }
1213
1214 /* L vs D. */
1215 if ( DescCS.Legacy.Gen.u1Long
1216 && DescCS.Legacy.Gen.u1DefBig)
1217 {
1218 Log(("BranchCallGate uNewCS %04x -> both L and D are set.\n", uNewCS));
1219 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1220 }
1221 }
1222
1223 if (!DescCS.Legacy.Gate.u1Present)
1224 {
1225 Log(("BranchCallGate target CS is not present. uSel=%04x uNewCS=%04x -> #NP(CS)\n", uSel, uNewCS));
1226 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCS);
1227 }
1228
1229 if (enmBranch == IEMBRANCH_JUMP)
1230 {
1231 /** @todo This is very similar to regular far jumps; merge! */
1232 /* Jumps are fairly simple... */
1233
1234 /* Chop the high bits off if 16-bit gate (Intel says so). */
1235 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1236 uNewRip = (uint16_t)uNewRip;
1237
1238 /* Limit check for non-long segments. */
1239 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1240 if (DescCS.Legacy.Gen.u1Long)
1241 u64Base = 0;
1242 else
1243 {
1244 if (uNewRip > cbLimit)
1245 {
1246 Log(("BranchCallGate jump %04x:%08RX64 -> out of bounds (%#x) -> #GP(0)\n", uNewCS, uNewRip, cbLimit));
1247 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1248 }
1249 u64Base = X86DESC_BASE(&DescCS.Legacy);
1250 }
1251
1252 /* Canonical address check. */
1253 if (!IEM_IS_CANONICAL(uNewRip))
1254 {
1255 Log(("BranchCallGate jump %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1256 return iemRaiseNotCanonical(pVCpu);
1257 }
1258
1259 /*
1260 * Ok, everything checked out fine. Now set the accessed bit before
1261 * committing the result into CS, CSHID and RIP.
1262 */
1263 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1264 {
1265 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1266 if (rcStrict != VINF_SUCCESS)
1267 return rcStrict;
1268 /** @todo check what VT-x and AMD-V does. */
1269 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1270 }
1271
1272 /* commit */
1273 pVCpu->cpum.GstCtx.rip = uNewRip;
1274 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1275 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1276 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1277 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1278 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1279 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1280 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1281 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1282 }
1283 else
1284 {
1285 Assert(enmBranch == IEMBRANCH_CALL);
1286 /* Calls are much more complicated. */
1287
1288 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF) && (DescCS.Legacy.Gen.u2Dpl < pVCpu->iem.s.uCpl))
1289 {
1290 uint16_t offNewStack; /* Offset of new stack in TSS. */
1291 uint16_t cbNewStack; /* Number of bytes the stack information takes up in TSS. */
1292 uint8_t uNewCSDpl;
1293 uint8_t cbWords;
1294 RTSEL uNewSS;
1295 RTSEL uOldSS;
1296 uint64_t uOldRsp;
1297 IEMSELDESC DescSS;
1298 RTPTRUNION uPtrTSS;
1299 RTGCPTR GCPtrTSS;
1300 RTPTRUNION uPtrParmWds;
1301 RTGCPTR GCPtrParmWds;
1302
1303 /* More privilege. This is the fun part. */
1304 Assert(!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)); /* Filtered out above. */
1305
1306 /*
1307 * Determine new SS:rSP from the TSS.
1308 */
1309 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
1310
1311 /* Figure out where the new stack pointer is stored in the TSS. */
1312 uNewCSDpl = DescCS.Legacy.Gen.u2Dpl;
1313 if (!IEM_IS_LONG_MODE(pVCpu))
1314 {
1315 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1316 {
1317 offNewStack = RT_UOFFSETOF(X86TSS32, esp0) + uNewCSDpl * 8;
1318 cbNewStack = RT_SIZEOFMEMB(X86TSS32, esp0) + RT_SIZEOFMEMB(X86TSS32, ss0);
1319 }
1320 else
1321 {
1322 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1323 offNewStack = RT_UOFFSETOF(X86TSS16, sp0) + uNewCSDpl * 4;
1324 cbNewStack = RT_SIZEOFMEMB(X86TSS16, sp0) + RT_SIZEOFMEMB(X86TSS16, ss0);
1325 }
1326 }
1327 else
1328 {
1329 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1330 offNewStack = RT_UOFFSETOF(X86TSS64, rsp0) + uNewCSDpl * RT_SIZEOFMEMB(X86TSS64, rsp0);
1331 cbNewStack = RT_SIZEOFMEMB(X86TSS64, rsp0);
1332 }
1333
1334 /* Check against TSS limit. */
1335 if ((uint16_t)(offNewStack + cbNewStack - 1) > pVCpu->cpum.GstCtx.tr.u32Limit)
1336 {
1337 Log(("BranchCallGate inner stack past TSS limit - %u > %u -> #TS(TSS)\n", offNewStack + cbNewStack - 1, pVCpu->cpum.GstCtx.tr.u32Limit));
1338 return iemRaiseTaskSwitchFaultBySelector(pVCpu, pVCpu->cpum.GstCtx.tr.Sel);
1339 }
1340
1341 GCPtrTSS = pVCpu->cpum.GstCtx.tr.u64Base + offNewStack;
1342 rcStrict = iemMemMap(pVCpu, &uPtrTSS.pv, cbNewStack, UINT8_MAX, GCPtrTSS, IEM_ACCESS_SYS_R, 0);
1343 if (rcStrict != VINF_SUCCESS)
1344 {
1345 Log(("BranchCallGate: TSS mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1346 return rcStrict;
1347 }
1348
1349 if (!IEM_IS_LONG_MODE(pVCpu))
1350 {
1351 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1352 {
1353 uNewRsp = uPtrTSS.pu32[0];
1354 uNewSS = uPtrTSS.pu16[2];
1355 }
1356 else
1357 {
1358 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1359 uNewRsp = uPtrTSS.pu16[0];
1360 uNewSS = uPtrTSS.pu16[1];
1361 }
1362 }
1363 else
1364 {
1365 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1366 /* SS will be a NULL selector, but that's valid. */
1367 uNewRsp = uPtrTSS.pu64[0];
1368 uNewSS = uNewCSDpl;
1369 }
1370
1371 /* Done with the TSS now. */
1372 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrTSS.pv, IEM_ACCESS_SYS_R);
1373 if (rcStrict != VINF_SUCCESS)
1374 {
1375 Log(("BranchCallGate: TSS unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1376 return rcStrict;
1377 }
1378
1379 /* Only used outside of long mode. */
1380 cbWords = pDesc->Legacy.Gate.u5ParmCount;
1381
1382 /* If EFER.LMA is 0, there's extra work to do. */
1383 if (!IEM_IS_LONG_MODE(pVCpu))
1384 {
1385 if ((uNewSS & X86_SEL_MASK_OFF_RPL) == 0)
1386 {
1387 Log(("BranchCallGate new SS NULL -> #TS(NewSS)\n"));
1388 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1389 }
1390
1391 /* Grab the new SS descriptor. */
1392 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1393 if (rcStrict != VINF_SUCCESS)
1394 return rcStrict;
1395
1396 /* Ensure that CS.DPL == SS.RPL == SS.DPL. */
1397 if ( (DescCS.Legacy.Gen.u2Dpl != (uNewSS & X86_SEL_RPL))
1398 || (DescCS.Legacy.Gen.u2Dpl != DescSS.Legacy.Gen.u2Dpl))
1399 {
1400 Log(("BranchCallGate call bad RPL/DPL uNewSS=%04x SS DPL=%d CS DPL=%u -> #TS(NewSS)\n",
1401 uNewSS, DescCS.Legacy.Gen.u2Dpl, DescCS.Legacy.Gen.u2Dpl));
1402 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1403 }
1404
1405 /* Ensure new SS is a writable data segment. */
1406 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
1407 {
1408 Log(("BranchCallGate call new SS -> not a writable data selector (u4Type=%#x)\n", DescSS.Legacy.Gen.u4Type));
1409 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1410 }
1411
1412 if (!DescSS.Legacy.Gen.u1Present)
1413 {
1414 Log(("BranchCallGate New stack not present uSel=%04x -> #SS(NewSS)\n", uNewSS));
1415 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
1416 }
1417 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1418 cbNewStack = (uint16_t)sizeof(uint32_t) * (4 + cbWords);
1419 else
1420 cbNewStack = (uint16_t)sizeof(uint16_t) * (4 + cbWords);
1421 }
1422 else
1423 {
1424 /* Just grab the new (NULL) SS descriptor. */
1425 /** @todo testcase: Check whether the zero GDT entry is actually loaded here
1426 * like we do... */
1427 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1428 if (rcStrict != VINF_SUCCESS)
1429 return rcStrict;
1430
1431 cbNewStack = sizeof(uint64_t) * 4;
1432 }
1433
1434 /** @todo According to Intel, new stack is checked for enough space first,
1435 * then switched. According to AMD, the stack is switched first and
1436 * then pushes might fault!
1437 * NB: OS/2 Warp 3/4 actively relies on the fact that possible
1438 * incoming stack \#PF happens before actual stack switch. AMD is
1439 * either lying or implicitly assumes that new state is committed
1440 * only if and when an instruction doesn't fault.
1441 */
1442
1443 /** @todo According to AMD, CS is loaded first, then SS.
1444 * According to Intel, it's the other way around!?
1445 */
1446
1447 /** @todo Intel and AMD disagree on when exactly the CPL changes! */
1448
1449 /* Set the accessed bit before committing new SS. */
1450 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1451 {
1452 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
1453 if (rcStrict != VINF_SUCCESS)
1454 return rcStrict;
1455 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1456 }
1457
1458 /* Remember the old SS:rSP and their linear address. */
1459 uOldSS = pVCpu->cpum.GstCtx.ss.Sel;
1460 uOldRsp = pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig ? pVCpu->cpum.GstCtx.rsp : pVCpu->cpum.GstCtx.sp;
1461
1462 GCPtrParmWds = pVCpu->cpum.GstCtx.ss.u64Base + uOldRsp;
1463
1464 /* HACK ALERT! Probe if the write to the new stack will succeed. May #SS(NewSS)
1465 or #PF, the former is not implemented in this workaround. */
1466 /** @todo Proper fix callgate target stack exceptions. */
1467 /** @todo testcase: Cover callgates with partially or fully inaccessible
1468 * target stacks. */
1469 void *pvNewFrame;
1470 RTGCPTR GCPtrNewStack = X86DESC_BASE(&DescSS.Legacy) + uNewRsp - cbNewStack;
1471 rcStrict = iemMemMap(pVCpu, &pvNewFrame, cbNewStack, UINT8_MAX, GCPtrNewStack, IEM_ACCESS_SYS_RW, 0);
1472 if (rcStrict != VINF_SUCCESS)
1473 {
1474 Log(("BranchCallGate: Incoming stack (%04x:%08RX64) not accessible, rc=%Rrc\n", uNewSS, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
1475 return rcStrict;
1476 }
1477 rcStrict = iemMemCommitAndUnmap(pVCpu, pvNewFrame, IEM_ACCESS_SYS_RW);
1478 if (rcStrict != VINF_SUCCESS)
1479 {
1480 Log(("BranchCallGate: New stack probe unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1481 return rcStrict;
1482 }
1483
1484 /* Commit new SS:rSP. */
1485 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
1486 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
1487 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
1488 pVCpu->cpum.GstCtx.ss.u32Limit = X86DESC_LIMIT_G(&DescSS.Legacy);
1489 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
1490 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
1491 pVCpu->cpum.GstCtx.rsp = uNewRsp;
1492 pVCpu->iem.s.uCpl = uNewCSDpl; /** @todo is the parameter words accessed using the new CPL or the old CPL? */
1493 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
1494 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
1495
1496 /* At this point the stack access must not fail because new state was already committed. */
1497 /** @todo this can still fail due to SS.LIMIT not check. */
1498 rcStrict = iemMemStackPushBeginSpecial(pVCpu, cbNewStack,
1499 IEM_IS_LONG_MODE(pVCpu) ? 7
1500 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 3 : 1,
1501 &uPtrRet.pv, &uNewRsp);
1502 AssertMsgReturn(rcStrict == VINF_SUCCESS, ("BranchCallGate: New stack mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)),
1503 VERR_INTERNAL_ERROR_5);
1504
1505 if (!IEM_IS_LONG_MODE(pVCpu))
1506 {
1507 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1508 {
1509 if (cbWords)
1510 {
1511 /* Map the relevant chunk of the old stack. */
1512 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 4, UINT8_MAX, GCPtrParmWds,
1513 IEM_ACCESS_DATA_R, 0 /** @todo Can uNewCSDpl == 3? Then we need alignment mask here! */);
1514 if (rcStrict != VINF_SUCCESS)
1515 {
1516 Log(("BranchCallGate: Old stack mapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1517 return rcStrict;
1518 }
1519
1520 /* Copy the parameter (d)words. */
1521 for (int i = 0; i < cbWords; ++i)
1522 uPtrRet.pu32[2 + i] = uPtrParmWds.pu32[i];
1523
1524 /* Unmap the old stack. */
1525 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1526 if (rcStrict != VINF_SUCCESS)
1527 {
1528 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1529 return rcStrict;
1530 }
1531 }
1532
1533 /* Push the old CS:rIP. */
1534 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1535 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1536
1537 /* Push the old SS:rSP. */
1538 uPtrRet.pu32[2 + cbWords + 0] = uOldRsp;
1539 uPtrRet.pu32[2 + cbWords + 1] = uOldSS;
1540 }
1541 else
1542 {
1543 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1544
1545 if (cbWords)
1546 {
1547 /* Map the relevant chunk of the old stack. */
1548 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 2, UINT8_MAX, GCPtrParmWds,
1549 IEM_ACCESS_DATA_R, 0 /** @todo Can uNewCSDpl == 3? Then we need alignment mask here! */);
1550 if (rcStrict != VINF_SUCCESS)
1551 {
1552 Log(("BranchCallGate: Old stack mapping (16-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1553 return rcStrict;
1554 }
1555
1556 /* Copy the parameter words. */
1557 for (int i = 0; i < cbWords; ++i)
1558 uPtrRet.pu16[2 + i] = uPtrParmWds.pu16[i];
1559
1560 /* Unmap the old stack. */
1561 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1562 if (rcStrict != VINF_SUCCESS)
1563 {
1564 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1565 return rcStrict;
1566 }
1567 }
1568
1569 /* Push the old CS:rIP. */
1570 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1571 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1572
1573 /* Push the old SS:rSP. */
1574 uPtrRet.pu16[2 + cbWords + 0] = uOldRsp;
1575 uPtrRet.pu16[2 + cbWords + 1] = uOldSS;
1576 }
1577 }
1578 else
1579 {
1580 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1581
1582 /* For 64-bit gates, no parameters are copied. Just push old SS:rSP and CS:rIP. */
1583 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1584 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1585 uPtrRet.pu64[2] = uOldRsp;
1586 uPtrRet.pu64[3] = uOldSS; /** @todo Testcase: What is written to the high words when pushing SS? */
1587 }
1588
1589 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1590 if (rcStrict != VINF_SUCCESS)
1591 {
1592 Log(("BranchCallGate: New stack unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1593 return rcStrict;
1594 }
1595
1596 /* Chop the high bits off if 16-bit gate (Intel says so). */
1597 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1598 uNewRip = (uint16_t)uNewRip;
1599
1600 /* Limit / canonical check. */
1601 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1602 if (!IEM_IS_LONG_MODE(pVCpu))
1603 {
1604 if (uNewRip > cbLimit)
1605 {
1606 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1607 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1608 }
1609 u64Base = X86DESC_BASE(&DescCS.Legacy);
1610 }
1611 else
1612 {
1613 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1614 if (!IEM_IS_CANONICAL(uNewRip))
1615 {
1616 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1617 return iemRaiseNotCanonical(pVCpu);
1618 }
1619 u64Base = 0;
1620 }
1621
1622 /*
1623 * Now set the accessed bit before
1624 * writing the return address to the stack and committing the result into
1625 * CS, CSHID and RIP.
1626 */
1627 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1628 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1629 {
1630 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1631 if (rcStrict != VINF_SUCCESS)
1632 return rcStrict;
1633 /** @todo check what VT-x and AMD-V does. */
1634 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1635 }
1636
1637 /* Commit new CS:rIP. */
1638 pVCpu->cpum.GstCtx.rip = uNewRip;
1639 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1640 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1641 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1642 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1643 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1644 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1645 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1646 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1647 }
1648 else
1649 {
1650 /* Same privilege. */
1651 /** @todo This is very similar to regular far calls; merge! */
1652
1653 /* Check stack first - may #SS(0). */
1654 /** @todo check how gate size affects pushing of CS! Does callf 16:32 in
1655 * 16-bit code cause a two or four byte CS to be pushed? */
1656 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
1657 IEM_IS_LONG_MODE(pVCpu) ? 8+8
1658 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 4+4 : 2+2,
1659 IEM_IS_LONG_MODE(pVCpu) ? 7
1660 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 3 : 2,
1661 &uPtrRet.pv, &uNewRsp);
1662 if (rcStrict != VINF_SUCCESS)
1663 return rcStrict;
1664
1665 /* Chop the high bits off if 16-bit gate (Intel says so). */
1666 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1667 uNewRip = (uint16_t)uNewRip;
1668
1669 /* Limit / canonical check. */
1670 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1671 if (!IEM_IS_LONG_MODE(pVCpu))
1672 {
1673 if (uNewRip > cbLimit)
1674 {
1675 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1676 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1677 }
1678 u64Base = X86DESC_BASE(&DescCS.Legacy);
1679 }
1680 else
1681 {
1682 if (!IEM_IS_CANONICAL(uNewRip))
1683 {
1684 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1685 return iemRaiseNotCanonical(pVCpu);
1686 }
1687 u64Base = 0;
1688 }
1689
1690 /*
1691 * Now set the accessed bit before
1692 * writing the return address to the stack and committing the result into
1693 * CS, CSHID and RIP.
1694 */
1695 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1696 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1697 {
1698 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1699 if (rcStrict != VINF_SUCCESS)
1700 return rcStrict;
1701 /** @todo check what VT-x and AMD-V does. */
1702 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1703 }
1704
1705 /* stack */
1706 if (!IEM_IS_LONG_MODE(pVCpu))
1707 {
1708 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1709 {
1710 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1711 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1712 }
1713 else
1714 {
1715 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1716 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1717 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1718 }
1719 }
1720 else
1721 {
1722 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1723 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1724 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1725 }
1726
1727 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1728 if (rcStrict != VINF_SUCCESS)
1729 return rcStrict;
1730
1731 /* commit */
1732 pVCpu->cpum.GstCtx.rip = uNewRip;
1733 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1734 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1735 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1736 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1737 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1738 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1739 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1740 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1741 }
1742 }
1743 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1744
1745 /* Flush the prefetch buffer. */
1746# ifdef IEM_WITH_CODE_TLB
1747 pVCpu->iem.s.pbInstrBuf = NULL;
1748# else
1749 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1750# endif
1751 return VINF_SUCCESS;
1752#endif
1753}
1754
1755
1756/**
1757 * Implements far jumps and calls thru system selectors.
1758 *
1759 * @param uSel The selector.
1760 * @param enmBranch The kind of branching we're performing.
1761 * @param enmEffOpSize The effective operand size.
1762 * @param pDesc The descriptor corresponding to @a uSel.
1763 */
1764IEM_CIMPL_DEF_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1765{
1766 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1767 Assert((uSel & X86_SEL_MASK_OFF_RPL));
1768 IEM_CTX_IMPORT_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1769
1770 if (IEM_IS_LONG_MODE(pVCpu))
1771 switch (pDesc->Legacy.Gen.u4Type)
1772 {
1773 case AMD64_SEL_TYPE_SYS_CALL_GATE:
1774 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1775
1776 default:
1777 case AMD64_SEL_TYPE_SYS_LDT:
1778 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
1779 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
1780 case AMD64_SEL_TYPE_SYS_TRAP_GATE:
1781 case AMD64_SEL_TYPE_SYS_INT_GATE:
1782 Log(("branch %04x -> wrong sys selector (64-bit): %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1783 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1784 }
1785
1786 switch (pDesc->Legacy.Gen.u4Type)
1787 {
1788 case X86_SEL_TYPE_SYS_286_CALL_GATE:
1789 case X86_SEL_TYPE_SYS_386_CALL_GATE:
1790 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1791
1792 case X86_SEL_TYPE_SYS_TASK_GATE:
1793 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskGate, uSel, enmBranch, enmEffOpSize, pDesc);
1794
1795 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1796 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1797 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskSegment, uSel, enmBranch, enmEffOpSize, pDesc);
1798
1799 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1800 Log(("branch %04x -> busy 286 TSS\n", uSel));
1801 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1802
1803 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1804 Log(("branch %04x -> busy 386 TSS\n", uSel));
1805 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1806
1807 default:
1808 case X86_SEL_TYPE_SYS_LDT:
1809 case X86_SEL_TYPE_SYS_286_INT_GATE:
1810 case X86_SEL_TYPE_SYS_286_TRAP_GATE:
1811 case X86_SEL_TYPE_SYS_386_INT_GATE:
1812 case X86_SEL_TYPE_SYS_386_TRAP_GATE:
1813 Log(("branch %04x -> wrong sys selector: %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1814 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1815 }
1816}
1817
1818
1819/**
1820 * Implements far jumps.
1821 *
1822 * @param uSel The selector.
1823 * @param offSeg The segment offset.
1824 * @param enmEffOpSize The effective operand size.
1825 */
1826IEM_CIMPL_DEF_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1827{
1828 NOREF(cbInstr);
1829 Assert(offSeg <= UINT32_MAX);
1830
1831 /*
1832 * Real mode and V8086 mode are easy. The only snag seems to be that
1833 * CS.limit doesn't change and the limit check is done against the current
1834 * limit.
1835 */
1836 /** @todo Robert Collins claims (The Segment Descriptor Cache, DDJ August
1837 * 1998) that up to and including the Intel 486, far control
1838 * transfers in real mode set default CS attributes (0x93) and also
1839 * set a 64K segment limit. Starting with the Pentium, the
1840 * attributes and limit are left alone but the access rights are
1841 * ignored. We only implement the Pentium+ behavior.
1842 * */
1843 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
1844 {
1845 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1846 if (offSeg > pVCpu->cpum.GstCtx.cs.u32Limit)
1847 {
1848 Log(("iemCImpl_FarJmp: 16-bit limit\n"));
1849 return iemRaiseGeneralProtectionFault0(pVCpu);
1850 }
1851
1852 if (enmEffOpSize == IEMMODE_16BIT) /** @todo WRONG, must pass this. */
1853 pVCpu->cpum.GstCtx.rip = offSeg;
1854 else
1855 pVCpu->cpum.GstCtx.rip = offSeg & UINT16_MAX;
1856 pVCpu->cpum.GstCtx.cs.Sel = uSel;
1857 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
1858 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1859 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
1860 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1861 return VINF_SUCCESS;
1862 }
1863
1864 /*
1865 * Protected mode. Need to parse the specified descriptor...
1866 */
1867 if (!(uSel & X86_SEL_MASK_OFF_RPL))
1868 {
1869 Log(("jmpf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
1870 return iemRaiseGeneralProtectionFault0(pVCpu);
1871 }
1872
1873 /* Fetch the descriptor. */
1874 IEMSELDESC Desc;
1875 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
1876 if (rcStrict != VINF_SUCCESS)
1877 return rcStrict;
1878
1879 /* Is it there? */
1880 if (!Desc.Legacy.Gen.u1Present) /** @todo this is probably checked too early. Testcase! */
1881 {
1882 Log(("jmpf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
1883 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1884 }
1885
1886 /*
1887 * Deal with it according to its type. We do the standard code selectors
1888 * here and dispatch the system selectors to worker functions.
1889 */
1890 if (!Desc.Legacy.Gen.u1DescType)
1891 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_JUMP, enmEffOpSize, &Desc);
1892
1893 /* Only code segments. */
1894 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1895 {
1896 Log(("jmpf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
1897 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1898 }
1899
1900 /* L vs D. */
1901 if ( Desc.Legacy.Gen.u1Long
1902 && Desc.Legacy.Gen.u1DefBig
1903 && IEM_IS_LONG_MODE(pVCpu))
1904 {
1905 Log(("jmpf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
1906 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1907 }
1908
1909 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
1910 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1911 {
1912 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
1913 {
1914 Log(("jmpf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
1915 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1916 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1917 }
1918 }
1919 else
1920 {
1921 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
1922 {
1923 Log(("jmpf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1924 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1925 }
1926 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
1927 {
1928 Log(("jmpf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
1929 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1930 }
1931 }
1932
1933 /* Chop the high bits if 16-bit (Intel says so). */
1934 if (enmEffOpSize == IEMMODE_16BIT)
1935 offSeg &= UINT16_MAX;
1936
1937 /* Limit check. (Should alternatively check for non-canonical addresses
1938 here, but that is ruled out by offSeg being 32-bit, right?) */
1939 uint64_t u64Base;
1940 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
1941 if (Desc.Legacy.Gen.u1Long)
1942 u64Base = 0;
1943 else
1944 {
1945 if (offSeg > cbLimit)
1946 {
1947 Log(("jmpf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
1948 /** @todo Intel says this is \#GP(0)! */
1949 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1950 }
1951 u64Base = X86DESC_BASE(&Desc.Legacy);
1952 }
1953
1954 /*
1955 * Ok, everything checked out fine. Now set the accessed bit before
1956 * committing the result into CS, CSHID and RIP.
1957 */
1958 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1959 {
1960 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
1961 if (rcStrict != VINF_SUCCESS)
1962 return rcStrict;
1963 /** @todo check what VT-x and AMD-V does. */
1964 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1965 }
1966
1967 /* commit */
1968 pVCpu->cpum.GstCtx.rip = offSeg;
1969 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
1970 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1971 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1972 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1973 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
1974 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1975 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1976 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1977 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1978 /** @todo check if the hidden bits are loaded correctly for 64-bit
1979 * mode. */
1980
1981 /* Flush the prefetch buffer. */
1982#ifdef IEM_WITH_CODE_TLB
1983 pVCpu->iem.s.pbInstrBuf = NULL;
1984#else
1985 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1986#endif
1987
1988 return VINF_SUCCESS;
1989}
1990
1991
1992/**
1993 * Implements far calls.
1994 *
1995 * This very similar to iemCImpl_FarJmp.
1996 *
1997 * @param uSel The selector.
1998 * @param offSeg The segment offset.
1999 * @param enmEffOpSize The operand size (in case we need it).
2000 */
2001IEM_CIMPL_DEF_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
2002{
2003 VBOXSTRICTRC rcStrict;
2004 uint64_t uNewRsp;
2005 RTPTRUNION uPtrRet;
2006
2007 /*
2008 * Real mode and V8086 mode are easy. The only snag seems to be that
2009 * CS.limit doesn't change and the limit check is done against the current
2010 * limit.
2011 */
2012 /** @todo See comment for similar code in iemCImpl_FarJmp */
2013 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2014 {
2015 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
2016
2017 /* Check stack first - may #SS(0). */
2018 rcStrict = iemMemStackPushBeginSpecial(pVCpu, enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2019 enmEffOpSize == IEMMODE_32BIT ? 3 : 1,
2020 &uPtrRet.pv, &uNewRsp);
2021 if (rcStrict != VINF_SUCCESS)
2022 return rcStrict;
2023
2024 /* Check the target address range. */
2025 if (offSeg > UINT32_MAX)
2026 return iemRaiseGeneralProtectionFault0(pVCpu);
2027
2028 /* Everything is fine, push the return address. */
2029 if (enmEffOpSize == IEMMODE_16BIT)
2030 {
2031 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2032 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2033 }
2034 else
2035 {
2036 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2037 uPtrRet.pu16[2] = pVCpu->cpum.GstCtx.cs.Sel;
2038 }
2039 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2040 if (rcStrict != VINF_SUCCESS)
2041 return rcStrict;
2042
2043 /* Branch. */
2044 pVCpu->cpum.GstCtx.rip = offSeg;
2045 pVCpu->cpum.GstCtx.cs.Sel = uSel;
2046 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
2047 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2048 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
2049 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2050 return VINF_SUCCESS;
2051 }
2052
2053 /*
2054 * Protected mode. Need to parse the specified descriptor...
2055 */
2056 if (!(uSel & X86_SEL_MASK_OFF_RPL))
2057 {
2058 Log(("callf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
2059 return iemRaiseGeneralProtectionFault0(pVCpu);
2060 }
2061
2062 /* Fetch the descriptor. */
2063 IEMSELDESC Desc;
2064 rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
2065 if (rcStrict != VINF_SUCCESS)
2066 return rcStrict;
2067
2068 /*
2069 * Deal with it according to its type. We do the standard code selectors
2070 * here and dispatch the system selectors to worker functions.
2071 */
2072 if (!Desc.Legacy.Gen.u1DescType)
2073 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_CALL, enmEffOpSize, &Desc);
2074
2075 /* Only code segments. */
2076 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
2077 {
2078 Log(("callf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
2079 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2080 }
2081
2082 /* L vs D. */
2083 if ( Desc.Legacy.Gen.u1Long
2084 && Desc.Legacy.Gen.u1DefBig
2085 && IEM_IS_LONG_MODE(pVCpu))
2086 {
2087 Log(("callf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
2088 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2089 }
2090
2091 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
2092 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2093 {
2094 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
2095 {
2096 Log(("callf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
2097 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2098 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2099 }
2100 }
2101 else
2102 {
2103 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
2104 {
2105 Log(("callf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2106 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2107 }
2108 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
2109 {
2110 Log(("callf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
2111 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2112 }
2113 }
2114
2115 /* Is it there? */
2116 if (!Desc.Legacy.Gen.u1Present)
2117 {
2118 Log(("callf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
2119 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
2120 }
2121
2122 /* Check stack first - may #SS(0). */
2123 /** @todo check how operand prefix affects pushing of CS! Does callf 16:32 in
2124 * 16-bit code cause a two or four byte CS to be pushed? */
2125 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
2126 enmEffOpSize == IEMMODE_64BIT ? 8+8 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2127 enmEffOpSize == IEMMODE_64BIT ? 7 : enmEffOpSize == IEMMODE_32BIT ? 3 : 1,
2128 &uPtrRet.pv, &uNewRsp);
2129 if (rcStrict != VINF_SUCCESS)
2130 return rcStrict;
2131
2132 /* Chop the high bits if 16-bit (Intel says so). */
2133 if (enmEffOpSize == IEMMODE_16BIT)
2134 offSeg &= UINT16_MAX;
2135
2136 /* Limit / canonical check. */
2137 uint64_t u64Base;
2138 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
2139 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2140 {
2141 if (!IEM_IS_CANONICAL(offSeg))
2142 {
2143 Log(("callf %04x:%016RX64 - not canonical -> #GP\n", uSel, offSeg));
2144 return iemRaiseNotCanonical(pVCpu);
2145 }
2146 u64Base = 0;
2147 }
2148 else
2149 {
2150 if (offSeg > cbLimit)
2151 {
2152 Log(("callf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
2153 /** @todo Intel says this is \#GP(0)! */
2154 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2155 }
2156 u64Base = X86DESC_BASE(&Desc.Legacy);
2157 }
2158
2159 /*
2160 * Now set the accessed bit before
2161 * writing the return address to the stack and committing the result into
2162 * CS, CSHID and RIP.
2163 */
2164 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2165 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2166 {
2167 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
2168 if (rcStrict != VINF_SUCCESS)
2169 return rcStrict;
2170 /** @todo check what VT-x and AMD-V does. */
2171 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2172 }
2173
2174 /* stack */
2175 if (enmEffOpSize == IEMMODE_16BIT)
2176 {
2177 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2178 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2179 }
2180 else if (enmEffOpSize == IEMMODE_32BIT)
2181 {
2182 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2183 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
2184 }
2185 else
2186 {
2187 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
2188 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
2189 }
2190 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2191 if (rcStrict != VINF_SUCCESS)
2192 return rcStrict;
2193
2194 /* commit */
2195 pVCpu->cpum.GstCtx.rip = offSeg;
2196 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
2197 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
2198 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
2199 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2200 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
2201 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
2202 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2203 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2204 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2205 /** @todo check if the hidden bits are loaded correctly for 64-bit
2206 * mode. */
2207
2208 /* Flush the prefetch buffer. */
2209#ifdef IEM_WITH_CODE_TLB
2210 pVCpu->iem.s.pbInstrBuf = NULL;
2211#else
2212 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2213#endif
2214 return VINF_SUCCESS;
2215}
2216
2217
2218/**
2219 * Implements retf.
2220 *
2221 * @param enmEffOpSize The effective operand size.
2222 * @param cbPop The amount of arguments to pop from the stack
2223 * (bytes).
2224 */
2225IEM_CIMPL_DEF_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2226{
2227 VBOXSTRICTRC rcStrict;
2228 RTCPTRUNION uPtrFrame;
2229 uint64_t uNewRsp;
2230 uint64_t uNewRip;
2231 uint16_t uNewCs;
2232 NOREF(cbInstr);
2233
2234 /*
2235 * Read the stack values first.
2236 */
2237 uint32_t cbRetPtr = enmEffOpSize == IEMMODE_16BIT ? 2+2
2238 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 8+8;
2239 rcStrict = iemMemStackPopBeginSpecial(pVCpu, cbRetPtr,
2240 enmEffOpSize == IEMMODE_16BIT ? 1 : enmEffOpSize == IEMMODE_32BIT ? 3 : 7,
2241 &uPtrFrame.pv, &uNewRsp);
2242 if (rcStrict != VINF_SUCCESS)
2243 return rcStrict;
2244 if (enmEffOpSize == IEMMODE_16BIT)
2245 {
2246 uNewRip = uPtrFrame.pu16[0];
2247 uNewCs = uPtrFrame.pu16[1];
2248 }
2249 else if (enmEffOpSize == IEMMODE_32BIT)
2250 {
2251 uNewRip = uPtrFrame.pu32[0];
2252 uNewCs = uPtrFrame.pu16[2];
2253 }
2254 else
2255 {
2256 uNewRip = uPtrFrame.pu64[0];
2257 uNewCs = uPtrFrame.pu16[4];
2258 }
2259 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2260 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2261 { /* extremely likely */ }
2262 else
2263 return rcStrict;
2264
2265 /*
2266 * Real mode and V8086 mode are easy.
2267 */
2268 /** @todo See comment for similar code in iemCImpl_FarJmp */
2269 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2270 {
2271 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2272 /** @todo check how this is supposed to work if sp=0xfffe. */
2273
2274 /* Check the limit of the new EIP. */
2275 /** @todo Intel pseudo code only does the limit check for 16-bit
2276 * operands, AMD does not make any distinction. What is right? */
2277 if (uNewRip > pVCpu->cpum.GstCtx.cs.u32Limit)
2278 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2279
2280 /* commit the operation. */
2281 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2282 pVCpu->cpum.GstCtx.rip = uNewRip;
2283 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2284 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2285 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2286 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
2287 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2288 if (cbPop)
2289 iemRegAddToRsp(pVCpu, cbPop);
2290 return VINF_SUCCESS;
2291 }
2292
2293 /*
2294 * Protected mode is complicated, of course.
2295 */
2296 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
2297 {
2298 Log(("retf %04x:%08RX64 -> invalid selector, #GP(0)\n", uNewCs, uNewRip));
2299 return iemRaiseGeneralProtectionFault0(pVCpu);
2300 }
2301
2302 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
2303
2304 /* Fetch the descriptor. */
2305 IEMSELDESC DescCs;
2306 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCs, uNewCs, X86_XCPT_GP);
2307 if (rcStrict != VINF_SUCCESS)
2308 return rcStrict;
2309
2310 /* Can only return to a code selector. */
2311 if ( !DescCs.Legacy.Gen.u1DescType
2312 || !(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
2313 {
2314 Log(("retf %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
2315 uNewCs, uNewRip, DescCs.Legacy.Gen.u1DescType, DescCs.Legacy.Gen.u4Type));
2316 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2317 }
2318
2319 /* L vs D. */
2320 if ( DescCs.Legacy.Gen.u1Long /** @todo Testcase: far return to a selector with both L and D set. */
2321 && DescCs.Legacy.Gen.u1DefBig
2322 && IEM_IS_LONG_MODE(pVCpu))
2323 {
2324 Log(("retf %04x:%08RX64 -> both L & D set.\n", uNewCs, uNewRip));
2325 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2326 }
2327
2328 /* DPL/RPL/CPL checks. */
2329 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
2330 {
2331 Log(("retf %04x:%08RX64 -> RPL < CPL(%d).\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
2332 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2333 }
2334
2335 if (DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2336 {
2337 if ((uNewCs & X86_SEL_RPL) < DescCs.Legacy.Gen.u2Dpl)
2338 {
2339 Log(("retf %04x:%08RX64 -> DPL violation (conforming); DPL=%u RPL=%u\n",
2340 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2341 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2342 }
2343 }
2344 else
2345 {
2346 if ((uNewCs & X86_SEL_RPL) != DescCs.Legacy.Gen.u2Dpl)
2347 {
2348 Log(("retf %04x:%08RX64 -> RPL != DPL; DPL=%u RPL=%u\n",
2349 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2350 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2351 }
2352 }
2353
2354 /* Is it there? */
2355 if (!DescCs.Legacy.Gen.u1Present)
2356 {
2357 Log(("retf %04x:%08RX64 -> segment not present\n", uNewCs, uNewRip));
2358 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2359 }
2360
2361 /*
2362 * Return to outer privilege? (We'll typically have entered via a call gate.)
2363 */
2364 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
2365 {
2366 /* Read the outer stack pointer stored *after* the parameters. */
2367 rcStrict = iemMemStackPopContinueSpecial(pVCpu, cbPop /*off*/, cbRetPtr, &uPtrFrame.pv, uNewRsp);
2368 if (rcStrict != VINF_SUCCESS)
2369 return rcStrict;
2370
2371 uint16_t uNewOuterSs;
2372 uint64_t uNewOuterRsp;
2373 if (enmEffOpSize == IEMMODE_16BIT)
2374 {
2375 uNewOuterRsp = uPtrFrame.pu16[0];
2376 uNewOuterSs = uPtrFrame.pu16[1];
2377 }
2378 else if (enmEffOpSize == IEMMODE_32BIT)
2379 {
2380 uNewOuterRsp = uPtrFrame.pu32[0];
2381 uNewOuterSs = uPtrFrame.pu16[2];
2382 }
2383 else
2384 {
2385 uNewOuterRsp = uPtrFrame.pu64[0];
2386 uNewOuterSs = uPtrFrame.pu16[4];
2387 }
2388 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2389 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2390 { /* extremely likely */ }
2391 else
2392 return rcStrict;
2393
2394 /* Check for NULL stack selector (invalid in ring-3 and non-long mode)
2395 and read the selector. */
2396 IEMSELDESC DescSs;
2397 if (!(uNewOuterSs & X86_SEL_MASK_OFF_RPL))
2398 {
2399 if ( !DescCs.Legacy.Gen.u1Long
2400 || (uNewOuterSs & X86_SEL_RPL) == 3)
2401 {
2402 Log(("retf %04x:%08RX64 %04x:%08RX64 -> invalid stack selector, #GP\n",
2403 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2404 return iemRaiseGeneralProtectionFault0(pVCpu);
2405 }
2406 /** @todo Testcase: Return far to ring-1 or ring-2 with SS=0. */
2407 iemMemFakeStackSelDesc(&DescSs, (uNewOuterSs & X86_SEL_RPL));
2408 }
2409 else
2410 {
2411 /* Fetch the descriptor for the new stack segment. */
2412 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSs, uNewOuterSs, X86_XCPT_GP);
2413 if (rcStrict != VINF_SUCCESS)
2414 return rcStrict;
2415 }
2416
2417 /* Check that RPL of stack and code selectors match. */
2418 if ((uNewCs & X86_SEL_RPL) != (uNewOuterSs & X86_SEL_RPL))
2419 {
2420 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.RPL != CS.RPL -> #GP(SS)\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2421 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2422 }
2423
2424 /* Must be a writable data segment. */
2425 if ( !DescSs.Legacy.Gen.u1DescType
2426 || (DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
2427 || !(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
2428 {
2429 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not a writable data segment (u1DescType=%u u4Type=%#x) -> #GP(SS).\n",
2430 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u1DescType, DescSs.Legacy.Gen.u4Type));
2431 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2432 }
2433
2434 /* L vs D. (Not mentioned by intel.) */
2435 if ( DescSs.Legacy.Gen.u1Long /** @todo Testcase: far return to a stack selector with both L and D set. */
2436 && DescSs.Legacy.Gen.u1DefBig
2437 && IEM_IS_LONG_MODE(pVCpu))
2438 {
2439 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS has both L & D set -> #GP(SS).\n",
2440 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2441 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2442 }
2443
2444 /* DPL/RPL/CPL checks. */
2445 if (DescSs.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
2446 {
2447 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.DPL(%u) != CS.RPL (%u) -> #GP(SS).\n",
2448 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u2Dpl, uNewCs & X86_SEL_RPL));
2449 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2450 }
2451
2452 /* Is it there? */
2453 if (!DescSs.Legacy.Gen.u1Present)
2454 {
2455 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not present -> #NP(SS).\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2456 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2457 }
2458
2459 /* Calc SS limit.*/
2460 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSs.Legacy);
2461
2462 /* Is RIP canonical or within CS.limit? */
2463 uint64_t u64Base;
2464 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2465
2466 /** @todo Testcase: Is this correct? */
2467 if ( DescCs.Legacy.Gen.u1Long
2468 && IEM_IS_LONG_MODE(pVCpu) )
2469 {
2470 if (!IEM_IS_CANONICAL(uNewRip))
2471 {
2472 Log(("retf %04x:%08RX64 %04x:%08RX64 - not canonical -> #GP.\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2473 return iemRaiseNotCanonical(pVCpu);
2474 }
2475 u64Base = 0;
2476 }
2477 else
2478 {
2479 if (uNewRip > cbLimitCs)
2480 {
2481 Log(("retf %04x:%08RX64 %04x:%08RX64 - out of bounds (%#x)-> #GP(CS).\n",
2482 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, cbLimitCs));
2483 /** @todo Intel says this is \#GP(0)! */
2484 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2485 }
2486 u64Base = X86DESC_BASE(&DescCs.Legacy);
2487 }
2488
2489 /*
2490 * Now set the accessed bit before
2491 * writing the return address to the stack and committing the result into
2492 * CS, CSHID and RIP.
2493 */
2494 /** @todo Testcase: Need to check WHEN exactly the CS accessed bit is set. */
2495 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2496 {
2497 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2498 if (rcStrict != VINF_SUCCESS)
2499 return rcStrict;
2500 /** @todo check what VT-x and AMD-V does. */
2501 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2502 }
2503 /** @todo Testcase: Need to check WHEN exactly the SS accessed bit is set. */
2504 if (!(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2505 {
2506 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewOuterSs);
2507 if (rcStrict != VINF_SUCCESS)
2508 return rcStrict;
2509 /** @todo check what VT-x and AMD-V does. */
2510 DescSs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2511 }
2512
2513 /* commit */
2514 if (enmEffOpSize == IEMMODE_16BIT)
2515 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2516 else
2517 pVCpu->cpum.GstCtx.rip = uNewRip;
2518 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2519 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2520 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2521 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2522 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2523 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2524 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2525 pVCpu->cpum.GstCtx.ss.Sel = uNewOuterSs;
2526 pVCpu->cpum.GstCtx.ss.ValidSel = uNewOuterSs;
2527 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
2528 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSs.Legacy);
2529 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
2530 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2531 pVCpu->cpum.GstCtx.ss.u64Base = 0;
2532 else
2533 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSs.Legacy);
2534 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2535 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewOuterRsp;
2536 else
2537 pVCpu->cpum.GstCtx.rsp = uNewOuterRsp;
2538
2539 pVCpu->iem.s.uCpl = (uNewCs & X86_SEL_RPL);
2540 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
2541 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
2542 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
2543 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
2544
2545 /** @todo check if the hidden bits are loaded correctly for 64-bit
2546 * mode. */
2547
2548 if (cbPop)
2549 iemRegAddToRsp(pVCpu, cbPop);
2550 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2551
2552 /* Done! */
2553 }
2554 /*
2555 * Return to the same privilege level
2556 */
2557 else
2558 {
2559 /* Limit / canonical check. */
2560 uint64_t u64Base;
2561 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2562
2563 /** @todo Testcase: Is this correct? */
2564 if ( DescCs.Legacy.Gen.u1Long
2565 && IEM_IS_LONG_MODE(pVCpu) )
2566 {
2567 if (!IEM_IS_CANONICAL(uNewRip))
2568 {
2569 Log(("retf %04x:%08RX64 - not canonical -> #GP\n", uNewCs, uNewRip));
2570 return iemRaiseNotCanonical(pVCpu);
2571 }
2572 u64Base = 0;
2573 }
2574 else
2575 {
2576 if (uNewRip > cbLimitCs)
2577 {
2578 Log(("retf %04x:%08RX64 -> out of bounds (%#x)\n", uNewCs, uNewRip, cbLimitCs));
2579 /** @todo Intel says this is \#GP(0)! */
2580 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2581 }
2582 u64Base = X86DESC_BASE(&DescCs.Legacy);
2583 }
2584
2585 /*
2586 * Now set the accessed bit before
2587 * writing the return address to the stack and committing the result into
2588 * CS, CSHID and RIP.
2589 */
2590 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2591 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2592 {
2593 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2594 if (rcStrict != VINF_SUCCESS)
2595 return rcStrict;
2596 /** @todo check what VT-x and AMD-V does. */
2597 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2598 }
2599
2600 /* commit */
2601 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2602 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
2603 else
2604 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2605 if (enmEffOpSize == IEMMODE_16BIT)
2606 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2607 else
2608 pVCpu->cpum.GstCtx.rip = uNewRip;
2609 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2610 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2611 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2612 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2613 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2614 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2615 /** @todo check if the hidden bits are loaded correctly for 64-bit
2616 * mode. */
2617 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2618 if (cbPop)
2619 iemRegAddToRsp(pVCpu, cbPop);
2620 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2621 }
2622
2623 /* Flush the prefetch buffer. */
2624#ifdef IEM_WITH_CODE_TLB
2625 pVCpu->iem.s.pbInstrBuf = NULL;
2626#else
2627 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2628#endif
2629 return VINF_SUCCESS;
2630}
2631
2632
2633/**
2634 * Implements retn.
2635 *
2636 * We're doing this in C because of the \#GP that might be raised if the popped
2637 * program counter is out of bounds.
2638 *
2639 * @param enmEffOpSize The effective operand size.
2640 * @param cbPop The amount of arguments to pop from the stack
2641 * (bytes).
2642 */
2643IEM_CIMPL_DEF_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2644{
2645 NOREF(cbInstr);
2646
2647 /* Fetch the RSP from the stack. */
2648 VBOXSTRICTRC rcStrict;
2649 RTUINT64U NewRip;
2650 RTUINT64U NewRsp;
2651 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2652
2653 switch (enmEffOpSize)
2654 {
2655 case IEMMODE_16BIT:
2656 NewRip.u = 0;
2657 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRip.Words.w0, &NewRsp);
2658 break;
2659 case IEMMODE_32BIT:
2660 NewRip.u = 0;
2661 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRip.DWords.dw0, &NewRsp);
2662 break;
2663 case IEMMODE_64BIT:
2664 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRip.u, &NewRsp);
2665 break;
2666 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2667 }
2668 if (rcStrict != VINF_SUCCESS)
2669 return rcStrict;
2670
2671 /* Check the new RSP before loading it. */
2672 /** @todo Should test this as the intel+amd pseudo code doesn't mention half
2673 * of it. The canonical test is performed here and for call. */
2674 if (enmEffOpSize != IEMMODE_64BIT)
2675 {
2676 if (NewRip.DWords.dw0 > pVCpu->cpum.GstCtx.cs.u32Limit)
2677 {
2678 Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pVCpu->cpum.GstCtx.cs.u32Limit));
2679 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2680 }
2681 }
2682 else
2683 {
2684 if (!IEM_IS_CANONICAL(NewRip.u))
2685 {
2686 Log(("retn newrip=%llx - not canonical -> #GP\n", NewRip.u));
2687 return iemRaiseNotCanonical(pVCpu);
2688 }
2689 }
2690
2691 /* Apply cbPop */
2692 if (cbPop)
2693 iemRegAddToRspEx(pVCpu, &NewRsp, cbPop);
2694
2695 /* Commit it. */
2696 pVCpu->cpum.GstCtx.rip = NewRip.u;
2697 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2698 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2699
2700 /* Flush the prefetch buffer. */
2701#ifndef IEM_WITH_CODE_TLB
2702 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2703#endif
2704
2705 return VINF_SUCCESS;
2706}
2707
2708
2709/**
2710 * Implements enter.
2711 *
2712 * We're doing this in C because the instruction is insane, even for the
2713 * u8NestingLevel=0 case dealing with the stack is tedious.
2714 *
2715 * @param enmEffOpSize The effective operand size.
2716 * @param cbFrame Frame size.
2717 * @param cParameters Frame parameter count.
2718 */
2719IEM_CIMPL_DEF_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters)
2720{
2721 /* Push RBP, saving the old value in TmpRbp. */
2722 RTUINT64U NewRsp; NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2723 RTUINT64U TmpRbp; TmpRbp.u = pVCpu->cpum.GstCtx.rbp;
2724 RTUINT64U NewRbp;
2725 VBOXSTRICTRC rcStrict;
2726 if (enmEffOpSize == IEMMODE_64BIT)
2727 {
2728 rcStrict = iemMemStackPushU64Ex(pVCpu, TmpRbp.u, &NewRsp);
2729 NewRbp = NewRsp;
2730 }
2731 else if (enmEffOpSize == IEMMODE_32BIT)
2732 {
2733 rcStrict = iemMemStackPushU32Ex(pVCpu, TmpRbp.DWords.dw0, &NewRsp);
2734 NewRbp = NewRsp;
2735 }
2736 else
2737 {
2738 rcStrict = iemMemStackPushU16Ex(pVCpu, TmpRbp.Words.w0, &NewRsp);
2739 NewRbp = TmpRbp;
2740 NewRbp.Words.w0 = NewRsp.Words.w0;
2741 }
2742 if (rcStrict != VINF_SUCCESS)
2743 return rcStrict;
2744
2745 /* Copy the parameters (aka nesting levels by Intel). */
2746 cParameters &= 0x1f;
2747 if (cParameters > 0)
2748 {
2749 switch (enmEffOpSize)
2750 {
2751 case IEMMODE_16BIT:
2752 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2753 TmpRbp.DWords.dw0 -= 2;
2754 else
2755 TmpRbp.Words.w0 -= 2;
2756 do
2757 {
2758 uint16_t u16Tmp;
2759 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Tmp, &TmpRbp);
2760 if (rcStrict != VINF_SUCCESS)
2761 break;
2762 rcStrict = iemMemStackPushU16Ex(pVCpu, u16Tmp, &NewRsp);
2763 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2764 break;
2765
2766 case IEMMODE_32BIT:
2767 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2768 TmpRbp.DWords.dw0 -= 4;
2769 else
2770 TmpRbp.Words.w0 -= 4;
2771 do
2772 {
2773 uint32_t u32Tmp;
2774 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Tmp, &TmpRbp);
2775 if (rcStrict != VINF_SUCCESS)
2776 break;
2777 rcStrict = iemMemStackPushU32Ex(pVCpu, u32Tmp, &NewRsp);
2778 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2779 break;
2780
2781 case IEMMODE_64BIT:
2782 TmpRbp.u -= 8;
2783 do
2784 {
2785 uint64_t u64Tmp;
2786 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Tmp, &TmpRbp);
2787 if (rcStrict != VINF_SUCCESS)
2788 break;
2789 rcStrict = iemMemStackPushU64Ex(pVCpu, u64Tmp, &NewRsp);
2790 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2791 break;
2792
2793 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2794 }
2795 if (rcStrict != VINF_SUCCESS)
2796 return VINF_SUCCESS;
2797
2798 /* Push the new RBP */
2799 if (enmEffOpSize == IEMMODE_64BIT)
2800 rcStrict = iemMemStackPushU64Ex(pVCpu, NewRbp.u, &NewRsp);
2801 else if (enmEffOpSize == IEMMODE_32BIT)
2802 rcStrict = iemMemStackPushU32Ex(pVCpu, NewRbp.DWords.dw0, &NewRsp);
2803 else
2804 rcStrict = iemMemStackPushU16Ex(pVCpu, NewRbp.Words.w0, &NewRsp);
2805 if (rcStrict != VINF_SUCCESS)
2806 return rcStrict;
2807
2808 }
2809
2810 /* Recalc RSP. */
2811 iemRegSubFromRspEx(pVCpu, &NewRsp, cbFrame);
2812
2813 /** @todo Should probe write access at the new RSP according to AMD. */
2814 /** @todo Should handle accesses to the VMX APIC-access page. */
2815
2816 /* Commit it. */
2817 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2818 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2819 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2820
2821 return VINF_SUCCESS;
2822}
2823
2824
2825
2826/**
2827 * Implements leave.
2828 *
2829 * We're doing this in C because messing with the stack registers is annoying
2830 * since they depends on SS attributes.
2831 *
2832 * @param enmEffOpSize The effective operand size.
2833 */
2834IEM_CIMPL_DEF_1(iemCImpl_leave, IEMMODE, enmEffOpSize)
2835{
2836 /* Calculate the intermediate RSP from RBP and the stack attributes. */
2837 RTUINT64U NewRsp;
2838 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2839 NewRsp.u = pVCpu->cpum.GstCtx.rbp;
2840 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2841 NewRsp.u = pVCpu->cpum.GstCtx.ebp;
2842 else
2843 {
2844 /** @todo Check that LEAVE actually preserve the high EBP bits. */
2845 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2846 NewRsp.Words.w0 = pVCpu->cpum.GstCtx.bp;
2847 }
2848
2849 /* Pop RBP according to the operand size. */
2850 VBOXSTRICTRC rcStrict;
2851 RTUINT64U NewRbp;
2852 switch (enmEffOpSize)
2853 {
2854 case IEMMODE_16BIT:
2855 NewRbp.u = pVCpu->cpum.GstCtx.rbp;
2856 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRbp.Words.w0, &NewRsp);
2857 break;
2858 case IEMMODE_32BIT:
2859 NewRbp.u = 0;
2860 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRbp.DWords.dw0, &NewRsp);
2861 break;
2862 case IEMMODE_64BIT:
2863 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRbp.u, &NewRsp);
2864 break;
2865 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2866 }
2867 if (rcStrict != VINF_SUCCESS)
2868 return rcStrict;
2869
2870
2871 /* Commit it. */
2872 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2873 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2874 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2875
2876 return VINF_SUCCESS;
2877}
2878
2879
2880/**
2881 * Implements int3 and int XX.
2882 *
2883 * @param u8Int The interrupt vector number.
2884 * @param enmInt The int instruction type.
2885 */
2886IEM_CIMPL_DEF_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt)
2887{
2888 Assert(pVCpu->iem.s.cXcptRecursions == 0);
2889
2890 /*
2891 * We must check if this INT3 might belong to DBGF before raising a #BP.
2892 */
2893 if (u8Int == 3)
2894 {
2895 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2896 if (pVM->dbgf.ro.cEnabledInt3Breakpoints == 0)
2897 { /* likely: No vbox debugger breakpoints */ }
2898 else
2899 {
2900 VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx));
2901 Log(("iemCImpl_int: DBGFTrap03Handler -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict) ));
2902 if (rcStrict != VINF_EM_RAW_GUEST_TRAP)
2903 return iemSetPassUpStatus(pVCpu, rcStrict);
2904 }
2905 }
2906 return iemRaiseXcptOrInt(pVCpu,
2907 cbInstr,
2908 u8Int,
2909 IEM_XCPT_FLAGS_T_SOFT_INT | enmInt,
2910 0,
2911 0);
2912}
2913
2914
2915/**
2916 * Implements iret for real mode and V8086 mode.
2917 *
2918 * @param enmEffOpSize The effective operand size.
2919 */
2920IEM_CIMPL_DEF_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize)
2921{
2922 X86EFLAGS Efl;
2923 Efl.u = IEMMISC_GET_EFL(pVCpu);
2924 NOREF(cbInstr);
2925
2926 /*
2927 * iret throws an exception if VME isn't enabled.
2928 */
2929 if ( Efl.Bits.u1VM
2930 && Efl.Bits.u2IOPL != 3
2931 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
2932 return iemRaiseGeneralProtectionFault0(pVCpu);
2933
2934 /*
2935 * Do the stack bits, but don't commit RSP before everything checks
2936 * out right.
2937 */
2938 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2939 VBOXSTRICTRC rcStrict;
2940 RTCPTRUNION uFrame;
2941 uint16_t uNewCs;
2942 uint32_t uNewEip;
2943 uint32_t uNewFlags;
2944 uint64_t uNewRsp;
2945 if (enmEffOpSize == IEMMODE_32BIT)
2946 {
2947 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, 1, &uFrame.pv, &uNewRsp);
2948 if (rcStrict != VINF_SUCCESS)
2949 return rcStrict;
2950 uNewEip = uFrame.pu32[0];
2951 if (uNewEip > UINT16_MAX)
2952 return iemRaiseGeneralProtectionFault0(pVCpu);
2953
2954 uNewCs = (uint16_t)uFrame.pu32[1];
2955 uNewFlags = uFrame.pu32[2];
2956 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2957 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT
2958 | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
2959 | X86_EFL_ID;
2960 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
2961 uNewFlags &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
2962 uNewFlags |= Efl.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
2963 }
2964 else
2965 {
2966 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, 1, &uFrame.pv, &uNewRsp);
2967 if (rcStrict != VINF_SUCCESS)
2968 return rcStrict;
2969 uNewEip = uFrame.pu16[0];
2970 uNewCs = uFrame.pu16[1];
2971 uNewFlags = uFrame.pu16[2];
2972 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2973 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT;
2974 uNewFlags |= Efl.u & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF);
2975 /** @todo The intel pseudo code does not indicate what happens to
2976 * reserved flags. We just ignore them. */
2977 /* Ancient CPU adjustments: See iemCImpl_popf. */
2978 if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286)
2979 uNewFlags &= ~(X86_EFL_NT | X86_EFL_IOPL);
2980 }
2981 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uFrame.pv);
2982 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2983 { /* extremely likely */ }
2984 else
2985 return rcStrict;
2986
2987 /** @todo Check how this is supposed to work if sp=0xfffe. */
2988 Log7(("iemCImpl_iret_real_v8086: uNewCs=%#06x uNewRip=%#010x uNewFlags=%#x uNewRsp=%#18llx\n",
2989 uNewCs, uNewEip, uNewFlags, uNewRsp));
2990
2991 /*
2992 * Check the limit of the new EIP.
2993 */
2994 /** @todo Only the AMD pseudo code check the limit here, what's
2995 * right? */
2996 if (uNewEip > pVCpu->cpum.GstCtx.cs.u32Limit)
2997 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2998
2999 /*
3000 * V8086 checks and flag adjustments
3001 */
3002 if (Efl.Bits.u1VM)
3003 {
3004 if (Efl.Bits.u2IOPL == 3)
3005 {
3006 /* Preserve IOPL and clear RF. */
3007 uNewFlags &= ~(X86_EFL_IOPL | X86_EFL_RF);
3008 uNewFlags |= Efl.u & (X86_EFL_IOPL);
3009 }
3010 else if ( enmEffOpSize == IEMMODE_16BIT
3011 && ( !(uNewFlags & X86_EFL_IF)
3012 || !Efl.Bits.u1VIP )
3013 && !(uNewFlags & X86_EFL_TF) )
3014 {
3015 /* Move IF to VIF, clear RF and preserve IF and IOPL.*/
3016 uNewFlags &= ~X86_EFL_VIF;
3017 uNewFlags |= (uNewFlags & X86_EFL_IF) << (19 - 9);
3018 uNewFlags &= ~(X86_EFL_IF | X86_EFL_IOPL | X86_EFL_RF);
3019 uNewFlags |= Efl.u & (X86_EFL_IF | X86_EFL_IOPL);
3020 }
3021 else
3022 return iemRaiseGeneralProtectionFault0(pVCpu);
3023 Log7(("iemCImpl_iret_real_v8086: u1VM=1: adjusted uNewFlags=%#x\n", uNewFlags));
3024 }
3025
3026 /*
3027 * Commit the operation.
3028 */
3029#ifdef DBGFTRACE_ENABLED
3030 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/rm %04x:%04x -> %04x:%04x %x %04llx",
3031 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewRsp);
3032#endif
3033 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3034 pVCpu->cpum.GstCtx.rip = uNewEip;
3035 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3036 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3037 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3038 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
3039 /** @todo do we load attribs and limit as well? */
3040 Assert(uNewFlags & X86_EFL_1);
3041 IEMMISC_SET_EFL(pVCpu, uNewFlags);
3042
3043 /* Flush the prefetch buffer. */
3044#ifdef IEM_WITH_CODE_TLB
3045 pVCpu->iem.s.pbInstrBuf = NULL;
3046#else
3047 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3048#endif
3049
3050 return VINF_SUCCESS;
3051}
3052
3053
3054/**
3055 * Loads a segment register when entering V8086 mode.
3056 *
3057 * @param pSReg The segment register.
3058 * @param uSeg The segment to load.
3059 */
3060static void iemCImplCommonV8086LoadSeg(PCPUMSELREG pSReg, uint16_t uSeg)
3061{
3062 pSReg->Sel = uSeg;
3063 pSReg->ValidSel = uSeg;
3064 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
3065 pSReg->u64Base = (uint32_t)uSeg << 4;
3066 pSReg->u32Limit = 0xffff;
3067 pSReg->Attr.u = X86_SEL_TYPE_RW_ACC | RT_BIT(4) /*!sys*/ | RT_BIT(7) /*P*/ | (3 /*DPL*/ << 5); /* VT-x wants 0xf3 */
3068 /** @todo Testcase: Check if VT-x really needs this and what it does itself when
3069 * IRET'ing to V8086. */
3070}
3071
3072
3073/**
3074 * Implements iret for protected mode returning to V8086 mode.
3075 *
3076 * @param uNewEip The new EIP.
3077 * @param uNewCs The new CS.
3078 * @param uNewFlags The new EFLAGS.
3079 * @param uNewRsp The RSP after the initial IRET frame.
3080 *
3081 * @note This can only be a 32-bit iret du to the X86_EFL_VM position.
3082 */
3083IEM_CIMPL_DEF_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp)
3084{
3085 RT_NOREF_PV(cbInstr);
3086 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
3087
3088 /*
3089 * Pop the V8086 specific frame bits off the stack.
3090 */
3091 VBOXSTRICTRC rcStrict;
3092 RTCPTRUNION uFrame;
3093 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0 /*off*/, 24 /*cbMem*/, &uFrame.pv, uNewRsp);
3094 if (rcStrict != VINF_SUCCESS)
3095 return rcStrict;
3096 uint32_t uNewEsp = uFrame.pu32[0];
3097 uint16_t uNewSs = uFrame.pu32[1];
3098 uint16_t uNewEs = uFrame.pu32[2];
3099 uint16_t uNewDs = uFrame.pu32[3];
3100 uint16_t uNewFs = uFrame.pu32[4];
3101 uint16_t uNewGs = uFrame.pu32[5];
3102 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
3103 if (rcStrict != VINF_SUCCESS)
3104 return rcStrict;
3105
3106 /*
3107 * Commit the operation.
3108 */
3109 uNewFlags &= X86_EFL_LIVE_MASK;
3110 uNewFlags |= X86_EFL_RA1_MASK;
3111#ifdef DBGFTRACE_ENABLED
3112 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/p/v %04x:%08x -> %04x:%04x %x %04x:%04x",
3113 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp);
3114#endif
3115 Log7(("iemCImpl_iret_prot_v8086: %04x:%08x -> %04x:%04x %x %04x:%04x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp));
3116
3117 IEMMISC_SET_EFL(pVCpu, uNewFlags);
3118 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.cs, uNewCs);
3119 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ss, uNewSs);
3120 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.es, uNewEs);
3121 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ds, uNewDs);
3122 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.fs, uNewFs);
3123 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.gs, uNewGs);
3124 pVCpu->cpum.GstCtx.rip = (uint16_t)uNewEip;
3125 pVCpu->cpum.GstCtx.rsp = uNewEsp; /** @todo check this out! */
3126 pVCpu->iem.s.uCpl = 3;
3127
3128 /* Flush the prefetch buffer. */
3129#ifdef IEM_WITH_CODE_TLB
3130 pVCpu->iem.s.pbInstrBuf = NULL;
3131#else
3132 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3133#endif
3134
3135 return VINF_SUCCESS;
3136}
3137
3138
3139/**
3140 * Implements iret for protected mode returning via a nested task.
3141 *
3142 * @param enmEffOpSize The effective operand size.
3143 */
3144IEM_CIMPL_DEF_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize)
3145{
3146 Log7(("iemCImpl_iret_prot_NestedTask:\n"));
3147#ifndef IEM_IMPLEMENTS_TASKSWITCH
3148 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
3149#else
3150 RT_NOREF_PV(enmEffOpSize);
3151
3152 /*
3153 * Read the segment selector in the link-field of the current TSS.
3154 */
3155 RTSEL uSelRet;
3156 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &uSelRet, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base);
3157 if (rcStrict != VINF_SUCCESS)
3158 return rcStrict;
3159
3160 /*
3161 * Fetch the returning task's TSS descriptor from the GDT.
3162 */
3163 if (uSelRet & X86_SEL_LDT)
3164 {
3165 Log(("iret_prot_NestedTask TSS not in LDT. uSelRet=%04x -> #TS\n", uSelRet));
3166 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet);
3167 }
3168
3169 IEMSELDESC TssDesc;
3170 rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelRet, X86_XCPT_GP);
3171 if (rcStrict != VINF_SUCCESS)
3172 return rcStrict;
3173
3174 if (TssDesc.Legacy.Gate.u1DescType)
3175 {
3176 Log(("iret_prot_NestedTask Invalid TSS type. uSelRet=%04x -> #TS\n", uSelRet));
3177 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3178 }
3179
3180 if ( TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_286_TSS_BUSY
3181 && TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
3182 {
3183 Log(("iret_prot_NestedTask TSS is not busy. uSelRet=%04x DescType=%#x -> #TS\n", uSelRet, TssDesc.Legacy.Gate.u4Type));
3184 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3185 }
3186
3187 if (!TssDesc.Legacy.Gate.u1Present)
3188 {
3189 Log(("iret_prot_NestedTask TSS is not present. uSelRet=%04x -> #NP\n", uSelRet));
3190 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3191 }
3192
3193 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
3194 return iemTaskSwitch(pVCpu, IEMTASKSWITCH_IRET, uNextEip, 0 /* fFlags */, 0 /* uErr */,
3195 0 /* uCr2 */, uSelRet, &TssDesc);
3196#endif
3197}
3198
3199
3200/**
3201 * Implements iret for protected mode
3202 *
3203 * @param enmEffOpSize The effective operand size.
3204 */
3205IEM_CIMPL_DEF_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize)
3206{
3207 NOREF(cbInstr);
3208 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3209
3210 /*
3211 * Nested task return.
3212 */
3213 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3214 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot_NestedTask, enmEffOpSize);
3215
3216 /*
3217 * Normal return.
3218 *
3219 * Do the stack bits, but don't commit RSP before everything checks
3220 * out right.
3221 */
3222 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3223 VBOXSTRICTRC rcStrict;
3224 RTCPTRUNION uFrame;
3225 uint16_t uNewCs;
3226 uint32_t uNewEip;
3227 uint32_t uNewFlags;
3228 uint64_t uNewRsp;
3229 if (enmEffOpSize == IEMMODE_32BIT)
3230 {
3231 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, 3, &uFrame.pv, &uNewRsp);
3232 if (rcStrict != VINF_SUCCESS)
3233 return rcStrict;
3234 uNewEip = uFrame.pu32[0];
3235 uNewCs = (uint16_t)uFrame.pu32[1];
3236 uNewFlags = uFrame.pu32[2];
3237 }
3238 else
3239 {
3240 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, 1, &uFrame.pv, &uNewRsp);
3241 if (rcStrict != VINF_SUCCESS)
3242 return rcStrict;
3243 uNewEip = uFrame.pu16[0];
3244 uNewCs = uFrame.pu16[1];
3245 uNewFlags = uFrame.pu16[2];
3246 }
3247 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3248 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3249 { /* extremely likely */ }
3250 else
3251 return rcStrict;
3252 Log7(("iemCImpl_iret_prot: uNewCs=%#06x uNewEip=%#010x uNewFlags=%#x uNewRsp=%#18llx uCpl=%u\n", uNewCs, uNewEip, uNewFlags, uNewRsp, pVCpu->iem.s.uCpl));
3253
3254 /*
3255 * We're hopefully not returning to V8086 mode...
3256 */
3257 if ( (uNewFlags & X86_EFL_VM)
3258 && pVCpu->iem.s.uCpl == 0)
3259 {
3260 Assert(enmEffOpSize == IEMMODE_32BIT);
3261 return IEM_CIMPL_CALL_4(iemCImpl_iret_prot_v8086, uNewEip, uNewCs, uNewFlags, uNewRsp);
3262 }
3263
3264 /*
3265 * Protected mode.
3266 */
3267 /* Read the CS descriptor. */
3268 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3269 {
3270 Log(("iret %04x:%08x -> invalid CS selector, #GP(0)\n", uNewCs, uNewEip));
3271 return iemRaiseGeneralProtectionFault0(pVCpu);
3272 }
3273
3274 IEMSELDESC DescCS;
3275 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3276 if (rcStrict != VINF_SUCCESS)
3277 {
3278 Log(("iret %04x:%08x - rcStrict=%Rrc when fetching CS\n", uNewCs, uNewEip, VBOXSTRICTRC_VAL(rcStrict)));
3279 return rcStrict;
3280 }
3281
3282 /* Must be a code descriptor. */
3283 if (!DescCS.Legacy.Gen.u1DescType)
3284 {
3285 Log(("iret %04x:%08x - CS is system segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3286 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3287 }
3288 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3289 {
3290 Log(("iret %04x:%08x - not code segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3291 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3292 }
3293
3294 /* Privilege checks. */
3295 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3296 {
3297 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3298 {
3299 Log(("iret %04x:%08x - RPL != DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3300 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3301 }
3302 }
3303 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3304 {
3305 Log(("iret %04x:%08x - RPL < DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3306 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3307 }
3308 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3309 {
3310 Log(("iret %04x:%08x - RPL < CPL (%d) -> #GP\n", uNewCs, uNewEip, pVCpu->iem.s.uCpl));
3311 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3312 }
3313
3314 /* Present? */
3315 if (!DescCS.Legacy.Gen.u1Present)
3316 {
3317 Log(("iret %04x:%08x - CS not present -> #NP\n", uNewCs, uNewEip));
3318 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3319 }
3320
3321 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3322
3323 /*
3324 * Return to outer level?
3325 */
3326 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
3327 {
3328 uint16_t uNewSS;
3329 uint32_t uNewESP;
3330 if (enmEffOpSize == IEMMODE_32BIT)
3331 {
3332 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0/*off*/, 8 /*cbMem*/, &uFrame.pv, uNewRsp);
3333 if (rcStrict != VINF_SUCCESS)
3334 return rcStrict;
3335/** @todo We might be popping a 32-bit ESP from the IRET frame, but whether
3336 * 16-bit or 32-bit are being loaded into SP depends on the D/B
3337 * bit of the popped SS selector it turns out. */
3338 uNewESP = uFrame.pu32[0];
3339 uNewSS = (uint16_t)uFrame.pu32[1];
3340 }
3341 else
3342 {
3343 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0 /*off*/, 4 /*cbMem*/, &uFrame.pv, uNewRsp);
3344 if (rcStrict != VINF_SUCCESS)
3345 return rcStrict;
3346 uNewESP = uFrame.pu16[0];
3347 uNewSS = uFrame.pu16[1];
3348 }
3349 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R);
3350 if (rcStrict != VINF_SUCCESS)
3351 return rcStrict;
3352 Log7(("iemCImpl_iret_prot: uNewSS=%#06x uNewESP=%#010x\n", uNewSS, uNewESP));
3353
3354 /* Read the SS descriptor. */
3355 if (!(uNewSS & X86_SEL_MASK_OFF_RPL))
3356 {
3357 Log(("iret %04x:%08x/%04x:%08x -> invalid SS selector, #GP(0)\n", uNewCs, uNewEip, uNewSS, uNewESP));
3358 return iemRaiseGeneralProtectionFault0(pVCpu);
3359 }
3360
3361 IEMSELDESC DescSS;
3362 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_GP); /** @todo Correct exception? */
3363 if (rcStrict != VINF_SUCCESS)
3364 {
3365 Log(("iret %04x:%08x/%04x:%08x - %Rrc when fetching SS\n",
3366 uNewCs, uNewEip, uNewSS, uNewESP, VBOXSTRICTRC_VAL(rcStrict)));
3367 return rcStrict;
3368 }
3369
3370 /* Privilege checks. */
3371 if ((uNewSS & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3372 {
3373 Log(("iret %04x:%08x/%04x:%08x -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewEip, uNewSS, uNewESP));
3374 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3375 }
3376 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3377 {
3378 Log(("iret %04x:%08x/%04x:%08x -> SS.DPL (%d) != CS.RPL -> #GP\n",
3379 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u2Dpl));
3380 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3381 }
3382
3383 /* Must be a writeable data segment descriptor. */
3384 if (!DescSS.Legacy.Gen.u1DescType)
3385 {
3386 Log(("iret %04x:%08x/%04x:%08x -> SS is system segment (%#x) -> #GP\n",
3387 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3388 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3389 }
3390 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3391 {
3392 Log(("iret %04x:%08x/%04x:%08x - not writable data segment (%#x) -> #GP\n",
3393 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3394 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3395 }
3396
3397 /* Present? */
3398 if (!DescSS.Legacy.Gen.u1Present)
3399 {
3400 Log(("iret %04x:%08x/%04x:%08x -> SS not present -> #SS\n", uNewCs, uNewEip, uNewSS, uNewESP));
3401 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
3402 }
3403
3404 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3405
3406 /* Check EIP. */
3407 if (uNewEip > cbLimitCS)
3408 {
3409 Log(("iret %04x:%08x/%04x:%08x -> EIP is out of bounds (%#x) -> #GP(0)\n",
3410 uNewCs, uNewEip, uNewSS, uNewESP, cbLimitCS));
3411 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3412 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3413 }
3414
3415 /*
3416 * Commit the changes, marking CS and SS accessed first since
3417 * that may fail.
3418 */
3419 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3420 {
3421 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3422 if (rcStrict != VINF_SUCCESS)
3423 return rcStrict;
3424 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3425 }
3426 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3427 {
3428 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
3429 if (rcStrict != VINF_SUCCESS)
3430 return rcStrict;
3431 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3432 }
3433
3434 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3435 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3436 if (enmEffOpSize != IEMMODE_16BIT)
3437 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3438 if (pVCpu->iem.s.uCpl == 0)
3439 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3440 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3441 fEFlagsMask |= X86_EFL_IF;
3442 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3443 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3444 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3445 fEFlagsNew &= ~fEFlagsMask;
3446 fEFlagsNew |= uNewFlags & fEFlagsMask;
3447#ifdef DBGFTRACE_ENABLED
3448 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up%u %04x:%08x -> %04x:%04x %x %04x:%04x",
3449 pVCpu->iem.s.uCpl, uNewCs & X86_SEL_RPL, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3450 uNewCs, uNewEip, uNewFlags, uNewSS, uNewESP);
3451#endif
3452
3453 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3454 pVCpu->cpum.GstCtx.rip = uNewEip;
3455 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3456 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3457 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3458 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3459 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3460 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3461 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3462
3463 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
3464 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
3465 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3466 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3467 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3468 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3469 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3470 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewESP;
3471 else
3472 pVCpu->cpum.GstCtx.rsp = uNewESP;
3473
3474 pVCpu->iem.s.uCpl = uNewCs & X86_SEL_RPL;
3475 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
3476 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
3477 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
3478 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
3479
3480 /* Done! */
3481
3482 }
3483 /*
3484 * Return to the same level.
3485 */
3486 else
3487 {
3488 /* Check EIP. */
3489 if (uNewEip > cbLimitCS)
3490 {
3491 Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCs, uNewEip, cbLimitCS));
3492 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3493 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3494 }
3495
3496 /*
3497 * Commit the changes, marking CS first since it may fail.
3498 */
3499 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3500 {
3501 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3502 if (rcStrict != VINF_SUCCESS)
3503 return rcStrict;
3504 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3505 }
3506
3507 X86EFLAGS NewEfl;
3508 NewEfl.u = IEMMISC_GET_EFL(pVCpu);
3509 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3510 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3511 if (enmEffOpSize != IEMMODE_16BIT)
3512 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3513 if (pVCpu->iem.s.uCpl == 0)
3514 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3515 else if (pVCpu->iem.s.uCpl <= NewEfl.Bits.u2IOPL)
3516 fEFlagsMask |= X86_EFL_IF;
3517 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3518 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3519 NewEfl.u &= ~fEFlagsMask;
3520 NewEfl.u |= fEFlagsMask & uNewFlags;
3521#ifdef DBGFTRACE_ENABLED
3522 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up %04x:%08x -> %04x:%04x %x %04x:%04llx",
3523 pVCpu->iem.s.uCpl, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3524 uNewCs, uNewEip, uNewFlags, pVCpu->cpum.GstCtx.ss.Sel, uNewRsp);
3525#endif
3526
3527 IEMMISC_SET_EFL(pVCpu, NewEfl.u);
3528 pVCpu->cpum.GstCtx.rip = uNewEip;
3529 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3530 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3531 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3532 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3533 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3534 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3535 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3536 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3537 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3538 else
3539 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3540 /* Done! */
3541 }
3542
3543 /* Flush the prefetch buffer. */
3544#ifdef IEM_WITH_CODE_TLB
3545 pVCpu->iem.s.pbInstrBuf = NULL;
3546#else
3547 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3548#endif
3549
3550 return VINF_SUCCESS;
3551}
3552
3553
3554/**
3555 * Implements iret for long mode
3556 *
3557 * @param enmEffOpSize The effective operand size.
3558 */
3559IEM_CIMPL_DEF_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize)
3560{
3561 NOREF(cbInstr);
3562
3563 /*
3564 * Nested task return is not supported in long mode.
3565 */
3566 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3567 {
3568 Log(("iretq with NT=1 (eflags=%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.eflags.u));
3569 return iemRaiseGeneralProtectionFault0(pVCpu);
3570 }
3571
3572 /*
3573 * Normal return.
3574 *
3575 * Do the stack bits, but don't commit RSP before everything checks
3576 * out right.
3577 */
3578 VBOXSTRICTRC rcStrict;
3579 RTCPTRUNION uFrame;
3580 uint64_t uNewRip;
3581 uint16_t uNewCs;
3582 uint16_t uNewSs;
3583 uint32_t uNewFlags;
3584 uint64_t uNewRsp;
3585 if (enmEffOpSize == IEMMODE_64BIT)
3586 {
3587 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*8, 7, &uFrame.pv, &uNewRsp);
3588 if (rcStrict != VINF_SUCCESS)
3589 return rcStrict;
3590 uNewRip = uFrame.pu64[0];
3591 uNewCs = (uint16_t)uFrame.pu64[1];
3592 uNewFlags = (uint32_t)uFrame.pu64[2];
3593 uNewRsp = uFrame.pu64[3];
3594 uNewSs = (uint16_t)uFrame.pu64[4];
3595 }
3596 else if (enmEffOpSize == IEMMODE_32BIT)
3597 {
3598 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*4, 3, &uFrame.pv, &uNewRsp);
3599 if (rcStrict != VINF_SUCCESS)
3600 return rcStrict;
3601 uNewRip = uFrame.pu32[0];
3602 uNewCs = (uint16_t)uFrame.pu32[1];
3603 uNewFlags = uFrame.pu32[2];
3604 uNewRsp = uFrame.pu32[3];
3605 uNewSs = (uint16_t)uFrame.pu32[4];
3606 }
3607 else
3608 {
3609 Assert(enmEffOpSize == IEMMODE_16BIT);
3610 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*2, 1, &uFrame.pv, &uNewRsp);
3611 if (rcStrict != VINF_SUCCESS)
3612 return rcStrict;
3613 uNewRip = uFrame.pu16[0];
3614 uNewCs = uFrame.pu16[1];
3615 uNewFlags = uFrame.pu16[2];
3616 uNewRsp = uFrame.pu16[3];
3617 uNewSs = uFrame.pu16[4];
3618 }
3619 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3620 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3621 { /* extremely like */ }
3622 else
3623 return rcStrict;
3624 Log7(("iretq stack: cs:rip=%04x:%016RX64 rflags=%016RX64 ss:rsp=%04x:%016RX64\n", uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp));
3625
3626 /*
3627 * Check stuff.
3628 */
3629 /* Read the CS descriptor. */
3630 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3631 {
3632 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid CS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3633 return iemRaiseGeneralProtectionFault0(pVCpu);
3634 }
3635
3636 IEMSELDESC DescCS;
3637 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3638 if (rcStrict != VINF_SUCCESS)
3639 {
3640 Log(("iret %04x:%016RX64/%04x:%016RX64 - rcStrict=%Rrc when fetching CS\n",
3641 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3642 return rcStrict;
3643 }
3644
3645 /* Must be a code descriptor. */
3646 if ( !DescCS.Legacy.Gen.u1DescType
3647 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3648 {
3649 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS is not a code segment T=%u T=%#xu -> #GP\n",
3650 uNewCs, uNewRip, uNewSs, uNewRsp, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
3651 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3652 }
3653
3654 /* Privilege checks. */
3655 uint8_t const uNewCpl = uNewCs & X86_SEL_RPL;
3656 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3657 {
3658 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3659 {
3660 Log(("iret %04x:%016RX64 - RPL != DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3661 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3662 }
3663 }
3664 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3665 {
3666 Log(("iret %04x:%016RX64 - RPL < DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3667 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3668 }
3669 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3670 {
3671 Log(("iret %04x:%016RX64 - RPL < CPL (%d) -> #GP\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
3672 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3673 }
3674
3675 /* Present? */
3676 if (!DescCS.Legacy.Gen.u1Present)
3677 {
3678 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS not present -> #NP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3679 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3680 }
3681
3682 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3683
3684 /* Read the SS descriptor. */
3685 IEMSELDESC DescSS;
3686 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3687 {
3688 if ( !DescCS.Legacy.Gen.u1Long
3689 || DescCS.Legacy.Gen.u1DefBig /** @todo exactly how does iret (and others) behave with u1Long=1 and u1DefBig=1? \#GP(sel)? */
3690 || uNewCpl > 2) /** @todo verify SS=0 impossible for ring-3. */
3691 {
3692 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid SS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3693 return iemRaiseGeneralProtectionFault0(pVCpu);
3694 }
3695 DescSS.Legacy.u = 0;
3696 }
3697 else
3698 {
3699 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSs, X86_XCPT_GP); /** @todo Correct exception? */
3700 if (rcStrict != VINF_SUCCESS)
3701 {
3702 Log(("iret %04x:%016RX64/%04x:%016RX64 - %Rrc when fetching SS\n",
3703 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3704 return rcStrict;
3705 }
3706 }
3707
3708 /* Privilege checks. */
3709 if ((uNewSs & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3710 {
3711 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3712 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3713 }
3714
3715 uint32_t cbLimitSs;
3716 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3717 cbLimitSs = UINT32_MAX;
3718 else
3719 {
3720 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3721 {
3722 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.DPL (%d) != CS.RPL -> #GP\n",
3723 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u2Dpl));
3724 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3725 }
3726
3727 /* Must be a writeable data segment descriptor. */
3728 if (!DescSS.Legacy.Gen.u1DescType)
3729 {
3730 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS is system segment (%#x) -> #GP\n",
3731 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3732 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3733 }
3734 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3735 {
3736 Log(("iret %04x:%016RX64/%04x:%016RX64 - not writable data segment (%#x) -> #GP\n",
3737 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3738 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3739 }
3740
3741 /* Present? */
3742 if (!DescSS.Legacy.Gen.u1Present)
3743 {
3744 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS not present -> #SS\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3745 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSs);
3746 }
3747 cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3748 }
3749
3750 /* Check EIP. */
3751 if (DescCS.Legacy.Gen.u1Long)
3752 {
3753 if (!IEM_IS_CANONICAL(uNewRip))
3754 {
3755 Log(("iret %04x:%016RX64/%04x:%016RX64 -> RIP is not canonical -> #GP(0)\n",
3756 uNewCs, uNewRip, uNewSs, uNewRsp));
3757 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3758 }
3759 }
3760 else
3761 {
3762 if (uNewRip > cbLimitCS)
3763 {
3764 Log(("iret %04x:%016RX64/%04x:%016RX64 -> EIP is out of bounds (%#x) -> #GP(0)\n",
3765 uNewCs, uNewRip, uNewSs, uNewRsp, cbLimitCS));
3766 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3767 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3768 }
3769 }
3770
3771 /*
3772 * Commit the changes, marking CS and SS accessed first since
3773 * that may fail.
3774 */
3775 /** @todo where exactly are these actually marked accessed by a real CPU? */
3776 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3777 {
3778 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3779 if (rcStrict != VINF_SUCCESS)
3780 return rcStrict;
3781 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3782 }
3783 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3784 {
3785 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSs);
3786 if (rcStrict != VINF_SUCCESS)
3787 return rcStrict;
3788 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3789 }
3790
3791 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3792 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3793 if (enmEffOpSize != IEMMODE_16BIT)
3794 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3795 if (pVCpu->iem.s.uCpl == 0)
3796 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is ignored */
3797 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3798 fEFlagsMask |= X86_EFL_IF;
3799 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3800 fEFlagsNew &= ~fEFlagsMask;
3801 fEFlagsNew |= uNewFlags & fEFlagsMask;
3802#ifdef DBGFTRACE_ENABLED
3803 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%ul%u %08llx -> %04x:%04llx %llx %04x:%04llx",
3804 pVCpu->iem.s.uCpl, uNewCpl, pVCpu->cpum.GstCtx.rip, uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp);
3805#endif
3806
3807 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3808 pVCpu->cpum.GstCtx.rip = uNewRip;
3809 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3810 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3811 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3812 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3813 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3814 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3815 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3816 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long || pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig)
3817 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3818 else
3819 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3820 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
3821 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
3822 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3823 {
3824 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3825 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_UNUSABLE | (uNewCpl << X86DESCATTR_DPL_SHIFT);
3826 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
3827 pVCpu->cpum.GstCtx.ss.u64Base = 0;
3828 Log2(("iretq new SS: NULL\n"));
3829 }
3830 else
3831 {
3832 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3833 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3834 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3835 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3836 Log2(("iretq new SS: base=%#RX64 lim=%#x attr=%#x\n", pVCpu->cpum.GstCtx.ss.u64Base, pVCpu->cpum.GstCtx.ss.u32Limit, pVCpu->cpum.GstCtx.ss.Attr.u));
3837 }
3838
3839 if (pVCpu->iem.s.uCpl != uNewCpl)
3840 {
3841 pVCpu->iem.s.uCpl = uNewCpl;
3842 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.ds);
3843 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.es);
3844 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.fs);
3845 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.gs);
3846 }
3847
3848 /* Flush the prefetch buffer. */
3849#ifdef IEM_WITH_CODE_TLB
3850 pVCpu->iem.s.pbInstrBuf = NULL;
3851#else
3852 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3853#endif
3854
3855 return VINF_SUCCESS;
3856}
3857
3858
3859/**
3860 * Implements iret.
3861 *
3862 * @param enmEffOpSize The effective operand size.
3863 */
3864IEM_CIMPL_DEF_1(iemCImpl_iret, IEMMODE, enmEffOpSize)
3865{
3866 bool fBlockingNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3867
3868#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3869 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
3870 {
3871 /*
3872 * Record whether NMI (or virtual-NMI) blocking is in effect during the execution
3873 * of this IRET instruction. We need to provide this information as part of some
3874 * VM-exits.
3875 *
3876 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3877 */
3878 if (IEM_VMX_IS_PINCTLS_SET(pVCpu, VMX_PIN_CTLS_VIRT_NMI))
3879 pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret = pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking;
3880 else
3881 pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret = fBlockingNmi;
3882
3883 /*
3884 * If "NMI exiting" is set, IRET does not affect blocking of NMIs.
3885 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3886 */
3887 if (IEM_VMX_IS_PINCTLS_SET(pVCpu, VMX_PIN_CTLS_NMI_EXIT))
3888 fBlockingNmi = false;
3889
3890 /* Clear virtual-NMI blocking, if any, before causing any further exceptions. */
3891 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
3892 }
3893#endif
3894
3895 /*
3896 * The SVM nested-guest intercept for IRET takes priority over all exceptions,
3897 * The NMI is still held pending (which I assume means blocking of further NMIs
3898 * is in effect).
3899 *
3900 * See AMD spec. 15.9 "Instruction Intercepts".
3901 * See AMD spec. 15.21.9 "NMI Support".
3902 */
3903 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IRET))
3904 {
3905 Log(("iret: Guest intercept -> #VMEXIT\n"));
3906 IEM_SVM_UPDATE_NRIP(pVCpu);
3907 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IRET, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
3908 }
3909
3910 /*
3911 * Clear NMI blocking, if any, before causing any further exceptions.
3912 * See Intel spec. 6.7.1 "Handling Multiple NMIs".
3913 */
3914 if (fBlockingNmi)
3915 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
3916
3917 /*
3918 * Call a mode specific worker.
3919 */
3920 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
3921 return IEM_CIMPL_CALL_1(iemCImpl_iret_real_v8086, enmEffOpSize);
3922 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
3923 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
3924 return IEM_CIMPL_CALL_1(iemCImpl_iret_64bit, enmEffOpSize);
3925 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot, enmEffOpSize);
3926}
3927
3928
3929static void iemLoadallSetSelector(PVMCPUCC pVCpu, uint8_t iSegReg, uint16_t uSel)
3930{
3931 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
3932
3933 pHid->Sel = uSel;
3934 pHid->ValidSel = uSel;
3935 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
3936}
3937
3938
3939static void iemLoadall286SetDescCache(PVMCPUCC pVCpu, uint8_t iSegReg, uint8_t const *pbMem)
3940{
3941 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
3942
3943 /* The base is in the first three bytes. */
3944 pHid->u64Base = pbMem[0] + (pbMem[1] << 8) + (pbMem[2] << 16);
3945 /* The attributes are in the fourth byte. */
3946 pHid->Attr.u = pbMem[3];
3947 /* The limit is in the last two bytes. */
3948 pHid->u32Limit = pbMem[4] + (pbMem[5] << 8);
3949}
3950
3951
3952/**
3953 * Implements 286 LOADALL (286 CPUs only).
3954 */
3955IEM_CIMPL_DEF_0(iemCImpl_loadall286)
3956{
3957 NOREF(cbInstr);
3958
3959 /* Data is loaded from a buffer at 800h. No checks are done on the
3960 * validity of loaded state.
3961 *
3962 * LOADALL only loads the internal CPU state, it does not access any
3963 * GDT, LDT, or similar tables.
3964 */
3965
3966 if (pVCpu->iem.s.uCpl != 0)
3967 {
3968 Log(("loadall286: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
3969 return iemRaiseGeneralProtectionFault0(pVCpu);
3970 }
3971
3972 uint8_t const *pbMem = NULL;
3973 uint16_t const *pa16Mem;
3974 uint8_t const *pa8Mem;
3975 RTGCPHYS GCPtrStart = 0x800; /* Fixed table location. */
3976 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&pbMem, 0x66, UINT8_MAX, GCPtrStart, IEM_ACCESS_SYS_R, 0);
3977 if (rcStrict != VINF_SUCCESS)
3978 return rcStrict;
3979
3980 /* The MSW is at offset 0x06. */
3981 pa16Mem = (uint16_t const *)(pbMem + 0x06);
3982 /* Even LOADALL can't clear the MSW.PE bit, though it can set it. */
3983 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3984 uNewCr0 |= *pa16Mem & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3985 uint64_t const uOldCr0 = pVCpu->cpum.GstCtx.cr0;
3986
3987 CPUMSetGuestCR0(pVCpu, uNewCr0);
3988 Assert(pVCpu->cpum.GstCtx.cr0 == uNewCr0);
3989
3990 /* Inform PGM if mode changed. */
3991 if ((uNewCr0 & X86_CR0_PE) != (uOldCr0 & X86_CR0_PE))
3992 {
3993 int rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
3994 AssertRCReturn(rc, rc);
3995 /* ignore informational status codes */
3996 }
3997 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
3998 false /* fForce */);
3999
4000 /* TR selector is at offset 0x16. */
4001 pa16Mem = (uint16_t const *)(pbMem + 0x16);
4002 pVCpu->cpum.GstCtx.tr.Sel = pa16Mem[0];
4003 pVCpu->cpum.GstCtx.tr.ValidSel = pa16Mem[0];
4004 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
4005
4006 /* Followed by FLAGS... */
4007 pVCpu->cpum.GstCtx.eflags.u = pa16Mem[1] | X86_EFL_1;
4008 pVCpu->cpum.GstCtx.ip = pa16Mem[2]; /* ...and IP. */
4009
4010 /* LDT is at offset 0x1C. */
4011 pa16Mem = (uint16_t const *)(pbMem + 0x1C);
4012 pVCpu->cpum.GstCtx.ldtr.Sel = pa16Mem[0];
4013 pVCpu->cpum.GstCtx.ldtr.ValidSel = pa16Mem[0];
4014 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4015
4016 /* Segment registers are at offset 0x1E. */
4017 pa16Mem = (uint16_t const *)(pbMem + 0x1E);
4018 iemLoadallSetSelector(pVCpu, X86_SREG_DS, pa16Mem[0]);
4019 iemLoadallSetSelector(pVCpu, X86_SREG_SS, pa16Mem[1]);
4020 iemLoadallSetSelector(pVCpu, X86_SREG_CS, pa16Mem[2]);
4021 iemLoadallSetSelector(pVCpu, X86_SREG_ES, pa16Mem[3]);
4022
4023 /* GPRs are at offset 0x26. */
4024 pa16Mem = (uint16_t const *)(pbMem + 0x26);
4025 pVCpu->cpum.GstCtx.di = pa16Mem[0];
4026 pVCpu->cpum.GstCtx.si = pa16Mem[1];
4027 pVCpu->cpum.GstCtx.bp = pa16Mem[2];
4028 pVCpu->cpum.GstCtx.sp = pa16Mem[3];
4029 pVCpu->cpum.GstCtx.bx = pa16Mem[4];
4030 pVCpu->cpum.GstCtx.dx = pa16Mem[5];
4031 pVCpu->cpum.GstCtx.cx = pa16Mem[6];
4032 pVCpu->cpum.GstCtx.ax = pa16Mem[7];
4033
4034 /* Descriptor caches are at offset 0x36, 6 bytes per entry. */
4035 iemLoadall286SetDescCache(pVCpu, X86_SREG_ES, pbMem + 0x36);
4036 iemLoadall286SetDescCache(pVCpu, X86_SREG_CS, pbMem + 0x3C);
4037 iemLoadall286SetDescCache(pVCpu, X86_SREG_SS, pbMem + 0x42);
4038 iemLoadall286SetDescCache(pVCpu, X86_SREG_DS, pbMem + 0x48);
4039
4040 /* GDTR contents are at offset 0x4E, 6 bytes. */
4041 RTGCPHYS GCPtrBase;
4042 uint16_t cbLimit;
4043 pa8Mem = pbMem + 0x4E;
4044 /* NB: Fourth byte "should be zero"; we are ignoring it. */
4045 GCPtrBase = pa8Mem[0] + (pa8Mem[1] << 8) + (pa8Mem[2] << 16);
4046 cbLimit = pa8Mem[4] + (pa8Mem[5] << 8);
4047 CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
4048
4049 /* IDTR contents are at offset 0x5A, 6 bytes. */
4050 pa8Mem = pbMem + 0x5A;
4051 GCPtrBase = pa8Mem[0] + (pa8Mem[1] << 8) + (pa8Mem[2] << 16);
4052 cbLimit = pa8Mem[4] + (pa8Mem[5] << 8);
4053 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
4054
4055 Log(("LOADALL: GDTR:%08RX64/%04X, IDTR:%08RX64/%04X\n", pVCpu->cpum.GstCtx.gdtr.pGdt, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.idtr.pIdt, pVCpu->cpum.GstCtx.idtr.cbIdt));
4056 Log(("LOADALL: CS:%04X, CS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.cs.u64Base, pVCpu->cpum.GstCtx.cs.u32Limit, pVCpu->cpum.GstCtx.cs.Attr.u));
4057 Log(("LOADALL: DS:%04X, DS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.ds.Sel, pVCpu->cpum.GstCtx.ds.u64Base, pVCpu->cpum.GstCtx.ds.u32Limit, pVCpu->cpum.GstCtx.ds.Attr.u));
4058 Log(("LOADALL: ES:%04X, ES base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.es.Sel, pVCpu->cpum.GstCtx.es.u64Base, pVCpu->cpum.GstCtx.es.u32Limit, pVCpu->cpum.GstCtx.es.Attr.u));
4059 Log(("LOADALL: SS:%04X, SS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.ss.u64Base, pVCpu->cpum.GstCtx.ss.u32Limit, pVCpu->cpum.GstCtx.ss.Attr.u));
4060 Log(("LOADALL: SI:%04X, DI:%04X, AX:%04X, BX:%04X, CX:%04X, DX:%04X\n", pVCpu->cpum.GstCtx.si, pVCpu->cpum.GstCtx.di, pVCpu->cpum.GstCtx.bx, pVCpu->cpum.GstCtx.bx, pVCpu->cpum.GstCtx.cx, pVCpu->cpum.GstCtx.dx));
4061
4062 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pbMem, IEM_ACCESS_SYS_R);
4063 if (rcStrict != VINF_SUCCESS)
4064 return rcStrict;
4065
4066 /* The CPL may change. It is taken from the "DPL fields of the SS and CS
4067 * descriptor caches" but there is no word as to what happens if those are
4068 * not identical (probably bad things).
4069 */
4070 pVCpu->iem.s.uCpl = pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl;
4071
4072 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS | CPUM_CHANGED_IDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_TR | CPUM_CHANGED_LDTR);
4073
4074 /* Flush the prefetch buffer. */
4075#ifdef IEM_WITH_CODE_TLB
4076 pVCpu->iem.s.pbInstrBuf = NULL;
4077#else
4078 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4079#endif
4080 return rcStrict;
4081}
4082
4083
4084/**
4085 * Implements SYSCALL (AMD and Intel64).
4086 */
4087IEM_CIMPL_DEF_0(iemCImpl_syscall)
4088{
4089 /** @todo hack, LOADALL should be decoded as such on a 286. */
4090 if (RT_UNLIKELY(pVCpu->iem.s.uTargetCpu == IEMTARGETCPU_286))
4091 return iemCImpl_loadall286(pVCpu, cbInstr);
4092
4093 /*
4094 * Check preconditions.
4095 *
4096 * Note that CPUs described in the documentation may load a few odd values
4097 * into CS and SS than we allow here. This has yet to be checked on real
4098 * hardware.
4099 */
4100 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
4101 {
4102 Log(("syscall: Not enabled in EFER -> #UD\n"));
4103 return iemRaiseUndefinedOpcode(pVCpu);
4104 }
4105 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4106 {
4107 Log(("syscall: Protected mode is required -> #GP(0)\n"));
4108 return iemRaiseGeneralProtectionFault0(pVCpu);
4109 }
4110 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4111 {
4112 Log(("syscall: Only available in long mode on intel -> #UD\n"));
4113 return iemRaiseUndefinedOpcode(pVCpu);
4114 }
4115
4116 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
4117
4118 /** @todo verify RPL ignoring and CS=0xfff8 (i.e. SS == 0). */
4119 /** @todo what about LDT selectors? Shouldn't matter, really. */
4120 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSCALL_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4121 uint16_t uNewSs = uNewCs + 8;
4122 if (uNewCs == 0 || uNewSs == 0)
4123 {
4124 /** @todo Neither Intel nor AMD document this check. */
4125 Log(("syscall: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4126 return iemRaiseGeneralProtectionFault0(pVCpu);
4127 }
4128
4129 /* Long mode and legacy mode differs. */
4130 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4131 {
4132 uint64_t uNewRip = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.msrLSTAR : pVCpu->cpum.GstCtx. msrCSTAR;
4133
4134 /* This test isn't in the docs, but I'm not trusting the guys writing
4135 the MSRs to have validated the values as canonical like they should. */
4136 if (!IEM_IS_CANONICAL(uNewRip))
4137 {
4138 /** @todo Intel claims this can't happen because IA32_LSTAR MSR can't be written with non-canonical address. */
4139 Log(("syscall: New RIP not canonical -> #UD\n"));
4140 return iemRaiseUndefinedOpcode(pVCpu);
4141 }
4142
4143 /*
4144 * Commit it.
4145 */
4146 Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, uNewRip));
4147 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.rip + cbInstr;
4148 pVCpu->cpum.GstCtx.rip = uNewRip;
4149
4150 pVCpu->cpum.GstCtx.rflags.u &= ~X86_EFL_RF;
4151 pVCpu->cpum.GstCtx.r11 = pVCpu->cpum.GstCtx.rflags.u;
4152 pVCpu->cpum.GstCtx.rflags.u &= ~pVCpu->cpum.GstCtx.msrSFMASK;
4153 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
4154
4155 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
4156 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
4157 }
4158 else
4159 {
4160 /*
4161 * Commit it.
4162 */
4163 Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, (uint32_t)(pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
4164 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.eip + cbInstr;
4165 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK;
4166 pVCpu->cpum.GstCtx.rflags.u &= ~(X86_EFL_VM | X86_EFL_IF | X86_EFL_RF);
4167
4168 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
4169 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
4170 }
4171 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
4172 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
4173 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4174 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4175 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4176
4177 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
4178 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
4179 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4180 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4181 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4182
4183 pVCpu->iem.s.uCpl = 0;
4184 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
4185
4186 /* Flush the prefetch buffer. */
4187#ifdef IEM_WITH_CODE_TLB
4188 pVCpu->iem.s.pbInstrBuf = NULL;
4189#else
4190 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4191#endif
4192
4193 return VINF_SUCCESS;
4194}
4195
4196
4197/**
4198 * Implements SYSRET (AMD and Intel64).
4199 */
4200IEM_CIMPL_DEF_0(iemCImpl_sysret)
4201
4202{
4203 RT_NOREF_PV(cbInstr);
4204
4205 /*
4206 * Check preconditions.
4207 *
4208 * Note that CPUs described in the documentation may load a few odd values
4209 * into CS and SS than we allow here. This has yet to be checked on real
4210 * hardware.
4211 */
4212 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
4213 {
4214 Log(("sysret: Not enabled in EFER -> #UD\n"));
4215 return iemRaiseUndefinedOpcode(pVCpu);
4216 }
4217 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4218 {
4219 Log(("sysret: Only available in long mode on intel -> #UD\n"));
4220 return iemRaiseUndefinedOpcode(pVCpu);
4221 }
4222 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4223 {
4224 Log(("sysret: Protected mode is required -> #GP(0)\n"));
4225 return iemRaiseGeneralProtectionFault0(pVCpu);
4226 }
4227 if (pVCpu->iem.s.uCpl != 0)
4228 {
4229 Log(("sysret: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
4230 return iemRaiseGeneralProtectionFault0(pVCpu);
4231 }
4232
4233 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
4234
4235 /** @todo Does SYSRET verify CS != 0 and SS != 0? Neither is valid in ring-3. */
4236 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSRET_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4237 uint16_t uNewSs = uNewCs + 8;
4238 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4239 uNewCs += 16;
4240 if (uNewCs == 0 || uNewSs == 0)
4241 {
4242 Log(("sysret: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4243 return iemRaiseGeneralProtectionFault0(pVCpu);
4244 }
4245
4246 /*
4247 * Commit it.
4248 */
4249 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4250 {
4251 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4252 {
4253 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.r11));
4254 /* Note! We disregard intel manual regarding the RCX canonical
4255 check, ask intel+xen why AMD doesn't do it. */
4256 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4257 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4258 | (3 << X86DESCATTR_DPL_SHIFT);
4259 }
4260 else
4261 {
4262 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.r11));
4263 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.ecx;
4264 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4265 | (3 << X86DESCATTR_DPL_SHIFT);
4266 }
4267 /** @todo testcase: See what kind of flags we can make SYSRET restore and
4268 * what it really ignores. RF and VM are hinted at being zero, by AMD.
4269 * Intel says: RFLAGS := (R11 & 3C7FD7H) | 2; */
4270 pVCpu->cpum.GstCtx.rflags.u = pVCpu->cpum.GstCtx.r11 & (X86_EFL_POPF_BITS | X86_EFL_VIF | X86_EFL_VIP);
4271 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
4272 }
4273 else
4274 {
4275 Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx));
4276 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4277 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_IF;
4278 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4279 | (3 << X86DESCATTR_DPL_SHIFT);
4280 }
4281 pVCpu->cpum.GstCtx.cs.Sel = uNewCs | 3;
4282 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs | 3;
4283 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4284 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4285 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4286
4287 pVCpu->cpum.GstCtx.ss.Sel = uNewSs | 3;
4288 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs | 3;
4289 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4290 /* The SS hidden bits remains unchanged says AMD. To that I say "Yeah, right!". */
4291 pVCpu->cpum.GstCtx.ss.Attr.u |= (3 << X86DESCATTR_DPL_SHIFT);
4292 /** @todo Testcase: verify that SS.u1Long and SS.u1DefBig are left unchanged
4293 * on sysret. */
4294
4295 pVCpu->iem.s.uCpl = 3;
4296 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
4297
4298 /* Flush the prefetch buffer. */
4299#ifdef IEM_WITH_CODE_TLB
4300 pVCpu->iem.s.pbInstrBuf = NULL;
4301#else
4302 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4303#endif
4304
4305 return VINF_SUCCESS;
4306}
4307
4308
4309/**
4310 * Implements SYSENTER (Intel, 32-bit AMD).
4311 */
4312IEM_CIMPL_DEF_0(iemCImpl_sysenter)
4313{
4314 RT_NOREF(cbInstr);
4315
4316 /*
4317 * Check preconditions.
4318 *
4319 * Note that CPUs described in the documentation may load a few odd values
4320 * into CS and SS than we allow here. This has yet to be checked on real
4321 * hardware.
4322 */
4323 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysEnter)
4324 {
4325 Log(("sysenter: not supported -=> #UD\n"));
4326 return iemRaiseUndefinedOpcode(pVCpu);
4327 }
4328 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4329 {
4330 Log(("sysenter: Protected or long mode is required -> #GP(0)\n"));
4331 return iemRaiseGeneralProtectionFault0(pVCpu);
4332 }
4333 bool fIsLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
4334 if (IEM_IS_GUEST_CPU_AMD(pVCpu) && fIsLongMode)
4335 {
4336 Log(("sysenter: Only available in protected mode on AMD -> #UD\n"));
4337 return iemRaiseUndefinedOpcode(pVCpu);
4338 }
4339 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4340 uint16_t uNewCs = pVCpu->cpum.GstCtx.SysEnter.cs;
4341 if ((uNewCs & X86_SEL_MASK_OFF_RPL) == 0)
4342 {
4343 Log(("sysenter: SYSENTER_CS = %#x -> #GP(0)\n", uNewCs));
4344 return iemRaiseGeneralProtectionFault0(pVCpu);
4345 }
4346
4347 /* This test isn't in the docs, it's just a safeguard against missing
4348 canonical checks when writing the registers. */
4349 if (RT_LIKELY( !fIsLongMode
4350 || ( IEM_IS_CANONICAL(pVCpu->cpum.GstCtx.SysEnter.eip)
4351 && IEM_IS_CANONICAL(pVCpu->cpum.GstCtx.SysEnter.esp))))
4352 { /* likely */ }
4353 else
4354 {
4355 Log(("sysenter: SYSENTER_EIP = %#RX64 or/and SYSENTER_ESP = %#RX64 not canonical -> #GP(0)\n",
4356 pVCpu->cpum.GstCtx.SysEnter.eip, pVCpu->cpum.GstCtx.SysEnter.esp));
4357 return iemRaiseUndefinedOpcode(pVCpu);
4358 }
4359
4360/** @todo Test: Sysenter from ring-0, ring-1 and ring-2. */
4361
4362 /*
4363 * Update registers and commit.
4364 */
4365 if (fIsLongMode)
4366 {
4367 Log(("sysenter: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4368 pVCpu->cpum.GstCtx.rflags.u, uNewCs & X86_SEL_MASK_OFF_RPL, pVCpu->cpum.GstCtx.SysEnter.eip));
4369 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.SysEnter.eip;
4370 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.SysEnter.esp;
4371 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_L | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4372 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC;
4373 }
4374 else
4375 {
4376 Log(("sysenter: %04x:%08RX32 [efl=%#llx] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, (uint32_t)pVCpu->cpum.GstCtx.rip,
4377 pVCpu->cpum.GstCtx.rflags.u, uNewCs & X86_SEL_MASK_OFF_RPL, (uint32_t)pVCpu->cpum.GstCtx.SysEnter.eip));
4378 pVCpu->cpum.GstCtx.rip = (uint32_t)pVCpu->cpum.GstCtx.SysEnter.eip;
4379 pVCpu->cpum.GstCtx.rsp = (uint32_t)pVCpu->cpum.GstCtx.SysEnter.esp;
4380 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4381 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC;
4382 }
4383 pVCpu->cpum.GstCtx.cs.Sel = uNewCs & X86_SEL_MASK_OFF_RPL;
4384 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs & X86_SEL_MASK_OFF_RPL;
4385 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4386 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4387 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4388
4389 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs & X86_SEL_MASK_OFF_RPL) + 8;
4390 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs & X86_SEL_MASK_OFF_RPL) + 8;
4391 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4392 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4393 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4394 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_RW_ACC;
4395 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4396
4397 pVCpu->cpum.GstCtx.rflags.Bits.u1IF = 0;
4398 pVCpu->cpum.GstCtx.rflags.Bits.u1VM = 0;
4399 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
4400
4401 pVCpu->iem.s.uCpl = 0;
4402
4403 /* Flush the prefetch buffer. */
4404#ifdef IEM_WITH_CODE_TLB
4405 pVCpu->iem.s.pbInstrBuf = NULL;
4406#else
4407 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4408#endif
4409
4410 return VINF_SUCCESS;
4411}
4412
4413
4414/**
4415 * Implements SYSEXIT (Intel, 32-bit AMD).
4416 *
4417 * @param enmEffOpSize The effective operand size.
4418 */
4419IEM_CIMPL_DEF_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize)
4420{
4421 RT_NOREF(cbInstr);
4422
4423 /*
4424 * Check preconditions.
4425 *
4426 * Note that CPUs described in the documentation may load a few odd values
4427 * into CS and SS than we allow here. This has yet to be checked on real
4428 * hardware.
4429 */
4430 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysEnter)
4431 {
4432 Log(("sysexit: not supported -=> #UD\n"));
4433 return iemRaiseUndefinedOpcode(pVCpu);
4434 }
4435 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4436 {
4437 Log(("sysexit: Protected or long mode is required -> #GP(0)\n"));
4438 return iemRaiseGeneralProtectionFault0(pVCpu);
4439 }
4440 bool fIsLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
4441 if (IEM_IS_GUEST_CPU_AMD(pVCpu) && fIsLongMode)
4442 {
4443 Log(("sysexit: Only available in protected mode on AMD -> #UD\n"));
4444 return iemRaiseUndefinedOpcode(pVCpu);
4445 }
4446 if (pVCpu->iem.s.uCpl != 0)
4447 {
4448 Log(("sysexit: CPL(=%u) != 0 -> #GP(0)\n", pVCpu->iem.s.uCpl));
4449 return iemRaiseGeneralProtectionFault0(pVCpu);
4450 }
4451 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4452 uint16_t uNewCs = pVCpu->cpum.GstCtx.SysEnter.cs;
4453 if ((uNewCs & X86_SEL_MASK_OFF_RPL) == 0)
4454 {
4455 Log(("sysexit: SYSENTER_CS = %#x -> #GP(0)\n", uNewCs));
4456 return iemRaiseGeneralProtectionFault0(pVCpu);
4457 }
4458
4459 /*
4460 * Update registers and commit.
4461 */
4462 if (enmEffOpSize == IEMMODE_64BIT)
4463 {
4464 Log(("sysexit: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4465 pVCpu->cpum.GstCtx.rflags.u, (uNewCs | 3) + 32, pVCpu->cpum.GstCtx.rcx));
4466 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rdx;
4467 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.rcx;
4468 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_L | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4469 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4470 pVCpu->cpum.GstCtx.cs.Sel = (uNewCs | 3) + 32;
4471 pVCpu->cpum.GstCtx.cs.ValidSel = (uNewCs | 3) + 32;
4472 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs | 3) + 40;
4473 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs | 3) + 40;
4474 }
4475 else
4476 {
4477 Log(("sysexit: %04x:%08RX64 [efl=%#llx] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4478 pVCpu->cpum.GstCtx.rflags.u, (uNewCs | 3) + 16, (uint32_t)pVCpu->cpum.GstCtx.edx));
4479 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.edx;
4480 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.ecx;
4481 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4482 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4483 pVCpu->cpum.GstCtx.cs.Sel = (uNewCs | 3) + 16;
4484 pVCpu->cpum.GstCtx.cs.ValidSel = (uNewCs | 3) + 16;
4485 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs | 3) + 24;
4486 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs | 3) + 24;
4487 }
4488 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4489 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4490 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4491
4492 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4493 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4494 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4495 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_RW_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4496 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4497 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
4498
4499 pVCpu->iem.s.uCpl = 3;
4500
4501 /* Flush the prefetch buffer. */
4502#ifdef IEM_WITH_CODE_TLB
4503 pVCpu->iem.s.pbInstrBuf = NULL;
4504#else
4505 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4506#endif
4507
4508 return VINF_SUCCESS;
4509}
4510
4511
4512/**
4513 * Common worker for 'pop SReg', 'mov SReg, GReg' and 'lXs GReg, reg/mem'.
4514 *
4515 * @param iSegReg The segment register number (valid).
4516 * @param uSel The new selector value.
4517 */
4518IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
4519{
4520 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
4521 uint16_t *pSel = iemSRegRef(pVCpu, iSegReg);
4522 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
4523
4524 Assert(iSegReg <= X86_SREG_GS && iSegReg != X86_SREG_CS);
4525
4526 /*
4527 * Real mode and V8086 mode are easy.
4528 */
4529 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4530 {
4531 *pSel = uSel;
4532 pHid->u64Base = (uint32_t)uSel << 4;
4533 pHid->ValidSel = uSel;
4534 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4535#if 0 /* AMD Volume 2, chapter 4.1 - "real mode segmentation" - states that limit and attributes are untouched. */
4536 /** @todo Does the CPU actually load limits and attributes in the
4537 * real/V8086 mode segment load case? It doesn't for CS in far
4538 * jumps... Affects unreal mode. */
4539 pHid->u32Limit = 0xffff;
4540 pHid->Attr.u = 0;
4541 pHid->Attr.n.u1Present = 1;
4542 pHid->Attr.n.u1DescType = 1;
4543 pHid->Attr.n.u4Type = iSegReg != X86_SREG_CS
4544 ? X86_SEL_TYPE_RW
4545 : X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
4546#endif
4547 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4548 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4549 return VINF_SUCCESS;
4550 }
4551
4552 /*
4553 * Protected mode.
4554 *
4555 * Check if it's a null segment selector value first, that's OK for DS, ES,
4556 * FS and GS. If not null, then we have to load and parse the descriptor.
4557 */
4558 if (!(uSel & X86_SEL_MASK_OFF_RPL))
4559 {
4560 Assert(iSegReg != X86_SREG_CS); /** @todo testcase for \#UD on MOV CS, ax! */
4561 if (iSegReg == X86_SREG_SS)
4562 {
4563 /* In 64-bit kernel mode, the stack can be 0 because of the way
4564 interrupts are dispatched. AMD seems to have a slighly more
4565 relaxed relationship to SS.RPL than intel does. */
4566 /** @todo We cannot 'mov ss, 3' in 64-bit kernel mode, can we? There is a testcase (bs-cpu-xcpt-1), but double check this! */
4567 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4568 || pVCpu->iem.s.uCpl > 2
4569 || ( uSel != pVCpu->iem.s.uCpl
4570 && !IEM_IS_GUEST_CPU_AMD(pVCpu)) )
4571 {
4572 Log(("load sreg %#x -> invalid stack selector, #GP(0)\n", uSel));
4573 return iemRaiseGeneralProtectionFault0(pVCpu);
4574 }
4575 }
4576
4577 *pSel = uSel; /* Not RPL, remember :-) */
4578 iemHlpLoadNullDataSelectorProt(pVCpu, pHid, uSel);
4579 if (iSegReg == X86_SREG_SS)
4580 pHid->Attr.u |= pVCpu->iem.s.uCpl << X86DESCATTR_DPL_SHIFT;
4581
4582 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4583 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4584
4585 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4586 return VINF_SUCCESS;
4587 }
4588
4589 /* Fetch the descriptor. */
4590 IEMSELDESC Desc;
4591 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP); /** @todo Correct exception? */
4592 if (rcStrict != VINF_SUCCESS)
4593 return rcStrict;
4594
4595 /* Check GPs first. */
4596 if (!Desc.Legacy.Gen.u1DescType)
4597 {
4598 Log(("load sreg %d (=%#x) - system selector (%#x) -> #GP\n", iSegReg, uSel, Desc.Legacy.Gen.u4Type));
4599 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4600 }
4601 if (iSegReg == X86_SREG_SS) /* SS gets different treatment */
4602 {
4603 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
4604 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
4605 {
4606 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
4607 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4608 }
4609 if ((uSel & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
4610 {
4611 Log(("load sreg SS, %#x - RPL and CPL (%d) differs -> #GP\n", uSel, pVCpu->iem.s.uCpl));
4612 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4613 }
4614 if (Desc.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
4615 {
4616 Log(("load sreg SS, %#x - DPL (%d) and CPL (%d) differs -> #GP\n", uSel, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
4617 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4618 }
4619 }
4620 else
4621 {
4622 if ((Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4623 {
4624 Log(("load sreg%u, %#x - execute only segment -> #GP\n", iSegReg, uSel));
4625 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4626 }
4627 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4628 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4629 {
4630#if 0 /* this is what intel says. */
4631 if ( (uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
4632 && pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4633 {
4634 Log(("load sreg%u, %#x - both RPL (%d) and CPL (%d) are greater than DPL (%d) -> #GP\n",
4635 iSegReg, uSel, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4636 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4637 }
4638#else /* this is what makes more sense. */
4639 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4640 {
4641 Log(("load sreg%u, %#x - RPL (%d) is greater than DPL (%d) -> #GP\n",
4642 iSegReg, uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl));
4643 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4644 }
4645 if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4646 {
4647 Log(("load sreg%u, %#x - CPL (%d) is greater than DPL (%d) -> #GP\n",
4648 iSegReg, uSel, pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4649 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4650 }
4651#endif
4652 }
4653 }
4654
4655 /* Is it there? */
4656 if (!Desc.Legacy.Gen.u1Present)
4657 {
4658 Log(("load sreg%d,%#x - segment not present -> #NP\n", iSegReg, uSel));
4659 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
4660 }
4661
4662 /* The base and limit. */
4663 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
4664 uint64_t u64Base = X86DESC_BASE(&Desc.Legacy);
4665
4666 /*
4667 * Ok, everything checked out fine. Now set the accessed bit before
4668 * committing the result into the registers.
4669 */
4670 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
4671 {
4672 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
4673 if (rcStrict != VINF_SUCCESS)
4674 return rcStrict;
4675 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
4676 }
4677
4678 /* commit */
4679 *pSel = uSel;
4680 pHid->Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4681 pHid->u32Limit = cbLimit;
4682 pHid->u64Base = u64Base;
4683 pHid->ValidSel = uSel;
4684 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4685
4686 /** @todo check if the hidden bits are loaded correctly for 64-bit
4687 * mode. */
4688 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4689
4690 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4691 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4692 return VINF_SUCCESS;
4693}
4694
4695
4696/**
4697 * Implements 'mov SReg, r/m'.
4698 *
4699 * @param iSegReg The segment register number (valid).
4700 * @param uSel The new selector value.
4701 */
4702IEM_CIMPL_DEF_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel)
4703{
4704 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4705 if (rcStrict == VINF_SUCCESS)
4706 {
4707 if (iSegReg == X86_SREG_SS)
4708 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
4709 }
4710 return rcStrict;
4711}
4712
4713
4714/**
4715 * Implements 'pop SReg'.
4716 *
4717 * @param iSegReg The segment register number (valid).
4718 * @param enmEffOpSize The efficient operand size (valid).
4719 */
4720IEM_CIMPL_DEF_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize)
4721{
4722 VBOXSTRICTRC rcStrict;
4723
4724 /*
4725 * Read the selector off the stack and join paths with mov ss, reg.
4726 */
4727 RTUINT64U TmpRsp;
4728 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
4729 switch (enmEffOpSize)
4730 {
4731 case IEMMODE_16BIT:
4732 {
4733 uint16_t uSel;
4734 rcStrict = iemMemStackPopU16Ex(pVCpu, &uSel, &TmpRsp);
4735 if (rcStrict == VINF_SUCCESS)
4736 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4737 break;
4738 }
4739
4740 case IEMMODE_32BIT:
4741 {
4742 uint32_t u32Value;
4743 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Value, &TmpRsp);
4744 if (rcStrict == VINF_SUCCESS)
4745 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u32Value);
4746 break;
4747 }
4748
4749 case IEMMODE_64BIT:
4750 {
4751 uint64_t u64Value;
4752 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Value, &TmpRsp);
4753 if (rcStrict == VINF_SUCCESS)
4754 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u64Value);
4755 break;
4756 }
4757 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4758 }
4759
4760 /*
4761 * Commit the stack on success.
4762 */
4763 if (rcStrict == VINF_SUCCESS)
4764 {
4765 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
4766 if (iSegReg == X86_SREG_SS)
4767 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
4768 }
4769 return rcStrict;
4770}
4771
4772
4773/**
4774 * Implements lgs, lfs, les, lds & lss.
4775 */
4776IEM_CIMPL_DEF_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize)
4777{
4778 /*
4779 * Use iemCImpl_LoadSReg to do the tricky segment register loading.
4780 */
4781 /** @todo verify and test that mov, pop and lXs works the segment
4782 * register loading in the exact same way. */
4783 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4784 if (rcStrict == VINF_SUCCESS)
4785 {
4786 switch (enmEffOpSize)
4787 {
4788 case IEMMODE_16BIT:
4789 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4790 break;
4791 case IEMMODE_32BIT:
4792 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4793 break;
4794 case IEMMODE_64BIT:
4795 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4796 break;
4797 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4798 }
4799 }
4800
4801 return rcStrict;
4802}
4803
4804
4805/**
4806 * Helper for VERR, VERW, LAR, and LSL and loads the descriptor into memory.
4807 *
4808 * @retval VINF_SUCCESS on success.
4809 * @retval VINF_IEM_SELECTOR_NOT_OK if the selector isn't ok.
4810 * @retval iemMemFetchSysU64 return value.
4811 *
4812 * @param pVCpu The cross context virtual CPU structure of the calling thread.
4813 * @param uSel The selector value.
4814 * @param fAllowSysDesc Whether system descriptors are OK or not.
4815 * @param pDesc Where to return the descriptor on success.
4816 */
4817static VBOXSTRICTRC iemCImpl_LoadDescHelper(PVMCPUCC pVCpu, uint16_t uSel, bool fAllowSysDesc, PIEMSELDESC pDesc)
4818{
4819 pDesc->Long.au64[0] = 0;
4820 pDesc->Long.au64[1] = 0;
4821
4822 if (!(uSel & X86_SEL_MASK_OFF_RPL)) /** @todo test this on 64-bit. */
4823 return VINF_IEM_SELECTOR_NOT_OK;
4824
4825 /* Within the table limits? */
4826 RTGCPTR GCPtrBase;
4827 if (uSel & X86_SEL_LDT)
4828 {
4829 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4830 if ( !pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Present
4831 || (uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.ldtr.u32Limit )
4832 return VINF_IEM_SELECTOR_NOT_OK;
4833 GCPtrBase = pVCpu->cpum.GstCtx.ldtr.u64Base;
4834 }
4835 else
4836 {
4837 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
4838 if ((uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.gdtr.cbGdt)
4839 return VINF_IEM_SELECTOR_NOT_OK;
4840 GCPtrBase = pVCpu->cpum.GstCtx.gdtr.pGdt;
4841 }
4842
4843 /* Fetch the descriptor. */
4844 VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
4845 if (rcStrict != VINF_SUCCESS)
4846 return rcStrict;
4847 if (!pDesc->Legacy.Gen.u1DescType)
4848 {
4849 if (!fAllowSysDesc)
4850 return VINF_IEM_SELECTOR_NOT_OK;
4851 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4852 {
4853 rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK) + 8);
4854 if (rcStrict != VINF_SUCCESS)
4855 return rcStrict;
4856 }
4857
4858 }
4859
4860 return VINF_SUCCESS;
4861}
4862
4863
4864/**
4865 * Implements verr (fWrite = false) and verw (fWrite = true).
4866 */
4867IEM_CIMPL_DEF_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite)
4868{
4869 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4870
4871 /** @todo figure whether the accessed bit is set or not. */
4872
4873 bool fAccessible = true;
4874 IEMSELDESC Desc;
4875 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4876 if (rcStrict == VINF_SUCCESS)
4877 {
4878 /* Check the descriptor, order doesn't matter much here. */
4879 if ( !Desc.Legacy.Gen.u1DescType
4880 || !Desc.Legacy.Gen.u1Present)
4881 fAccessible = false;
4882 else
4883 {
4884 if ( fWrite
4885 ? (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE
4886 : (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4887 fAccessible = false;
4888
4889 /** @todo testcase for the conforming behavior. */
4890 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4891 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4892 {
4893 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4894 fAccessible = false;
4895 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4896 fAccessible = false;
4897 }
4898 }
4899
4900 }
4901 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4902 fAccessible = false;
4903 else
4904 return rcStrict;
4905
4906 /* commit */
4907 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fAccessible;
4908
4909 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4910 return VINF_SUCCESS;
4911}
4912
4913
4914/**
4915 * Implements LAR and LSL with 64-bit operand size.
4916 *
4917 * @returns VINF_SUCCESS.
4918 * @param pu64Dst Pointer to the destination register.
4919 * @param uSel The selector to load details for.
4920 * @param fIsLar true = LAR, false = LSL.
4921 */
4922IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar)
4923{
4924 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4925
4926 /** @todo figure whether the accessed bit is set or not. */
4927
4928 bool fDescOk = true;
4929 IEMSELDESC Desc;
4930 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, true /*fAllowSysDesc*/, &Desc);
4931 if (rcStrict == VINF_SUCCESS)
4932 {
4933 /*
4934 * Check the descriptor type.
4935 */
4936 if (!Desc.Legacy.Gen.u1DescType)
4937 {
4938 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4939 {
4940 if (Desc.Long.Gen.u5Zeros)
4941 fDescOk = false;
4942 else
4943 switch (Desc.Long.Gen.u4Type)
4944 {
4945 /** @todo Intel lists 0 as valid for LSL, verify whether that's correct */
4946 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
4947 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
4948 case AMD64_SEL_TYPE_SYS_LDT: /** @todo Intel lists this as invalid for LAR, AMD and 32-bit does otherwise. */
4949 break;
4950 case AMD64_SEL_TYPE_SYS_CALL_GATE:
4951 fDescOk = fIsLar;
4952 break;
4953 default:
4954 fDescOk = false;
4955 break;
4956 }
4957 }
4958 else
4959 {
4960 switch (Desc.Long.Gen.u4Type)
4961 {
4962 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
4963 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
4964 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
4965 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
4966 case X86_SEL_TYPE_SYS_LDT:
4967 break;
4968 case X86_SEL_TYPE_SYS_286_CALL_GATE:
4969 case X86_SEL_TYPE_SYS_TASK_GATE:
4970 case X86_SEL_TYPE_SYS_386_CALL_GATE:
4971 fDescOk = fIsLar;
4972 break;
4973 default:
4974 fDescOk = false;
4975 break;
4976 }
4977 }
4978 }
4979 if (fDescOk)
4980 {
4981 /*
4982 * Check the RPL/DPL/CPL interaction..
4983 */
4984 /** @todo testcase for the conforming behavior. */
4985 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
4986 || !Desc.Legacy.Gen.u1DescType)
4987 {
4988 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4989 fDescOk = false;
4990 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4991 fDescOk = false;
4992 }
4993 }
4994
4995 if (fDescOk)
4996 {
4997 /*
4998 * All fine, start committing the result.
4999 */
5000 if (fIsLar)
5001 *pu64Dst = Desc.Legacy.au32[1] & UINT32_C(0x00ffff00);
5002 else
5003 *pu64Dst = X86DESC_LIMIT_G(&Desc.Legacy);
5004 }
5005
5006 }
5007 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
5008 fDescOk = false;
5009 else
5010 return rcStrict;
5011
5012 /* commit flags value and advance rip. */
5013 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fDescOk;
5014 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5015
5016 return VINF_SUCCESS;
5017}
5018
5019
5020/**
5021 * Implements LAR and LSL with 16-bit operand size.
5022 *
5023 * @returns VINF_SUCCESS.
5024 * @param pu16Dst Pointer to the destination register.
5025 * @param uSel The selector to load details for.
5026 * @param fIsLar true = LAR, false = LSL.
5027 */
5028IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar)
5029{
5030 uint64_t u64TmpDst = *pu16Dst;
5031 IEM_CIMPL_CALL_3(iemCImpl_LarLsl_u64, &u64TmpDst, uSel, fIsLar);
5032 *pu16Dst = u64TmpDst;
5033 return VINF_SUCCESS;
5034}
5035
5036
5037/**
5038 * Implements lgdt.
5039 *
5040 * @param iEffSeg The segment of the new gdtr contents
5041 * @param GCPtrEffSrc The address of the new gdtr contents.
5042 * @param enmEffOpSize The effective operand size.
5043 */
5044IEM_CIMPL_DEF_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
5045{
5046 if (pVCpu->iem.s.uCpl != 0)
5047 return iemRaiseGeneralProtectionFault0(pVCpu);
5048 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5049
5050 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5051 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5052 {
5053 Log(("lgdt: Guest intercept -> VM-exit\n"));
5054 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_GDTR_IDTR_ACCESS, VMXINSTRID_LGDT, cbInstr);
5055 }
5056
5057 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_WRITES))
5058 {
5059 Log(("lgdt: Guest intercept -> #VMEXIT\n"));
5060 IEM_SVM_UPDATE_NRIP(pVCpu);
5061 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5062 }
5063
5064 /*
5065 * Fetch the limit and base address.
5066 */
5067 uint16_t cbLimit;
5068 RTGCPTR GCPtrBase;
5069 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
5070 if (rcStrict == VINF_SUCCESS)
5071 {
5072 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
5073 || X86_IS_CANONICAL(GCPtrBase))
5074 {
5075 rcStrict = CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
5076 if (rcStrict == VINF_SUCCESS)
5077 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5078 }
5079 else
5080 {
5081 Log(("iemCImpl_lgdt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
5082 return iemRaiseGeneralProtectionFault0(pVCpu);
5083 }
5084 }
5085 return rcStrict;
5086}
5087
5088
5089/**
5090 * Implements sgdt.
5091 *
5092 * @param iEffSeg The segment where to store the gdtr content.
5093 * @param GCPtrEffDst The address where to store the gdtr content.
5094 */
5095IEM_CIMPL_DEF_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5096{
5097 /*
5098 * Join paths with sidt.
5099 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
5100 * you really must know.
5101 */
5102 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5103 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5104 {
5105 Log(("sgdt: Guest intercept -> VM-exit\n"));
5106 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_GDTR_IDTR_ACCESS, VMXINSTRID_SGDT, cbInstr);
5107 }
5108
5109 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_READS))
5110 {
5111 Log(("sgdt: Guest intercept -> #VMEXIT\n"));
5112 IEM_SVM_UPDATE_NRIP(pVCpu);
5113 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5114 }
5115
5116 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
5117 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.gdtr.pGdt, iEffSeg, GCPtrEffDst);
5118 if (rcStrict == VINF_SUCCESS)
5119 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5120 return rcStrict;
5121}
5122
5123
5124/**
5125 * Implements lidt.
5126 *
5127 * @param iEffSeg The segment of the new idtr contents
5128 * @param GCPtrEffSrc The address of the new idtr contents.
5129 * @param enmEffOpSize The effective operand size.
5130 */
5131IEM_CIMPL_DEF_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
5132{
5133 if (pVCpu->iem.s.uCpl != 0)
5134 return iemRaiseGeneralProtectionFault0(pVCpu);
5135 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5136
5137 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_WRITES))
5138 {
5139 Log(("lidt: Guest intercept -> #VMEXIT\n"));
5140 IEM_SVM_UPDATE_NRIP(pVCpu);
5141 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5142 }
5143
5144 /*
5145 * Fetch the limit and base address.
5146 */
5147 uint16_t cbLimit;
5148 RTGCPTR GCPtrBase;
5149 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
5150 if (rcStrict == VINF_SUCCESS)
5151 {
5152 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
5153 || X86_IS_CANONICAL(GCPtrBase))
5154 {
5155 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
5156 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5157 }
5158 else
5159 {
5160 Log(("iemCImpl_lidt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
5161 return iemRaiseGeneralProtectionFault0(pVCpu);
5162 }
5163 }
5164 return rcStrict;
5165}
5166
5167
5168/**
5169 * Implements sidt.
5170 *
5171 * @param iEffSeg The segment where to store the idtr content.
5172 * @param GCPtrEffDst The address where to store the idtr content.
5173 */
5174IEM_CIMPL_DEF_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5175{
5176 /*
5177 * Join paths with sgdt.
5178 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
5179 * you really must know.
5180 */
5181 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_READS))
5182 {
5183 Log(("sidt: Guest intercept -> #VMEXIT\n"));
5184 IEM_SVM_UPDATE_NRIP(pVCpu);
5185 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5186 }
5187
5188 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_IDTR);
5189 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.idtr.cbIdt, pVCpu->cpum.GstCtx.idtr.pIdt, iEffSeg, GCPtrEffDst);
5190 if (rcStrict == VINF_SUCCESS)
5191 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5192 return rcStrict;
5193}
5194
5195
5196/**
5197 * Implements lldt.
5198 *
5199 * @param uNewLdt The new LDT selector value.
5200 */
5201IEM_CIMPL_DEF_1(iemCImpl_lldt, uint16_t, uNewLdt)
5202{
5203 /*
5204 * Check preconditions.
5205 */
5206 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
5207 {
5208 Log(("lldt %04x - real or v8086 mode -> #GP(0)\n", uNewLdt));
5209 return iemRaiseUndefinedOpcode(pVCpu);
5210 }
5211 if (pVCpu->iem.s.uCpl != 0)
5212 {
5213 Log(("lldt %04x - CPL is %d -> #GP(0)\n", uNewLdt, pVCpu->iem.s.uCpl));
5214 return iemRaiseGeneralProtectionFault0(pVCpu);
5215 }
5216 /* Nested-guest VMX intercept. */
5217 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5218 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5219 {
5220 Log(("lldt: Guest intercept -> VM-exit\n"));
5221 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_LLDT, cbInstr);
5222 }
5223 if (uNewLdt & X86_SEL_LDT)
5224 {
5225 Log(("lldt %04x - LDT selector -> #GP\n", uNewLdt));
5226 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewLdt);
5227 }
5228
5229 /*
5230 * Now, loading a NULL selector is easy.
5231 */
5232 if (!(uNewLdt & X86_SEL_MASK_OFF_RPL))
5233 {
5234 /* Nested-guest SVM intercept. */
5235 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
5236 {
5237 Log(("lldt: Guest intercept -> #VMEXIT\n"));
5238 IEM_SVM_UPDATE_NRIP(pVCpu);
5239 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5240 }
5241
5242 Log(("lldt %04x: Loading NULL selector.\n", uNewLdt));
5243 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_LDTR;
5244 CPUMSetGuestLDTR(pVCpu, uNewLdt);
5245 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt;
5246 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5247 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
5248 {
5249 /* AMD-V seems to leave the base and limit alone. */
5250 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
5251 }
5252 else
5253 {
5254 /* VT-x (Intel 3960x) seems to be doing the following. */
5255 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D;
5256 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
5257 pVCpu->cpum.GstCtx.ldtr.u32Limit = UINT32_MAX;
5258 }
5259
5260 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5261 return VINF_SUCCESS;
5262 }
5263
5264 /*
5265 * Read the descriptor.
5266 */
5267 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR);
5268 IEMSELDESC Desc;
5269 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewLdt, X86_XCPT_GP); /** @todo Correct exception? */
5270 if (rcStrict != VINF_SUCCESS)
5271 return rcStrict;
5272
5273 /* Check GPs first. */
5274 if (Desc.Legacy.Gen.u1DescType)
5275 {
5276 Log(("lldt %#x - not system selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
5277 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5278 }
5279 if (Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
5280 {
5281 Log(("lldt %#x - not LDT selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
5282 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5283 }
5284 uint64_t u64Base;
5285 if (!IEM_IS_LONG_MODE(pVCpu))
5286 u64Base = X86DESC_BASE(&Desc.Legacy);
5287 else
5288 {
5289 if (Desc.Long.Gen.u5Zeros)
5290 {
5291 Log(("lldt %#x - u5Zeros=%#x -> #GP\n", uNewLdt, Desc.Long.Gen.u5Zeros));
5292 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5293 }
5294
5295 u64Base = X86DESC64_BASE(&Desc.Long);
5296 if (!IEM_IS_CANONICAL(u64Base))
5297 {
5298 Log(("lldt %#x - non-canonical base address %#llx -> #GP\n", uNewLdt, u64Base));
5299 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5300 }
5301 }
5302
5303 /* NP */
5304 if (!Desc.Legacy.Gen.u1Present)
5305 {
5306 Log(("lldt %#x - segment not present -> #NP\n", uNewLdt));
5307 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewLdt);
5308 }
5309
5310 /* Nested-guest SVM intercept. */
5311 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
5312 {
5313 Log(("lldt: Guest intercept -> #VMEXIT\n"));
5314 IEM_SVM_UPDATE_NRIP(pVCpu);
5315 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5316 }
5317
5318 /*
5319 * It checks out alright, update the registers.
5320 */
5321/** @todo check if the actual value is loaded or if the RPL is dropped */
5322 CPUMSetGuestLDTR(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5323 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt & X86_SEL_MASK_OFF_RPL;
5324 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5325 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5326 pVCpu->cpum.GstCtx.ldtr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5327 pVCpu->cpum.GstCtx.ldtr.u64Base = u64Base;
5328
5329 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5330 return VINF_SUCCESS;
5331}
5332
5333
5334/**
5335 * Implements sldt GReg
5336 *
5337 * @param iGReg The general register to store the CRx value in.
5338 * @param enmEffOpSize The operand size.
5339 */
5340IEM_CIMPL_DEF_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5341{
5342 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5343 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5344 {
5345 Log(("sldt: Guest intercept -> VM-exit\n"));
5346 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_SLDT, cbInstr);
5347 }
5348
5349 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
5350
5351 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
5352 switch (enmEffOpSize)
5353 {
5354 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5355 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5356 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5357 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5358 }
5359 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5360 return VINF_SUCCESS;
5361}
5362
5363
5364/**
5365 * Implements sldt mem.
5366 *
5367 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5368 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5369 */
5370IEM_CIMPL_DEF_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5371{
5372 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
5373
5374 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
5375 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.ldtr.Sel);
5376 if (rcStrict == VINF_SUCCESS)
5377 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5378 return rcStrict;
5379}
5380
5381
5382/**
5383 * Implements ltr.
5384 *
5385 * @param uNewTr The new TSS selector value.
5386 */
5387IEM_CIMPL_DEF_1(iemCImpl_ltr, uint16_t, uNewTr)
5388{
5389 /*
5390 * Check preconditions.
5391 */
5392 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
5393 {
5394 Log(("ltr %04x - real or v8086 mode -> #GP(0)\n", uNewTr));
5395 return iemRaiseUndefinedOpcode(pVCpu);
5396 }
5397 if (pVCpu->iem.s.uCpl != 0)
5398 {
5399 Log(("ltr %04x - CPL is %d -> #GP(0)\n", uNewTr, pVCpu->iem.s.uCpl));
5400 return iemRaiseGeneralProtectionFault0(pVCpu);
5401 }
5402 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5403 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5404 {
5405 Log(("ltr: Guest intercept -> VM-exit\n"));
5406 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_LTR, cbInstr);
5407 }
5408 if (uNewTr & X86_SEL_LDT)
5409 {
5410 Log(("ltr %04x - LDT selector -> #GP\n", uNewTr));
5411 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewTr);
5412 }
5413 if (!(uNewTr & X86_SEL_MASK_OFF_RPL))
5414 {
5415 Log(("ltr %04x - NULL selector -> #GP(0)\n", uNewTr));
5416 return iemRaiseGeneralProtectionFault0(pVCpu);
5417 }
5418 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_TR_WRITES))
5419 {
5420 Log(("ltr: Guest intercept -> #VMEXIT\n"));
5421 IEM_SVM_UPDATE_NRIP(pVCpu);
5422 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_TR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5423 }
5424
5425 /*
5426 * Read the descriptor.
5427 */
5428 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_TR);
5429 IEMSELDESC Desc;
5430 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewTr, X86_XCPT_GP); /** @todo Correct exception? */
5431 if (rcStrict != VINF_SUCCESS)
5432 return rcStrict;
5433
5434 /* Check GPs first. */
5435 if (Desc.Legacy.Gen.u1DescType)
5436 {
5437 Log(("ltr %#x - not system selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
5438 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5439 }
5440 if ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL /* same as AMD64_SEL_TYPE_SYS_TSS_AVAIL */
5441 && ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
5442 || IEM_IS_LONG_MODE(pVCpu)) )
5443 {
5444 Log(("ltr %#x - not an available TSS selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
5445 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5446 }
5447 uint64_t u64Base;
5448 if (!IEM_IS_LONG_MODE(pVCpu))
5449 u64Base = X86DESC_BASE(&Desc.Legacy);
5450 else
5451 {
5452 if (Desc.Long.Gen.u5Zeros)
5453 {
5454 Log(("ltr %#x - u5Zeros=%#x -> #GP\n", uNewTr, Desc.Long.Gen.u5Zeros));
5455 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5456 }
5457
5458 u64Base = X86DESC64_BASE(&Desc.Long);
5459 if (!IEM_IS_CANONICAL(u64Base))
5460 {
5461 Log(("ltr %#x - non-canonical base address %#llx -> #GP\n", uNewTr, u64Base));
5462 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5463 }
5464 }
5465
5466 /* NP */
5467 if (!Desc.Legacy.Gen.u1Present)
5468 {
5469 Log(("ltr %#x - segment not present -> #NP\n", uNewTr));
5470 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewTr);
5471 }
5472
5473 /*
5474 * Set it busy.
5475 * Note! Intel says this should lock down the whole descriptor, but we'll
5476 * restrict our selves to 32-bit for now due to lack of inline
5477 * assembly and such.
5478 */
5479 void *pvDesc;
5480 rcStrict = iemMemMap(pVCpu, &pvDesc, 8, UINT8_MAX, pVCpu->cpum.GstCtx.gdtr.pGdt + (uNewTr & X86_SEL_MASK_OFF_RPL),
5481 IEM_ACCESS_DATA_RW, 0);
5482 if (rcStrict != VINF_SUCCESS)
5483 return rcStrict;
5484 switch ((uintptr_t)pvDesc & 3)
5485 {
5486 case 0: ASMAtomicBitSet(pvDesc, 40 + 1); break;
5487 case 1: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 24); break;
5488 case 2: ASMAtomicBitSet((uint8_t *)pvDesc + 2, 40 + 1 - 16); break;
5489 case 3: ASMAtomicBitSet((uint8_t *)pvDesc + 1, 40 + 1 - 8); break;
5490 }
5491 rcStrict = iemMemCommitAndUnmap(pVCpu, pvDesc, IEM_ACCESS_DATA_RW);
5492 if (rcStrict != VINF_SUCCESS)
5493 return rcStrict;
5494 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
5495
5496 /*
5497 * It checks out alright, update the registers.
5498 */
5499/** @todo check if the actual value is loaded or if the RPL is dropped */
5500 CPUMSetGuestTR(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5501 pVCpu->cpum.GstCtx.tr.ValidSel = uNewTr & X86_SEL_MASK_OFF_RPL;
5502 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
5503 pVCpu->cpum.GstCtx.tr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5504 pVCpu->cpum.GstCtx.tr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5505 pVCpu->cpum.GstCtx.tr.u64Base = u64Base;
5506
5507 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5508 return VINF_SUCCESS;
5509}
5510
5511
5512/**
5513 * Implements str GReg
5514 *
5515 * @param iGReg The general register to store the CRx value in.
5516 * @param enmEffOpSize The operand size.
5517 */
5518IEM_CIMPL_DEF_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5519{
5520 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5521 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5522 {
5523 Log(("str_reg: Guest intercept -> VM-exit\n"));
5524 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_STR, cbInstr);
5525 }
5526
5527 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5528
5529 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5530 switch (enmEffOpSize)
5531 {
5532 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5533 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5534 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5535 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5536 }
5537 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5538 return VINF_SUCCESS;
5539}
5540
5541
5542/**
5543 * Implements str mem.
5544 *
5545 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5546 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5547 */
5548IEM_CIMPL_DEF_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5549{
5550 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5551 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5552 {
5553 Log(("str_mem: Guest intercept -> VM-exit\n"));
5554 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_STR, cbInstr);
5555 }
5556
5557 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5558
5559 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5560 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.tr.Sel);
5561 if (rcStrict == VINF_SUCCESS)
5562 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5563 return rcStrict;
5564}
5565
5566
5567/**
5568 * Implements mov GReg,CRx.
5569 *
5570 * @param iGReg The general register to store the CRx value in.
5571 * @param iCrReg The CRx register to read (valid).
5572 */
5573IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg)
5574{
5575 if (pVCpu->iem.s.uCpl != 0)
5576 return iemRaiseGeneralProtectionFault0(pVCpu);
5577 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5578
5579 if (IEM_SVM_IS_READ_CR_INTERCEPT_SET(pVCpu, iCrReg))
5580 {
5581 Log(("iemCImpl_mov_Rd_Cd: Guest intercept CR%u -> #VMEXIT\n", iCrReg));
5582 IEM_SVM_UPDATE_NRIP(pVCpu);
5583 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_READ_CR0 + iCrReg, IEMACCESSCRX_MOV_CRX, iGReg);
5584 }
5585
5586 /* Read it. */
5587 uint64_t crX;
5588 switch (iCrReg)
5589 {
5590 case 0:
5591 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5592 crX = pVCpu->cpum.GstCtx.cr0;
5593 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
5594 crX |= UINT32_C(0x7fffffe0); /* All reserved CR0 flags are set on a 386, just like MSW on 286. */
5595 break;
5596 case 2:
5597 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR2);
5598 crX = pVCpu->cpum.GstCtx.cr2;
5599 break;
5600 case 3:
5601 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5602 crX = pVCpu->cpum.GstCtx.cr3;
5603 break;
5604 case 4:
5605 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
5606 crX = pVCpu->cpum.GstCtx.cr4;
5607 break;
5608 case 8:
5609 {
5610 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
5611#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5612 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5613 {
5614 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovFromCr8(pVCpu, iGReg, cbInstr);
5615 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5616 return rcStrict;
5617
5618 /*
5619 * If the Mov-from-CR8 doesn't cause a VM-exit, bits 7:4 of the VTPR is copied
5620 * to bits 0:3 of the destination operand. Bits 63:4 of the destination operand
5621 * are cleared.
5622 *
5623 * See Intel Spec. 29.3 "Virtualizing CR8-based TPR Accesses"
5624 */
5625 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_USE_TPR_SHADOW))
5626 {
5627 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5628 crX = (uTpr >> 4) & 0xf;
5629 break;
5630 }
5631 }
5632#endif
5633#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5634 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5635 {
5636 PCSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
5637 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
5638 {
5639 crX = pVmcbCtrl->IntCtrl.n.u8VTPR & 0xf;
5640 break;
5641 }
5642 }
5643#endif
5644 uint8_t uTpr;
5645 int rc = APICGetTpr(pVCpu, &uTpr, NULL, NULL);
5646 if (RT_SUCCESS(rc))
5647 crX = uTpr >> 4;
5648 else
5649 crX = 0;
5650 break;
5651 }
5652 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5653 }
5654
5655#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5656 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5657 {
5658 switch (iCrReg)
5659 {
5660 /* CR0/CR4 reads are subject to masking when in VMX non-root mode. */
5661 case 0: crX = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u); break;
5662 case 4: crX = CPUMGetGuestVmxMaskedCr4(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u); break;
5663
5664 case 3:
5665 {
5666 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovFromCr3(pVCpu, iGReg, cbInstr);
5667 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5668 return rcStrict;
5669 break;
5670 }
5671 }
5672 }
5673#endif
5674
5675 /* Store it. */
5676 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5677 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = crX;
5678 else
5679 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX;
5680
5681 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5682 return VINF_SUCCESS;
5683}
5684
5685
5686/**
5687 * Implements smsw GReg.
5688 *
5689 * @param iGReg The general register to store the CRx value in.
5690 * @param enmEffOpSize The operand size.
5691 */
5692IEM_CIMPL_DEF_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5693{
5694 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5695
5696#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5697 uint64_t u64MaskedCr0;
5698 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5699 u64MaskedCr0 = pVCpu->cpum.GstCtx.cr0;
5700 else
5701 u64MaskedCr0 = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u);
5702 uint64_t const u64GuestCr0 = u64MaskedCr0;
5703#else
5704 uint64_t const u64GuestCr0 = pVCpu->cpum.GstCtx.cr0;
5705#endif
5706
5707 switch (enmEffOpSize)
5708 {
5709 case IEMMODE_16BIT:
5710 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5711 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0;
5712 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5713 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xffe0;
5714 else
5715 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xfff0;
5716 break;
5717
5718 case IEMMODE_32BIT:
5719 *(uint32_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)u64GuestCr0;
5720 break;
5721
5722 case IEMMODE_64BIT:
5723 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = u64GuestCr0;
5724 break;
5725
5726 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5727 }
5728
5729 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5730 return VINF_SUCCESS;
5731}
5732
5733
5734/**
5735 * Implements smsw mem.
5736 *
5737 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5738 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5739 */
5740IEM_CIMPL_DEF_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5741{
5742 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5743
5744#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5745 uint64_t u64MaskedCr0;
5746 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5747 u64MaskedCr0 = pVCpu->cpum.GstCtx.cr0;
5748 else
5749 u64MaskedCr0 = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u);
5750 uint64_t const u64GuestCr0 = u64MaskedCr0;
5751#else
5752 uint64_t const u64GuestCr0 = pVCpu->cpum.GstCtx.cr0;
5753#endif
5754
5755 uint16_t u16Value;
5756 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5757 u16Value = (uint16_t)u64GuestCr0;
5758 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5759 u16Value = (uint16_t)u64GuestCr0 | 0xffe0;
5760 else
5761 u16Value = (uint16_t)u64GuestCr0 | 0xfff0;
5762
5763 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, u16Value);
5764 if (rcStrict == VINF_SUCCESS)
5765 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5766 return rcStrict;
5767}
5768
5769
5770/**
5771 * Helper for mapping CR3 and PAE PDPEs for 'mov CRx,GReg'.
5772 */
5773#define IEM_MAP_PAE_PDPES_AT_CR3_RET(a_pVCpu, a_iCrReg, a_uCr3) \
5774 do \
5775 { \
5776 int const rcX = PGMGstMapPaePdpesAtCr3(a_pVCpu, a_uCr3); \
5777 if (RT_SUCCESS(rcX)) \
5778 { /* likely */ } \
5779 else \
5780 { \
5781 /* Either invalid PDPTEs or CR3 second-level translation failed. Raise #GP(0) either way. */ \
5782 Log(("iemCImpl_load_Cr%#x: Trying to load invalid PAE PDPEs\n", a_iCrReg)); \
5783 return iemRaiseGeneralProtectionFault0(a_pVCpu); \
5784 } \
5785 } while (0)
5786
5787
5788/**
5789 * Used to implemented 'mov CRx,GReg' and 'lmsw r/m16'.
5790 *
5791 * @param iCrReg The CRx register to write (valid).
5792 * @param uNewCrX The new value.
5793 * @param enmAccessCrX The instruction that caused the CrX load.
5794 * @param iGReg The general register in case of a 'mov CRx,GReg'
5795 * instruction.
5796 */
5797IEM_CIMPL_DEF_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg)
5798{
5799 VBOXSTRICTRC rcStrict;
5800 int rc;
5801#ifndef VBOX_WITH_NESTED_HWVIRT_SVM
5802 RT_NOREF2(iGReg, enmAccessCrX);
5803#endif
5804
5805 /*
5806 * Try store it.
5807 * Unfortunately, CPUM only does a tiny bit of the work.
5808 */
5809 switch (iCrReg)
5810 {
5811 case 0:
5812 {
5813 /*
5814 * Perform checks.
5815 */
5816 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5817
5818 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr0;
5819 uint32_t const fValid = CPUMGetGuestCR0ValidMask();
5820
5821 /* ET is hardcoded on 486 and later. */
5822 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_486)
5823 uNewCrX |= X86_CR0_ET;
5824 /* The 386 and 486 didn't #GP(0) on attempting to set reserved CR0 bits. ET was settable on 386. */
5825 else if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_486)
5826 {
5827 uNewCrX &= fValid;
5828 uNewCrX |= X86_CR0_ET;
5829 }
5830 else
5831 uNewCrX &= X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG | X86_CR0_ET;
5832
5833 /* Check for reserved bits. */
5834 if (uNewCrX & ~(uint64_t)fValid)
5835 {
5836 Log(("Trying to set reserved CR0 bits: NewCR0=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5837 return iemRaiseGeneralProtectionFault0(pVCpu);
5838 }
5839
5840 /* Check for invalid combinations. */
5841 if ( (uNewCrX & X86_CR0_PG)
5842 && !(uNewCrX & X86_CR0_PE) )
5843 {
5844 Log(("Trying to set CR0.PG without CR0.PE\n"));
5845 return iemRaiseGeneralProtectionFault0(pVCpu);
5846 }
5847
5848 if ( !(uNewCrX & X86_CR0_CD)
5849 && (uNewCrX & X86_CR0_NW) )
5850 {
5851 Log(("Trying to clear CR0.CD while leaving CR0.NW set\n"));
5852 return iemRaiseGeneralProtectionFault0(pVCpu);
5853 }
5854
5855 if ( !(uNewCrX & X86_CR0_PG)
5856 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE))
5857 {
5858 Log(("Trying to clear CR0.PG while leaving CR4.PCID set\n"));
5859 return iemRaiseGeneralProtectionFault0(pVCpu);
5860 }
5861
5862 /* Long mode consistency checks. */
5863 if ( (uNewCrX & X86_CR0_PG)
5864 && !(uOldCrX & X86_CR0_PG)
5865 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5866 {
5867 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE))
5868 {
5869 Log(("Trying to enabled long mode paging without CR4.PAE set\n"));
5870 return iemRaiseGeneralProtectionFault0(pVCpu);
5871 }
5872 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long)
5873 {
5874 Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
5875 return iemRaiseGeneralProtectionFault0(pVCpu);
5876 }
5877 }
5878
5879 /* Check for bits that must remain set or cleared in VMX operation,
5880 see Intel spec. 23.8 "Restrictions on VMX operation". */
5881 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
5882 {
5883#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5884 uint64_t const uCr0Fixed0 = IEM_VMX_IS_NON_ROOT_MODE(pVCpu) ? iemVmxGetCr0Fixed0(pVCpu) : VMX_V_CR0_FIXED0;
5885#else
5886 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
5887#endif
5888 if ((uNewCrX & uCr0Fixed0) != uCr0Fixed0)
5889 {
5890 Log(("Trying to clear reserved CR0 bits in VMX operation: NewCr0=%#llx MB1=%#llx\n", uNewCrX, uCr0Fixed0));
5891 return iemRaiseGeneralProtectionFault0(pVCpu);
5892 }
5893
5894 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5895 if (uNewCrX & ~uCr0Fixed1)
5896 {
5897 Log(("Trying to set reserved CR0 bits in VMX operation: NewCr0=%#llx MB0=%#llx\n", uNewCrX, uCr0Fixed1));
5898 return iemRaiseGeneralProtectionFault0(pVCpu);
5899 }
5900 }
5901
5902 /*
5903 * SVM nested-guest CR0 write intercepts.
5904 */
5905 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, iCrReg))
5906 {
5907 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5908 IEM_SVM_UPDATE_NRIP(pVCpu);
5909 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR0, enmAccessCrX, iGReg);
5910 }
5911 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5912 {
5913 /* 'lmsw' intercepts regardless of whether the TS/MP bits are actually toggled. */
5914 if ( enmAccessCrX == IEMACCESSCRX_LMSW
5915 || (uNewCrX & ~(X86_CR0_TS | X86_CR0_MP)) != (uOldCrX & ~(X86_CR0_TS | X86_CR0_MP)))
5916 {
5917 Assert(enmAccessCrX != IEMACCESSCRX_CLTS);
5918 Log(("iemCImpl_load_Cr%#x: lmsw or bits other than TS/MP changed: Guest intercept -> #VMEXIT\n", iCrReg));
5919 IEM_SVM_UPDATE_NRIP(pVCpu);
5920 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_CR0_SEL_WRITE, enmAccessCrX, iGReg);
5921 }
5922 }
5923
5924 /*
5925 * Change EFER.LMA if entering or leaving long mode.
5926 */
5927 uint64_t NewEFER = pVCpu->cpum.GstCtx.msrEFER;
5928 if ( (uNewCrX & X86_CR0_PG) != (uOldCrX & X86_CR0_PG)
5929 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5930 {
5931 if (uNewCrX & X86_CR0_PG)
5932 NewEFER |= MSR_K6_EFER_LMA;
5933 else
5934 NewEFER &= ~MSR_K6_EFER_LMA;
5935
5936 CPUMSetGuestEFER(pVCpu, NewEFER);
5937 Assert(pVCpu->cpum.GstCtx.msrEFER == NewEFER);
5938 }
5939
5940 /*
5941 * Inform PGM.
5942 */
5943 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE | X86_CR0_CD | X86_CR0_NW))
5944 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE | X86_CR0_CD | X86_CR0_NW)) )
5945 {
5946 if ( enmAccessCrX != IEMACCESSCRX_MOV_CRX
5947 || !CPUMIsPaePagingEnabled(uNewCrX, pVCpu->cpum.GstCtx.cr4, NewEFER)
5948 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5949 { /* likely */ }
5950 else
5951 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, pVCpu->cpum.GstCtx.cr3);
5952 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
5953 AssertRCReturn(rc, rc);
5954 /* ignore informational status codes */
5955 }
5956
5957 /*
5958 * Change CR0.
5959 */
5960 CPUMSetGuestCR0(pVCpu, uNewCrX);
5961 Assert(pVCpu->cpum.GstCtx.cr0 == uNewCrX);
5962
5963 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
5964 false /* fForce */);
5965 break;
5966 }
5967
5968 /*
5969 * CR2 can be changed without any restrictions.
5970 */
5971 case 2:
5972 {
5973 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 2))
5974 {
5975 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5976 IEM_SVM_UPDATE_NRIP(pVCpu);
5977 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR2, enmAccessCrX, iGReg);
5978 }
5979 pVCpu->cpum.GstCtx.cr2 = uNewCrX;
5980 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_CR2;
5981 rcStrict = VINF_SUCCESS;
5982 break;
5983 }
5984
5985 /*
5986 * CR3 is relatively simple, although AMD and Intel have different
5987 * accounts of how setting reserved bits are handled. We take intel's
5988 * word for the lower bits and AMD's for the high bits (63:52). The
5989 * lower reserved bits are ignored and left alone; OpenBSD 5.8 relies
5990 * on this.
5991 */
5992 /** @todo Testcase: Setting reserved bits in CR3, especially before
5993 * enabling paging. */
5994 case 3:
5995 {
5996 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5997
5998 /* Bit 63 being clear in the source operand with PCIDE indicates no invalidations are required. */
5999 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE)
6000 && (uNewCrX & RT_BIT_64(63)))
6001 {
6002 /** @todo r=ramshankar: avoiding a TLB flush altogether here causes Windows 10
6003 * SMP(w/o nested-paging) to hang during bootup on Skylake systems, see
6004 * Intel spec. 4.10.4.1 "Operations that Invalidate TLBs and
6005 * Paging-Structure Caches". */
6006 uNewCrX &= ~RT_BIT_64(63);
6007 }
6008
6009 /* Check / mask the value. */
6010#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6011 /* See Intel spec. 27.2.2 "EPT Translation Mechanism" footnote. */
6012 uint64_t const fInvPhysMask = !CPUMIsGuestVmxEptPagingEnabledEx(IEM_GET_CTX(pVCpu))
6013 ? (UINT64_MAX << IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth)
6014 : (~X86_CR3_EPT_PAGE_MASK & X86_PAGE_4K_BASE_MASK);
6015#else
6016 uint64_t const fInvPhysMask = UINT64_C(0xfff0000000000000);
6017#endif
6018 if (uNewCrX & fInvPhysMask)
6019 {
6020 /** @todo Should we raise this only for 64-bit mode like Intel claims? AMD is
6021 * very vague in this area. As mentioned above, need testcase on real
6022 * hardware... Sigh. */
6023 Log(("Trying to load CR3 with invalid high bits set: %#llx\n", uNewCrX));
6024 return iemRaiseGeneralProtectionFault0(pVCpu);
6025 }
6026
6027 uint64_t fValid;
6028 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
6029 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME))
6030 {
6031 /** @todo Redundant? This value has already been validated above. */
6032 fValid = UINT64_C(0x000fffffffffffff);
6033 }
6034 else
6035 fValid = UINT64_C(0xffffffff);
6036 if (uNewCrX & ~fValid)
6037 {
6038 Log(("Automatically clearing reserved MBZ bits in CR3 load: NewCR3=%#llx ClearedBits=%#llx\n",
6039 uNewCrX, uNewCrX & ~fValid));
6040 uNewCrX &= fValid;
6041 }
6042
6043 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 3))
6044 {
6045 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6046 IEM_SVM_UPDATE_NRIP(pVCpu);
6047 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR3, enmAccessCrX, iGReg);
6048 }
6049
6050 /* Inform PGM. */
6051 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG)
6052 {
6053 if ( !CPUMIsGuestInPAEModeEx(IEM_GET_CTX(pVCpu))
6054 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6055 { /* likely */ }
6056 else
6057 {
6058 Assert(enmAccessCrX == IEMACCESSCRX_MOV_CRX);
6059 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, uNewCrX);
6060 }
6061 rc = PGMFlushTLB(pVCpu, uNewCrX, !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PGE));
6062 AssertRCReturn(rc, rc);
6063 /* ignore informational status codes */
6064 }
6065
6066 /* Make the change. */
6067 rc = CPUMSetGuestCR3(pVCpu, uNewCrX);
6068 AssertRCSuccessReturn(rc, rc);
6069
6070 rcStrict = VINF_SUCCESS;
6071 break;
6072 }
6073
6074 /*
6075 * CR4 is a bit more tedious as there are bits which cannot be cleared
6076 * under some circumstances and such.
6077 */
6078 case 4:
6079 {
6080 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6081 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr4;
6082
6083 /* Reserved bits. */
6084 uint32_t const fValid = CPUMGetGuestCR4ValidMask(pVCpu->CTX_SUFF(pVM));
6085 if (uNewCrX & ~(uint64_t)fValid)
6086 {
6087 Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
6088 return iemRaiseGeneralProtectionFault0(pVCpu);
6089 }
6090
6091 bool const fPcide = !(uOldCrX & X86_CR4_PCIDE) && (uNewCrX & X86_CR4_PCIDE);
6092 bool const fLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
6093
6094 /* PCIDE check. */
6095 if ( fPcide
6096 && ( !fLongMode
6097 || (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))))
6098 {
6099 Log(("Trying to set PCIDE with invalid PCID or outside long mode. Pcid=%#x\n", (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))));
6100 return iemRaiseGeneralProtectionFault0(pVCpu);
6101 }
6102
6103 /* PAE check. */
6104 if ( fLongMode
6105 && (uOldCrX & X86_CR4_PAE)
6106 && !(uNewCrX & X86_CR4_PAE))
6107 {
6108 Log(("Trying to set clear CR4.PAE while long mode is active\n"));
6109 return iemRaiseGeneralProtectionFault0(pVCpu);
6110 }
6111
6112 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 4))
6113 {
6114 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6115 IEM_SVM_UPDATE_NRIP(pVCpu);
6116 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR4, enmAccessCrX, iGReg);
6117 }
6118
6119 /* Check for bits that must remain set or cleared in VMX operation,
6120 see Intel spec. 23.8 "Restrictions on VMX operation". */
6121 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
6122 {
6123 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6124 if ((uNewCrX & uCr4Fixed0) != uCr4Fixed0)
6125 {
6126 Log(("Trying to clear reserved CR4 bits in VMX operation: NewCr4=%#llx MB1=%#llx\n", uNewCrX, uCr4Fixed0));
6127 return iemRaiseGeneralProtectionFault0(pVCpu);
6128 }
6129
6130 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6131 if (uNewCrX & ~uCr4Fixed1)
6132 {
6133 Log(("Trying to set reserved CR4 bits in VMX operation: NewCr4=%#llx MB0=%#llx\n", uNewCrX, uCr4Fixed1));
6134 return iemRaiseGeneralProtectionFault0(pVCpu);
6135 }
6136 }
6137
6138 /*
6139 * Notify PGM.
6140 */
6141 if ((uNewCrX ^ uOldCrX) & (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_PCIDE /* | X86_CR4_SMEP */))
6142 {
6143 if ( !CPUMIsPaePagingEnabled(pVCpu->cpum.GstCtx.cr0, uNewCrX, pVCpu->cpum.GstCtx.msrEFER)
6144 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6145 { /* likely */ }
6146 else
6147 {
6148 Assert(enmAccessCrX == IEMACCESSCRX_MOV_CRX);
6149 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, pVCpu->cpum.GstCtx.cr3);
6150 }
6151 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
6152 AssertRCReturn(rc, rc);
6153 /* ignore informational status codes */
6154 }
6155
6156 /*
6157 * Change it.
6158 */
6159 rc = CPUMSetGuestCR4(pVCpu, uNewCrX);
6160 AssertRCSuccessReturn(rc, rc);
6161 Assert(pVCpu->cpum.GstCtx.cr4 == uNewCrX);
6162
6163 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
6164 false /* fForce */);
6165 break;
6166 }
6167
6168 /*
6169 * CR8 maps to the APIC TPR.
6170 */
6171 case 8:
6172 {
6173 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
6174 if (uNewCrX & ~(uint64_t)0xf)
6175 {
6176 Log(("Trying to set reserved CR8 bits (%#RX64)\n", uNewCrX));
6177 return iemRaiseGeneralProtectionFault0(pVCpu);
6178 }
6179
6180#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6181 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6182 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_USE_TPR_SHADOW))
6183 {
6184 /*
6185 * If the Mov-to-CR8 doesn't cause a VM-exit, bits 0:3 of the source operand
6186 * is copied to bits 7:4 of the VTPR. Bits 0:3 and bits 31:8 of the VTPR are
6187 * cleared. Following this the processor performs TPR virtualization.
6188 *
6189 * However, we should not perform TPR virtualization immediately here but
6190 * after this instruction has completed.
6191 *
6192 * See Intel spec. 29.3 "Virtualizing CR8-based TPR Accesses"
6193 * See Intel spec. 27.1 "Architectural State Before A VM-exit"
6194 */
6195 uint32_t const uTpr = (uNewCrX & 0xf) << 4;
6196 Log(("iemCImpl_load_Cr%#x: Virtualizing TPR (%#x) write\n", iCrReg, uTpr));
6197 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
6198 iemVmxVirtApicSetPendingWrite(pVCpu, XAPIC_OFF_TPR);
6199 rcStrict = VINF_SUCCESS;
6200 break;
6201 }
6202#endif
6203
6204#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6205 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6206 {
6207 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 8))
6208 {
6209 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6210 IEM_SVM_UPDATE_NRIP(pVCpu);
6211 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR8, enmAccessCrX, iGReg);
6212 }
6213
6214 pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u8VTPR = uNewCrX;
6215 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
6216 {
6217 rcStrict = VINF_SUCCESS;
6218 break;
6219 }
6220 }
6221#endif
6222 uint8_t const u8Tpr = (uint8_t)uNewCrX << 4;
6223 APICSetTpr(pVCpu, u8Tpr);
6224 rcStrict = VINF_SUCCESS;
6225 break;
6226 }
6227
6228 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
6229 }
6230
6231 /*
6232 * Advance the RIP on success.
6233 */
6234 if (RT_SUCCESS(rcStrict))
6235 {
6236 if (rcStrict != VINF_SUCCESS)
6237 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6238 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6239 }
6240
6241 return rcStrict;
6242}
6243
6244
6245/**
6246 * Implements mov CRx,GReg.
6247 *
6248 * @param iCrReg The CRx register to write (valid).
6249 * @param iGReg The general register to load the CRx value from.
6250 */
6251IEM_CIMPL_DEF_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg)
6252{
6253 if (pVCpu->iem.s.uCpl != 0)
6254 return iemRaiseGeneralProtectionFault0(pVCpu);
6255 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6256
6257 /*
6258 * Read the new value from the source register and call common worker.
6259 */
6260 uint64_t uNewCrX;
6261 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6262 uNewCrX = iemGRegFetchU64(pVCpu, iGReg);
6263 else
6264 uNewCrX = iemGRegFetchU32(pVCpu, iGReg);
6265
6266#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6267 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6268 {
6269 VBOXSTRICTRC rcStrict = VINF_VMX_INTERCEPT_NOT_ACTIVE;
6270 switch (iCrReg)
6271 {
6272 case 0:
6273 case 4: rcStrict = iemVmxVmexitInstrMovToCr0Cr4(pVCpu, iCrReg, &uNewCrX, iGReg, cbInstr); break;
6274 case 3: rcStrict = iemVmxVmexitInstrMovToCr3(pVCpu, uNewCrX, iGReg, cbInstr); break;
6275 case 8: rcStrict = iemVmxVmexitInstrMovToCr8(pVCpu, iGReg, cbInstr); break;
6276 }
6277 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6278 return rcStrict;
6279 }
6280#endif
6281
6282 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, iCrReg, uNewCrX, IEMACCESSCRX_MOV_CRX, iGReg);
6283}
6284
6285
6286/**
6287 * Implements 'LMSW r/m16'
6288 *
6289 * @param u16NewMsw The new value.
6290 * @param GCPtrEffDst The guest-linear address of the source operand in case
6291 * of a memory operand. For register operand, pass
6292 * NIL_RTGCPTR.
6293 */
6294IEM_CIMPL_DEF_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst)
6295{
6296 if (pVCpu->iem.s.uCpl != 0)
6297 return iemRaiseGeneralProtectionFault0(pVCpu);
6298 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6299 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6300
6301#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6302 /* Check nested-guest VMX intercept and get updated MSW if there's no VM-exit. */
6303 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6304 {
6305 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrLmsw(pVCpu, pVCpu->cpum.GstCtx.cr0, &u16NewMsw, GCPtrEffDst, cbInstr);
6306 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6307 return rcStrict;
6308 }
6309#else
6310 RT_NOREF_PV(GCPtrEffDst);
6311#endif
6312
6313 /*
6314 * Compose the new CR0 value and call common worker.
6315 */
6316 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
6317 uNewCr0 |= u16NewMsw & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
6318 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_LMSW, UINT8_MAX /* iGReg */);
6319}
6320
6321
6322/**
6323 * Implements 'CLTS'.
6324 */
6325IEM_CIMPL_DEF_0(iemCImpl_clts)
6326{
6327 if (pVCpu->iem.s.uCpl != 0)
6328 return iemRaiseGeneralProtectionFault0(pVCpu);
6329
6330 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6331 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0;
6332 uNewCr0 &= ~X86_CR0_TS;
6333
6334#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6335 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6336 {
6337 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrClts(pVCpu, cbInstr);
6338 if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
6339 uNewCr0 |= (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS);
6340 else if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6341 return rcStrict;
6342 }
6343#endif
6344
6345 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_CLTS, UINT8_MAX /* iGReg */);
6346}
6347
6348
6349/**
6350 * Implements mov GReg,DRx.
6351 *
6352 * @param iGReg The general register to store the DRx value in.
6353 * @param iDrReg The DRx register to read (0-7).
6354 */
6355IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg)
6356{
6357#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6358 /*
6359 * Check nested-guest VMX intercept.
6360 * Unlike most other intercepts, the Mov DRx intercept takes preceedence
6361 * over CPL and CR4.DE and even DR4/DR5 checks.
6362 *
6363 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
6364 */
6365 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6366 {
6367 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovDrX(pVCpu, VMXINSTRID_MOV_FROM_DRX, iDrReg, iGReg, cbInstr);
6368 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6369 return rcStrict;
6370 }
6371#endif
6372
6373 /*
6374 * Check preconditions.
6375 */
6376 /* Raise GPs. */
6377 if (pVCpu->iem.s.uCpl != 0)
6378 return iemRaiseGeneralProtectionFault0(pVCpu);
6379 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6380 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR0);
6381
6382 if ( (iDrReg == 4 || iDrReg == 5)
6383 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
6384 {
6385 Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
6386 return iemRaiseGeneralProtectionFault0(pVCpu);
6387 }
6388
6389 /* Raise #DB if general access detect is enabled. */
6390 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
6391 {
6392 Log(("mov r%u,dr%u: DR7.GD=1 -> #DB\n", iGReg, iDrReg));
6393 return iemRaiseDebugException(pVCpu);
6394 }
6395
6396 /*
6397 * Read the debug register and store it in the specified general register.
6398 */
6399 uint64_t drX;
6400 switch (iDrReg)
6401 {
6402 case 0:
6403 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6404 drX = pVCpu->cpum.GstCtx.dr[0];
6405 break;
6406 case 1:
6407 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6408 drX = pVCpu->cpum.GstCtx.dr[1];
6409 break;
6410 case 2:
6411 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6412 drX = pVCpu->cpum.GstCtx.dr[2];
6413 break;
6414 case 3:
6415 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6416 drX = pVCpu->cpum.GstCtx.dr[3];
6417 break;
6418 case 6:
6419 case 4:
6420 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
6421 drX = pVCpu->cpum.GstCtx.dr[6];
6422 drX |= X86_DR6_RA1_MASK;
6423 drX &= ~X86_DR6_RAZ_MASK;
6424 break;
6425 case 7:
6426 case 5:
6427 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
6428 drX = pVCpu->cpum.GstCtx.dr[7];
6429 drX |=X86_DR7_RA1_MASK;
6430 drX &= ~X86_DR7_RAZ_MASK;
6431 break;
6432 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
6433 }
6434
6435 /** @todo SVM nested-guest intercept for DR8-DR15? */
6436 /*
6437 * Check for any SVM nested-guest intercepts for the DRx read.
6438 */
6439 if (IEM_SVM_IS_READ_DR_INTERCEPT_SET(pVCpu, iDrReg))
6440 {
6441 Log(("mov r%u,dr%u: Guest intercept -> #VMEXIT\n", iGReg, iDrReg));
6442 IEM_SVM_UPDATE_NRIP(pVCpu);
6443 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_READ_DR0 + (iDrReg & 0xf),
6444 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
6445 }
6446
6447 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6448 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = drX;
6449 else
6450 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX;
6451
6452 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6453 return VINF_SUCCESS;
6454}
6455
6456
6457/**
6458 * Implements mov DRx,GReg.
6459 *
6460 * @param iDrReg The DRx register to write (valid).
6461 * @param iGReg The general register to load the DRx value from.
6462 */
6463IEM_CIMPL_DEF_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg)
6464{
6465#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6466 /*
6467 * Check nested-guest VMX intercept.
6468 * Unlike most other intercepts, the Mov DRx intercept takes preceedence
6469 * over CPL and CR4.DE and even DR4/DR5 checks.
6470 *
6471 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
6472 */
6473 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6474 {
6475 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovDrX(pVCpu, VMXINSTRID_MOV_TO_DRX, iDrReg, iGReg, cbInstr);
6476 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6477 return rcStrict;
6478 }
6479#endif
6480
6481 /*
6482 * Check preconditions.
6483 */
6484 if (pVCpu->iem.s.uCpl != 0)
6485 return iemRaiseGeneralProtectionFault0(pVCpu);
6486 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6487 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR4);
6488
6489 if (iDrReg == 4 || iDrReg == 5)
6490 {
6491 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)
6492 {
6493 Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
6494 return iemRaiseGeneralProtectionFault0(pVCpu);
6495 }
6496 iDrReg += 2;
6497 }
6498
6499 /* Raise #DB if general access detect is enabled. */
6500 /** @todo is \#DB/DR7.GD raised before any reserved high bits in DR7/DR6
6501 * \#GP? */
6502 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
6503 {
6504 Log(("mov dr%u,r%u: DR7.GD=1 -> #DB\n", iDrReg, iGReg));
6505 return iemRaiseDebugException(pVCpu);
6506 }
6507
6508 /*
6509 * Read the new value from the source register.
6510 */
6511 uint64_t uNewDrX;
6512 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6513 uNewDrX = iemGRegFetchU64(pVCpu, iGReg);
6514 else
6515 uNewDrX = iemGRegFetchU32(pVCpu, iGReg);
6516
6517 /*
6518 * Adjust it.
6519 */
6520 switch (iDrReg)
6521 {
6522 case 0:
6523 case 1:
6524 case 2:
6525 case 3:
6526 /* nothing to adjust */
6527 break;
6528
6529 case 6:
6530 if (uNewDrX & X86_DR6_MBZ_MASK)
6531 {
6532 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
6533 return iemRaiseGeneralProtectionFault0(pVCpu);
6534 }
6535 uNewDrX |= X86_DR6_RA1_MASK;
6536 uNewDrX &= ~X86_DR6_RAZ_MASK;
6537 break;
6538
6539 case 7:
6540 if (uNewDrX & X86_DR7_MBZ_MASK)
6541 {
6542 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
6543 return iemRaiseGeneralProtectionFault0(pVCpu);
6544 }
6545 uNewDrX |= X86_DR7_RA1_MASK;
6546 uNewDrX &= ~X86_DR7_RAZ_MASK;
6547 break;
6548
6549 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6550 }
6551
6552 /** @todo SVM nested-guest intercept for DR8-DR15? */
6553 /*
6554 * Check for any SVM nested-guest intercepts for the DRx write.
6555 */
6556 if (IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(pVCpu, iDrReg))
6557 {
6558 Log2(("mov dr%u,r%u: Guest intercept -> #VMEXIT\n", iDrReg, iGReg));
6559 IEM_SVM_UPDATE_NRIP(pVCpu);
6560 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_DR0 + (iDrReg & 0xf),
6561 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
6562 }
6563
6564 /*
6565 * Do the actual setting.
6566 */
6567 if (iDrReg < 4)
6568 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6569 else if (iDrReg == 6)
6570 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
6571
6572 int rc = CPUMSetGuestDRx(pVCpu, iDrReg, uNewDrX);
6573 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_IEM_IPE_1 : rc);
6574
6575 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6576 return VINF_SUCCESS;
6577}
6578
6579
6580/**
6581 * Implements mov GReg,TRx.
6582 *
6583 * @param iGReg The general register to store the
6584 * TRx value in.
6585 * @param iTrReg The TRx register to read (6/7).
6586 */
6587IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg)
6588{
6589 /*
6590 * Check preconditions. NB: This instruction is 386/486 only.
6591 */
6592
6593 /* Raise GPs. */
6594 if (pVCpu->iem.s.uCpl != 0)
6595 return iemRaiseGeneralProtectionFault0(pVCpu);
6596 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6597
6598 if (iTrReg < 6 || iTrReg > 7)
6599 {
6600 /** @todo Do Intel CPUs reject this or are the TRs aliased? */
6601 Log(("mov r%u,tr%u: invalid register -> #GP(0)\n", iGReg, iTrReg));
6602 return iemRaiseGeneralProtectionFault0(pVCpu);
6603 }
6604
6605 /*
6606 * Read the test register and store it in the specified general register.
6607 * This is currently a dummy implementation that only exists to satisfy
6608 * old debuggers like WDEB386 or OS/2 KDB which unconditionally read the
6609 * TR6/TR7 registers. Software which actually depends on the TR values
6610 * (different on 386/486) is exceedingly rare.
6611 */
6612 uint64_t trX;
6613 switch (iTrReg)
6614 {
6615 case 6:
6616 trX = 0; /* Currently a dummy. */
6617 break;
6618 case 7:
6619 trX = 0; /* Currently a dummy. */
6620 break;
6621 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
6622 }
6623
6624 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)trX;
6625
6626 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6627 return VINF_SUCCESS;
6628}
6629
6630
6631/**
6632 * Implements mov TRx,GReg.
6633 *
6634 * @param iTrReg The TRx register to write (valid).
6635 * @param iGReg The general register to load the TRx
6636 * value from.
6637 */
6638IEM_CIMPL_DEF_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg)
6639{
6640 /*
6641 * Check preconditions. NB: This instruction is 386/486 only.
6642 */
6643
6644 /* Raise GPs. */
6645 if (pVCpu->iem.s.uCpl != 0)
6646 return iemRaiseGeneralProtectionFault0(pVCpu);
6647 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6648
6649 if (iTrReg < 6 || iTrReg > 7)
6650 {
6651 /** @todo Do Intel CPUs reject this or are the TRs aliased? */
6652 Log(("mov r%u,tr%u: invalid register -> #GP(0)\n", iGReg, iTrReg));
6653 return iemRaiseGeneralProtectionFault0(pVCpu);
6654 }
6655
6656 /*
6657 * Read the new value from the source register.
6658 */
6659 uint64_t uNewTrX;
6660 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6661 uNewTrX = iemGRegFetchU64(pVCpu, iGReg);
6662 else
6663 uNewTrX = iemGRegFetchU32(pVCpu, iGReg);
6664
6665 /*
6666 * Here we would do the actual setting if this weren't a dummy implementation.
6667 * This is currently a dummy implementation that only exists to prevent
6668 * old debuggers like WDEB386 or OS/2 KDB from crashing.
6669 */
6670 RT_NOREF(uNewTrX);
6671
6672 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6673 return VINF_SUCCESS;
6674}
6675
6676
6677/**
6678 * Implements 'INVLPG m'.
6679 *
6680 * @param GCPtrPage The effective address of the page to invalidate.
6681 * @remarks Updates the RIP.
6682 */
6683IEM_CIMPL_DEF_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage)
6684{
6685 /* ring-0 only. */
6686 if (pVCpu->iem.s.uCpl != 0)
6687 return iemRaiseGeneralProtectionFault0(pVCpu);
6688 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6689 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6690
6691#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6692 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6693 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6694 {
6695 Log(("invlpg: Guest intercept (%RGp) -> VM-exit\n", GCPtrPage));
6696 return iemVmxVmexitInstrInvlpg(pVCpu, GCPtrPage, cbInstr);
6697 }
6698#endif
6699
6700 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
6701 {
6702 Log(("invlpg: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
6703 IEM_SVM_UPDATE_NRIP(pVCpu);
6704 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_INVLPG,
6705 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? GCPtrPage : 0, 0 /* uExitInfo2 */);
6706 }
6707
6708 int rc = PGMInvalidatePage(pVCpu, GCPtrPage);
6709 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6710
6711 if (rc == VINF_SUCCESS)
6712 return VINF_SUCCESS;
6713 if (rc == VINF_PGM_SYNC_CR3)
6714 return iemSetPassUpStatus(pVCpu, rc);
6715
6716 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
6717 Log(("PGMInvalidatePage(%RGv) -> %Rrc\n", GCPtrPage, rc));
6718 return rc;
6719}
6720
6721
6722/**
6723 * Implements INVPCID.
6724 *
6725 * @param iEffSeg The segment of the invpcid descriptor.
6726 * @param GCPtrInvpcidDesc The address of invpcid descriptor.
6727 * @param uInvpcidType The invalidation type.
6728 * @remarks Updates the RIP.
6729 */
6730IEM_CIMPL_DEF_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType)
6731{
6732 /*
6733 * Check preconditions.
6734 */
6735 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fInvpcid)
6736 return iemRaiseUndefinedOpcode(pVCpu);
6737
6738 /* When in VMX non-root mode and INVPCID is not enabled, it results in #UD. */
6739 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6740 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_INVPCID))
6741 {
6742 Log(("invpcid: Not enabled for nested-guest execution -> #UD\n"));
6743 return iemRaiseUndefinedOpcode(pVCpu);
6744 }
6745
6746 if (pVCpu->iem.s.uCpl != 0)
6747 {
6748 Log(("invpcid: CPL != 0 -> #GP(0)\n"));
6749 return iemRaiseGeneralProtectionFault0(pVCpu);
6750 }
6751
6752 if (IEM_IS_V86_MODE(pVCpu))
6753 {
6754 Log(("invpcid: v8086 mode -> #GP(0)\n"));
6755 return iemRaiseGeneralProtectionFault0(pVCpu);
6756 }
6757
6758 /*
6759 * Check nested-guest intercept.
6760 *
6761 * INVPCID causes a VM-exit if "enable INVPCID" and "INVLPG exiting" are
6762 * both set. We have already checked the former earlier in this function.
6763 *
6764 * CPL and virtual-8086 mode checks take priority over this VM-exit.
6765 * See Intel spec. "25.1.1 Relative Priority of Faults and VM Exits".
6766 */
6767 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6768 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6769 {
6770 Log(("invpcid: Guest intercept -> #VM-exit\n"));
6771 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_INVPCID, VMXINSTRID_NONE, cbInstr);
6772 }
6773
6774 if (uInvpcidType > X86_INVPCID_TYPE_MAX_VALID)
6775 {
6776 Log(("invpcid: invalid/unrecognized invpcid type %#RX64 -> #GP(0)\n", uInvpcidType));
6777 return iemRaiseGeneralProtectionFault0(pVCpu);
6778 }
6779 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6780
6781 /*
6782 * Fetch the invpcid descriptor from guest memory.
6783 */
6784 RTUINT128U uDesc;
6785 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvpcidDesc);
6786 if (rcStrict == VINF_SUCCESS)
6787 {
6788 /*
6789 * Validate the descriptor.
6790 */
6791 if (uDesc.s.Lo > 0xfff)
6792 {
6793 Log(("invpcid: reserved bits set in invpcid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
6794 return iemRaiseGeneralProtectionFault0(pVCpu);
6795 }
6796
6797 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
6798 uint8_t const uPcid = uDesc.s.Lo & UINT64_C(0xfff);
6799 uint32_t const uCr4 = pVCpu->cpum.GstCtx.cr4;
6800 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
6801 switch (uInvpcidType)
6802 {
6803 case X86_INVPCID_TYPE_INDV_ADDR:
6804 {
6805 if (!IEM_IS_CANONICAL(GCPtrInvAddr))
6806 {
6807 Log(("invpcid: invalidation address %#RGP is not canonical -> #GP(0)\n", GCPtrInvAddr));
6808 return iemRaiseGeneralProtectionFault0(pVCpu);
6809 }
6810 if ( !(uCr4 & X86_CR4_PCIDE)
6811 && uPcid != 0)
6812 {
6813 Log(("invpcid: invalid pcid %#x\n", uPcid));
6814 return iemRaiseGeneralProtectionFault0(pVCpu);
6815 }
6816
6817 /* Invalidate mappings for the linear address tagged with PCID except global translations. */
6818 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6819 break;
6820 }
6821
6822 case X86_INVPCID_TYPE_SINGLE_CONTEXT:
6823 {
6824 if ( !(uCr4 & X86_CR4_PCIDE)
6825 && uPcid != 0)
6826 {
6827 Log(("invpcid: invalid pcid %#x\n", uPcid));
6828 return iemRaiseGeneralProtectionFault0(pVCpu);
6829 }
6830 /* Invalidate all mappings associated with PCID except global translations. */
6831 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6832 break;
6833 }
6834
6835 case X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL:
6836 {
6837 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
6838 break;
6839 }
6840
6841 case X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL:
6842 {
6843 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6844 break;
6845 }
6846 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6847 }
6848 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6849 }
6850 return rcStrict;
6851}
6852
6853
6854/**
6855 * Implements INVD.
6856 */
6857IEM_CIMPL_DEF_0(iemCImpl_invd)
6858{
6859 if (pVCpu->iem.s.uCpl != 0)
6860 {
6861 Log(("invd: CPL != 0 -> #GP(0)\n"));
6862 return iemRaiseGeneralProtectionFault0(pVCpu);
6863 }
6864
6865 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6866 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_INVD, cbInstr);
6867
6868 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_INVD, SVM_EXIT_INVD, 0, 0);
6869
6870 /* We currently take no action here. */
6871 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6872 return VINF_SUCCESS;
6873}
6874
6875
6876/**
6877 * Implements WBINVD.
6878 */
6879IEM_CIMPL_DEF_0(iemCImpl_wbinvd)
6880{
6881 if (pVCpu->iem.s.uCpl != 0)
6882 {
6883 Log(("wbinvd: CPL != 0 -> #GP(0)\n"));
6884 return iemRaiseGeneralProtectionFault0(pVCpu);
6885 }
6886
6887 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6888 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WBINVD, cbInstr);
6889
6890 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_WBINVD, SVM_EXIT_WBINVD, 0, 0);
6891
6892 /* We currently take no action here. */
6893 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6894 return VINF_SUCCESS;
6895}
6896
6897
6898/** Opcode 0x0f 0xaa. */
6899IEM_CIMPL_DEF_0(iemCImpl_rsm)
6900{
6901 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RSM, SVM_EXIT_RSM, 0, 0);
6902 NOREF(cbInstr);
6903 return iemRaiseUndefinedOpcode(pVCpu);
6904}
6905
6906
6907/**
6908 * Implements RDTSC.
6909 */
6910IEM_CIMPL_DEF_0(iemCImpl_rdtsc)
6911{
6912 /*
6913 * Check preconditions.
6914 */
6915 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTsc)
6916 return iemRaiseUndefinedOpcode(pVCpu);
6917
6918 if (pVCpu->iem.s.uCpl != 0)
6919 {
6920 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6921 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6922 {
6923 Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6924 return iemRaiseGeneralProtectionFault0(pVCpu);
6925 }
6926 }
6927
6928 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6929 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDTSC_EXIT))
6930 {
6931 Log(("rdtsc: Guest intercept -> VM-exit\n"));
6932 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSC, cbInstr);
6933 }
6934
6935 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
6936 {
6937 Log(("rdtsc: Guest intercept -> #VMEXIT\n"));
6938 IEM_SVM_UPDATE_NRIP(pVCpu);
6939 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6940 }
6941
6942 /*
6943 * Do the job.
6944 */
6945 uint64_t uTicks = TMCpuTickGet(pVCpu);
6946#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
6947 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
6948#endif
6949 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
6950 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
6951 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX); /* For IEMExecDecodedRdtsc. */
6952 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6953 return VINF_SUCCESS;
6954}
6955
6956
6957/**
6958 * Implements RDTSC.
6959 */
6960IEM_CIMPL_DEF_0(iemCImpl_rdtscp)
6961{
6962 /*
6963 * Check preconditions.
6964 */
6965 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdTscP)
6966 return iemRaiseUndefinedOpcode(pVCpu);
6967
6968 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6969 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_RDTSCP))
6970 {
6971 Log(("rdtscp: Not enabled for VMX non-root mode -> #UD\n"));
6972 return iemRaiseUndefinedOpcode(pVCpu);
6973 }
6974
6975 if (pVCpu->iem.s.uCpl != 0)
6976 {
6977 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6978 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6979 {
6980 Log(("rdtscp: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6981 return iemRaiseGeneralProtectionFault0(pVCpu);
6982 }
6983 }
6984
6985 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6986 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDTSC_EXIT))
6987 {
6988 Log(("rdtscp: Guest intercept -> VM-exit\n"));
6989 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSCP, cbInstr);
6990 }
6991 else if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
6992 {
6993 Log(("rdtscp: Guest intercept -> #VMEXIT\n"));
6994 IEM_SVM_UPDATE_NRIP(pVCpu);
6995 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSCP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6996 }
6997
6998 /*
6999 * Do the job.
7000 * Query the MSR first in case of trips to ring-3.
7001 */
7002 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TSC_AUX);
7003 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pVCpu->cpum.GstCtx.rcx);
7004 if (rcStrict == VINF_SUCCESS)
7005 {
7006 /* Low dword of the TSC_AUX msr only. */
7007 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
7008
7009 uint64_t uTicks = TMCpuTickGet(pVCpu);
7010#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
7011 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
7012#endif
7013 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
7014 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
7015 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX); /* For IEMExecDecodedRdtscp. */
7016 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7017 }
7018 return rcStrict;
7019}
7020
7021
7022/**
7023 * Implements RDPMC.
7024 */
7025IEM_CIMPL_DEF_0(iemCImpl_rdpmc)
7026{
7027 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
7028
7029 if ( pVCpu->iem.s.uCpl != 0
7030 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCE))
7031 return iemRaiseGeneralProtectionFault0(pVCpu);
7032
7033 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7034 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDPMC_EXIT))
7035 {
7036 Log(("rdpmc: Guest intercept -> VM-exit\n"));
7037 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDPMC, cbInstr);
7038 }
7039
7040 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
7041 {
7042 Log(("rdpmc: Guest intercept -> #VMEXIT\n"));
7043 IEM_SVM_UPDATE_NRIP(pVCpu);
7044 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDPMC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7045 }
7046
7047 /** @todo Emulate performance counters, for now just return 0. */
7048 pVCpu->cpum.GstCtx.rax = 0;
7049 pVCpu->cpum.GstCtx.rdx = 0;
7050 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
7051 /** @todo We should trigger a \#GP here if the CPU doesn't support the index in
7052 * ecx but see @bugref{3472}! */
7053
7054 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7055 return VINF_SUCCESS;
7056}
7057
7058
7059/**
7060 * Implements RDMSR.
7061 */
7062IEM_CIMPL_DEF_0(iemCImpl_rdmsr)
7063{
7064 /*
7065 * Check preconditions.
7066 */
7067 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
7068 return iemRaiseUndefinedOpcode(pVCpu);
7069 if (pVCpu->iem.s.uCpl != 0)
7070 return iemRaiseGeneralProtectionFault0(pVCpu);
7071
7072 /*
7073 * Check nested-guest intercepts.
7074 */
7075#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7076 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7077 {
7078 if (iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_RDMSR, pVCpu->cpum.GstCtx.ecx))
7079 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDMSR, cbInstr);
7080 }
7081#endif
7082
7083#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7084 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
7085 {
7086 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, false /* fWrite */);
7087 if (rcStrict == VINF_SVM_VMEXIT)
7088 return VINF_SUCCESS;
7089 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7090 {
7091 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.ecx, VBOXSTRICTRC_VAL(rcStrict)));
7092 return rcStrict;
7093 }
7094 }
7095#endif
7096
7097 /*
7098 * Do the job.
7099 */
7100 RTUINT64U uValue;
7101 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
7102 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
7103
7104 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pVCpu->cpum.GstCtx.ecx, &uValue.u);
7105 if (rcStrict == VINF_SUCCESS)
7106 {
7107 pVCpu->cpum.GstCtx.rax = uValue.s.Lo;
7108 pVCpu->cpum.GstCtx.rdx = uValue.s.Hi;
7109 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
7110
7111 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7112 return VINF_SUCCESS;
7113 }
7114
7115#ifndef IN_RING3
7116 /* Deferred to ring-3. */
7117 if (rcStrict == VINF_CPUM_R3_MSR_READ)
7118 {
7119 Log(("IEM: rdmsr(%#x) -> ring-3\n", pVCpu->cpum.GstCtx.ecx));
7120 return rcStrict;
7121 }
7122#endif
7123
7124 /* Often a unimplemented MSR or MSR bit, so worth logging. */
7125 if (pVCpu->iem.s.cLogRelRdMsr < 32)
7126 {
7127 pVCpu->iem.s.cLogRelRdMsr++;
7128 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
7129 }
7130 else
7131 Log(( "IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
7132 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
7133 return iemRaiseGeneralProtectionFault0(pVCpu);
7134}
7135
7136
7137/**
7138 * Implements WRMSR.
7139 */
7140IEM_CIMPL_DEF_0(iemCImpl_wrmsr)
7141{
7142 /*
7143 * Check preconditions.
7144 */
7145 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
7146 return iemRaiseUndefinedOpcode(pVCpu);
7147 if (pVCpu->iem.s.uCpl != 0)
7148 return iemRaiseGeneralProtectionFault0(pVCpu);
7149
7150 RTUINT64U uValue;
7151 uValue.s.Lo = pVCpu->cpum.GstCtx.eax;
7152 uValue.s.Hi = pVCpu->cpum.GstCtx.edx;
7153
7154 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
7155
7156 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
7157 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
7158
7159 /*
7160 * Check nested-guest intercepts.
7161 */
7162#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7163 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7164 {
7165 if (iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_WRMSR, idMsr))
7166 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WRMSR, cbInstr);
7167 }
7168#endif
7169
7170#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7171 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
7172 {
7173 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, idMsr, true /* fWrite */);
7174 if (rcStrict == VINF_SVM_VMEXIT)
7175 return VINF_SUCCESS;
7176 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7177 {
7178 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", idMsr, VBOXSTRICTRC_VAL(rcStrict)));
7179 return rcStrict;
7180 }
7181 }
7182#endif
7183
7184 /*
7185 * Do the job.
7186 */
7187 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, idMsr, uValue.u);
7188 if (rcStrict == VINF_SUCCESS)
7189 {
7190 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7191 return VINF_SUCCESS;
7192 }
7193
7194#ifndef IN_RING3
7195 /* Deferred to ring-3. */
7196 if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
7197 {
7198 Log(("IEM: wrmsr(%#x) -> ring-3\n", idMsr));
7199 return rcStrict;
7200 }
7201#endif
7202
7203 /* Often a unimplemented MSR or MSR bit, so worth logging. */
7204 if (pVCpu->iem.s.cLogRelWrMsr < 32)
7205 {
7206 pVCpu->iem.s.cLogRelWrMsr++;
7207 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", idMsr, uValue.s.Hi, uValue.s.Lo));
7208 }
7209 else
7210 Log(( "IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", idMsr, uValue.s.Hi, uValue.s.Lo));
7211 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
7212 return iemRaiseGeneralProtectionFault0(pVCpu);
7213}
7214
7215
7216/**
7217 * Implements 'IN eAX, port'.
7218 *
7219 * @param u16Port The source port.
7220 * @param fImm Whether the port was specified through an immediate operand
7221 * or the implicit DX register.
7222 * @param cbReg The register size.
7223 */
7224IEM_CIMPL_DEF_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg)
7225{
7226 /*
7227 * CPL check
7228 */
7229 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
7230 if (rcStrict != VINF_SUCCESS)
7231 return rcStrict;
7232
7233 /*
7234 * Check VMX nested-guest IO intercept.
7235 */
7236#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7237 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7238 {
7239 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_IN, u16Port, fImm, cbReg, cbInstr);
7240 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7241 return rcStrict;
7242 }
7243#else
7244 RT_NOREF(fImm);
7245#endif
7246
7247 /*
7248 * Check SVM nested-guest IO intercept.
7249 */
7250#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7251 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
7252 {
7253 uint8_t cAddrSizeBits;
7254 switch (pVCpu->iem.s.enmEffAddrMode)
7255 {
7256 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
7257 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
7258 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
7259 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7260 }
7261 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_IN, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
7262 false /* fRep */, false /* fStrIo */, cbInstr);
7263 if (rcStrict == VINF_SVM_VMEXIT)
7264 return VINF_SUCCESS;
7265 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7266 {
7267 Log(("iemCImpl_in: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
7268 VBOXSTRICTRC_VAL(rcStrict)));
7269 return rcStrict;
7270 }
7271 }
7272#endif
7273
7274 /*
7275 * Perform the I/O.
7276 */
7277 uint32_t u32Value = 0;
7278 rcStrict = IOMIOPortRead(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, &u32Value, cbReg);
7279 if (IOM_SUCCESS(rcStrict))
7280 {
7281 switch (cbReg)
7282 {
7283 case 1: pVCpu->cpum.GstCtx.al = (uint8_t)u32Value; break;
7284 case 2: pVCpu->cpum.GstCtx.ax = (uint16_t)u32Value; break;
7285 case 4: pVCpu->cpum.GstCtx.rax = u32Value; break;
7286 default: AssertFailedReturn(VERR_IEM_IPE_3);
7287 }
7288 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7289 pVCpu->iem.s.cPotentialExits++;
7290 if (rcStrict != VINF_SUCCESS)
7291 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7292 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
7293
7294 /*
7295 * Check for I/O breakpoints.
7296 */
7297 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
7298 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7299 && X86_DR7_ANY_RW_IO(uDr7)
7300 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
7301 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
7302 {
7303 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
7304 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
7305 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
7306 rcStrict = iemRaiseDebugException(pVCpu);
7307 }
7308 }
7309
7310 return rcStrict;
7311}
7312
7313
7314/**
7315 * Implements 'IN eAX, DX'.
7316 *
7317 * @param cbReg The register size.
7318 */
7319IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg)
7320{
7321 return IEM_CIMPL_CALL_3(iemCImpl_in, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg);
7322}
7323
7324
7325/**
7326 * Implements 'OUT port, eAX'.
7327 *
7328 * @param u16Port The destination port.
7329 * @param fImm Whether the port was specified through an immediate operand
7330 * or the implicit DX register.
7331 * @param cbReg The register size.
7332 */
7333IEM_CIMPL_DEF_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg)
7334{
7335 /*
7336 * CPL check
7337 */
7338 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
7339 if (rcStrict != VINF_SUCCESS)
7340 return rcStrict;
7341
7342 /*
7343 * Check VMX nested-guest I/O intercept.
7344 */
7345#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7346 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7347 {
7348 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_OUT, u16Port, fImm, cbReg, cbInstr);
7349 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7350 return rcStrict;
7351 }
7352#else
7353 RT_NOREF(fImm);
7354#endif
7355
7356 /*
7357 * Check SVM nested-guest I/O intercept.
7358 */
7359#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7360 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
7361 {
7362 uint8_t cAddrSizeBits;
7363 switch (pVCpu->iem.s.enmEffAddrMode)
7364 {
7365 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
7366 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
7367 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
7368 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7369 }
7370 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_OUT, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
7371 false /* fRep */, false /* fStrIo */, cbInstr);
7372 if (rcStrict == VINF_SVM_VMEXIT)
7373 return VINF_SUCCESS;
7374 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7375 {
7376 Log(("iemCImpl_out: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
7377 VBOXSTRICTRC_VAL(rcStrict)));
7378 return rcStrict;
7379 }
7380 }
7381#endif
7382
7383 /*
7384 * Perform the I/O.
7385 */
7386 uint32_t u32Value;
7387 switch (cbReg)
7388 {
7389 case 1: u32Value = pVCpu->cpum.GstCtx.al; break;
7390 case 2: u32Value = pVCpu->cpum.GstCtx.ax; break;
7391 case 4: u32Value = pVCpu->cpum.GstCtx.eax; break;
7392 default: AssertFailedReturn(VERR_IEM_IPE_4);
7393 }
7394 rcStrict = IOMIOPortWrite(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, u32Value, cbReg);
7395 if (IOM_SUCCESS(rcStrict))
7396 {
7397 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7398 pVCpu->iem.s.cPotentialExits++;
7399 if (rcStrict != VINF_SUCCESS)
7400 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7401 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
7402
7403 /*
7404 * Check for I/O breakpoints.
7405 */
7406 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
7407 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7408 && X86_DR7_ANY_RW_IO(uDr7)
7409 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
7410 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
7411 {
7412 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
7413 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
7414 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
7415 rcStrict = iemRaiseDebugException(pVCpu);
7416 }
7417 }
7418 return rcStrict;
7419}
7420
7421
7422/**
7423 * Implements 'OUT DX, eAX'.
7424 *
7425 * @param cbReg The register size.
7426 */
7427IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg)
7428{
7429 return IEM_CIMPL_CALL_3(iemCImpl_out, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg);
7430}
7431
7432
7433/**
7434 * Implements 'CLI'.
7435 */
7436IEM_CIMPL_DEF_0(iemCImpl_cli)
7437{
7438 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
7439 uint32_t const fEflOld = fEfl;
7440
7441 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
7442 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
7443 {
7444 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
7445 if (!(fEfl & X86_EFL_VM))
7446 {
7447 if (pVCpu->iem.s.uCpl <= uIopl)
7448 fEfl &= ~X86_EFL_IF;
7449 else if ( pVCpu->iem.s.uCpl == 3
7450 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI) )
7451 fEfl &= ~X86_EFL_VIF;
7452 else
7453 return iemRaiseGeneralProtectionFault0(pVCpu);
7454 }
7455 /* V8086 */
7456 else if (uIopl == 3)
7457 fEfl &= ~X86_EFL_IF;
7458 else if ( uIopl < 3
7459 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
7460 fEfl &= ~X86_EFL_VIF;
7461 else
7462 return iemRaiseGeneralProtectionFault0(pVCpu);
7463 }
7464 /* real mode */
7465 else
7466 fEfl &= ~X86_EFL_IF;
7467
7468 /* Commit. */
7469 IEMMISC_SET_EFL(pVCpu, fEfl);
7470 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7471 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); NOREF(fEflOld);
7472 return VINF_SUCCESS;
7473}
7474
7475
7476/**
7477 * Implements 'STI'.
7478 */
7479IEM_CIMPL_DEF_0(iemCImpl_sti)
7480{
7481 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
7482 uint32_t const fEflOld = fEfl;
7483
7484 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
7485 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
7486 {
7487 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
7488 if (!(fEfl & X86_EFL_VM))
7489 {
7490 if (pVCpu->iem.s.uCpl <= uIopl)
7491 fEfl |= X86_EFL_IF;
7492 else if ( pVCpu->iem.s.uCpl == 3
7493 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI)
7494 && !(fEfl & X86_EFL_VIP) )
7495 fEfl |= X86_EFL_VIF;
7496 else
7497 return iemRaiseGeneralProtectionFault0(pVCpu);
7498 }
7499 /* V8086 */
7500 else if (uIopl == 3)
7501 fEfl |= X86_EFL_IF;
7502 else if ( uIopl < 3
7503 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME)
7504 && !(fEfl & X86_EFL_VIP) )
7505 fEfl |= X86_EFL_VIF;
7506 else
7507 return iemRaiseGeneralProtectionFault0(pVCpu);
7508 }
7509 /* real mode */
7510 else
7511 fEfl |= X86_EFL_IF;
7512
7513 /* Commit. */
7514 IEMMISC_SET_EFL(pVCpu, fEfl);
7515 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7516 if (!(fEflOld & X86_EFL_IF) && (fEfl & X86_EFL_IF))
7517 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
7518 Log2(("STI: %#x -> %#x\n", fEflOld, fEfl));
7519 return VINF_SUCCESS;
7520}
7521
7522
7523/**
7524 * Implements 'HLT'.
7525 */
7526IEM_CIMPL_DEF_0(iemCImpl_hlt)
7527{
7528 if (pVCpu->iem.s.uCpl != 0)
7529 return iemRaiseGeneralProtectionFault0(pVCpu);
7530
7531 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7532 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_HLT_EXIT))
7533 {
7534 Log2(("hlt: Guest intercept -> VM-exit\n"));
7535 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_HLT, cbInstr);
7536 }
7537
7538 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_HLT))
7539 {
7540 Log2(("hlt: Guest intercept -> #VMEXIT\n"));
7541 IEM_SVM_UPDATE_NRIP(pVCpu);
7542 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_HLT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7543 }
7544
7545 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7546 return VINF_EM_HALT;
7547}
7548
7549
7550/**
7551 * Implements 'MONITOR'.
7552 */
7553IEM_CIMPL_DEF_1(iemCImpl_monitor, uint8_t, iEffSeg)
7554{
7555 /*
7556 * Permission checks.
7557 */
7558 if (pVCpu->iem.s.uCpl != 0)
7559 {
7560 Log2(("monitor: CPL != 0\n"));
7561 return iemRaiseUndefinedOpcode(pVCpu); /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. */
7562 }
7563 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
7564 {
7565 Log2(("monitor: Not in CPUID\n"));
7566 return iemRaiseUndefinedOpcode(pVCpu);
7567 }
7568
7569 /*
7570 * Check VMX guest-intercept.
7571 * This should be considered a fault-like VM-exit.
7572 * See Intel spec. 25.1.1 "Relative Priority of Faults and VM Exits".
7573 */
7574 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7575 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_MONITOR_EXIT))
7576 {
7577 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
7578 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_MONITOR, cbInstr);
7579 }
7580
7581 /*
7582 * Gather the operands and validate them.
7583 */
7584 RTGCPTR GCPtrMem = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
7585 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7586 uint32_t uEdx = pVCpu->cpum.GstCtx.edx;
7587/** @todo Test whether EAX or ECX is processed first, i.e. do we get \#PF or
7588 * \#GP first. */
7589 if (uEcx != 0)
7590 {
7591 Log2(("monitor rax=%RX64, ecx=%RX32, edx=%RX32; ECX != 0 -> #GP(0)\n", GCPtrMem, uEcx, uEdx)); NOREF(uEdx);
7592 return iemRaiseGeneralProtectionFault0(pVCpu);
7593 }
7594
7595 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrMem);
7596 if (rcStrict != VINF_SUCCESS)
7597 return rcStrict;
7598
7599 RTGCPHYS GCPhysMem;
7600 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
7601 if (rcStrict != VINF_SUCCESS)
7602 return rcStrict;
7603
7604#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7605 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7606 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
7607 {
7608 /*
7609 * MONITOR does not access the memory, just monitors the address. However,
7610 * if the address falls in the APIC-access page, the address monitored must
7611 * instead be the corresponding address in the virtual-APIC page.
7612 *
7613 * See Intel spec. 29.4.4 "Instruction-Specific Considerations".
7614 */
7615 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, 1, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA);
7616 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE
7617 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR)
7618 return rcStrict;
7619 }
7620#endif
7621
7622 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
7623 {
7624 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
7625 IEM_SVM_UPDATE_NRIP(pVCpu);
7626 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MONITOR, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7627 }
7628
7629 /*
7630 * Call EM to prepare the monitor/wait.
7631 */
7632 rcStrict = EMMonitorWaitPrepare(pVCpu, pVCpu->cpum.GstCtx.rax, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.rdx, GCPhysMem);
7633 Assert(rcStrict == VINF_SUCCESS);
7634
7635 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7636 return rcStrict;
7637}
7638
7639
7640/**
7641 * Implements 'MWAIT'.
7642 */
7643IEM_CIMPL_DEF_0(iemCImpl_mwait)
7644{
7645 /*
7646 * Permission checks.
7647 */
7648 if (pVCpu->iem.s.uCpl != 0)
7649 {
7650 Log2(("mwait: CPL != 0\n"));
7651 /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. (Remember to check
7652 * EFLAGS.VM then.) */
7653 return iemRaiseUndefinedOpcode(pVCpu);
7654 }
7655 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
7656 {
7657 Log2(("mwait: Not in CPUID\n"));
7658 return iemRaiseUndefinedOpcode(pVCpu);
7659 }
7660
7661 /* Check VMX nested-guest intercept. */
7662 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7663 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_MWAIT_EXIT))
7664 IEM_VMX_VMEXIT_MWAIT_RET(pVCpu, EMMonitorIsArmed(pVCpu), cbInstr);
7665
7666 /*
7667 * Gather the operands and validate them.
7668 */
7669 uint32_t const uEax = pVCpu->cpum.GstCtx.eax;
7670 uint32_t const uEcx = pVCpu->cpum.GstCtx.ecx;
7671 if (uEcx != 0)
7672 {
7673 /* Only supported extension is break on IRQ when IF=0. */
7674 if (uEcx > 1)
7675 {
7676 Log2(("mwait eax=%RX32, ecx=%RX32; ECX > 1 -> #GP(0)\n", uEax, uEcx));
7677 return iemRaiseGeneralProtectionFault0(pVCpu);
7678 }
7679 uint32_t fMWaitFeatures = 0;
7680 uint32_t uIgnore = 0;
7681 CPUMGetGuestCpuId(pVCpu, 5, 0, -1 /*f64BitMode*/, &uIgnore, &uIgnore, &fMWaitFeatures, &uIgnore);
7682 if ( (fMWaitFeatures & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
7683 != (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
7684 {
7685 Log2(("mwait eax=%RX32, ecx=%RX32; break-on-IRQ-IF=0 extension not enabled -> #GP(0)\n", uEax, uEcx));
7686 return iemRaiseGeneralProtectionFault0(pVCpu);
7687 }
7688
7689#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7690 /*
7691 * If the interrupt-window exiting control is set or a virtual-interrupt is pending
7692 * for delivery; and interrupts are disabled the processor does not enter its
7693 * mwait state but rather passes control to the next instruction.
7694 *
7695 * See Intel spec. 25.3 "Changes to Instruction Behavior In VMX Non-root Operation".
7696 */
7697 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7698 && !pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
7699 {
7700 if ( IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INT_WINDOW_EXIT)
7701 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
7702 {
7703 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7704 return VINF_SUCCESS;
7705 }
7706 }
7707#endif
7708 }
7709
7710 /*
7711 * Check SVM nested-guest mwait intercepts.
7712 */
7713 if ( IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT_ARMED)
7714 && EMMonitorIsArmed(pVCpu))
7715 {
7716 Log2(("mwait: Guest intercept (monitor hardware armed) -> #VMEXIT\n"));
7717 IEM_SVM_UPDATE_NRIP(pVCpu);
7718 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT_ARMED, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7719 }
7720 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
7721 {
7722 Log2(("mwait: Guest intercept -> #VMEXIT\n"));
7723 IEM_SVM_UPDATE_NRIP(pVCpu);
7724 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7725 }
7726
7727 /*
7728 * Call EM to prepare the monitor/wait.
7729 */
7730 VBOXSTRICTRC rcStrict = EMMonitorWaitPerform(pVCpu, uEax, uEcx);
7731
7732 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7733 return rcStrict;
7734}
7735
7736
7737/**
7738 * Implements 'SWAPGS'.
7739 */
7740IEM_CIMPL_DEF_0(iemCImpl_swapgs)
7741{
7742 Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT); /* Caller checks this. */
7743
7744 /*
7745 * Permission checks.
7746 */
7747 if (pVCpu->iem.s.uCpl != 0)
7748 {
7749 Log2(("swapgs: CPL != 0\n"));
7750 return iemRaiseUndefinedOpcode(pVCpu);
7751 }
7752
7753 /*
7754 * Do the job.
7755 */
7756 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_GS);
7757 uint64_t uOtherGsBase = pVCpu->cpum.GstCtx.msrKERNELGSBASE;
7758 pVCpu->cpum.GstCtx.msrKERNELGSBASE = pVCpu->cpum.GstCtx.gs.u64Base;
7759 pVCpu->cpum.GstCtx.gs.u64Base = uOtherGsBase;
7760
7761 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7762 return VINF_SUCCESS;
7763}
7764
7765
7766#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
7767/**
7768 * Handles a CPUID call.
7769 */
7770static VBOXSTRICTRC iemCpuIdVBoxCall(PVMCPUCC pVCpu, uint32_t iFunction,
7771 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
7772{
7773 switch (iFunction)
7774 {
7775 case VBOX_CPUID_FN_ID:
7776 LogFlow(("iemCpuIdVBoxCall: VBOX_CPUID_FN_ID\n"));
7777 *pEax = VBOX_CPUID_RESP_ID_EAX;
7778 *pEbx = VBOX_CPUID_RESP_ID_EBX;
7779 *pEcx = VBOX_CPUID_RESP_ID_ECX;
7780 *pEdx = VBOX_CPUID_RESP_ID_EDX;
7781 break;
7782
7783 case VBOX_CPUID_FN_LOG:
7784 {
7785 CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX | CPUMCTX_EXTRN_RSI
7786 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
7787
7788 /* Validate input. */
7789 uint32_t cchToLog = *pEdx;
7790 if (cchToLog <= _2M)
7791 {
7792 uint32_t const uLogPicker = *pEbx;
7793 if (uLogPicker <= 1)
7794 {
7795 /* Resolve the logger. */
7796 PRTLOGGER const pLogger = !uLogPicker
7797 ? RTLogDefaultInstanceEx(UINT32_MAX) : RTLogRelGetDefaultInstanceEx(UINT32_MAX);
7798 if (pLogger)
7799 {
7800 /* Copy over the data: */
7801 RTGCPTR GCPtrSrc = pVCpu->cpum.GstCtx.rsi;
7802 while (cchToLog > 0)
7803 {
7804 uint32_t cbToMap = GUEST_PAGE_SIZE - (GCPtrSrc & GUEST_PAGE_OFFSET_MASK);
7805 if (cbToMap > cchToLog)
7806 cbToMap = cchToLog;
7807 /** @todo Extend iemMemMap to allowing page size accessing and avoid 7
7808 * unnecessary calls & iterations per pages. */
7809 if (cbToMap > 512)
7810 cbToMap = 512;
7811 void *pvSrc = NULL;
7812 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvSrc, cbToMap, UINT8_MAX, GCPtrSrc, IEM_ACCESS_DATA_R, 0);
7813 if (rcStrict == VINF_SUCCESS)
7814 {
7815 RTLogBulkNestedWrite(pLogger, (const char *)pvSrc, cbToMap, "Gst:");
7816 rcStrict = iemMemCommitAndUnmap(pVCpu, pvSrc, IEM_ACCESS_DATA_R);
7817 AssertRCSuccessReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7818 }
7819 else
7820 {
7821 Log(("iemCpuIdVBoxCall: %Rrc at %RGp LB %#x\n", VBOXSTRICTRC_VAL(rcStrict), GCPtrSrc, cbToMap));
7822 return rcStrict;
7823 }
7824
7825 /* Advance. */
7826 pVCpu->cpum.GstCtx.rsi = GCPtrSrc += cbToMap;
7827 *pEdx = cchToLog -= cbToMap;
7828 }
7829 *pEax = VINF_SUCCESS;
7830 }
7831 else
7832 *pEax = (uint32_t)VERR_NOT_FOUND;
7833 }
7834 else
7835 *pEax = (uint32_t)VERR_NOT_FOUND;
7836 }
7837 else
7838 *pEax = (uint32_t)VERR_TOO_MUCH_DATA;
7839 *pEdx = VBOX_CPUID_RESP_GEN_EDX;
7840 *pEcx = VBOX_CPUID_RESP_GEN_ECX;
7841 *pEbx = VBOX_CPUID_RESP_GEN_EBX;
7842 break;
7843 }
7844
7845 default:
7846 LogFlow(("iemCpuIdVBoxCall: Invalid function %#x (%#x, %#x)\n", iFunction, *pEbx, *pEdx));
7847 *pEax = (uint32_t)VERR_INVALID_FUNCTION;
7848 *pEbx = (uint32_t)VERR_INVALID_FUNCTION;
7849 *pEcx = (uint32_t)VERR_INVALID_FUNCTION;
7850 *pEdx = (uint32_t)VERR_INVALID_FUNCTION;
7851 break;
7852 }
7853 return VINF_SUCCESS;
7854}
7855#endif /* VBOX_WITHOUT_CPUID_HOST_CALL */
7856
7857/**
7858 * Implements 'CPUID'.
7859 */
7860IEM_CIMPL_DEF_0(iemCImpl_cpuid)
7861{
7862 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7863 {
7864 Log2(("cpuid: Guest intercept -> VM-exit\n"));
7865 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_CPUID, cbInstr);
7866 }
7867
7868 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
7869 {
7870 Log2(("cpuid: Guest intercept -> #VMEXIT\n"));
7871 IEM_SVM_UPDATE_NRIP(pVCpu);
7872 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_CPUID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7873 }
7874
7875
7876 uint32_t const uEax = pVCpu->cpum.GstCtx.eax;
7877 uint32_t const uEcx = pVCpu->cpum.GstCtx.ecx;
7878
7879#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
7880 /*
7881 * CPUID host call backdoor.
7882 */
7883 if ( uEax == VBOX_CPUID_REQ_EAX_FIXED
7884 && (uEcx & VBOX_CPUID_REQ_ECX_FIXED_MASK) == VBOX_CPUID_REQ_ECX_FIXED
7885 && pVCpu->CTX_SUFF(pVM)->iem.s.fCpuIdHostCall)
7886 {
7887 VBOXSTRICTRC rcStrict = iemCpuIdVBoxCall(pVCpu, uEcx & VBOX_CPUID_REQ_ECX_FN_MASK,
7888 &pVCpu->cpum.GstCtx.eax, &pVCpu->cpum.GstCtx.ebx,
7889 &pVCpu->cpum.GstCtx.ecx, &pVCpu->cpum.GstCtx.edx);
7890 if (rcStrict != VINF_SUCCESS)
7891 return rcStrict;
7892 }
7893 /*
7894 * Regular CPUID.
7895 */
7896 else
7897#endif
7898 CPUMGetGuestCpuId(pVCpu, uEax, uEcx, pVCpu->cpum.GstCtx.cs.Attr.n.u1Long,
7899 &pVCpu->cpum.GstCtx.eax, &pVCpu->cpum.GstCtx.ebx, &pVCpu->cpum.GstCtx.ecx, &pVCpu->cpum.GstCtx.edx);
7900
7901 pVCpu->cpum.GstCtx.rax &= UINT32_C(0xffffffff);
7902 pVCpu->cpum.GstCtx.rbx &= UINT32_C(0xffffffff);
7903 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
7904 pVCpu->cpum.GstCtx.rdx &= UINT32_C(0xffffffff);
7905 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX);
7906
7907 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7908 pVCpu->iem.s.cPotentialExits++;
7909 return VINF_SUCCESS;
7910}
7911
7912
7913/**
7914 * Implements 'AAD'.
7915 *
7916 * @param bImm The immediate operand.
7917 */
7918IEM_CIMPL_DEF_1(iemCImpl_aad, uint8_t, bImm)
7919{
7920 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
7921 uint8_t const al = (uint8_t)ax + (uint8_t)(ax >> 8) * bImm;
7922 pVCpu->cpum.GstCtx.ax = al;
7923 iemHlpUpdateArithEFlagsU8(pVCpu, al,
7924 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
7925 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
7926
7927 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7928 return VINF_SUCCESS;
7929}
7930
7931
7932/**
7933 * Implements 'AAM'.
7934 *
7935 * @param bImm The immediate operand. Cannot be 0.
7936 */
7937IEM_CIMPL_DEF_1(iemCImpl_aam, uint8_t, bImm)
7938{
7939 Assert(bImm != 0); /* #DE on 0 is handled in the decoder. */
7940
7941 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
7942 uint8_t const al = (uint8_t)ax % bImm;
7943 uint8_t const ah = (uint8_t)ax / bImm;
7944 pVCpu->cpum.GstCtx.ax = (ah << 8) + al;
7945 iemHlpUpdateArithEFlagsU8(pVCpu, al,
7946 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
7947 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
7948
7949 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7950 return VINF_SUCCESS;
7951}
7952
7953
7954/**
7955 * Implements 'DAA'.
7956 */
7957IEM_CIMPL_DEF_0(iemCImpl_daa)
7958{
7959 uint8_t const al = pVCpu->cpum.GstCtx.al;
7960 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7961
7962 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7963 || (al & 0xf) >= 10)
7964 {
7965 pVCpu->cpum.GstCtx.al = al + 6;
7966 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7967 }
7968 else
7969 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7970
7971 if (al >= 0x9a || fCarry)
7972 {
7973 pVCpu->cpum.GstCtx.al += 0x60;
7974 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7975 }
7976 else
7977 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7978
7979 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7980 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7981 return VINF_SUCCESS;
7982}
7983
7984
7985/**
7986 * Implements 'DAS'.
7987 */
7988IEM_CIMPL_DEF_0(iemCImpl_das)
7989{
7990 uint8_t const uInputAL = pVCpu->cpum.GstCtx.al;
7991 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7992
7993 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7994 || (uInputAL & 0xf) >= 10)
7995 {
7996 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7997 if (uInputAL < 6)
7998 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7999 pVCpu->cpum.GstCtx.al = uInputAL - 6;
8000 }
8001 else
8002 {
8003 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8004 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8005 }
8006
8007 if (uInputAL >= 0x9a || fCarry)
8008 {
8009 pVCpu->cpum.GstCtx.al -= 0x60;
8010 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8011 }
8012
8013 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8014 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8015 return VINF_SUCCESS;
8016}
8017
8018
8019/**
8020 * Implements 'AAA'.
8021 */
8022IEM_CIMPL_DEF_0(iemCImpl_aaa)
8023{
8024 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
8025 {
8026 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8027 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8028 {
8029 iemAImpl_add_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u32);
8030 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8031 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8032 }
8033 else
8034 {
8035 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8036 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8037 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8038 }
8039 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8040 }
8041 else
8042 {
8043 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8044 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8045 {
8046 pVCpu->cpum.GstCtx.ax += UINT16_C(0x106);
8047 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8048 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8049 }
8050 else
8051 {
8052 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8053 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8054 }
8055 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8056 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8057 }
8058
8059 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8060 return VINF_SUCCESS;
8061}
8062
8063
8064/**
8065 * Implements 'AAS'.
8066 */
8067IEM_CIMPL_DEF_0(iemCImpl_aas)
8068{
8069 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
8070 {
8071 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8072 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8073 {
8074 iemAImpl_sub_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u32);
8075 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8076 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8077 }
8078 else
8079 {
8080 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8081 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8082 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8083 }
8084 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8085 }
8086 else
8087 {
8088 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8089 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8090 {
8091 pVCpu->cpum.GstCtx.ax -= UINT16_C(0x106);
8092 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8093 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8094 }
8095 else
8096 {
8097 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8098 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8099 }
8100 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8101 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8102 }
8103
8104 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8105 return VINF_SUCCESS;
8106}
8107
8108
8109/**
8110 * Implements the 16-bit version of 'BOUND'.
8111 *
8112 * @note We have separate 16-bit and 32-bit variants of this function due to
8113 * the decoder using unsigned parameters, whereas we want signed one to
8114 * do the job. This is significant for a recompiler.
8115 */
8116IEM_CIMPL_DEF_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound)
8117{
8118 /*
8119 * Check if the index is inside the bounds, otherwise raise #BR.
8120 */
8121 if ( idxArray >= idxLowerBound
8122 && idxArray <= idxUpperBound)
8123 {
8124 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8125 return VINF_SUCCESS;
8126 }
8127
8128 return iemRaiseBoundRangeExceeded(pVCpu);
8129}
8130
8131
8132/**
8133 * Implements the 32-bit version of 'BOUND'.
8134 */
8135IEM_CIMPL_DEF_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound)
8136{
8137 /*
8138 * Check if the index is inside the bounds, otherwise raise #BR.
8139 */
8140 if ( idxArray >= idxLowerBound
8141 && idxArray <= idxUpperBound)
8142 {
8143 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8144 return VINF_SUCCESS;
8145 }
8146
8147 return iemRaiseBoundRangeExceeded(pVCpu);
8148}
8149
8150
8151
8152/*
8153 * Instantiate the various string operation combinations.
8154 */
8155#define OP_SIZE 8
8156#define ADDR_SIZE 16
8157#include "IEMAllCImplStrInstr.cpp.h"
8158#define OP_SIZE 8
8159#define ADDR_SIZE 32
8160#include "IEMAllCImplStrInstr.cpp.h"
8161#define OP_SIZE 8
8162#define ADDR_SIZE 64
8163#include "IEMAllCImplStrInstr.cpp.h"
8164
8165#define OP_SIZE 16
8166#define ADDR_SIZE 16
8167#include "IEMAllCImplStrInstr.cpp.h"
8168#define OP_SIZE 16
8169#define ADDR_SIZE 32
8170#include "IEMAllCImplStrInstr.cpp.h"
8171#define OP_SIZE 16
8172#define ADDR_SIZE 64
8173#include "IEMAllCImplStrInstr.cpp.h"
8174
8175#define OP_SIZE 32
8176#define ADDR_SIZE 16
8177#include "IEMAllCImplStrInstr.cpp.h"
8178#define OP_SIZE 32
8179#define ADDR_SIZE 32
8180#include "IEMAllCImplStrInstr.cpp.h"
8181#define OP_SIZE 32
8182#define ADDR_SIZE 64
8183#include "IEMAllCImplStrInstr.cpp.h"
8184
8185#define OP_SIZE 64
8186#define ADDR_SIZE 32
8187#include "IEMAllCImplStrInstr.cpp.h"
8188#define OP_SIZE 64
8189#define ADDR_SIZE 64
8190#include "IEMAllCImplStrInstr.cpp.h"
8191
8192
8193/**
8194 * Implements 'XGETBV'.
8195 */
8196IEM_CIMPL_DEF_0(iemCImpl_xgetbv)
8197{
8198 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
8199 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
8200 {
8201 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
8202 switch (uEcx)
8203 {
8204 case 0:
8205 break;
8206
8207 case 1: /** @todo Implement XCR1 support. */
8208 default:
8209 Log(("xgetbv ecx=%RX32 -> #GP(0)\n", uEcx));
8210 return iemRaiseGeneralProtectionFault0(pVCpu);
8211
8212 }
8213 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
8214 pVCpu->cpum.GstCtx.rax = RT_LO_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
8215 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
8216
8217 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8218 return VINF_SUCCESS;
8219 }
8220 Log(("xgetbv CR4.OSXSAVE=0 -> UD\n"));
8221 return iemRaiseUndefinedOpcode(pVCpu);
8222}
8223
8224
8225/**
8226 * Implements 'XSETBV'.
8227 */
8228IEM_CIMPL_DEF_0(iemCImpl_xsetbv)
8229{
8230 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
8231 {
8232 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
8233 {
8234 Log2(("xsetbv: Guest intercept -> #VMEXIT\n"));
8235 IEM_SVM_UPDATE_NRIP(pVCpu);
8236 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_XSETBV, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
8237 }
8238
8239 if (pVCpu->iem.s.uCpl == 0)
8240 {
8241 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
8242
8243 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8244 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_XSETBV, cbInstr);
8245
8246 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
8247 uint64_t uNewValue = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx);
8248 switch (uEcx)
8249 {
8250 case 0:
8251 {
8252 int rc = CPUMSetGuestXcr0(pVCpu, uNewValue);
8253 if (rc == VINF_SUCCESS)
8254 break;
8255 Assert(rc == VERR_CPUM_RAISE_GP_0);
8256 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
8257 return iemRaiseGeneralProtectionFault0(pVCpu);
8258 }
8259
8260 case 1: /** @todo Implement XCR1 support. */
8261 default:
8262 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
8263 return iemRaiseGeneralProtectionFault0(pVCpu);
8264
8265 }
8266
8267 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8268 return VINF_SUCCESS;
8269 }
8270
8271 Log(("xsetbv cpl=%u -> GP(0)\n", pVCpu->iem.s.uCpl));
8272 return iemRaiseGeneralProtectionFault0(pVCpu);
8273 }
8274 Log(("xsetbv CR4.OSXSAVE=0 -> UD\n"));
8275 return iemRaiseUndefinedOpcode(pVCpu);
8276}
8277
8278#ifndef RT_ARCH_ARM64
8279# ifdef IN_RING3
8280
8281/** Argument package for iemCImpl_cmpxchg16b_fallback_rendezvous_callback. */
8282struct IEMCIMPLCX16ARGS
8283{
8284 PRTUINT128U pu128Dst;
8285 PRTUINT128U pu128RaxRdx;
8286 PRTUINT128U pu128RbxRcx;
8287 uint32_t *pEFlags;
8288# ifdef VBOX_STRICT
8289 uint32_t cCalls;
8290# endif
8291};
8292
8293/**
8294 * @callback_method_impl{FNVMMEMTRENDEZVOUS,
8295 * Worker for iemCImpl_cmpxchg16b_fallback_rendezvous}
8296 */
8297static DECLCALLBACK(VBOXSTRICTRC) iemCImpl_cmpxchg16b_fallback_rendezvous_callback(PVM pVM, PVMCPUCC pVCpu, void *pvUser)
8298{
8299 RT_NOREF(pVM, pVCpu);
8300 struct IEMCIMPLCX16ARGS *pArgs = (struct IEMCIMPLCX16ARGS *)pvUser;
8301# ifdef VBOX_STRICT
8302 Assert(pArgs->cCalls == 0);
8303 pArgs->cCalls++;
8304# endif
8305
8306 iemAImpl_cmpxchg16b_fallback(pArgs->pu128Dst, pArgs->pu128RaxRdx, pArgs->pu128RbxRcx, pArgs->pEFlags);
8307 return VINF_SUCCESS;
8308}
8309
8310# endif /* IN_RING3 */
8311
8312/**
8313 * Implements 'CMPXCHG16B' fallback using rendezvous.
8314 */
8315IEM_CIMPL_DEF_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
8316 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags)
8317{
8318# ifdef IN_RING3
8319 struct IEMCIMPLCX16ARGS Args;
8320 Args.pu128Dst = pu128Dst;
8321 Args.pu128RaxRdx = pu128RaxRdx;
8322 Args.pu128RbxRcx = pu128RbxRcx;
8323 Args.pEFlags = pEFlags;
8324# ifdef VBOX_STRICT
8325 Args.cCalls = 0;
8326# endif
8327 VBOXSTRICTRC rcStrict = VMMR3EmtRendezvous(pVCpu->CTX_SUFF(pVM), VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE,
8328 iemCImpl_cmpxchg16b_fallback_rendezvous_callback, &Args);
8329 Assert(Args.cCalls == 1);
8330 if (rcStrict == VINF_SUCCESS)
8331 {
8332 /* Duplicated tail code. */
8333 rcStrict = iemMemCommitAndUnmap(pVCpu, pu128Dst, IEM_ACCESS_DATA_RW);
8334 if (rcStrict == VINF_SUCCESS)
8335 {
8336 pVCpu->cpum.GstCtx.eflags.u = *pEFlags; /* IEM_MC_COMMIT_EFLAGS */
8337 if (!(*pEFlags & X86_EFL_ZF))
8338 {
8339 pVCpu->cpum.GstCtx.rax = pu128RaxRdx->s.Lo;
8340 pVCpu->cpum.GstCtx.rdx = pu128RaxRdx->s.Hi;
8341 }
8342 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8343 }
8344 }
8345 return rcStrict;
8346# else
8347 RT_NOREF(pVCpu, cbInstr, pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
8348 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; /* This should get us to ring-3 for now. Should perhaps be replaced later. */
8349# endif
8350}
8351
8352#endif /* RT_ARCH_ARM64 */
8353
8354/**
8355 * Implements 'CLFLUSH' and 'CLFLUSHOPT'.
8356 *
8357 * This is implemented in C because it triggers a load like behaviour without
8358 * actually reading anything. Since that's not so common, it's implemented
8359 * here.
8360 *
8361 * @param iEffSeg The effective segment.
8362 * @param GCPtrEff The address of the image.
8363 */
8364IEM_CIMPL_DEF_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8365{
8366 /*
8367 * Pretend to do a load w/o reading (see also iemCImpl_monitor and iemMemMap).
8368 */
8369 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrEff);
8370 if (rcStrict == VINF_SUCCESS)
8371 {
8372 RTGCPHYS GCPhysMem;
8373 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrEff, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
8374 if (rcStrict == VINF_SUCCESS)
8375 {
8376#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8377 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8378 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
8379 {
8380 /*
8381 * CLFLUSH/CLFLUSHOPT does not access the memory, but flushes the cache-line
8382 * that contains the address. However, if the address falls in the APIC-access
8383 * page, the address flushed must instead be the corresponding address in the
8384 * virtual-APIC page.
8385 *
8386 * See Intel spec. 29.4.4 "Instruction-Specific Considerations".
8387 */
8388 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, 1, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA);
8389 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE
8390 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR)
8391 return rcStrict;
8392 }
8393#endif
8394 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8395 return VINF_SUCCESS;
8396 }
8397 }
8398
8399 return rcStrict;
8400}
8401
8402
8403/**
8404 * Implements 'FINIT' and 'FNINIT'.
8405 *
8406 * @param fCheckXcpts Whether to check for umasked pending exceptions or
8407 * not.
8408 */
8409IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts)
8410{
8411 /*
8412 * Exceptions.
8413 */
8414 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
8415 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
8416 return iemRaiseDeviceNotAvailable(pVCpu);
8417
8418 iemFpuActualizeStateForChange(pVCpu);
8419 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_X87);
8420
8421 /* FINIT: Raise #MF on pending exception(s): */
8422 if (fCheckXcpts && (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))
8423 return iemRaiseMathFault(pVCpu);
8424
8425 /*
8426 * Reset the state.
8427 */
8428 PX86XSAVEAREA pXState = &pVCpu->cpum.GstCtx.XState;
8429
8430 /* Rotate the stack to account for changed TOS. */
8431 iemFpuRotateStackSetTop(&pXState->x87, 0);
8432
8433 pXState->x87.FCW = 0x37f;
8434 pXState->x87.FSW = 0;
8435 pXState->x87.FTW = 0x00; /* 0 - empty. */
8436 /** @todo Intel says the instruction and data pointers are not cleared on
8437 * 387, presume that 8087 and 287 doesn't do so either. */
8438 /** @todo test this stuff. */
8439 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
8440 {
8441 pXState->x87.FPUDP = 0;
8442 pXState->x87.DS = 0; //??
8443 pXState->x87.Rsrvd2 = 0;
8444 pXState->x87.FPUIP = 0;
8445 pXState->x87.CS = 0; //??
8446 pXState->x87.Rsrvd1 = 0;
8447 }
8448 pXState->x87.FOP = 0;
8449
8450 iemHlpUsedFpu(pVCpu);
8451 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8452 return VINF_SUCCESS;
8453}
8454
8455
8456/**
8457 * Implements 'FXSAVE'.
8458 *
8459 * @param iEffSeg The effective segment.
8460 * @param GCPtrEff The address of the image.
8461 * @param enmEffOpSize The operand size (only REX.W really matters).
8462 */
8463IEM_CIMPL_DEF_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8464{
8465 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8466
8467 /*
8468 * Raise exceptions.
8469 */
8470 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
8471 return iemRaiseDeviceNotAvailable(pVCpu);
8472
8473 /*
8474 * Access the memory.
8475 */
8476 void *pvMem512;
8477 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
8478 15 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8479 if (rcStrict != VINF_SUCCESS)
8480 return rcStrict;
8481 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
8482 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.XState.x87;
8483
8484 /*
8485 * Store the registers.
8486 */
8487 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
8488 * implementation specific whether MXCSR and XMM0-XMM7 are saved. */
8489
8490 /* common for all formats */
8491 pDst->FCW = pSrc->FCW;
8492 pDst->FSW = pSrc->FSW;
8493 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8494 pDst->FOP = pSrc->FOP;
8495 pDst->MXCSR = pSrc->MXCSR;
8496 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8497 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8498 {
8499 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
8500 * them for now... */
8501 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8502 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8503 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8504 pDst->aRegs[i].au32[3] = 0;
8505 }
8506
8507 /* FPU IP, CS, DP and DS. */
8508 pDst->FPUIP = pSrc->FPUIP;
8509 pDst->CS = pSrc->CS;
8510 pDst->FPUDP = pSrc->FPUDP;
8511 pDst->DS = pSrc->DS;
8512 if (enmEffOpSize == IEMMODE_64BIT)
8513 {
8514 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8515 pDst->Rsrvd1 = pSrc->Rsrvd1;
8516 pDst->Rsrvd2 = pSrc->Rsrvd2;
8517 }
8518 else
8519 {
8520 pDst->Rsrvd1 = 0;
8521 pDst->Rsrvd2 = 0;
8522 }
8523
8524 /* XMM registers. */
8525 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
8526 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
8527 || pVCpu->iem.s.uCpl != 0)
8528 {
8529 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8530 for (uint32_t i = 0; i < cXmmRegs; i++)
8531 pDst->aXMM[i] = pSrc->aXMM[i];
8532 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8533 * right? */
8534 }
8535
8536 /*
8537 * Commit the memory.
8538 */
8539 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8540 if (rcStrict != VINF_SUCCESS)
8541 return rcStrict;
8542
8543 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8544 return VINF_SUCCESS;
8545}
8546
8547
8548/**
8549 * Implements 'FXRSTOR'.
8550 *
8551 * @param iEffSeg The effective segment register for @a GCPtrEff.
8552 * @param GCPtrEff The address of the image.
8553 * @param enmEffOpSize The operand size (only REX.W really matters).
8554 */
8555IEM_CIMPL_DEF_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8556{
8557 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8558
8559 /*
8560 * Raise exceptions.
8561 */
8562 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
8563 return iemRaiseDeviceNotAvailable(pVCpu);
8564
8565 /*
8566 * Access the memory.
8567 */
8568 void *pvMem512;
8569 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R,
8570 15 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8571 if (rcStrict != VINF_SUCCESS)
8572 return rcStrict;
8573 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
8574 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.XState.x87;
8575
8576 /*
8577 * Check the state for stuff which will #GP(0).
8578 */
8579 uint32_t const fMXCSR = pSrc->MXCSR;
8580 uint32_t const fMXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8581 if (fMXCSR & ~fMXCSR_MASK)
8582 {
8583 Log(("fxrstor: MXCSR=%#x (MXCSR_MASK=%#x) -> #GP(0)\n", fMXCSR, fMXCSR_MASK));
8584 return iemRaiseGeneralProtectionFault0(pVCpu);
8585 }
8586
8587 /*
8588 * Load the registers.
8589 */
8590 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
8591 * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
8592
8593 /* common for all formats */
8594 pDst->FCW = pSrc->FCW;
8595 pDst->FSW = pSrc->FSW;
8596 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8597 pDst->FOP = pSrc->FOP;
8598 pDst->MXCSR = fMXCSR;
8599 /* (MXCSR_MASK is read-only) */
8600 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
8601 {
8602 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8603 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8604 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8605 pDst->aRegs[i].au32[3] = 0;
8606 }
8607
8608 /* FPU IP, CS, DP and DS. */
8609 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8610 {
8611 pDst->FPUIP = pSrc->FPUIP;
8612 pDst->CS = pSrc->CS;
8613 pDst->Rsrvd1 = pSrc->Rsrvd1;
8614 pDst->FPUDP = pSrc->FPUDP;
8615 pDst->DS = pSrc->DS;
8616 pDst->Rsrvd2 = pSrc->Rsrvd2;
8617 }
8618 else
8619 {
8620 pDst->FPUIP = pSrc->FPUIP;
8621 pDst->CS = pSrc->CS;
8622 pDst->Rsrvd1 = 0;
8623 pDst->FPUDP = pSrc->FPUDP;
8624 pDst->DS = pSrc->DS;
8625 pDst->Rsrvd2 = 0;
8626 }
8627
8628 /* XMM registers. */
8629 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
8630 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
8631 || pVCpu->iem.s.uCpl != 0)
8632 {
8633 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8634 for (uint32_t i = 0; i < cXmmRegs; i++)
8635 pDst->aXMM[i] = pSrc->aXMM[i];
8636 }
8637
8638 if (pDst->FSW & X86_FSW_ES)
8639 Log11(("fxrstor: %04x:%08RX64: loading state with pending FPU exception (FSW=%#x)\n",
8640 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pSrc->FSW));
8641
8642 /*
8643 * Commit the memory.
8644 */
8645 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
8646 if (rcStrict != VINF_SUCCESS)
8647 return rcStrict;
8648
8649 iemHlpUsedFpu(pVCpu);
8650 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8651 return VINF_SUCCESS;
8652}
8653
8654
8655/**
8656 * Implements 'XSAVE'.
8657 *
8658 * @param iEffSeg The effective segment.
8659 * @param GCPtrEff The address of the image.
8660 * @param enmEffOpSize The operand size (only REX.W really matters).
8661 */
8662IEM_CIMPL_DEF_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8663{
8664 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
8665
8666 /*
8667 * Raise exceptions.
8668 */
8669 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8670 return iemRaiseUndefinedOpcode(pVCpu);
8671 /* When in VMX non-root mode and XSAVE/XRSTOR is not enabled, it results in #UD. */
8672 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8673 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_XSAVES_XRSTORS))
8674 {
8675 Log(("xrstor: Not enabled for nested-guest execution -> #UD\n"));
8676 return iemRaiseUndefinedOpcode(pVCpu);
8677 }
8678 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
8679 return iemRaiseDeviceNotAvailable(pVCpu);
8680
8681 /*
8682 * Calc the requested mask.
8683 */
8684 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
8685 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8686 uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
8687
8688/** @todo figure out the exact protocol for the memory access. Currently we
8689 * just need this crap to work halfways to make it possible to test
8690 * AVX instructions. */
8691/** @todo figure out the XINUSE and XMODIFIED */
8692
8693 /*
8694 * Access the x87 memory state.
8695 */
8696 /* The x87+SSE state. */
8697 void *pvMem512;
8698 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
8699 63 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8700 if (rcStrict != VINF_SUCCESS)
8701 return rcStrict;
8702 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
8703 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.XState.x87;
8704
8705 /* The header. */
8706 PX86XSAVEHDR pHdr;
8707 rcStrict = iemMemMap(pVCpu, (void **)&pHdr, sizeof(&pHdr), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_RW, 0 /* checked above */);
8708 if (rcStrict != VINF_SUCCESS)
8709 return rcStrict;
8710
8711 /*
8712 * Store the X87 state.
8713 */
8714 if (fReqComponents & XSAVE_C_X87)
8715 {
8716 /* common for all formats */
8717 pDst->FCW = pSrc->FCW;
8718 pDst->FSW = pSrc->FSW;
8719 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8720 pDst->FOP = pSrc->FOP;
8721 pDst->FPUIP = pSrc->FPUIP;
8722 pDst->CS = pSrc->CS;
8723 pDst->FPUDP = pSrc->FPUDP;
8724 pDst->DS = pSrc->DS;
8725 if (enmEffOpSize == IEMMODE_64BIT)
8726 {
8727 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8728 pDst->Rsrvd1 = pSrc->Rsrvd1;
8729 pDst->Rsrvd2 = pSrc->Rsrvd2;
8730 }
8731 else
8732 {
8733 pDst->Rsrvd1 = 0;
8734 pDst->Rsrvd2 = 0;
8735 }
8736 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8737 {
8738 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
8739 * them for now... */
8740 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8741 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8742 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8743 pDst->aRegs[i].au32[3] = 0;
8744 }
8745
8746 }
8747
8748 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
8749 {
8750 pDst->MXCSR = pSrc->MXCSR;
8751 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8752 }
8753
8754 if (fReqComponents & XSAVE_C_SSE)
8755 {
8756 /* XMM registers. */
8757 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8758 for (uint32_t i = 0; i < cXmmRegs; i++)
8759 pDst->aXMM[i] = pSrc->aXMM[i];
8760 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8761 * right? */
8762 }
8763
8764 /* Commit the x87 state bits. (probably wrong) */
8765 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8766 if (rcStrict != VINF_SUCCESS)
8767 return rcStrict;
8768
8769 /*
8770 * Store AVX state.
8771 */
8772 if (fReqComponents & XSAVE_C_YMM)
8773 {
8774 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8775 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8776 PCX86XSAVEYMMHI pCompSrc = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
8777 PX86XSAVEYMMHI pCompDst;
8778 rcStrict = iemMemMap(pVCpu, (void **)&pCompDst, sizeof(*pCompDst), iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT],
8779 IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE, 0 /* checked above */);
8780 if (rcStrict != VINF_SUCCESS)
8781 return rcStrict;
8782
8783 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8784 for (uint32_t i = 0; i < cXmmRegs; i++)
8785 pCompDst->aYmmHi[i] = pCompSrc->aYmmHi[i];
8786
8787 rcStrict = iemMemCommitAndUnmap(pVCpu, pCompDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8788 if (rcStrict != VINF_SUCCESS)
8789 return rcStrict;
8790 }
8791
8792 /*
8793 * Update the header.
8794 */
8795 pHdr->bmXState = (pHdr->bmXState & ~fReqComponents)
8796 | (fReqComponents & fXInUse);
8797
8798 rcStrict = iemMemCommitAndUnmap(pVCpu, pHdr, IEM_ACCESS_DATA_RW);
8799 if (rcStrict != VINF_SUCCESS)
8800 return rcStrict;
8801
8802 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8803 return VINF_SUCCESS;
8804}
8805
8806
8807/**
8808 * Implements 'XRSTOR'.
8809 *
8810 * @param iEffSeg The effective segment.
8811 * @param GCPtrEff The address of the image.
8812 * @param enmEffOpSize The operand size (only REX.W really matters).
8813 */
8814IEM_CIMPL_DEF_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8815{
8816 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
8817
8818 /*
8819 * Raise exceptions.
8820 */
8821 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8822 return iemRaiseUndefinedOpcode(pVCpu);
8823 /* When in VMX non-root mode and XSAVE/XRSTOR is not enabled, it results in #UD. */
8824 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8825 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_XSAVES_XRSTORS))
8826 {
8827 Log(("xrstor: Not enabled for nested-guest execution -> #UD\n"));
8828 return iemRaiseUndefinedOpcode(pVCpu);
8829 }
8830 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
8831 return iemRaiseDeviceNotAvailable(pVCpu);
8832 if (GCPtrEff & 63)
8833 {
8834 /** @todo CPU/VM detection possible! \#AC might not be signal for
8835 * all/any misalignment sizes, intel says its an implementation detail. */
8836 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
8837 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
8838 && pVCpu->iem.s.uCpl == 3)
8839 return iemRaiseAlignmentCheckException(pVCpu);
8840 return iemRaiseGeneralProtectionFault0(pVCpu);
8841 }
8842
8843/** @todo figure out the exact protocol for the memory access. Currently we
8844 * just need this crap to work halfways to make it possible to test
8845 * AVX instructions. */
8846/** @todo figure out the XINUSE and XMODIFIED */
8847
8848 /*
8849 * Access the x87 memory state.
8850 */
8851 /* The x87+SSE state. */
8852 void *pvMem512;
8853 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R,
8854 63 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8855 if (rcStrict != VINF_SUCCESS)
8856 return rcStrict;
8857 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
8858 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.XState.x87;
8859
8860 /*
8861 * Calc the requested mask
8862 */
8863 PX86XSAVEHDR pHdrDst = &pVCpu->cpum.GstCtx.XState.Hdr;
8864 PCX86XSAVEHDR pHdrSrc;
8865 rcStrict = iemMemMap(pVCpu, (void **)&pHdrSrc, sizeof(&pHdrSrc), iEffSeg, GCPtrEff + 512,
8866 IEM_ACCESS_DATA_R, 0 /* checked above */);
8867 if (rcStrict != VINF_SUCCESS)
8868 return rcStrict;
8869
8870 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
8871 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8872 //uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
8873 uint64_t const fRstorMask = pHdrSrc->bmXState;
8874 uint64_t const fCompMask = pHdrSrc->bmXComp;
8875
8876 AssertLogRelReturn(!(fCompMask & XSAVE_C_X), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8877
8878 uint32_t const cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8879
8880 /* We won't need this any longer. */
8881 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pHdrSrc, IEM_ACCESS_DATA_R);
8882 if (rcStrict != VINF_SUCCESS)
8883 return rcStrict;
8884
8885 /*
8886 * Store the X87 state.
8887 */
8888 if (fReqComponents & XSAVE_C_X87)
8889 {
8890 if (fRstorMask & XSAVE_C_X87)
8891 {
8892 pDst->FCW = pSrc->FCW;
8893 pDst->FSW = pSrc->FSW;
8894 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8895 pDst->FOP = pSrc->FOP;
8896 pDst->FPUIP = pSrc->FPUIP;
8897 pDst->CS = pSrc->CS;
8898 pDst->FPUDP = pSrc->FPUDP;
8899 pDst->DS = pSrc->DS;
8900 if (enmEffOpSize == IEMMODE_64BIT)
8901 {
8902 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8903 pDst->Rsrvd1 = pSrc->Rsrvd1;
8904 pDst->Rsrvd2 = pSrc->Rsrvd2;
8905 }
8906 else
8907 {
8908 pDst->Rsrvd1 = 0;
8909 pDst->Rsrvd2 = 0;
8910 }
8911 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8912 {
8913 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8914 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8915 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8916 pDst->aRegs[i].au32[3] = 0;
8917 }
8918 if (pDst->FSW & X86_FSW_ES)
8919 Log11(("xrstor: %04x:%08RX64: loading state with pending FPU exception (FSW=%#x)\n",
8920 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pSrc->FSW));
8921 }
8922 else
8923 {
8924 pDst->FCW = 0x37f;
8925 pDst->FSW = 0;
8926 pDst->FTW = 0x00; /* 0 - empty. */
8927 pDst->FPUDP = 0;
8928 pDst->DS = 0; //??
8929 pDst->Rsrvd2= 0;
8930 pDst->FPUIP = 0;
8931 pDst->CS = 0; //??
8932 pDst->Rsrvd1= 0;
8933 pDst->FOP = 0;
8934 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
8935 {
8936 pDst->aRegs[i].au32[0] = 0;
8937 pDst->aRegs[i].au32[1] = 0;
8938 pDst->aRegs[i].au32[2] = 0;
8939 pDst->aRegs[i].au32[3] = 0;
8940 }
8941 }
8942 pHdrDst->bmXState |= XSAVE_C_X87; /* playing safe for now */
8943 }
8944
8945 /* MXCSR */
8946 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
8947 {
8948 if (fRstorMask & (XSAVE_C_SSE | XSAVE_C_YMM))
8949 pDst->MXCSR = pSrc->MXCSR;
8950 else
8951 pDst->MXCSR = 0x1f80;
8952 }
8953
8954 /* XMM registers. */
8955 if (fReqComponents & XSAVE_C_SSE)
8956 {
8957 if (fRstorMask & XSAVE_C_SSE)
8958 {
8959 for (uint32_t i = 0; i < cXmmRegs; i++)
8960 pDst->aXMM[i] = pSrc->aXMM[i];
8961 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8962 * right? */
8963 }
8964 else
8965 {
8966 for (uint32_t i = 0; i < cXmmRegs; i++)
8967 {
8968 pDst->aXMM[i].au64[0] = 0;
8969 pDst->aXMM[i].au64[1] = 0;
8970 }
8971 }
8972 pHdrDst->bmXState |= XSAVE_C_SSE; /* playing safe for now */
8973 }
8974
8975 /* Unmap the x87 state bits (so we've don't run out of mapping). */
8976 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
8977 if (rcStrict != VINF_SUCCESS)
8978 return rcStrict;
8979
8980 /*
8981 * Restore AVX state.
8982 */
8983 if (fReqComponents & XSAVE_C_YMM)
8984 {
8985 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8986 PX86XSAVEYMMHI pCompDst = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
8987
8988 if (fRstorMask & XSAVE_C_YMM)
8989 {
8990 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8991 PCX86XSAVEYMMHI pCompSrc;
8992 rcStrict = iemMemMap(pVCpu, (void **)&pCompSrc, sizeof(*pCompDst),
8993 iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT],
8994 IEM_ACCESS_DATA_R, 0 /* checked above */);
8995 if (rcStrict != VINF_SUCCESS)
8996 return rcStrict;
8997
8998 for (uint32_t i = 0; i < cXmmRegs; i++)
8999 {
9000 pCompDst->aYmmHi[i].au64[0] = pCompSrc->aYmmHi[i].au64[0];
9001 pCompDst->aYmmHi[i].au64[1] = pCompSrc->aYmmHi[i].au64[1];
9002 }
9003
9004 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pCompSrc, IEM_ACCESS_DATA_R);
9005 if (rcStrict != VINF_SUCCESS)
9006 return rcStrict;
9007 }
9008 else
9009 {
9010 for (uint32_t i = 0; i < cXmmRegs; i++)
9011 {
9012 pCompDst->aYmmHi[i].au64[0] = 0;
9013 pCompDst->aYmmHi[i].au64[1] = 0;
9014 }
9015 }
9016 pHdrDst->bmXState |= XSAVE_C_YMM; /* playing safe for now */
9017 }
9018
9019 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9020 return VINF_SUCCESS;
9021}
9022
9023
9024
9025
9026/**
9027 * Implements 'STMXCSR'.
9028 *
9029 * @param iEffSeg The effective segment register for @a GCPtrEff.
9030 * @param GCPtrEff The address of the image.
9031 */
9032IEM_CIMPL_DEF_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9033{
9034 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
9035
9036 /*
9037 * Raise exceptions.
9038 */
9039 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
9040 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
9041 {
9042 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9043 {
9044 /*
9045 * Do the job.
9046 */
9047 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.XState.x87.MXCSR);
9048 if (rcStrict == VINF_SUCCESS)
9049 {
9050 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9051 return VINF_SUCCESS;
9052 }
9053 return rcStrict;
9054 }
9055 return iemRaiseDeviceNotAvailable(pVCpu);
9056 }
9057 return iemRaiseUndefinedOpcode(pVCpu);
9058}
9059
9060
9061/**
9062 * Implements 'VSTMXCSR'.
9063 *
9064 * @param iEffSeg The effective segment register for @a GCPtrEff.
9065 * @param GCPtrEff The address of the image.
9066 */
9067IEM_CIMPL_DEF_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9068{
9069 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_XCRx);
9070
9071 /*
9072 * Raise exceptions.
9073 */
9074 if ( ( !IEM_IS_GUEST_CPU_AMD(pVCpu)
9075 ? (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) == (XSAVE_C_SSE | XSAVE_C_YMM)
9076 : !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)) /* AMD Jaguar CPU (f0x16,m0,s1) behaviour */
9077 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
9078 {
9079 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9080 {
9081 /*
9082 * Do the job.
9083 */
9084 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.XState.x87.MXCSR);
9085 if (rcStrict == VINF_SUCCESS)
9086 {
9087 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9088 return VINF_SUCCESS;
9089 }
9090 return rcStrict;
9091 }
9092 return iemRaiseDeviceNotAvailable(pVCpu);
9093 }
9094 return iemRaiseUndefinedOpcode(pVCpu);
9095}
9096
9097
9098/**
9099 * Implements 'LDMXCSR'.
9100 *
9101 * @param iEffSeg The effective segment register for @a GCPtrEff.
9102 * @param GCPtrEff The address of the image.
9103 */
9104IEM_CIMPL_DEF_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9105{
9106 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
9107
9108 /*
9109 * Raise exceptions.
9110 */
9111 /** @todo testcase - order of LDMXCSR faults. Does \#PF, \#GP and \#SS
9112 * happen after or before \#UD and \#EM? */
9113 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
9114 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
9115 {
9116 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9117 {
9118 /*
9119 * Do the job.
9120 */
9121 uint32_t fNewMxCsr;
9122 VBOXSTRICTRC rcStrict = iemMemFetchDataU32(pVCpu, &fNewMxCsr, iEffSeg, GCPtrEff);
9123 if (rcStrict == VINF_SUCCESS)
9124 {
9125 uint32_t const fMxCsrMask = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
9126 if (!(fNewMxCsr & ~fMxCsrMask))
9127 {
9128 pVCpu->cpum.GstCtx.XState.x87.MXCSR = fNewMxCsr;
9129 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9130 return VINF_SUCCESS;
9131 }
9132 Log(("ldmxcsr: New MXCSR=%#RX32 & ~MASK=%#RX32 = %#RX32 -> #GP(0)\n",
9133 fNewMxCsr, fMxCsrMask, fNewMxCsr & ~fMxCsrMask));
9134 return iemRaiseGeneralProtectionFault0(pVCpu);
9135 }
9136 return rcStrict;
9137 }
9138 return iemRaiseDeviceNotAvailable(pVCpu);
9139 }
9140 return iemRaiseUndefinedOpcode(pVCpu);
9141}
9142
9143
9144/**
9145 * Commmon routine for fnstenv and fnsave.
9146 *
9147 * @param pVCpu The cross context virtual CPU structure of the calling thread.
9148 * @param enmEffOpSize The effective operand size.
9149 * @param uPtr Where to store the state.
9150 */
9151static void iemCImplCommonFpuStoreEnv(PVMCPUCC pVCpu, IEMMODE enmEffOpSize, RTPTRUNION uPtr)
9152{
9153 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9154 PCX86FXSTATE pSrcX87 = &pVCpu->cpum.GstCtx.XState.x87;
9155 if (enmEffOpSize == IEMMODE_16BIT)
9156 {
9157 uPtr.pu16[0] = pSrcX87->FCW;
9158 uPtr.pu16[1] = pSrcX87->FSW;
9159 uPtr.pu16[2] = iemFpuCalcFullFtw(pSrcX87);
9160 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9161 {
9162 /** @todo Testcase: How does this work when the FPUIP/CS was saved in
9163 * protected mode or long mode and we save it in real mode? And vice
9164 * versa? And with 32-bit operand size? I think CPU is storing the
9165 * effective address ((CS << 4) + IP) in the offset register and not
9166 * doing any address calculations here. */
9167 uPtr.pu16[3] = (uint16_t)pSrcX87->FPUIP;
9168 uPtr.pu16[4] = ((pSrcX87->FPUIP >> 4) & UINT16_C(0xf000)) | pSrcX87->FOP;
9169 uPtr.pu16[5] = (uint16_t)pSrcX87->FPUDP;
9170 uPtr.pu16[6] = (pSrcX87->FPUDP >> 4) & UINT16_C(0xf000);
9171 }
9172 else
9173 {
9174 uPtr.pu16[3] = pSrcX87->FPUIP;
9175 uPtr.pu16[4] = pSrcX87->CS;
9176 uPtr.pu16[5] = pSrcX87->FPUDP;
9177 uPtr.pu16[6] = pSrcX87->DS;
9178 }
9179 }
9180 else
9181 {
9182 /** @todo Testcase: what is stored in the "gray" areas? (figure 8-9 and 8-10) */
9183 uPtr.pu16[0*2] = pSrcX87->FCW;
9184 uPtr.pu16[0*2+1] = 0xffff; /* (0xffff observed on intel skylake.) */
9185 uPtr.pu16[1*2] = pSrcX87->FSW;
9186 uPtr.pu16[1*2+1] = 0xffff;
9187 uPtr.pu16[2*2] = iemFpuCalcFullFtw(pSrcX87);
9188 uPtr.pu16[2*2+1] = 0xffff;
9189 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9190 {
9191 uPtr.pu16[3*2] = (uint16_t)pSrcX87->FPUIP;
9192 uPtr.pu32[4] = ((pSrcX87->FPUIP & UINT32_C(0xffff0000)) >> 4) | pSrcX87->FOP;
9193 uPtr.pu16[5*2] = (uint16_t)pSrcX87->FPUDP;
9194 uPtr.pu32[6] = (pSrcX87->FPUDP & UINT32_C(0xffff0000)) >> 4;
9195 }
9196 else
9197 {
9198 uPtr.pu32[3] = pSrcX87->FPUIP;
9199 uPtr.pu16[4*2] = pSrcX87->CS;
9200 uPtr.pu16[4*2+1] = pSrcX87->FOP;
9201 uPtr.pu32[5] = pSrcX87->FPUDP;
9202 uPtr.pu16[6*2] = pSrcX87->DS;
9203 uPtr.pu16[6*2+1] = 0xffff;
9204 }
9205 }
9206}
9207
9208
9209/**
9210 * Commmon routine for fldenv and frstor
9211 *
9212 * @param pVCpu The cross context virtual CPU structure of the calling thread.
9213 * @param enmEffOpSize The effective operand size.
9214 * @param uPtr Where to store the state.
9215 */
9216static void iemCImplCommonFpuRestoreEnv(PVMCPUCC pVCpu, IEMMODE enmEffOpSize, RTCPTRUNION uPtr)
9217{
9218 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9219 PX86FXSTATE pDstX87 = &pVCpu->cpum.GstCtx.XState.x87;
9220 if (enmEffOpSize == IEMMODE_16BIT)
9221 {
9222 pDstX87->FCW = uPtr.pu16[0];
9223 pDstX87->FSW = uPtr.pu16[1];
9224 pDstX87->FTW = uPtr.pu16[2];
9225 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9226 {
9227 pDstX87->FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
9228 pDstX87->FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
9229 pDstX87->FOP = uPtr.pu16[4] & UINT16_C(0x07ff);
9230 pDstX87->CS = 0;
9231 pDstX87->Rsrvd1= 0;
9232 pDstX87->DS = 0;
9233 pDstX87->Rsrvd2= 0;
9234 }
9235 else
9236 {
9237 pDstX87->FPUIP = uPtr.pu16[3];
9238 pDstX87->CS = uPtr.pu16[4];
9239 pDstX87->Rsrvd1= 0;
9240 pDstX87->FPUDP = uPtr.pu16[5];
9241 pDstX87->DS = uPtr.pu16[6];
9242 pDstX87->Rsrvd2= 0;
9243 /** @todo Testcase: Is FOP cleared when doing 16-bit protected mode fldenv? */
9244 }
9245 }
9246 else
9247 {
9248 pDstX87->FCW = uPtr.pu16[0*2];
9249 pDstX87->FSW = uPtr.pu16[1*2];
9250 pDstX87->FTW = uPtr.pu16[2*2];
9251 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9252 {
9253 pDstX87->FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
9254 pDstX87->FOP = uPtr.pu32[4] & UINT16_C(0x07ff);
9255 pDstX87->FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
9256 pDstX87->CS = 0;
9257 pDstX87->Rsrvd1= 0;
9258 pDstX87->DS = 0;
9259 pDstX87->Rsrvd2= 0;
9260 }
9261 else
9262 {
9263 pDstX87->FPUIP = uPtr.pu32[3];
9264 pDstX87->CS = uPtr.pu16[4*2];
9265 pDstX87->Rsrvd1= 0;
9266 pDstX87->FOP = uPtr.pu16[4*2+1];
9267 pDstX87->FPUDP = uPtr.pu32[5];
9268 pDstX87->DS = uPtr.pu16[6*2];
9269 pDstX87->Rsrvd2= 0;
9270 }
9271 }
9272
9273 /* Make adjustments. */
9274 pDstX87->FTW = iemFpuCompressFtw(pDstX87->FTW);
9275#ifdef LOG_ENABLED
9276 uint16_t const fOldFsw = pDstX87->FSW;
9277#endif
9278 pDstX87->FCW &= ~X86_FCW_ZERO_MASK;
9279 iemFpuRecalcExceptionStatus(pDstX87);
9280#ifdef LOG_ENABLED
9281 if ((pDstX87->FSW & X86_FSW_ES) ^ (fOldFsw & X86_FSW_ES))
9282 Log11(("iemCImplCommonFpuRestoreEnv: %04x:%08RX64: %s FPU exception (FCW=%#x FSW=%#x -> %#x)\n",
9283 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fOldFsw & X86_FSW_ES ? "Supressed" : "Raised",
9284 pDstX87->FCW, fOldFsw, pDstX87->FSW));
9285#endif
9286
9287 /** @todo Testcase: Check if ES and/or B are automatically cleared if no
9288 * exceptions are pending after loading the saved state? */
9289}
9290
9291
9292/**
9293 * Implements 'FNSTENV'.
9294 *
9295 * @param enmEffOpSize The operand size (only REX.W really matters).
9296 * @param iEffSeg The effective segment register for @a GCPtrEffDst.
9297 * @param GCPtrEffDst The address of the image.
9298 */
9299IEM_CIMPL_DEF_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
9300{
9301 RTPTRUNION uPtr;
9302 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
9303 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
9304 enmEffOpSize == IEMMODE_16BIT ? 1 : 3 /** @todo ? */);
9305 if (rcStrict != VINF_SUCCESS)
9306 return rcStrict;
9307
9308 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
9309
9310 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
9311 if (rcStrict != VINF_SUCCESS)
9312 return rcStrict;
9313
9314 /* Mask all math exceptions. Any possibly pending exceptions will be cleared. */
9315 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9316 pFpuCtx->FCW |= X86_FCW_XCPT_MASK;
9317#ifdef LOG_ENABLED
9318 uint16_t fOldFsw = pFpuCtx->FSW;
9319#endif
9320 iemFpuRecalcExceptionStatus(pFpuCtx);
9321#ifdef LOG_ENABLED
9322 if ((pFpuCtx->FSW & X86_FSW_ES) ^ (fOldFsw & X86_FSW_ES))
9323 Log11(("fnstenv: %04x:%08RX64: %s FPU exception (FCW=%#x, FSW %#x -> %#x)\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
9324 fOldFsw & X86_FSW_ES ? "Supressed" : "Raised", pFpuCtx->FCW, fOldFsw, pFpuCtx->FSW));
9325#endif
9326
9327 iemHlpUsedFpu(pVCpu);
9328
9329 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
9330 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9331 return VINF_SUCCESS;
9332}
9333
9334
9335/**
9336 * Implements 'FNSAVE'.
9337 *
9338 * @param enmEffOpSize The operand size.
9339 * @param iEffSeg The effective segment register for @a GCPtrEffDst.
9340 * @param GCPtrEffDst The address of the image.
9341 */
9342IEM_CIMPL_DEF_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
9343{
9344 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9345
9346 RTPTRUNION uPtr;
9347 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
9348 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE, 3 /** @todo ? */);
9349 if (rcStrict != VINF_SUCCESS)
9350 return rcStrict;
9351
9352 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9353 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
9354 PRTFLOAT80U paRegs = (PRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
9355 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
9356 {
9357 paRegs[i].au32[0] = pFpuCtx->aRegs[i].au32[0];
9358 paRegs[i].au32[1] = pFpuCtx->aRegs[i].au32[1];
9359 paRegs[i].au16[4] = pFpuCtx->aRegs[i].au16[4];
9360 }
9361
9362 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
9363 if (rcStrict != VINF_SUCCESS)
9364 return rcStrict;
9365
9366 /* Rotate the stack to account for changed TOS. */
9367 iemFpuRotateStackSetTop(pFpuCtx, 0);
9368
9369 /*
9370 * Re-initialize the FPU context.
9371 */
9372 pFpuCtx->FCW = 0x37f;
9373 pFpuCtx->FSW = 0;
9374 pFpuCtx->FTW = 0x00; /* 0 - empty */
9375 pFpuCtx->FPUDP = 0;
9376 pFpuCtx->DS = 0;
9377 pFpuCtx->Rsrvd2= 0;
9378 pFpuCtx->FPUIP = 0;
9379 pFpuCtx->CS = 0;
9380 pFpuCtx->Rsrvd1= 0;
9381 pFpuCtx->FOP = 0;
9382
9383 iemHlpUsedFpu(pVCpu);
9384 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9385 return VINF_SUCCESS;
9386}
9387
9388
9389
9390/**
9391 * Implements 'FLDENV'.
9392 *
9393 * @param enmEffOpSize The operand size (only REX.W really matters).
9394 * @param iEffSeg The effective segment register for @a GCPtrEffSrc.
9395 * @param GCPtrEffSrc The address of the image.
9396 */
9397IEM_CIMPL_DEF_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
9398{
9399 RTCPTRUNION uPtr;
9400 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
9401 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R,
9402 enmEffOpSize == IEMMODE_16BIT ? 1 : 3 /** @todo ?*/);
9403 if (rcStrict != VINF_SUCCESS)
9404 return rcStrict;
9405
9406 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
9407
9408 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
9409 if (rcStrict != VINF_SUCCESS)
9410 return rcStrict;
9411
9412 iemHlpUsedFpu(pVCpu);
9413 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9414 return VINF_SUCCESS;
9415}
9416
9417
9418/**
9419 * Implements 'FRSTOR'.
9420 *
9421 * @param enmEffOpSize The operand size.
9422 * @param iEffSeg The effective segment register for @a GCPtrEffSrc.
9423 * @param GCPtrEffSrc The address of the image.
9424 */
9425IEM_CIMPL_DEF_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
9426{
9427 RTCPTRUNION uPtr;
9428 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
9429 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R, 3 /** @todo ?*/ );
9430 if (rcStrict != VINF_SUCCESS)
9431 return rcStrict;
9432
9433 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9434 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
9435 PCRTFLOAT80U paRegs = (PCRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
9436 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
9437 {
9438 pFpuCtx->aRegs[i].au32[0] = paRegs[i].au32[0];
9439 pFpuCtx->aRegs[i].au32[1] = paRegs[i].au32[1];
9440 pFpuCtx->aRegs[i].au32[2] = paRegs[i].au16[4];
9441 pFpuCtx->aRegs[i].au32[3] = 0;
9442 }
9443
9444 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
9445 if (rcStrict != VINF_SUCCESS)
9446 return rcStrict;
9447
9448 iemHlpUsedFpu(pVCpu);
9449 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9450 return VINF_SUCCESS;
9451}
9452
9453
9454/**
9455 * Implements 'FLDCW'.
9456 *
9457 * @param u16Fcw The new FCW.
9458 */
9459IEM_CIMPL_DEF_1(iemCImpl_fldcw, uint16_t, u16Fcw)
9460{
9461 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9462
9463 /** @todo Testcase: Check what happens when trying to load X86_FCW_PC_RSVD. */
9464 /** @todo Testcase: Try see what happens when trying to set undefined bits
9465 * (other than 6 and 7). Currently ignoring them. */
9466 /** @todo Testcase: Test that it raises and loweres the FPU exception bits
9467 * according to FSW. (This is what is currently implemented.) */
9468 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9469 pFpuCtx->FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
9470#ifdef LOG_ENABLED
9471 uint16_t fOldFsw = pFpuCtx->FSW;
9472#endif
9473 iemFpuRecalcExceptionStatus(pFpuCtx);
9474#ifdef LOG_ENABLED
9475 if ((pFpuCtx->FSW & X86_FSW_ES) ^ (fOldFsw & X86_FSW_ES))
9476 Log11(("fldcw: %04x:%08RX64: %s FPU exception (FCW=%#x, FSW %#x -> %#x)\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
9477 fOldFsw & X86_FSW_ES ? "Supressed" : "Raised", pFpuCtx->FCW, fOldFsw, pFpuCtx->FSW));
9478#endif
9479
9480 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
9481 iemHlpUsedFpu(pVCpu);
9482 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9483 return VINF_SUCCESS;
9484}
9485
9486
9487
9488/**
9489 * Implements the underflow case of fxch.
9490 *
9491 * @param iStReg The other stack register.
9492 */
9493IEM_CIMPL_DEF_1(iemCImpl_fxch_underflow, uint8_t, iStReg)
9494{
9495 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9496
9497 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9498 unsigned const iReg1 = X86_FSW_TOP_GET(pFpuCtx->FSW);
9499 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
9500 Assert(!(RT_BIT(iReg1) & pFpuCtx->FTW) || !(RT_BIT(iReg2) & pFpuCtx->FTW));
9501
9502 /** @todo Testcase: fxch underflow. Making assumptions that underflowed
9503 * registers are read as QNaN and then exchanged. This could be
9504 * wrong... */
9505 if (pFpuCtx->FCW & X86_FCW_IM)
9506 {
9507 if (RT_BIT(iReg1) & pFpuCtx->FTW)
9508 {
9509 if (RT_BIT(iReg2) & pFpuCtx->FTW)
9510 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
9511 else
9512 pFpuCtx->aRegs[0].r80 = pFpuCtx->aRegs[iStReg].r80;
9513 iemFpuStoreQNan(&pFpuCtx->aRegs[iStReg].r80);
9514 }
9515 else
9516 {
9517 pFpuCtx->aRegs[iStReg].r80 = pFpuCtx->aRegs[0].r80;
9518 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
9519 }
9520 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
9521 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
9522 }
9523 else
9524 {
9525 /* raise underflow exception, don't change anything. */
9526 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
9527 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
9528 Log11(("fxch: %04x:%08RX64: Underflow exception (FSW=%#x)\n",
9529 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pFpuCtx->FSW));
9530 }
9531
9532 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
9533 iemHlpUsedFpu(pVCpu);
9534 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9535 return VINF_SUCCESS;
9536}
9537
9538
9539/**
9540 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
9541 *
9542 * @param iStReg The other stack register.
9543 * @param pfnAImpl The assembly comparison implementation.
9544 * @param fPop Whether we should pop the stack when done or not.
9545 */
9546IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)
9547{
9548 Assert(iStReg < 8);
9549 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9550
9551 /*
9552 * Raise exceptions.
9553 */
9554 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
9555 return iemRaiseDeviceNotAvailable(pVCpu);
9556
9557 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9558 uint16_t u16Fsw = pFpuCtx->FSW;
9559 if (u16Fsw & X86_FSW_ES)
9560 return iemRaiseMathFault(pVCpu);
9561
9562 /*
9563 * Check if any of the register accesses causes #SF + #IA.
9564 */
9565 unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
9566 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
9567 if ((pFpuCtx->FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
9568 {
9569 uint32_t u32Eflags = pfnAImpl(pFpuCtx, &u16Fsw, &pFpuCtx->aRegs[0].r80, &pFpuCtx->aRegs[iStReg].r80);
9570
9571 pFpuCtx->FSW &= ~X86_FSW_C1;
9572 pFpuCtx->FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
9573 if ( !(u16Fsw & X86_FSW_IE)
9574 || (pFpuCtx->FCW & X86_FCW_IM) )
9575 {
9576 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9577 pVCpu->cpum.GstCtx.eflags.u |= u32Eflags & (X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9578 }
9579 }
9580 else if (pFpuCtx->FCW & X86_FCW_IM)
9581 {
9582 /* Masked underflow. */
9583 pFpuCtx->FSW &= ~X86_FSW_C1;
9584 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
9585 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9586 pVCpu->cpum.GstCtx.eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
9587 }
9588 else
9589 {
9590 /* Raise underflow - don't touch EFLAGS or TOP. */
9591 pFpuCtx->FSW &= ~X86_FSW_C1;
9592 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
9593 Log11(("fxch: %04x:%08RX64: Raising IE+SF exception (FSW=%#x)\n",
9594 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pFpuCtx->FSW));
9595 fPop = false;
9596 }
9597
9598 /*
9599 * Pop if necessary.
9600 */
9601 if (fPop)
9602 {
9603 pFpuCtx->FTW &= ~RT_BIT(iReg1);
9604 iemFpuStackIncTop(pVCpu);
9605 }
9606
9607 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
9608 iemHlpUsedFpu(pVCpu);
9609 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9610 return VINF_SUCCESS;
9611}
9612
9613/** @} */
9614
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