1 | /* $Id: IEMAllAImplC.cpp 94156 2022-03-10 13:59:24Z vboxsync $ */
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2 | /** @file
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3 | * IEM - Instruction Implementation in Assembly, portable C variant.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2011-2022 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | /*********************************************************************************************************************************
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20 | * Header Files *
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21 | *********************************************************************************************************************************/
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22 | #include "IEMInternal.h"
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23 | #include <VBox/vmm/vmcc.h>
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24 | #include <iprt/errcore.h>
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25 | #include <iprt/x86.h>
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26 | #include <iprt/uint128.h>
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27 |
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28 |
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29 | /*********************************************************************************************************************************
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30 | * Defined Constants And Macros *
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31 | *********************************************************************************************************************************/
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32 | /** @def IEM_WITHOUT_ASSEMBLY
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33 | * Enables all the code in this file.
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34 | */
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35 | #if !defined(IEM_WITHOUT_ASSEMBLY)
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36 | # if defined(RT_ARCH_ARM32) || defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING)
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37 | # define IEM_WITHOUT_ASSEMBLY
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38 | # endif
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39 | #endif
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40 | /* IEM_WITH_ASSEMBLY trumps IEM_WITHOUT_ASSEMBLY for tstIEMAImplAsm purposes. */
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41 | #ifdef IEM_WITH_ASSEMBLY
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42 | # undef IEM_WITHOUT_ASSEMBLY
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43 | #endif
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44 |
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45 | /**
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46 | * Calculates the signed flag value given a result and it's bit width.
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47 | *
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48 | * The signed flag (SF) is a duplication of the most significant bit in the
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49 | * result.
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50 | *
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51 | * @returns X86_EFL_SF or 0.
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52 | * @param a_uResult Unsigned result value.
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53 | * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
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54 | */
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55 | #define X86_EFL_CALC_SF(a_uResult, a_cBitsWidth) \
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56 | ( (uint32_t)((a_uResult) >> ((a_cBitsWidth) - X86_EFL_SF_BIT - 1)) & X86_EFL_SF )
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57 |
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58 | /**
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59 | * Calculates the zero flag value given a result.
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60 | *
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61 | * The zero flag (ZF) indicates whether the result is zero or not.
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62 | *
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63 | * @returns X86_EFL_ZF or 0.
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64 | * @param a_uResult Unsigned result value.
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65 | */
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66 | #define X86_EFL_CALC_ZF(a_uResult) \
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67 | ( (uint32_t)((a_uResult) == 0) << X86_EFL_ZF_BIT )
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68 |
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69 | /**
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70 | * Extracts the OF flag from a OF calculation result.
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71 | *
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72 | * These are typically used by concating with a bitcount. The problem is that
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73 | * 8-bit values needs shifting in the other direction than the others.
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74 | */
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75 | #define X86_EFL_GET_OF_8(a_uValue) (((uint32_t)(a_uValue) << (X86_EFL_OF_BIT - 8 + 1)) & X86_EFL_OF)
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76 | #define X86_EFL_GET_OF_16(a_uValue) ((uint32_t)((a_uValue) >> (16 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
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77 | #define X86_EFL_GET_OF_32(a_uValue) ((uint32_t)((a_uValue) >> (32 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
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78 | #define X86_EFL_GET_OF_64(a_uValue) ((uint32_t)((a_uValue) >> (64 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
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79 |
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80 | /**
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81 | * Updates the status bits (CF, PF, AF, ZF, SF, and OF) after arithmetic op.
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82 | *
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83 | * @returns Status bits.
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84 | * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
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85 | * @param a_uResult Unsigned result value.
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86 | * @param a_uSrc The source value (for AF calc).
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87 | * @param a_uDst The original destination value (for AF calc).
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88 | * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
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89 | * @param a_CfExpr Bool expression for the carry flag (CF).
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90 | * @param a_uSrcOf The a_uSrc value to use for overflow calculation.
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91 | */
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92 | #define IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(a_pfEFlags, a_uResult, a_uDst, a_uSrc, a_cBitsWidth, a_CfExpr, a_uSrcOf) \
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93 | do { \
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94 | uint32_t fEflTmp = *(a_pfEFlags); \
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95 | fEflTmp &= ~X86_EFL_STATUS_BITS; \
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96 | fEflTmp |= (a_CfExpr) << X86_EFL_CF_BIT; \
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97 | fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
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98 | fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uSrc) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
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99 | fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
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100 | fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
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101 | \
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102 | /* Overflow during ADDition happens when both inputs have the same signed \
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103 | bit value and the result has a different sign bit value. \
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104 | \
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105 | Since subtraction can be rewritten as addition: 2 - 1 == 2 + -1, it \
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106 | follows that for SUBtraction the signed bit value must differ between \
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107 | the two inputs and the result's signed bit diff from the first input. \
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108 | Note! Must xor with sign bit to convert, not do (0 - a_uSrc). \
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109 | \
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110 | See also: http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt */ \
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111 | fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth( ( ((uint ## a_cBitsWidth ## _t)~((a_uDst) ^ (a_uSrcOf))) \
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112 | & RT_BIT_64(a_cBitsWidth - 1)) \
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113 | & ((a_uResult) ^ (a_uDst)) ); \
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114 | *(a_pfEFlags) = fEflTmp; \
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115 | } while (0)
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116 |
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117 | /**
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118 | * Updates the status bits (CF, PF, AF, ZF, SF, and OF) after a logical op.
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119 | *
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120 | * CF and OF are defined to be 0 by logical operations. AF on the other hand is
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121 | * undefined. We do not set AF, as that seems to make the most sense (which
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122 | * probably makes it the most wrong in real life).
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123 | *
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124 | * @returns Status bits.
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125 | * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
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126 | * @param a_uResult Unsigned result value.
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127 | * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
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128 | * @param a_fExtra Additional bits to set.
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129 | */
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130 | #define IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(a_pfEFlags, a_uResult, a_cBitsWidth, a_fExtra) \
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131 | do { \
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132 | uint32_t fEflTmp = *(a_pfEFlags); \
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133 | fEflTmp &= ~X86_EFL_STATUS_BITS; \
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134 | fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
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135 | fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
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136 | fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
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137 | fEflTmp |= (a_fExtra); \
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138 | *(a_pfEFlags) = fEflTmp; \
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139 | } while (0)
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140 |
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141 |
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142 | /*********************************************************************************************************************************
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143 | * Global Variables *
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144 | *********************************************************************************************************************************/
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145 | /**
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146 | * Parity calculation table.
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147 | *
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148 | * This is also used by iemAllAImpl.asm.
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149 | *
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150 | * The generator code:
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151 | * @code
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152 | * #include <stdio.h>
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153 | *
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154 | * int main()
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155 | * {
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156 | * unsigned b;
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157 | * for (b = 0; b < 256; b++)
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158 | * {
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159 | * int cOnes = ( b & 1)
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160 | * + ((b >> 1) & 1)
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161 | * + ((b >> 2) & 1)
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162 | * + ((b >> 3) & 1)
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163 | * + ((b >> 4) & 1)
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164 | * + ((b >> 5) & 1)
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165 | * + ((b >> 6) & 1)
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166 | * + ((b >> 7) & 1);
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167 | * printf(" /" "* %#04x = %u%u%u%u%u%u%u%ub *" "/ %s,\n",
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168 | * b,
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169 | * (b >> 7) & 1,
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170 | * (b >> 6) & 1,
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171 | * (b >> 5) & 1,
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172 | * (b >> 4) & 1,
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173 | * (b >> 3) & 1,
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174 | * (b >> 2) & 1,
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175 | * (b >> 1) & 1,
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176 | * b & 1,
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177 | * cOnes & 1 ? "0" : "X86_EFL_PF");
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178 | * }
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179 | * return 0;
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180 | * }
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181 | * @endcode
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182 | */
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183 | uint8_t const g_afParity[256] =
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184 | {
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185 | /* 0000 = 00000000b */ X86_EFL_PF,
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186 | /* 0x01 = 00000001b */ 0,
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187 | /* 0x02 = 00000010b */ 0,
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188 | /* 0x03 = 00000011b */ X86_EFL_PF,
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189 | /* 0x04 = 00000100b */ 0,
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190 | /* 0x05 = 00000101b */ X86_EFL_PF,
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191 | /* 0x06 = 00000110b */ X86_EFL_PF,
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192 | /* 0x07 = 00000111b */ 0,
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193 | /* 0x08 = 00001000b */ 0,
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194 | /* 0x09 = 00001001b */ X86_EFL_PF,
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195 | /* 0x0a = 00001010b */ X86_EFL_PF,
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196 | /* 0x0b = 00001011b */ 0,
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197 | /* 0x0c = 00001100b */ X86_EFL_PF,
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198 | /* 0x0d = 00001101b */ 0,
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199 | /* 0x0e = 00001110b */ 0,
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200 | /* 0x0f = 00001111b */ X86_EFL_PF,
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201 | /* 0x10 = 00010000b */ 0,
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202 | /* 0x11 = 00010001b */ X86_EFL_PF,
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203 | /* 0x12 = 00010010b */ X86_EFL_PF,
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204 | /* 0x13 = 00010011b */ 0,
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205 | /* 0x14 = 00010100b */ X86_EFL_PF,
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206 | /* 0x15 = 00010101b */ 0,
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207 | /* 0x16 = 00010110b */ 0,
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208 | /* 0x17 = 00010111b */ X86_EFL_PF,
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209 | /* 0x18 = 00011000b */ X86_EFL_PF,
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210 | /* 0x19 = 00011001b */ 0,
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211 | /* 0x1a = 00011010b */ 0,
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212 | /* 0x1b = 00011011b */ X86_EFL_PF,
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213 | /* 0x1c = 00011100b */ 0,
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214 | /* 0x1d = 00011101b */ X86_EFL_PF,
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215 | /* 0x1e = 00011110b */ X86_EFL_PF,
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216 | /* 0x1f = 00011111b */ 0,
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217 | /* 0x20 = 00100000b */ 0,
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218 | /* 0x21 = 00100001b */ X86_EFL_PF,
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219 | /* 0x22 = 00100010b */ X86_EFL_PF,
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220 | /* 0x23 = 00100011b */ 0,
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221 | /* 0x24 = 00100100b */ X86_EFL_PF,
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222 | /* 0x25 = 00100101b */ 0,
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223 | /* 0x26 = 00100110b */ 0,
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224 | /* 0x27 = 00100111b */ X86_EFL_PF,
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225 | /* 0x28 = 00101000b */ X86_EFL_PF,
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226 | /* 0x29 = 00101001b */ 0,
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227 | /* 0x2a = 00101010b */ 0,
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228 | /* 0x2b = 00101011b */ X86_EFL_PF,
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229 | /* 0x2c = 00101100b */ 0,
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230 | /* 0x2d = 00101101b */ X86_EFL_PF,
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231 | /* 0x2e = 00101110b */ X86_EFL_PF,
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232 | /* 0x2f = 00101111b */ 0,
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233 | /* 0x30 = 00110000b */ X86_EFL_PF,
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234 | /* 0x31 = 00110001b */ 0,
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235 | /* 0x32 = 00110010b */ 0,
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236 | /* 0x33 = 00110011b */ X86_EFL_PF,
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237 | /* 0x34 = 00110100b */ 0,
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238 | /* 0x35 = 00110101b */ X86_EFL_PF,
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239 | /* 0x36 = 00110110b */ X86_EFL_PF,
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240 | /* 0x37 = 00110111b */ 0,
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241 | /* 0x38 = 00111000b */ 0,
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242 | /* 0x39 = 00111001b */ X86_EFL_PF,
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243 | /* 0x3a = 00111010b */ X86_EFL_PF,
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244 | /* 0x3b = 00111011b */ 0,
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245 | /* 0x3c = 00111100b */ X86_EFL_PF,
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246 | /* 0x3d = 00111101b */ 0,
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247 | /* 0x3e = 00111110b */ 0,
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248 | /* 0x3f = 00111111b */ X86_EFL_PF,
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249 | /* 0x40 = 01000000b */ 0,
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250 | /* 0x41 = 01000001b */ X86_EFL_PF,
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251 | /* 0x42 = 01000010b */ X86_EFL_PF,
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252 | /* 0x43 = 01000011b */ 0,
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253 | /* 0x44 = 01000100b */ X86_EFL_PF,
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254 | /* 0x45 = 01000101b */ 0,
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255 | /* 0x46 = 01000110b */ 0,
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256 | /* 0x47 = 01000111b */ X86_EFL_PF,
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257 | /* 0x48 = 01001000b */ X86_EFL_PF,
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258 | /* 0x49 = 01001001b */ 0,
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259 | /* 0x4a = 01001010b */ 0,
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260 | /* 0x4b = 01001011b */ X86_EFL_PF,
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261 | /* 0x4c = 01001100b */ 0,
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262 | /* 0x4d = 01001101b */ X86_EFL_PF,
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263 | /* 0x4e = 01001110b */ X86_EFL_PF,
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264 | /* 0x4f = 01001111b */ 0,
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265 | /* 0x50 = 01010000b */ X86_EFL_PF,
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266 | /* 0x51 = 01010001b */ 0,
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267 | /* 0x52 = 01010010b */ 0,
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268 | /* 0x53 = 01010011b */ X86_EFL_PF,
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269 | /* 0x54 = 01010100b */ 0,
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270 | /* 0x55 = 01010101b */ X86_EFL_PF,
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271 | /* 0x56 = 01010110b */ X86_EFL_PF,
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272 | /* 0x57 = 01010111b */ 0,
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273 | /* 0x58 = 01011000b */ 0,
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274 | /* 0x59 = 01011001b */ X86_EFL_PF,
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275 | /* 0x5a = 01011010b */ X86_EFL_PF,
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276 | /* 0x5b = 01011011b */ 0,
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277 | /* 0x5c = 01011100b */ X86_EFL_PF,
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278 | /* 0x5d = 01011101b */ 0,
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279 | /* 0x5e = 01011110b */ 0,
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280 | /* 0x5f = 01011111b */ X86_EFL_PF,
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281 | /* 0x60 = 01100000b */ X86_EFL_PF,
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282 | /* 0x61 = 01100001b */ 0,
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283 | /* 0x62 = 01100010b */ 0,
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284 | /* 0x63 = 01100011b */ X86_EFL_PF,
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285 | /* 0x64 = 01100100b */ 0,
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286 | /* 0x65 = 01100101b */ X86_EFL_PF,
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287 | /* 0x66 = 01100110b */ X86_EFL_PF,
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288 | /* 0x67 = 01100111b */ 0,
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289 | /* 0x68 = 01101000b */ 0,
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290 | /* 0x69 = 01101001b */ X86_EFL_PF,
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291 | /* 0x6a = 01101010b */ X86_EFL_PF,
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292 | /* 0x6b = 01101011b */ 0,
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293 | /* 0x6c = 01101100b */ X86_EFL_PF,
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294 | /* 0x6d = 01101101b */ 0,
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295 | /* 0x6e = 01101110b */ 0,
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296 | /* 0x6f = 01101111b */ X86_EFL_PF,
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297 | /* 0x70 = 01110000b */ 0,
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298 | /* 0x71 = 01110001b */ X86_EFL_PF,
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299 | /* 0x72 = 01110010b */ X86_EFL_PF,
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300 | /* 0x73 = 01110011b */ 0,
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301 | /* 0x74 = 01110100b */ X86_EFL_PF,
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302 | /* 0x75 = 01110101b */ 0,
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303 | /* 0x76 = 01110110b */ 0,
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304 | /* 0x77 = 01110111b */ X86_EFL_PF,
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305 | /* 0x78 = 01111000b */ X86_EFL_PF,
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306 | /* 0x79 = 01111001b */ 0,
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307 | /* 0x7a = 01111010b */ 0,
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308 | /* 0x7b = 01111011b */ X86_EFL_PF,
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309 | /* 0x7c = 01111100b */ 0,
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310 | /* 0x7d = 01111101b */ X86_EFL_PF,
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311 | /* 0x7e = 01111110b */ X86_EFL_PF,
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312 | /* 0x7f = 01111111b */ 0,
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313 | /* 0x80 = 10000000b */ 0,
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314 | /* 0x81 = 10000001b */ X86_EFL_PF,
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315 | /* 0x82 = 10000010b */ X86_EFL_PF,
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316 | /* 0x83 = 10000011b */ 0,
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317 | /* 0x84 = 10000100b */ X86_EFL_PF,
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318 | /* 0x85 = 10000101b */ 0,
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319 | /* 0x86 = 10000110b */ 0,
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320 | /* 0x87 = 10000111b */ X86_EFL_PF,
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321 | /* 0x88 = 10001000b */ X86_EFL_PF,
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322 | /* 0x89 = 10001001b */ 0,
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323 | /* 0x8a = 10001010b */ 0,
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324 | /* 0x8b = 10001011b */ X86_EFL_PF,
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325 | /* 0x8c = 10001100b */ 0,
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326 | /* 0x8d = 10001101b */ X86_EFL_PF,
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327 | /* 0x8e = 10001110b */ X86_EFL_PF,
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328 | /* 0x8f = 10001111b */ 0,
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329 | /* 0x90 = 10010000b */ X86_EFL_PF,
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330 | /* 0x91 = 10010001b */ 0,
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331 | /* 0x92 = 10010010b */ 0,
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332 | /* 0x93 = 10010011b */ X86_EFL_PF,
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333 | /* 0x94 = 10010100b */ 0,
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334 | /* 0x95 = 10010101b */ X86_EFL_PF,
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335 | /* 0x96 = 10010110b */ X86_EFL_PF,
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336 | /* 0x97 = 10010111b */ 0,
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337 | /* 0x98 = 10011000b */ 0,
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338 | /* 0x99 = 10011001b */ X86_EFL_PF,
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339 | /* 0x9a = 10011010b */ X86_EFL_PF,
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340 | /* 0x9b = 10011011b */ 0,
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341 | /* 0x9c = 10011100b */ X86_EFL_PF,
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342 | /* 0x9d = 10011101b */ 0,
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343 | /* 0x9e = 10011110b */ 0,
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344 | /* 0x9f = 10011111b */ X86_EFL_PF,
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345 | /* 0xa0 = 10100000b */ X86_EFL_PF,
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346 | /* 0xa1 = 10100001b */ 0,
|
---|
347 | /* 0xa2 = 10100010b */ 0,
|
---|
348 | /* 0xa3 = 10100011b */ X86_EFL_PF,
|
---|
349 | /* 0xa4 = 10100100b */ 0,
|
---|
350 | /* 0xa5 = 10100101b */ X86_EFL_PF,
|
---|
351 | /* 0xa6 = 10100110b */ X86_EFL_PF,
|
---|
352 | /* 0xa7 = 10100111b */ 0,
|
---|
353 | /* 0xa8 = 10101000b */ 0,
|
---|
354 | /* 0xa9 = 10101001b */ X86_EFL_PF,
|
---|
355 | /* 0xaa = 10101010b */ X86_EFL_PF,
|
---|
356 | /* 0xab = 10101011b */ 0,
|
---|
357 | /* 0xac = 10101100b */ X86_EFL_PF,
|
---|
358 | /* 0xad = 10101101b */ 0,
|
---|
359 | /* 0xae = 10101110b */ 0,
|
---|
360 | /* 0xaf = 10101111b */ X86_EFL_PF,
|
---|
361 | /* 0xb0 = 10110000b */ 0,
|
---|
362 | /* 0xb1 = 10110001b */ X86_EFL_PF,
|
---|
363 | /* 0xb2 = 10110010b */ X86_EFL_PF,
|
---|
364 | /* 0xb3 = 10110011b */ 0,
|
---|
365 | /* 0xb4 = 10110100b */ X86_EFL_PF,
|
---|
366 | /* 0xb5 = 10110101b */ 0,
|
---|
367 | /* 0xb6 = 10110110b */ 0,
|
---|
368 | /* 0xb7 = 10110111b */ X86_EFL_PF,
|
---|
369 | /* 0xb8 = 10111000b */ X86_EFL_PF,
|
---|
370 | /* 0xb9 = 10111001b */ 0,
|
---|
371 | /* 0xba = 10111010b */ 0,
|
---|
372 | /* 0xbb = 10111011b */ X86_EFL_PF,
|
---|
373 | /* 0xbc = 10111100b */ 0,
|
---|
374 | /* 0xbd = 10111101b */ X86_EFL_PF,
|
---|
375 | /* 0xbe = 10111110b */ X86_EFL_PF,
|
---|
376 | /* 0xbf = 10111111b */ 0,
|
---|
377 | /* 0xc0 = 11000000b */ X86_EFL_PF,
|
---|
378 | /* 0xc1 = 11000001b */ 0,
|
---|
379 | /* 0xc2 = 11000010b */ 0,
|
---|
380 | /* 0xc3 = 11000011b */ X86_EFL_PF,
|
---|
381 | /* 0xc4 = 11000100b */ 0,
|
---|
382 | /* 0xc5 = 11000101b */ X86_EFL_PF,
|
---|
383 | /* 0xc6 = 11000110b */ X86_EFL_PF,
|
---|
384 | /* 0xc7 = 11000111b */ 0,
|
---|
385 | /* 0xc8 = 11001000b */ 0,
|
---|
386 | /* 0xc9 = 11001001b */ X86_EFL_PF,
|
---|
387 | /* 0xca = 11001010b */ X86_EFL_PF,
|
---|
388 | /* 0xcb = 11001011b */ 0,
|
---|
389 | /* 0xcc = 11001100b */ X86_EFL_PF,
|
---|
390 | /* 0xcd = 11001101b */ 0,
|
---|
391 | /* 0xce = 11001110b */ 0,
|
---|
392 | /* 0xcf = 11001111b */ X86_EFL_PF,
|
---|
393 | /* 0xd0 = 11010000b */ 0,
|
---|
394 | /* 0xd1 = 11010001b */ X86_EFL_PF,
|
---|
395 | /* 0xd2 = 11010010b */ X86_EFL_PF,
|
---|
396 | /* 0xd3 = 11010011b */ 0,
|
---|
397 | /* 0xd4 = 11010100b */ X86_EFL_PF,
|
---|
398 | /* 0xd5 = 11010101b */ 0,
|
---|
399 | /* 0xd6 = 11010110b */ 0,
|
---|
400 | /* 0xd7 = 11010111b */ X86_EFL_PF,
|
---|
401 | /* 0xd8 = 11011000b */ X86_EFL_PF,
|
---|
402 | /* 0xd9 = 11011001b */ 0,
|
---|
403 | /* 0xda = 11011010b */ 0,
|
---|
404 | /* 0xdb = 11011011b */ X86_EFL_PF,
|
---|
405 | /* 0xdc = 11011100b */ 0,
|
---|
406 | /* 0xdd = 11011101b */ X86_EFL_PF,
|
---|
407 | /* 0xde = 11011110b */ X86_EFL_PF,
|
---|
408 | /* 0xdf = 11011111b */ 0,
|
---|
409 | /* 0xe0 = 11100000b */ 0,
|
---|
410 | /* 0xe1 = 11100001b */ X86_EFL_PF,
|
---|
411 | /* 0xe2 = 11100010b */ X86_EFL_PF,
|
---|
412 | /* 0xe3 = 11100011b */ 0,
|
---|
413 | /* 0xe4 = 11100100b */ X86_EFL_PF,
|
---|
414 | /* 0xe5 = 11100101b */ 0,
|
---|
415 | /* 0xe6 = 11100110b */ 0,
|
---|
416 | /* 0xe7 = 11100111b */ X86_EFL_PF,
|
---|
417 | /* 0xe8 = 11101000b */ X86_EFL_PF,
|
---|
418 | /* 0xe9 = 11101001b */ 0,
|
---|
419 | /* 0xea = 11101010b */ 0,
|
---|
420 | /* 0xeb = 11101011b */ X86_EFL_PF,
|
---|
421 | /* 0xec = 11101100b */ 0,
|
---|
422 | /* 0xed = 11101101b */ X86_EFL_PF,
|
---|
423 | /* 0xee = 11101110b */ X86_EFL_PF,
|
---|
424 | /* 0xef = 11101111b */ 0,
|
---|
425 | /* 0xf0 = 11110000b */ X86_EFL_PF,
|
---|
426 | /* 0xf1 = 11110001b */ 0,
|
---|
427 | /* 0xf2 = 11110010b */ 0,
|
---|
428 | /* 0xf3 = 11110011b */ X86_EFL_PF,
|
---|
429 | /* 0xf4 = 11110100b */ 0,
|
---|
430 | /* 0xf5 = 11110101b */ X86_EFL_PF,
|
---|
431 | /* 0xf6 = 11110110b */ X86_EFL_PF,
|
---|
432 | /* 0xf7 = 11110111b */ 0,
|
---|
433 | /* 0xf8 = 11111000b */ 0,
|
---|
434 | /* 0xf9 = 11111001b */ X86_EFL_PF,
|
---|
435 | /* 0xfa = 11111010b */ X86_EFL_PF,
|
---|
436 | /* 0xfb = 11111011b */ 0,
|
---|
437 | /* 0xfc = 11111100b */ X86_EFL_PF,
|
---|
438 | /* 0xfd = 11111101b */ 0,
|
---|
439 | /* 0xfe = 11111110b */ 0,
|
---|
440 | /* 0xff = 11111111b */ X86_EFL_PF,
|
---|
441 | };
|
---|
442 |
|
---|
443 |
|
---|
444 | /*
|
---|
445 | * There are a few 64-bit on 32-bit things we'd rather do in C. Actually, doing
|
---|
446 | * it all in C is probably safer atm., optimize what's necessary later, maybe.
|
---|
447 | */
|
---|
448 | #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
449 |
|
---|
450 |
|
---|
451 | /*********************************************************************************************************************************
|
---|
452 | * Binary Operations *
|
---|
453 | *********************************************************************************************************************************/
|
---|
454 |
|
---|
455 | /*
|
---|
456 | * ADD
|
---|
457 | */
|
---|
458 |
|
---|
459 | IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
460 | {
|
---|
461 | uint64_t uDst = *puDst;
|
---|
462 | uint64_t uResult = uDst + uSrc;
|
---|
463 | *puDst = uResult;
|
---|
464 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult < uDst, uSrc);
|
---|
465 | }
|
---|
466 |
|
---|
467 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
468 |
|
---|
469 | IEM_DECL_IMPL_DEF(void, iemAImpl_add_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
470 | {
|
---|
471 | uint32_t uDst = *puDst;
|
---|
472 | uint32_t uResult = uDst + uSrc;
|
---|
473 | *puDst = uResult;
|
---|
474 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult < uDst, uSrc);
|
---|
475 | }
|
---|
476 |
|
---|
477 |
|
---|
478 | IEM_DECL_IMPL_DEF(void, iemAImpl_add_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
479 | {
|
---|
480 | uint16_t uDst = *puDst;
|
---|
481 | uint16_t uResult = uDst + uSrc;
|
---|
482 | *puDst = uResult;
|
---|
483 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult < uDst, uSrc);
|
---|
484 | }
|
---|
485 |
|
---|
486 |
|
---|
487 | IEM_DECL_IMPL_DEF(void, iemAImpl_add_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
488 | {
|
---|
489 | uint8_t uDst = *puDst;
|
---|
490 | uint8_t uResult = uDst + uSrc;
|
---|
491 | *puDst = uResult;
|
---|
492 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult < uDst, uSrc);
|
---|
493 | }
|
---|
494 |
|
---|
495 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
496 |
|
---|
497 | /*
|
---|
498 | * ADC
|
---|
499 | */
|
---|
500 |
|
---|
501 | IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
502 | {
|
---|
503 | if (!(*pfEFlags & X86_EFL_CF))
|
---|
504 | iemAImpl_add_u64(puDst, uSrc, pfEFlags);
|
---|
505 | else
|
---|
506 | {
|
---|
507 | uint64_t uDst = *puDst;
|
---|
508 | uint64_t uResult = uDst + uSrc + 1;
|
---|
509 | *puDst = uResult;
|
---|
510 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult <= uDst, uSrc);
|
---|
511 | }
|
---|
512 | }
|
---|
513 |
|
---|
514 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
515 |
|
---|
516 | IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
517 | {
|
---|
518 | if (!(*pfEFlags & X86_EFL_CF))
|
---|
519 | iemAImpl_add_u32(puDst, uSrc, pfEFlags);
|
---|
520 | else
|
---|
521 | {
|
---|
522 | uint32_t uDst = *puDst;
|
---|
523 | uint32_t uResult = uDst + uSrc + 1;
|
---|
524 | *puDst = uResult;
|
---|
525 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult <= uDst, uSrc);
|
---|
526 | }
|
---|
527 | }
|
---|
528 |
|
---|
529 |
|
---|
530 | IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
531 | {
|
---|
532 | if (!(*pfEFlags & X86_EFL_CF))
|
---|
533 | iemAImpl_add_u16(puDst, uSrc, pfEFlags);
|
---|
534 | else
|
---|
535 | {
|
---|
536 | uint16_t uDst = *puDst;
|
---|
537 | uint16_t uResult = uDst + uSrc + 1;
|
---|
538 | *puDst = uResult;
|
---|
539 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult <= uDst, uSrc);
|
---|
540 | }
|
---|
541 | }
|
---|
542 |
|
---|
543 |
|
---|
544 | IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
545 | {
|
---|
546 | if (!(*pfEFlags & X86_EFL_CF))
|
---|
547 | iemAImpl_add_u8(puDst, uSrc, pfEFlags);
|
---|
548 | else
|
---|
549 | {
|
---|
550 | uint8_t uDst = *puDst;
|
---|
551 | uint8_t uResult = uDst + uSrc + 1;
|
---|
552 | *puDst = uResult;
|
---|
553 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult <= uDst, uSrc);
|
---|
554 | }
|
---|
555 | }
|
---|
556 |
|
---|
557 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
558 |
|
---|
559 | /*
|
---|
560 | * SUB
|
---|
561 | */
|
---|
562 |
|
---|
563 | IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
564 | {
|
---|
565 | uint64_t uDst = *puDst;
|
---|
566 | uint64_t uResult = uDst - uSrc;
|
---|
567 | *puDst = uResult;
|
---|
568 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst < uSrc, uSrc ^ RT_BIT_64(63));
|
---|
569 | }
|
---|
570 |
|
---|
571 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
572 |
|
---|
573 | IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
574 | {
|
---|
575 | uint32_t uDst = *puDst;
|
---|
576 | uint32_t uResult = uDst - uSrc;
|
---|
577 | *puDst = uResult;
|
---|
578 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst < uSrc, uSrc ^ RT_BIT_32(31));
|
---|
579 | }
|
---|
580 |
|
---|
581 |
|
---|
582 | IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
583 | {
|
---|
584 | uint16_t uDst = *puDst;
|
---|
585 | uint16_t uResult = uDst - uSrc;
|
---|
586 | *puDst = uResult;
|
---|
587 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst < uSrc, uSrc ^ (uint16_t)0x8000);
|
---|
588 | }
|
---|
589 |
|
---|
590 |
|
---|
591 | IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
592 | {
|
---|
593 | uint8_t uDst = *puDst;
|
---|
594 | uint8_t uResult = uDst - uSrc;
|
---|
595 | *puDst = uResult;
|
---|
596 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst < uSrc, uSrc ^ (uint8_t)0x80);
|
---|
597 | }
|
---|
598 |
|
---|
599 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
600 |
|
---|
601 | /*
|
---|
602 | * SBB
|
---|
603 | */
|
---|
604 |
|
---|
605 | IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
606 | {
|
---|
607 | if (!(*pfEFlags & X86_EFL_CF))
|
---|
608 | iemAImpl_sub_u64(puDst, uSrc, pfEFlags);
|
---|
609 | else
|
---|
610 | {
|
---|
611 | uint64_t uDst = *puDst;
|
---|
612 | uint64_t uResult = uDst - uSrc - 1;
|
---|
613 | *puDst = uResult;
|
---|
614 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst <= uSrc, uSrc ^ RT_BIT_64(63));
|
---|
615 | }
|
---|
616 | }
|
---|
617 |
|
---|
618 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
619 |
|
---|
620 | IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
621 | {
|
---|
622 | if (!(*pfEFlags & X86_EFL_CF))
|
---|
623 | iemAImpl_sub_u32(puDst, uSrc, pfEFlags);
|
---|
624 | else
|
---|
625 | {
|
---|
626 | uint32_t uDst = *puDst;
|
---|
627 | uint32_t uResult = uDst - uSrc - 1;
|
---|
628 | *puDst = uResult;
|
---|
629 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst <= uSrc, uSrc ^ RT_BIT_32(31));
|
---|
630 | }
|
---|
631 | }
|
---|
632 |
|
---|
633 |
|
---|
634 | IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
635 | {
|
---|
636 | if (!(*pfEFlags & X86_EFL_CF))
|
---|
637 | iemAImpl_sub_u16(puDst, uSrc, pfEFlags);
|
---|
638 | else
|
---|
639 | {
|
---|
640 | uint16_t uDst = *puDst;
|
---|
641 | uint16_t uResult = uDst - uSrc - 1;
|
---|
642 | *puDst = uResult;
|
---|
643 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst <= uSrc, uSrc ^ (uint16_t)0x8000);
|
---|
644 | }
|
---|
645 | }
|
---|
646 |
|
---|
647 |
|
---|
648 | IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
649 | {
|
---|
650 | if (!(*pfEFlags & X86_EFL_CF))
|
---|
651 | iemAImpl_sub_u8(puDst, uSrc, pfEFlags);
|
---|
652 | else
|
---|
653 | {
|
---|
654 | uint8_t uDst = *puDst;
|
---|
655 | uint8_t uResult = uDst - uSrc - 1;
|
---|
656 | *puDst = uResult;
|
---|
657 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst <= uSrc, uSrc ^ (uint8_t)0x80);
|
---|
658 | }
|
---|
659 | }
|
---|
660 |
|
---|
661 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
662 |
|
---|
663 |
|
---|
664 | /*
|
---|
665 | * OR
|
---|
666 | */
|
---|
667 |
|
---|
668 | IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
669 | {
|
---|
670 | uint64_t uResult = *puDst | uSrc;
|
---|
671 | *puDst = uResult;
|
---|
672 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
|
---|
673 | }
|
---|
674 |
|
---|
675 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
676 |
|
---|
677 | IEM_DECL_IMPL_DEF(void, iemAImpl_or_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
678 | {
|
---|
679 | uint32_t uResult = *puDst | uSrc;
|
---|
680 | *puDst = uResult;
|
---|
681 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
|
---|
682 | }
|
---|
683 |
|
---|
684 |
|
---|
685 | IEM_DECL_IMPL_DEF(void, iemAImpl_or_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
686 | {
|
---|
687 | uint16_t uResult = *puDst | uSrc;
|
---|
688 | *puDst = uResult;
|
---|
689 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
|
---|
690 | }
|
---|
691 |
|
---|
692 |
|
---|
693 | IEM_DECL_IMPL_DEF(void, iemAImpl_or_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
694 | {
|
---|
695 | uint8_t uResult = *puDst | uSrc;
|
---|
696 | *puDst = uResult;
|
---|
697 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
|
---|
698 | }
|
---|
699 |
|
---|
700 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
701 |
|
---|
702 | /*
|
---|
703 | * XOR
|
---|
704 | */
|
---|
705 |
|
---|
706 | IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
707 | {
|
---|
708 | uint64_t uResult = *puDst ^ uSrc;
|
---|
709 | *puDst = uResult;
|
---|
710 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
|
---|
711 | }
|
---|
712 |
|
---|
713 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
714 |
|
---|
715 | IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
716 | {
|
---|
717 | uint32_t uResult = *puDst ^ uSrc;
|
---|
718 | *puDst = uResult;
|
---|
719 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
|
---|
720 | }
|
---|
721 |
|
---|
722 |
|
---|
723 | IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
724 | {
|
---|
725 | uint16_t uResult = *puDst ^ uSrc;
|
---|
726 | *puDst = uResult;
|
---|
727 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
|
---|
728 | }
|
---|
729 |
|
---|
730 |
|
---|
731 | IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
732 | {
|
---|
733 | uint8_t uResult = *puDst ^ uSrc;
|
---|
734 | *puDst = uResult;
|
---|
735 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
|
---|
736 | }
|
---|
737 |
|
---|
738 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
739 |
|
---|
740 | /*
|
---|
741 | * AND
|
---|
742 | */
|
---|
743 |
|
---|
744 | IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
745 | {
|
---|
746 | uint64_t uResult = *puDst & uSrc;
|
---|
747 | *puDst = uResult;
|
---|
748 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
|
---|
749 | }
|
---|
750 |
|
---|
751 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
752 |
|
---|
753 | IEM_DECL_IMPL_DEF(void, iemAImpl_and_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
754 | {
|
---|
755 | uint32_t uResult = *puDst & uSrc;
|
---|
756 | *puDst = uResult;
|
---|
757 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
|
---|
758 | }
|
---|
759 |
|
---|
760 |
|
---|
761 | IEM_DECL_IMPL_DEF(void, iemAImpl_and_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
762 | {
|
---|
763 | uint16_t uResult = *puDst & uSrc;
|
---|
764 | *puDst = uResult;
|
---|
765 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
|
---|
766 | }
|
---|
767 |
|
---|
768 |
|
---|
769 | IEM_DECL_IMPL_DEF(void, iemAImpl_and_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
770 | {
|
---|
771 | uint8_t uResult = *puDst & uSrc;
|
---|
772 | *puDst = uResult;
|
---|
773 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
|
---|
774 | }
|
---|
775 |
|
---|
776 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
777 |
|
---|
778 | /*
|
---|
779 | * CMP
|
---|
780 | */
|
---|
781 |
|
---|
782 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
783 | {
|
---|
784 | uint64_t uDstTmp = *puDst;
|
---|
785 | iemAImpl_sub_u64(&uDstTmp, uSrc, pfEFlags);
|
---|
786 | }
|
---|
787 |
|
---|
788 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
789 |
|
---|
790 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
791 | {
|
---|
792 | uint32_t uDstTmp = *puDst;
|
---|
793 | iemAImpl_sub_u32(&uDstTmp, uSrc, pfEFlags);
|
---|
794 | }
|
---|
795 |
|
---|
796 |
|
---|
797 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
798 | {
|
---|
799 | uint16_t uDstTmp = *puDst;
|
---|
800 | iemAImpl_sub_u16(&uDstTmp, uSrc, pfEFlags);
|
---|
801 | }
|
---|
802 |
|
---|
803 |
|
---|
804 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
805 | {
|
---|
806 | uint8_t uDstTmp = *puDst;
|
---|
807 | iemAImpl_sub_u8(&uDstTmp, uSrc, pfEFlags);
|
---|
808 | }
|
---|
809 |
|
---|
810 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
811 |
|
---|
812 | /*
|
---|
813 | * TEST
|
---|
814 | */
|
---|
815 |
|
---|
816 | IEM_DECL_IMPL_DEF(void, iemAImpl_test_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
817 | {
|
---|
818 | uint64_t uResult = *puDst & uSrc;
|
---|
819 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
|
---|
820 | }
|
---|
821 |
|
---|
822 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
823 |
|
---|
824 | IEM_DECL_IMPL_DEF(void, iemAImpl_test_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
825 | {
|
---|
826 | uint32_t uResult = *puDst & uSrc;
|
---|
827 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
|
---|
828 | }
|
---|
829 |
|
---|
830 |
|
---|
831 | IEM_DECL_IMPL_DEF(void, iemAImpl_test_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
832 | {
|
---|
833 | uint16_t uResult = *puDst & uSrc;
|
---|
834 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
|
---|
835 | }
|
---|
836 |
|
---|
837 |
|
---|
838 | IEM_DECL_IMPL_DEF(void, iemAImpl_test_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
|
---|
839 | {
|
---|
840 | uint8_t uResult = *puDst & uSrc;
|
---|
841 | IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
|
---|
842 | }
|
---|
843 |
|
---|
844 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
845 |
|
---|
846 |
|
---|
847 | /*
|
---|
848 | * LOCK prefixed variants of the above
|
---|
849 | */
|
---|
850 |
|
---|
851 | /** 64-bit locked binary operand operation. */
|
---|
852 | # define DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
|
---|
853 | do { \
|
---|
854 | uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
|
---|
855 | uint ## a_cBitsWidth ## _t uTmp; \
|
---|
856 | uint32_t fEflTmp; \
|
---|
857 | do \
|
---|
858 | { \
|
---|
859 | uTmp = uOld; \
|
---|
860 | fEflTmp = *pfEFlags; \
|
---|
861 | iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, uSrc, &fEflTmp); \
|
---|
862 | } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
|
---|
863 | *pfEFlags = fEflTmp; \
|
---|
864 | } while (0)
|
---|
865 |
|
---|
866 |
|
---|
867 | #define EMIT_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
|
---|
868 | IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
|
---|
869 | uint ## a_cBitsWidth ## _t uSrc, \
|
---|
870 | uint32_t *pfEFlags)) \
|
---|
871 | { \
|
---|
872 | DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth); \
|
---|
873 | }
|
---|
874 |
|
---|
875 | EMIT_LOCKED_BIN_OP(add, 64)
|
---|
876 | EMIT_LOCKED_BIN_OP(adc, 64)
|
---|
877 | EMIT_LOCKED_BIN_OP(sub, 64)
|
---|
878 | EMIT_LOCKED_BIN_OP(sbb, 64)
|
---|
879 | EMIT_LOCKED_BIN_OP(or, 64)
|
---|
880 | EMIT_LOCKED_BIN_OP(xor, 64)
|
---|
881 | EMIT_LOCKED_BIN_OP(and, 64)
|
---|
882 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
883 | EMIT_LOCKED_BIN_OP(add, 32)
|
---|
884 | EMIT_LOCKED_BIN_OP(adc, 32)
|
---|
885 | EMIT_LOCKED_BIN_OP(sub, 32)
|
---|
886 | EMIT_LOCKED_BIN_OP(sbb, 32)
|
---|
887 | EMIT_LOCKED_BIN_OP(or, 32)
|
---|
888 | EMIT_LOCKED_BIN_OP(xor, 32)
|
---|
889 | EMIT_LOCKED_BIN_OP(and, 32)
|
---|
890 |
|
---|
891 | EMIT_LOCKED_BIN_OP(add, 16)
|
---|
892 | EMIT_LOCKED_BIN_OP(adc, 16)
|
---|
893 | EMIT_LOCKED_BIN_OP(sub, 16)
|
---|
894 | EMIT_LOCKED_BIN_OP(sbb, 16)
|
---|
895 | EMIT_LOCKED_BIN_OP(or, 16)
|
---|
896 | EMIT_LOCKED_BIN_OP(xor, 16)
|
---|
897 | EMIT_LOCKED_BIN_OP(and, 16)
|
---|
898 |
|
---|
899 | EMIT_LOCKED_BIN_OP(add, 8)
|
---|
900 | EMIT_LOCKED_BIN_OP(adc, 8)
|
---|
901 | EMIT_LOCKED_BIN_OP(sub, 8)
|
---|
902 | EMIT_LOCKED_BIN_OP(sbb, 8)
|
---|
903 | EMIT_LOCKED_BIN_OP(or, 8)
|
---|
904 | EMIT_LOCKED_BIN_OP(xor, 8)
|
---|
905 | EMIT_LOCKED_BIN_OP(and, 8)
|
---|
906 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
907 |
|
---|
908 |
|
---|
909 | /*
|
---|
910 | * Bit operations (same signature as above).
|
---|
911 | */
|
---|
912 |
|
---|
913 | /*
|
---|
914 | * BT
|
---|
915 | */
|
---|
916 |
|
---|
917 | IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
918 | {
|
---|
919 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
|
---|
920 | not modified by either AMD (3990x) or Intel (i9-9980HK). */
|
---|
921 | Assert(uSrc < 64);
|
---|
922 | uint64_t uDst = *puDst;
|
---|
923 | if (uDst & RT_BIT_64(uSrc))
|
---|
924 | *pfEFlags |= X86_EFL_CF;
|
---|
925 | else
|
---|
926 | *pfEFlags &= ~X86_EFL_CF;
|
---|
927 | }
|
---|
928 |
|
---|
929 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
930 |
|
---|
931 | IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
932 | {
|
---|
933 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
|
---|
934 | not modified by either AMD (3990x) or Intel (i9-9980HK). */
|
---|
935 | Assert(uSrc < 32);
|
---|
936 | uint32_t uDst = *puDst;
|
---|
937 | if (uDst & RT_BIT_32(uSrc))
|
---|
938 | *pfEFlags |= X86_EFL_CF;
|
---|
939 | else
|
---|
940 | *pfEFlags &= ~X86_EFL_CF;
|
---|
941 | }
|
---|
942 |
|
---|
943 | IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
944 | {
|
---|
945 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
|
---|
946 | not modified by either AMD (3990x) or Intel (i9-9980HK). */
|
---|
947 | Assert(uSrc < 16);
|
---|
948 | uint16_t uDst = *puDst;
|
---|
949 | if (uDst & RT_BIT_32(uSrc))
|
---|
950 | *pfEFlags |= X86_EFL_CF;
|
---|
951 | else
|
---|
952 | *pfEFlags &= ~X86_EFL_CF;
|
---|
953 | }
|
---|
954 |
|
---|
955 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
956 |
|
---|
957 | /*
|
---|
958 | * BTC
|
---|
959 | */
|
---|
960 |
|
---|
961 | IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
962 | {
|
---|
963 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
|
---|
964 | not modified by either AMD (3990x) or Intel (i9-9980HK). */
|
---|
965 | Assert(uSrc < 64);
|
---|
966 | uint64_t fMask = RT_BIT_64(uSrc);
|
---|
967 | uint64_t uDst = *puDst;
|
---|
968 | if (uDst & fMask)
|
---|
969 | {
|
---|
970 | uDst &= ~fMask;
|
---|
971 | *puDst = uDst;
|
---|
972 | *pfEFlags |= X86_EFL_CF;
|
---|
973 | }
|
---|
974 | else
|
---|
975 | {
|
---|
976 | uDst |= fMask;
|
---|
977 | *puDst = uDst;
|
---|
978 | *pfEFlags &= ~X86_EFL_CF;
|
---|
979 | }
|
---|
980 | }
|
---|
981 |
|
---|
982 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
983 |
|
---|
984 | IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
985 | {
|
---|
986 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
|
---|
987 | not modified by either AMD (3990x) or Intel (i9-9980HK). */
|
---|
988 | Assert(uSrc < 32);
|
---|
989 | uint32_t fMask = RT_BIT_32(uSrc);
|
---|
990 | uint32_t uDst = *puDst;
|
---|
991 | if (uDst & fMask)
|
---|
992 | {
|
---|
993 | uDst &= ~fMask;
|
---|
994 | *puDst = uDst;
|
---|
995 | *pfEFlags |= X86_EFL_CF;
|
---|
996 | }
|
---|
997 | else
|
---|
998 | {
|
---|
999 | uDst |= fMask;
|
---|
1000 | *puDst = uDst;
|
---|
1001 | *pfEFlags &= ~X86_EFL_CF;
|
---|
1002 | }
|
---|
1003 | }
|
---|
1004 |
|
---|
1005 |
|
---|
1006 | IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1007 | {
|
---|
1008 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
|
---|
1009 | not modified by either AMD (3990x) or Intel (i9-9980HK). */
|
---|
1010 | Assert(uSrc < 16);
|
---|
1011 | uint16_t fMask = RT_BIT_32(uSrc);
|
---|
1012 | uint16_t uDst = *puDst;
|
---|
1013 | if (uDst & fMask)
|
---|
1014 | {
|
---|
1015 | uDst &= ~fMask;
|
---|
1016 | *puDst = uDst;
|
---|
1017 | *pfEFlags |= X86_EFL_CF;
|
---|
1018 | }
|
---|
1019 | else
|
---|
1020 | {
|
---|
1021 | uDst |= fMask;
|
---|
1022 | *puDst = uDst;
|
---|
1023 | *pfEFlags &= ~X86_EFL_CF;
|
---|
1024 | }
|
---|
1025 | }
|
---|
1026 |
|
---|
1027 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1028 |
|
---|
1029 | /*
|
---|
1030 | * BTR
|
---|
1031 | */
|
---|
1032 |
|
---|
1033 | IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
1034 | {
|
---|
1035 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
|
---|
1036 | logical operation (AND/OR/whatever). */
|
---|
1037 | Assert(uSrc < 64);
|
---|
1038 | uint64_t fMask = RT_BIT_64(uSrc);
|
---|
1039 | uint64_t uDst = *puDst;
|
---|
1040 | if (uDst & fMask)
|
---|
1041 | {
|
---|
1042 | uDst &= ~fMask;
|
---|
1043 | *puDst = uDst;
|
---|
1044 | *pfEFlags |= X86_EFL_CF;
|
---|
1045 | }
|
---|
1046 | else
|
---|
1047 | *pfEFlags &= ~X86_EFL_CF;
|
---|
1048 | }
|
---|
1049 |
|
---|
1050 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1051 |
|
---|
1052 | IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
1053 | {
|
---|
1054 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
|
---|
1055 | logical operation (AND/OR/whatever). */
|
---|
1056 | Assert(uSrc < 32);
|
---|
1057 | uint32_t fMask = RT_BIT_32(uSrc);
|
---|
1058 | uint32_t uDst = *puDst;
|
---|
1059 | if (uDst & fMask)
|
---|
1060 | {
|
---|
1061 | uDst &= ~fMask;
|
---|
1062 | *puDst = uDst;
|
---|
1063 | *pfEFlags |= X86_EFL_CF;
|
---|
1064 | }
|
---|
1065 | else
|
---|
1066 | *pfEFlags &= ~X86_EFL_CF;
|
---|
1067 | }
|
---|
1068 |
|
---|
1069 |
|
---|
1070 | IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1071 | {
|
---|
1072 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
|
---|
1073 | logical operation (AND/OR/whatever). */
|
---|
1074 | Assert(uSrc < 16);
|
---|
1075 | uint16_t fMask = RT_BIT_32(uSrc);
|
---|
1076 | uint16_t uDst = *puDst;
|
---|
1077 | if (uDst & fMask)
|
---|
1078 | {
|
---|
1079 | uDst &= ~fMask;
|
---|
1080 | *puDst = uDst;
|
---|
1081 | *pfEFlags |= X86_EFL_CF;
|
---|
1082 | }
|
---|
1083 | else
|
---|
1084 | *pfEFlags &= ~X86_EFL_CF;
|
---|
1085 | }
|
---|
1086 |
|
---|
1087 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1088 |
|
---|
1089 | /*
|
---|
1090 | * BTS
|
---|
1091 | */
|
---|
1092 |
|
---|
1093 | IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
1094 | {
|
---|
1095 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
|
---|
1096 | logical operation (AND/OR/whatever). */
|
---|
1097 | Assert(uSrc < 64);
|
---|
1098 | uint64_t fMask = RT_BIT_64(uSrc);
|
---|
1099 | uint64_t uDst = *puDst;
|
---|
1100 | if (uDst & fMask)
|
---|
1101 | *pfEFlags |= X86_EFL_CF;
|
---|
1102 | else
|
---|
1103 | {
|
---|
1104 | uDst |= fMask;
|
---|
1105 | *puDst = uDst;
|
---|
1106 | *pfEFlags &= ~X86_EFL_CF;
|
---|
1107 | }
|
---|
1108 | }
|
---|
1109 |
|
---|
1110 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1111 |
|
---|
1112 | IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
1113 | {
|
---|
1114 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
|
---|
1115 | logical operation (AND/OR/whatever). */
|
---|
1116 | Assert(uSrc < 32);
|
---|
1117 | uint32_t fMask = RT_BIT_32(uSrc);
|
---|
1118 | uint32_t uDst = *puDst;
|
---|
1119 | if (uDst & fMask)
|
---|
1120 | *pfEFlags |= X86_EFL_CF;
|
---|
1121 | else
|
---|
1122 | {
|
---|
1123 | uDst |= fMask;
|
---|
1124 | *puDst = uDst;
|
---|
1125 | *pfEFlags &= ~X86_EFL_CF;
|
---|
1126 | }
|
---|
1127 | }
|
---|
1128 |
|
---|
1129 |
|
---|
1130 | IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1131 | {
|
---|
1132 | /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
|
---|
1133 | logical operation (AND/OR/whatever). */
|
---|
1134 | Assert(uSrc < 16);
|
---|
1135 | uint16_t fMask = RT_BIT_32(uSrc);
|
---|
1136 | uint32_t uDst = *puDst;
|
---|
1137 | if (uDst & fMask)
|
---|
1138 | *pfEFlags |= X86_EFL_CF;
|
---|
1139 | else
|
---|
1140 | {
|
---|
1141 | uDst |= fMask;
|
---|
1142 | *puDst = uDst;
|
---|
1143 | *pfEFlags &= ~X86_EFL_CF;
|
---|
1144 | }
|
---|
1145 | }
|
---|
1146 |
|
---|
1147 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1148 |
|
---|
1149 |
|
---|
1150 | EMIT_LOCKED_BIN_OP(btc, 64)
|
---|
1151 | EMIT_LOCKED_BIN_OP(btr, 64)
|
---|
1152 | EMIT_LOCKED_BIN_OP(bts, 64)
|
---|
1153 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1154 | EMIT_LOCKED_BIN_OP(btc, 32)
|
---|
1155 | EMIT_LOCKED_BIN_OP(btr, 32)
|
---|
1156 | EMIT_LOCKED_BIN_OP(bts, 32)
|
---|
1157 |
|
---|
1158 | EMIT_LOCKED_BIN_OP(btc, 16)
|
---|
1159 | EMIT_LOCKED_BIN_OP(btr, 16)
|
---|
1160 | EMIT_LOCKED_BIN_OP(bts, 16)
|
---|
1161 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1162 |
|
---|
1163 |
|
---|
1164 | /*
|
---|
1165 | * Helpers for BSR and BSF.
|
---|
1166 | *
|
---|
1167 | * Note! "undefined" flags: OF, SF, AF, PF, CF.
|
---|
1168 | * Intel behavior modelled on 10980xe, AMD on 3990X. Other marchs may
|
---|
1169 | * produce different result (see https://www.sandpile.org/x86/flags.htm),
|
---|
1170 | * but we restrict ourselves to emulating these recent marchs.
|
---|
1171 | */
|
---|
1172 | #define SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlag, a_iBit) do { \
|
---|
1173 | unsigned iBit = (a_iBit); \
|
---|
1174 | uint32_t fEfl = *pfEFlags & ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \
|
---|
1175 | if (iBit) \
|
---|
1176 | { \
|
---|
1177 | *puDst = --iBit; \
|
---|
1178 | fEfl |= g_afParity[iBit]; \
|
---|
1179 | } \
|
---|
1180 | else \
|
---|
1181 | fEfl |= X86_EFL_ZF | X86_EFL_PF; \
|
---|
1182 | *pfEFlags = fEfl; \
|
---|
1183 | } while (0)
|
---|
1184 | #define SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlag, a_iBit) do { \
|
---|
1185 | unsigned const iBit = (a_iBit); \
|
---|
1186 | if (iBit) \
|
---|
1187 | { \
|
---|
1188 | *puDst = iBit - 1; \
|
---|
1189 | *pfEFlags &= ~X86_EFL_ZF; \
|
---|
1190 | } \
|
---|
1191 | else \
|
---|
1192 | *pfEFlags |= X86_EFL_ZF; \
|
---|
1193 | } while (0)
|
---|
1194 |
|
---|
1195 |
|
---|
1196 | /*
|
---|
1197 | * BSF - first (least significant) bit set
|
---|
1198 | */
|
---|
1199 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
1200 | {
|
---|
1201 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
|
---|
1202 | }
|
---|
1203 |
|
---|
1204 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64_intel,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
1205 | {
|
---|
1206 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
|
---|
1207 | }
|
---|
1208 |
|
---|
1209 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64_amd,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
1210 | {
|
---|
1211 | SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
|
---|
1212 | }
|
---|
1213 |
|
---|
1214 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1215 |
|
---|
1216 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
1217 | {
|
---|
1218 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
|
---|
1219 | }
|
---|
1220 |
|
---|
1221 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32_intel,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
1222 | {
|
---|
1223 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
|
---|
1224 | }
|
---|
1225 |
|
---|
1226 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32_amd,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
1227 | {
|
---|
1228 | SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
|
---|
1229 | }
|
---|
1230 |
|
---|
1231 |
|
---|
1232 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1233 | {
|
---|
1234 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
|
---|
1235 | }
|
---|
1236 |
|
---|
1237 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16_intel,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1238 | {
|
---|
1239 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
|
---|
1240 | }
|
---|
1241 |
|
---|
1242 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16_amd,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1243 | {
|
---|
1244 | SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
|
---|
1245 | }
|
---|
1246 |
|
---|
1247 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1248 |
|
---|
1249 |
|
---|
1250 | /*
|
---|
1251 | * BSR - last (most significant) bit set
|
---|
1252 | */
|
---|
1253 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
1254 | {
|
---|
1255 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
|
---|
1256 | }
|
---|
1257 |
|
---|
1258 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64_intel,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
1259 | {
|
---|
1260 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
|
---|
1261 | }
|
---|
1262 |
|
---|
1263 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64_amd,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
|
---|
1264 | {
|
---|
1265 | SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
|
---|
1266 | }
|
---|
1267 |
|
---|
1268 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1269 |
|
---|
1270 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
1271 | {
|
---|
1272 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
|
---|
1273 | }
|
---|
1274 |
|
---|
1275 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32_intel,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
1276 | {
|
---|
1277 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
|
---|
1278 | }
|
---|
1279 |
|
---|
1280 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32_amd,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
|
---|
1281 | {
|
---|
1282 | SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
|
---|
1283 | }
|
---|
1284 |
|
---|
1285 |
|
---|
1286 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1287 | {
|
---|
1288 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
|
---|
1289 | }
|
---|
1290 |
|
---|
1291 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16_intel,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1292 | {
|
---|
1293 | SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
|
---|
1294 | }
|
---|
1295 |
|
---|
1296 | IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16_amd,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
|
---|
1297 | {
|
---|
1298 | SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
|
---|
1299 | }
|
---|
1300 |
|
---|
1301 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1302 |
|
---|
1303 |
|
---|
1304 | /*
|
---|
1305 | * XCHG
|
---|
1306 | */
|
---|
1307 |
|
---|
1308 | IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t *puMem, uint64_t *puReg))
|
---|
1309 | {
|
---|
1310 | #if ARCH_BITS >= 64
|
---|
1311 | *puReg = ASMAtomicXchgU64(puMem, *puReg);
|
---|
1312 | #else
|
---|
1313 | uint64_t uOldMem = *puMem;
|
---|
1314 | while (!ASMAtomicCmpXchgExU64(puMem, *puReg, uOldMem, &uOldMem))
|
---|
1315 | ASMNopPause();
|
---|
1316 | *puReg = uOldMem;
|
---|
1317 | #endif
|
---|
1318 | }
|
---|
1319 |
|
---|
1320 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1321 |
|
---|
1322 | IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t *puMem, uint32_t *puReg))
|
---|
1323 | {
|
---|
1324 | *puReg = ASMAtomicXchgU32(puMem, *puReg);
|
---|
1325 | }
|
---|
1326 |
|
---|
1327 |
|
---|
1328 | IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t *puMem, uint16_t *puReg))
|
---|
1329 | {
|
---|
1330 | *puReg = ASMAtomicXchgU16(puMem, *puReg);
|
---|
1331 | }
|
---|
1332 |
|
---|
1333 |
|
---|
1334 | IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked,(uint8_t *puMem, uint8_t *puReg))
|
---|
1335 | {
|
---|
1336 | *puReg = ASMAtomicXchgU8(puMem, *puReg);
|
---|
1337 | }
|
---|
1338 |
|
---|
1339 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1340 |
|
---|
1341 |
|
---|
1342 | /* Unlocked variants for fDisregardLock mode: */
|
---|
1343 |
|
---|
1344 | IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t *puMem, uint64_t *puReg))
|
---|
1345 | {
|
---|
1346 | uint64_t const uOld = *puMem;
|
---|
1347 | *puMem = *puReg;
|
---|
1348 | *puReg = uOld;
|
---|
1349 | }
|
---|
1350 |
|
---|
1351 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1352 |
|
---|
1353 | IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t *puMem, uint32_t *puReg))
|
---|
1354 | {
|
---|
1355 | uint32_t const uOld = *puMem;
|
---|
1356 | *puMem = *puReg;
|
---|
1357 | *puReg = uOld;
|
---|
1358 | }
|
---|
1359 |
|
---|
1360 |
|
---|
1361 | IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t *puMem, uint16_t *puReg))
|
---|
1362 | {
|
---|
1363 | uint16_t const uOld = *puMem;
|
---|
1364 | *puMem = *puReg;
|
---|
1365 | *puReg = uOld;
|
---|
1366 | }
|
---|
1367 |
|
---|
1368 |
|
---|
1369 | IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked,(uint8_t *puMem, uint8_t *puReg))
|
---|
1370 | {
|
---|
1371 | uint8_t const uOld = *puMem;
|
---|
1372 | *puMem = *puReg;
|
---|
1373 | *puReg = uOld;
|
---|
1374 | }
|
---|
1375 |
|
---|
1376 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1377 |
|
---|
1378 |
|
---|
1379 | /*
|
---|
1380 | * XADD and LOCK XADD.
|
---|
1381 | */
|
---|
1382 | #define EMIT_XADD(a_cBitsWidth, a_Type) \
|
---|
1383 | IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u ## a_cBitsWidth,(a_Type *puDst, a_Type *puReg, uint32_t *pfEFlags)) \
|
---|
1384 | { \
|
---|
1385 | a_Type uDst = *puDst; \
|
---|
1386 | a_Type uResult = uDst; \
|
---|
1387 | iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, pfEFlags); \
|
---|
1388 | *puDst = uResult; \
|
---|
1389 | *puReg = uDst; \
|
---|
1390 | } \
|
---|
1391 | \
|
---|
1392 | IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u ## a_cBitsWidth ## _locked,(a_Type *puDst, a_Type *puReg, uint32_t *pfEFlags)) \
|
---|
1393 | { \
|
---|
1394 | a_Type uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
|
---|
1395 | a_Type uResult; \
|
---|
1396 | uint32_t fEflTmp; \
|
---|
1397 | do \
|
---|
1398 | { \
|
---|
1399 | uResult = uOld; \
|
---|
1400 | fEflTmp = *pfEFlags; \
|
---|
1401 | iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, &fEflTmp); \
|
---|
1402 | } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uResult, uOld, &uOld)); \
|
---|
1403 | *puReg = uOld; \
|
---|
1404 | *pfEFlags = fEflTmp; \
|
---|
1405 | }
|
---|
1406 | EMIT_XADD(64, uint64_t)
|
---|
1407 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1408 | EMIT_XADD(32, uint32_t)
|
---|
1409 | EMIT_XADD(16, uint16_t)
|
---|
1410 | EMIT_XADD(8, uint8_t)
|
---|
1411 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1412 |
|
---|
1413 | #endif
|
---|
1414 |
|
---|
1415 | /*
|
---|
1416 | * CMPXCHG, CMPXCHG8B, CMPXCHG16B
|
---|
1417 | *
|
---|
1418 | * Note! We don't have non-locking/atomic cmpxchg primitives, so all cmpxchg
|
---|
1419 | * instructions are emulated as locked.
|
---|
1420 | */
|
---|
1421 | #if defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1422 |
|
---|
1423 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags))
|
---|
1424 | {
|
---|
1425 | uint8_t uOld = *puAl;
|
---|
1426 | if (ASMAtomicCmpXchgExU8(pu8Dst, uSrcReg, uOld, puAl))
|
---|
1427 | Assert(*puAl == uOld);
|
---|
1428 | iemAImpl_cmp_u8(&uOld, *puAl, pEFlags);
|
---|
1429 | }
|
---|
1430 |
|
---|
1431 |
|
---|
1432 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags))
|
---|
1433 | {
|
---|
1434 | uint16_t uOld = *puAx;
|
---|
1435 | if (ASMAtomicCmpXchgExU16(pu16Dst, uSrcReg, uOld, puAx))
|
---|
1436 | Assert(*puAx == uOld);
|
---|
1437 | iemAImpl_cmp_u16(&uOld, *puAx, pEFlags);
|
---|
1438 | }
|
---|
1439 |
|
---|
1440 |
|
---|
1441 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags))
|
---|
1442 | {
|
---|
1443 | uint32_t uOld = *puEax;
|
---|
1444 | if (ASMAtomicCmpXchgExU32(pu32Dst, uSrcReg, uOld, puEax))
|
---|
1445 | Assert(*puEax == uOld);
|
---|
1446 | iemAImpl_cmp_u32(&uOld, *puEax, pEFlags);
|
---|
1447 | }
|
---|
1448 |
|
---|
1449 |
|
---|
1450 | # if ARCH_BITS == 32
|
---|
1451 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags))
|
---|
1452 | # else
|
---|
1453 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags))
|
---|
1454 | # endif
|
---|
1455 | {
|
---|
1456 | # if ARCH_BITS == 32
|
---|
1457 | uint64_t const uSrcReg = *puSrcReg;
|
---|
1458 | # endif
|
---|
1459 | uint64_t uOld = *puRax;
|
---|
1460 | if (ASMAtomicCmpXchgExU64(pu64Dst, uSrcReg, uOld, puRax))
|
---|
1461 | Assert(*puRax == uOld);
|
---|
1462 | iemAImpl_cmp_u64(&uOld, *puRax, pEFlags);
|
---|
1463 | }
|
---|
1464 |
|
---|
1465 |
|
---|
1466 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
|
---|
1467 | uint32_t *pEFlags))
|
---|
1468 | {
|
---|
1469 | uint64_t const uNew = pu64EbxEcx->u;
|
---|
1470 | uint64_t const uOld = pu64EaxEdx->u;
|
---|
1471 | if (ASMAtomicCmpXchgExU64(pu64Dst, uNew, uOld, &pu64EaxEdx->u))
|
---|
1472 | {
|
---|
1473 | Assert(pu64EaxEdx->u == uOld);
|
---|
1474 | *pEFlags |= X86_EFL_ZF;
|
---|
1475 | }
|
---|
1476 | else
|
---|
1477 | *pEFlags &= ~X86_EFL_ZF;
|
---|
1478 | }
|
---|
1479 |
|
---|
1480 |
|
---|
1481 | # if defined(RT_ARCH_AMD64) || defined(RT_ARCH_ARM64)
|
---|
1482 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
|
---|
1483 | uint32_t *pEFlags))
|
---|
1484 | {
|
---|
1485 | # ifdef VBOX_STRICT
|
---|
1486 | RTUINT128U const uOld = *pu128RaxRdx;
|
---|
1487 | # endif
|
---|
1488 | # if defined(RT_ARCH_AMD64)
|
---|
1489 | if (ASMAtomicCmpXchgU128v2(&pu128Dst->u, pu128RbxRcx->s.Hi, pu128RbxRcx->s.Lo, pu128RaxRdx->s.Hi, pu128RaxRdx->s.Lo,
|
---|
1490 | &pu128RaxRdx->u))
|
---|
1491 | # else
|
---|
1492 | if (ASMAtomicCmpXchgU128(&pu128Dst->u, pu128RbxRcx->u, pu128RaxRdx->u, &pu128RaxRdx->u))
|
---|
1493 | # endif
|
---|
1494 | {
|
---|
1495 | Assert(pu128RaxRdx->s.Lo == uOld.s.Lo && pu128RaxRdx->s.Hi == uOld.s.Hi);
|
---|
1496 | *pEFlags |= X86_EFL_ZF;
|
---|
1497 | }
|
---|
1498 | else
|
---|
1499 | *pEFlags &= ~X86_EFL_ZF;
|
---|
1500 | }
|
---|
1501 | # endif
|
---|
1502 |
|
---|
1503 | #endif /* defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1504 |
|
---|
1505 | # if !defined(RT_ARCH_ARM64) /** @todo may need this for unaligned accesses... */
|
---|
1506 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
|
---|
1507 | PRTUINT128U pu128RbxRcx, uint32_t *pEFlags))
|
---|
1508 | {
|
---|
1509 | RTUINT128U u128Tmp = *pu128Dst;
|
---|
1510 | if ( u128Tmp.s.Lo == pu128RaxRdx->s.Lo
|
---|
1511 | && u128Tmp.s.Hi == pu128RaxRdx->s.Hi)
|
---|
1512 | {
|
---|
1513 | *pu128Dst = *pu128RbxRcx;
|
---|
1514 | *pEFlags |= X86_EFL_ZF;
|
---|
1515 | }
|
---|
1516 | else
|
---|
1517 | {
|
---|
1518 | *pu128RaxRdx = u128Tmp;
|
---|
1519 | *pEFlags &= ~X86_EFL_ZF;
|
---|
1520 | }
|
---|
1521 | }
|
---|
1522 | #endif /* !RT_ARCH_ARM64 */
|
---|
1523 |
|
---|
1524 | #if defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1525 |
|
---|
1526 | /* Unlocked versions mapped to the locked ones: */
|
---|
1527 |
|
---|
1528 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags))
|
---|
1529 | {
|
---|
1530 | iemAImpl_cmpxchg_u8_locked(pu8Dst, puAl, uSrcReg, pEFlags);
|
---|
1531 | }
|
---|
1532 |
|
---|
1533 |
|
---|
1534 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags))
|
---|
1535 | {
|
---|
1536 | iemAImpl_cmpxchg_u16_locked(pu16Dst, puAx, uSrcReg, pEFlags);
|
---|
1537 | }
|
---|
1538 |
|
---|
1539 |
|
---|
1540 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags))
|
---|
1541 | {
|
---|
1542 | iemAImpl_cmpxchg_u32_locked(pu32Dst, puEax, uSrcReg, pEFlags);
|
---|
1543 | }
|
---|
1544 |
|
---|
1545 |
|
---|
1546 | # if ARCH_BITS == 32
|
---|
1547 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags))
|
---|
1548 | {
|
---|
1549 | iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, puSrcReg, pEFlags);
|
---|
1550 | }
|
---|
1551 | # else
|
---|
1552 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags))
|
---|
1553 | {
|
---|
1554 | iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, uSrcReg, pEFlags);
|
---|
1555 | }
|
---|
1556 | # endif
|
---|
1557 |
|
---|
1558 |
|
---|
1559 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx, uint32_t *pEFlags))
|
---|
1560 | {
|
---|
1561 | iemAImpl_cmpxchg8b_locked(pu64Dst, pu64EaxEdx, pu64EbxEcx, pEFlags);
|
---|
1562 | }
|
---|
1563 |
|
---|
1564 |
|
---|
1565 | IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
|
---|
1566 | uint32_t *pEFlags))
|
---|
1567 | {
|
---|
1568 | iemAImpl_cmpxchg16b_locked(pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
|
---|
1569 | }
|
---|
1570 |
|
---|
1571 | #endif /* defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1572 |
|
---|
1573 | #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1574 |
|
---|
1575 | /*
|
---|
1576 | * MUL, IMUL, DIV and IDIV helpers.
|
---|
1577 | *
|
---|
1578 | * - The U64 versions must use 128-bit intermediates, so we need to abstract the
|
---|
1579 | * division step so we can select between using C operators and
|
---|
1580 | * RTUInt128DivRem/RTUInt128MulU64ByU64.
|
---|
1581 | *
|
---|
1582 | * - The U8 versions work returns output in AL + AH instead of xDX + xAX, with the
|
---|
1583 | * IDIV/DIV taking all the input in AX too. This means we have to abstract some
|
---|
1584 | * input loads and the result storing.
|
---|
1585 | */
|
---|
1586 |
|
---|
1587 | DECLINLINE(void) RTUInt128DivRemByU64(PRTUINT128U pQuotient, PRTUINT128U pRemainder, PCRTUINT128U pDividend, uint64_t u64Divisor)
|
---|
1588 | {
|
---|
1589 | # ifdef __GNUC__ /* GCC maybe really annoying in function. */
|
---|
1590 | pQuotient->s.Lo = 0;
|
---|
1591 | pQuotient->s.Hi = 0;
|
---|
1592 | # endif
|
---|
1593 | RTUINT128U Divisor;
|
---|
1594 | Divisor.s.Lo = u64Divisor;
|
---|
1595 | Divisor.s.Hi = 0;
|
---|
1596 | RTUInt128DivRem(pQuotient, pRemainder, pDividend, &Divisor);
|
---|
1597 | }
|
---|
1598 |
|
---|
1599 | # define DIV_LOAD(a_Dividend) \
|
---|
1600 | a_Dividend.s.Lo = *puA, a_Dividend.s.Hi = *puD
|
---|
1601 | # define DIV_LOAD_U8(a_Dividend) \
|
---|
1602 | a_Dividend.u = *puAX
|
---|
1603 |
|
---|
1604 | # define DIV_STORE(a_Quotient, a_uReminder) *puA = (a_Quotient), *puD = (a_uReminder)
|
---|
1605 | # define DIV_STORE_U8(a_Quotient, a_uReminder) *puAX = (uint8_t)(a_Quotient) | ((uint16_t)(a_uReminder) << 8)
|
---|
1606 |
|
---|
1607 | # define MUL_LOAD_F1() *puA
|
---|
1608 | # define MUL_LOAD_F1_U8() ((uint8_t)*puAX)
|
---|
1609 |
|
---|
1610 | # define MUL_STORE(a_Result) *puA = (a_Result).s.Lo, *puD = (a_Result).s.Hi
|
---|
1611 | # define MUL_STORE_U8(a_Result) *puAX = a_Result.u
|
---|
1612 |
|
---|
1613 | # define MULDIV_NEG(a_Value, a_cBitsWidth2x) \
|
---|
1614 | (a_Value).u = UINT ## a_cBitsWidth2x ## _C(0) - (a_Value).u
|
---|
1615 | # define MULDIV_NEG_U128(a_Value, a_cBitsWidth2x) \
|
---|
1616 | RTUInt128AssignNeg(&(a_Value))
|
---|
1617 |
|
---|
1618 | # define MULDIV_MUL(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
|
---|
1619 | (a_Result).u = (uint ## a_cBitsWidth2x ## _t)(a_Factor1) * (a_Factor2)
|
---|
1620 | # define MULDIV_MUL_U128(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
|
---|
1621 | RTUInt128MulU64ByU64(&(a_Result), a_Factor1, a_Factor2);
|
---|
1622 |
|
---|
1623 | # define MULDIV_MODDIV(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
|
---|
1624 | a_Quotient.u = (a_Dividend).u / (a_uDivisor), \
|
---|
1625 | a_Remainder.u = (a_Dividend).u % (a_uDivisor)
|
---|
1626 | # define MULDIV_MODDIV_U128(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
|
---|
1627 | RTUInt128DivRemByU64(&a_Quotient, &a_Remainder, &a_Dividend, a_uDivisor)
|
---|
1628 |
|
---|
1629 |
|
---|
1630 | /*
|
---|
1631 | * MUL
|
---|
1632 | */
|
---|
1633 | # define EMIT_MUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnMul) \
|
---|
1634 | IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u ## a_cBitsWidth, a_Args) \
|
---|
1635 | { \
|
---|
1636 | RTUINT ## a_cBitsWidth2x ## U Result; \
|
---|
1637 | a_fnMul(Result, a_fnLoadF1(), uFactor, a_cBitsWidth2x); \
|
---|
1638 | a_fnStore(Result); \
|
---|
1639 | \
|
---|
1640 | /* MUL EFLAGS according to Skylake (similar to IMUL). */ \
|
---|
1641 | uint32_t fEfl = *pfEFlags & ~(X86_EFL_SF | X86_EFL_CF | X86_EFL_OF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF); \
|
---|
1642 | if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1643 | fEfl |= X86_EFL_SF; \
|
---|
1644 | fEfl |= g_afParity[Result.s.Lo & 0xff]; \
|
---|
1645 | if (Result.s.Hi != 0) \
|
---|
1646 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1647 | *pfEFlags = fEfl; \
|
---|
1648 | return 0; \
|
---|
1649 | } \
|
---|
1650 | IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u ## a_cBitsWidth ## _intel, a_Args) \
|
---|
1651 | { \
|
---|
1652 | return iemAImpl_mul_u ## a_cBitsWidth a_CallArgs; \
|
---|
1653 | } \
|
---|
1654 | IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u ## a_cBitsWidth ## _amd, a_Args) \
|
---|
1655 | { \
|
---|
1656 | RTUINT ## a_cBitsWidth2x ## U Result; \
|
---|
1657 | a_fnMul(Result, a_fnLoadF1(), uFactor, a_cBitsWidth2x); \
|
---|
1658 | a_fnStore(Result); \
|
---|
1659 | \
|
---|
1660 | /* MUL EFLAGS according to Skylake (similar to IMUL). */ \
|
---|
1661 | uint32_t fEfl = *pfEFlags & ~(X86_EFL_SF | X86_EFL_CF | X86_EFL_OF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF); \
|
---|
1662 | if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1663 | fEfl |= X86_EFL_SF; \
|
---|
1664 | fEfl |= g_afParity[Result.s.Lo & 0xff]; /* (Skylake behaviour) */ \
|
---|
1665 | if (Result.s.Hi != 0) \
|
---|
1666 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1667 | *pfEFlags = fEfl; \
|
---|
1668 | return 0; \
|
---|
1669 | }
|
---|
1670 |
|
---|
1671 | EMIT_MUL(64, 128, (uint64_t *puA, uint64_t *puD, uint64_t uFactor, uint32_t *pfEFlags), (puA, puD, uFactor, pfEFlags),
|
---|
1672 | MUL_LOAD_F1, MUL_STORE, MULDIV_MUL_U128)
|
---|
1673 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1674 | EMIT_MUL(32, 64, (uint32_t *puA, uint32_t *puD, uint32_t uFactor, uint32_t *pfEFlags), (puA, puD, uFactor, pfEFlags),
|
---|
1675 | MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
|
---|
1676 | EMIT_MUL(16, 32, (uint16_t *puA, uint16_t *puD, uint16_t uFactor, uint32_t *pfEFlags), (puA, puD, uFactor, pfEFlags),
|
---|
1677 | MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
|
---|
1678 | EMIT_MUL(8, 16, (uint16_t *puAX, uint8_t uFactor, uint32_t *pfEFlags), (puAX, uFactor, pfEFlags),
|
---|
1679 | MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_MUL)
|
---|
1680 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1681 |
|
---|
1682 |
|
---|
1683 | /*
|
---|
1684 | * IMUL
|
---|
1685 | *
|
---|
1686 | * The SF, ZF, AF and PF flags are "undefined". AMD (3990x) leaves these
|
---|
1687 | * flags as is - at least for the two op version. Whereas Intel skylake (6700K
|
---|
1688 | * and 10980X (Cascade Lake)) always clear AF and ZF and calculates SF and PF
|
---|
1689 | * as per the lower half of the result.
|
---|
1690 | */
|
---|
1691 | # define EMIT_IMUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul) \
|
---|
1692 | IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u ## a_cBitsWidth,a_Args) \
|
---|
1693 | { \
|
---|
1694 | RTUINT ## a_cBitsWidth2x ## U Result; \
|
---|
1695 | uint32_t fEfl = *pfEFlags & ~(X86_EFL_CF | X86_EFL_OF); \
|
---|
1696 | \
|
---|
1697 | uint ## a_cBitsWidth ## _t const uFactor1 = a_fnLoadF1(); \
|
---|
1698 | if (!(uFactor1 & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
1699 | { \
|
---|
1700 | if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
1701 | { \
|
---|
1702 | a_fnMul(Result, uFactor1, uFactor2, a_cBitsWidth2x); \
|
---|
1703 | if (Result.s.Hi != 0 || Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1704 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1705 | } \
|
---|
1706 | else \
|
---|
1707 | { \
|
---|
1708 | uint ## a_cBitsWidth ## _t const uPositiveFactor2 = UINT ## a_cBitsWidth ## _C(0) - uFactor2; \
|
---|
1709 | a_fnMul(Result, uFactor1, uPositiveFactor2, a_cBitsWidth2x); \
|
---|
1710 | if (Result.s.Hi != 0 || Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1711 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1712 | a_fnNeg(Result, a_cBitsWidth2x); \
|
---|
1713 | } \
|
---|
1714 | } \
|
---|
1715 | else \
|
---|
1716 | { \
|
---|
1717 | if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
1718 | { \
|
---|
1719 | uint ## a_cBitsWidth ## _t const uPositiveFactor1 = UINT ## a_cBitsWidth ## _C(0) - uFactor1; \
|
---|
1720 | a_fnMul(Result, uPositiveFactor1, uFactor2, a_cBitsWidth2x); \
|
---|
1721 | if (Result.s.Hi != 0 || Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1722 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1723 | a_fnNeg(Result, a_cBitsWidth2x); \
|
---|
1724 | } \
|
---|
1725 | else \
|
---|
1726 | { \
|
---|
1727 | uint ## a_cBitsWidth ## _t const uPositiveFactor1 = UINT ## a_cBitsWidth ## _C(0) - uFactor1; \
|
---|
1728 | uint ## a_cBitsWidth ## _t const uPositiveFactor2 = UINT ## a_cBitsWidth ## _C(0) - uFactor2; \
|
---|
1729 | a_fnMul(Result, uPositiveFactor1, uPositiveFactor2, a_cBitsWidth2x); \
|
---|
1730 | if (Result.s.Hi != 0 || Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1731 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1732 | } \
|
---|
1733 | } \
|
---|
1734 | a_fnStore(Result); \
|
---|
1735 | \
|
---|
1736 | fEfl &= ~(X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_PF); \
|
---|
1737 | if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1738 | fEfl |= X86_EFL_SF; \
|
---|
1739 | fEfl |= g_afParity[Result.s.Lo & 0xff]; \
|
---|
1740 | *pfEFlags = fEfl; \
|
---|
1741 | return 0; \
|
---|
1742 | } \
|
---|
1743 | \
|
---|
1744 | IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u ## a_cBitsWidth ## _intel,a_Args) \
|
---|
1745 | { \
|
---|
1746 | return iemAImpl_imul_u ## a_cBitsWidth a_CallArgs; \
|
---|
1747 | } \
|
---|
1748 | \
|
---|
1749 | IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u ## a_cBitsWidth ## _amd,a_Args) \
|
---|
1750 | { \
|
---|
1751 | RTUINT ## a_cBitsWidth2x ## U Result; \
|
---|
1752 | /* The SF, ZF, AF and PF flags are "undefined". AMD (3990x) leaves these \
|
---|
1753 | flags as is - at least for the two op version. Whereas Intel skylake \
|
---|
1754 | always clear AF and ZF and calculates SF and PF as per the lower half \
|
---|
1755 | of the result. */ \
|
---|
1756 | uint32_t fEfl = *pfEFlags & ~(X86_EFL_CF | X86_EFL_OF); \
|
---|
1757 | \
|
---|
1758 | uint ## a_cBitsWidth ## _t const uFactor1 = a_fnLoadF1(); \
|
---|
1759 | if (!(uFactor1 & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
1760 | { \
|
---|
1761 | if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
1762 | { \
|
---|
1763 | a_fnMul(Result, uFactor1, uFactor2, a_cBitsWidth2x); \
|
---|
1764 | if (Result.s.Hi != 0 || Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1765 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1766 | } \
|
---|
1767 | else \
|
---|
1768 | { \
|
---|
1769 | uint ## a_cBitsWidth ## _t const uPositiveFactor2 = UINT ## a_cBitsWidth ## _C(0) - uFactor2; \
|
---|
1770 | a_fnMul(Result, uFactor1, uPositiveFactor2, a_cBitsWidth2x); \
|
---|
1771 | if (Result.s.Hi != 0 || Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1772 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1773 | a_fnNeg(Result, a_cBitsWidth2x); \
|
---|
1774 | } \
|
---|
1775 | } \
|
---|
1776 | else \
|
---|
1777 | { \
|
---|
1778 | if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
1779 | { \
|
---|
1780 | uint ## a_cBitsWidth ## _t const uPositiveFactor1 = UINT ## a_cBitsWidth ## _C(0) - uFactor1; \
|
---|
1781 | a_fnMul(Result, uPositiveFactor1, uFactor2, a_cBitsWidth2x); \
|
---|
1782 | if (Result.s.Hi != 0 || Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1783 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1784 | a_fnNeg(Result, a_cBitsWidth2x); \
|
---|
1785 | } \
|
---|
1786 | else \
|
---|
1787 | { \
|
---|
1788 | uint ## a_cBitsWidth ## _t const uPositiveFactor1 = UINT ## a_cBitsWidth ## _C(0) - uFactor1; \
|
---|
1789 | uint ## a_cBitsWidth ## _t const uPositiveFactor2 = UINT ## a_cBitsWidth ## _C(0) - uFactor2; \
|
---|
1790 | a_fnMul(Result, uPositiveFactor1, uPositiveFactor2, a_cBitsWidth2x); \
|
---|
1791 | if (Result.s.Hi != 0 || Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1792 | fEfl |= X86_EFL_CF | X86_EFL_OF; \
|
---|
1793 | } \
|
---|
1794 | } \
|
---|
1795 | a_fnStore(Result); \
|
---|
1796 | *pfEFlags = fEfl; \
|
---|
1797 | return 0; \
|
---|
1798 | }
|
---|
1799 | EMIT_IMUL(64, 128, (uint64_t *puA, uint64_t *puD, uint64_t uFactor2, uint32_t *pfEFlags), (puA, puD, uFactor2, pfEFlags),
|
---|
1800 | MUL_LOAD_F1, MUL_STORE, MULDIV_NEG_U128, MULDIV_MUL_U128)
|
---|
1801 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1802 | EMIT_IMUL(32, 64, (uint32_t *puA, uint32_t *puD, uint32_t uFactor2, uint32_t *pfEFlags), (puA, puD, uFactor2, pfEFlags),
|
---|
1803 | MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
|
---|
1804 | EMIT_IMUL(16, 32, (uint16_t *puA, uint16_t *puD, uint16_t uFactor2, uint32_t *pfEFlags), (puA, puD, uFactor2, pfEFlags),
|
---|
1805 | MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
|
---|
1806 | EMIT_IMUL(8, 16, (uint16_t *puAX, uint8_t uFactor2, uint32_t *pfEFlags), (puAX, uFactor2, pfEFlags),
|
---|
1807 | MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_NEG, MULDIV_MUL)
|
---|
1808 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1809 |
|
---|
1810 |
|
---|
1811 | # define EMIT_IMUL_TWO(a_cBits, a_uType) \
|
---|
1812 | IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
|
---|
1813 | { \
|
---|
1814 | a_uType uIgn; \
|
---|
1815 | iemAImpl_imul_u ## a_cBits(puDst, &uIgn, uSrc, pfEFlags); \
|
---|
1816 | } \
|
---|
1817 | \
|
---|
1818 | IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits ## _intel,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
|
---|
1819 | { \
|
---|
1820 | a_uType uIgn; \
|
---|
1821 | iemAImpl_imul_u ## a_cBits(puDst, &uIgn, uSrc, pfEFlags); \
|
---|
1822 | } \
|
---|
1823 | \
|
---|
1824 | IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits ## _amd,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
|
---|
1825 | { \
|
---|
1826 | a_uType uIgn; \
|
---|
1827 | iemAImpl_imul_u ## a_cBits(puDst, &uIgn, uSrc, pfEFlags); \
|
---|
1828 | }
|
---|
1829 |
|
---|
1830 | EMIT_IMUL_TWO(64, uint64_t)
|
---|
1831 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1832 | EMIT_IMUL_TWO(32, uint32_t)
|
---|
1833 | EMIT_IMUL_TWO(16, uint16_t)
|
---|
1834 | # endif
|
---|
1835 |
|
---|
1836 | /*
|
---|
1837 | * DIV
|
---|
1838 | */
|
---|
1839 | # define EMIT_DIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnDivRem) \
|
---|
1840 | IEM_DECL_IMPL_DEF(int, iemAImpl_div_u ## a_cBitsWidth,a_Args) \
|
---|
1841 | { \
|
---|
1842 | /* Note! Skylake leaves all flags alone. */ \
|
---|
1843 | RT_NOREF_PV(pfEFlags); \
|
---|
1844 | \
|
---|
1845 | RTUINT ## a_cBitsWidth2x ## U Dividend; \
|
---|
1846 | a_fnLoad(Dividend); \
|
---|
1847 | if ( uDivisor != 0 \
|
---|
1848 | && Dividend.s.Hi < uDivisor) \
|
---|
1849 | { \
|
---|
1850 | RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
|
---|
1851 | a_fnDivRem(Quotient, Remainder, Dividend, uDivisor); \
|
---|
1852 | a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
|
---|
1853 | /** @todo research the undefined DIV flags. */ \
|
---|
1854 | return 0; \
|
---|
1855 | } \
|
---|
1856 | /* #DE */ \
|
---|
1857 | return -1; \
|
---|
1858 | } \
|
---|
1859 | \
|
---|
1860 | IEM_DECL_IMPL_DEF(int, iemAImpl_div_u ## a_cBitsWidth ## _intel,a_Args) \
|
---|
1861 | { \
|
---|
1862 | return iemAImpl_div_u ## a_cBitsWidth a_CallArgs; \
|
---|
1863 | } \
|
---|
1864 | \
|
---|
1865 | IEM_DECL_IMPL_DEF(int, iemAImpl_div_u ## a_cBitsWidth ## _amd,a_Args) \
|
---|
1866 | { \
|
---|
1867 | /* Note! Skylake leaves all flags alone. */ \
|
---|
1868 | RT_NOREF_PV(pfEFlags); \
|
---|
1869 | \
|
---|
1870 | RTUINT ## a_cBitsWidth2x ## U Dividend; \
|
---|
1871 | a_fnLoad(Dividend); \
|
---|
1872 | if ( uDivisor != 0 \
|
---|
1873 | && Dividend.s.Hi < uDivisor) \
|
---|
1874 | { \
|
---|
1875 | RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
|
---|
1876 | a_fnDivRem(Quotient, Remainder, Dividend, uDivisor); \
|
---|
1877 | a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
|
---|
1878 | /** @todo research the undefined DIV flags. */ \
|
---|
1879 | return 0; \
|
---|
1880 | } \
|
---|
1881 | /* #DE */ \
|
---|
1882 | return -1; \
|
---|
1883 | }
|
---|
1884 | EMIT_DIV(64,128,(uint64_t *puA, uint64_t *puD, uint64_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
|
---|
1885 | DIV_LOAD, DIV_STORE, MULDIV_MODDIV_U128)
|
---|
1886 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
1887 | EMIT_DIV(32,64, (uint32_t *puA, uint32_t *puD, uint32_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
|
---|
1888 | DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
|
---|
1889 | EMIT_DIV(16,32, (uint16_t *puA, uint16_t *puD, uint16_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
|
---|
1890 | DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
|
---|
1891 | EMIT_DIV(8,16, (uint16_t *puAX, uint8_t uDivisor, uint32_t *pfEFlags), (puAX, uDivisor, pfEFlags),
|
---|
1892 | DIV_LOAD_U8, DIV_STORE_U8, MULDIV_MODDIV)
|
---|
1893 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
1894 |
|
---|
1895 |
|
---|
1896 | /*
|
---|
1897 | * IDIV
|
---|
1898 | */
|
---|
1899 | # define EMIT_IDIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem) \
|
---|
1900 | IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u ## a_cBitsWidth,a_Args) \
|
---|
1901 | { \
|
---|
1902 | /* Note! Skylake leaves all flags alone. */ \
|
---|
1903 | RT_NOREF_PV(pfEFlags); \
|
---|
1904 | \
|
---|
1905 | /** @todo overflow checks */ \
|
---|
1906 | if (uDivisor != 0) \
|
---|
1907 | { \
|
---|
1908 | /* \
|
---|
1909 | * Convert to unsigned division. \
|
---|
1910 | */ \
|
---|
1911 | RTUINT ## a_cBitsWidth2x ## U Dividend; \
|
---|
1912 | a_fnLoad(Dividend); \
|
---|
1913 | bool const fSignedDividend = RT_BOOL(Dividend.s.Hi & RT_BIT_64(a_cBitsWidth - 1)); \
|
---|
1914 | if (fSignedDividend) \
|
---|
1915 | a_fnNeg(Dividend, a_cBitsWidth2x); \
|
---|
1916 | \
|
---|
1917 | uint ## a_cBitsWidth ## _t uDivisorPositive; \
|
---|
1918 | if (!(uDivisor & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
1919 | uDivisorPositive = uDivisor; \
|
---|
1920 | else \
|
---|
1921 | uDivisorPositive = UINT ## a_cBitsWidth ## _C(0) - uDivisor; \
|
---|
1922 | \
|
---|
1923 | RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
|
---|
1924 | a_fnDivRem(Quotient, Remainder, Dividend, uDivisorPositive); \
|
---|
1925 | \
|
---|
1926 | /* \
|
---|
1927 | * Setup the result, checking for overflows. \
|
---|
1928 | */ \
|
---|
1929 | if (!(uDivisor & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
1930 | { \
|
---|
1931 | if (!fSignedDividend) \
|
---|
1932 | { \
|
---|
1933 | /* Positive divisor, positive dividend => result positive. */ \
|
---|
1934 | if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
|
---|
1935 | { \
|
---|
1936 | a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
|
---|
1937 | return 0; \
|
---|
1938 | } \
|
---|
1939 | } \
|
---|
1940 | else \
|
---|
1941 | { \
|
---|
1942 | /* Positive divisor, negative dividend => result negative. */ \
|
---|
1943 | if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1944 | { \
|
---|
1945 | a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
|
---|
1946 | return 0; \
|
---|
1947 | } \
|
---|
1948 | } \
|
---|
1949 | } \
|
---|
1950 | else \
|
---|
1951 | { \
|
---|
1952 | if (!fSignedDividend) \
|
---|
1953 | { \
|
---|
1954 | /* Negative divisor, positive dividend => negative quotient, positive remainder. */ \
|
---|
1955 | if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
1956 | { \
|
---|
1957 | a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, Remainder.s.Lo); \
|
---|
1958 | return 0; \
|
---|
1959 | } \
|
---|
1960 | } \
|
---|
1961 | else \
|
---|
1962 | { \
|
---|
1963 | /* Negative divisor, negative dividend => positive quotient, negative remainder. */ \
|
---|
1964 | if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
|
---|
1965 | { \
|
---|
1966 | a_fnStore(Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
|
---|
1967 | return 0; \
|
---|
1968 | } \
|
---|
1969 | } \
|
---|
1970 | } \
|
---|
1971 | } \
|
---|
1972 | /* #DE */ \
|
---|
1973 | return -1; \
|
---|
1974 | } \
|
---|
1975 | \
|
---|
1976 | IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u ## a_cBitsWidth ## _intel,a_Args) \
|
---|
1977 | { \
|
---|
1978 | return iemAImpl_idiv_u ## a_cBitsWidth a_CallArgs; \
|
---|
1979 | } \
|
---|
1980 | \
|
---|
1981 | IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u ## a_cBitsWidth ## _amd,a_Args) \
|
---|
1982 | { \
|
---|
1983 | /* Note! Skylake leaves all flags alone. */ \
|
---|
1984 | RT_NOREF_PV(pfEFlags); \
|
---|
1985 | \
|
---|
1986 | /** @todo overflow checks */ \
|
---|
1987 | if (uDivisor != 0) \
|
---|
1988 | { \
|
---|
1989 | /* \
|
---|
1990 | * Convert to unsigned division. \
|
---|
1991 | */ \
|
---|
1992 | RTUINT ## a_cBitsWidth2x ## U Dividend; \
|
---|
1993 | a_fnLoad(Dividend); \
|
---|
1994 | bool const fSignedDividend = RT_BOOL(Dividend.s.Hi & RT_BIT_64(a_cBitsWidth - 1)); \
|
---|
1995 | if (fSignedDividend) \
|
---|
1996 | a_fnNeg(Dividend, a_cBitsWidth2x); \
|
---|
1997 | \
|
---|
1998 | uint ## a_cBitsWidth ## _t uDivisorPositive; \
|
---|
1999 | if (!(uDivisor & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
2000 | uDivisorPositive = uDivisor; \
|
---|
2001 | else \
|
---|
2002 | uDivisorPositive = UINT ## a_cBitsWidth ## _C(0) - uDivisor; \
|
---|
2003 | \
|
---|
2004 | RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
|
---|
2005 | a_fnDivRem(Quotient, Remainder, Dividend, uDivisorPositive); \
|
---|
2006 | \
|
---|
2007 | /* \
|
---|
2008 | * Setup the result, checking for overflows. \
|
---|
2009 | */ \
|
---|
2010 | if (!(uDivisor & RT_BIT_64(a_cBitsWidth - 1))) \
|
---|
2011 | { \
|
---|
2012 | if (!fSignedDividend) \
|
---|
2013 | { \
|
---|
2014 | /* Positive divisor, positive dividend => result positive. */ \
|
---|
2015 | if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
|
---|
2016 | { \
|
---|
2017 | a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
|
---|
2018 | return 0; \
|
---|
2019 | } \
|
---|
2020 | } \
|
---|
2021 | else \
|
---|
2022 | { \
|
---|
2023 | /* Positive divisor, negative dividend => result negative. */ \
|
---|
2024 | if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
2025 | { \
|
---|
2026 | a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
|
---|
2027 | return 0; \
|
---|
2028 | } \
|
---|
2029 | } \
|
---|
2030 | } \
|
---|
2031 | else \
|
---|
2032 | { \
|
---|
2033 | if (!fSignedDividend) \
|
---|
2034 | { \
|
---|
2035 | /* Negative divisor, positive dividend => negative quotient, positive remainder. */ \
|
---|
2036 | if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
|
---|
2037 | { \
|
---|
2038 | a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, Remainder.s.Lo); \
|
---|
2039 | return 0; \
|
---|
2040 | } \
|
---|
2041 | } \
|
---|
2042 | else \
|
---|
2043 | { \
|
---|
2044 | /* Negative divisor, negative dividend => positive quotient, negative remainder. */ \
|
---|
2045 | if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
|
---|
2046 | { \
|
---|
2047 | a_fnStore(Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
|
---|
2048 | return 0; \
|
---|
2049 | } \
|
---|
2050 | } \
|
---|
2051 | } \
|
---|
2052 | } \
|
---|
2053 | /* #DE */ \
|
---|
2054 | return -1; \
|
---|
2055 | }
|
---|
2056 |
|
---|
2057 | EMIT_IDIV(64,128,(uint64_t *puA, uint64_t *puD, uint64_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
|
---|
2058 | DIV_LOAD, DIV_STORE, MULDIV_NEG_U128, MULDIV_MODDIV_U128)
|
---|
2059 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2060 | EMIT_IDIV(32,64,(uint32_t *puA, uint32_t *puD, uint32_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
|
---|
2061 | DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
|
---|
2062 | EMIT_IDIV(16,32,(uint16_t *puA, uint16_t *puD, uint16_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
|
---|
2063 | DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
|
---|
2064 | EMIT_IDIV(8,16,(uint16_t *puAX, uint8_t uDivisor, uint32_t *pfEFlags), (puAX, uDivisor, pfEFlags),
|
---|
2065 | DIV_LOAD_U8, DIV_STORE_U8, MULDIV_NEG, MULDIV_MODDIV)
|
---|
2066 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
2067 |
|
---|
2068 |
|
---|
2069 | /*********************************************************************************************************************************
|
---|
2070 | * Unary operations. *
|
---|
2071 | *********************************************************************************************************************************/
|
---|
2072 |
|
---|
2073 | /**
|
---|
2074 | * Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an INC or DEC instruction.
|
---|
2075 | *
|
---|
2076 | * CF is NOT modified for hysterical raisins (allegedly for carrying and
|
---|
2077 | * borrowing in arithmetic loops on intel 8008).
|
---|
2078 | *
|
---|
2079 | * @returns Status bits.
|
---|
2080 | * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
|
---|
2081 | * @param a_uResult Unsigned result value.
|
---|
2082 | * @param a_uDst The original destination value (for AF calc).
|
---|
2083 | * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
|
---|
2084 | * @param a_OfMethod 0 for INC-style, 1 for DEC-style.
|
---|
2085 | */
|
---|
2086 | #define IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth, a_OfMethod) \
|
---|
2087 | do { \
|
---|
2088 | uint32_t fEflTmp = *(a_pfEFlags); \
|
---|
2089 | fEflTmp &= ~X86_EFL_STATUS_BITS | X86_EFL_CF; \
|
---|
2090 | fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
|
---|
2091 | fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
|
---|
2092 | fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
|
---|
2093 | fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
|
---|
2094 | fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth(a_OfMethod == 0 ? (((a_uDst) ^ RT_BIT_64(a_cBitsWidth - 1)) & (a_uResult)) \
|
---|
2095 | : ((a_uDst) & ((a_uResult) ^ RT_BIT_64(a_cBitsWidth - 1))) ); \
|
---|
2096 | *(a_pfEFlags) = fEflTmp; \
|
---|
2097 | } while (0)
|
---|
2098 |
|
---|
2099 | /*
|
---|
2100 | * INC
|
---|
2101 | */
|
---|
2102 |
|
---|
2103 | IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64,(uint64_t *puDst, uint32_t *pfEFlags))
|
---|
2104 | {
|
---|
2105 | uint64_t uDst = *puDst;
|
---|
2106 | uint64_t uResult = uDst + 1;
|
---|
2107 | *puDst = uResult;
|
---|
2108 | IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 0 /*INC*/);
|
---|
2109 | }
|
---|
2110 |
|
---|
2111 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2112 |
|
---|
2113 | IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u32,(uint32_t *puDst, uint32_t *pfEFlags))
|
---|
2114 | {
|
---|
2115 | uint32_t uDst = *puDst;
|
---|
2116 | uint32_t uResult = uDst + 1;
|
---|
2117 | *puDst = uResult;
|
---|
2118 | IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 0 /*INC*/);
|
---|
2119 | }
|
---|
2120 |
|
---|
2121 |
|
---|
2122 | IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u16,(uint16_t *puDst, uint32_t *pfEFlags))
|
---|
2123 | {
|
---|
2124 | uint16_t uDst = *puDst;
|
---|
2125 | uint16_t uResult = uDst + 1;
|
---|
2126 | *puDst = uResult;
|
---|
2127 | IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 0 /*INC*/);
|
---|
2128 | }
|
---|
2129 |
|
---|
2130 | IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u8,(uint8_t *puDst, uint32_t *pfEFlags))
|
---|
2131 | {
|
---|
2132 | uint8_t uDst = *puDst;
|
---|
2133 | uint8_t uResult = uDst + 1;
|
---|
2134 | *puDst = uResult;
|
---|
2135 | IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 0 /*INC*/);
|
---|
2136 | }
|
---|
2137 |
|
---|
2138 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
2139 |
|
---|
2140 |
|
---|
2141 | /*
|
---|
2142 | * DEC
|
---|
2143 | */
|
---|
2144 |
|
---|
2145 | IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64,(uint64_t *puDst, uint32_t *pfEFlags))
|
---|
2146 | {
|
---|
2147 | uint64_t uDst = *puDst;
|
---|
2148 | uint64_t uResult = uDst - 1;
|
---|
2149 | *puDst = uResult;
|
---|
2150 | IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 1 /*INC*/);
|
---|
2151 | }
|
---|
2152 |
|
---|
2153 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2154 |
|
---|
2155 | IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u32,(uint32_t *puDst, uint32_t *pfEFlags))
|
---|
2156 | {
|
---|
2157 | uint32_t uDst = *puDst;
|
---|
2158 | uint32_t uResult = uDst - 1;
|
---|
2159 | *puDst = uResult;
|
---|
2160 | IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 1 /*INC*/);
|
---|
2161 | }
|
---|
2162 |
|
---|
2163 |
|
---|
2164 | IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u16,(uint16_t *puDst, uint32_t *pfEFlags))
|
---|
2165 | {
|
---|
2166 | uint16_t uDst = *puDst;
|
---|
2167 | uint16_t uResult = uDst - 1;
|
---|
2168 | *puDst = uResult;
|
---|
2169 | IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 1 /*INC*/);
|
---|
2170 | }
|
---|
2171 |
|
---|
2172 |
|
---|
2173 | IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u8,(uint8_t *puDst, uint32_t *pfEFlags))
|
---|
2174 | {
|
---|
2175 | uint8_t uDst = *puDst;
|
---|
2176 | uint8_t uResult = uDst - 1;
|
---|
2177 | *puDst = uResult;
|
---|
2178 | IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 1 /*INC*/);
|
---|
2179 | }
|
---|
2180 |
|
---|
2181 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
2182 |
|
---|
2183 |
|
---|
2184 | /*
|
---|
2185 | * NOT
|
---|
2186 | */
|
---|
2187 |
|
---|
2188 | IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64,(uint64_t *puDst, uint32_t *pfEFlags))
|
---|
2189 | {
|
---|
2190 | uint64_t uDst = *puDst;
|
---|
2191 | uint64_t uResult = ~uDst;
|
---|
2192 | *puDst = uResult;
|
---|
2193 | /* EFLAGS are not modified. */
|
---|
2194 | RT_NOREF_PV(pfEFlags);
|
---|
2195 | }
|
---|
2196 |
|
---|
2197 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2198 |
|
---|
2199 | IEM_DECL_IMPL_DEF(void, iemAImpl_not_u32,(uint32_t *puDst, uint32_t *pfEFlags))
|
---|
2200 | {
|
---|
2201 | uint32_t uDst = *puDst;
|
---|
2202 | uint32_t uResult = ~uDst;
|
---|
2203 | *puDst = uResult;
|
---|
2204 | /* EFLAGS are not modified. */
|
---|
2205 | RT_NOREF_PV(pfEFlags);
|
---|
2206 | }
|
---|
2207 |
|
---|
2208 | IEM_DECL_IMPL_DEF(void, iemAImpl_not_u16,(uint16_t *puDst, uint32_t *pfEFlags))
|
---|
2209 | {
|
---|
2210 | uint16_t uDst = *puDst;
|
---|
2211 | uint16_t uResult = ~uDst;
|
---|
2212 | *puDst = uResult;
|
---|
2213 | /* EFLAGS are not modified. */
|
---|
2214 | RT_NOREF_PV(pfEFlags);
|
---|
2215 | }
|
---|
2216 |
|
---|
2217 | IEM_DECL_IMPL_DEF(void, iemAImpl_not_u8,(uint8_t *puDst, uint32_t *pfEFlags))
|
---|
2218 | {
|
---|
2219 | uint8_t uDst = *puDst;
|
---|
2220 | uint8_t uResult = ~uDst;
|
---|
2221 | *puDst = uResult;
|
---|
2222 | /* EFLAGS are not modified. */
|
---|
2223 | RT_NOREF_PV(pfEFlags);
|
---|
2224 | }
|
---|
2225 |
|
---|
2226 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
2227 |
|
---|
2228 |
|
---|
2229 | /*
|
---|
2230 | * NEG
|
---|
2231 | */
|
---|
2232 |
|
---|
2233 | /**
|
---|
2234 | * Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an NEG instruction.
|
---|
2235 | *
|
---|
2236 | * @returns Status bits.
|
---|
2237 | * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
|
---|
2238 | * @param a_uResult Unsigned result value.
|
---|
2239 | * @param a_uDst The original destination value (for AF calc).
|
---|
2240 | * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
|
---|
2241 | */
|
---|
2242 | #define IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth) \
|
---|
2243 | do { \
|
---|
2244 | uint32_t fEflTmp = *(a_pfEFlags); \
|
---|
2245 | fEflTmp &= ~X86_EFL_STATUS_BITS & ~X86_EFL_CF; \
|
---|
2246 | fEflTmp |= ((a_uDst) != 0) << X86_EFL_CF_BIT; \
|
---|
2247 | fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
|
---|
2248 | fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
|
---|
2249 | fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
|
---|
2250 | fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
|
---|
2251 | fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth((a_uDst) & (a_uResult)); \
|
---|
2252 | *(a_pfEFlags) = fEflTmp; \
|
---|
2253 | } while (0)
|
---|
2254 |
|
---|
2255 | IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64,(uint64_t *puDst, uint32_t *pfEFlags))
|
---|
2256 | {
|
---|
2257 | uint64_t uDst = *puDst;
|
---|
2258 | uint64_t uResult = (uint64_t)0 - uDst;
|
---|
2259 | *puDst = uResult;
|
---|
2260 | IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 64);
|
---|
2261 | }
|
---|
2262 |
|
---|
2263 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2264 |
|
---|
2265 | IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u32,(uint32_t *puDst, uint32_t *pfEFlags))
|
---|
2266 | {
|
---|
2267 | uint32_t uDst = *puDst;
|
---|
2268 | uint32_t uResult = (uint32_t)0 - uDst;
|
---|
2269 | *puDst = uResult;
|
---|
2270 | IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 32);
|
---|
2271 | }
|
---|
2272 |
|
---|
2273 |
|
---|
2274 | IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u16,(uint16_t *puDst, uint32_t *pfEFlags))
|
---|
2275 | {
|
---|
2276 | uint16_t uDst = *puDst;
|
---|
2277 | uint16_t uResult = (uint16_t)0 - uDst;
|
---|
2278 | *puDst = uResult;
|
---|
2279 | IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 16);
|
---|
2280 | }
|
---|
2281 |
|
---|
2282 |
|
---|
2283 | IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u8,(uint8_t *puDst, uint32_t *pfEFlags))
|
---|
2284 | {
|
---|
2285 | uint8_t uDst = *puDst;
|
---|
2286 | uint8_t uResult = (uint8_t)0 - uDst;
|
---|
2287 | *puDst = uResult;
|
---|
2288 | IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 8);
|
---|
2289 | }
|
---|
2290 |
|
---|
2291 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
2292 |
|
---|
2293 | /*
|
---|
2294 | * Locked variants.
|
---|
2295 | */
|
---|
2296 |
|
---|
2297 | /** Emit a function for doing a locked unary operand operation. */
|
---|
2298 | # define EMIT_LOCKED_UNARY_OP(a_Mnemonic, a_cBitsWidth) \
|
---|
2299 | IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
|
---|
2300 | uint32_t *pfEFlags)) \
|
---|
2301 | { \
|
---|
2302 | uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
|
---|
2303 | uint ## a_cBitsWidth ## _t uTmp; \
|
---|
2304 | uint32_t fEflTmp; \
|
---|
2305 | do \
|
---|
2306 | { \
|
---|
2307 | uTmp = uOld; \
|
---|
2308 | fEflTmp = *pfEFlags; \
|
---|
2309 | iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, &fEflTmp); \
|
---|
2310 | } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
|
---|
2311 | *pfEFlags = fEflTmp; \
|
---|
2312 | }
|
---|
2313 |
|
---|
2314 | EMIT_LOCKED_UNARY_OP(inc, 64)
|
---|
2315 | EMIT_LOCKED_UNARY_OP(dec, 64)
|
---|
2316 | EMIT_LOCKED_UNARY_OP(not, 64)
|
---|
2317 | EMIT_LOCKED_UNARY_OP(neg, 64)
|
---|
2318 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2319 | EMIT_LOCKED_UNARY_OP(inc, 32)
|
---|
2320 | EMIT_LOCKED_UNARY_OP(dec, 32)
|
---|
2321 | EMIT_LOCKED_UNARY_OP(not, 32)
|
---|
2322 | EMIT_LOCKED_UNARY_OP(neg, 32)
|
---|
2323 |
|
---|
2324 | EMIT_LOCKED_UNARY_OP(inc, 16)
|
---|
2325 | EMIT_LOCKED_UNARY_OP(dec, 16)
|
---|
2326 | EMIT_LOCKED_UNARY_OP(not, 16)
|
---|
2327 | EMIT_LOCKED_UNARY_OP(neg, 16)
|
---|
2328 |
|
---|
2329 | EMIT_LOCKED_UNARY_OP(inc, 8)
|
---|
2330 | EMIT_LOCKED_UNARY_OP(dec, 8)
|
---|
2331 | EMIT_LOCKED_UNARY_OP(not, 8)
|
---|
2332 | EMIT_LOCKED_UNARY_OP(neg, 8)
|
---|
2333 | # endif
|
---|
2334 |
|
---|
2335 |
|
---|
2336 | /*********************************************************************************************************************************
|
---|
2337 | * Shifting and Rotating *
|
---|
2338 | *********************************************************************************************************************************/
|
---|
2339 |
|
---|
2340 | /*
|
---|
2341 | * ROL
|
---|
2342 | */
|
---|
2343 |
|
---|
2344 | /**
|
---|
2345 | * Updates the status bits (OF and CF) for an ROL instruction.
|
---|
2346 | *
|
---|
2347 | * @returns Status bits.
|
---|
2348 | * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
|
---|
2349 | * @param a_uResult Unsigned result value.
|
---|
2350 | * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
|
---|
2351 | */
|
---|
2352 | #define IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(a_pfEFlags, a_uResult, a_cBitsWidth) do { \
|
---|
2353 | /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
|
---|
2354 | it the same way as for 1 bit shifts. */ \
|
---|
2355 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2356 | uint32_t fEflTmp = *(a_pfEFlags); \
|
---|
2357 | fEflTmp &= ~(X86_EFL_CF | X86_EFL_OF); \
|
---|
2358 | uint32_t const fCarry = ((a_uResult) & X86_EFL_CF); \
|
---|
2359 | fEflTmp |= fCarry; \
|
---|
2360 | fEflTmp |= (((a_uResult) >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
|
---|
2361 | *(a_pfEFlags) = fEflTmp; \
|
---|
2362 | } while (0)
|
---|
2363 |
|
---|
2364 | IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
|
---|
2365 | {
|
---|
2366 | cShift &= 63;
|
---|
2367 | if (cShift)
|
---|
2368 | {
|
---|
2369 | uint64_t uResult = ASMRotateLeftU64(*puDst, cShift);
|
---|
2370 | *puDst = uResult;
|
---|
2371 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 64);
|
---|
2372 | }
|
---|
2373 | }
|
---|
2374 |
|
---|
2375 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2376 |
|
---|
2377 | IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u32,(uint32_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
|
---|
2378 | {
|
---|
2379 | cShift &= 31;
|
---|
2380 | if (cShift)
|
---|
2381 | {
|
---|
2382 | uint32_t uResult = ASMRotateLeftU32(*puDst, cShift);
|
---|
2383 | *puDst = uResult;
|
---|
2384 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 32);
|
---|
2385 | }
|
---|
2386 | }
|
---|
2387 |
|
---|
2388 |
|
---|
2389 | IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u16,(uint16_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
|
---|
2390 | {
|
---|
2391 | cShift &= 15;
|
---|
2392 | if (cShift)
|
---|
2393 | {
|
---|
2394 | uint16_t uDst = *puDst;
|
---|
2395 | uint16_t uResult = (uDst << cShift) | (uDst >> (16 - cShift));
|
---|
2396 | *puDst = uResult;
|
---|
2397 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 16);
|
---|
2398 | }
|
---|
2399 | }
|
---|
2400 |
|
---|
2401 |
|
---|
2402 | IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u8,(uint8_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
|
---|
2403 | {
|
---|
2404 | cShift &= 7;
|
---|
2405 | if (cShift)
|
---|
2406 | {
|
---|
2407 | uint8_t uDst = *puDst;
|
---|
2408 | uint8_t uResult = (uDst << cShift) | (uDst >> (8 - cShift));
|
---|
2409 | *puDst = uResult;
|
---|
2410 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 8);
|
---|
2411 | }
|
---|
2412 | }
|
---|
2413 |
|
---|
2414 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
2415 |
|
---|
2416 |
|
---|
2417 | /*
|
---|
2418 | * ROR
|
---|
2419 | */
|
---|
2420 |
|
---|
2421 | /**
|
---|
2422 | * Updates the status bits (OF and CF) for an ROL instruction.
|
---|
2423 | *
|
---|
2424 | * @returns Status bits.
|
---|
2425 | * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
|
---|
2426 | * @param a_uResult Unsigned result value.
|
---|
2427 | * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
|
---|
2428 | */
|
---|
2429 | #define IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(a_pfEFlags, a_uResult, a_cBitsWidth) do { \
|
---|
2430 | /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
|
---|
2431 | it the same way as for 1 bit shifts. */ \
|
---|
2432 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2433 | uint32_t fEflTmp = *(a_pfEFlags); \
|
---|
2434 | fEflTmp &= ~(X86_EFL_CF | X86_EFL_OF); \
|
---|
2435 | uint32_t const fCarry = ((a_uResult) >> ((a_cBitsWidth) - 1)) & X86_EFL_CF; \
|
---|
2436 | fEflTmp |= fCarry; \
|
---|
2437 | fEflTmp |= ((((a_uResult) >> ((a_cBitsWidth) - 2)) ^ fCarry) & 1) << X86_EFL_OF_BIT; \
|
---|
2438 | *(a_pfEFlags) = fEflTmp; \
|
---|
2439 | } while (0)
|
---|
2440 |
|
---|
2441 | IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
|
---|
2442 | {
|
---|
2443 | cShift &= 63;
|
---|
2444 | if (cShift)
|
---|
2445 | {
|
---|
2446 | uint64_t const uResult = ASMRotateRightU64(*puDst, cShift);
|
---|
2447 | *puDst = uResult;
|
---|
2448 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 64);
|
---|
2449 | }
|
---|
2450 | }
|
---|
2451 |
|
---|
2452 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2453 |
|
---|
2454 | IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u32,(uint32_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
|
---|
2455 | {
|
---|
2456 | cShift &= 31;
|
---|
2457 | if (cShift)
|
---|
2458 | {
|
---|
2459 | uint64_t const uResult = ASMRotateRightU32(*puDst, cShift);
|
---|
2460 | *puDst = uResult;
|
---|
2461 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 32);
|
---|
2462 | }
|
---|
2463 | }
|
---|
2464 |
|
---|
2465 |
|
---|
2466 | IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u16,(uint16_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
|
---|
2467 | {
|
---|
2468 | cShift &= 15;
|
---|
2469 | if (cShift)
|
---|
2470 | {
|
---|
2471 | uint16_t uDst = *puDst;
|
---|
2472 | uint16_t uResult;
|
---|
2473 | uResult = uDst >> cShift;
|
---|
2474 | uResult |= uDst << (16 - cShift);
|
---|
2475 | *puDst = uResult;
|
---|
2476 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 16);
|
---|
2477 | }
|
---|
2478 | }
|
---|
2479 |
|
---|
2480 |
|
---|
2481 | IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u8,(uint8_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
|
---|
2482 | {
|
---|
2483 | cShift &= 7;
|
---|
2484 | if (cShift)
|
---|
2485 | {
|
---|
2486 | uint8_t uDst = *puDst;
|
---|
2487 | uint8_t uResult;
|
---|
2488 | uResult = uDst >> cShift;
|
---|
2489 | uResult |= uDst << (8 - cShift);
|
---|
2490 | *puDst = uResult;
|
---|
2491 | IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 8);
|
---|
2492 | }
|
---|
2493 | }
|
---|
2494 |
|
---|
2495 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
2496 |
|
---|
2497 |
|
---|
2498 | /*
|
---|
2499 | * RCL
|
---|
2500 | */
|
---|
2501 | #define EMIT_RCL(a_cBitsWidth) \
|
---|
2502 | IEM_DECL_IMPL_DEF(void, iemAImpl_rcl_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
|
---|
2503 | { \
|
---|
2504 | cShift &= a_cBitsWidth - 1; \
|
---|
2505 | if (cShift) \
|
---|
2506 | { \
|
---|
2507 | uint ## a_cBitsWidth ## _t const uDst = *puDst; \
|
---|
2508 | uint ## a_cBitsWidth ## _t uResult = uDst << cShift; \
|
---|
2509 | if (cShift > 1) \
|
---|
2510 | uResult |= uDst >> (a_cBitsWidth + 1 - cShift); \
|
---|
2511 | \
|
---|
2512 | uint32_t fEfl = *pfEFlags; \
|
---|
2513 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2514 | uResult |= (uint ## a_cBitsWidth ## _t)(fEfl & X86_EFL_CF) << (cShift - 1); \
|
---|
2515 | \
|
---|
2516 | *puDst = uResult; \
|
---|
2517 | \
|
---|
2518 | /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
|
---|
2519 | it the same way as for 1 bit shifts. */ \
|
---|
2520 | fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
|
---|
2521 | uint32_t const fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
|
---|
2522 | fEfl |= fCarry; \
|
---|
2523 | fEfl |= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
|
---|
2524 | *pfEFlags = fEfl; \
|
---|
2525 | } \
|
---|
2526 | }
|
---|
2527 | EMIT_RCL(64)
|
---|
2528 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2529 | EMIT_RCL(32)
|
---|
2530 | EMIT_RCL(16)
|
---|
2531 | EMIT_RCL(8)
|
---|
2532 | # endif
|
---|
2533 |
|
---|
2534 |
|
---|
2535 | /*
|
---|
2536 | * RCR
|
---|
2537 | */
|
---|
2538 | #define EMIT_RCR(a_cBitsWidth) \
|
---|
2539 | IEM_DECL_IMPL_DEF(void, iemAImpl_rcr_u ## a_cBitsWidth,(uint ## a_cBitsWidth ##_t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
|
---|
2540 | { \
|
---|
2541 | cShift &= a_cBitsWidth - 1; \
|
---|
2542 | if (cShift) \
|
---|
2543 | { \
|
---|
2544 | uint ## a_cBitsWidth ## _t const uDst = *puDst; \
|
---|
2545 | uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
|
---|
2546 | if (cShift > 1) \
|
---|
2547 | uResult |= uDst << (a_cBitsWidth + 1 - cShift); \
|
---|
2548 | \
|
---|
2549 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2550 | uint32_t fEfl = *pfEFlags; \
|
---|
2551 | uResult |= (uint ## a_cBitsWidth ## _t)(fEfl & X86_EFL_CF) << (a_cBitsWidth - cShift); \
|
---|
2552 | *puDst = uResult; \
|
---|
2553 | \
|
---|
2554 | /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
|
---|
2555 | it the same way as for 1 bit shifts. */ \
|
---|
2556 | fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
|
---|
2557 | uint32_t const fCarry = (uDst >> (cShift - 1)) & X86_EFL_CF; \
|
---|
2558 | fEfl |= fCarry; \
|
---|
2559 | fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uResult ^ (uResult << 1)); /* XOR two most signficant bits of the result */ \
|
---|
2560 | *pfEFlags = fEfl; \
|
---|
2561 | } \
|
---|
2562 | }
|
---|
2563 | EMIT_RCR(64)
|
---|
2564 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2565 | EMIT_RCR(32)
|
---|
2566 | EMIT_RCR(16)
|
---|
2567 | EMIT_RCR(8)
|
---|
2568 | # endif
|
---|
2569 |
|
---|
2570 |
|
---|
2571 | /*
|
---|
2572 | * SHL
|
---|
2573 | */
|
---|
2574 | #define EMIT_SHL(a_cBitsWidth) \
|
---|
2575 | IEM_DECL_IMPL_DEF(void, iemAImpl_shl_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
|
---|
2576 | { \
|
---|
2577 | cShift &= a_cBitsWidth - 1; \
|
---|
2578 | if (cShift) \
|
---|
2579 | { \
|
---|
2580 | uint ## a_cBitsWidth ##_t const uDst = *puDst; \
|
---|
2581 | uint ## a_cBitsWidth ##_t uResult = uDst << cShift; \
|
---|
2582 | *puDst = uResult; \
|
---|
2583 | \
|
---|
2584 | /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
|
---|
2585 | it the same way as for 1 bit shifts. The AF bit is undefined, but
|
---|
2586 | AMD 3990x sets it unconditionally so we do the same. */ \
|
---|
2587 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2588 | uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
|
---|
2589 | uint32_t fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
|
---|
2590 | fEfl |= fCarry; \
|
---|
2591 | fEfl |= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
|
---|
2592 | fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
|
---|
2593 | fEfl |= X86_EFL_CALC_ZF(uResult); \
|
---|
2594 | fEfl |= g_afParity[uResult & 0xff]; \
|
---|
2595 | fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally */ \
|
---|
2596 | *pfEFlags = fEfl; \
|
---|
2597 | } \
|
---|
2598 | }
|
---|
2599 | EMIT_SHL(64)
|
---|
2600 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2601 | EMIT_SHL(32)
|
---|
2602 | EMIT_SHL(16)
|
---|
2603 | EMIT_SHL(8)
|
---|
2604 | # endif
|
---|
2605 |
|
---|
2606 |
|
---|
2607 | /*
|
---|
2608 | * SHR
|
---|
2609 | */
|
---|
2610 | #define EMIT_SHR(a_cBitsWidth) \
|
---|
2611 | IEM_DECL_IMPL_DEF(void, iemAImpl_shr_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
|
---|
2612 | { \
|
---|
2613 | cShift &= a_cBitsWidth - 1; \
|
---|
2614 | if (cShift) \
|
---|
2615 | { \
|
---|
2616 | uint ## a_cBitsWidth ## _t const uDst = *puDst; \
|
---|
2617 | uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
|
---|
2618 | *puDst = uResult; \
|
---|
2619 | \
|
---|
2620 | /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
|
---|
2621 | it the same way as for 1 bit shifts. The AF bit is undefined, but \
|
---|
2622 | AMD 3990x sets it unconditionally so we do the same. */ \
|
---|
2623 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2624 | uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
|
---|
2625 | fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
|
---|
2626 | if (cShift == 1) /* AMD 3990x does this too, even if only intel documents this. */ \
|
---|
2627 | fEfl |= (uDst >> (a_cBitsWidth - 1)) << X86_EFL_OF_BIT; \
|
---|
2628 | fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
|
---|
2629 | fEfl |= X86_EFL_CALC_ZF(uResult); \
|
---|
2630 | fEfl |= g_afParity[uResult & 0xff]; \
|
---|
2631 | fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally */ \
|
---|
2632 | *pfEFlags = fEfl; \
|
---|
2633 | } \
|
---|
2634 | }
|
---|
2635 | EMIT_SHR(64)
|
---|
2636 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2637 | EMIT_SHR(32)
|
---|
2638 | EMIT_SHR(16)
|
---|
2639 | EMIT_SHR(8)
|
---|
2640 | # endif
|
---|
2641 |
|
---|
2642 |
|
---|
2643 | /*
|
---|
2644 | * SAR
|
---|
2645 | */
|
---|
2646 | #define EMIT_SAR(a_cBitsWidth) \
|
---|
2647 | IEM_DECL_IMPL_DEF(void, iemAImpl_sar_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
|
---|
2648 | { \
|
---|
2649 | cShift &= a_cBitsWidth - 1; \
|
---|
2650 | if (cShift) \
|
---|
2651 | { \
|
---|
2652 | uint ## a_cBitsWidth ## _t const uDst = *puDst; \
|
---|
2653 | uint ## a_cBitsWidth ## _t uResult = (int ## a_cBitsWidth ## _t)uDst >> cShift; \
|
---|
2654 | *puDst = uResult; \
|
---|
2655 | \
|
---|
2656 | /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
|
---|
2657 | it the same way as for 1 bit shifts (0). The AF bit is undefined, but \
|
---|
2658 | AMD 3990x sets it unconditionally so we do the same. The OF flag is \
|
---|
2659 | zero because the result never differs from the input. */ \
|
---|
2660 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2661 | uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
|
---|
2662 | fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
|
---|
2663 | fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
|
---|
2664 | fEfl |= X86_EFL_CALC_ZF(uResult); \
|
---|
2665 | fEfl |= g_afParity[uResult & 0xff]; \
|
---|
2666 | fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally */ \
|
---|
2667 | *pfEFlags = fEfl; \
|
---|
2668 | } \
|
---|
2669 | }
|
---|
2670 | EMIT_SAR(64)
|
---|
2671 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2672 | EMIT_SAR(32)
|
---|
2673 | EMIT_SAR(16)
|
---|
2674 | EMIT_SAR(8)
|
---|
2675 | # endif
|
---|
2676 |
|
---|
2677 |
|
---|
2678 | /*
|
---|
2679 | * SHLD
|
---|
2680 | */
|
---|
2681 | #define EMIT_SHLD(a_cBitsWidth) \
|
---|
2682 | IEM_DECL_IMPL_DEF(void, iemAImpl_shld_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, \
|
---|
2683 | uint ## a_cBitsWidth ## _t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
|
---|
2684 | { \
|
---|
2685 | cShift &= a_cBitsWidth - 1; \
|
---|
2686 | if (cShift) \
|
---|
2687 | { \
|
---|
2688 | uint ## a_cBitsWidth ## _t const uDst = *puDst; \
|
---|
2689 | uint ## a_cBitsWidth ## _t uResult = uDst << cShift; \
|
---|
2690 | uResult |= uSrc >> (a_cBitsWidth - cShift); \
|
---|
2691 | *puDst = uResult; \
|
---|
2692 | \
|
---|
2693 | /* Calc EFLAGS. CF is the last bit shifted out of puDst. The OF flag \
|
---|
2694 | indicates a sign change for a single shift, whereas intel documents \
|
---|
2695 | setting it to zero for higher shift counts and AMD just says it's \
|
---|
2696 | undefined, however AMD x3990 sets it according to the last sub-shift. \
|
---|
2697 | On AMD x3990 the AF flag is always set. */ \
|
---|
2698 | uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
|
---|
2699 | if (true /*AMD*/) \
|
---|
2700 | { \
|
---|
2701 | fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth((uDst << (cShift - 1)) ^ uResult); /* Set according to last shift. */ \
|
---|
2702 | fEfl |= X86_EFL_AF; \
|
---|
2703 | } \
|
---|
2704 | else \
|
---|
2705 | { \
|
---|
2706 | if (cShift == 1) \
|
---|
2707 | fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth((uDst ^ uResult)); \
|
---|
2708 | fEfl |= X86_EFL_AF; /* ? */ \
|
---|
2709 | } \
|
---|
2710 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2711 | fEfl |= (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; /* CF = last bit shifted out */ \
|
---|
2712 | fEfl |= g_afParity[uResult & 0xff]; \
|
---|
2713 | fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
|
---|
2714 | fEfl |= X86_EFL_CALC_ZF(uResult); \
|
---|
2715 | *pfEFlags = fEfl; \
|
---|
2716 | } \
|
---|
2717 | }
|
---|
2718 | EMIT_SHLD(64)
|
---|
2719 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2720 | EMIT_SHLD(32)
|
---|
2721 | EMIT_SHLD(16)
|
---|
2722 | # endif
|
---|
2723 |
|
---|
2724 |
|
---|
2725 | /*
|
---|
2726 | * SHRD
|
---|
2727 | */
|
---|
2728 | #define EMIT_SHRD(a_cBitsWidth) \
|
---|
2729 | IEM_DECL_IMPL_DEF(void, iemAImpl_shrd_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, \
|
---|
2730 | uint ## a_cBitsWidth ## _t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
|
---|
2731 | { \
|
---|
2732 | cShift &= a_cBitsWidth - 1; \
|
---|
2733 | if (cShift) \
|
---|
2734 | { \
|
---|
2735 | uint ## a_cBitsWidth ## _t const uDst = *puDst; \
|
---|
2736 | uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
|
---|
2737 | uResult |= uSrc << (a_cBitsWidth - cShift); \
|
---|
2738 | *puDst = uResult; \
|
---|
2739 | \
|
---|
2740 | /* Calc EFLAGS. CF is the last bit shifted out of puDst. The OF flag \
|
---|
2741 | indicates a sign change for a single shift, whereas intel documents \
|
---|
2742 | setting it to zero for higher shift counts and AMD just says it's \
|
---|
2743 | undefined, however AMD x3990 sets it according to the last sub-shift. \
|
---|
2744 | On AMD x3990 the AF flag is always set. */ \
|
---|
2745 | uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
|
---|
2746 | if (true /*AMD*/) \
|
---|
2747 | { \
|
---|
2748 | if (cShift > 1) /* Set according to last shift. */ \
|
---|
2749 | fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth((uSrc << (a_cBitsWidth - cShift + 1)) ^ uResult); \
|
---|
2750 | else \
|
---|
2751 | fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ uResult); \
|
---|
2752 | fEfl |= X86_EFL_AF; \
|
---|
2753 | } \
|
---|
2754 | else \
|
---|
2755 | { \
|
---|
2756 | if (cShift == 1) \
|
---|
2757 | fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth((uDst >> (a_cBitsWidth - 1)) ^ (uint32_t)(uResult >> (a_cBitsWidth - 1))); \
|
---|
2758 | fEfl |= X86_EFL_AF; /* ? */ \
|
---|
2759 | } \
|
---|
2760 | AssertCompile(X86_EFL_CF_BIT == 0); \
|
---|
2761 | fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
|
---|
2762 | fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
|
---|
2763 | fEfl |= X86_EFL_CALC_ZF(uResult); \
|
---|
2764 | fEfl |= g_afParity[uResult & 0xff]; \
|
---|
2765 | *pfEFlags = fEfl; \
|
---|
2766 | } \
|
---|
2767 | }
|
---|
2768 | EMIT_SHRD(64)
|
---|
2769 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2770 | EMIT_SHRD(32)
|
---|
2771 | EMIT_SHRD(16)
|
---|
2772 | # endif
|
---|
2773 |
|
---|
2774 |
|
---|
2775 | # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2776 | /*
|
---|
2777 | * BSWAP
|
---|
2778 | */
|
---|
2779 |
|
---|
2780 | IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u64,(uint64_t *puDst))
|
---|
2781 | {
|
---|
2782 | *puDst = ASMByteSwapU64(*puDst);
|
---|
2783 | }
|
---|
2784 |
|
---|
2785 |
|
---|
2786 | IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u32,(uint32_t *puDst))
|
---|
2787 | {
|
---|
2788 | *puDst = ASMByteSwapU32(*puDst);
|
---|
2789 | }
|
---|
2790 |
|
---|
2791 |
|
---|
2792 | /* Note! undocument, so 32-bit arg */
|
---|
2793 | IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u16,(uint32_t *puDst))
|
---|
2794 | {
|
---|
2795 | #if 0
|
---|
2796 | *(uint16_t *)puDst = ASMByteSwapU16(*(uint16_t *)puDst);
|
---|
2797 | #else
|
---|
2798 | /* This is the behaviour AMD 3990x (64-bit mode): */
|
---|
2799 | *(uint16_t *)puDst = 0;
|
---|
2800 | #endif
|
---|
2801 | }
|
---|
2802 |
|
---|
2803 | # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
|
---|
2804 |
|
---|
2805 |
|
---|
2806 |
|
---|
2807 | # if defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2808 |
|
---|
2809 | /*
|
---|
2810 | * LFENCE, SFENCE & MFENCE.
|
---|
2811 | */
|
---|
2812 |
|
---|
2813 | IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void))
|
---|
2814 | {
|
---|
2815 | ASMReadFence();
|
---|
2816 | }
|
---|
2817 |
|
---|
2818 |
|
---|
2819 | IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void))
|
---|
2820 | {
|
---|
2821 | ASMWriteFence();
|
---|
2822 | }
|
---|
2823 |
|
---|
2824 |
|
---|
2825 | IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void))
|
---|
2826 | {
|
---|
2827 | ASMMemoryFence();
|
---|
2828 | }
|
---|
2829 |
|
---|
2830 |
|
---|
2831 | # ifndef RT_ARCH_ARM64
|
---|
2832 | IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void))
|
---|
2833 | {
|
---|
2834 | ASMMemoryFence();
|
---|
2835 | }
|
---|
2836 | # endif
|
---|
2837 |
|
---|
2838 | # endif
|
---|
2839 |
|
---|
2840 | #endif /* !RT_ARCH_AMD64 || IEM_WITHOUT_ASSEMBLY */
|
---|
2841 |
|
---|
2842 |
|
---|
2843 | IEM_DECL_IMPL_DEF(void, iemAImpl_arpl,(uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pfEFlags))
|
---|
2844 | {
|
---|
2845 | if ((*pu16Dst & X86_SEL_RPL) < (u16Src & X86_SEL_RPL))
|
---|
2846 | {
|
---|
2847 | *pu16Dst &= X86_SEL_MASK_OFF_RPL;
|
---|
2848 | *pu16Dst |= u16Src & X86_SEL_RPL;
|
---|
2849 |
|
---|
2850 | *pfEFlags |= X86_EFL_ZF;
|
---|
2851 | }
|
---|
2852 | else
|
---|
2853 | *pfEFlags &= ~X86_EFL_ZF;
|
---|
2854 | }
|
---|
2855 |
|
---|
2856 |
|
---|
2857 | /*********************************************************************************************************************************
|
---|
2858 | * x87 FPU *
|
---|
2859 | *********************************************************************************************************************************/
|
---|
2860 | #if defined(IEM_WITHOUT_ASSEMBLY)
|
---|
2861 |
|
---|
2862 | IEM_DECL_IMPL_DEF(void, iemAImpl_f2xm1_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
|
---|
2863 | {
|
---|
2864 | RT_NOREF(pFpuState, pFpuRes, pr80Val);
|
---|
2865 | AssertReleaseFailed();
|
---|
2866 | }
|
---|
2867 |
|
---|
2868 |
|
---|
2869 | IEM_DECL_IMPL_DEF(void, iemAImpl_fabs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
|
---|
2870 | {
|
---|
2871 | RT_NOREF(pFpuState, pFpuRes, pr80Val);
|
---|
2872 | AssertReleaseFailed();
|
---|
2873 | }
|
---|
2874 |
|
---|
2875 |
|
---|
2876 | IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2877 | PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
|
---|
2878 | {
|
---|
2879 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
|
---|
2880 | AssertReleaseFailed();
|
---|
2881 | }
|
---|
2882 |
|
---|
2883 |
|
---|
2884 | IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2885 | PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
|
---|
2886 | {
|
---|
2887 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
|
---|
2888 | AssertReleaseFailed();
|
---|
2889 | }
|
---|
2890 |
|
---|
2891 |
|
---|
2892 | IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2893 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
2894 | {
|
---|
2895 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
2896 | AssertReleaseFailed();
|
---|
2897 | }
|
---|
2898 |
|
---|
2899 |
|
---|
2900 | IEM_DECL_IMPL_DEF(void, iemAImpl_fchs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
|
---|
2901 | {
|
---|
2902 | RT_NOREF(pFpuState, pFpuRes, pr80Val);
|
---|
2903 | AssertReleaseFailed();
|
---|
2904 | }
|
---|
2905 |
|
---|
2906 |
|
---|
2907 | IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r32,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
|
---|
2908 | PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
|
---|
2909 | {
|
---|
2910 | RT_NOREF(pFpuState, pFSW, pr80Val1, pr32Val2);
|
---|
2911 | AssertReleaseFailed();
|
---|
2912 | }
|
---|
2913 |
|
---|
2914 |
|
---|
2915 | IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
|
---|
2916 | PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
|
---|
2917 | {
|
---|
2918 | RT_NOREF(pFpuState, pFSW, pr80Val1, pr64Val2);
|
---|
2919 | AssertReleaseFailed();
|
---|
2920 | }
|
---|
2921 |
|
---|
2922 |
|
---|
2923 | IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
|
---|
2924 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
2925 | {
|
---|
2926 | RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
|
---|
2927 | AssertReleaseFailed();
|
---|
2928 | }
|
---|
2929 |
|
---|
2930 |
|
---|
2931 | IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fcomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
|
---|
2932 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
2933 | {
|
---|
2934 | RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
|
---|
2935 | AssertReleaseFailed();
|
---|
2936 | return 0;
|
---|
2937 | }
|
---|
2938 |
|
---|
2939 |
|
---|
2940 | IEM_DECL_IMPL_DEF(void, iemAImpl_fcos_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
|
---|
2941 | {
|
---|
2942 | RT_NOREF(pFpuState, pFpuRes, pr80Val);
|
---|
2943 | AssertReleaseFailed();
|
---|
2944 | }
|
---|
2945 |
|
---|
2946 |
|
---|
2947 | IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2948 | PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
|
---|
2949 | {
|
---|
2950 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
|
---|
2951 | AssertReleaseFailed();
|
---|
2952 | }
|
---|
2953 |
|
---|
2954 |
|
---|
2955 | IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2956 | PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
|
---|
2957 | {
|
---|
2958 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
|
---|
2959 | AssertReleaseFailed();
|
---|
2960 | }
|
---|
2961 |
|
---|
2962 |
|
---|
2963 | IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2964 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
2965 | {
|
---|
2966 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
2967 | AssertReleaseFailed();
|
---|
2968 | }
|
---|
2969 |
|
---|
2970 |
|
---|
2971 | IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2972 | PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
|
---|
2973 | {
|
---|
2974 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
|
---|
2975 | AssertReleaseFailed();
|
---|
2976 | }
|
---|
2977 |
|
---|
2978 |
|
---|
2979 | IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2980 | PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
|
---|
2981 | {
|
---|
2982 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
|
---|
2983 | AssertReleaseFailed();
|
---|
2984 | }
|
---|
2985 |
|
---|
2986 |
|
---|
2987 | IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2988 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
2989 | {
|
---|
2990 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
2991 | AssertReleaseFailed();
|
---|
2992 | }
|
---|
2993 |
|
---|
2994 |
|
---|
2995 | IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
2996 | PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
|
---|
2997 | {
|
---|
2998 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
|
---|
2999 | AssertReleaseFailed();
|
---|
3000 | }
|
---|
3001 |
|
---|
3002 |
|
---|
3003 | IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3004 | PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
|
---|
3005 | {
|
---|
3006 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
|
---|
3007 | AssertReleaseFailed();
|
---|
3008 | }
|
---|
3009 |
|
---|
3010 |
|
---|
3011 | IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
|
---|
3012 | PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
|
---|
3013 | {
|
---|
3014 | RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi16Val2);
|
---|
3015 | AssertReleaseFailed();
|
---|
3016 | }
|
---|
3017 |
|
---|
3018 |
|
---|
3019 | IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
|
---|
3020 | PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
|
---|
3021 | {
|
---|
3022 | RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi32Val2);
|
---|
3023 | AssertReleaseFailed();
|
---|
3024 | }
|
---|
3025 |
|
---|
3026 |
|
---|
3027 | IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3028 | PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
|
---|
3029 | {
|
---|
3030 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
|
---|
3031 | AssertReleaseFailed();
|
---|
3032 | }
|
---|
3033 |
|
---|
3034 |
|
---|
3035 | IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3036 | PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
|
---|
3037 | {
|
---|
3038 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
|
---|
3039 | AssertReleaseFailed();
|
---|
3040 | }
|
---|
3041 |
|
---|
3042 |
|
---|
3043 | IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3044 | PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
|
---|
3045 | {
|
---|
3046 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
|
---|
3047 | AssertReleaseFailed();
|
---|
3048 | }
|
---|
3049 |
|
---|
3050 |
|
---|
3051 | IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3052 | PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
|
---|
3053 | {
|
---|
3054 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
|
---|
3055 | AssertReleaseFailed();
|
---|
3056 | }
|
---|
3057 |
|
---|
3058 |
|
---|
3059 | IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val))
|
---|
3060 | {
|
---|
3061 | RT_NOREF(pFpuState, pFpuRes, pi16Val);
|
---|
3062 | AssertReleaseFailed();
|
---|
3063 | }
|
---|
3064 |
|
---|
3065 |
|
---|
3066 | IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val))
|
---|
3067 | {
|
---|
3068 | RT_NOREF(pFpuState, pFpuRes, pi32Val);
|
---|
3069 | AssertReleaseFailed();
|
---|
3070 | }
|
---|
3071 |
|
---|
3072 |
|
---|
3073 | IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val))
|
---|
3074 | {
|
---|
3075 | RT_NOREF(pFpuState, pFpuRes, pi64Val);
|
---|
3076 | AssertReleaseFailed();
|
---|
3077 | }
|
---|
3078 |
|
---|
3079 |
|
---|
3080 | IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3081 | PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
|
---|
3082 | {
|
---|
3083 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
|
---|
3084 | AssertReleaseFailed();
|
---|
3085 | }
|
---|
3086 |
|
---|
3087 |
|
---|
3088 | IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3089 | PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
|
---|
3090 | {
|
---|
3091 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
|
---|
3092 | AssertReleaseFailed();
|
---|
3093 | }
|
---|
3094 |
|
---|
3095 |
|
---|
3096 | IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3097 | int16_t *pi16Val, PCRTFLOAT80U pr80Val))
|
---|
3098 | {
|
---|
3099 | RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
|
---|
3100 | AssertReleaseFailed();
|
---|
3101 | }
|
---|
3102 |
|
---|
3103 |
|
---|
3104 | IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3105 | int32_t *pi32Val, PCRTFLOAT80U pr80Val))
|
---|
3106 | {
|
---|
3107 | RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
|
---|
3108 | AssertReleaseFailed();
|
---|
3109 | }
|
---|
3110 |
|
---|
3111 |
|
---|
3112 | IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3113 | int64_t *pi64Val, PCRTFLOAT80U pr80Val))
|
---|
3114 | {
|
---|
3115 | RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
|
---|
3116 | AssertReleaseFailed();
|
---|
3117 | }
|
---|
3118 |
|
---|
3119 |
|
---|
3120 | IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3121 | int16_t *pi16Val, PCRTFLOAT80U pr80Val))
|
---|
3122 | {
|
---|
3123 | RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
|
---|
3124 | AssertReleaseFailed();
|
---|
3125 | }
|
---|
3126 |
|
---|
3127 |
|
---|
3128 | IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3129 | int32_t *pi32Val, PCRTFLOAT80U pr80Val))
|
---|
3130 | {
|
---|
3131 | RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
|
---|
3132 | AssertReleaseFailed();
|
---|
3133 | }
|
---|
3134 |
|
---|
3135 |
|
---|
3136 | IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3137 | int64_t *pi64Val, PCRTFLOAT80U pr80Val))
|
---|
3138 | {
|
---|
3139 | RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
|
---|
3140 | AssertReleaseFailed();
|
---|
3141 | }
|
---|
3142 |
|
---|
3143 |
|
---|
3144 | IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3145 | PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
|
---|
3146 | {
|
---|
3147 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
|
---|
3148 | AssertReleaseFailed();
|
---|
3149 | }
|
---|
3150 |
|
---|
3151 |
|
---|
3152 | IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3153 | PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
|
---|
3154 | {
|
---|
3155 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
|
---|
3156 | AssertReleaseFailed();
|
---|
3157 | }
|
---|
3158 |
|
---|
3159 |
|
---|
3160 | IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3161 | PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
|
---|
3162 | {
|
---|
3163 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
|
---|
3164 | AssertReleaseFailed();
|
---|
3165 | }
|
---|
3166 |
|
---|
3167 |
|
---|
3168 | IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3169 | PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
|
---|
3170 | {
|
---|
3171 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
|
---|
3172 | AssertReleaseFailed();
|
---|
3173 | }
|
---|
3174 |
|
---|
3175 |
|
---|
3176 | IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val))
|
---|
3177 | {
|
---|
3178 | RT_NOREF(pFpuState, pFpuRes, pr32Val);
|
---|
3179 | AssertReleaseFailed();
|
---|
3180 | }
|
---|
3181 |
|
---|
3182 |
|
---|
3183 | IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val))
|
---|
3184 | {
|
---|
3185 | RT_NOREF(pFpuState, pFpuRes, pr64Val);
|
---|
3186 | AssertReleaseFailed();
|
---|
3187 | }
|
---|
3188 |
|
---|
3189 | IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
|
---|
3190 | {
|
---|
3191 | RT_NOREF(pFpuState, pFpuRes, pr80Val);
|
---|
3192 | AssertReleaseFailed();
|
---|
3193 | }
|
---|
3194 |
|
---|
3195 |
|
---|
3196 | IEM_DECL_IMPL_DEF(void, iemAImpl_fld1,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
|
---|
3197 | {
|
---|
3198 | RT_NOREF(pFpuState, pFpuRes);
|
---|
3199 | AssertReleaseFailed();
|
---|
3200 | }
|
---|
3201 |
|
---|
3202 |
|
---|
3203 | IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2e,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
|
---|
3204 | {
|
---|
3205 | RT_NOREF(pFpuState, pFpuRes);
|
---|
3206 | AssertReleaseFailed();
|
---|
3207 | }
|
---|
3208 |
|
---|
3209 |
|
---|
3210 | IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2t,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
|
---|
3211 | {
|
---|
3212 | RT_NOREF(pFpuState, pFpuRes);
|
---|
3213 | AssertReleaseFailed();
|
---|
3214 | }
|
---|
3215 |
|
---|
3216 |
|
---|
3217 | IEM_DECL_IMPL_DEF(void, iemAImpl_fldlg2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
|
---|
3218 | {
|
---|
3219 | RT_NOREF(pFpuState, pFpuRes);
|
---|
3220 | AssertReleaseFailed();
|
---|
3221 | }
|
---|
3222 |
|
---|
3223 |
|
---|
3224 | IEM_DECL_IMPL_DEF(void, iemAImpl_fldln2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
|
---|
3225 | {
|
---|
3226 | RT_NOREF(pFpuState, pFpuRes);
|
---|
3227 | AssertReleaseFailed();
|
---|
3228 | }
|
---|
3229 |
|
---|
3230 |
|
---|
3231 | IEM_DECL_IMPL_DEF(void, iemAImpl_fldpi,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
|
---|
3232 | {
|
---|
3233 | RT_NOREF(pFpuState, pFpuRes);
|
---|
3234 | AssertReleaseFailed();
|
---|
3235 | }
|
---|
3236 |
|
---|
3237 |
|
---|
3238 | IEM_DECL_IMPL_DEF(void, iemAImpl_fldz,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
|
---|
3239 | {
|
---|
3240 | RT_NOREF(pFpuState, pFpuRes);
|
---|
3241 | AssertReleaseFailed();
|
---|
3242 | }
|
---|
3243 |
|
---|
3244 |
|
---|
3245 | IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3246 | PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
|
---|
3247 | {
|
---|
3248 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
|
---|
3249 | AssertReleaseFailed();
|
---|
3250 | }
|
---|
3251 |
|
---|
3252 |
|
---|
3253 | IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3254 | PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
|
---|
3255 | {
|
---|
3256 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
|
---|
3257 | AssertReleaseFailed();
|
---|
3258 | }
|
---|
3259 |
|
---|
3260 |
|
---|
3261 | IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3262 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3263 | {
|
---|
3264 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3265 | AssertReleaseFailed();
|
---|
3266 | }
|
---|
3267 |
|
---|
3268 |
|
---|
3269 | IEM_DECL_IMPL_DEF(void, iemAImpl_fpatan_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3270 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3271 | {
|
---|
3272 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3273 | AssertReleaseFailed();
|
---|
3274 | }
|
---|
3275 |
|
---|
3276 |
|
---|
3277 | IEM_DECL_IMPL_DEF(void, iemAImpl_fprem_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3278 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3279 | {
|
---|
3280 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3281 | AssertReleaseFailed();
|
---|
3282 | }
|
---|
3283 |
|
---|
3284 |
|
---|
3285 | IEM_DECL_IMPL_DEF(void, iemAImpl_fprem1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3286 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3287 | {
|
---|
3288 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3289 | AssertReleaseFailed();
|
---|
3290 | }
|
---|
3291 |
|
---|
3292 |
|
---|
3293 | IEM_DECL_IMPL_DEF(void, iemAImpl_fptan_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
|
---|
3294 | {
|
---|
3295 | RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
|
---|
3296 | AssertReleaseFailed();
|
---|
3297 | }
|
---|
3298 |
|
---|
3299 |
|
---|
3300 | IEM_DECL_IMPL_DEF(void, iemAImpl_frndint_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
|
---|
3301 | {
|
---|
3302 | RT_NOREF(pFpuState, pFpuRes, pr80Val);
|
---|
3303 | AssertReleaseFailed();
|
---|
3304 | }
|
---|
3305 |
|
---|
3306 |
|
---|
3307 | IEM_DECL_IMPL_DEF(void, iemAImpl_fscale_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3308 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3309 | {
|
---|
3310 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3311 | AssertReleaseFailed();
|
---|
3312 | }
|
---|
3313 |
|
---|
3314 |
|
---|
3315 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsin_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
|
---|
3316 | {
|
---|
3317 | RT_NOREF(pFpuState, pFpuRes, pr80Val);
|
---|
3318 | AssertReleaseFailed();
|
---|
3319 | }
|
---|
3320 |
|
---|
3321 |
|
---|
3322 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsincos_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
|
---|
3323 | {
|
---|
3324 | RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
|
---|
3325 | AssertReleaseFailed();
|
---|
3326 | }
|
---|
3327 |
|
---|
3328 |
|
---|
3329 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsqrt_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
|
---|
3330 | {
|
---|
3331 | RT_NOREF(pFpuState, pFpuRes, pr80Val);
|
---|
3332 | AssertReleaseFailed();
|
---|
3333 | }
|
---|
3334 |
|
---|
3335 |
|
---|
3336 | IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3337 | PRTFLOAT32U pr32Dst, PCRTFLOAT80U pr80Src))
|
---|
3338 | {
|
---|
3339 | RT_NOREF(pFpuState, pu16FSW, pr32Dst, pr80Src);
|
---|
3340 | AssertReleaseFailed();
|
---|
3341 | }
|
---|
3342 |
|
---|
3343 |
|
---|
3344 | IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3345 | PRTFLOAT64U pr64Dst, PCRTFLOAT80U pr80Src))
|
---|
3346 | {
|
---|
3347 | RT_NOREF(pFpuState, pu16FSW, pr64Dst, pr80Src);
|
---|
3348 | AssertReleaseFailed();
|
---|
3349 | }
|
---|
3350 |
|
---|
3351 |
|
---|
3352 | IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3353 | PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src))
|
---|
3354 | {
|
---|
3355 | RT_NOREF(pFpuState, pu16FSW, pr80Dst, pr80Src);
|
---|
3356 | AssertReleaseFailed();
|
---|
3357 | }
|
---|
3358 |
|
---|
3359 |
|
---|
3360 | IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
|
---|
3361 | PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src))
|
---|
3362 | {
|
---|
3363 | RT_NOREF(pFpuState, pu16FSW, pd80Dst, pr80Src);
|
---|
3364 | AssertReleaseFailed();
|
---|
3365 | }
|
---|
3366 |
|
---|
3367 |
|
---|
3368 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3369 | PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
|
---|
3370 | {
|
---|
3371 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
|
---|
3372 | AssertReleaseFailed();
|
---|
3373 | }
|
---|
3374 |
|
---|
3375 |
|
---|
3376 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3377 | PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
|
---|
3378 | {
|
---|
3379 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
|
---|
3380 | AssertReleaseFailed();
|
---|
3381 | }
|
---|
3382 |
|
---|
3383 |
|
---|
3384 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3385 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3386 | {
|
---|
3387 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3388 | AssertReleaseFailed();
|
---|
3389 | }
|
---|
3390 |
|
---|
3391 |
|
---|
3392 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3393 | PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
|
---|
3394 | {
|
---|
3395 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
|
---|
3396 | AssertReleaseFailed();
|
---|
3397 | }
|
---|
3398 |
|
---|
3399 |
|
---|
3400 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3401 | PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
|
---|
3402 | {
|
---|
3403 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
|
---|
3404 | AssertReleaseFailed();
|
---|
3405 | }
|
---|
3406 |
|
---|
3407 |
|
---|
3408 | IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3409 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3410 | {
|
---|
3411 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3412 | AssertReleaseFailed();
|
---|
3413 | }
|
---|
3414 |
|
---|
3415 |
|
---|
3416 | IEM_DECL_IMPL_DEF(void, iemAImpl_ftst_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
|
---|
3417 | {
|
---|
3418 | RT_NOREF(pFpuState, pu16Fsw, pr80Val);
|
---|
3419 | AssertReleaseFailed();
|
---|
3420 | }
|
---|
3421 |
|
---|
3422 |
|
---|
3423 | IEM_DECL_IMPL_DEF(void, iemAImpl_fucom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
|
---|
3424 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3425 | {
|
---|
3426 | RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
|
---|
3427 | AssertReleaseFailed();
|
---|
3428 | }
|
---|
3429 |
|
---|
3430 |
|
---|
3431 | IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fucomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
|
---|
3432 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3433 | {
|
---|
3434 | RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pr80Val2);
|
---|
3435 | AssertReleaseFailed();
|
---|
3436 | return 0;
|
---|
3437 | }
|
---|
3438 |
|
---|
3439 |
|
---|
3440 | IEM_DECL_IMPL_DEF(void, iemAImpl_fxam_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
|
---|
3441 | {
|
---|
3442 | RT_NOREF(pFpuState, pu16Fsw, pr80Val);
|
---|
3443 | AssertReleaseFailed();
|
---|
3444 | }
|
---|
3445 |
|
---|
3446 |
|
---|
3447 | IEM_DECL_IMPL_DEF(void, iemAImpl_fxtract_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
|
---|
3448 | {
|
---|
3449 | RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
|
---|
3450 | AssertReleaseFailed();
|
---|
3451 | }
|
---|
3452 |
|
---|
3453 |
|
---|
3454 | IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2x_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3455 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3456 | {
|
---|
3457 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3458 | AssertReleaseFailed();
|
---|
3459 | }
|
---|
3460 |
|
---|
3461 |
|
---|
3462 | IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2xp1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
|
---|
3463 | PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
|
---|
3464 | {
|
---|
3465 | RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
|
---|
3466 | AssertReleaseFailed();
|
---|
3467 | }
|
---|
3468 |
|
---|
3469 | #endif /* IEM_WITHOUT_ASSEMBLY */
|
---|
3470 |
|
---|
3471 |
|
---|
3472 | /*********************************************************************************************************************************
|
---|
3473 | * MMX, SSE & AVX *
|
---|
3474 | *********************************************************************************************************************************/
|
---|
3475 |
|
---|
3476 | IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
|
---|
3477 | {
|
---|
3478 | RT_NOREF(pFpuState);
|
---|
3479 | puDst->au32[0] = puSrc->au32[0];
|
---|
3480 | puDst->au32[1] = puSrc->au32[0];
|
---|
3481 | puDst->au32[2] = puSrc->au32[2];
|
---|
3482 | puDst->au32[3] = puSrc->au32[2];
|
---|
3483 | }
|
---|
3484 |
|
---|
3485 | #ifdef IEM_WITH_VEX
|
---|
3486 |
|
---|
3487 | IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
|
---|
3488 | {
|
---|
3489 | pXState->x87.aXMM[iYRegDst].au32[0] = pXState->x87.aXMM[iYRegSrc].au32[0];
|
---|
3490 | pXState->x87.aXMM[iYRegDst].au32[1] = pXState->x87.aXMM[iYRegSrc].au32[0];
|
---|
3491 | pXState->x87.aXMM[iYRegDst].au32[2] = pXState->x87.aXMM[iYRegSrc].au32[2];
|
---|
3492 | pXState->x87.aXMM[iYRegDst].au32[3] = pXState->x87.aXMM[iYRegSrc].au32[2];
|
---|
3493 | pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
|
---|
3494 | pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
|
---|
3495 | pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
|
---|
3496 | pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
|
---|
3497 | }
|
---|
3498 |
|
---|
3499 |
|
---|
3500 | IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
|
---|
3501 | {
|
---|
3502 | pXState->x87.aXMM[iYRegDst].au32[0] = pSrc->au32[0];
|
---|
3503 | pXState->x87.aXMM[iYRegDst].au32[1] = pSrc->au32[0];
|
---|
3504 | pXState->x87.aXMM[iYRegDst].au32[2] = pSrc->au32[2];
|
---|
3505 | pXState->x87.aXMM[iYRegDst].au32[3] = pSrc->au32[2];
|
---|
3506 | pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pSrc->au32[4];
|
---|
3507 | pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pSrc->au32[4];
|
---|
3508 | pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pSrc->au32[6];
|
---|
3509 | pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pSrc->au32[6];
|
---|
3510 | }
|
---|
3511 |
|
---|
3512 | #endif /* IEM_WITH_VEX */
|
---|
3513 |
|
---|
3514 |
|
---|
3515 | IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
|
---|
3516 | {
|
---|
3517 | RT_NOREF(pFpuState);
|
---|
3518 | puDst->au32[0] = puSrc->au32[1];
|
---|
3519 | puDst->au32[1] = puSrc->au32[1];
|
---|
3520 | puDst->au32[2] = puSrc->au32[3];
|
---|
3521 | puDst->au32[3] = puSrc->au32[3];
|
---|
3522 | }
|
---|
3523 |
|
---|
3524 |
|
---|
3525 | IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc))
|
---|
3526 | {
|
---|
3527 | RT_NOREF(pFpuState);
|
---|
3528 | puDst->au64[0] = uSrc;
|
---|
3529 | puDst->au64[1] = uSrc;
|
---|
3530 | }
|
---|
3531 |
|
---|
3532 | #ifdef IEM_WITH_VEX
|
---|
3533 |
|
---|
3534 | IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
|
---|
3535 | {
|
---|
3536 | pXState->x87.aXMM[iYRegDst].au64[0] = pXState->x87.aXMM[iYRegSrc].au64[0];
|
---|
3537 | pXState->x87.aXMM[iYRegDst].au64[1] = pXState->x87.aXMM[iYRegSrc].au64[0];
|
---|
3538 | pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
|
---|
3539 | pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
|
---|
3540 | }
|
---|
3541 |
|
---|
3542 | IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
|
---|
3543 | {
|
---|
3544 | pXState->x87.aXMM[iYRegDst].au64[0] = pSrc->au64[0];
|
---|
3545 | pXState->x87.aXMM[iYRegDst].au64[1] = pSrc->au64[0];
|
---|
3546 | pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pSrc->au64[2];
|
---|
3547 | pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pSrc->au64[2];
|
---|
3548 | }
|
---|
3549 |
|
---|
3550 | #endif /* IEM_WITH_VEX */
|
---|
3551 |
|
---|
3552 | #ifdef IEM_WITHOUT_ASSEMBLY
|
---|
3553 |
|
---|
3554 | IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
|
---|
3555 | {
|
---|
3556 | RT_NOREF(pFpuState, pu64Dst, pu64Src);
|
---|
3557 | AssertReleaseFailed();
|
---|
3558 | }
|
---|
3559 |
|
---|
3560 |
|
---|
3561 | IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
|
---|
3562 | {
|
---|
3563 | RT_NOREF(pFpuState, pu128Dst, pu128Src);
|
---|
3564 | AssertReleaseFailed();
|
---|
3565 | }
|
---|
3566 |
|
---|
3567 |
|
---|
3568 | IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
|
---|
3569 | {
|
---|
3570 | RT_NOREF(pFpuState, pu64Dst, pu64Src);
|
---|
3571 | AssertReleaseFailed();
|
---|
3572 | }
|
---|
3573 |
|
---|
3574 |
|
---|
3575 | IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
|
---|
3576 | {
|
---|
3577 | RT_NOREF(pFpuState, pu128Dst, pu128Src);
|
---|
3578 | AssertReleaseFailed();
|
---|
3579 | }
|
---|
3580 |
|
---|
3581 |
|
---|
3582 | IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
|
---|
3583 | {
|
---|
3584 | RT_NOREF(pFpuState, pu64Dst, pu64Src);
|
---|
3585 | AssertReleaseFailed();
|
---|
3586 | }
|
---|
3587 |
|
---|
3588 |
|
---|
3589 | IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
|
---|
3590 | {
|
---|
3591 | RT_NOREF(pFpuState, pu128Dst, pu128Src);
|
---|
3592 | AssertReleaseFailed();
|
---|
3593 | }
|
---|
3594 |
|
---|
3595 |
|
---|
3596 | IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
|
---|
3597 | {
|
---|
3598 | RT_NOREF(pFpuState, pu64Dst, pu64Src);
|
---|
3599 | AssertReleaseFailed();
|
---|
3600 | }
|
---|
3601 |
|
---|
3602 |
|
---|
3603 | IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
|
---|
3604 | {
|
---|
3605 | RT_NOREF(pFpuState, pu128Dst, pu128Src);
|
---|
3606 | AssertReleaseFailed();
|
---|
3607 | }
|
---|
3608 |
|
---|
3609 |
|
---|
3610 | IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
|
---|
3611 | {
|
---|
3612 | RT_NOREF(pFpuState, pu64Dst, pu64Src);
|
---|
3613 | AssertReleaseFailed();
|
---|
3614 |
|
---|
3615 | }
|
---|
3616 |
|
---|
3617 |
|
---|
3618 | IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src))
|
---|
3619 | {
|
---|
3620 | RT_NOREF(pFpuState, pu64Dst, pu128Src);
|
---|
3621 | AssertReleaseFailed();
|
---|
3622 | }
|
---|
3623 |
|
---|
3624 |
|
---|
3625 | IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src, uint8_t bEvil))
|
---|
3626 | {
|
---|
3627 | RT_NOREF(pFpuState, pu64Dst, pu64Src, bEvil);
|
---|
3628 | AssertReleaseFailed();
|
---|
3629 | }
|
---|
3630 |
|
---|
3631 |
|
---|
3632 | IEM_DECL_IMPL_DEF(void, iemAImpl_pshufhw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
|
---|
3633 | {
|
---|
3634 | RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
|
---|
3635 | AssertReleaseFailed();
|
---|
3636 | }
|
---|
3637 |
|
---|
3638 |
|
---|
3639 | IEM_DECL_IMPL_DEF(void, iemAImpl_pshuflw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
|
---|
3640 | {
|
---|
3641 | RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
|
---|
3642 | AssertReleaseFailed();
|
---|
3643 | }
|
---|
3644 |
|
---|
3645 |
|
---|
3646 | IEM_DECL_IMPL_DEF(void, iemAImpl_pshufd,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
|
---|
3647 | {
|
---|
3648 | RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
|
---|
3649 | AssertReleaseFailed();
|
---|
3650 | }
|
---|
3651 |
|
---|
3652 | /* PUNPCKHxxx */
|
---|
3653 |
|
---|
3654 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
|
---|
3655 | {
|
---|
3656 | RT_NOREF(pFpuState, pu64Dst, pu64Src);
|
---|
3657 | AssertReleaseFailed();
|
---|
3658 | }
|
---|
3659 |
|
---|
3660 |
|
---|
3661 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
|
---|
3662 | {
|
---|
3663 | RT_NOREF(pFpuState, pu128Dst, pu128Src);
|
---|
3664 | AssertReleaseFailed();
|
---|
3665 | }
|
---|
3666 |
|
---|
3667 |
|
---|
3668 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
|
---|
3669 | {
|
---|
3670 | RT_NOREF(pFpuState, pu64Dst, pu64Src);
|
---|
3671 | AssertReleaseFailed();
|
---|
3672 | }
|
---|
3673 |
|
---|
3674 |
|
---|
3675 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
|
---|
3676 | {
|
---|
3677 | RT_NOREF(pFpuState, pu128Dst, pu128Src);
|
---|
3678 | AssertReleaseFailed();
|
---|
3679 | }
|
---|
3680 |
|
---|
3681 |
|
---|
3682 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
|
---|
3683 | {
|
---|
3684 | RT_NOREF(pFpuState, pu64Dst, pu64Src);
|
---|
3685 | AssertReleaseFailed();
|
---|
3686 | }
|
---|
3687 |
|
---|
3688 |
|
---|
3689 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
|
---|
3690 | {
|
---|
3691 | RT_NOREF(pFpuState, pu128Dst, pu128Src);
|
---|
3692 | AssertReleaseFailed();
|
---|
3693 | }
|
---|
3694 |
|
---|
3695 |
|
---|
3696 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
|
---|
3697 | {
|
---|
3698 | RT_NOREF(pFpuState, pu128Dst, pu128Src);
|
---|
3699 | AssertReleaseFailed();
|
---|
3700 | }
|
---|
3701 |
|
---|
3702 | /* PUNPCKLxxx */
|
---|
3703 |
|
---|
3704 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
|
---|
3705 | {
|
---|
3706 | RT_NOREF(pFpuState, pu64Dst, pu32Src);
|
---|
3707 | AssertReleaseFailed();
|
---|
3708 | }
|
---|
3709 |
|
---|
3710 |
|
---|
3711 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
|
---|
3712 | {
|
---|
3713 | RT_NOREF(pFpuState, pu128Dst, pu64Src);
|
---|
3714 | AssertReleaseFailed();
|
---|
3715 | }
|
---|
3716 |
|
---|
3717 |
|
---|
3718 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
|
---|
3719 | {
|
---|
3720 | RT_NOREF(pFpuState, pu64Dst, pu32Src);
|
---|
3721 | AssertReleaseFailed();
|
---|
3722 | }
|
---|
3723 |
|
---|
3724 |
|
---|
3725 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
|
---|
3726 | {
|
---|
3727 | RT_NOREF(pFpuState, pu128Dst, pu64Src);
|
---|
3728 | AssertReleaseFailed();
|
---|
3729 | }
|
---|
3730 |
|
---|
3731 |
|
---|
3732 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
|
---|
3733 | {
|
---|
3734 | RT_NOREF(pFpuState, pu64Dst, pu32Src);
|
---|
3735 | AssertReleaseFailed();
|
---|
3736 | }
|
---|
3737 |
|
---|
3738 |
|
---|
3739 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
|
---|
3740 | {
|
---|
3741 | RT_NOREF(pFpuState, pu128Dst, pu64Src);
|
---|
3742 | AssertReleaseFailed();
|
---|
3743 | }
|
---|
3744 |
|
---|
3745 |
|
---|
3746 | IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
|
---|
3747 | {
|
---|
3748 | RT_NOREF(pFpuState, pu128Dst, pu64Src);
|
---|
3749 | AssertReleaseFailed();
|
---|
3750 | }
|
---|
3751 |
|
---|
3752 | #endif /* IEM_WITHOUT_ASSEMBLY */
|
---|