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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp@ 93554

Last change on this file since 93554 was 93115, checked in by vboxsync, 3 years ago

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1/* $Id: IEMAllAImplC.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in Assembly, portable C variant.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#include "IEMInternal.h"
23#include <VBox/vmm/vmcc.h>
24#include <VBox/err.h>
25#include <iprt/x86.h>
26#include <iprt/uint128.h>
27
28
29/*********************************************************************************************************************************
30* Global Variables *
31*********************************************************************************************************************************/
32#ifdef RT_ARCH_X86
33/**
34 * Parity calculation table.
35 *
36 * The generator code:
37 * @code
38 * #include <stdio.h>
39 *
40 * int main()
41 * {
42 * unsigned b;
43 * for (b = 0; b < 256; b++)
44 * {
45 * int cOnes = ( b & 1)
46 * + ((b >> 1) & 1)
47 * + ((b >> 2) & 1)
48 * + ((b >> 3) & 1)
49 * + ((b >> 4) & 1)
50 * + ((b >> 5) & 1)
51 * + ((b >> 6) & 1)
52 * + ((b >> 7) & 1);
53 * printf(" /" "* %#04x = %u%u%u%u%u%u%u%ub *" "/ %s,\n",
54 * b,
55 * (b >> 7) & 1,
56 * (b >> 6) & 1,
57 * (b >> 5) & 1,
58 * (b >> 4) & 1,
59 * (b >> 3) & 1,
60 * (b >> 2) & 1,
61 * (b >> 1) & 1,
62 * b & 1,
63 * cOnes & 1 ? "0" : "X86_EFL_PF");
64 * }
65 * return 0;
66 * }
67 * @endcode
68 */
69static uint8_t const g_afParity[256] =
70{
71 /* 0000 = 00000000b */ X86_EFL_PF,
72 /* 0x01 = 00000001b */ 0,
73 /* 0x02 = 00000010b */ 0,
74 /* 0x03 = 00000011b */ X86_EFL_PF,
75 /* 0x04 = 00000100b */ 0,
76 /* 0x05 = 00000101b */ X86_EFL_PF,
77 /* 0x06 = 00000110b */ X86_EFL_PF,
78 /* 0x07 = 00000111b */ 0,
79 /* 0x08 = 00001000b */ 0,
80 /* 0x09 = 00001001b */ X86_EFL_PF,
81 /* 0x0a = 00001010b */ X86_EFL_PF,
82 /* 0x0b = 00001011b */ 0,
83 /* 0x0c = 00001100b */ X86_EFL_PF,
84 /* 0x0d = 00001101b */ 0,
85 /* 0x0e = 00001110b */ 0,
86 /* 0x0f = 00001111b */ X86_EFL_PF,
87 /* 0x10 = 00010000b */ 0,
88 /* 0x11 = 00010001b */ X86_EFL_PF,
89 /* 0x12 = 00010010b */ X86_EFL_PF,
90 /* 0x13 = 00010011b */ 0,
91 /* 0x14 = 00010100b */ X86_EFL_PF,
92 /* 0x15 = 00010101b */ 0,
93 /* 0x16 = 00010110b */ 0,
94 /* 0x17 = 00010111b */ X86_EFL_PF,
95 /* 0x18 = 00011000b */ X86_EFL_PF,
96 /* 0x19 = 00011001b */ 0,
97 /* 0x1a = 00011010b */ 0,
98 /* 0x1b = 00011011b */ X86_EFL_PF,
99 /* 0x1c = 00011100b */ 0,
100 /* 0x1d = 00011101b */ X86_EFL_PF,
101 /* 0x1e = 00011110b */ X86_EFL_PF,
102 /* 0x1f = 00011111b */ 0,
103 /* 0x20 = 00100000b */ 0,
104 /* 0x21 = 00100001b */ X86_EFL_PF,
105 /* 0x22 = 00100010b */ X86_EFL_PF,
106 /* 0x23 = 00100011b */ 0,
107 /* 0x24 = 00100100b */ X86_EFL_PF,
108 /* 0x25 = 00100101b */ 0,
109 /* 0x26 = 00100110b */ 0,
110 /* 0x27 = 00100111b */ X86_EFL_PF,
111 /* 0x28 = 00101000b */ X86_EFL_PF,
112 /* 0x29 = 00101001b */ 0,
113 /* 0x2a = 00101010b */ 0,
114 /* 0x2b = 00101011b */ X86_EFL_PF,
115 /* 0x2c = 00101100b */ 0,
116 /* 0x2d = 00101101b */ X86_EFL_PF,
117 /* 0x2e = 00101110b */ X86_EFL_PF,
118 /* 0x2f = 00101111b */ 0,
119 /* 0x30 = 00110000b */ X86_EFL_PF,
120 /* 0x31 = 00110001b */ 0,
121 /* 0x32 = 00110010b */ 0,
122 /* 0x33 = 00110011b */ X86_EFL_PF,
123 /* 0x34 = 00110100b */ 0,
124 /* 0x35 = 00110101b */ X86_EFL_PF,
125 /* 0x36 = 00110110b */ X86_EFL_PF,
126 /* 0x37 = 00110111b */ 0,
127 /* 0x38 = 00111000b */ 0,
128 /* 0x39 = 00111001b */ X86_EFL_PF,
129 /* 0x3a = 00111010b */ X86_EFL_PF,
130 /* 0x3b = 00111011b */ 0,
131 /* 0x3c = 00111100b */ X86_EFL_PF,
132 /* 0x3d = 00111101b */ 0,
133 /* 0x3e = 00111110b */ 0,
134 /* 0x3f = 00111111b */ X86_EFL_PF,
135 /* 0x40 = 01000000b */ 0,
136 /* 0x41 = 01000001b */ X86_EFL_PF,
137 /* 0x42 = 01000010b */ X86_EFL_PF,
138 /* 0x43 = 01000011b */ 0,
139 /* 0x44 = 01000100b */ X86_EFL_PF,
140 /* 0x45 = 01000101b */ 0,
141 /* 0x46 = 01000110b */ 0,
142 /* 0x47 = 01000111b */ X86_EFL_PF,
143 /* 0x48 = 01001000b */ X86_EFL_PF,
144 /* 0x49 = 01001001b */ 0,
145 /* 0x4a = 01001010b */ 0,
146 /* 0x4b = 01001011b */ X86_EFL_PF,
147 /* 0x4c = 01001100b */ 0,
148 /* 0x4d = 01001101b */ X86_EFL_PF,
149 /* 0x4e = 01001110b */ X86_EFL_PF,
150 /* 0x4f = 01001111b */ 0,
151 /* 0x50 = 01010000b */ X86_EFL_PF,
152 /* 0x51 = 01010001b */ 0,
153 /* 0x52 = 01010010b */ 0,
154 /* 0x53 = 01010011b */ X86_EFL_PF,
155 /* 0x54 = 01010100b */ 0,
156 /* 0x55 = 01010101b */ X86_EFL_PF,
157 /* 0x56 = 01010110b */ X86_EFL_PF,
158 /* 0x57 = 01010111b */ 0,
159 /* 0x58 = 01011000b */ 0,
160 /* 0x59 = 01011001b */ X86_EFL_PF,
161 /* 0x5a = 01011010b */ X86_EFL_PF,
162 /* 0x5b = 01011011b */ 0,
163 /* 0x5c = 01011100b */ X86_EFL_PF,
164 /* 0x5d = 01011101b */ 0,
165 /* 0x5e = 01011110b */ 0,
166 /* 0x5f = 01011111b */ X86_EFL_PF,
167 /* 0x60 = 01100000b */ X86_EFL_PF,
168 /* 0x61 = 01100001b */ 0,
169 /* 0x62 = 01100010b */ 0,
170 /* 0x63 = 01100011b */ X86_EFL_PF,
171 /* 0x64 = 01100100b */ 0,
172 /* 0x65 = 01100101b */ X86_EFL_PF,
173 /* 0x66 = 01100110b */ X86_EFL_PF,
174 /* 0x67 = 01100111b */ 0,
175 /* 0x68 = 01101000b */ 0,
176 /* 0x69 = 01101001b */ X86_EFL_PF,
177 /* 0x6a = 01101010b */ X86_EFL_PF,
178 /* 0x6b = 01101011b */ 0,
179 /* 0x6c = 01101100b */ X86_EFL_PF,
180 /* 0x6d = 01101101b */ 0,
181 /* 0x6e = 01101110b */ 0,
182 /* 0x6f = 01101111b */ X86_EFL_PF,
183 /* 0x70 = 01110000b */ 0,
184 /* 0x71 = 01110001b */ X86_EFL_PF,
185 /* 0x72 = 01110010b */ X86_EFL_PF,
186 /* 0x73 = 01110011b */ 0,
187 /* 0x74 = 01110100b */ X86_EFL_PF,
188 /* 0x75 = 01110101b */ 0,
189 /* 0x76 = 01110110b */ 0,
190 /* 0x77 = 01110111b */ X86_EFL_PF,
191 /* 0x78 = 01111000b */ X86_EFL_PF,
192 /* 0x79 = 01111001b */ 0,
193 /* 0x7a = 01111010b */ 0,
194 /* 0x7b = 01111011b */ X86_EFL_PF,
195 /* 0x7c = 01111100b */ 0,
196 /* 0x7d = 01111101b */ X86_EFL_PF,
197 /* 0x7e = 01111110b */ X86_EFL_PF,
198 /* 0x7f = 01111111b */ 0,
199 /* 0x80 = 10000000b */ 0,
200 /* 0x81 = 10000001b */ X86_EFL_PF,
201 /* 0x82 = 10000010b */ X86_EFL_PF,
202 /* 0x83 = 10000011b */ 0,
203 /* 0x84 = 10000100b */ X86_EFL_PF,
204 /* 0x85 = 10000101b */ 0,
205 /* 0x86 = 10000110b */ 0,
206 /* 0x87 = 10000111b */ X86_EFL_PF,
207 /* 0x88 = 10001000b */ X86_EFL_PF,
208 /* 0x89 = 10001001b */ 0,
209 /* 0x8a = 10001010b */ 0,
210 /* 0x8b = 10001011b */ X86_EFL_PF,
211 /* 0x8c = 10001100b */ 0,
212 /* 0x8d = 10001101b */ X86_EFL_PF,
213 /* 0x8e = 10001110b */ X86_EFL_PF,
214 /* 0x8f = 10001111b */ 0,
215 /* 0x90 = 10010000b */ X86_EFL_PF,
216 /* 0x91 = 10010001b */ 0,
217 /* 0x92 = 10010010b */ 0,
218 /* 0x93 = 10010011b */ X86_EFL_PF,
219 /* 0x94 = 10010100b */ 0,
220 /* 0x95 = 10010101b */ X86_EFL_PF,
221 /* 0x96 = 10010110b */ X86_EFL_PF,
222 /* 0x97 = 10010111b */ 0,
223 /* 0x98 = 10011000b */ 0,
224 /* 0x99 = 10011001b */ X86_EFL_PF,
225 /* 0x9a = 10011010b */ X86_EFL_PF,
226 /* 0x9b = 10011011b */ 0,
227 /* 0x9c = 10011100b */ X86_EFL_PF,
228 /* 0x9d = 10011101b */ 0,
229 /* 0x9e = 10011110b */ 0,
230 /* 0x9f = 10011111b */ X86_EFL_PF,
231 /* 0xa0 = 10100000b */ X86_EFL_PF,
232 /* 0xa1 = 10100001b */ 0,
233 /* 0xa2 = 10100010b */ 0,
234 /* 0xa3 = 10100011b */ X86_EFL_PF,
235 /* 0xa4 = 10100100b */ 0,
236 /* 0xa5 = 10100101b */ X86_EFL_PF,
237 /* 0xa6 = 10100110b */ X86_EFL_PF,
238 /* 0xa7 = 10100111b */ 0,
239 /* 0xa8 = 10101000b */ 0,
240 /* 0xa9 = 10101001b */ X86_EFL_PF,
241 /* 0xaa = 10101010b */ X86_EFL_PF,
242 /* 0xab = 10101011b */ 0,
243 /* 0xac = 10101100b */ X86_EFL_PF,
244 /* 0xad = 10101101b */ 0,
245 /* 0xae = 10101110b */ 0,
246 /* 0xaf = 10101111b */ X86_EFL_PF,
247 /* 0xb0 = 10110000b */ 0,
248 /* 0xb1 = 10110001b */ X86_EFL_PF,
249 /* 0xb2 = 10110010b */ X86_EFL_PF,
250 /* 0xb3 = 10110011b */ 0,
251 /* 0xb4 = 10110100b */ X86_EFL_PF,
252 /* 0xb5 = 10110101b */ 0,
253 /* 0xb6 = 10110110b */ 0,
254 /* 0xb7 = 10110111b */ X86_EFL_PF,
255 /* 0xb8 = 10111000b */ X86_EFL_PF,
256 /* 0xb9 = 10111001b */ 0,
257 /* 0xba = 10111010b */ 0,
258 /* 0xbb = 10111011b */ X86_EFL_PF,
259 /* 0xbc = 10111100b */ 0,
260 /* 0xbd = 10111101b */ X86_EFL_PF,
261 /* 0xbe = 10111110b */ X86_EFL_PF,
262 /* 0xbf = 10111111b */ 0,
263 /* 0xc0 = 11000000b */ X86_EFL_PF,
264 /* 0xc1 = 11000001b */ 0,
265 /* 0xc2 = 11000010b */ 0,
266 /* 0xc3 = 11000011b */ X86_EFL_PF,
267 /* 0xc4 = 11000100b */ 0,
268 /* 0xc5 = 11000101b */ X86_EFL_PF,
269 /* 0xc6 = 11000110b */ X86_EFL_PF,
270 /* 0xc7 = 11000111b */ 0,
271 /* 0xc8 = 11001000b */ 0,
272 /* 0xc9 = 11001001b */ X86_EFL_PF,
273 /* 0xca = 11001010b */ X86_EFL_PF,
274 /* 0xcb = 11001011b */ 0,
275 /* 0xcc = 11001100b */ X86_EFL_PF,
276 /* 0xcd = 11001101b */ 0,
277 /* 0xce = 11001110b */ 0,
278 /* 0xcf = 11001111b */ X86_EFL_PF,
279 /* 0xd0 = 11010000b */ 0,
280 /* 0xd1 = 11010001b */ X86_EFL_PF,
281 /* 0xd2 = 11010010b */ X86_EFL_PF,
282 /* 0xd3 = 11010011b */ 0,
283 /* 0xd4 = 11010100b */ X86_EFL_PF,
284 /* 0xd5 = 11010101b */ 0,
285 /* 0xd6 = 11010110b */ 0,
286 /* 0xd7 = 11010111b */ X86_EFL_PF,
287 /* 0xd8 = 11011000b */ X86_EFL_PF,
288 /* 0xd9 = 11011001b */ 0,
289 /* 0xda = 11011010b */ 0,
290 /* 0xdb = 11011011b */ X86_EFL_PF,
291 /* 0xdc = 11011100b */ 0,
292 /* 0xdd = 11011101b */ X86_EFL_PF,
293 /* 0xde = 11011110b */ X86_EFL_PF,
294 /* 0xdf = 11011111b */ 0,
295 /* 0xe0 = 11100000b */ 0,
296 /* 0xe1 = 11100001b */ X86_EFL_PF,
297 /* 0xe2 = 11100010b */ X86_EFL_PF,
298 /* 0xe3 = 11100011b */ 0,
299 /* 0xe4 = 11100100b */ X86_EFL_PF,
300 /* 0xe5 = 11100101b */ 0,
301 /* 0xe6 = 11100110b */ 0,
302 /* 0xe7 = 11100111b */ X86_EFL_PF,
303 /* 0xe8 = 11101000b */ X86_EFL_PF,
304 /* 0xe9 = 11101001b */ 0,
305 /* 0xea = 11101010b */ 0,
306 /* 0xeb = 11101011b */ X86_EFL_PF,
307 /* 0xec = 11101100b */ 0,
308 /* 0xed = 11101101b */ X86_EFL_PF,
309 /* 0xee = 11101110b */ X86_EFL_PF,
310 /* 0xef = 11101111b */ 0,
311 /* 0xf0 = 11110000b */ X86_EFL_PF,
312 /* 0xf1 = 11110001b */ 0,
313 /* 0xf2 = 11110010b */ 0,
314 /* 0xf3 = 11110011b */ X86_EFL_PF,
315 /* 0xf4 = 11110100b */ 0,
316 /* 0xf5 = 11110101b */ X86_EFL_PF,
317 /* 0xf6 = 11110110b */ X86_EFL_PF,
318 /* 0xf7 = 11110111b */ 0,
319 /* 0xf8 = 11111000b */ 0,
320 /* 0xf9 = 11111001b */ X86_EFL_PF,
321 /* 0xfa = 11111010b */ X86_EFL_PF,
322 /* 0xfb = 11111011b */ 0,
323 /* 0xfc = 11111100b */ X86_EFL_PF,
324 /* 0xfd = 11111101b */ 0,
325 /* 0xfe = 11111110b */ 0,
326 /* 0xff = 11111111b */ X86_EFL_PF,
327};
328#endif /* RT_ARCH_X86 */
329
330
331/**
332 * Calculates the signed flag value given a result and it's bit width.
333 *
334 * The signed flag (SF) is a duplication of the most significant bit in the
335 * result.
336 *
337 * @returns X86_EFL_SF or 0.
338 * @param a_uResult Unsigned result value.
339 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
340 */
341#define X86_EFL_CALC_SF(a_uResult, a_cBitsWidth) \
342 ( (uint32_t)((a_uResult) >> ((a_cBitsWidth) - X86_EFL_SF_BIT - 1)) & X86_EFL_SF )
343
344/**
345 * Calculates the zero flag value given a result.
346 *
347 * The zero flag (ZF) indicates whether the result is zero or not.
348 *
349 * @returns X86_EFL_ZF or 0.
350 * @param a_uResult Unsigned result value.
351 */
352#define X86_EFL_CALC_ZF(a_uResult) \
353 ( (uint32_t)((a_uResult) == 0) << X86_EFL_ZF_BIT )
354
355/**
356 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) after a logical op.
357 *
358 * CF and OF are defined to be 0 by logical operations. AF on the other hand is
359 * undefined. We do not set AF, as that seems to make the most sense (which
360 * probably makes it the most wrong in real life).
361 *
362 * @returns Status bits.
363 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
364 * @param a_uResult Unsigned result value.
365 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
366 * @param a_fExtra Additional bits to set.
367 */
368#define IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(a_pfEFlags, a_uResult, a_cBitsWidth, a_fExtra) \
369 do { \
370 uint32_t fEflTmp = *(a_pfEFlags); \
371 fEflTmp &= ~X86_EFL_STATUS_BITS; \
372 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
373 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
374 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
375 fEflTmp |= (a_fExtra); \
376 *(a_pfEFlags) = fEflTmp; \
377 } while (0)
378
379
380#ifdef RT_ARCH_X86
381/*
382 * There are a few 64-bit on 32-bit things we'd rather do in C. Actually, doing
383 * it all in C is probably safer atm., optimize what's necessary later, maybe.
384 */
385
386
387/* Binary ops */
388
389IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
390{
391 uint64_t uDst = *puDst;
392 uint64_t uResult = uDst + uSrc;
393 *puDst = uResult;
394
395 /* Calc EFLAGS. */
396 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
397 fEfl |= (uResult < uDst) << X86_EFL_CF_BIT;
398 fEfl |= g_afParity[uResult & 0xff];
399 fEfl |= ((uint32_t)uResult ^ (uint32_t)uSrc ^ (uint32_t)uDst) & X86_EFL_AF;
400 fEfl |= X86_EFL_CALC_ZF(uResult);
401 fEfl |= X86_EFL_CALC_SF(uResult, 64);
402 fEfl |= (((uDst ^ uSrc ^ RT_BIT_64(63)) & (uResult ^ uDst)) >> (64 - X86_EFL_OF_BIT)) & X86_EFL_OF;
403 *pfEFlags = fEfl;
404}
405
406
407IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
408{
409 if (!(*pfEFlags & X86_EFL_CF))
410 iemAImpl_add_u64(puDst, uSrc, pfEFlags);
411 else
412 {
413 uint64_t uDst = *puDst;
414 uint64_t uResult = uDst + uSrc + 1;
415 *puDst = uResult;
416
417 /* Calc EFLAGS. */
418 /** @todo verify AF and OF calculations. */
419 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
420 fEfl |= (uResult <= uDst) << X86_EFL_CF_BIT;
421 fEfl |= g_afParity[uResult & 0xff];
422 fEfl |= ((uint32_t)uResult ^ (uint32_t)uSrc ^ (uint32_t)uDst) & X86_EFL_AF;
423 fEfl |= X86_EFL_CALC_ZF(uResult);
424 fEfl |= X86_EFL_CALC_SF(uResult, 64);
425 fEfl |= (((uDst ^ uSrc ^ RT_BIT_64(63)) & (uResult ^ uDst)) >> (64 - X86_EFL_OF_BIT)) & X86_EFL_OF;
426 *pfEFlags = fEfl;
427 }
428}
429
430
431IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
432{
433 uint64_t uDst = *puDst;
434 uint64_t uResult = uDst - uSrc;
435 *puDst = uResult;
436
437 /* Calc EFLAGS. */
438 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
439 fEfl |= (uDst < uSrc) << X86_EFL_CF_BIT;
440 fEfl |= g_afParity[uResult & 0xff];
441 fEfl |= ((uint32_t)uResult ^ (uint32_t)uSrc ^ (uint32_t)uDst) & X86_EFL_AF;
442 fEfl |= X86_EFL_CALC_ZF(uResult);
443 fEfl |= X86_EFL_CALC_SF(uResult, 64);
444 fEfl |= (((uDst ^ uSrc) & (uResult ^ uDst)) >> (64 - X86_EFL_OF_BIT)) & X86_EFL_OF;
445 *pfEFlags = fEfl;
446}
447
448
449IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
450{
451 if (!(*pfEFlags & X86_EFL_CF))
452 iemAImpl_sub_u64(puDst, uSrc, pfEFlags);
453 else
454 {
455 uint64_t uDst = *puDst;
456 uint64_t uResult = uDst - uSrc - 1;
457 *puDst = uResult;
458
459 /* Calc EFLAGS. */
460 /** @todo verify AF and OF calculations. */
461 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
462 fEfl |= (uDst <= uSrc) << X86_EFL_CF_BIT;
463 fEfl |= g_afParity[uResult & 0xff];
464 fEfl |= ((uint32_t)uResult ^ (uint32_t)uSrc ^ (uint32_t)uDst) & X86_EFL_AF;
465 fEfl |= X86_EFL_CALC_ZF(uResult);
466 fEfl |= X86_EFL_CALC_SF(uResult, 64);
467 fEfl |= (((uDst ^ uSrc) & (uResult ^ uDst)) >> (64 - X86_EFL_OF_BIT)) & X86_EFL_OF;
468 *pfEFlags = fEfl;
469 }
470}
471
472
473IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
474{
475 uint64_t uResult = *puDst | uSrc;
476 *puDst = uResult;
477 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
478}
479
480
481IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
482{
483 uint64_t uResult = *puDst ^ uSrc;
484 *puDst = uResult;
485 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
486}
487
488
489IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
490{
491 uint64_t uResult = *puDst & uSrc;
492 *puDst = uResult;
493 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
494}
495
496
497IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
498{
499 uint64_t uDstTmp = *puDst;
500 iemAImpl_sub_u64(&uDstTmp, uSrc, pfEFlags);
501}
502
503
504IEM_DECL_IMPL_DEF(void, iemAImpl_test_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
505{
506 uint64_t uResult = *puDst & uSrc;
507 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
508}
509
510
511/** 64-bit locked binary operand operation. */
512# define DO_LOCKED_BIN_OP_U64(a_Mnemonic) \
513 do { \
514 uint64_t uOld = ASMAtomicReadU64(puDst); \
515 uint64_t uTmp; \
516 uint32_t fEflTmp; \
517 do \
518 { \
519 uTmp = uOld; \
520 fEflTmp = *pfEFlags; \
521 iemAImpl_ ## a_Mnemonic ## _u64(&uTmp, uSrc, &fEflTmp); \
522 } while (!ASMAtomicCmpXchgExU64(puDst, uTmp, uOld, &uOld)); \
523 *pfEFlags = fEflTmp; \
524 } while (0)
525
526
527IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
528{
529 DO_LOCKED_BIN_OP_U64(add);
530}
531
532
533IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
534{
535 DO_LOCKED_BIN_OP_U64(adc);
536}
537
538
539IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
540{
541 DO_LOCKED_BIN_OP_U64(sub);
542}
543
544
545IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
546{
547 DO_LOCKED_BIN_OP_U64(sbb);
548}
549
550
551IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
552{
553 DO_LOCKED_BIN_OP_U64(or);
554}
555
556
557IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
558{
559 DO_LOCKED_BIN_OP_U64(xor);
560}
561
562
563IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
564{
565 DO_LOCKED_BIN_OP_U64(and);
566}
567
568
569IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t *puDst, uint64_t *puReg, uint32_t *pfEFlags))
570{
571 uint64_t uDst = *puDst;
572 uint64_t uResult = uDst;
573 iemAImpl_add_u64(&uResult, *puReg, pfEFlags);
574 *puDst = uResult;
575 *puReg = uDst;
576}
577
578
579IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t *puDst, uint64_t *puReg, uint32_t *pfEFlags))
580{
581 uint64_t uOld = ASMAtomicReadU64(puDst);
582 uint64_t uTmpDst;
583 uint32_t fEflTmp;
584 do
585 {
586 uTmpDst = uOld;
587 fEflTmp = *pfEFlags;
588 iemAImpl_add_u64(&uTmpDst, *puReg, pfEFlags);
589 } while (!ASMAtomicCmpXchgExU64(puDst, uTmpDst, uOld, &uOld));
590 *puReg = uOld;
591 *pfEFlags = fEflTmp;
592}
593
594
595/* Bit operations (same signature as above). */
596
597IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
598{
599 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
600 logical operation (AND/OR/whatever). */
601 Assert(uSrc < 64);
602 uint64_t uDst = *puDst;
603 if (uDst & RT_BIT_64(uSrc))
604 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uDst, 64, X86_EFL_CF);
605 else
606 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uDst, 64, 0);
607}
608
609IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
610{
611 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
612 logical operation (AND/OR/whatever). */
613 Assert(uSrc < 64);
614 uint64_t fMask = RT_BIT_64(uSrc);
615 uint64_t uDst = *puDst;
616 if (uDst & fMask)
617 {
618 uDst &= ~fMask;
619 *puDst = uDst;
620 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uDst, 64, X86_EFL_CF);
621 }
622 else
623 {
624 uDst |= fMask;
625 *puDst = uDst;
626 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uDst, 64, 0);
627 }
628}
629
630IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
631{
632 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
633 logical operation (AND/OR/whatever). */
634 Assert(uSrc < 64);
635 uint64_t fMask = RT_BIT_64(uSrc);
636 uint64_t uDst = *puDst;
637 if (uDst & fMask)
638 {
639 uDst &= ~fMask;
640 *puDst = uDst;
641 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uDst, 64, X86_EFL_CF);
642 }
643 else
644 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uDst, 64, 0);
645}
646
647IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
648{
649 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
650 logical operation (AND/OR/whatever). */
651 Assert(uSrc < 64);
652 uint64_t fMask = RT_BIT_64(uSrc);
653 uint64_t uDst = *puDst;
654 if (uDst & fMask)
655 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uDst, 64, X86_EFL_CF);
656 else
657 {
658 uDst |= fMask;
659 *puDst = uDst;
660 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uDst, 64, 0);
661 }
662}
663
664
665IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
666{
667 DO_LOCKED_BIN_OP_U64(btc);
668}
669
670IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
671{
672 DO_LOCKED_BIN_OP_U64(btr);
673}
674
675IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
676{
677 DO_LOCKED_BIN_OP_U64(bts);
678}
679
680
681/* bit scan */
682
683IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
684{
685 /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
686 /** @todo check what real CPUs do. */
687 if (uSrc)
688 {
689 uint8_t iBit;
690 uint32_t u32Src;
691 if (uSrc & UINT32_MAX)
692 {
693 iBit = 0;
694 u32Src = uSrc;
695 }
696 else
697 {
698 iBit = 32;
699 u32Src = uSrc >> 32;
700 }
701 if (!(u32Src & UINT16_MAX))
702 {
703 iBit += 16;
704 u32Src >>= 16;
705 }
706 if (!(u32Src & UINT8_MAX))
707 {
708 iBit += 8;
709 u32Src >>= 8;
710 }
711 if (!(u32Src & 0xf))
712 {
713 iBit += 4;
714 u32Src >>= 4;
715 }
716 if (!(u32Src & 0x3))
717 {
718 iBit += 2;
719 u32Src >>= 2;
720 }
721 if (!(u32Src & 1))
722 {
723 iBit += 1;
724 Assert(u32Src & 2);
725 }
726
727 *puDst = iBit;
728 *pfEFlags &= ~X86_EFL_ZF;
729 }
730 else
731 *pfEFlags |= X86_EFL_ZF;
732}
733
734IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
735{
736 /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
737 /** @todo check what real CPUs do. */
738 if (uSrc)
739 {
740 uint8_t iBit;
741 uint32_t u32Src;
742 if (uSrc & UINT64_C(0xffffffff00000000))
743 {
744 iBit = 63;
745 u32Src = uSrc >> 32;
746 }
747 else
748 {
749 iBit = 31;
750 u32Src = uSrc;
751 }
752 if (!(u32Src & UINT32_C(0xffff0000)))
753 {
754 iBit -= 16;
755 u32Src <<= 16;
756 }
757 if (!(u32Src & UINT32_C(0xff000000)))
758 {
759 iBit -= 8;
760 u32Src <<= 8;
761 }
762 if (!(u32Src & UINT32_C(0xf0000000)))
763 {
764 iBit -= 4;
765 u32Src <<= 4;
766 }
767 if (!(u32Src & UINT32_C(0xc0000000)))
768 {
769 iBit -= 2;
770 u32Src <<= 2;
771 }
772 if (!(u32Src & UINT32_C(0x80000000)))
773 {
774 iBit -= 1;
775 Assert(u32Src & RT_BIT(30));
776 }
777
778 *puDst = iBit;
779 *pfEFlags &= ~X86_EFL_ZF;
780 }
781 else
782 *pfEFlags |= X86_EFL_ZF;
783}
784
785
786/* Unary operands. */
787
788IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64,(uint64_t *puDst, uint32_t *pfEFlags))
789{
790 uint64_t uDst = *puDst;
791 uint64_t uResult = uDst + 1;
792 *puDst = uResult;
793
794 /*
795 * Calc EFLAGS.
796 * CF is NOT modified for hysterical raisins (allegedly for carrying and
797 * borrowing in arithmetic loops on intel 8008).
798 */
799 uint32_t fEfl = *pfEFlags & ~(X86_EFL_STATUS_BITS & ~X86_EFL_CF);
800 fEfl |= g_afParity[uResult & 0xff];
801 fEfl |= ((uint32_t)uResult ^ (uint32_t)uDst) & X86_EFL_AF;
802 fEfl |= X86_EFL_CALC_ZF(uResult);
803 fEfl |= X86_EFL_CALC_SF(uResult, 64);
804 fEfl |= (((uDst ^ RT_BIT_64(63)) & uResult) >> (64 - X86_EFL_OF_BIT)) & X86_EFL_OF;
805 *pfEFlags = fEfl;
806}
807
808
809IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64,(uint64_t *puDst, uint32_t *pfEFlags))
810{
811 uint64_t uDst = *puDst;
812 uint64_t uResult = uDst - 1;
813 *puDst = uResult;
814
815 /*
816 * Calc EFLAGS.
817 * CF is NOT modified for hysterical raisins (allegedly for carrying and
818 * borrowing in arithmetic loops on intel 8008).
819 */
820 uint32_t fEfl = *pfEFlags & ~(X86_EFL_STATUS_BITS & ~X86_EFL_CF);
821 fEfl |= g_afParity[uResult & 0xff];
822 fEfl |= ((uint32_t)uResult ^ (uint32_t)uDst) & X86_EFL_AF;
823 fEfl |= X86_EFL_CALC_ZF(uResult);
824 fEfl |= X86_EFL_CALC_SF(uResult, 64);
825 fEfl |= ((uDst & (uResult ^ RT_BIT_64(63))) >> (64 - X86_EFL_OF_BIT)) & X86_EFL_OF;
826 *pfEFlags = fEfl;
827}
828
829
830IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64,(uint64_t *puDst, uint32_t *pfEFlags))
831{
832 uint64_t uDst = *puDst;
833 uint64_t uResult = ~uDst;
834 *puDst = uResult;
835 /* EFLAGS are not modified. */
836 RT_NOREF_PV(pfEFlags);
837}
838
839
840IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64,(uint64_t *puDst, uint32_t *pfEFlags))
841{
842 uint64_t uDst = 0;
843 uint64_t uSrc = *puDst;
844 uint64_t uResult = uDst - uSrc;
845 *puDst = uResult;
846
847 /* Calc EFLAGS. */
848 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
849 fEfl |= (uSrc != 0) << X86_EFL_CF_BIT;
850 fEfl |= g_afParity[uResult & 0xff];
851 fEfl |= ((uint32_t)uResult ^ (uint32_t)uDst) & X86_EFL_AF;
852 fEfl |= X86_EFL_CALC_ZF(uResult);
853 fEfl |= X86_EFL_CALC_SF(uResult, 64);
854 fEfl |= ((uSrc & uResult) >> (64 - X86_EFL_OF_BIT)) & X86_EFL_OF;
855 *pfEFlags = fEfl;
856}
857
858
859/** 64-bit locked unary operand operation. */
860# define DO_LOCKED_UNARY_OP_U64(a_Mnemonic) \
861 do { \
862 uint64_t uOld = ASMAtomicReadU64(puDst); \
863 uint64_t uTmp; \
864 uint32_t fEflTmp; \
865 do \
866 { \
867 uTmp = uOld; \
868 fEflTmp = *pfEFlags; \
869 iemAImpl_ ## a_Mnemonic ## _u64(&uTmp, &fEflTmp); \
870 } while (!ASMAtomicCmpXchgExU64(puDst, uTmp, uOld, &uOld)); \
871 *pfEFlags = fEflTmp; \
872 } while (0)
873
874IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64_locked,(uint64_t *puDst, uint32_t *pfEFlags))
875{
876 DO_LOCKED_UNARY_OP_U64(inc);
877}
878
879
880IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64_locked,(uint64_t *puDst, uint32_t *pfEFlags))
881{
882 DO_LOCKED_UNARY_OP_U64(dec);
883}
884
885
886IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64_locked,(uint64_t *puDst, uint32_t *pfEFlags))
887{
888 DO_LOCKED_UNARY_OP_U64(not);
889}
890
891
892IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64_locked,(uint64_t *puDst, uint32_t *pfEFlags))
893{
894 DO_LOCKED_UNARY_OP_U64(neg);
895}
896
897
898/* Shift and rotate. */
899
900IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
901{
902 cShift &= 63;
903 if (cShift)
904 {
905 uint64_t uDst = *puDst;
906 uint64_t uResult;
907 uResult = uDst << cShift;
908 uResult |= uDst >> (64 - cShift);
909 *puDst = uResult;
910
911 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
912 it the same way as for 1 bit shifts. */
913 AssertCompile(X86_EFL_CF_BIT == 0);
914 uint32_t fEfl = *pfEFlags & ~(X86_EFL_CF | X86_EFL_OF);
915 uint32_t fCarry = (uResult & 1);
916 fEfl |= fCarry;
917 fEfl |= ((uResult >> 63) ^ fCarry) << X86_EFL_OF_BIT;
918 *pfEFlags = fEfl;
919 }
920}
921
922
923IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
924{
925 cShift &= 63;
926 if (cShift)
927 {
928 uint64_t uDst = *puDst;
929 uint64_t uResult;
930 uResult = uDst >> cShift;
931 uResult |= uDst << (64 - cShift);
932 *puDst = uResult;
933
934 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
935 it the same way as for 1 bit shifts (OF = OF XOR New-CF). */
936 AssertCompile(X86_EFL_CF_BIT == 0);
937 uint32_t fEfl = *pfEFlags & ~(X86_EFL_CF | X86_EFL_OF);
938 uint32_t fCarry = (uResult >> 63) & X86_EFL_CF;
939 fEfl |= fCarry;
940 fEfl |= (((uResult >> 62) ^ fCarry) << X86_EFL_OF_BIT) & X86_EFL_OF;
941 *pfEFlags = fEfl;
942 }
943}
944
945
946IEM_DECL_IMPL_DEF(void, iemAImpl_rcl_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
947{
948 cShift &= 63;
949 if (cShift)
950 {
951 uint32_t fEfl = *pfEFlags;
952 uint64_t uDst = *puDst;
953 uint64_t uResult;
954 uResult = uDst << cShift;
955 AssertCompile(X86_EFL_CF_BIT == 0);
956 if (cShift > 1)
957 uResult |= uDst >> (65 - cShift);
958 uResult |= (uint64_t)(fEfl & X86_EFL_CF) << (cShift - 1);
959 *puDst = uResult;
960
961 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
962 it the same way as for 1 bit shifts. */
963 uint32_t fCarry = (uDst >> (64 - cShift)) & X86_EFL_CF;
964 fEfl &= ~(X86_EFL_CF | X86_EFL_OF);
965 fEfl |= fCarry;
966 fEfl |= ((uResult >> 63) ^ fCarry) << X86_EFL_OF_BIT;
967 *pfEFlags = fEfl;
968 }
969}
970
971
972IEM_DECL_IMPL_DEF(void, iemAImpl_rcr_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
973{
974 cShift &= 63;
975 if (cShift)
976 {
977 uint32_t fEfl = *pfEFlags;
978 uint64_t uDst = *puDst;
979 uint64_t uResult;
980 uResult = uDst >> cShift;
981 AssertCompile(X86_EFL_CF_BIT == 0);
982 if (cShift > 1)
983 uResult |= uDst << (65 - cShift);
984 uResult |= (uint64_t)(fEfl & X86_EFL_CF) << (64 - cShift);
985 *puDst = uResult;
986
987 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
988 it the same way as for 1 bit shifts. */
989 uint32_t fCarry = (uDst >> (cShift - 1)) & X86_EFL_CF;
990 fEfl &= ~(X86_EFL_CF | X86_EFL_OF);
991 fEfl |= fCarry;
992 fEfl |= ((uResult >> 63) ^ fCarry) << X86_EFL_OF_BIT;
993 *pfEFlags = fEfl;
994 }
995}
996
997
998IEM_DECL_IMPL_DEF(void, iemAImpl_shl_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
999{
1000 cShift &= 63;
1001 if (cShift)
1002 {
1003 uint64_t uDst = *puDst;
1004 uint64_t uResult = uDst << cShift;
1005 *puDst = uResult;
1006
1007 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
1008 it the same way as for 1 bit shifts. The AF bit is undefined, we
1009 always set it to zero atm. */
1010 AssertCompile(X86_EFL_CF_BIT == 0);
1011 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
1012 uint32_t fCarry = (uDst >> (64 - cShift)) & X86_EFL_CF;
1013 fEfl |= fCarry;
1014 fEfl |= ((uResult >> 63) ^ fCarry) << X86_EFL_OF_BIT;
1015 fEfl |= X86_EFL_CALC_SF(uResult, 64);
1016 fEfl |= X86_EFL_CALC_ZF(uResult);
1017 fEfl |= g_afParity[uResult & 0xff];
1018 *pfEFlags = fEfl;
1019 }
1020}
1021
1022
1023IEM_DECL_IMPL_DEF(void, iemAImpl_shr_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
1024{
1025 cShift &= 63;
1026 if (cShift)
1027 {
1028 uint64_t uDst = *puDst;
1029 uint64_t uResult = uDst >> cShift;
1030 *puDst = uResult;
1031
1032 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
1033 it the same way as for 1 bit shifts. The AF bit is undefined, we
1034 always set it to zero atm. */
1035 AssertCompile(X86_EFL_CF_BIT == 0);
1036 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
1037 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF;
1038 fEfl |= (uDst >> 63) << X86_EFL_OF_BIT;
1039 fEfl |= X86_EFL_CALC_SF(uResult, 64);
1040 fEfl |= X86_EFL_CALC_ZF(uResult);
1041 fEfl |= g_afParity[uResult & 0xff];
1042 *pfEFlags = fEfl;
1043 }
1044}
1045
1046
1047IEM_DECL_IMPL_DEF(void, iemAImpl_sar_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
1048{
1049 cShift &= 63;
1050 if (cShift)
1051 {
1052 uint64_t uDst = *puDst;
1053 uint64_t uResult = (int64_t)uDst >> cShift;
1054 *puDst = uResult;
1055
1056 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
1057 it the same way as for 1 bit shifts (0). The AF bit is undefined,
1058 we always set it to zero atm. */
1059 AssertCompile(X86_EFL_CF_BIT == 0);
1060 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
1061 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF;
1062 fEfl |= X86_EFL_CALC_SF(uResult, 64);
1063 fEfl |= X86_EFL_CALC_ZF(uResult);
1064 fEfl |= g_afParity[uResult & 0xff];
1065 *pfEFlags = fEfl;
1066 }
1067}
1068
1069
1070IEM_DECL_IMPL_DEF(void, iemAImpl_shld_u64,(uint64_t *puDst, uint64_t uSrc, uint8_t cShift, uint32_t *pfEFlags))
1071{
1072 cShift &= 63;
1073 if (cShift)
1074 {
1075 uint64_t uDst = *puDst;
1076 uint64_t uResult;
1077 uResult = uDst << cShift;
1078 uResult |= uSrc >> (64 - cShift);
1079 *puDst = uResult;
1080
1081 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
1082 it the same way as for 1 bit shifts. The AF bit is undefined,
1083 we always set it to zero atm. */
1084 AssertCompile(X86_EFL_CF_BIT == 0);
1085 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
1086 fEfl |= (uDst >> (64 - cShift)) & X86_EFL_CF;
1087 fEfl |= (uint32_t)((uDst >> 63) ^ (uint32_t)(uResult >> 63)) << X86_EFL_OF_BIT;
1088 fEfl |= X86_EFL_CALC_SF(uResult, 64);
1089 fEfl |= X86_EFL_CALC_ZF(uResult);
1090 fEfl |= g_afParity[uResult & 0xff];
1091 *pfEFlags = fEfl;
1092 }
1093}
1094
1095
1096IEM_DECL_IMPL_DEF(void, iemAImpl_shrd_u64,(uint64_t *puDst, uint64_t uSrc, uint8_t cShift, uint32_t *pfEFlags))
1097{
1098 cShift &= 63;
1099 if (cShift)
1100 {
1101 uint64_t uDst = *puDst;
1102 uint64_t uResult;
1103 uResult = uDst >> cShift;
1104 uResult |= uSrc << (64 - cShift);
1105 *puDst = uResult;
1106
1107 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement
1108 it the same way as for 1 bit shifts. The AF bit is undefined,
1109 we always set it to zero atm. */
1110 AssertCompile(X86_EFL_CF_BIT == 0);
1111 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
1112 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF;
1113 fEfl |= (uint32_t)((uDst >> 63) ^ (uint32_t)(uResult >> 63)) << X86_EFL_OF_BIT;
1114 fEfl |= X86_EFL_CALC_SF(uResult, 64);
1115 fEfl |= X86_EFL_CALC_ZF(uResult);
1116 fEfl |= g_afParity[uResult & 0xff];
1117 *pfEFlags = fEfl;
1118 }
1119}
1120
1121
1122/* misc */
1123
1124IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t *puMem, uint64_t *puReg))
1125{
1126 /* XCHG implies LOCK. */
1127 uint64_t uOldMem = *puMem;
1128 while (!ASMAtomicCmpXchgExU64(puMem, *puReg, uOldMem, &uOldMem))
1129 ASMNopPause();
1130 *puReg = uOldMem;
1131}
1132
1133
1134#endif /* RT_ARCH_X86 */
1135#ifdef RT_ARCH_X86
1136
1137/* multiplication and division */
1138
1139
1140IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Factor, uint32_t *pfEFlags))
1141{
1142 RTUINT128U Result;
1143 RTUInt128MulU64ByU64(&Result, *pu64RAX, u64Factor);
1144 *pu64RAX = Result.s.Lo;
1145 *pu64RDX = Result.s.Hi;
1146
1147 /* MUL EFLAGS according to Skylake (similar to IMUL). */
1148 *pfEFlags &= ~(X86_EFL_SF | X86_EFL_CF | X86_EFL_OF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF);
1149 if (Result.s.Lo & RT_BIT_64(63))
1150 *pfEFlags |= X86_EFL_SF;
1151 *pfEFlags |= g_afParity[Result.s.Lo & 0xff]; /* (Skylake behaviour) */
1152 if (Result.s.Hi != 0)
1153 *pfEFlags |= X86_EFL_CF | X86_EFL_OF;
1154 return 0;
1155}
1156
1157
1158IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Factor, uint32_t *pfEFlags))
1159{
1160 RTUINT128U Result;
1161 *pfEFlags &= ~( X86_EFL_SF | X86_EFL_CF | X86_EFL_OF
1162 /* Skylake always clears: */ | X86_EFL_AF | X86_EFL_ZF
1163 /* Skylake may set: */ | X86_EFL_PF);
1164
1165 if ((int64_t)*pu64RAX >= 0)
1166 {
1167 if ((int64_t)u64Factor >= 0)
1168 {
1169 RTUInt128MulU64ByU64(&Result, *pu64RAX, u64Factor);
1170 if (Result.s.Hi != 0 || Result.s.Lo >= UINT64_C(0x8000000000000000))
1171 *pfEFlags |= X86_EFL_CF | X86_EFL_OF;
1172 }
1173 else
1174 {
1175 RTUInt128MulU64ByU64(&Result, *pu64RAX, UINT64_C(0) - u64Factor);
1176 if (Result.s.Hi != 0 || Result.s.Lo > UINT64_C(0x8000000000000000))
1177 *pfEFlags |= X86_EFL_CF | X86_EFL_OF;
1178 RTUInt128AssignNeg(&Result);
1179 }
1180 }
1181 else
1182 {
1183 if ((int64_t)u64Factor >= 0)
1184 {
1185 RTUInt128MulU64ByU64(&Result, UINT64_C(0) - *pu64RAX, u64Factor);
1186 if (Result.s.Hi != 0 || Result.s.Lo > UINT64_C(0x8000000000000000))
1187 *pfEFlags |= X86_EFL_CF | X86_EFL_OF;
1188 RTUInt128AssignNeg(&Result);
1189 }
1190 else
1191 {
1192 RTUInt128MulU64ByU64(&Result, UINT64_C(0) - *pu64RAX, UINT64_C(0) - u64Factor);
1193 if (Result.s.Hi != 0 || Result.s.Lo >= UINT64_C(0x8000000000000000))
1194 *pfEFlags |= X86_EFL_CF | X86_EFL_OF;
1195 }
1196 }
1197 *pu64RAX = Result.s.Lo;
1198 if (Result.s.Lo & RT_BIT_64(63))
1199 *pfEFlags |= X86_EFL_SF;
1200 *pfEFlags |= g_afParity[Result.s.Lo & 0xff]; /* (Skylake behaviour) */
1201 *pu64RDX = Result.s.Hi;
1202
1203 return 0;
1204}
1205
1206
1207IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1208{
1209/** @todo Testcase: IMUL 2 and 3 operands. */
1210 uint64_t u64Ign;
1211 iemAImpl_imul_u64(puDst, &u64Ign, uSrc, pfEFlags);
1212}
1213
1214
1215
1216IEM_DECL_IMPL_DEF(int, iemAImpl_div_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Divisor, uint32_t *pfEFlags))
1217{
1218 /* Note! Skylake leaves all flags alone. */
1219 RT_NOREF_PV(pfEFlags);
1220
1221 if ( u64Divisor != 0
1222 && *pu64RDX < u64Divisor)
1223 {
1224 RTUINT128U Dividend;
1225 Dividend.s.Lo = *pu64RAX;
1226 Dividend.s.Hi = *pu64RDX;
1227
1228 RTUINT128U Divisor;
1229 Divisor.s.Lo = u64Divisor;
1230 Divisor.s.Hi = 0;
1231
1232 RTUINT128U Remainder;
1233 RTUINT128U Quotient;
1234# ifdef __GNUC__ /* GCC maybe really annoying in function. */
1235 Quotient.s.Lo = 0;
1236 Quotient.s.Hi = 0;
1237# endif
1238 RTUInt128DivRem(&Quotient, &Remainder, &Dividend, &Divisor);
1239 Assert(Quotient.s.Hi == 0);
1240 Assert(Remainder.s.Hi == 0);
1241
1242 *pu64RAX = Quotient.s.Lo;
1243 *pu64RDX = Remainder.s.Lo;
1244 /** @todo research the undefined DIV flags. */
1245 return 0;
1246
1247 }
1248 /* #DE */
1249 return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
1250}
1251
1252
1253IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Divisor, uint32_t *pfEFlags))
1254{
1255 /* Note! Skylake leaves all flags alone. */
1256 RT_NOREF_PV(pfEFlags);
1257
1258 if (u64Divisor != 0)
1259 {
1260 /*
1261 * Convert to unsigned division.
1262 */
1263 RTUINT128U Dividend;
1264 Dividend.s.Lo = *pu64RAX;
1265 Dividend.s.Hi = *pu64RDX;
1266 if ((int64_t)*pu64RDX < 0)
1267 RTUInt128AssignNeg(&Dividend);
1268
1269 RTUINT128U Divisor;
1270 Divisor.s.Hi = 0;
1271 if ((int64_t)u64Divisor >= 0)
1272 Divisor.s.Lo = u64Divisor;
1273 else
1274 Divisor.s.Lo = UINT64_C(0) - u64Divisor;
1275
1276 RTUINT128U Remainder;
1277 RTUINT128U Quotient;
1278# ifdef __GNUC__ /* GCC maybe really annoying in function. */
1279 Quotient.s.Lo = 0;
1280 Quotient.s.Hi = 0;
1281# endif
1282 RTUInt128DivRem(&Quotient, &Remainder, &Dividend, &Divisor);
1283
1284 /*
1285 * Setup the result, checking for overflows.
1286 */
1287 if ((int64_t)u64Divisor >= 0)
1288 {
1289 if ((int64_t)*pu64RDX >= 0)
1290 {
1291 /* Positive divisor, positive dividend => result positive. */
1292 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint64_t)INT64_MAX)
1293 {
1294 *pu64RAX = Quotient.s.Lo;
1295 *pu64RDX = Remainder.s.Lo;
1296 return 0;
1297 }
1298 }
1299 else
1300 {
1301 /* Positive divisor, positive dividend => result negative. */
1302 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= UINT64_C(0x8000000000000000))
1303 {
1304 *pu64RAX = UINT64_C(0) - Quotient.s.Lo;
1305 *pu64RDX = UINT64_C(0) - Remainder.s.Lo;
1306 return 0;
1307 }
1308 }
1309 }
1310 else
1311 {
1312 if ((int64_t)*pu64RDX >= 0)
1313 {
1314 /* Negative divisor, positive dividend => negative quotient, positive remainder. */
1315 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= UINT64_C(0x8000000000000000))
1316 {
1317 *pu64RAX = UINT64_C(0) - Quotient.s.Lo;
1318 *pu64RDX = Remainder.s.Lo;
1319 return 0;
1320 }
1321 }
1322 else
1323 {
1324 /* Negative divisor, negative dividend => positive quotient, negative remainder. */
1325 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint64_t)INT64_MAX)
1326 {
1327 *pu64RAX = Quotient.s.Lo;
1328 *pu64RDX = UINT64_C(0) - Remainder.s.Lo;
1329 return 0;
1330 }
1331 }
1332 }
1333 }
1334 /* #DE */
1335 return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
1336}
1337
1338
1339#endif /* RT_ARCH_X86 */
1340
1341
1342IEM_DECL_IMPL_DEF(void, iemAImpl_arpl,(uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pfEFlags))
1343{
1344 if ((*pu16Dst & X86_SEL_RPL) < (u16Src & X86_SEL_RPL))
1345 {
1346 *pu16Dst &= X86_SEL_MASK_OFF_RPL;
1347 *pu16Dst |= u16Src & X86_SEL_RPL;
1348
1349 *pfEFlags |= X86_EFL_ZF;
1350 }
1351 else
1352 *pfEFlags &= ~X86_EFL_ZF;
1353}
1354
1355
1356
1357IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1358 PRTUINT128U pu128RbxRcx, uint32_t *pEFlags))
1359{
1360 RTUINT128U u128Tmp = *pu128Dst;
1361 if ( u128Tmp.s.Lo == pu128RaxRdx->s.Lo
1362 && u128Tmp.s.Hi == pu128RaxRdx->s.Hi)
1363 {
1364 *pu128Dst = *pu128RbxRcx;
1365 *pEFlags |= X86_EFL_ZF;
1366 }
1367 else
1368 {
1369 *pu128RaxRdx = u128Tmp;
1370 *pEFlags &= ~X86_EFL_ZF;
1371 }
1372}
1373
1374
1375IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
1376{
1377 RT_NOREF(pFpuState);
1378 puDst->au32[0] = puSrc->au32[0];
1379 puDst->au32[1] = puSrc->au32[0];
1380 puDst->au32[2] = puSrc->au32[2];
1381 puDst->au32[3] = puSrc->au32[2];
1382}
1383
1384#ifdef IEM_WITH_VEX
1385
1386IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
1387{
1388 pXState->x87.aXMM[iYRegDst].au32[0] = pXState->x87.aXMM[iYRegSrc].au32[0];
1389 pXState->x87.aXMM[iYRegDst].au32[1] = pXState->x87.aXMM[iYRegSrc].au32[0];
1390 pXState->x87.aXMM[iYRegDst].au32[2] = pXState->x87.aXMM[iYRegSrc].au32[2];
1391 pXState->x87.aXMM[iYRegDst].au32[3] = pXState->x87.aXMM[iYRegSrc].au32[2];
1392 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
1393 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
1394 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
1395 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
1396}
1397
1398
1399IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
1400{
1401 pXState->x87.aXMM[iYRegDst].au32[0] = pSrc->au32[0];
1402 pXState->x87.aXMM[iYRegDst].au32[1] = pSrc->au32[0];
1403 pXState->x87.aXMM[iYRegDst].au32[2] = pSrc->au32[2];
1404 pXState->x87.aXMM[iYRegDst].au32[3] = pSrc->au32[2];
1405 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pSrc->au32[4];
1406 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pSrc->au32[4];
1407 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pSrc->au32[6];
1408 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pSrc->au32[6];
1409}
1410
1411#endif /* IEM_WITH_VEX */
1412
1413
1414IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
1415{
1416 RT_NOREF(pFpuState);
1417 puDst->au32[0] = puSrc->au32[1];
1418 puDst->au32[1] = puSrc->au32[1];
1419 puDst->au32[2] = puSrc->au32[3];
1420 puDst->au32[3] = puSrc->au32[3];
1421}
1422
1423
1424IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc))
1425{
1426 RT_NOREF(pFpuState);
1427 puDst->au64[0] = uSrc;
1428 puDst->au64[1] = uSrc;
1429}
1430
1431#ifdef IEM_WITH_VEX
1432
1433IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
1434{
1435 pXState->x87.aXMM[iYRegDst].au64[0] = pXState->x87.aXMM[iYRegSrc].au64[0];
1436 pXState->x87.aXMM[iYRegDst].au64[1] = pXState->x87.aXMM[iYRegSrc].au64[0];
1437 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
1438 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
1439}
1440
1441IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
1442{
1443 pXState->x87.aXMM[iYRegDst].au64[0] = pSrc->au64[0];
1444 pXState->x87.aXMM[iYRegDst].au64[1] = pSrc->au64[0];
1445 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pSrc->au64[2];
1446 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pSrc->au64[2];
1447}
1448
1449#endif /* IEM_WITH_VEX */
1450
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