HMVMXAll.cpp@ 93115

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1	/* $Id: HMVMXAll.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2	/** @file
3	* HM VMX (VT-x) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2018-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/hmvmxinline.h>
26	#include <VBox/vmm/vmcc.h>
27	#include <VBox/vmm/pdmapi.h>
28	#include <iprt/errcore.h>
29
30
31	/*********************************************************************************************************************************
32	* Global Variables *
33	*********************************************************************************************************************************/
34	#define VMXV_DIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
35	/** VMX virtual-instructions and VM-exit diagnostics. */
36	static const char * const g_apszVmxVDiagDesc[] =
37	{
38	/* Internal processing errors. */
39	VMXV_DIAG_DESC(kVmxVDiag_None , "None" ),
40	VMXV_DIAG_DESC(kVmxVDiag_Ipe_1 , "Ipe_1" ),
41	VMXV_DIAG_DESC(kVmxVDiag_Ipe_2 , "Ipe_2" ),
42	VMXV_DIAG_DESC(kVmxVDiag_Ipe_3 , "Ipe_3" ),
43	VMXV_DIAG_DESC(kVmxVDiag_Ipe_4 , "Ipe_4" ),
44	VMXV_DIAG_DESC(kVmxVDiag_Ipe_5 , "Ipe_5" ),
45	VMXV_DIAG_DESC(kVmxVDiag_Ipe_6 , "Ipe_6" ),
46	VMXV_DIAG_DESC(kVmxVDiag_Ipe_7 , "Ipe_7" ),
47	VMXV_DIAG_DESC(kVmxVDiag_Ipe_8 , "Ipe_8" ),
48	VMXV_DIAG_DESC(kVmxVDiag_Ipe_9 , "Ipe_9" ),
49	VMXV_DIAG_DESC(kVmxVDiag_Ipe_10 , "Ipe_10" ),
50	VMXV_DIAG_DESC(kVmxVDiag_Ipe_11 , "Ipe_11" ),
51	VMXV_DIAG_DESC(kVmxVDiag_Ipe_12 , "Ipe_12" ),
52	VMXV_DIAG_DESC(kVmxVDiag_Ipe_13 , "Ipe_13" ),
53	VMXV_DIAG_DESC(kVmxVDiag_Ipe_14 , "Ipe_14" ),
54	VMXV_DIAG_DESC(kVmxVDiag_Ipe_15 , "Ipe_15" ),
55	VMXV_DIAG_DESC(kVmxVDiag_Ipe_16 , "Ipe_16" ),
56	/* VMXON. */
57	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_A20M , "A20M" ),
58	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cpl , "Cpl" ),
59	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed0 , "Cr0Fixed0" ),
60	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed1 , "Cr0Fixed1" ),
61	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed0 , "Cr4Fixed0" ),
62	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed1 , "Cr4Fixed1" ),
63	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Intercept , "Intercept" ),
64	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_LongModeCS , "LongModeCS" ),
65	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_MsrFeatCtl , "MsrFeatCtl" ),
66	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAbnormal , "PtrAbnormal" ),
67	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAlign , "PtrAlign" ),
68	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrMap , "PtrMap" ),
69	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrReadPhys , "PtrReadPhys" ),
70	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrWidth , "PtrWidth" ),
71	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_RealOrV86Mode , "RealOrV86Mode" ),
72	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_ShadowVmcs , "ShadowVmcs" ),
73	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxAlreadyRoot , "VmxAlreadyRoot" ),
74	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Vmxe , "Vmxe" ),
75	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmcsRevId , "VmcsRevId" ),
76	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxRootCpl , "VmxRootCpl" ),
77	/* VMXOFF. */
78	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Cpl , "Cpl" ),
79	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Intercept , "Intercept" ),
80	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_LongModeCS , "LongModeCS" ),
81	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_RealOrV86Mode , "RealOrV86Mode" ),
82	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Vmxe , "Vmxe" ),
83	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_VmxRoot , "VmxRoot" ),
84	/* VMPTRLD. */
85	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_Cpl , "Cpl" ),
86	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_LongModeCS , "LongModeCS" ),
87	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAbnormal , "PtrAbnormal" ),
88	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAlign , "PtrAlign" ),
89	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrMap , "PtrMap" ),
90	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrReadPhys , "PtrReadPhys" ),
91	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrVmxon , "PtrVmxon" ),
92	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrWidth , "PtrWidth" ),
93	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RealOrV86Mode , "RealOrV86Mode" ),
94	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RevPtrReadPhys , "RevPtrReadPhys" ),
95	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_ShadowVmcs , "ShadowVmcs" ),
96	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmcsRevId , "VmcsRevId" ),
97	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmxRoot , "VmxRoot" ),
98	/* VMPTRST. */
99	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_Cpl , "Cpl" ),
100	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_LongModeCS , "LongModeCS" ),
101	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_PtrMap , "PtrMap" ),
102	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_RealOrV86Mode , "RealOrV86Mode" ),
103	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_VmxRoot , "VmxRoot" ),
104	/* VMCLEAR. */
105	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_Cpl , "Cpl" ),
106	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_LongModeCS , "LongModeCS" ),
107	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAbnormal , "PtrAbnormal" ),
108	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAlign , "PtrAlign" ),
109	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrMap , "PtrMap" ),
110	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrReadPhys , "PtrReadPhys" ),
111	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrVmxon , "PtrVmxon" ),
112	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrWidth , "PtrWidth" ),
113	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_RealOrV86Mode , "RealOrV86Mode" ),
114	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_VmxRoot , "VmxRoot" ),
115	/* VMWRITE. */
116	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_Cpl , "Cpl" ),
117	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldInvalid , "FieldInvalid" ),
118	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldRo , "FieldRo" ),
119	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LinkPtrInvalid , "LinkPtrInvalid" ),
120	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LongModeCS , "LongModeCS" ),
121	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrInvalid , "PtrInvalid" ),
122	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrMap , "PtrMap" ),
123	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_RealOrV86Mode , "RealOrV86Mode" ),
124	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_VmxRoot , "VmxRoot" ),
125	/* VMREAD. */
126	VMXV_DIAG_DESC(kVmxVDiag_Vmread_Cpl , "Cpl" ),
127	VMXV_DIAG_DESC(kVmxVDiag_Vmread_FieldInvalid , "FieldInvalid" ),
128	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LinkPtrInvalid , "LinkPtrInvalid" ),
129	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LongModeCS , "LongModeCS" ),
130	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrInvalid , "PtrInvalid" ),
131	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrMap , "PtrMap" ),
132	VMXV_DIAG_DESC(kVmxVDiag_Vmread_RealOrV86Mode , "RealOrV86Mode" ),
133	VMXV_DIAG_DESC(kVmxVDiag_Vmread_VmxRoot , "VmxRoot" ),
134	/* INVVPID. */
135	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Cpl , "Cpl" ),
136	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_DescRsvd , "DescRsvd" ),
137	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_LongModeCS , "LongModeCS" ),
138	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_RealOrV86Mode , "RealOrV86Mode" ),
139	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_TypeInvalid , "TypeInvalid" ),
140	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type0InvalidAddr , "Type0InvalidAddr" ),
141	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type0InvalidVpid , "Type0InvalidVpid" ),
142	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type1InvalidVpid , "Type1InvalidVpid" ),
143	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type3InvalidVpid , "Type3InvalidVpid" ),
144	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_VmxRoot , "VmxRoot" ),
145	/* INVEPT. */
146	VMXV_DIAG_DESC(kVmxVDiag_Invept_Cpl , "Cpl" ),
147	VMXV_DIAG_DESC(kVmxVDiag_Invept_DescRsvd , "DescRsvd" ),
148	VMXV_DIAG_DESC(kVmxVDiag_Invept_EptpInvalid , "EptpInvalid" ),
149	VMXV_DIAG_DESC(kVmxVDiag_Invept_LongModeCS , "LongModeCS" ),
150	VMXV_DIAG_DESC(kVmxVDiag_Invept_RealOrV86Mode , "RealOrV86Mode" ),
151	VMXV_DIAG_DESC(kVmxVDiag_Invept_TypeInvalid , "TypeInvalid" ),
152	VMXV_DIAG_DESC(kVmxVDiag_Invept_VmxRoot , "VmxRoot" ),
153	/* VMLAUNCH/VMRESUME. */
154	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess , "AddrApicAccess" ),
155	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic , "AddrApicAccessEqVirtApic" ),
156	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessHandlerReg , "AddrApicAccessHandlerReg" ),
157	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad , "AddrEntryMsrLoad" ),
158	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad , "AddrExitMsrLoad" ),
159	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrStore , "AddrExitMsrStore" ),
160	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapA , "AddrIoBitmapA" ),
161	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapB , "AddrIoBitmapB" ),
162	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrMsrBitmap , "AddrMsrBitmap" ),
163	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVirtApicPage , "AddrVirtApicPage" ),
164	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmcsLinkPtr , "AddrVmcsLinkPtr" ),
165	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmreadBitmap , "AddrVmreadBitmap" ),
166	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmwriteBitmap , "AddrVmwriteBitmap" ),
167	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ApicRegVirt , "ApicRegVirt" ),
168	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_BlocKMovSS , "BlockMovSS" ),
169	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cpl , "Cpl" ),
170	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cr3TargetCount , "Cr3TargetCount" ),
171	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsAllowed1 , "EntryCtlsAllowed1" ),
172	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsDisallowed0 , "EntryCtlsDisallowed0" ),
173	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLen , "EntryInstrLen" ),
174	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLenZero , "EntryInstrLenZero" ),
175	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodePe , "EntryIntInfoErrCodePe" ),
176	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec , "EntryIntInfoErrCodeVec" ),
177	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd , "EntryIntInfoTypeVecRsvd" ),
178	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd , "EntryXcptErrCodeRsvd" ),
179	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EptpAccessDirty , "EptpAccessDirty" ),
180	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EptpPageWalkLength , "EptpPageWalkLength" ),
181	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EptpMemType , "EptpMemType" ),
182	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EptpRsvd , "EptpRsvd" ),
183	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsAllowed1 , "ExitCtlsAllowed1" ),
184	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsDisallowed0 , "ExitCtlsDisallowed0" ),
185	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateHlt , "GuestActStateHlt" ),
186	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateRsvd , "GuestActStateRsvd" ),
187	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateShutdown , "GuestActStateShutdown" ),
188	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateSsDpl , "GuestActStateSsDpl" ),
189	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateStiMovSs , "GuestActStateStiMovSs" ),
190	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed0 , "GuestCr0Fixed0" ),
191	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed1 , "GuestCr0Fixed1" ),
192	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0PgPe , "GuestCr0PgPe" ),
193	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr3 , "GuestCr3" ),
194	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed0 , "GuestCr4Fixed0" ),
195	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed1 , "GuestCr4Fixed1" ),
196	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDebugCtl , "GuestDebugCtl" ),
197	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDr7 , "GuestDr7" ),
198	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsr , "GuestEferMsr" ),
199	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsrRsvd , "GuestEferMsrRsvd" ),
200	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrBase , "GuestGdtrBase" ),
201	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrLimit , "GuestGdtrLimit" ),
202	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ),
203	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ),
204	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ),
205	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ),
206	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ),
207	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ),
208	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ),
209	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ),
210	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ),
211	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ),
212	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ),
213	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ),
214	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPcide , "GuestPcide" ),
215	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte , "GuestPdpteRsvd" ),
216	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf , "GuestPndDbgXcptBsNoTf" ),
217	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf , "GuestPndDbgXcptBsTf" ),
218	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd , "GuestPndDbgXcptRsvd" ),
219	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRtm , "GuestPndDbgXcptRtm" ),
220	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRip , "GuestRip" ),
221	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRipRsvd , "GuestRipRsvd" ),
222	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsIf , "GuestRFlagsIf" ),
223	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsRsvd , "GuestRFlagsRsvd" ),
224	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsVm , "GuestRFlagsVm" ),
225	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDefBig , "GuestSegAttrCsDefBig" ),
226	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs , "GuestSegAttrCsDplEqSs" ),
227	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs , "GuestSegAttrCsDplLtSs" ),
228	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplZero , "GuestSegAttrCsDplZero" ),
229	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsType , "GuestSegAttrCsType" ),
230	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead , "GuestSegAttrCsTypeRead" ),
231	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs , "GuestSegAttrDescTypeCs" ),
232	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs , "GuestSegAttrDescTypeDs" ),
233	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs , "GuestSegAttrDescTypeEs" ),
234	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs , "GuestSegAttrDescTypeFs" ),
235	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs , "GuestSegAttrDescTypeGs" ),
236	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs , "GuestSegAttrDescTypeSs" ),
237	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplCs , "GuestSegAttrDplRplCs" ),
238	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplDs , "GuestSegAttrDplRplDs" ),
239	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplEs , "GuestSegAttrDplRplEs" ),
240	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplFs , "GuestSegAttrDplRplFs" ),
241	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplGs , "GuestSegAttrDplRplGs" ),
242	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplSs , "GuestSegAttrDplRplSs" ),
243	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranCs , "GuestSegAttrGranCs" ),
244	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranDs , "GuestSegAttrGranDs" ),
245	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranEs , "GuestSegAttrGranEs" ),
246	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranFs , "GuestSegAttrGranFs" ),
247	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranGs , "GuestSegAttrGranGs" ),
248	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranSs , "GuestSegAttrGranSs" ),
249	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType , "GuestSegAttrLdtrDescType" ),
250	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrGran , "GuestSegAttrLdtrGran" ),
251	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent , "GuestSegAttrLdtrPresent" ),
252	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd , "GuestSegAttrLdtrRsvd" ),
253	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrType , "GuestSegAttrLdtrType" ),
254	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentCs , "GuestSegAttrPresentCs" ),
255	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentDs , "GuestSegAttrPresentDs" ),
256	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentEs , "GuestSegAttrPresentEs" ),
257	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentFs , "GuestSegAttrPresentFs" ),
258	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentGs , "GuestSegAttrPresentGs" ),
259	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentSs , "GuestSegAttrPresentSs" ),
260	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdCs , "GuestSegAttrRsvdCs" ),
261	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdDs , "GuestSegAttrRsvdDs" ),
262	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdEs , "GuestSegAttrRsvdEs" ),
263	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdFs , "GuestSegAttrRsvdFs" ),
264	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdGs , "GuestSegAttrRsvdGs" ),
265	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdSs , "GuestSegAttrRsvdSs" ),
266	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl , "GuestSegAttrSsDplEqRpl" ),
267	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplZero , "GuestSegAttrSsDplZero " ),
268	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsType , "GuestSegAttrSsType" ),
269	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrDescType , "GuestSegAttrTrDescType" ),
270	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrGran , "GuestSegAttrTrGran" ),
271	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrPresent , "GuestSegAttrTrPresent" ),
272	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrRsvd , "GuestSegAttrTrRsvd" ),
273	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrType , "GuestSegAttrTrType" ),
274	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrUnusable , "GuestSegAttrTrUnusable" ),
275	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs , "GuestSegAttrTypeAccCs" ),
276	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs , "GuestSegAttrTypeAccDs" ),
277	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs , "GuestSegAttrTypeAccEs" ),
278	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs , "GuestSegAttrTypeAccFs" ),
279	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs , "GuestSegAttrTypeAccGs" ),
280	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs , "GuestSegAttrTypeAccSs" ),
281	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Cs , "GuestSegAttrV86Cs" ),
282	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ds , "GuestSegAttrV86Ds" ),
283	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Es , "GuestSegAttrV86Es" ),
284	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Fs , "GuestSegAttrV86Fs" ),
285	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Gs , "GuestSegAttrV86Gs" ),
286	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ss , "GuestSegAttrV86Ss" ),
287	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseCs , "GuestSegBaseCs" ),
288	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseDs , "GuestSegBaseDs" ),
289	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseEs , "GuestSegBaseEs" ),
290	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseFs , "GuestSegBaseFs" ),
291	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseGs , "GuestSegBaseGs" ),
292	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseLdtr , "GuestSegBaseLdtr" ),
293	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseSs , "GuestSegBaseSs" ),
294	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseTr , "GuestSegBaseTr" ),
295	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Cs , "GuestSegBaseV86Cs" ),
296	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ds , "GuestSegBaseV86Ds" ),
297	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Es , "GuestSegBaseV86Es" ),
298	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Fs , "GuestSegBaseV86Fs" ),
299	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Gs , "GuestSegBaseV86Gs" ),
300	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ss , "GuestSegBaseV86Ss" ),
301	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Cs , "GuestSegLimitV86Cs" ),
302	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ds , "GuestSegLimitV86Ds" ),
303	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Es , "GuestSegLimitV86Es" ),
304	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Fs , "GuestSegLimitV86Fs" ),
305	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Gs , "GuestSegLimitV86Gs" ),
306	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ss , "GuestSegLimitV86Ss" ),
307	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelCsSsRpl , "GuestSegSelCsSsRpl" ),
308	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelLdtr , "GuestSegSelLdtr" ),
309	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelTr , "GuestSegSelTr" ),
310	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSysenterEspEip , "GuestSysenterEspEip" ),
311	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs , "VmcsLinkPtrCurVmcs" ),
312	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys , "VmcsLinkPtrReadPhys" ),
313	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrRevId , "VmcsLinkPtrRevId" ),
314	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrShadow , "VmcsLinkPtrShadow" ),
315	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed0 , "HostCr0Fixed0" ),
316	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed1 , "HostCr0Fixed1" ),
317	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr3 , "HostCr3" ),
318	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed0 , "HostCr4Fixed0" ),
319	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed1 , "HostCr4Fixed1" ),
320	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pae , "HostCr4Pae" ),
321	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pcide , "HostCr4Pcide" ),
322	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCsTr , "HostCsTr" ),
323	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsr , "HostEferMsr" ),
324	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsrRsvd , "HostEferMsrRsvd" ),
325	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongMode , "HostGuestLongMode" ),
326	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongModeNoCpu , "HostGuestLongModeNoCpu" ),
327	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostLongMode , "HostLongMode" ),
328	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostPatMsr , "HostPatMsr" ),
329	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRip , "HostRip" ),
330	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRipRsvd , "HostRipRsvd" ),
331	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSel , "HostSel" ),
332	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSegBase , "HostSegBase" ),
333	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSs , "HostSs" ),
334	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSysenterEspEip , "HostSysenterEspEip" ),
335	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys , "IoBitmapAPtrReadPhys" ),
336	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys , "IoBitmapBPtrReadPhys" ),
337	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_LongModeCS , "LongModeCS" ),
338	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys , "MsrBitmapPtrReadPhys" ),
339	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoad , "MsrLoad" ),
340	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadCount , "MsrLoadCount" ),
341	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
342	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRing3 , "MsrLoadRing3" ),
343	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRsvd , "MsrLoadRsvd" ),
344	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_NmiWindowExit , "NmiWindowExit" ),
345	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsAllowed1 , "PinCtlsAllowed1" ),
346	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsDisallowed0 , "PinCtlsDisallowed0" ),
347	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsAllowed1 , "ProcCtlsAllowed1" ),
348	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsDisallowed0 , "ProcCtlsDisallowed0" ),
349	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Allowed1 , "ProcCtls2Allowed1" ),
350	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Disallowed0 , "ProcCtls2Disallowed0" ),
351	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrInvalid , "PtrInvalid" ),
352	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrShadowVmcs , "PtrShadowVmcs" ),
353	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_RealOrV86Mode , "RealOrV86Mode" ),
354	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ),
355	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ),
356	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ),
357	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ),
358	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtIntDelivery , "VirtIntDelivery" ),
359	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtNmi , "VirtNmi" ),
360	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicTprShadow , "VirtX2ApicTprShadow" ),
361	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicVirtApic , "VirtX2ApicVirtApic" ),
362	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsClear , "VmcsClear" ),
363	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLaunch , "VmcsLaunch" ),
364	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys , "VmreadBitmapPtrReadPhys" ),
365	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys , "VmwriteBitmapPtrReadPhys" ),
366	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmxRoot , "VmxRoot" ),
367	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Vpid , "Vpid" ),
368	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte , "HostPdpte" ),
369	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoad , "MsrLoad" ),
370	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadCount , "MsrLoadCount" ),
371	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
372	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRing3 , "MsrLoadRing3" ),
373	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRsvd , "MsrLoadRsvd" ),
374	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStore , "MsrStore" ),
375	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreCount , "MsrStoreCount" ),
376	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrReadPhys , "MsrStorePtrReadPhys" ),
377	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrWritePhys , "MsrStorePtrWritePhys" ),
378	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRing3 , "MsrStoreRing3" ),
379	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRsvd , "MsrStoreRsvd" ),
380	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys , "VirtApicPagePtrWritePhys" )
381	/* kVmxVDiag_End */
382	};
383	AssertCompile(RT_ELEMENTS(g_apszVmxVDiagDesc) == kVmxVDiag_End);
384	#undef VMXV_DIAG_DESC
385
386
387	/**
388	* Gets the descriptive name of a VMX instruction/VM-exit diagnostic code.
389	*
390	* @returns The descriptive string.
391	* @param enmDiag The VMX diagnostic.
392	*/
393	VMM_INT_DECL(const char *) HMGetVmxDiagDesc(VMXVDIAG enmDiag)
394	{
395	if (RT_LIKELY((unsigned)enmDiag < RT_ELEMENTS(g_apszVmxVDiagDesc)))
396	return g_apszVmxVDiagDesc[enmDiag];
397	return "Unknown/invalid";
398	}
399
400
401	/**
402	* Checks if a code selector (CS) is suitable for execution using hardware-assisted
403	* VMX when unrestricted execution isn't available.
404	*
405	* @returns true if selector is suitable for VMX, otherwise
406	* false.
407	* @param pSel Pointer to the selector to check (CS).
408	* @param uStackDpl The CPL, aka the DPL of the stack segment.
409	*/
410	static bool hmVmxIsCodeSelectorOk(PCCPUMSELREG pSel, unsigned uStackDpl)
411	{
412	/*
413	* Segment must be an accessed code segment, it must be present and it must
414	* be usable.
415	* Note! These are all standard requirements and if CS holds anything else
416	* we've got buggy code somewhere!
417	*/
418	AssertCompile(X86DESCATTR_TYPE == 0xf);
419	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
420	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
421	("%#x\n", pSel->Attr.u),
422	false);
423
424	/*
425	* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL must equal
426	* SS.DPL for non-confroming segments.
427	* Note! This is also a hard requirement like above.
428	*/
429	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
430	? pSel->Attr.n.u2Dpl <= uStackDpl
431	: pSel->Attr.n.u2Dpl == uStackDpl,
432	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
433	false);
434
435	/*
436	* The following two requirements are VT-x specific:
437	* - G bit must be set if any high limit bits are set.
438	* - G bit must be clear if any low limit bits are clear.
439	*/
440	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
441	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
442	return true;
443	return false;
444	}
445
446
447	/**
448	* Checks if a data selector (DS/ES/FS/GS) is suitable for execution using
449	* hardware-assisted VMX when unrestricted execution isn't available.
450	*
451	* @returns true if selector is suitable for VMX, otherwise
452	* false.
453	* @param pSel Pointer to the selector to check
454	* (DS/ES/FS/GS).
455	*/
456	static bool hmVmxIsDataSelectorOk(PCCPUMSELREG pSel)
457	{
458	/*
459	* Unusable segments are OK. These days they should be marked as such, as
460	* but as an alternative we for old saved states and AMD<->VT-x migration
461	* we also treat segments with all the attributes cleared as unusable.
462	*/
463	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
464	return true;
465
466	/** @todo tighten these checks. Will require CPUM load adjusting. */
467
468	/* Segment must be accessed. */
469	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
470	{
471	/* Code segments must also be readable. */
472	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
473	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
474	{
475	/* The S bit must be set. */
476	if (pSel->Attr.n.u1DescType)
477	{
478	/* Except for conforming segments, DPL >= RPL. */
479	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
480	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
481	{
482	/* Segment must be present. */
483	if (pSel->Attr.n.u1Present)
484	{
485	/*
486	* The following two requirements are VT-x specific:
487	* - G bit must be set if any high limit bits are set.
488	* - G bit must be clear if any low limit bits are clear.
489	*/
490	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
491	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
492	return true;
493	}
494	}
495	}
496	}
497	}
498
499	return false;
500	}
501
502
503	/**
504	* Checks if the stack selector (SS) is suitable for execution using
505	* hardware-assisted VMX when unrestricted execution isn't available.
506	*
507	* @returns true if selector is suitable for VMX, otherwise
508	* false.
509	* @param pSel Pointer to the selector to check (SS).
510	*/
511	static bool hmVmxIsStackSelectorOk(PCCPUMSELREG pSel)
512	{
513	/*
514	* Unusable segments are OK. These days they should be marked as such, as
515	* but as an alternative we for old saved states and AMD<->VT-x migration
516	* we also treat segments with all the attributes cleared as unusable.
517	*/
518	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
519	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
520	return true;
521
522	/*
523	* Segment must be an accessed writable segment, it must be present.
524	* Note! These are all standard requirements and if SS holds anything else
525	* we've got buggy code somewhere!
526	*/
527	AssertCompile(X86DESCATTR_TYPE == 0xf);
528	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
529	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
530	("%#x\n", pSel->Attr.u), false);
531
532	/*
533	* DPL must equal RPL. But in real mode or soon after enabling protected
534	* mode, it might not be.
535	*/
536	if (pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL))
537	{
538	/*
539	* The following two requirements are VT-x specific:
540	* - G bit must be set if any high limit bits are set.
541	* - G bit must be clear if any low limit bits are clear.
542	*/
543	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
544	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
545	return true;
546	}
547	return false;
548	}
549
550
551	/**
552	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count Down at
553	* the Rate Specified" erratum.
554	*
555	* Errata names and related steppings:
556	* - BA86 - D0.
557	* - AAX65 - C2.
558	* - AAU65 - C2, K0.
559	* - AAO95 - B1.
560	* - AAT59 - C2.
561	* - AAK139 - D0.
562	* - AAM126 - C0, C1, D0.
563	* - AAN92 - B1.
564	* - AAJ124 - C0, D0.
565	* - AAP86 - B1.
566	*
567	* Steppings: B1, C0, C1, C2, D0, K0.
568	*
569	* @returns @c true if subject to it, @c false if not.
570	*/
571	VMM_INT_DECL(bool) HMIsSubjectToVmxPreemptTimerErratum(void)
572	{
573	uint32_t u = ASMCpuId_EAX(1);
574	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
575	if ( u == 0x000206E6 /* 323344.pdf - BA86 - D0 - Xeon Processor 7500 Series */
576	\|\| u == 0x00020652 /* 323056.pdf - AAX65 - C2 - Xeon Processor L3406 */
577	/* 322814.pdf - AAT59 - C2 - CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
578	/* 322911.pdf - AAU65 - C2 - CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
579	\|\| u == 0x00020655 /* 322911.pdf - AAU65 - K0 - CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
580	\|\| u == 0x000106E5 /* 322373.pdf - AAO95 - B1 - Xeon Processor 3400 Series */
581	/* 322166.pdf - AAN92 - B1 - CoreTM i7-800 and i5-700 Desktop Processor Series */
582	/* 320767.pdf - AAP86 - B1 - Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
583	\|\| u == 0x000106A0 /* 321333.pdf - AAM126 - C0 - Xeon Processor 3500 Series Specification */
584	\|\| u == 0x000106A1 /* 321333.pdf - AAM126 - C1 - Xeon Processor 3500 Series Specification */
585	\|\| u == 0x000106A4 /* 320836.pdf - AAJ124 - C0 - Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
586	\|\| u == 0x000106A5 /* 321333.pdf - AAM126 - D0 - Xeon Processor 3500 Series Specification */
587	/* 321324.pdf - AAK139 - D0 - Xeon Processor 5500 Series Specification */
588	/* 320836.pdf - AAJ124 - D0 - Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
589	\|\| u == 0x000306A8 /* ?????????? - ?????? - ?? - Xeon E3-1220 v2 */
590	)
591	return true;
592	return false;
593	}
594
595
596	/**
597	* Checks if the guest is in a suitable state for hardware-assisted VMX execution.
598	*
599	* @returns @c true if it is suitable, @c false otherwise.
600	* @param pVM The cross context VM structure.
601	* @param pVCpu The cross context virtual CPU structure.
602	* @param pCtx Pointer to the guest CPU context.
603	*
604	* @remarks @a pCtx can be a partial context and thus may not be necessarily the
605	* same as pVCpu->cpum.GstCtx! Thus don't eliminate the @a pCtx parameter.
606	* Secondly, if additional checks are added that require more of the CPU
607	* state, make sure REM (which supplies a partial state) is updated.
608	*/
609	VMM_INT_DECL(bool) HMCanExecuteVmxGuest(PVMCC pVM, PVMCPUCC pVCpu, PCCPUMCTX pCtx)
610	{
611	Assert(HMIsEnabled(pVM));
612	bool const fUnrestrictedGuest = CTX_EXPR(pVM->hm.s.vmx.fUnrestrictedGuestCfg, pVM->hmr0.s.vmx.fUnrestrictedGuest, RT_NOTHING);
613	Assert( ( fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
614	\|\| (!fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
615
616	pVCpu->hm.s.fActive = false;
617
618	bool const fSupportsRealMode = fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
619	if (!fUnrestrictedGuest)
620	{
621	/*
622	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
623	* guest execution feature is missing (VT-x only).
624	*/
625	if (fSupportsRealMode)
626	{
627	if (CPUMIsGuestInRealModeEx(pCtx))
628	{
629	/*
630	* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
631	* bases, limits, and attributes, i.e. limit must be 64K, base must be selector * 16,
632	* and attributes must be 0x9b for code and 0x93 for code segments.
633	* If this is not true, we cannot execute real mode as V86 and have to fall
634	* back to emulation.
635	*/
636	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
637	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
638	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
639	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
640	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
641	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
642	{
643	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
644	return false;
645	}
646	if ( (pCtx->cs.u32Limit != 0xffff)
647	\|\| (pCtx->ds.u32Limit != 0xffff)
648	\|\| (pCtx->es.u32Limit != 0xffff)
649	\|\| (pCtx->ss.u32Limit != 0xffff)
650	\|\| (pCtx->fs.u32Limit != 0xffff)
651	\|\| (pCtx->gs.u32Limit != 0xffff))
652	{
653	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
654	return false;
655	}
656	if ( (pCtx->cs.Attr.u != 0x9b)
657	\|\| (pCtx->ds.Attr.u != 0x93)
658	\|\| (pCtx->es.Attr.u != 0x93)
659	\|\| (pCtx->ss.Attr.u != 0x93)
660	\|\| (pCtx->fs.Attr.u != 0x93)
661	\|\| (pCtx->gs.Attr.u != 0x93))
662	{
663	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr);
664	return false;
665	}
666	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
667	}
668	else
669	{
670	/*
671	* Verify the requirements for executing code in protected mode. VT-x can't
672	* handle the CPU state right after a switch from real to protected mode
673	* (all sorts of RPL & DPL assumptions).
674	*/
675	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
676	if (pVmcsInfo->fWasInRealMode)
677	{
678	if (!CPUMIsGuestInV86ModeEx(pCtx))
679	{
680	/* The guest switched to protected mode, check if the state is suitable for VT-x. */
681	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
682	{
683	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
684	return false;
685	}
686	if ( !hmVmxIsCodeSelectorOk(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
687	\|\| !hmVmxIsDataSelectorOk(&pCtx->ds)
688	\|\| !hmVmxIsDataSelectorOk(&pCtx->es)
689	\|\| !hmVmxIsDataSelectorOk(&pCtx->fs)
690	\|\| !hmVmxIsDataSelectorOk(&pCtx->gs)
691	\|\| !hmVmxIsStackSelectorOk(&pCtx->ss))
692	{
693	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
694	return false;
695	}
696	}
697	else
698	{
699	/* The guest switched to V86 mode, check if the state is suitable for VT-x. */
700	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
701	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
702	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
703	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
704	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
705	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
706	{
707	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelBase);
708	return false;
709	}
710	if ( pCtx->cs.u32Limit != 0xffff
711	\|\| pCtx->ds.u32Limit != 0xffff
712	\|\| pCtx->es.u32Limit != 0xffff
713	\|\| pCtx->ss.u32Limit != 0xffff
714	\|\| pCtx->fs.u32Limit != 0xffff
715	\|\| pCtx->gs.u32Limit != 0xffff)
716	{
717	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelLimit);
718	return false;
719	}
720	if ( pCtx->cs.Attr.u != 0xf3
721	\|\| pCtx->ds.Attr.u != 0xf3
722	\|\| pCtx->es.Attr.u != 0xf3
723	\|\| pCtx->ss.Attr.u != 0xf3
724	\|\| pCtx->fs.Attr.u != 0xf3
725	\|\| pCtx->gs.Attr.u != 0xf3)
726	{
727	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelAttr);
728	return false;
729	}
730	}
731	}
732	}
733	}
734	else
735	{
736	if (!CPUMIsGuestInLongModeEx(pCtx))
737	{
738	if (/* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap: */
739	!CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING)
740	/* Requires a fake TSS for real mode - stored in the VMM device heap: */
741	\|\| CPUMIsGuestInRealModeEx(pCtx))
742	return false;
743
744	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
745	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
746	return false;
747
748	/*
749	* The guest is about to complete the switch to protected mode. Wait a bit longer.
750	* Windows XP; switch to protected mode; all selectors are marked not present
751	* in the hidden registers (possible recompiler bug; see load_seg_vm).
752	*/
753	/** @todo Is this supposed recompiler bug still relevant with IEM? */
754	if (pCtx->cs.Attr.n.u1Present == 0)
755	return false;
756	if (pCtx->ss.Attr.n.u1Present == 0)
757	return false;
758
759	/*
760	* Windows XP: possible same as above, but new recompiler requires new
761	* heuristics? VT-x doesn't seem to like something about the guest state and
762	* this stuff avoids it.
763	*/
764	/** @todo This check is actually wrong, it doesn't take the direction of the
765	* stack segment into account. But, it does the job for now. */
766	if (pCtx->rsp >= pCtx->ss.u32Limit)
767	return false;
768	}
769	}
770	}
771
772	if (pVM->hm.s.vmx.fEnabled)
773	{
774	/* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
775	uint32_t uCr0Mask = (uint32_t)CTX_EXPR(pVM->hm.s.ForR3.vmx.Msrs.u64Cr0Fixed0, g_HmMsrs.u.vmx.u64Cr0Fixed0, RT_NOTHING);
776
777	/* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
778	uCr0Mask &= ~X86_CR0_NE;
779
780	if (fSupportsRealMode)
781	{
782	/* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
783	uCr0Mask &= ~(X86_CR0_PG \| X86_CR0_PE);
784	}
785	else
786	{
787	/* We support protected mode without paging using identity mapping. */
788	uCr0Mask &= ~X86_CR0_PG;
789	}
790	if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
791	return false;
792
793	/* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
794	uCr0Mask = (uint32_t)~CTX_EXPR(pVM->hm.s.ForR3.vmx.Msrs.u64Cr0Fixed1, g_HmMsrs.u.vmx.u64Cr0Fixed1, RT_NOTHING);
795	if ((pCtx->cr0 & uCr0Mask) != 0)
796	return false;
797
798	/* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
799	uCr0Mask = (uint32_t)CTX_EXPR(pVM->hm.s.ForR3.vmx.Msrs.u64Cr4Fixed0, g_HmMsrs.u.vmx.u64Cr4Fixed0, RT_NOTHING);
800	uCr0Mask &= ~X86_CR4_VMXE;
801	if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
802	return false;
803
804	/* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
805	uCr0Mask = (uint32_t)~CTX_EXPR(pVM->hm.s.ForR3.vmx.Msrs.u64Cr4Fixed1, g_HmMsrs.u.vmx.u64Cr4Fixed1, RT_NOTHING);
806	if ((pCtx->cr4 & uCr0Mask) != 0)
807	return false;
808
809	pVCpu->hm.s.fActive = true;
810	return true;
811	}
812
813	return false;
814	}
815
816
817	/**
818	* Dumps the virtual VMCS state to the release log.
819	*
820	* This is a purely a convenience function to output to the release log because
821	* cpumR3InfoVmxVmcs dumps only to the debug console and isn't always easy to use in
822	* case of a crash.
823	*
824	* @param pVCpu The cross context virtual CPU structure.
825	*/
826	VMM_INT_DECL(void) HMDumpHwvirtVmxState(PVMCPU pVCpu)
827	{
828	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
829	#define HMVMX_DUMP_HOST_XDTR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
830	do { \
831	LogRel((" %s%-4s = {base=%016RX64}\n", \
832	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u)); \
833	} while (0)
834	#define HMVMX_DUMP_HOST_FS_GS_TR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
835	do { \
836	LogRel((" %s%-4s = {%04x base=%016RX64}\n", \
837	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u)); \
838	} while (0)
839	#define HMVMX_DUMP_GUEST_SEGREG(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
840	do { \
841	LogRel((" %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
842	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
843	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr)); \
844	} while (0)
845	#define HMVMX_DUMP_GUEST_XDTR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
846	do { \
847	LogRel((" %s%-4s = {base=%016RX64 limit=%08x}\n", \
848	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit)); \
849	} while (0)
850
851	PCCPUMCTX const pCtx = &pVCpu->cpum.GstCtx;
852	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
853	if (!pVmcs)
854	{
855	LogRel(("Virtual VMCS not allocated\n"));
856	return;
857	}
858	LogRel(("GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon));
859	LogRel(("GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs));
860	LogRel(("GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs));
861	LogRel(("enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag)));
862	LogRel(("uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux));
863	LogRel(("enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort)));
864	LogRel(("uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux));
865	LogRel(("fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode));
866	LogRel(("fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode));
867	LogRel(("fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents));
868	LogRel(("fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret));
869	LogRel(("uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick));
870	LogRel(("uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick));
871	LogRel(("uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick));
872	LogRel(("offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite));
873	LogRel(("fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking));
874	LogRel(("VMCS cache:\n"));
875
876	const char *pszPrefix = " ";
877	/* Header. */
878	{
879	LogRel(("%sHeader:\n", pszPrefix));
880	LogRel((" %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId));
881	LogRel((" %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort)));
882	LogRel((" %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState)));
883	}
884
885	/* Control fields. */
886	{
887	/* 16-bit. */
888	LogRel(("%sControl:\n", pszPrefix));
889	LogRel((" %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid));
890	LogRel((" %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector));
891	LogRel((" %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex));
892
893	/* 32-bit. */
894	LogRel((" %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls));
895	LogRel((" %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls));
896	LogRel((" %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2));
897	LogRel((" %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls));
898	LogRel((" %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls));
899	LogRel((" %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap));
900	LogRel((" %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask));
901	LogRel((" %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch));
902	LogRel((" %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount));
903	LogRel((" %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount));
904	LogRel((" %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount));
905	LogRel((" %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount));
906	LogRel((" %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo));
907	{
908	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
909	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
910	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo)));
911	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType)));
912	LogRel((" %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo)));
913	LogRel((" %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo)));
914	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo)));
915	}
916	LogRel((" %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode));
917	LogRel((" %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen));
918	LogRel((" %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold));
919	LogRel((" %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap));
920	LogRel((" %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow));
921
922	/* 64-bit. */
923	LogRel((" %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u));
924	LogRel((" %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u));
925	LogRel((" %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u));
926	LogRel((" %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u));
927	LogRel((" %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u));
928	LogRel((" %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u));
929	LogRel((" %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u));
930	LogRel((" %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u));
931	LogRel((" %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u));
932	LogRel((" %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u));
933	LogRel((" %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u));
934	LogRel((" %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u));
935	LogRel((" %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u));
936	LogRel((" %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u));
937	LogRel((" %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u));
938	LogRel((" %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u));
939	LogRel((" %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u));
940	LogRel((" %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u));
941	LogRel((" %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u));
942	LogRel((" %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u));
943	LogRel((" %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u));
944	LogRel((" %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u));
945	LogRel((" %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u));
946	LogRel((" %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u));
947	LogRel((" %sSPP table pointer = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u));
948	LogRel((" %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u));
949	LogRel((" %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u));
950
951	/* Natural width. */
952	LogRel((" %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u));
953	LogRel((" %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u));
954	LogRel((" %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u));
955	LogRel((" %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u));
956	LogRel((" %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u));
957	LogRel((" %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u));
958	LogRel((" %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u));
959	LogRel((" %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u));
960	}
961
962	/* Guest state. */
963	{
964	LogRel(("%sGuest state:\n", pszPrefix));
965
966	/* 16-bit. */
967	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Cs, "cs", pszPrefix);
968	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ss, "ss", pszPrefix);
969	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Es, "es", pszPrefix);
970	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ds, "ds", pszPrefix);
971	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Fs, "fs", pszPrefix);
972	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Gs, "gs", pszPrefix);
973	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ldtr, "ldtr", pszPrefix);
974	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Tr, "tr", pszPrefix);
975	HMVMX_DUMP_GUEST_XDTR( pVmcs, Gdtr, "gdtr", pszPrefix);
976	HMVMX_DUMP_GUEST_XDTR( pVmcs, Idtr, "idtr", pszPrefix);
977	LogRel((" %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus));
978	LogRel((" %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex));
979
980	/* 32-bit. */
981	LogRel((" %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState));
982	LogRel((" %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState));
983	LogRel((" %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase));
984	LogRel((" %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS));
985	LogRel((" %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer));
986
987	/* 64-bit. */
988	LogRel((" %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u));
989	LogRel((" %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u));
990	LogRel((" %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u));
991	LogRel((" %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u));
992	LogRel((" %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u));
993	LogRel((" %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u));
994	LogRel((" %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u));
995	LogRel((" %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u));
996	LogRel((" %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u));
997	LogRel((" %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u));
998	LogRel((" %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u));
999
1000	/* Natural width. */
1001	LogRel((" %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u));
1002	LogRel((" %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u));
1003	LogRel((" %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u));
1004	LogRel((" %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u));
1005	LogRel((" %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u));
1006	LogRel((" %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u));
1007	LogRel((" %srflags = %#RX64\n", pszPrefix, pVmcs->u64GuestRFlags.u));
1008	LogRel((" %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u));
1009	LogRel((" %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u));
1010	LogRel((" %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u));
1011	}
1012
1013	/* Host state. */
1014	{
1015	LogRel(("%sHost state:\n", pszPrefix));
1016
1017	/* 16-bit. */
1018	LogRel((" %scs = %#RX16\n", pszPrefix, pVmcs->HostCs));
1019	LogRel((" %sss = %#RX16\n", pszPrefix, pVmcs->HostSs));
1020	LogRel((" %sds = %#RX16\n", pszPrefix, pVmcs->HostDs));
1021	LogRel((" %ses = %#RX16\n", pszPrefix, pVmcs->HostEs));
1022	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Fs, "fs", pszPrefix);
1023	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Gs, "gs", pszPrefix);
1024	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Tr, "tr", pszPrefix);
1025	HMVMX_DUMP_HOST_XDTR(pVmcs, Gdtr, "gdtr", pszPrefix);
1026	HMVMX_DUMP_HOST_XDTR(pVmcs, Idtr, "idtr", pszPrefix);
1027
1028	/* 32-bit. */
1029	LogRel((" %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs));
1030
1031	/* 64-bit. */
1032	LogRel((" %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u));
1033	LogRel((" %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u));
1034	LogRel((" %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u));
1035
1036	/* Natural width. */
1037	LogRel((" %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u));
1038	LogRel((" %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u));
1039	LogRel((" %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u));
1040	LogRel((" %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u));
1041	LogRel((" %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u));
1042	LogRel((" %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u));
1043	LogRel((" %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u));
1044	}
1045
1046	/* Read-only fields. */
1047	{
1048	LogRel(("%sRead-only data fields:\n", pszPrefix));
1049
1050	/* 16-bit (none currently). */
1051
1052	/* 32-bit. */
1053	uint32_t const uExitReason = pVmcs->u32RoExitReason;
1054	LogRel((" %sExit reason = %u (%s)\n", pszPrefix, uExitReason, HMGetVmxExitName(uExitReason)));
1055	LogRel((" %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u));
1056	LogRel((" %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError));
1057	LogRel((" %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo));
1058	{
1059	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
1060	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
1061	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo)));
1062	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType)));
1063	LogRel((" %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo)));
1064	LogRel((" %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo)));
1065	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo)));
1066	}
1067	LogRel((" %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode));
1068	LogRel((" %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo));
1069	{
1070	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
1071	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
1072	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo)));
1073	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType)));
1074	LogRel((" %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo)));
1075	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo)));
1076	}
1077	LogRel((" %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode));
1078	LogRel((" %sVM-exit instruction length = %u bytes\n", pszPrefix, pVmcs->u32RoExitInstrLen));
1079	LogRel((" %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo));
1080
1081	/* 64-bit. */
1082	LogRel((" %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u));
1083
1084	/* Natural width. */
1085	LogRel((" %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u));
1086	LogRel((" %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u));
1087	LogRel((" %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u));
1088	LogRel((" %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u));
1089	LogRel((" %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u));
1090	}
1091
1092	#undef HMVMX_DUMP_HOST_XDTR
1093	#undef HMVMX_DUMP_HOST_FS_GS_TR
1094	#undef HMVMX_DUMP_GUEST_SEGREG
1095	#undef HMVMX_DUMP_GUEST_XDTR
1096	}
1097
1098
1099	/**
1100	* Gets the active (in use) VMCS info. object for the specified VCPU.
1101	*
1102	* This is either the guest or nested-guest VMCS info. and need not necessarily
1103	* pertain to the "current" VMCS (in the VMX definition of the term). For instance,
1104	* if the VM-entry failed due to an invalid-guest state, we may have "cleared" the
1105	* current VMCS while returning to ring-3. However, the VMCS info. object for that
1106	* VMCS would still be active and returned here so that we could dump the VMCS
1107	* fields to ring-3 for diagnostics. This function is thus only used to
1108	* distinguish between the nested-guest or guest VMCS.
1109	*
1110	* @returns The active VMCS information.
1111	* @param pVCpu The cross context virtual CPU structure.
1112	*
1113	* @thread EMT.
1114	* @remarks This function may be called with preemption or interrupts disabled!
1115	*/
1116	VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu)
1117	{
1118	#ifdef IN_RING0
1119	if (!pVCpu->hmr0.s.vmx.fSwitchedToNstGstVmcs)
1120	#else
1121	if (!pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3)
1122	#endif
1123	return &pVCpu->hm.s.vmx.VmcsInfo;
1124	return &pVCpu->hm.s.vmx.VmcsInfoNstGst;
1125	}
1126
1127
1128	/**
1129	* Converts a VMX event type into an appropriate TRPM event type.
1130	*
1131	* @returns TRPM event.
1132	* @param uIntInfo The VMX event.
1133	*/
1134	VMM_INT_DECL(TRPMEVENT) HMVmxEventTypeToTrpmEventType(uint32_t uIntInfo)
1135	{
1136	Assert(VMX_IDT_VECTORING_INFO_IS_VALID(uIntInfo));
1137
1138	TRPMEVENT enmTrapType;
1139	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(uIntInfo);
1140	uint8_t const uVector = VMX_IDT_VECTORING_INFO_VECTOR(uIntInfo);
1141
1142	switch (uType)
1143	{
1144	case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
1145	enmTrapType = TRPM_HARDWARE_INT;
1146	break;
1147
1148	case VMX_IDT_VECTORING_INFO_TYPE_NMI:
1149	case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
1150	enmTrapType = TRPM_TRAP;
1151	break;
1152
1153	case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT: /* INT1 (ICEBP). */
1154	Assert(uVector == X86_XCPT_DB); NOREF(uVector);
1155	enmTrapType = TRPM_SOFTWARE_INT;
1156	break;
1157
1158	case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* INT3 (#BP) and INTO (#OF) */
1159	Assert(uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF); NOREF(uVector);
1160	enmTrapType = TRPM_SOFTWARE_INT;
1161	break;
1162
1163	case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
1164	enmTrapType = TRPM_SOFTWARE_INT;
1165	break;
1166
1167	default:
1168	AssertMsgFailed(("Invalid trap type %#x\n", uType));
1169	enmTrapType = TRPM_32BIT_HACK;
1170	break;
1171	}
1172
1173	return enmTrapType;
1174	}
1175
1176
1177	/**
1178	* Converts a TRPM event type into an appropriate VMX event type.
1179	*
1180	* @returns VMX event type mask.
1181	* @param uVector The event vector.
1182	* @param enmTrpmEvent The TRPM event.
1183	* @param fIcebp Whether the \#DB vector is caused by an INT1/ICEBP
1184	* instruction.
1185	*/
1186	VMM_INT_DECL(uint32_t) HMTrpmEventTypeToVmxEventType(uint8_t uVector, TRPMEVENT enmTrpmEvent, bool fIcebp)
1187	{
1188	uint32_t uIntInfoType = 0;
1189	if (enmTrpmEvent == TRPM_TRAP)
1190	{
1191	Assert(!fIcebp);
1192	switch (uVector)
1193	{
1194	case X86_XCPT_NMI:
1195	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_NMI << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1196	break;
1197
1198	case X86_XCPT_BP:
1199	case X86_XCPT_OF:
1200	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1201	break;
1202
1203	case X86_XCPT_PF:
1204	case X86_XCPT_DF:
1205	case X86_XCPT_TS:
1206	case X86_XCPT_NP:
1207	case X86_XCPT_SS:
1208	case X86_XCPT_GP:
1209	case X86_XCPT_AC:
1210	uIntInfoType \|= VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID;
1211	RT_FALL_THRU();
1212	default:
1213	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1214	break;
1215	}
1216	}
1217	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
1218	{
1219	Assert(!fIcebp);
1220	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_EXT_INT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1221	}
1222	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
1223	{
1224	switch (uVector)
1225	{
1226	case X86_XCPT_BP:
1227	case X86_XCPT_OF:
1228	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1229	break;
1230
1231	case X86_XCPT_DB:
1232	{
1233	if (fIcebp)
1234	{
1235	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1236	break;
1237	}
1238	RT_FALL_THRU();
1239	}
1240	default:
1241	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_SW_INT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1242	break;
1243	}
1244	}
1245	else
1246	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
1247	return uIntInfoType;
1248	}
1249
1250
1251	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1252	/**
1253	* Notification callback for when a VM-exit happens outside VMX R0 code (e.g. in
1254	* IEM).
1255	*
1256	* @param pVCpu The cross context virtual CPU structure.
1257	*
1258	* @remarks Can be called from ring-0 as well as ring-3.
1259	*/
1260	VMM_INT_DECL(void) HMNotifyVmxNstGstVmexit(PVMCPU pVCpu)
1261	{
1262	LogFlowFunc(("\n"));
1263
1264	/*
1265	* Transitions to ring-3 flag a full CPU-state change except if we transition to ring-3
1266	* in response to a physical CPU interrupt as no changes to the guest-CPU state are
1267	* expected (see VINF_EM_RAW_INTERRUPT handling in hmR0VmxExitToRing3).
1268	*
1269	* However, with nested-guests, the state -can- change on trips to ring-3 for we might
1270	* try to inject a nested-guest physical interrupt and cause a VMX_EXIT_EXT_INT VM-exit
1271	* for the nested-guest from ring-3.
1272	*
1273	* Signalling reload of just the guest-CPU state that changed with the VM-exit is -not-
1274	* sufficient since HM also needs to reload state related to VM-entry/VM-exit controls
1275	* etc. So signal reloading of the entire state. It does not seem worth making this any
1276	* more fine grained at the moment.
1277	*/
1278	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ALL);
1279	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
1280
1281	/*
1282	* Make sure we need to merge the guest VMCS controls with the nested-guest
1283	* VMCS controls on the next nested-guest VM-entry.
1284	*/
1285	pVCpu->hm.s.vmx.fMergedNstGstCtls = false;
1286
1287	/*
1288	* Flush the TLB before entering the outer guest execution (mainly required since the
1289	* APIC-access guest-physical address would have changed and probably more things in
1290	* the future).
1291	*/
1292	pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb = true;
1293
1294	/** @todo Handle releasing of the page-mapping lock later. */
1295	#if 0
1296	if (pVCpu->hm.s.vmx.fVirtApicPageLocked)
1297	{
1298	PGMPhysReleasePageMappingLock(pVCpu->CTX_SUFF(pVM), &pVCpu->hm.s.vmx.PgMapLockVirtApic);
1299	pVCpu->hm.s.vmx.fVirtApicPageLocked = false;
1300	}
1301	#endif
1302	}
1303
1304
1305	/**
1306	* Notification callback for when the nested hypervisor's current VMCS is loaded or
1307	* changed outside VMX R0 code (e.g. in IEM).
1308	*
1309	* This need -not- be called for modifications to the nested hypervisor's current
1310	* VMCS when the guest is in VMX non-root mode as VMCS shadowing is not applicable
1311	* there.
1312	*
1313	* @param pVCpu The cross context virtual CPU structure.
1314	*
1315	* @remarks Can be called from ring-0 as well as ring-3.
1316	*/
1317	VMM_INT_DECL(void) HMNotifyVmxNstGstCurrentVmcsChanged(PVMCPU pVCpu)
1318	{
1319	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1320	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, CPUMCTX_EXTRN_HWVIRT);
1321
1322	/*
1323	* Make sure we need to copy the nested hypervisor's current VMCS into the shadow VMCS
1324	* on the next guest VM-entry.
1325	*/
1326	pVCpu->hm.s.vmx.fCopiedNstGstToShadowVmcs = false;
1327	}
1328
1329	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
1330

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp@ 93115

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