HMVMXAll.cpp@ 84247

Last change on this file since 84247 was 82968, checked in by vboxsync, 5 years ago
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1	/* $Id: HMVMXAll.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2	/** @file
3	* HM VMX (VT-x) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2018-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/hmvmxinline.h>
26	#include <VBox/vmm/vmcc.h>
27	#include <VBox/vmm/pdmapi.h>
28	#include <iprt/errcore.h>
29
30
31	/*********************************************************************************************************************************
32	* Global Variables *
33	*********************************************************************************************************************************/
34	#define VMXV_DIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
35	/** VMX virtual-instructions and VM-exit diagnostics. */
36	static const char * const g_apszVmxVDiagDesc[] =
37	{
38	/* Internal processing errors. */
39	VMXV_DIAG_DESC(kVmxVDiag_None , "None" ),
40	VMXV_DIAG_DESC(kVmxVDiag_Ipe_1 , "Ipe_1" ),
41	VMXV_DIAG_DESC(kVmxVDiag_Ipe_2 , "Ipe_2" ),
42	VMXV_DIAG_DESC(kVmxVDiag_Ipe_3 , "Ipe_3" ),
43	VMXV_DIAG_DESC(kVmxVDiag_Ipe_4 , "Ipe_4" ),
44	VMXV_DIAG_DESC(kVmxVDiag_Ipe_5 , "Ipe_5" ),
45	VMXV_DIAG_DESC(kVmxVDiag_Ipe_6 , "Ipe_6" ),
46	VMXV_DIAG_DESC(kVmxVDiag_Ipe_7 , "Ipe_7" ),
47	VMXV_DIAG_DESC(kVmxVDiag_Ipe_8 , "Ipe_8" ),
48	VMXV_DIAG_DESC(kVmxVDiag_Ipe_9 , "Ipe_9" ),
49	VMXV_DIAG_DESC(kVmxVDiag_Ipe_10 , "Ipe_10" ),
50	VMXV_DIAG_DESC(kVmxVDiag_Ipe_11 , "Ipe_11" ),
51	VMXV_DIAG_DESC(kVmxVDiag_Ipe_12 , "Ipe_12" ),
52	VMXV_DIAG_DESC(kVmxVDiag_Ipe_13 , "Ipe_13" ),
53	VMXV_DIAG_DESC(kVmxVDiag_Ipe_14 , "Ipe_14" ),
54	VMXV_DIAG_DESC(kVmxVDiag_Ipe_15 , "Ipe_15" ),
55	VMXV_DIAG_DESC(kVmxVDiag_Ipe_16 , "Ipe_16" ),
56	/* VMXON. */
57	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_A20M , "A20M" ),
58	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cpl , "Cpl" ),
59	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed0 , "Cr0Fixed0" ),
60	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed1 , "Cr0Fixed1" ),
61	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed0 , "Cr4Fixed0" ),
62	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed1 , "Cr4Fixed1" ),
63	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Intercept , "Intercept" ),
64	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_LongModeCS , "LongModeCS" ),
65	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_MsrFeatCtl , "MsrFeatCtl" ),
66	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAbnormal , "PtrAbnormal" ),
67	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAlign , "PtrAlign" ),
68	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrMap , "PtrMap" ),
69	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrReadPhys , "PtrReadPhys" ),
70	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrWidth , "PtrWidth" ),
71	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_RealOrV86Mode , "RealOrV86Mode" ),
72	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_ShadowVmcs , "ShadowVmcs" ),
73	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxAlreadyRoot , "VmxAlreadyRoot" ),
74	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Vmxe , "Vmxe" ),
75	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmcsRevId , "VmcsRevId" ),
76	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxRootCpl , "VmxRootCpl" ),
77	/* VMXOFF. */
78	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Cpl , "Cpl" ),
79	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Intercept , "Intercept" ),
80	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_LongModeCS , "LongModeCS" ),
81	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_RealOrV86Mode , "RealOrV86Mode" ),
82	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Vmxe , "Vmxe" ),
83	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_VmxRoot , "VmxRoot" ),
84	/* VMPTRLD. */
85	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_Cpl , "Cpl" ),
86	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_LongModeCS , "LongModeCS" ),
87	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAbnormal , "PtrAbnormal" ),
88	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAlign , "PtrAlign" ),
89	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrMap , "PtrMap" ),
90	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrReadPhys , "PtrReadPhys" ),
91	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrVmxon , "PtrVmxon" ),
92	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrWidth , "PtrWidth" ),
93	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RealOrV86Mode , "RealOrV86Mode" ),
94	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RevPtrReadPhys , "RevPtrReadPhys" ),
95	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_ShadowVmcs , "ShadowVmcs" ),
96	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmcsRevId , "VmcsRevId" ),
97	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmxRoot , "VmxRoot" ),
98	/* VMPTRST. */
99	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_Cpl , "Cpl" ),
100	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_LongModeCS , "LongModeCS" ),
101	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_PtrMap , "PtrMap" ),
102	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_RealOrV86Mode , "RealOrV86Mode" ),
103	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_VmxRoot , "VmxRoot" ),
104	/* VMCLEAR. */
105	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_Cpl , "Cpl" ),
106	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_LongModeCS , "LongModeCS" ),
107	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAbnormal , "PtrAbnormal" ),
108	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAlign , "PtrAlign" ),
109	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrMap , "PtrMap" ),
110	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrReadPhys , "PtrReadPhys" ),
111	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrVmxon , "PtrVmxon" ),
112	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrWidth , "PtrWidth" ),
113	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_RealOrV86Mode , "RealOrV86Mode" ),
114	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_VmxRoot , "VmxRoot" ),
115	/* VMWRITE. */
116	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_Cpl , "Cpl" ),
117	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldInvalid , "FieldInvalid" ),
118	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldRo , "FieldRo" ),
119	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LinkPtrInvalid , "LinkPtrInvalid" ),
120	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LongModeCS , "LongModeCS" ),
121	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrInvalid , "PtrInvalid" ),
122	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrMap , "PtrMap" ),
123	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_RealOrV86Mode , "RealOrV86Mode" ),
124	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_VmxRoot , "VmxRoot" ),
125	/* VMREAD. */
126	VMXV_DIAG_DESC(kVmxVDiag_Vmread_Cpl , "Cpl" ),
127	VMXV_DIAG_DESC(kVmxVDiag_Vmread_FieldInvalid , "FieldInvalid" ),
128	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LinkPtrInvalid , "LinkPtrInvalid" ),
129	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LongModeCS , "LongModeCS" ),
130	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrInvalid , "PtrInvalid" ),
131	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrMap , "PtrMap" ),
132	VMXV_DIAG_DESC(kVmxVDiag_Vmread_RealOrV86Mode , "RealOrV86Mode" ),
133	VMXV_DIAG_DESC(kVmxVDiag_Vmread_VmxRoot , "VmxRoot" ),
134	/* INVVPID. */
135	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Cpl , "Cpl" ),
136	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_DescRsvd , "DescRsvd" ),
137	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_LongModeCS , "LongModeCS" ),
138	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_RealOrV86Mode , "RealOrV86Mode" ),
139	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_TypeInvalid , "TypeInvalid" ),
140	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type0InvalidAddr , "Type0InvalidAddr" ),
141	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type0InvalidVpid , "Type0InvalidVpid" ),
142	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type1InvalidVpid , "Type1InvalidVpid" ),
143	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type3InvalidVpid , "Type3InvalidVpid" ),
144	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_VmxRoot , "VmxRoot" ),
145	/* VMLAUNCH/VMRESUME. */
146	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess , "AddrApicAccess" ),
147	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic , "AddrApicAccessEqVirtApic" ),
148	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessHandlerReg , "AddrApicAccessHandlerReg" ),
149	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad , "AddrEntryMsrLoad" ),
150	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad , "AddrExitMsrLoad" ),
151	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrStore , "AddrExitMsrStore" ),
152	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapA , "AddrIoBitmapA" ),
153	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapB , "AddrIoBitmapB" ),
154	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrMsrBitmap , "AddrMsrBitmap" ),
155	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVirtApicPage , "AddrVirtApicPage" ),
156	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmcsLinkPtr , "AddrVmcsLinkPtr" ),
157	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmreadBitmap , "AddrVmreadBitmap" ),
158	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmwriteBitmap , "AddrVmwriteBitmap" ),
159	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ApicRegVirt , "ApicRegVirt" ),
160	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_BlocKMovSS , "BlockMovSS" ),
161	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cpl , "Cpl" ),
162	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cr3TargetCount , "Cr3TargetCount" ),
163	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsAllowed1 , "EntryCtlsAllowed1" ),
164	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsDisallowed0 , "EntryCtlsDisallowed0" ),
165	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLen , "EntryInstrLen" ),
166	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLenZero , "EntryInstrLenZero" ),
167	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodePe , "EntryIntInfoErrCodePe" ),
168	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec , "EntryIntInfoErrCodeVec" ),
169	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd , "EntryIntInfoTypeVecRsvd" ),
170	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd , "EntryXcptErrCodeRsvd" ),
171	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsAllowed1 , "ExitCtlsAllowed1" ),
172	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsDisallowed0 , "ExitCtlsDisallowed0" ),
173	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateHlt , "GuestActStateHlt" ),
174	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateRsvd , "GuestActStateRsvd" ),
175	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateShutdown , "GuestActStateShutdown" ),
176	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateSsDpl , "GuestActStateSsDpl" ),
177	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateStiMovSs , "GuestActStateStiMovSs" ),
178	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed0 , "GuestCr0Fixed0" ),
179	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed1 , "GuestCr0Fixed1" ),
180	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0PgPe , "GuestCr0PgPe" ),
181	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr3 , "GuestCr3" ),
182	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed0 , "GuestCr4Fixed0" ),
183	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed1 , "GuestCr4Fixed1" ),
184	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDebugCtl , "GuestDebugCtl" ),
185	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDr7 , "GuestDr7" ),
186	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsr , "GuestEferMsr" ),
187	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsrRsvd , "GuestEferMsrRsvd" ),
188	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrBase , "GuestGdtrBase" ),
189	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrLimit , "GuestGdtrLimit" ),
190	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ),
191	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ),
192	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ),
193	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ),
194	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ),
195	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ),
196	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ),
197	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ),
198	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ),
199	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ),
200	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ),
201	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ),
202	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPcide , "GuestPcide" ),
203	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys , "GuestPdpteCr3ReadPhys" ),
204	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte0Rsvd , "GuestPdpte0Rsvd" ),
205	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte1Rsvd , "GuestPdpte1Rsvd" ),
206	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte2Rsvd , "GuestPdpte2Rsvd" ),
207	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte3Rsvd , "GuestPdpte3Rsvd" ),
208	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf , "GuestPndDbgXcptBsNoTf" ),
209	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf , "GuestPndDbgXcptBsTf" ),
210	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd , "GuestPndDbgXcptRsvd" ),
211	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRtm , "GuestPndDbgXcptRtm" ),
212	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRip , "GuestRip" ),
213	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRipRsvd , "GuestRipRsvd" ),
214	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsIf , "GuestRFlagsIf" ),
215	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsRsvd , "GuestRFlagsRsvd" ),
216	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsVm , "GuestRFlagsVm" ),
217	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDefBig , "GuestSegAttrCsDefBig" ),
218	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs , "GuestSegAttrCsDplEqSs" ),
219	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs , "GuestSegAttrCsDplLtSs" ),
220	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplZero , "GuestSegAttrCsDplZero" ),
221	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsType , "GuestSegAttrCsType" ),
222	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead , "GuestSegAttrCsTypeRead" ),
223	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs , "GuestSegAttrDescTypeCs" ),
224	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs , "GuestSegAttrDescTypeDs" ),
225	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs , "GuestSegAttrDescTypeEs" ),
226	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs , "GuestSegAttrDescTypeFs" ),
227	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs , "GuestSegAttrDescTypeGs" ),
228	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs , "GuestSegAttrDescTypeSs" ),
229	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplCs , "GuestSegAttrDplRplCs" ),
230	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplDs , "GuestSegAttrDplRplDs" ),
231	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplEs , "GuestSegAttrDplRplEs" ),
232	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplFs , "GuestSegAttrDplRplFs" ),
233	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplGs , "GuestSegAttrDplRplGs" ),
234	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplSs , "GuestSegAttrDplRplSs" ),
235	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranCs , "GuestSegAttrGranCs" ),
236	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranDs , "GuestSegAttrGranDs" ),
237	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranEs , "GuestSegAttrGranEs" ),
238	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranFs , "GuestSegAttrGranFs" ),
239	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranGs , "GuestSegAttrGranGs" ),
240	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranSs , "GuestSegAttrGranSs" ),
241	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType , "GuestSegAttrLdtrDescType" ),
242	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrGran , "GuestSegAttrLdtrGran" ),
243	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent , "GuestSegAttrLdtrPresent" ),
244	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd , "GuestSegAttrLdtrRsvd" ),
245	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrType , "GuestSegAttrLdtrType" ),
246	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentCs , "GuestSegAttrPresentCs" ),
247	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentDs , "GuestSegAttrPresentDs" ),
248	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentEs , "GuestSegAttrPresentEs" ),
249	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentFs , "GuestSegAttrPresentFs" ),
250	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentGs , "GuestSegAttrPresentGs" ),
251	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentSs , "GuestSegAttrPresentSs" ),
252	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdCs , "GuestSegAttrRsvdCs" ),
253	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdDs , "GuestSegAttrRsvdDs" ),
254	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdEs , "GuestSegAttrRsvdEs" ),
255	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdFs , "GuestSegAttrRsvdFs" ),
256	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdGs , "GuestSegAttrRsvdGs" ),
257	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdSs , "GuestSegAttrRsvdSs" ),
258	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl , "GuestSegAttrSsDplEqRpl" ),
259	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplZero , "GuestSegAttrSsDplZero " ),
260	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsType , "GuestSegAttrSsType" ),
261	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrDescType , "GuestSegAttrTrDescType" ),
262	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrGran , "GuestSegAttrTrGran" ),
263	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrPresent , "GuestSegAttrTrPresent" ),
264	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrRsvd , "GuestSegAttrTrRsvd" ),
265	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrType , "GuestSegAttrTrType" ),
266	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrUnusable , "GuestSegAttrTrUnusable" ),
267	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs , "GuestSegAttrTypeAccCs" ),
268	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs , "GuestSegAttrTypeAccDs" ),
269	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs , "GuestSegAttrTypeAccEs" ),
270	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs , "GuestSegAttrTypeAccFs" ),
271	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs , "GuestSegAttrTypeAccGs" ),
272	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs , "GuestSegAttrTypeAccSs" ),
273	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Cs , "GuestSegAttrV86Cs" ),
274	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ds , "GuestSegAttrV86Ds" ),
275	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Es , "GuestSegAttrV86Es" ),
276	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Fs , "GuestSegAttrV86Fs" ),
277	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Gs , "GuestSegAttrV86Gs" ),
278	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ss , "GuestSegAttrV86Ss" ),
279	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseCs , "GuestSegBaseCs" ),
280	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseDs , "GuestSegBaseDs" ),
281	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseEs , "GuestSegBaseEs" ),
282	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseFs , "GuestSegBaseFs" ),
283	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseGs , "GuestSegBaseGs" ),
284	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseLdtr , "GuestSegBaseLdtr" ),
285	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseSs , "GuestSegBaseSs" ),
286	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseTr , "GuestSegBaseTr" ),
287	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Cs , "GuestSegBaseV86Cs" ),
288	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ds , "GuestSegBaseV86Ds" ),
289	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Es , "GuestSegBaseV86Es" ),
290	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Fs , "GuestSegBaseV86Fs" ),
291	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Gs , "GuestSegBaseV86Gs" ),
292	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ss , "GuestSegBaseV86Ss" ),
293	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Cs , "GuestSegLimitV86Cs" ),
294	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ds , "GuestSegLimitV86Ds" ),
295	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Es , "GuestSegLimitV86Es" ),
296	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Fs , "GuestSegLimitV86Fs" ),
297	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Gs , "GuestSegLimitV86Gs" ),
298	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ss , "GuestSegLimitV86Ss" ),
299	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelCsSsRpl , "GuestSegSelCsSsRpl" ),
300	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelLdtr , "GuestSegSelLdtr" ),
301	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelTr , "GuestSegSelTr" ),
302	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSysenterEspEip , "GuestSysenterEspEip" ),
303	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs , "VmcsLinkPtrCurVmcs" ),
304	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys , "VmcsLinkPtrReadPhys" ),
305	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrRevId , "VmcsLinkPtrRevId" ),
306	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrShadow , "VmcsLinkPtrShadow" ),
307	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed0 , "HostCr0Fixed0" ),
308	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed1 , "HostCr0Fixed1" ),
309	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr3 , "HostCr3" ),
310	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed0 , "HostCr4Fixed0" ),
311	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed1 , "HostCr4Fixed1" ),
312	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pae , "HostCr4Pae" ),
313	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pcide , "HostCr4Pcide" ),
314	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCsTr , "HostCsTr" ),
315	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsr , "HostEferMsr" ),
316	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsrRsvd , "HostEferMsrRsvd" ),
317	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongMode , "HostGuestLongMode" ),
318	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongModeNoCpu , "HostGuestLongModeNoCpu" ),
319	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostLongMode , "HostLongMode" ),
320	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostPatMsr , "HostPatMsr" ),
321	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRip , "HostRip" ),
322	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRipRsvd , "HostRipRsvd" ),
323	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSel , "HostSel" ),
324	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSegBase , "HostSegBase" ),
325	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSs , "HostSs" ),
326	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSysenterEspEip , "HostSysenterEspEip" ),
327	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys , "IoBitmapAPtrReadPhys" ),
328	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys , "IoBitmapBPtrReadPhys" ),
329	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_LongModeCS , "LongModeCS" ),
330	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys , "MsrBitmapPtrReadPhys" ),
331	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoad , "MsrLoad" ),
332	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadCount , "MsrLoadCount" ),
333	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
334	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRing3 , "MsrLoadRing3" ),
335	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRsvd , "MsrLoadRsvd" ),
336	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_NmiWindowExit , "NmiWindowExit" ),
337	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsAllowed1 , "PinCtlsAllowed1" ),
338	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsDisallowed0 , "PinCtlsDisallowed0" ),
339	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsAllowed1 , "ProcCtlsAllowed1" ),
340	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsDisallowed0 , "ProcCtlsDisallowed0" ),
341	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Allowed1 , "ProcCtls2Allowed1" ),
342	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Disallowed0 , "ProcCtls2Disallowed0" ),
343	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrInvalid , "PtrInvalid" ),
344	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrShadowVmcs , "PtrShadowVmcs" ),
345	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_RealOrV86Mode , "RealOrV86Mode" ),
346	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ),
347	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ),
348	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ),
349	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ),
350	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtIntDelivery , "VirtIntDelivery" ),
351	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtNmi , "VirtNmi" ),
352	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicTprShadow , "VirtX2ApicTprShadow" ),
353	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicVirtApic , "VirtX2ApicVirtApic" ),
354	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsClear , "VmcsClear" ),
355	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLaunch , "VmcsLaunch" ),
356	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys , "VmreadBitmapPtrReadPhys" ),
357	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys , "VmwriteBitmapPtrReadPhys" ),
358	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmxRoot , "VmxRoot" ),
359	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Vpid , "Vpid" ),
360	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys , "HostPdpteCr3ReadPhys" ),
361	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte0Rsvd , "HostPdpte0Rsvd" ),
362	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte1Rsvd , "HostPdpte1Rsvd" ),
363	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte2Rsvd , "HostPdpte2Rsvd" ),
364	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte3Rsvd , "HostPdpte3Rsvd" ),
365	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoad , "MsrLoad" ),
366	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadCount , "MsrLoadCount" ),
367	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
368	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRing3 , "MsrLoadRing3" ),
369	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRsvd , "MsrLoadRsvd" ),
370	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStore , "MsrStore" ),
371	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreCount , "MsrStoreCount" ),
372	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrReadPhys , "MsrStorePtrReadPhys" ),
373	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrWritePhys , "MsrStorePtrWritePhys" ),
374	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRing3 , "MsrStoreRing3" ),
375	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRsvd , "MsrStoreRsvd" ),
376	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys , "VirtApicPagePtrWritePhys" )
377	/* kVmxVDiag_End */
378	};
379	AssertCompile(RT_ELEMENTS(g_apszVmxVDiagDesc) == kVmxVDiag_End);
380	#undef VMXV_DIAG_DESC
381
382
383	/**
384	* Gets the descriptive name of a VMX instruction/VM-exit diagnostic code.
385	*
386	* @returns The descriptive string.
387	* @param enmDiag The VMX diagnostic.
388	*/
389	VMM_INT_DECL(const char *) HMGetVmxDiagDesc(VMXVDIAG enmDiag)
390	{
391	if (RT_LIKELY((unsigned)enmDiag < RT_ELEMENTS(g_apszVmxVDiagDesc)))
392	return g_apszVmxVDiagDesc[enmDiag];
393	return "Unknown/invalid";
394	}
395
396
397	/**
398	* Checks if a code selector (CS) is suitable for execution using hardware-assisted
399	* VMX when unrestricted execution isn't available.
400	*
401	* @returns true if selector is suitable for VMX, otherwise
402	* false.
403	* @param pSel Pointer to the selector to check (CS).
404	* @param uStackDpl The CPL, aka the DPL of the stack segment.
405	*/
406	static bool hmVmxIsCodeSelectorOk(PCCPUMSELREG pSel, unsigned uStackDpl)
407	{
408	/*
409	* Segment must be an accessed code segment, it must be present and it must
410	* be usable.
411	* Note! These are all standard requirements and if CS holds anything else
412	* we've got buggy code somewhere!
413	*/
414	AssertCompile(X86DESCATTR_TYPE == 0xf);
415	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
416	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
417	("%#x\n", pSel->Attr.u),
418	false);
419
420	/*
421	* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL must equal
422	* SS.DPL for non-confroming segments.
423	* Note! This is also a hard requirement like above.
424	*/
425	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
426	? pSel->Attr.n.u2Dpl <= uStackDpl
427	: pSel->Attr.n.u2Dpl == uStackDpl,
428	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
429	false);
430
431	/*
432	* The following two requirements are VT-x specific:
433	* - G bit must be set if any high limit bits are set.
434	* - G bit must be clear if any low limit bits are clear.
435	*/
436	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
437	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
438	return true;
439	return false;
440	}
441
442
443	/**
444	* Checks if a data selector (DS/ES/FS/GS) is suitable for execution using
445	* hardware-assisted VMX when unrestricted execution isn't available.
446	*
447	* @returns true if selector is suitable for VMX, otherwise
448	* false.
449	* @param pSel Pointer to the selector to check
450	* (DS/ES/FS/GS).
451	*/
452	static bool hmVmxIsDataSelectorOk(PCCPUMSELREG pSel)
453	{
454	/*
455	* Unusable segments are OK. These days they should be marked as such, as
456	* but as an alternative we for old saved states and AMD<->VT-x migration
457	* we also treat segments with all the attributes cleared as unusable.
458	*/
459	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
460	return true;
461
462	/** @todo tighten these checks. Will require CPUM load adjusting. */
463
464	/* Segment must be accessed. */
465	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
466	{
467	/* Code segments must also be readable. */
468	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
469	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
470	{
471	/* The S bit must be set. */
472	if (pSel->Attr.n.u1DescType)
473	{
474	/* Except for conforming segments, DPL >= RPL. */
475	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
476	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
477	{
478	/* Segment must be present. */
479	if (pSel->Attr.n.u1Present)
480	{
481	/*
482	* The following two requirements are VT-x specific:
483	* - G bit must be set if any high limit bits are set.
484	* - G bit must be clear if any low limit bits are clear.
485	*/
486	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
487	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
488	return true;
489	}
490	}
491	}
492	}
493	}
494
495	return false;
496	}
497
498
499	/**
500	* Checks if the stack selector (SS) is suitable for execution using
501	* hardware-assisted VMX when unrestricted execution isn't available.
502	*
503	* @returns true if selector is suitable for VMX, otherwise
504	* false.
505	* @param pSel Pointer to the selector to check (SS).
506	*/
507	static bool hmVmxIsStackSelectorOk(PCCPUMSELREG pSel)
508	{
509	/*
510	* Unusable segments are OK. These days they should be marked as such, as
511	* but as an alternative we for old saved states and AMD<->VT-x migration
512	* we also treat segments with all the attributes cleared as unusable.
513	*/
514	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
515	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
516	return true;
517
518	/*
519	* Segment must be an accessed writable segment, it must be present.
520	* Note! These are all standard requirements and if SS holds anything else
521	* we've got buggy code somewhere!
522	*/
523	AssertCompile(X86DESCATTR_TYPE == 0xf);
524	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
525	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
526	("%#x\n", pSel->Attr.u), false);
527
528	/*
529	* DPL must equal RPL. But in real mode or soon after enabling protected
530	* mode, it might not be.
531	*/
532	if (pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL))
533	{
534	/*
535	* The following two requirements are VT-x specific:
536	* - G bit must be set if any high limit bits are set.
537	* - G bit must be clear if any low limit bits are clear.
538	*/
539	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
540	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
541	return true;
542	}
543	return false;
544	}
545
546
547	/**
548	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count Down at
549	* the Rate Specified" erratum.
550	*
551	* Errata names and related steppings:
552	* - BA86 - D0.
553	* - AAX65 - C2.
554	* - AAU65 - C2, K0.
555	* - AAO95 - B1.
556	* - AAT59 - C2.
557	* - AAK139 - D0.
558	* - AAM126 - C0, C1, D0.
559	* - AAN92 - B1.
560	* - AAJ124 - C0, D0.
561	* - AAP86 - B1.
562	*
563	* Steppings: B1, C0, C1, C2, D0, K0.
564	*
565	* @returns @c true if subject to it, @c false if not.
566	*/
567	VMM_INT_DECL(bool) HMIsSubjectToVmxPreemptTimerErratum(void)
568	{
569	uint32_t u = ASMCpuId_EAX(1);
570	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
571	if ( u == 0x000206E6 /* 323344.pdf - BA86 - D0 - Xeon Processor 7500 Series */
572	\|\| u == 0x00020652 /* 323056.pdf - AAX65 - C2 - Xeon Processor L3406 */
573	/* 322814.pdf - AAT59 - C2 - CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
574	/* 322911.pdf - AAU65 - C2 - CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
575	\|\| u == 0x00020655 /* 322911.pdf - AAU65 - K0 - CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
576	\|\| u == 0x000106E5 /* 322373.pdf - AAO95 - B1 - Xeon Processor 3400 Series */
577	/* 322166.pdf - AAN92 - B1 - CoreTM i7-800 and i5-700 Desktop Processor Series */
578	/* 320767.pdf - AAP86 - B1 - Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
579	\|\| u == 0x000106A0 /* 321333.pdf - AAM126 - C0 - Xeon Processor 3500 Series Specification */
580	\|\| u == 0x000106A1 /* 321333.pdf - AAM126 - C1 - Xeon Processor 3500 Series Specification */
581	\|\| u == 0x000106A4 /* 320836.pdf - AAJ124 - C0 - Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
582	\|\| u == 0x000106A5 /* 321333.pdf - AAM126 - D0 - Xeon Processor 3500 Series Specification */
583	/* 321324.pdf - AAK139 - D0 - Xeon Processor 5500 Series Specification */
584	/* 320836.pdf - AAJ124 - D0 - Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
585	)
586	return true;
587	return false;
588	}
589
590
591	/**
592	* Checks if the guest is in a suitable state for hardware-assisted VMX execution.
593	*
594	* @returns @c true if it is suitable, @c false otherwise.
595	* @param pVM The cross context VM structure.
596	* @param pVCpu The cross context virtual CPU structure.
597	* @param pCtx Pointer to the guest CPU context.
598	*
599	* @remarks @a pCtx can be a partial context and thus may not be necessarily the
600	* same as pVCpu->cpum.GstCtx! Thus don't eliminate the @a pCtx parameter.
601	* Secondly, if additional checks are added that require more of the CPU
602	* state, make sure REM (which supplies a partial state) is updated.
603	*/
604	VMM_INT_DECL(bool) HMCanExecuteVmxGuest(PVMCC pVM, PVMCPUCC pVCpu, PCCPUMCTX pCtx)
605	{
606	Assert(HMIsEnabled(pVM));
607	Assert( ( pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
608	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
609
610	pVCpu->hm.s.fActive = false;
611
612	bool const fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
613	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
614	{
615	/*
616	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
617	* guest execution feature is missing (VT-x only).
618	*/
619	if (fSupportsRealMode)
620	{
621	if (CPUMIsGuestInRealModeEx(pCtx))
622	{
623	/*
624	* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
625	* bases, limits, and attributes, i.e. limit must be 64K, base must be selector * 16,
626	* and attributes must be 0x9b for code and 0x93 for code segments.
627	* If this is not true, we cannot execute real mode as V86 and have to fall
628	* back to emulation.
629	*/
630	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
631	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
632	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
633	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
634	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
635	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
636	{
637	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
638	return false;
639	}
640	if ( (pCtx->cs.u32Limit != 0xffff)
641	\|\| (pCtx->ds.u32Limit != 0xffff)
642	\|\| (pCtx->es.u32Limit != 0xffff)
643	\|\| (pCtx->ss.u32Limit != 0xffff)
644	\|\| (pCtx->fs.u32Limit != 0xffff)
645	\|\| (pCtx->gs.u32Limit != 0xffff))
646	{
647	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
648	return false;
649	}
650	if ( (pCtx->cs.Attr.u != 0x9b)
651	\|\| (pCtx->ds.Attr.u != 0x93)
652	\|\| (pCtx->es.Attr.u != 0x93)
653	\|\| (pCtx->ss.Attr.u != 0x93)
654	\|\| (pCtx->fs.Attr.u != 0x93)
655	\|\| (pCtx->gs.Attr.u != 0x93))
656	{
657	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr);
658	return false;
659	}
660	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
661	}
662	else
663	{
664	/*
665	* Verify the requirements for executing code in protected mode. VT-x can't
666	* handle the CPU state right after a switch from real to protected mode
667	* (all sorts of RPL & DPL assumptions).
668	*/
669	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
670	if (pVmcsInfo->fWasInRealMode)
671	{
672	if (!CPUMIsGuestInV86ModeEx(pCtx))
673	{
674	/* The guest switched to protected mode, check if the state is suitable for VT-x. */
675	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
676	{
677	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
678	return false;
679	}
680	if ( !hmVmxIsCodeSelectorOk(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
681	\|\| !hmVmxIsDataSelectorOk(&pCtx->ds)
682	\|\| !hmVmxIsDataSelectorOk(&pCtx->es)
683	\|\| !hmVmxIsDataSelectorOk(&pCtx->fs)
684	\|\| !hmVmxIsDataSelectorOk(&pCtx->gs)
685	\|\| !hmVmxIsStackSelectorOk(&pCtx->ss))
686	{
687	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
688	return false;
689	}
690	}
691	else
692	{
693	/* The guest switched to V86 mode, check if the state is suitable for VT-x. */
694	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
695	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
696	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
697	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
698	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
699	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
700	{
701	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelBase);
702	return false;
703	}
704	if ( pCtx->cs.u32Limit != 0xffff
705	\|\| pCtx->ds.u32Limit != 0xffff
706	\|\| pCtx->es.u32Limit != 0xffff
707	\|\| pCtx->ss.u32Limit != 0xffff
708	\|\| pCtx->fs.u32Limit != 0xffff
709	\|\| pCtx->gs.u32Limit != 0xffff)
710	{
711	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelLimit);
712	return false;
713	}
714	if ( pCtx->cs.Attr.u != 0xf3
715	\|\| pCtx->ds.Attr.u != 0xf3
716	\|\| pCtx->es.Attr.u != 0xf3
717	\|\| pCtx->ss.Attr.u != 0xf3
718	\|\| pCtx->fs.Attr.u != 0xf3
719	\|\| pCtx->gs.Attr.u != 0xf3)
720	{
721	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelAttr);
722	return false;
723	}
724	}
725	}
726	}
727	}
728	else
729	{
730	if (!CPUMIsGuestInLongModeEx(pCtx))
731	{
732	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
733	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
734	return false;
735
736	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
737	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
738	return false;
739
740	/*
741	* The guest is about to complete the switch to protected mode. Wait a bit longer.
742	* Windows XP; switch to protected mode; all selectors are marked not present
743	* in the hidden registers (possible recompiler bug; see load_seg_vm).
744	*/
745	/** @todo Is this supposed recompiler bug still relevant with IEM? */
746	if (pCtx->cs.Attr.n.u1Present == 0)
747	return false;
748	if (pCtx->ss.Attr.n.u1Present == 0)
749	return false;
750
751	/*
752	* Windows XP: possible same as above, but new recompiler requires new
753	* heuristics? VT-x doesn't seem to like something about the guest state and
754	* this stuff avoids it.
755	*/
756	/** @todo This check is actually wrong, it doesn't take the direction of the
757	* stack segment into account. But, it does the job for now. */
758	if (pCtx->rsp >= pCtx->ss.u32Limit)
759	return false;
760	}
761	}
762	}
763
764	if (pVM->hm.s.vmx.fEnabled)
765	{
766	uint32_t uCr0Mask;
767
768	/* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
769	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
770
771	/* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
772	uCr0Mask &= ~X86_CR0_NE;
773
774	if (fSupportsRealMode)
775	{
776	/* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
777	uCr0Mask &= ~(X86_CR0_PG \| X86_CR0_PE);
778	}
779	else
780	{
781	/* We support protected mode without paging using identity mapping. */
782	uCr0Mask &= ~X86_CR0_PG;
783	}
784	if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
785	return false;
786
787	/* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
788	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
789	if ((pCtx->cr0 & uCr0Mask) != 0)
790	return false;
791
792	/* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
793	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
794	uCr0Mask &= ~X86_CR4_VMXE;
795	if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
796	return false;
797
798	/* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
799	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
800	if ((pCtx->cr4 & uCr0Mask) != 0)
801	return false;
802
803	pVCpu->hm.s.fActive = true;
804	return true;
805	}
806
807	return false;
808	}
809
810
811	/**
812	* Dumps the virtual VMCS state to the release log.
813	*
814	* @param pVCpu The cross context virtual CPU structure.
815	*/
816	VMM_INT_DECL(void) HMDumpHwvirtVmxState(PVMCPU pVCpu)
817	{
818	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
819	#define HMVMX_DUMP_HOST_XDTR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
820	do { \
821	LogRel((" %s%-4s = {base=%016RX64}\n", \
822	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u)); \
823	} while (0)
824	#define HMVMX_DUMP_HOST_FS_GS_TR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
825	do { \
826	LogRel((" %s%-4s = {%04x base=%016RX64}\n", \
827	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u)); \
828	} while (0)
829	#define HMVMX_DUMP_GUEST_SEGREG(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
830	do { \
831	LogRel((" %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
832	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
833	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr)); \
834	} while (0)
835	#define HMVMX_DUMP_GUEST_XDTR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
836	do { \
837	LogRel((" %s%-4s = {base=%016RX64 limit=%08x}\n", \
838	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit)); \
839	} while (0)
840
841	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
842	PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
843	if (!pVmcs)
844	{
845	LogRel(("Virtual VMCS not allocated\n"));
846	return;
847	}
848	LogRel(("GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon));
849	LogRel(("GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs));
850	LogRel(("GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs));
851	LogRel(("enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag)));
852	LogRel(("uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux));
853	LogRel(("enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort)));
854	LogRel(("uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux));
855	LogRel(("fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode));
856	LogRel(("fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode));
857	LogRel(("fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents));
858	LogRel(("fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret));
859	LogRel(("uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick));
860	LogRel(("uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick));
861	LogRel(("uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick));
862	LogRel(("offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite));
863	LogRel(("fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking));
864	LogRel(("VMCS cache:\n"));
865
866	const char *pszPrefix = " ";
867	/* Header. */
868	{
869	LogRel(("%sHeader:\n", pszPrefix));
870	LogRel((" %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId));
871	LogRel((" %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort)));
872	LogRel((" %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState)));
873	}
874
875	/* Control fields. */
876	{
877	/* 16-bit. */
878	LogRel(("%sControl:\n", pszPrefix));
879	LogRel((" %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid));
880	LogRel((" %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector));
881	LogRel((" %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex));
882
883	/* 32-bit. */
884	LogRel((" %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls));
885	LogRel((" %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls));
886	LogRel((" %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2));
887	LogRel((" %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls));
888	LogRel((" %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls));
889	LogRel((" %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap));
890	LogRel((" %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask));
891	LogRel((" %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch));
892	LogRel((" %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount));
893	LogRel((" %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount));
894	LogRel((" %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount));
895	LogRel((" %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount));
896	LogRel((" %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo));
897	{
898	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
899	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
900	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo)));
901	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType)));
902	LogRel((" %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo)));
903	LogRel((" %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo)));
904	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo)));
905	}
906	LogRel((" %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode));
907	LogRel((" %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen));
908	LogRel((" %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold));
909	LogRel((" %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap));
910	LogRel((" %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow));
911
912	/* 64-bit. */
913	LogRel((" %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u));
914	LogRel((" %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u));
915	LogRel((" %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u));
916	LogRel((" %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u));
917	LogRel((" %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u));
918	LogRel((" %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u));
919	LogRel((" %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u));
920	LogRel((" %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u));
921	LogRel((" %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u));
922	LogRel((" %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u));
923	LogRel((" %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u));
924	LogRel((" %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u));
925	LogRel((" %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u));
926	LogRel((" %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u));
927	LogRel((" %sEOI-exit bitmap 0 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u));
928	LogRel((" %sEOI-exit bitmap 1 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u));
929	LogRel((" %sEOI-exit bitmap 2 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u));
930	LogRel((" %sEOI-exit bitmap 3 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u));
931	LogRel((" %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u));
932	LogRel((" %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u));
933	LogRel((" %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u));
934	LogRel((" %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u));
935	LogRel((" %sXSS-bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssBitmap.u));
936	LogRel((" %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsBitmap.u));
937	LogRel((" %sSPPT pointer = %#RX64\n", pszPrefix, pVmcs->u64SpptPtr.u));
938	LogRel((" %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u));
939
940	/* Natural width. */
941	LogRel((" %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u));
942	LogRel((" %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u));
943	LogRel((" %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u));
944	LogRel((" %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u));
945	LogRel((" %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u));
946	LogRel((" %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u));
947	LogRel((" %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u));
948	LogRel((" %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u));
949	}
950
951	/* Guest state. */
952	{
953	LogRel(("%sGuest state:\n", pszPrefix));
954
955	/* 16-bit. */
956	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Cs, "cs", pszPrefix);
957	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ss, "ss", pszPrefix);
958	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Es, "es", pszPrefix);
959	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ds, "ds", pszPrefix);
960	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Fs, "fs", pszPrefix);
961	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Gs, "gs", pszPrefix);
962	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ldtr, "ldtr", pszPrefix);
963	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Tr, "tr", pszPrefix);
964	HMVMX_DUMP_GUEST_XDTR( pVmcs, Gdtr, "gdtr", pszPrefix);
965	HMVMX_DUMP_GUEST_XDTR( pVmcs, Idtr, "idtr", pszPrefix);
966	LogRel((" %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus));
967	LogRel((" %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex));
968
969	/* 32-bit. */
970	LogRel((" %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState));
971	LogRel((" %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState));
972	LogRel((" %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase));
973	LogRel((" %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS));
974	LogRel((" %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer));
975
976	/* 64-bit. */
977	LogRel((" %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u));
978	LogRel((" %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u));
979	LogRel((" %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u));
980	LogRel((" %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u));
981	LogRel((" %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u));
982	LogRel((" %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u));
983	LogRel((" %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u));
984	LogRel((" %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u));
985	LogRel((" %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u));
986	LogRel((" %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u));
987	LogRel((" %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u));
988
989	/* Natural width. */
990	LogRel((" %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u));
991	LogRel((" %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u));
992	LogRel((" %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u));
993	LogRel((" %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u));
994	LogRel((" %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u));
995	LogRel((" %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u));
996	LogRel((" %srflags = %#RX64\n", pszPrefix, pVmcs->u64GuestRFlags.u));
997	LogRel((" %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u));
998	LogRel((" %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u));
999	LogRel((" %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u));
1000	}
1001
1002	/* Host state. */
1003	{
1004	LogRel(("%sHost state:\n", pszPrefix));
1005
1006	/* 16-bit. */
1007	LogRel((" %scs = %#RX16\n", pszPrefix, pVmcs->HostCs));
1008	LogRel((" %sss = %#RX16\n", pszPrefix, pVmcs->HostSs));
1009	LogRel((" %sds = %#RX16\n", pszPrefix, pVmcs->HostDs));
1010	LogRel((" %ses = %#RX16\n", pszPrefix, pVmcs->HostEs));
1011	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Fs, "fs", pszPrefix);
1012	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Gs, "gs", pszPrefix);
1013	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Tr, "tr", pszPrefix);
1014	HMVMX_DUMP_HOST_XDTR(pVmcs, Gdtr, "gdtr", pszPrefix);
1015	HMVMX_DUMP_HOST_XDTR(pVmcs, Idtr, "idtr", pszPrefix);
1016
1017	/* 32-bit. */
1018	LogRel((" %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs));
1019
1020	/* 64-bit. */
1021	LogRel((" %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u));
1022	LogRel((" %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u));
1023	LogRel((" %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u));
1024
1025	/* Natural width. */
1026	LogRel((" %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u));
1027	LogRel((" %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u));
1028	LogRel((" %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u));
1029	LogRel((" %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u));
1030	LogRel((" %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u));
1031	LogRel((" %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u));
1032	LogRel((" %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u));
1033	}
1034
1035	/* Read-only fields. */
1036	{
1037	LogRel(("%sRead-only data fields:\n", pszPrefix));
1038
1039	/* 16-bit (none currently). */
1040
1041	/* 32-bit. */
1042	uint32_t const uExitReason = pVmcs->u32RoExitReason;
1043	LogRel((" %sExit reason = %u (%s)\n", pszPrefix, uExitReason, HMGetVmxExitName(uExitReason)));
1044	LogRel((" %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u));
1045	LogRel((" %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError));
1046	LogRel((" %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo));
1047	{
1048	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
1049	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
1050	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo)));
1051	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType)));
1052	LogRel((" %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo)));
1053	LogRel((" %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo)));
1054	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo)));
1055	}
1056	LogRel((" %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode));
1057	LogRel((" %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo));
1058	{
1059	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
1060	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
1061	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo)));
1062	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType)));
1063	LogRel((" %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo)));
1064	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo)));
1065	}
1066	LogRel((" %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode));
1067	LogRel((" %sVM-exit instruction length = %u bytes\n", pszPrefix, pVmcs->u32RoExitInstrLen));
1068	LogRel((" %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo));
1069
1070	/* 64-bit. */
1071	LogRel((" %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u));
1072
1073	/* Natural width. */
1074	LogRel((" %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u));
1075	LogRel((" %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u));
1076	LogRel((" %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u));
1077	LogRel((" %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u));
1078	LogRel((" %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u));
1079	}
1080
1081	#undef HMVMX_DUMP_HOST_XDTR
1082	#undef HMVMX_DUMP_HOST_FS_GS_TR
1083	#undef HMVMX_DUMP_GUEST_SEGREG
1084	#undef HMVMX_DUMP_GUEST_XDTR
1085	}
1086
1087
1088	/**
1089	* Gets the active (in use) VMCS info. object for the specified VCPU.
1090	*
1091	* This is either the guest or nested-guest VMCS info. and need not necessarily
1092	* pertain to the "current" VMCS (in the VMX definition of the term). For instance,
1093	* if the VM-entry failed due to an invalid-guest state, we may have "cleared" the
1094	* current VMCS while returning to ring-3. However, the VMCS info. object for that
1095	* VMCS would still be active and returned here so that we could dump the VMCS
1096	* fields to ring-3 for diagnostics. This function is thus only used to
1097	* distinguish between the nested-guest or guest VMCS.
1098	*
1099	* @returns The active VMCS information.
1100	* @param pVCpu The cross context virtual CPU structure.
1101	*
1102	* @thread EMT.
1103	* @remarks This function may be called with preemption or interrupts disabled!
1104	*/
1105	VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu)
1106	{
1107	if (!pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs)
1108	return &pVCpu->hm.s.vmx.VmcsInfo;
1109	return &pVCpu->hm.s.vmx.VmcsInfoNstGst;
1110	}
1111
1112
1113	/**
1114	* Converts a VMX event type into an appropriate TRPM event type.
1115	*
1116	* @returns TRPM event.
1117	* @param uIntInfo The VMX event.
1118	*/
1119	VMM_INT_DECL(TRPMEVENT) HMVmxEventTypeToTrpmEventType(uint32_t uIntInfo)
1120	{
1121	Assert(VMX_IDT_VECTORING_INFO_IS_VALID(uIntInfo));
1122
1123	TRPMEVENT enmTrapType;
1124	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(uIntInfo);
1125	uint8_t const uVector = VMX_IDT_VECTORING_INFO_VECTOR(uIntInfo);
1126
1127	switch (uType)
1128	{
1129	case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
1130	enmTrapType = TRPM_HARDWARE_INT;
1131	break;
1132
1133	case VMX_IDT_VECTORING_INFO_TYPE_NMI:
1134	case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
1135	enmTrapType = TRPM_TRAP;
1136	break;
1137
1138	case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT: /* INT1 (ICEBP). */
1139	Assert(uVector == X86_XCPT_DB); NOREF(uVector);
1140	enmTrapType = TRPM_SOFTWARE_INT;
1141	break;
1142
1143	case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* INT3 (#BP) and INTO (#OF) */
1144	Assert(uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF); NOREF(uVector);
1145	enmTrapType = TRPM_SOFTWARE_INT;
1146	break;
1147
1148	case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
1149	enmTrapType = TRPM_SOFTWARE_INT;
1150	break;
1151
1152	default:
1153	AssertMsgFailed(("Invalid trap type %#x\n", uType));
1154	enmTrapType = TRPM_32BIT_HACK;
1155	break;
1156	}
1157
1158	return enmTrapType;
1159	}
1160
1161
1162	/**
1163	* Converts a TRPM event type into an appropriate VMX event type.
1164	*
1165	* @returns VMX event type mask.
1166	* @param uVector The event vector.
1167	* @param enmTrpmEvent The TRPM event.
1168	* @param fIcebp Whether the \#DB vector is caused by an INT1/ICEBP
1169	* instruction.
1170	*/
1171	VMM_INT_DECL(uint32_t) HMTrpmEventTypeToVmxEventType(uint8_t uVector, TRPMEVENT enmTrpmEvent, bool fIcebp)
1172	{
1173	uint32_t uIntInfoType = 0;
1174	if (enmTrpmEvent == TRPM_TRAP)
1175	{
1176	Assert(!fIcebp);
1177	switch (uVector)
1178	{
1179	case X86_XCPT_NMI:
1180	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_NMI << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1181	break;
1182
1183	case X86_XCPT_BP:
1184	case X86_XCPT_OF:
1185	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1186	break;
1187
1188	case X86_XCPT_PF:
1189	case X86_XCPT_DF:
1190	case X86_XCPT_TS:
1191	case X86_XCPT_NP:
1192	case X86_XCPT_SS:
1193	case X86_XCPT_GP:
1194	case X86_XCPT_AC:
1195	uIntInfoType \|= VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID;
1196	RT_FALL_THRU();
1197	default:
1198	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1199	break;
1200	}
1201	}
1202	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
1203	{
1204	Assert(!fIcebp);
1205	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_EXT_INT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1206	}
1207	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
1208	{
1209	switch (uVector)
1210	{
1211	case X86_XCPT_BP:
1212	case X86_XCPT_OF:
1213	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1214	break;
1215
1216	case X86_XCPT_DB:
1217	{
1218	if (fIcebp)
1219	{
1220	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1221	break;
1222	}
1223	RT_FALL_THRU();
1224	}
1225	default:
1226	uIntInfoType \|= (VMX_IDT_VECTORING_INFO_TYPE_SW_INT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT);
1227	break;
1228	}
1229	}
1230	else
1231	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
1232	return uIntInfoType;
1233	}
1234
1235
1236	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1237	/**
1238	* Notification callback for when a VM-exit happens outside VMX R0 code (e.g. in
1239	* IEM).
1240	*
1241	* @param pVCpu The cross context virtual CPU structure.
1242	*
1243	* @remarks Can be called from ring-0 as well as ring-3.
1244	*/
1245	VMM_INT_DECL(void) HMNotifyVmxNstGstVmexit(PVMCPU pVCpu)
1246	{
1247	LogFlowFunc(("\n"));
1248
1249	/*
1250	* Transitions to ring-3 flag a full CPU-state change except if we transition to ring-3
1251	* in response to a physical CPU interrupt as no changes to the guest-CPU state are
1252	* expected (see VINF_EM_RAW_INTERRUPT handling in hmR0VmxExitToRing3).
1253	*
1254	* However, with nested-guests, the state -can- change on trips to ring-3 for we might
1255	* try to inject a nested-guest physical interrupt and cause a VMX_EXIT_EXT_INT VM-exit
1256	* for the nested-guest from ring-3.
1257	*
1258	* Signalling reload of just the guest-CPU state that changed with the VM-exit is -not-
1259	* sufficient since HM also needs to reload state related to VM-entry/VM-exit controls
1260	* etc. So signal reloading of the entire state. It does not seem worth making this any
1261	* more fine grained at the moment.
1262	*/
1263	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ALL);
1264	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
1265
1266	/*
1267	* Make sure we need to merge the guest VMCS controls with the nested-guest
1268	* VMCS controls on the next nested-guest VM-entry.
1269	*/
1270	pVCpu->hm.s.vmx.fMergedNstGstCtls = false;
1271
1272	/*
1273	* Flush the TLB before entering the outer guest execution (mainly required since the
1274	* APIC-access guest-physical address would have changed and probably more things in
1275	* the future).
1276	*/
1277	pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb = true;
1278
1279	/** @todo Handle releasing of the page-mapping lock later. */
1280	#if 0
1281	if (pVCpu->hm.s.vmx.fVirtApicPageLocked)
1282	{
1283	PGMPhysReleasePageMappingLock(pVCpu->CTX_SUFF(pVM), &pVCpu->hm.s.vmx.PgMapLockVirtApic);
1284	pVCpu->hm.s.vmx.fVirtApicPageLocked = false;
1285	}
1286	#endif
1287	}
1288
1289
1290	/**
1291	* Notification callback for when the nested hypervisor's current VMCS is loaded or
1292	* changed outside VMX R0 code (e.g. in IEM).
1293	*
1294	* This need -not- be called for modifications to the nested hypervisor's current
1295	* VMCS when the guest is in VMX non-root mode as VMCS shadowing is not applicable
1296	* there.
1297	*
1298	* @param pVCpu The cross context virtual CPU structure.
1299	*
1300	* @remarks Can be called from ring-0 as well as ring-3.
1301	*/
1302	VMM_INT_DECL(void) HMNotifyVmxNstGstCurrentVmcsChanged(PVMCPU pVCpu)
1303	{
1304	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1305	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, CPUMCTX_EXTRN_HWVIRT);
1306
1307	/*
1308	* Make sure we need to copy the nested hypervisor's current VMCS into the shadow VMCS
1309	* on the next guest VM-entry.
1310	*/
1311	pVCpu->hm.s.vmx.fCopiedNstGstToShadowVmcs = false;
1312	}
1313
1314	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
1315

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp@ 84247

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