1 | /* $Id: HMSVMAll.cpp 97492 2022-11-10 10:56:17Z vboxsync $ */
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2 | /** @file
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3 | * HM SVM (AMD-V) - All contexts.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2017-2022 Oracle and/or its affiliates.
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8 | *
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9 | * This file is part of VirtualBox base platform packages, as
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10 | * available from https://www.virtualbox.org.
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11 | *
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12 | * This program is free software; you can redistribute it and/or
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13 | * modify it under the terms of the GNU General Public License
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14 | * as published by the Free Software Foundation, in version 3 of the
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15 | * License.
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16 | *
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17 | * This program is distributed in the hope that it will be useful, but
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18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | * General Public License for more details.
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21 | *
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22 | * You should have received a copy of the GNU General Public License
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23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | *
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25 | * SPDX-License-Identifier: GPL-3.0-only
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26 | */
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27 |
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28 |
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29 | /*********************************************************************************************************************************
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30 | * Header Files *
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31 | *********************************************************************************************************************************/
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32 | #define LOG_GROUP LOG_GROUP_HM
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33 | #define VMCPU_INCL_CPUM_GST_CTX
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34 | #include "HMInternal.h"
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35 | #include <VBox/vmm/apic.h>
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36 | #include <VBox/vmm/gim.h>
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37 | #include <VBox/vmm/iem.h>
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38 | #include <VBox/vmm/vmcc.h>
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39 |
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40 | #include <VBox/err.h>
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41 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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42 | # include <iprt/asm-amd64-x86.h> /* ASMCpuId */
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43 | #endif
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44 |
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45 |
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46 |
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47 | /**
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48 | * Emulates a simple MOV TPR (CR8) instruction.
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49 | *
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50 | * Used for TPR patching on 32-bit guests. This simply looks up the patch record
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51 | * at EIP and does the required.
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52 | *
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53 | * This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
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54 | * like how we want it to be (e.g. not followed by shr 4 as is usually done for
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55 | * TPR). See hmR3ReplaceTprInstr() for the details.
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56 | *
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57 | * @returns VBox status code.
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58 | * @retval VINF_SUCCESS if the access was handled successfully, RIP + RFLAGS updated.
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59 | * @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
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60 | * @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
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61 | *
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62 | * @param pVM The cross context VM structure.
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63 | * @param pVCpu The cross context virtual CPU structure.
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64 | */
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65 | VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu)
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66 | {
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67 | PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
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68 | Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
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69 |
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70 | AssertCompile(DISGREG_EAX == X86_GREG_xAX);
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71 | AssertCompile(DISGREG_ECX == X86_GREG_xCX);
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72 | AssertCompile(DISGREG_EDX == X86_GREG_xDX);
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73 | AssertCompile(DISGREG_EBX == X86_GREG_xBX);
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74 | AssertCompile(DISGREG_ESP == X86_GREG_xSP);
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75 | AssertCompile(DISGREG_EBP == X86_GREG_xBP);
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76 | AssertCompile(DISGREG_ESI == X86_GREG_xSI);
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77 | AssertCompile(DISGREG_EDI == X86_GREG_xDI);
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78 | AssertCompile(DISGREG_R8D == X86_GREG_x8);
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79 | AssertCompile(DISGREG_R9D == X86_GREG_x9);
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80 | AssertCompile(DISGREG_R10D == X86_GREG_x10);
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81 | AssertCompile(DISGREG_R11D == X86_GREG_x11);
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82 | AssertCompile(DISGREG_R12D == X86_GREG_x12);
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83 | AssertCompile(DISGREG_R13D == X86_GREG_x13);
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84 | AssertCompile(DISGREG_R14D == X86_GREG_x14);
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85 | AssertCompile(DISGREG_R15D == X86_GREG_x15);
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86 |
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87 | /*
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88 | * We do this in a loop as we increment the RIP after a successful emulation
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89 | * and the new RIP may be a patched instruction which needs emulation as well.
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90 | */
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91 | bool fPatchFound = false;
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92 | for (;;)
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93 | {
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94 | PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
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95 | if (!pPatch)
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96 | break;
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97 | fPatchFound = true;
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98 |
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99 | uint8_t u8Tpr;
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100 | switch (pPatch->enmType)
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101 | {
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102 | case HMTPRINSTR_READ:
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103 | {
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104 | bool fPending;
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105 | int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
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106 | AssertRC(rc);
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107 |
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108 | uint8_t idxReg = pPatch->uDstOperand;
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109 | AssertStmt(idxReg < RT_ELEMENTS(pCtx->aGRegs), idxReg = RT_ELEMENTS(pCtx->aGRegs) - 1);
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110 | pCtx->aGRegs[idxReg].u64 = u8Tpr;
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111 | pCtx->rip += pPatch->cbOp;
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112 | pCtx->eflags.Bits.u1RF = 0;
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113 | break;
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114 | }
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115 |
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116 | case HMTPRINSTR_WRITE_REG:
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117 | case HMTPRINSTR_WRITE_IMM:
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118 | {
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119 | if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
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120 | {
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121 | uint8_t idxReg = pPatch->uSrcOperand;
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122 | AssertStmt(idxReg < RT_ELEMENTS(pCtx->aGRegs), idxReg = RT_ELEMENTS(pCtx->aGRegs) - 1);
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123 | u8Tpr = pCtx->aGRegs[idxReg].u8;
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124 | }
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125 | else
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126 | u8Tpr = (uint8_t)pPatch->uSrcOperand;
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127 |
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128 | int rc2 = APICSetTpr(pVCpu, u8Tpr);
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129 | AssertRC(rc2);
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130 | pCtx->rip += pPatch->cbOp;
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131 | pCtx->eflags.Bits.u1RF = 0;
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132 | ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR
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133 | | HM_CHANGED_GUEST_RIP
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134 | | HM_CHANGED_GUEST_RFLAGS);
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135 | break;
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136 | }
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137 |
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138 | default:
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139 | {
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140 | AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
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141 | pVCpu->hm.s.u32HMError = pPatch->enmType;
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142 | return VERR_SVM_UNEXPECTED_PATCH_TYPE;
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143 | }
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144 | }
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145 | }
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146 |
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147 | return fPatchFound ? VINF_SUCCESS : VERR_NOT_FOUND;
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148 | }
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149 |
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150 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
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151 | /**
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152 | * Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
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153 | * in IEM).
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154 | *
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155 | * @param pVCpu The cross context virtual CPU structure.
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156 | * @param pCtx Pointer to the guest-CPU context.
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157 | *
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158 | * @sa hmR0SvmVmRunCacheVmcb.
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159 | */
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160 | VMM_INT_DECL(void) HMNotifySvmNstGstVmexit(PVMCPUCC pVCpu, PCPUMCTX pCtx)
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161 | {
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162 | PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
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163 | if (pVmcbNstGstCache->fCacheValid)
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164 | {
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165 | /*
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166 | * Restore fields as our own code might look at the VMCB controls as part
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167 | * of the #VMEXIT handling in IEM. Otherwise, strictly speaking we don't need to
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168 | * restore these fields because currently none of them are written back to memory
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169 | * by a physical CPU on #VMEXIT.
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170 | */
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171 | PSVMVMCBCTRL pVmcbNstGstCtrl = &pCtx->hwvirt.svm.Vmcb.ctrl;
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172 | pVmcbNstGstCtrl->u16InterceptRdCRx = pVmcbNstGstCache->u16InterceptRdCRx;
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173 | pVmcbNstGstCtrl->u16InterceptWrCRx = pVmcbNstGstCache->u16InterceptWrCRx;
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174 | pVmcbNstGstCtrl->u16InterceptRdDRx = pVmcbNstGstCache->u16InterceptRdDRx;
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175 | pVmcbNstGstCtrl->u16InterceptWrDRx = pVmcbNstGstCache->u16InterceptWrDRx;
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176 | pVmcbNstGstCtrl->u16PauseFilterThreshold = pVmcbNstGstCache->u16PauseFilterThreshold;
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177 | pVmcbNstGstCtrl->u16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
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178 | pVmcbNstGstCtrl->u32InterceptXcpt = pVmcbNstGstCache->u32InterceptXcpt;
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179 | pVmcbNstGstCtrl->u64InterceptCtrl = pVmcbNstGstCache->u64InterceptCtrl;
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180 | pVmcbNstGstCtrl->u64TSCOffset = pVmcbNstGstCache->u64TSCOffset;
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181 | pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pVmcbNstGstCache->fVIntrMasking;
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182 | pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVmcbNstGstCache->fNestedPaging;
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183 | pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcbNstGstCache->fLbrVirt;
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184 | pVmcbNstGstCache->fCacheValid = false;
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185 | }
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186 |
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187 | /*
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188 | * Transitions to ring-3 flag a full CPU-state change except if we transition to ring-3
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189 | * in response to a physical CPU interrupt as no changes to the guest-CPU state are
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190 | * expected (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
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191 | *
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192 | * However, with nested-guests, the state -can- change on trips to ring-3 for we might
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193 | * try to inject a nested-guest physical interrupt and cause a SVM_EXIT_INTR #VMEXIT for
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194 | * the nested-guest from ring-3. Import the complete state here as we will be swapping
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195 | * to the guest VMCB after the #VMEXIT.
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196 | */
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197 | CPUMImportGuestStateOnDemand(pVCpu, CPUMCTX_EXTRN_ALL);
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198 | CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ALL);
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199 | ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
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200 | }
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201 | #endif
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202 |
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203 | /**
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204 | * Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
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205 | * enabled for the VM.
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206 | *
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207 | * @returns @c true if VGIF is enabled, @c false otherwise.
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208 | * @param pVM The cross context VM structure.
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209 | *
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210 | * @remarks This value returned by this functions is expected by the callers not
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211 | * to change throughout the lifetime of the VM.
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212 | */
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213 | VMM_INT_DECL(bool) HMIsSvmVGifActive(PCVMCC pVM)
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214 | {
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215 | #ifdef IN_RING0
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216 | bool const fVGif = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
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217 | #else
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218 | bool const fVGif = RT_BOOL(pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
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219 | #endif
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220 | return fVGif && pVM->hm.s.svm.fVGif;
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221 | }
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222 |
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223 |
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224 | /**
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225 | * Interface used by IEM to handle patched TPR accesses.
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226 | *
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227 | * @returns VBox status code
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228 | * @retval VINF_SUCCESS if hypercall was handled, RIP + RFLAGS all dealt with.
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229 | * @retval VERR_NOT_FOUND if hypercall was _not_ handled.
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230 | * @retval VERR_SVM_UNEXPECTED_PATCH_TYPE on IPE.
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231 | *
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232 | * @param pVM The cross context VM structure.
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233 | * @param pVCpu The cross context virtual CPU structure.
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234 | */
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235 | VMM_INT_DECL(int) HMHCMaybeMovTprSvmHypercall(PVMCC pVM, PVMCPUCC pVCpu)
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236 | {
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237 | if (pVM->hm.s.fTprPatchingAllowed)
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238 | {
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239 | int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
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240 | if (RT_SUCCESS(rc))
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241 | return VINF_SUCCESS;
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242 | return rc;
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243 | }
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244 | return VERR_NOT_FOUND;
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245 | }
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246 |
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247 |
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248 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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249 | /**
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250 | * Checks if the current AMD CPU is subject to erratum 170 "In SVM mode,
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251 | * incorrect code bytes may be fetched after a world-switch".
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252 | *
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253 | * @param pu32Family Where to store the CPU family (can be NULL).
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254 | * @param pu32Model Where to store the CPU model (can be NULL).
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255 | * @param pu32Stepping Where to store the CPU stepping (can be NULL).
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256 | * @returns true if the erratum applies, false otherwise.
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257 | */
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258 | VMM_INT_DECL(int) HMIsSubjectToSvmErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping)
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259 | {
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260 | /*
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261 | * Erratum 170 which requires a forced TLB flush for each world switch:
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262 | * See AMD spec. "Revision Guide for AMD NPT Family 0Fh Processors".
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263 | *
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264 | * All BH-G1/2 and DH-G1/2 models include a fix:
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265 | * Athlon X2: 0x6b 1/2
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266 | * 0x68 1/2
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267 | * Athlon 64: 0x7f 1
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268 | * 0x6f 2
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269 | * Sempron: 0x7f 1/2
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270 | * 0x6f 2
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271 | * 0x6c 2
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272 | * 0x7c 2
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273 | * Turion 64: 0x68 2
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274 | */
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275 | uint32_t u32Dummy;
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276 | uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
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277 | ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
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278 | u32BaseFamily = (u32Version >> 8) & 0xf;
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279 | u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
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280 | u32Model = ((u32Version >> 4) & 0xf);
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281 | u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
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282 | u32Stepping = u32Version & 0xf;
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283 |
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284 | bool fErratumApplies = false;
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285 | if ( u32Family == 0xf
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286 | && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
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287 | && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
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288 | fErratumApplies = true;
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289 |
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290 | if (pu32Family)
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291 | *pu32Family = u32Family;
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292 | if (pu32Model)
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293 | *pu32Model = u32Model;
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294 | if (pu32Stepping)
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295 | *pu32Stepping = u32Stepping;
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296 |
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297 | return fErratumApplies;
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298 | }
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299 | #endif
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300 |
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301 |
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302 | /**
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303 | * Converts an SVM event type to a TRPM event type.
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304 | *
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305 | * @returns The TRPM event type.
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306 | * @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
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307 | * of recognized trap types.
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308 | *
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309 | * @param pEvent Pointer to the SVM event.
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310 | * @param uVector The vector associated with the event.
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311 | */
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312 | VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent, uint8_t uVector)
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313 | {
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314 | uint8_t const uType = pEvent->n.u3Type;
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315 | switch (uType)
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316 | {
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317 | case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
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318 | case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
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319 | case SVM_EVENT_NMI: return TRPM_TRAP;
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320 | case SVM_EVENT_EXCEPTION:
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321 | {
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322 | if ( uVector == X86_XCPT_BP
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323 | || uVector == X86_XCPT_OF)
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324 | return TRPM_SOFTWARE_INT;
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325 | return TRPM_TRAP;
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326 | }
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327 | default:
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328 | break;
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329 | }
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330 | AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
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331 | return TRPM_32BIT_HACK;
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332 | }
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333 |
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334 |
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335 | /**
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336 | * Gets the SVM nested-guest control intercepts if cached by HM.
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337 | *
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338 | * @returns @c true on success, @c false otherwise.
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339 | * @param pVCpu The cross context virtual CPU structure of the calling
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340 | * EMT.
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341 | * @param pu64Intercepts Where to store the control intercepts. Only updated when
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342 | * @c true is returned.
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343 | */
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344 | VMM_INT_DECL(bool) HMGetGuestSvmCtrlIntercepts(PCVMCPU pVCpu, uint64_t *pu64Intercepts)
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345 | {
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346 | Assert(pu64Intercepts);
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347 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
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348 | if (pVmcbNstGstCache->fCacheValid)
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349 | {
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350 | *pu64Intercepts = pVmcbNstGstCache->u64InterceptCtrl;
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351 | return true;
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352 | }
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353 | return false;
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354 | }
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355 |
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356 |
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357 | /**
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358 | * Gets the SVM nested-guest CRx-read intercepts if cached by HM.
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359 | *
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360 | * @returns @c true on success, @c false otherwise.
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361 | * @param pVCpu The cross context virtual CPU structure of the calling
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362 | * EMT.
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363 | * @param pu16Intercepts Where to store the CRx-read intercepts. Only updated
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364 | * when @c true is returned.
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365 | */
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366 | VMM_INT_DECL(bool) HMGetGuestSvmReadCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
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367 | {
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368 | Assert(pu16Intercepts);
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369 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
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370 | if (pVmcbNstGstCache->fCacheValid)
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371 | {
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372 | *pu16Intercepts = pVmcbNstGstCache->u16InterceptRdCRx;
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373 | return true;
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374 | }
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375 | return false;
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376 | }
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377 |
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378 |
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379 | /**
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380 | * Gets the SVM nested-guest CRx-write intercepts if cached by HM.
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381 | *
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382 | * @returns @c true on success, @c false otherwise.
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383 | * @param pVCpu The cross context virtual CPU structure of the calling
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384 | * EMT.
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385 | * @param pu16Intercepts Where to store the CRx-write intercepts. Only updated
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386 | * when @c true is returned.
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387 | */
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388 | VMM_INT_DECL(bool) HMGetGuestSvmWriteCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
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389 | {
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390 | Assert(pu16Intercepts);
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391 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
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392 | if (pVmcbNstGstCache->fCacheValid)
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393 | {
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394 | *pu16Intercepts = pVmcbNstGstCache->u16InterceptWrCRx;
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395 | return true;
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396 | }
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397 | return false;
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398 | }
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399 |
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400 |
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401 | /**
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402 | * Gets the SVM nested-guest DRx-read intercepts if cached by HM.
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403 | *
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404 | * @returns @c true on success, @c false otherwise.
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405 | * @param pVCpu The cross context virtual CPU structure of the calling
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406 | * EMT.
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407 | * @param pu16Intercepts Where to store the DRx-read intercepts. Only updated
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408 | * when @c true is returned.
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409 | */
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410 | VMM_INT_DECL(bool) HMGetGuestSvmReadDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
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411 | {
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412 | Assert(pu16Intercepts);
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413 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
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414 | if (pVmcbNstGstCache->fCacheValid)
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415 | {
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416 | *pu16Intercepts = pVmcbNstGstCache->u16InterceptRdDRx;
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417 | return true;
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418 | }
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419 | return false;
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420 | }
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421 |
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422 |
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423 | /**
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424 | * Gets the SVM nested-guest DRx-write intercepts if cached by HM.
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425 | *
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426 | * @returns @c true on success, @c false otherwise.
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427 | * @param pVCpu The cross context virtual CPU structure of the calling
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428 | * EMT.
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429 | * @param pu16Intercepts Where to store the DRx-write intercepts. Only updated
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430 | * when @c true is returned.
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431 | */
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432 | VMM_INT_DECL(bool) HMGetGuestSvmWriteDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
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433 | {
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434 | Assert(pu16Intercepts);
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435 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
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436 | if (pVmcbNstGstCache->fCacheValid)
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437 | {
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438 | *pu16Intercepts = pVmcbNstGstCache->u16InterceptWrDRx;
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439 | return true;
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440 | }
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441 | return false;
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442 | }
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443 |
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444 |
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445 | /**
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446 | * Gets the SVM nested-guest exception intercepts if cached by HM.
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447 | *
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448 | * @returns @c true on success, @c false otherwise.
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449 | * @param pVCpu The cross context virtual CPU structure of the calling
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450 | * EMT.
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451 | * @param pu32Intercepts Where to store the exception intercepts. Only updated
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452 | * when @c true is returned.
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453 | */
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454 | VMM_INT_DECL(bool) HMGetGuestSvmXcptIntercepts(PCVMCPU pVCpu, uint32_t *pu32Intercepts)
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455 | {
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456 | Assert(pu32Intercepts);
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457 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
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458 | if (pVmcbNstGstCache->fCacheValid)
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459 | {
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460 | *pu32Intercepts = pVmcbNstGstCache->u32InterceptXcpt;
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461 | return true;
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462 | }
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463 | return false;
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464 | }
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465 |
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466 |
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467 | /**
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468 | * Checks if the nested-guest VMCB has virtual-interrupts masking enabled.
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469 | *
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470 | * @returns @c true on success, @c false otherwise.
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471 | * @param pVCpu The cross context virtual CPU structure of the calling
|
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472 | * EMT.
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473 | * @param pfVIntrMasking Where to store the virtual-interrupt masking bit.
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474 | * Updated only when @c true is returned.
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475 | */
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476 | VMM_INT_DECL(bool) HMGetGuestSvmVirtIntrMasking(PCVMCPU pVCpu, bool *pfVIntrMasking)
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477 | {
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478 | Assert(pfVIntrMasking);
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479 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
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480 | if (pVmcbNstGstCache->fCacheValid)
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481 | {
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482 | *pfVIntrMasking = pVmcbNstGstCache->fVIntrMasking;
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483 | return true;
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---|
484 | }
|
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485 | return false;
|
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486 | }
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487 |
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488 |
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489 | /**
|
---|
490 | * Gets the SVM nested-guest nested-paging bit if cached by HM.
|
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491 | *
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492 | * @returns @c true on success, @c false otherwise.
|
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493 | * @param pVCpu The cross context virtual CPU structure of the
|
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494 | * calling EMT.
|
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495 | * @param pfNestedPaging Where to store the nested-paging bit. Updated only
|
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496 | * when @c true is returned.
|
---|
497 | */
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498 | VMM_INT_DECL(bool) HMGetGuestSvmNestedPaging(PCVMCPU pVCpu, bool *pfNestedPaging)
|
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499 | {
|
---|
500 | Assert(pfNestedPaging);
|
---|
501 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
|
---|
502 | if (pVmcbNstGstCache->fCacheValid)
|
---|
503 | {
|
---|
504 | *pfNestedPaging = pVmcbNstGstCache->fNestedPaging;
|
---|
505 | return true;
|
---|
506 | }
|
---|
507 | return false;
|
---|
508 | }
|
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509 |
|
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510 |
|
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511 | /**
|
---|
512 | * Returns the nested-guest VMCB pause-filter count.
|
---|
513 | *
|
---|
514 | * @returns @c true on success, @c false otherwise.
|
---|
515 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
516 | * calling EMT.
|
---|
517 | * @param pu16PauseFilterCount Where to store the pause-filter count. Only
|
---|
518 | * updated @c true is returned.
|
---|
519 | */
|
---|
520 | VMM_INT_DECL(bool) HMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, uint16_t *pu16PauseFilterCount)
|
---|
521 | {
|
---|
522 | Assert(pu16PauseFilterCount);
|
---|
523 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
|
---|
524 | if (pVmcbNstGstCache->fCacheValid)
|
---|
525 | {
|
---|
526 | *pu16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
|
---|
527 | return true;
|
---|
528 | }
|
---|
529 | return false;
|
---|
530 | }
|
---|
531 |
|
---|
532 |
|
---|
533 | /**
|
---|
534 | * Returns the SVM nested-guest TSC offset if cached by HM.
|
---|
535 | *
|
---|
536 | * @returns The TSC offset after applying any nested-guest TSC offset.
|
---|
537 | * @param pVCpu The cross context virtual CPU structure of the calling
|
---|
538 | * EMT.
|
---|
539 | * @param pu64TscOffset Where to store the TSC offset. Only updated when @c
|
---|
540 | * true is returned.
|
---|
541 | */
|
---|
542 | VMM_INT_DECL(bool) HMGetGuestSvmTscOffset(PCVMCPU pVCpu, uint64_t *pu64TscOffset)
|
---|
543 | {
|
---|
544 | Assert(pu64TscOffset);
|
---|
545 | PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
|
---|
546 | if (pVmcbNstGstCache->fCacheValid)
|
---|
547 | {
|
---|
548 | *pu64TscOffset = pVmcbNstGstCache->u64TSCOffset;
|
---|
549 | return true;
|
---|
550 | }
|
---|
551 | return false;
|
---|
552 | }
|
---|
553 |
|
---|