HMSVMAll.cpp@ 97405

Last change on this file since 97405 was 97209, checked in by vboxsync, 2 years ago
VMM/HMSVMAll: Replace DISFetchReg32 and DISWriteReg32 with direct register accesses, because the two functions use CPUMCTXCORE and will soon be removed.
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1	/* $Id: HMSVMAll.cpp 97209 2022-10-18 14:37:10Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_HM
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include "HMInternal.h"
35	#include <VBox/vmm/apic.h>
36	#include <VBox/vmm/gim.h>
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/vmcc.h>
39
40	#include <VBox/err.h>
41	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
42	# include <iprt/asm-amd64-x86.h> /* ASMCpuId */
43	#endif
44
45
46
47	/**
48	* Emulates a simple MOV TPR (CR8) instruction.
49	*
50	* Used for TPR patching on 32-bit guests. This simply looks up the patch record
51	* at EIP and does the required.
52	*
53	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
54	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
55	* TPR). See hmR3ReplaceTprInstr() for the details.
56	*
57	* @returns VBox status code.
58	* @retval VINF_SUCCESS if the access was handled successfully, RIP + RFLAGS updated.
59	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
60	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
61	*
62	* @param pVM The cross context VM structure.
63	* @param pVCpu The cross context virtual CPU structure.
64	*/
65	VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu)
66	{
67	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
68	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
69
70	AssertCompile(DISGREG_EAX == X86_GREG_xAX);
71	AssertCompile(DISGREG_ECX == X86_GREG_xCX);
72	AssertCompile(DISGREG_EDX == X86_GREG_xDX);
73	AssertCompile(DISGREG_EBX == X86_GREG_xBX);
74	AssertCompile(DISGREG_ESP == X86_GREG_xSP);
75	AssertCompile(DISGREG_EBP == X86_GREG_xBP);
76	AssertCompile(DISGREG_ESI == X86_GREG_xSI);
77	AssertCompile(DISGREG_EDI == X86_GREG_xDI);
78	AssertCompile(DISGREG_R8D == X86_GREG_x8);
79	AssertCompile(DISGREG_R9D == X86_GREG_x9);
80	AssertCompile(DISGREG_R10D == X86_GREG_x10);
81	AssertCompile(DISGREG_R11D == X86_GREG_x11);
82	AssertCompile(DISGREG_R12D == X86_GREG_x12);
83	AssertCompile(DISGREG_R13D == X86_GREG_x13);
84	AssertCompile(DISGREG_R14D == X86_GREG_x14);
85	AssertCompile(DISGREG_R15D == X86_GREG_x15);
86
87	/*
88	* We do this in a loop as we increment the RIP after a successful emulation
89	* and the new RIP may be a patched instruction which needs emulation as well.
90	*/
91	bool fPatchFound = false;
92	for (;;)
93	{
94	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
95	if (!pPatch)
96	break;
97	fPatchFound = true;
98
99	uint8_t u8Tpr;
100	switch (pPatch->enmType)
101	{
102	case HMTPRINSTR_READ:
103	{
104	bool fPending;
105	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
106	AssertRC(rc);
107
108	uint8_t idxReg = pPatch->uDstOperand;
109	AssertStmt(idxReg < RT_ELEMENTS(pCtx->aGRegs), idxReg = RT_ELEMENTS(pCtx->aGRegs) - 1);
110	pCtx->aGRegs[idxReg].u64 = u8Tpr;
111	pCtx->rip += pPatch->cbOp;
112	pCtx->eflags.Bits.u1RF = 0;
113	break;
114	}
115
116	case HMTPRINSTR_WRITE_REG:
117	case HMTPRINSTR_WRITE_IMM:
118	{
119	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
120	{
121	uint8_t idxReg = pPatch->uDstOperand;
122	AssertStmt(idxReg < RT_ELEMENTS(pCtx->aGRegs), idxReg = RT_ELEMENTS(pCtx->aGRegs) - 1);
123	u8Tpr = pCtx->aGRegs[idxReg].u8;
124	}
125	else
126	u8Tpr = (uint8_t)pPatch->uSrcOperand;
127
128	int rc2 = APICSetTpr(pVCpu, u8Tpr);
129	AssertRC(rc2);
130	pCtx->rip += pPatch->cbOp;
131	pCtx->eflags.Bits.u1RF = 0;
132	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR
133	\| HM_CHANGED_GUEST_RIP
134	\| HM_CHANGED_GUEST_RFLAGS);
135	break;
136	}
137
138	default:
139	{
140	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
141	pVCpu->hm.s.u32HMError = pPatch->enmType;
142	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
143	}
144	}
145	}
146
147	return fPatchFound ? VINF_SUCCESS : VERR_NOT_FOUND;
148	}
149
150	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
151	/**
152	* Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
153	* in IEM).
154	*
155	* @param pVCpu The cross context virtual CPU structure.
156	* @param pCtx Pointer to the guest-CPU context.
157	*
158	* @sa hmR0SvmVmRunCacheVmcb.
159	*/
160	VMM_INT_DECL(void) HMNotifySvmNstGstVmexit(PVMCPUCC pVCpu, PCPUMCTX pCtx)
161	{
162	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
163	if (pVmcbNstGstCache->fCacheValid)
164	{
165	/*
166	* Restore fields as our own code might look at the VMCB controls as part
167	* of the #VMEXIT handling in IEM. Otherwise, strictly speaking we don't need to
168	* restore these fields because currently none of them are written back to memory
169	* by a physical CPU on #VMEXIT.
170	*/
171	PSVMVMCBCTRL pVmcbNstGstCtrl = &pCtx->hwvirt.svm.Vmcb.ctrl;
172	pVmcbNstGstCtrl->u16InterceptRdCRx = pVmcbNstGstCache->u16InterceptRdCRx;
173	pVmcbNstGstCtrl->u16InterceptWrCRx = pVmcbNstGstCache->u16InterceptWrCRx;
174	pVmcbNstGstCtrl->u16InterceptRdDRx = pVmcbNstGstCache->u16InterceptRdDRx;
175	pVmcbNstGstCtrl->u16InterceptWrDRx = pVmcbNstGstCache->u16InterceptWrDRx;
176	pVmcbNstGstCtrl->u16PauseFilterThreshold = pVmcbNstGstCache->u16PauseFilterThreshold;
177	pVmcbNstGstCtrl->u16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
178	pVmcbNstGstCtrl->u32InterceptXcpt = pVmcbNstGstCache->u32InterceptXcpt;
179	pVmcbNstGstCtrl->u64InterceptCtrl = pVmcbNstGstCache->u64InterceptCtrl;
180	pVmcbNstGstCtrl->u64TSCOffset = pVmcbNstGstCache->u64TSCOffset;
181	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pVmcbNstGstCache->fVIntrMasking;
182	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVmcbNstGstCache->fNestedPaging;
183	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcbNstGstCache->fLbrVirt;
184	pVmcbNstGstCache->fCacheValid = false;
185	}
186
187	/*
188	* Transitions to ring-3 flag a full CPU-state change except if we transition to ring-3
189	* in response to a physical CPU interrupt as no changes to the guest-CPU state are
190	* expected (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
191	*
192	* However, with nested-guests, the state -can- change on trips to ring-3 for we might
193	* try to inject a nested-guest physical interrupt and cause a SVM_EXIT_INTR #VMEXIT for
194	* the nested-guest from ring-3. Import the complete state here as we will be swapping
195	* to the guest VMCB after the #VMEXIT.
196	*/
197	CPUMImportGuestStateOnDemand(pVCpu, CPUMCTX_EXTRN_ALL);
198	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ALL);
199	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
200	}
201	#endif
202
203	/**
204	* Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
205	* enabled for the VM.
206	*
207	* @returns @c true if VGIF is enabled, @c false otherwise.
208	* @param pVM The cross context VM structure.
209	*
210	* @remarks This value returned by this functions is expected by the callers not
211	* to change throughout the lifetime of the VM.
212	*/
213	VMM_INT_DECL(bool) HMIsSvmVGifActive(PCVMCC pVM)
214	{
215	#ifdef IN_RING0
216	bool const fVGif = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
217	#else
218	bool const fVGif = RT_BOOL(pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
219	#endif
220	return fVGif && pVM->hm.s.svm.fVGif;
221	}
222
223
224	/**
225	* Interface used by IEM to handle patched TPR accesses.
226	*
227	* @returns VBox status code
228	* @retval VINF_SUCCESS if hypercall was handled, RIP + RFLAGS all dealt with.
229	* @retval VERR_NOT_FOUND if hypercall was _not_ handled.
230	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE on IPE.
231	*
232	* @param pVM The cross context VM structure.
233	* @param pVCpu The cross context virtual CPU structure.
234	*/
235	VMM_INT_DECL(int) HMHCMaybeMovTprSvmHypercall(PVMCC pVM, PVMCPUCC pVCpu)
236	{
237	if (pVM->hm.s.fTprPatchingAllowed)
238	{
239	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
240	if (RT_SUCCESS(rc))
241	return VINF_SUCCESS;
242	return rc;
243	}
244	return VERR_NOT_FOUND;
245	}
246
247
248	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
249	/**
250	* Checks if the current AMD CPU is subject to erratum 170 "In SVM mode,
251	* incorrect code bytes may be fetched after a world-switch".
252	*
253	* @param pu32Family Where to store the CPU family (can be NULL).
254	* @param pu32Model Where to store the CPU model (can be NULL).
255	* @param pu32Stepping Where to store the CPU stepping (can be NULL).
256	* @returns true if the erratum applies, false otherwise.
257	*/
258	VMM_INT_DECL(int) HMIsSubjectToSvmErratum170(uint32_t pu32Family, uint32_t pu32Model, uint32_t *pu32Stepping)
259	{
260	/*
261	* Erratum 170 which requires a forced TLB flush for each world switch:
262	* See AMD spec. "Revision Guide for AMD NPT Family 0Fh Processors".
263	*
264	* All BH-G1/2 and DH-G1/2 models include a fix:
265	* Athlon X2: 0x6b 1/2
266	* 0x68 1/2
267	* Athlon 64: 0x7f 1
268	* 0x6f 2
269	* Sempron: 0x7f 1/2
270	* 0x6f 2
271	* 0x6c 2
272	* 0x7c 2
273	* Turion 64: 0x68 2
274	*/
275	uint32_t u32Dummy;
276	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
277	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
278	u32BaseFamily = (u32Version >> 8) & 0xf;
279	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
280	u32Model = ((u32Version >> 4) & 0xf);
281	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
282	u32Stepping = u32Version & 0xf;
283
284	bool fErratumApplies = false;
285	if ( u32Family == 0xf
286	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
287	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
288	fErratumApplies = true;
289
290	if (pu32Family)
291	*pu32Family = u32Family;
292	if (pu32Model)
293	*pu32Model = u32Model;
294	if (pu32Stepping)
295	*pu32Stepping = u32Stepping;
296
297	return fErratumApplies;
298	}
299	#endif
300
301
302	/**
303	* Converts an SVM event type to a TRPM event type.
304	*
305	* @returns The TRPM event type.
306	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
307	* of recognized trap types.
308	*
309	* @param pEvent Pointer to the SVM event.
310	* @param uVector The vector associated with the event.
311	*/
312	VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent, uint8_t uVector)
313	{
314	uint8_t const uType = pEvent->n.u3Type;
315	switch (uType)
316	{
317	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
318	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
319	case SVM_EVENT_NMI: return TRPM_TRAP;
320	case SVM_EVENT_EXCEPTION:
321	{
322	if ( uVector == X86_XCPT_BP
323	\|\| uVector == X86_XCPT_OF)
324	return TRPM_SOFTWARE_INT;
325	return TRPM_TRAP;
326	}
327	default:
328	break;
329	}
330	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
331	return TRPM_32BIT_HACK;
332	}
333
334
335	/**
336	* Gets the SVM nested-guest control intercepts if cached by HM.
337	*
338	* @returns @c true on success, @c false otherwise.
339	* @param pVCpu The cross context virtual CPU structure of the calling
340	* EMT.
341	* @param pu64Intercepts Where to store the control intercepts. Only updated when
342	* @c true is returned.
343	*/
344	VMM_INT_DECL(bool) HMGetGuestSvmCtrlIntercepts(PCVMCPU pVCpu, uint64_t *pu64Intercepts)
345	{
346	Assert(pu64Intercepts);
347	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
348	if (pVmcbNstGstCache->fCacheValid)
349	{
350	*pu64Intercepts = pVmcbNstGstCache->u64InterceptCtrl;
351	return true;
352	}
353	return false;
354	}
355
356
357	/**
358	* Gets the SVM nested-guest CRx-read intercepts if cached by HM.
359	*
360	* @returns @c true on success, @c false otherwise.
361	* @param pVCpu The cross context virtual CPU structure of the calling
362	* EMT.
363	* @param pu16Intercepts Where to store the CRx-read intercepts. Only updated
364	* when @c true is returned.
365	*/
366	VMM_INT_DECL(bool) HMGetGuestSvmReadCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
367	{
368	Assert(pu16Intercepts);
369	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
370	if (pVmcbNstGstCache->fCacheValid)
371	{
372	*pu16Intercepts = pVmcbNstGstCache->u16InterceptRdCRx;
373	return true;
374	}
375	return false;
376	}
377
378
379	/**
380	* Gets the SVM nested-guest CRx-write intercepts if cached by HM.
381	*
382	* @returns @c true on success, @c false otherwise.
383	* @param pVCpu The cross context virtual CPU structure of the calling
384	* EMT.
385	* @param pu16Intercepts Where to store the CRx-write intercepts. Only updated
386	* when @c true is returned.
387	*/
388	VMM_INT_DECL(bool) HMGetGuestSvmWriteCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
389	{
390	Assert(pu16Intercepts);
391	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
392	if (pVmcbNstGstCache->fCacheValid)
393	{
394	*pu16Intercepts = pVmcbNstGstCache->u16InterceptWrCRx;
395	return true;
396	}
397	return false;
398	}
399
400
401	/**
402	* Gets the SVM nested-guest DRx-read intercepts if cached by HM.
403	*
404	* @returns @c true on success, @c false otherwise.
405	* @param pVCpu The cross context virtual CPU structure of the calling
406	* EMT.
407	* @param pu16Intercepts Where to store the DRx-read intercepts. Only updated
408	* when @c true is returned.
409	*/
410	VMM_INT_DECL(bool) HMGetGuestSvmReadDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
411	{
412	Assert(pu16Intercepts);
413	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
414	if (pVmcbNstGstCache->fCacheValid)
415	{
416	*pu16Intercepts = pVmcbNstGstCache->u16InterceptRdDRx;
417	return true;
418	}
419	return false;
420	}
421
422
423	/**
424	* Gets the SVM nested-guest DRx-write intercepts if cached by HM.
425	*
426	* @returns @c true on success, @c false otherwise.
427	* @param pVCpu The cross context virtual CPU structure of the calling
428	* EMT.
429	* @param pu16Intercepts Where to store the DRx-write intercepts. Only updated
430	* when @c true is returned.
431	*/
432	VMM_INT_DECL(bool) HMGetGuestSvmWriteDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
433	{
434	Assert(pu16Intercepts);
435	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
436	if (pVmcbNstGstCache->fCacheValid)
437	{
438	*pu16Intercepts = pVmcbNstGstCache->u16InterceptWrDRx;
439	return true;
440	}
441	return false;
442	}
443
444
445	/**
446	* Gets the SVM nested-guest exception intercepts if cached by HM.
447	*
448	* @returns @c true on success, @c false otherwise.
449	* @param pVCpu The cross context virtual CPU structure of the calling
450	* EMT.
451	* @param pu32Intercepts Where to store the exception intercepts. Only updated
452	* when @c true is returned.
453	*/
454	VMM_INT_DECL(bool) HMGetGuestSvmXcptIntercepts(PCVMCPU pVCpu, uint32_t *pu32Intercepts)
455	{
456	Assert(pu32Intercepts);
457	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
458	if (pVmcbNstGstCache->fCacheValid)
459	{
460	*pu32Intercepts = pVmcbNstGstCache->u32InterceptXcpt;
461	return true;
462	}
463	return false;
464	}
465
466
467	/**
468	* Checks if the nested-guest VMCB has virtual-interrupts masking enabled.
469	*
470	* @returns @c true on success, @c false otherwise.
471	* @param pVCpu The cross context virtual CPU structure of the calling
472	* EMT.
473	* @param pfVIntrMasking Where to store the virtual-interrupt masking bit.
474	* Updated only when @c true is returned.
475	*/
476	VMM_INT_DECL(bool) HMGetGuestSvmVirtIntrMasking(PCVMCPU pVCpu, bool *pfVIntrMasking)
477	{
478	Assert(pfVIntrMasking);
479	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
480	if (pVmcbNstGstCache->fCacheValid)
481	{
482	*pfVIntrMasking = pVmcbNstGstCache->fVIntrMasking;
483	return true;
484	}
485	return false;
486	}
487
488
489	/**
490	* Gets the SVM nested-guest nested-paging bit if cached by HM.
491	*
492	* @returns @c true on success, @c false otherwise.
493	* @param pVCpu The cross context virtual CPU structure of the
494	* calling EMT.
495	* @param pfNestedPaging Where to store the nested-paging bit. Updated only
496	* when @c true is returned.
497	*/
498	VMM_INT_DECL(bool) HMGetGuestSvmNestedPaging(PCVMCPU pVCpu, bool *pfNestedPaging)
499	{
500	Assert(pfNestedPaging);
501	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
502	if (pVmcbNstGstCache->fCacheValid)
503	{
504	*pfNestedPaging = pVmcbNstGstCache->fNestedPaging;
505	return true;
506	}
507	return false;
508	}
509
510
511	/**
512	* Returns the nested-guest VMCB pause-filter count.
513	*
514	* @returns @c true on success, @c false otherwise.
515	* @param pVCpu The cross context virtual CPU structure of the
516	* calling EMT.
517	* @param pu16PauseFilterCount Where to store the pause-filter count. Only
518	* updated @c true is returned.
519	*/
520	VMM_INT_DECL(bool) HMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, uint16_t *pu16PauseFilterCount)
521	{
522	Assert(pu16PauseFilterCount);
523	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
524	if (pVmcbNstGstCache->fCacheValid)
525	{
526	*pu16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
527	return true;
528	}
529	return false;
530	}
531
532
533	/**
534	* Returns the SVM nested-guest TSC offset if cached by HM.
535	*
536	* @returns The TSC offset after applying any nested-guest TSC offset.
537	* @param pVCpu The cross context virtual CPU structure of the calling
538	* EMT.
539	* @param pu64TscOffset Where to store the TSC offset. Only updated when @c
540	* true is returned.
541	*/
542	VMM_INT_DECL(bool) HMGetGuestSvmTscOffset(PCVMCPU pVCpu, uint64_t *pu64TscOffset)
543	{
544	Assert(pu64TscOffset);
545	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
546	if (pVmcbNstGstCache->fCacheValid)
547	{
548	*pu64TscOffset = pVmcbNstGstCache->u64TSCOffset;
549	return true;
550	}
551	return false;
552	}
553

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 97405

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