VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/HMAll.cpp@ 95085

Last change on this file since 95085 was 93725, checked in by vboxsync, 3 years ago

VMM: More arm64 adjustments. bugref:9898
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 37.4 KB
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1/* $Id: HMAll.cpp 93725 2022-02-14 13:46:16Z vboxsync $ */
2/** @file
3 * HM - All contexts.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/pgm.h>
26#include "HMInternal.h"
27#include <VBox/vmm/vmcc.h>
28#include <VBox/vmm/hm_vmx.h>
29#include <VBox/vmm/hm_svm.h>
30#include <iprt/errcore.h>
31#include <VBox/log.h>
32#include <iprt/param.h>
33#include <iprt/assert.h>
34#include <iprt/asm.h>
35#include <iprt/string.h>
36#include <iprt/thread.h>
37#include <iprt/x86.h>
38
39
40/*********************************************************************************************************************************
41* Global Variables *
42*********************************************************************************************************************************/
43#define EXIT_REASON(a_Def, a_Val, a_Str) #a_Def " - " #a_Val " - " a_Str
44#define EXIT_REASON_NIL() NULL
45
46/** Exit reason descriptions for VT-x, used to describe statistics and exit
47 * history. */
48static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
49{
50 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
51 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
52 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
53 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
54 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
55 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
56 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
57 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
58 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
59 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
60 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
61 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instruction."),
62 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
63 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
64 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
65 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMC instruction."),
66 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
67 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
68 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
69 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
70 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
71 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
72 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
73 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
74 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
75 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
76 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
77 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
78 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
79 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
80 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
81 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
82 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
83 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
84 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
85 EXIT_REASON_NIL(),
86 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
87 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
88 EXIT_REASON_NIL(),
89 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
90 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
91 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
92 EXIT_REASON_NIL(),
93 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
94 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
95 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
96 EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
97 EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
98 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
99 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
100 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
101 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
102 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
103 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
104 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
105 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
106 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
107 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
108 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
109 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
110 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
111 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
112 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
113 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
114 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction."),
115 EXIT_REASON_NIL(),
116 EXIT_REASON(VMX_EXIT_SPP_EVENT , 66, "SPP-related event."),
117 EXIT_REASON(VMX_EXIT_UMWAIT , 67, "UMWAIT instruction."),
118 EXIT_REASON(VMX_EXIT_TPAUSE , 68, "TPAUSE instruction.")
119};
120/** Array index of the last valid VT-x exit reason. */
121#define MAX_EXITREASON_VTX 68
122
123/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
124 * statistics and exit history.
125 *
126 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
127 * this array doesn't contain the entire set of exit reasons, we
128 * handle them via hmSvmGetSpecialExitReasonDesc(). */
129static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
130{
131 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
132 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
133 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
134 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
135 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
136 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
137 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
138 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
139 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
140 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
141 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
142 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
143 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
144 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
145 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
146 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
160 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
161 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
162 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
163 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
164 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
165 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
166 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
167 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
168 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
169 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
170 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
171 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
172 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
173 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
174 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
175 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
176 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
177 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
178 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
192 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
193 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
194 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
195 EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
196 EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
197 EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
198 EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
199 EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
200 EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
201 EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
202 EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
203 EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
204 EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
205 EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
206 EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
207 EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
208 EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
209 EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
210 EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
211 EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
212 EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
213 EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
214 EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
215 EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
216 EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
217 EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
218 EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
219 EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
220 EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
221 EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
222 EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
223 EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
224 EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
225 EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
226 EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
227 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
228 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
229 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
230 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
231 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
232 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE , 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
233 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
234 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
235 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
237 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
238 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
239 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
240 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
241 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
242 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
243 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
244 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
245 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
246 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
247 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
248 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
249 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
250 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
251 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
252 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
253 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
254 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
255 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
256 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
257 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
258 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
259 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
260 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
261 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
262 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
263 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
264 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
265 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
266 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
267 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
268 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
269 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
270 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
271 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
272 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
273 EXIT_REASON(SVM_EXIT_RDPRU , 142, "RDPRU instruction."),
274 EXIT_REASON(SVM_EXIT_WRITE_EFER_TRAP, 143, "Write EFER (trap-like)."),
275 EXIT_REASON(SVM_EXIT_WRITE_CR0_TRAP , 144, "Write CR0 (trap-like)."),
276 EXIT_REASON(SVM_EXIT_WRITE_CR1_TRAP , 145, "Write CR1 (trap-like)."),
277 EXIT_REASON(SVM_EXIT_WRITE_CR2_TRAP , 146, "Write CR2 (trap-like)."),
278 EXIT_REASON(SVM_EXIT_WRITE_CR3_TRAP , 147, "Write CR3 (trap-like)."),
279 EXIT_REASON(SVM_EXIT_WRITE_CR4_TRAP , 148, "Write CR4 (trap-like)."),
280 EXIT_REASON(SVM_EXIT_WRITE_CR5_TRAP , 149, "Write CR5 (trap-like)."),
281 EXIT_REASON(SVM_EXIT_WRITE_CR6_TRAP , 150, "Write CR6 (trap-like)."),
282 EXIT_REASON(SVM_EXIT_WRITE_CR7_TRAP , 151, "Write CR7 (trap-like)."),
283 EXIT_REASON(SVM_EXIT_WRITE_CR8_TRAP , 152, "Write CR8 (trap-like)."),
284 EXIT_REASON(SVM_EXIT_WRITE_CR9_TRAP , 153, "Write CR9 (trap-like)."),
285 EXIT_REASON(SVM_EXIT_WRITE_CR10_TRAP, 154, "Write CR10 (trap-like)."),
286 EXIT_REASON(SVM_EXIT_WRITE_CR11_TRAP, 155, "Write CR11 (trap-like)."),
287 EXIT_REASON(SVM_EXIT_WRITE_CR12_TRAP, 156, "Write CR12 (trap-like)."),
288 EXIT_REASON(SVM_EXIT_WRITE_CR13_TRAP, 157, "Write CR13 (trap-like)."),
289 EXIT_REASON(SVM_EXIT_WRITE_CR14_TRAP, 158, "Write CR14 (trap-like)."),
290 EXIT_REASON(SVM_EXIT_WRITE_CR15_TRAP, 159, "Write CR15 (trap-like)."),
291 EXIT_REASON_NIL() ,
292 EXIT_REASON_NIL() ,
293 EXIT_REASON_NIL() ,
294 EXIT_REASON(SVM_EXIT_MCOMMIT , 163, "MCOMMIT instruction."),
295};
296/** Array index of the last valid AMD-V exit reason. */
297#define MAX_EXITREASON_AMDV 163
298
299/** Special exit reasons not covered in the array above. */
300#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
301#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
302#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
303
304/**
305 * Gets the SVM exit reason if it's one of the reasons not present in the @c
306 * g_apszSvmExitReasons array.
307 *
308 * @returns The exit reason or NULL if unknown.
309 * @param uExit The exit.
310 */
311DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
312{
313 switch (uExit)
314 {
315 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
316 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
317 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
318 }
319 return EXIT_REASON_NIL();
320}
321#undef EXIT_REASON_NIL
322#undef EXIT_REASON
323
324
325/**
326 * Checks whether HM (VT-x/AMD-V) is being used by this VM.
327 *
328 * @retval true if used.
329 * @retval false if software virtualization (raw-mode) is used.
330 * @param pVM The cross context VM structure.
331 * @sa HMIsEnabled, HMR3IsEnabled
332 * @internal
333 */
334VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM)
335{
336 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
337 return pVM->fHMEnabled;
338}
339
340
341/**
342 * Checks if the guest is in a suitable state for hardware-assisted execution.
343 *
344 * @returns @c true if it is suitable, @c false otherwise.
345 * @param pVM The cross context VM structure.
346 * @param pVCpu The cross context virtual CPU structure.
347 * @param pCtx Pointer to the guest CPU context.
348 *
349 * @remarks @a pCtx can be a partial context created and not necessarily the same as
350 * pVCpu->cpum.GstCtx.
351 */
352VMMDECL(bool) HMCanExecuteGuest(PVMCC pVM, PVMCPUCC pVCpu, PCCPUMCTX pCtx)
353{
354 Assert(HMIsEnabled(pVM));
355
356#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
357 if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
358 || CPUMIsGuestInVmxNonRootMode(pCtx))
359 {
360 LogFunc(("In nested-guest mode - returning false"));
361 return false;
362 }
363#endif
364
365 /* AMD-V supports real & protected mode with or without paging. */
366 if (pVM->hm.s.svm.fEnabled)
367 {
368 pVCpu->hm.s.fActive = true;
369 return true;
370 }
371
372 bool rc = HMCanExecuteVmxGuest(pVM, pVCpu, pCtx);
373 LogFlowFunc(("returning %RTbool\n", rc));
374 return rc;
375}
376
377
378/**
379 * Queues a guest page for invalidation.
380 *
381 * @returns VBox status code.
382 * @param pVCpu The cross context virtual CPU structure.
383 * @param GCVirt Page to invalidate.
384 */
385static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
386{
387 /* Nothing to do if a TLB flush is already pending */
388 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
389 return;
390 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
391 NOREF(GCVirt);
392}
393
394
395/**
396 * Invalidates a guest page.
397 *
398 * @returns VBox status code.
399 * @param pVCpu The cross context virtual CPU structure.
400 * @param GCVirt Page to invalidate.
401 */
402VMM_INT_DECL(int) HMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
403{
404 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
405#ifdef IN_RING0
406 return HMR0InvalidatePage(pVCpu, GCVirt);
407#else
408 hmQueueInvlPage(pVCpu, GCVirt);
409 return VINF_SUCCESS;
410#endif
411}
412
413
414#ifdef IN_RING0
415
416/**
417 * Dummy RTMpOnSpecific handler since RTMpPokeCpu couldn't be used.
418 *
419 */
420static DECLCALLBACK(void) hmFlushHandler(RTCPUID idCpu, void *pvUser1, void *pvUser2)
421{
422 NOREF(idCpu); NOREF(pvUser1); NOREF(pvUser2);
423 return;
424}
425
426
427/**
428 * Wrapper for RTMpPokeCpu to deal with VERR_NOT_SUPPORTED.
429 */
430static void hmR0PokeCpu(PVMCPUCC pVCpu, RTCPUID idHostCpu)
431{
432 uint32_t cWorldSwitchExits = ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits);
433
434 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatPoke, x);
435 int rc = RTMpPokeCpu(idHostCpu);
436 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPoke, x);
437
438 /* Not implemented on some platforms (Darwin, Linux kernel < 2.6.19); fall
439 back to a less efficient implementation (broadcast). */
440 if (rc == VERR_NOT_SUPPORTED)
441 {
442 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
443 /* synchronous. */
444 RTMpOnSpecific(idHostCpu, hmFlushHandler, 0, 0);
445 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
446 }
447 else
448 {
449 if (rc == VINF_SUCCESS)
450 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
451 else
452 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPokeFailed, z);
453
454/** @todo If more than one CPU is going to be poked, we could optimize this
455 * operation by poking them first and wait afterwards. Would require
456 * recording who to poke and their current cWorldSwitchExits values,
457 * that's something not suitable for stack... So, pVCpu->hm.s.something
458 * then. */
459 /* Spin until the VCPU has switched back (poking is async). */
460 while ( ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush)
461 && cWorldSwitchExits == ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits))
462 ASMNopPause();
463
464 if (rc == VINF_SUCCESS)
465 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
466 else
467 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPokeFailed, z);
468 }
469}
470
471#endif /* IN_RING0 */
472
473/**
474 * Flushes the guest TLB.
475 *
476 * @returns VBox status code.
477 * @param pVCpu The cross context virtual CPU structure.
478 */
479VMM_INT_DECL(int) HMFlushTlb(PVMCPU pVCpu)
480{
481 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
482 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbManual);
483 return VINF_SUCCESS;
484}
485
486
487/**
488 * Poke an EMT so it can perform the appropriate TLB shootdowns.
489 *
490 * @param pVCpu The cross context virtual CPU structure of the
491 * EMT poke.
492 * @param fAccountFlushStat Whether to account the call to
493 * StatTlbShootdownFlush or StatTlbShootdown.
494 */
495static void hmPokeCpuForTlbFlush(PVMCPUCC pVCpu, bool fAccountFlushStat)
496{
497 if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
498 {
499 if (fAccountFlushStat)
500 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdownFlush);
501 else
502 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
503#ifdef IN_RING0
504 RTCPUID idHostCpu = pVCpu->hmr0.s.idEnteredCpu;
505 if (idHostCpu != NIL_RTCPUID)
506 hmR0PokeCpu(pVCpu, idHostCpu);
507#else
508 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
509#endif
510 }
511 else
512 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
513}
514
515
516/**
517 * Invalidates a guest page on all VCPUs.
518 *
519 * @returns VBox status code.
520 * @param pVM The cross context VM structure.
521 * @param GCVirt Page to invalidate.
522 */
523VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVMCC pVM, RTGCPTR GCVirt)
524{
525 /*
526 * The VT-x/AMD-V code will be flushing TLB each time a VCPU migrates to a different
527 * host CPU, see hmR0VmxFlushTaggedTlbBoth() and hmR0SvmFlushTaggedTlb().
528 *
529 * This is the reason why we do not care about thread preemption here and just
530 * execute HMInvalidatePage() assuming it might be the 'right' CPU.
531 */
532 VMCPUID const idCurCpu = VMMGetCpuId(pVM);
533 STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idCurCpu)->hm.s.StatFlushPage);
534
535 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
536 {
537 PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
538
539 /* Nothing to do if a TLB flush is already pending; the VCPU should
540 have already been poked if it were active. */
541 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
542 continue;
543
544 if (pVCpu->idCpu == idCurCpu)
545 HMInvalidatePage(pVCpu, GCVirt);
546 else
547 {
548 hmQueueInvlPage(pVCpu, GCVirt);
549 hmPokeCpuForTlbFlush(pVCpu, false /* fAccountFlushStat */);
550 }
551 }
552
553 return VINF_SUCCESS;
554}
555
556
557/**
558 * Flush the TLBs of all VCPUs.
559 *
560 * @returns VBox status code.
561 * @param pVM The cross context VM structure.
562 */
563VMM_INT_DECL(int) HMFlushTlbOnAllVCpus(PVMCC pVM)
564{
565 if (pVM->cCpus == 1)
566 return HMFlushTlb(VMCC_GET_CPU_0(pVM));
567
568 VMCPUID const idThisCpu = VMMGetCpuId(pVM);
569
570 STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idThisCpu)->hm.s.StatFlushTlb);
571
572 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
573 {
574 PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
575
576 /* Nothing to do if a TLB flush is already pending; the VCPU should
577 have already been poked if it were active. */
578 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
579 {
580 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
581 if (idThisCpu != idCpu)
582 hmPokeCpuForTlbFlush(pVCpu, true /* fAccountFlushStat */);
583 }
584 }
585
586 return VINF_SUCCESS;
587}
588
589
590/**
591 * Invalidates a guest page by physical address.
592 *
593 * @returns VBox status code.
594 * @param pVM The cross context VM structure.
595 * @param GCPhys Page to invalidate.
596 *
597 * @remarks Assumes the current instruction references this physical page
598 * though a virtual address!
599 */
600VMM_INT_DECL(int) HMInvalidatePhysPage(PVMCC pVM, RTGCPHYS GCPhys)
601{
602 if (!HMIsNestedPagingActive(pVM))
603 return VINF_SUCCESS;
604
605 /*
606 * AMD-V: Doesn't support invalidation with guest physical addresses.
607 *
608 * VT-x: Doesn't support invalidation with guest physical addresses.
609 * INVVPID instruction takes only a linear address while invept only flushes by EPT
610 * not individual addresses.
611 *
612 * We update the force flag and flush before the next VM-entry, see @bugref{6568}.
613 */
614 RT_NOREF(GCPhys);
615 /** @todo Remove or figure out to way to update the Phys STAT counter. */
616 /* STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys); */
617 return HMFlushTlbOnAllVCpus(pVM);
618}
619
620
621/**
622 * Checks if nested paging is enabled.
623 *
624 * @returns true if nested paging is active, false otherwise.
625 * @param pVM The cross context VM structure.
626 *
627 * @remarks Works before hmR3InitFinalizeR0.
628 */
629VMM_INT_DECL(bool) HMIsNestedPagingActive(PVMCC pVM)
630{
631 return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING);
632}
633
634
635/**
636 * Checks if both nested paging and unhampered guest execution are enabled.
637 *
638 * The almost complete guest execution in hardware is only applicable to VT-x.
639 *
640 * @returns true if we have both enabled, otherwise false.
641 * @param pVM The cross context VM structure.
642 *
643 * @remarks Works before hmR3InitFinalizeR0.
644 */
645VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVMCC pVM)
646{
647 return HMIsEnabled(pVM)
648 && CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING)
649 && ( CTX_EXPR(pVM->hm.s.vmx.fUnrestrictedGuestCfg, pVM->hmr0.s.vmx.fUnrestrictedGuest, RT_NOTHING)
650 || pVM->hm.s.svm.fSupported);
651}
652
653
654/**
655 * Checks if this VM is using HM and is long-mode capable.
656 *
657 * Use VMR3IsLongModeAllowed() instead of this, when possible.
658 *
659 * @returns true if long mode is allowed, false otherwise.
660 * @param pVM The cross context VM structure.
661 * @sa VMR3IsLongModeAllowed, NEMHCIsLongModeAllowed
662 */
663VMM_INT_DECL(bool) HMIsLongModeAllowed(PVMCC pVM)
664{
665 return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fAllow64BitGuestsCfg, pVM->hmr0.s.fAllow64BitGuests, RT_NOTHING);
666}
667
668
669/**
670 * Checks if MSR bitmaps are active. It is assumed that when it's available
671 * it will be used as well.
672 *
673 * @returns true if MSR bitmaps are available, false otherwise.
674 * @param pVM The cross context VM structure.
675 */
676VMM_INT_DECL(bool) HMIsMsrBitmapActive(PVM pVM)
677{
678 if (HMIsEnabled(pVM))
679 {
680 if (pVM->hm.s.svm.fSupported)
681 return true;
682
683 if ( pVM->hm.s.vmx.fSupported
684 && ( CTX_EXPR(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1, g_HmMsrs.u.vmx.ProcCtls.n.allowed1, RT_NOTHING)
685 & VMX_PROC_CTLS_USE_MSR_BITMAPS))
686 return true;
687 }
688 return false;
689}
690
691
692/**
693 * Checks if AMD-V is active.
694 *
695 * @returns true if AMD-V is active.
696 * @param pVM The cross context VM structure.
697 *
698 * @remarks Works before hmR3InitFinalizeR0.
699 */
700VMM_INT_DECL(bool) HMIsSvmActive(PVM pVM)
701{
702 return pVM->hm.s.svm.fSupported && HMIsEnabled(pVM);
703}
704
705
706/**
707 * Checks if VT-x is active.
708 *
709 * @returns true if VT-x is active.
710 * @param pVM The cross context VM structure.
711 *
712 * @remarks Works before hmR3InitFinalizeR0.
713 */
714VMM_INT_DECL(bool) HMIsVmxActive(PVM pVM)
715{
716 return pVM->hm.s.vmx.fSupported && HMIsEnabled(pVM);
717}
718
719
720/**
721 * Checks if an interrupt event is currently pending.
722 *
723 * @returns Interrupt event pending state.
724 * @param pVM The cross context VM structure.
725 */
726VMM_INT_DECL(bool) HMHasPendingIrq(PVMCC pVM)
727{
728 PVMCPUCC pVCpu = VMMGetCpu(pVM);
729 return !!pVCpu->hm.s.Event.fPending;
730}
731
732
733/**
734 * Sets or clears the single instruction flag.
735 *
736 * When set, HM will try its best to return to ring-3 after executing a single
737 * instruction. This can be used for debugging. See also
738 * EMR3HmSingleInstruction.
739 *
740 * @returns The old flag state.
741 * @param pVM The cross context VM structure.
742 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
743 * @param fEnable The new flag state.
744 */
745VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCC pVM, PVMCPUCC pVCpu, bool fEnable)
746{
747 VMCPU_ASSERT_EMT(pVCpu);
748 bool fOld = pVCpu->hm.s.fSingleInstruction;
749 pVCpu->hm.s.fSingleInstruction = fEnable;
750 pVCpu->hm.s.fUseDebugLoop = fEnable || pVM->hm.s.fUseDebugLoop;
751 return fOld;
752}
753
754
755/**
756 * Notification callback which is called whenever there is a chance that a CR3
757 * value might have changed.
758 *
759 * This is called by PGM.
760 *
761 * @param pVM The cross context VM structure.
762 * @param pVCpu The cross context virtual CPU structure.
763 * @param enmShadowMode New shadow paging mode.
764 * @param enmGuestMode New guest paging mode.
765 */
766VMM_INT_DECL(void) HMHCChangedPagingMode(PVM pVM, PVMCPUCC pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
767{
768#ifdef IN_RING3
769 /* Ignore page mode changes during state loading. */
770 if (VMR3GetState(pVM) == VMSTATE_LOADING)
771 return;
772#endif
773
774 pVCpu->hm.s.enmShadowMode = enmShadowMode;
775
776 /*
777 * If the guest left protected mode VMX execution, we'll have to be
778 * extra careful if/when the guest switches back to protected mode.
779 */
780 if (enmGuestMode == PGMMODE_REAL)
781 {
782 PVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
783 pVmcsInfoShared->fWasInRealMode = true;
784 }
785
786#ifdef IN_RING0
787 /*
788 * We need to tickle SVM and VT-x state updates.
789 *
790 * Note! We could probably reduce this depending on what exactly changed.
791 */
792 if (VM_IS_HM_ENABLED(pVM))
793 {
794 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER); /* No recursion! */
795 uint64_t fChanged = HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 | HM_CHANGED_GUEST_EFER_MSR;
796 if (pVM->hm.s.svm.fSupported)
797 fChanged |= HM_CHANGED_SVM_XCPT_INTERCEPTS;
798 else
799 fChanged |= HM_CHANGED_VMX_XCPT_INTERCEPTS | HM_CHANGED_VMX_ENTRY_EXIT_CTLS;
800 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, fChanged);
801 }
802#endif
803
804 Log4(("HMHCChangedPagingMode: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
805 PGMGetModeName(enmShadowMode)));
806}
807
808
809/**
810 * Gets VMX MSRs from the provided hardware-virtualization MSRs struct.
811 *
812 * This abstraction exists to insulate the support driver from including VMX
813 * structures from HM headers.
814 *
815 * @param pHwvirtMsrs The hardware-virtualization MSRs.
816 * @param pVmxMsrs Where to store the VMX MSRs.
817 */
818VMM_INT_DECL(void) HMGetVmxMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PVMXMSRS pVmxMsrs)
819{
820 AssertReturnVoid(pHwvirtMsrs);
821 AssertReturnVoid(pVmxMsrs);
822 pVmxMsrs->u64Basic = pHwvirtMsrs->u.vmx.u64Basic;
823 pVmxMsrs->PinCtls.u = pHwvirtMsrs->u.vmx.PinCtls.u;
824 pVmxMsrs->ProcCtls.u = pHwvirtMsrs->u.vmx.ProcCtls.u;
825 pVmxMsrs->ProcCtls2.u = pHwvirtMsrs->u.vmx.ProcCtls2.u;
826 pVmxMsrs->ExitCtls.u = pHwvirtMsrs->u.vmx.ExitCtls.u;
827 pVmxMsrs->EntryCtls.u = pHwvirtMsrs->u.vmx.EntryCtls.u;
828 pVmxMsrs->TruePinCtls.u = pHwvirtMsrs->u.vmx.TruePinCtls.u;
829 pVmxMsrs->TrueProcCtls.u = pHwvirtMsrs->u.vmx.TrueProcCtls.u;
830 pVmxMsrs->TrueEntryCtls.u = pHwvirtMsrs->u.vmx.TrueEntryCtls.u;
831 pVmxMsrs->TrueExitCtls.u = pHwvirtMsrs->u.vmx.TrueExitCtls.u;
832 pVmxMsrs->u64Misc = pHwvirtMsrs->u.vmx.u64Misc;
833 pVmxMsrs->u64Cr0Fixed0 = pHwvirtMsrs->u.vmx.u64Cr0Fixed0;
834 pVmxMsrs->u64Cr0Fixed1 = pHwvirtMsrs->u.vmx.u64Cr0Fixed1;
835 pVmxMsrs->u64Cr4Fixed0 = pHwvirtMsrs->u.vmx.u64Cr4Fixed0;
836 pVmxMsrs->u64Cr4Fixed1 = pHwvirtMsrs->u.vmx.u64Cr4Fixed1;
837 pVmxMsrs->u64VmcsEnum = pHwvirtMsrs->u.vmx.u64VmcsEnum;
838 pVmxMsrs->u64VmFunc = pHwvirtMsrs->u.vmx.u64VmFunc;
839 pVmxMsrs->u64EptVpidCaps = pHwvirtMsrs->u.vmx.u64EptVpidCaps;
840 pVmxMsrs->u64ProcCtls3 = pHwvirtMsrs->u.vmx.u64ProcCtls3;
841}
842
843
844/**
845 * Gets SVM MSRs from the provided hardware-virtualization MSRs struct.
846 *
847 * This abstraction exists to insulate the support driver from including SVM
848 * structures from HM headers.
849 *
850 * @param pHwvirtMsrs The hardware-virtualization MSRs.
851 * @param pSvmMsrs Where to store the SVM MSRs.
852 */
853VMM_INT_DECL(void) HMGetSvmMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PSVMMSRS pSvmMsrs)
854{
855 AssertReturnVoid(pHwvirtMsrs);
856 AssertReturnVoid(pSvmMsrs);
857 pSvmMsrs->u64MsrHwcr = pHwvirtMsrs->u.svm.u64MsrHwcr;
858}
859
860
861/**
862 * Gets the name of a VT-x exit code.
863 *
864 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
865 * @param uExit The VT-x exit to name.
866 */
867VMM_INT_DECL(const char *) HMGetVmxExitName(uint32_t uExit)
868{
869 uint16_t const uReason = VMX_EXIT_REASON_BASIC(uExit);
870 if (uReason <= MAX_EXITREASON_VTX)
871 {
872 Assert(uReason < RT_ELEMENTS(g_apszVmxExitReasons));
873 return g_apszVmxExitReasons[uReason];
874 }
875 return NULL;
876}
877
878
879/**
880 * Gets the name of an AMD-V exit code.
881 *
882 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
883 * @param uExit The AMD-V exit to name.
884 */
885VMM_INT_DECL(const char *) HMGetSvmExitName(uint32_t uExit)
886{
887 if (uExit <= MAX_EXITREASON_AMDV)
888 {
889 Assert(uExit < RT_ELEMENTS(g_apszSvmExitReasons));
890 return g_apszSvmExitReasons[uExit];
891 }
892 return hmSvmGetSpecialExitReasonDesc(uExit);
893}
894
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