VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/HMAll.cpp@ 51906

Last change on this file since 51906 was 51560, checked in by vboxsync, 10 years ago

VMM/GIM: Mapping of GIM MMIO2 regions and Hyper-V provider work.
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1/* $Id: HMAll.cpp 51560 2014-06-06 05:17:02Z vboxsync $ */
2/** @file
3 * HM - All contexts.
4 */
5
6/*
7 * Copyright (C) 2006-2014 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/hm.h>
24#include <VBox/vmm/pgm.h>
25#include "HMInternal.h"
26#include <VBox/vmm/vm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/hm_svm.h>
29#include <VBox/err.h>
30#include <VBox/log.h>
31#include <iprt/param.h>
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/string.h>
35#include <iprt/thread.h>
36#include <iprt/x86.h>
37#include <iprt/asm-amd64-x86.h>
38
39
40/**
41 * Checks whether HM (VT-x/AMD-V) is being used by this VM.
42 *
43 * @retval @c true if used.
44 * @retval @c false if software virtualization (raw-mode) is used.
45 * @param pVM The cross context VM structure.
46 * @sa HMIsEnabled, HMR3IsEnabled
47 * @internal
48 */
49VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM)
50{
51 Assert(pVM->fHMEnabledFixed);
52 return pVM->fHMEnabled;
53}
54
55
56/**
57 * Queues a page for invalidation
58 *
59 * @returns VBox status code.
60 * @param pVCpu Pointer to the VMCPU.
61 * @param GCVirt Page to invalidate
62 */
63static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
64{
65 /* Nothing to do if a TLB flush is already pending */
66 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
67 return;
68#if 1
69 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
70 NOREF(GCVirt);
71#else
72 /* Be very careful when activating this code! */
73 if (iPage == RT_ELEMENTS(pVCpu->hm.s.TlbShootdown.aPages))
74 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
75 else
76 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
77#endif
78}
79
80
81/**
82 * Invalidates a guest page
83 *
84 * @returns VBox status code.
85 * @param pVCpu Pointer to the VMCPU.
86 * @param GCVirt Page to invalidate
87 */
88VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
89{
90 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
91#ifdef IN_RING0
92 PVM pVM = pVCpu->CTX_SUFF(pVM);
93 if (pVM->hm.s.vmx.fSupported)
94 return VMXR0InvalidatePage(pVM, pVCpu, GCVirt);
95
96 Assert(pVM->hm.s.svm.fSupported);
97 return SVMR0InvalidatePage(pVM, pVCpu, GCVirt);
98
99#else
100 hmQueueInvlPage(pVCpu, GCVirt);
101 return VINF_SUCCESS;
102#endif
103}
104
105
106/**
107 * Flushes the guest TLB.
108 *
109 * @returns VBox status code.
110 * @param pVCpu Pointer to the VMCPU.
111 */
112VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu)
113{
114 LogFlow(("HMFlushTLB\n"));
115
116 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
117 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbManual);
118 return VINF_SUCCESS;
119}
120
121
122#ifdef IN_RING0
123/**
124 * Dummy RTMpOnSpecific handler since RTMpPokeCpu couldn't be used.
125 *
126 */
127static DECLCALLBACK(void) hmFlushHandler(RTCPUID idCpu, void *pvUser1, void *pvUser2)
128{
129 NOREF(idCpu); NOREF(pvUser1); NOREF(pvUser2);
130 return;
131}
132
133/**
134 * Wrapper for RTMpPokeCpu to deal with VERR_NOT_SUPPORTED.
135 */
136static void hmR0PokeCpu(PVMCPU pVCpu, RTCPUID idHostCpu)
137{
138 uint32_t cWorldSwitchExits = ASMAtomicUoReadU32(&pVCpu->hm.s.cWorldSwitchExits);
139
140 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatPoke, x);
141 int rc = RTMpPokeCpu(idHostCpu);
142 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPoke, x);
143
144 /* Not implemented on some platforms (Darwin, Linux kernel < 2.6.19); fall
145 back to a less efficient implementation (broadcast). */
146 if (rc == VERR_NOT_SUPPORTED)
147 {
148 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
149 /* synchronous. */
150 RTMpOnSpecific(idHostCpu, hmFlushHandler, 0, 0);
151 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
152 }
153 else
154 {
155 if (rc == VINF_SUCCESS)
156 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
157 else
158 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPokeFailed, z);
159
160/** @todo If more than one CPU is going to be poked, we could optimize this
161 * operation by poking them first and wait afterwards. Would require
162 * recording who to poke and their current cWorldSwitchExits values,
163 * that's something not suitable for stack... So, pVCpu->hm.s.something
164 * then. */
165 /* Spin until the VCPU has switched back (poking is async). */
166 while ( ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush)
167 && cWorldSwitchExits == ASMAtomicUoReadU32(&pVCpu->hm.s.cWorldSwitchExits))
168 ASMNopPause();
169
170 if (rc == VINF_SUCCESS)
171 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
172 else
173 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPokeFailed, z);
174 }
175}
176#endif /* IN_RING0 */
177
178
179#ifndef IN_RC
180/**
181 * Poke an EMT so it can perform the appropriate TLB shootdowns.
182 *
183 * @param pVCpu The handle of the virtual CPU to poke.
184 * @param fAccountFlushStat Whether to account the call to
185 * StatTlbShootdownFlush or StatTlbShootdown.
186 */
187static void hmPokeCpuForTlbFlush(PVMCPU pVCpu, bool fAccountFlushStat)
188{
189 if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
190 {
191 if (fAccountFlushStat)
192 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdownFlush);
193 else
194 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
195#ifdef IN_RING0
196 RTCPUID idHostCpu = pVCpu->hm.s.idEnteredCpu;
197 if (idHostCpu != NIL_RTCPUID)
198 hmR0PokeCpu(pVCpu, idHostCpu);
199#else
200 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
201#endif
202 }
203 else
204 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
205}
206
207
208/**
209 * Invalidates a guest page on all VCPUs.
210 *
211 * @returns VBox status code.
212 * @param pVM Pointer to the VM.
213 * @param GCVirt Page to invalidate
214 */
215VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCPtr)
216{
217 VMCPUID idCurCpu = VMMGetCpuId(pVM);
218 STAM_COUNTER_INC(&pVM->aCpus[idCurCpu].hm.s.StatFlushPage);
219
220 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
221 {
222 PVMCPU pVCpu = &pVM->aCpus[idCpu];
223
224 /* Nothing to do if a TLB flush is already pending; the VCPU should
225 have already been poked if it were active. */
226 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
227 continue;
228
229 if (pVCpu->idCpu == idCurCpu)
230 HMInvalidatePage(pVCpu, GCPtr);
231 else
232 {
233 hmQueueInvlPage(pVCpu, GCPtr);
234 hmPokeCpuForTlbFlush(pVCpu, false /* fAccountFlushStat */);
235 }
236 }
237
238 return VINF_SUCCESS;
239}
240
241
242/**
243 * Flush the TLBs of all VCPUs.
244 *
245 * @returns VBox status code.
246 * @param pVM Pointer to the VM.
247 */
248VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM)
249{
250 if (pVM->cCpus == 1)
251 return HMFlushTLB(&pVM->aCpus[0]);
252
253 VMCPUID idThisCpu = VMMGetCpuId(pVM);
254
255 STAM_COUNTER_INC(&pVM->aCpus[idThisCpu].hm.s.StatFlushTlb);
256
257 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
258 {
259 PVMCPU pVCpu = &pVM->aCpus[idCpu];
260
261 /* Nothing to do if a TLB flush is already pending; the VCPU should
262 have already been poked if it were active. */
263 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
264 {
265 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
266 if (idThisCpu != idCpu)
267 hmPokeCpuForTlbFlush(pVCpu, true /* fAccountFlushStat */);
268 }
269 }
270
271 return VINF_SUCCESS;
272}
273#endif /* !IN_RC */
274
275/**
276 * Checks if nested paging is enabled
277 *
278 * @returns boolean
279 * @param pVM Pointer to the VM.
280 */
281VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM)
282{
283 return HMIsEnabled(pVM) && pVM->hm.s.fNestedPaging;
284}
285
286/**
287 * Return the shadow paging mode for nested paging/ept
288 *
289 * @returns shadow paging mode
290 * @param pVM Pointer to the VM.
291 */
292VMM_INT_DECL(PGMMODE) HMGetShwPagingMode(PVM pVM)
293{
294 Assert(HMIsNestedPagingActive(pVM));
295 if (pVM->hm.s.svm.fSupported)
296 return PGMMODE_NESTED;
297
298 Assert(pVM->hm.s.vmx.fSupported);
299 return PGMMODE_EPT;
300}
301
302/**
303 * Invalidates a guest page by physical address
304 *
305 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
306 *
307 * @returns VBox status code.
308 * @param pVM Pointer to the VM.
309 * @param GCPhys Page to invalidate
310 */
311VMM_INT_DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
312{
313 if (!HMIsNestedPagingActive(pVM))
314 return VINF_SUCCESS;
315
316#ifdef IN_RING0
317 if (pVM->hm.s.vmx.fSupported)
318 {
319 VMCPUID idThisCpu = VMMGetCpuId(pVM);
320
321 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
322 {
323 PVMCPU pVCpu = &pVM->aCpus[idCpu];
324
325 if (idThisCpu == idCpu)
326 {
327 /** @todo r=ramshankar: Intel does not support flushing by guest physical
328 * address either. See comment in VMXR0InvalidatePhysPage(). Fix this. */
329 VMXR0InvalidatePhysPage(pVM, pVCpu, GCPhys);
330 }
331 else
332 {
333 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
334 hmPokeCpuForTlbFlush(pVCpu, true /*fAccountFlushStat*/);
335 }
336 }
337 return VINF_SUCCESS;
338 }
339
340 /* AMD-V doesn't support invalidation with guest physical addresses; see
341 comment in SVMR0InvalidatePhysPage. */
342 Assert(pVM->hm.s.svm.fSupported);
343#else
344 NOREF(GCPhys);
345#endif
346
347 HMFlushTLBOnAllVCpus(pVM);
348 return VINF_SUCCESS;
349}
350
351/**
352 * Checks if an interrupt event is currently pending.
353 *
354 * @returns Interrupt event pending state.
355 * @param pVM Pointer to the VM.
356 */
357VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM)
358{
359 PVMCPU pVCpu = VMMGetCpu(pVM);
360 return !!pVCpu->hm.s.Event.fPending;
361}
362
363
364/**
365 * Return the PAE PDPE entries.
366 *
367 * @returns Pointer to the PAE PDPE array.
368 * @param pVCpu Pointer to the VMCPU.
369 */
370VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu)
371{
372 return &pVCpu->hm.s.aPdpes[0];
373}
374
375
376/**
377 * Checks if the current AMD CPU is subject to erratum 170 "In SVM mode,
378 * incorrect code bytes may be fetched after a world-switch".
379 *
380 * @param pu32Family Where to store the CPU family (can be NULL).
381 * @param pu32Model Where to store the CPU model (can be NULL).
382 * @param pu32Stepping Where to store the CPU stepping (can be NULL).
383 * @returns true if the erratum applies, false otherwise.
384 */
385VMM_INT_DECL(int) HMAmdIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping)
386{
387 /*
388 * Erratum 170 which requires a forced TLB flush for each world switch:
389 * See AMD spec. "Revision Guide for AMD NPT Family 0Fh Processors".
390 *
391 * All BH-G1/2 and DH-G1/2 models include a fix:
392 * Athlon X2: 0x6b 1/2
393 * 0x68 1/2
394 * Athlon 64: 0x7f 1
395 * 0x6f 2
396 * Sempron: 0x7f 1/2
397 * 0x6f 2
398 * 0x6c 2
399 * 0x7c 2
400 * Turion 64: 0x68 2
401 */
402 uint32_t u32Dummy;
403 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
404 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
405 u32BaseFamily = (u32Version >> 8) & 0xf;
406 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
407 u32Model = ((u32Version >> 4) & 0xf);
408 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
409 u32Stepping = u32Version & 0xf;
410
411 bool fErratumApplies = false;
412 if ( u32Family == 0xf
413 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
414 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
415 {
416 fErratumApplies = true;
417 }
418
419 if (pu32Family)
420 *pu32Family = u32Family;
421 if (pu32Model)
422 *pu32Model = u32Model;
423 if (pu32Stepping)
424 *pu32Stepping = u32Stepping;
425
426 return fErratumApplies;
427}
428
429
430/**
431 * Sets or clears the single instruction flag.
432 *
433 * When set, HM will try its best to return to ring-3 after executing a single
434 * instruction. This can be used for debugging. See also
435 * EMR3HmSingleInstruction.
436 *
437 * @returns The old flag state.
438 * @param pVCpu Pointer to the cross context CPU structure of
439 * the calling EMT.
440 * @param fEnable The new flag state.
441 */
442VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable)
443{
444 VMCPU_ASSERT_EMT(pVCpu);
445 bool fOld = pVCpu->hm.s.fSingleInstruction;
446 pVCpu->hm.s.fSingleInstruction = fEnable;
447 return fOld;
448}
449
450
451/**
452 * Patches the instructions necessary for making a hypercall to the hypervisor.
453 * Used by GIM.
454 *
455 * @returns VBox status code.
456 * @param pVM Pointer to the VM.
457 * @param pvBuf The buffer in the hypercall page(s) to be patched.
458 * @param cbBuf The size of the buffer.
459 * @param pcbWritten Where to store the number of bytes patched. This
460 * is reliably updated only when this function returns
461 * VINF_SUCCESS.
462 */
463VMM_INT_DECL(int) HMPatchHypercall(PVM pVM, void *pvBuf, size_t cbBuf, size_t *pcbWritten)
464{
465 AssertReturn(pvBuf, VERR_INVALID_POINTER);
466 AssertReturn(pcbWritten, VERR_INVALID_POINTER);
467 AssertReturn(HMIsEnabled(pVM), VERR_HM_IPE_5);
468
469 if (pVM->hm.s.vmx.fSupported)
470 {
471 uint8_t abHypercall[] = { 0x0F, 0x01, 0xC1 }; /* VMCALL */
472 if (RT_LIKELY(cbBuf >= sizeof(abHypercall)))
473 {
474 memcpy(pvBuf, abHypercall, sizeof(abHypercall));
475 *pcbWritten = sizeof(abHypercall);
476 return VINF_SUCCESS;
477 }
478 return VERR_BUFFER_OVERFLOW;
479 }
480 else
481 {
482 Assert(pVM->hm.s.svm.fSupported);
483 uint8_t abHypercall[] = { 0x0F, 0x01, 0xD9 }; /* VMMCALL */
484 if (RT_LIKELY(cbBuf >= sizeof(abHypercall)))
485 {
486 memcpy(pvBuf, abHypercall, sizeof(abHypercall));
487 *pcbWritten = sizeof(abHypercall);
488 return VINF_SUCCESS;
489 }
490 return VERR_BUFFER_OVERFLOW;
491 }
492}
493
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