VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllKvm.cpp@ 96407

Last change on this file since 96407 was 96407, checked in by vboxsync, 2 years ago

scm copyright and license note update
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 14.5 KB
Line 
1/* $Id: GIMAllKvm.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * GIM - Guest Interface Manager, KVM, All Contexts.
4 */
5
6/*
7 * Copyright (C) 2015-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_GIM
33#include <VBox/vmm/gim.h>
34#include <VBox/vmm/hm.h>
35#include <VBox/vmm/em.h>
36#include <VBox/vmm/tm.h>
37#include <VBox/vmm/pgm.h>
38#include <VBox/vmm/pdmdev.h>
39#include <VBox/vmm/pdmapi.h>
40#include "GIMKvmInternal.h"
41#include "GIMInternal.h"
42#include <VBox/vmm/vmcc.h>
43
44#include <VBox/dis.h>
45#include <VBox/err.h>
46#include <VBox/sup.h>
47
48#include <iprt/time.h>
49
50
51/**
52 * Handles the KVM hypercall.
53 *
54 * @returns Strict VBox status code.
55 * @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
56 * failed).
57 * @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
58 * @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
59 *
60 * @param pVCpu The cross context virtual CPU structure.
61 * @param pCtx Pointer to the guest-CPU context.
62 *
63 * @thread EMT(pVCpu).
64 */
65VMM_INT_DECL(VBOXSTRICTRC) gimKvmHypercall(PVMCPUCC pVCpu, PCPUMCTX pCtx)
66{
67 VMCPU_ASSERT_EMT(pVCpu);
68
69 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
70 STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
71
72 /*
73 * Get the hypercall operation and arguments.
74 */
75 bool const fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
76 uint64_t uHyperOp = pCtx->rax;
77 uint64_t uHyperArg0 = pCtx->rbx;
78 uint64_t uHyperArg1 = pCtx->rcx;
79 uint64_t uHyperArg2 = pCtx->rdi;
80 uint64_t uHyperArg3 = pCtx->rsi;
81 uint64_t uHyperRet = KVM_HYPERCALL_RET_ENOSYS;
82 uint64_t uAndMask = UINT64_C(0xffffffffffffffff);
83 if (!fIs64BitMode)
84 {
85 uAndMask = UINT64_C(0xffffffff);
86 uHyperOp &= UINT64_C(0xffffffff);
87 uHyperArg0 &= UINT64_C(0xffffffff);
88 uHyperArg1 &= UINT64_C(0xffffffff);
89 uHyperArg2 &= UINT64_C(0xffffffff);
90 uHyperArg3 &= UINT64_C(0xffffffff);
91 uHyperRet &= UINT64_C(0xffffffff);
92 }
93
94 /*
95 * Verify that guest ring-0 is the one making the hypercall.
96 */
97 uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
98 if (RT_UNLIKELY(uCpl))
99 {
100 pCtx->rax = KVM_HYPERCALL_RET_EPERM & uAndMask;
101 return VERR_GIM_HYPERCALL_ACCESS_DENIED;
102 }
103
104 /*
105 * Do the work.
106 */
107 int rc = VINF_SUCCESS;
108 switch (uHyperOp)
109 {
110 case KVM_HYPERCALL_OP_KICK_CPU:
111 {
112 if (uHyperArg1 < pVM->cCpus)
113 {
114 PVMCPUCC pVCpuDst = VMCC_GET_CPU(pVM, uHyperArg1); /* ASSUMES pVCpu index == ApicId of the VCPU. */
115 EMUnhaltAndWakeUp(pVM, pVCpuDst);
116 uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
117 }
118 else
119 {
120 /* Shouldn't ever happen! If it does, throw a guru, as otherwise it'll lead to deadlocks in the guest anyway! */
121 rc = VERR_GIM_HYPERCALL_FAILED;
122 }
123 break;
124 }
125
126 case KVM_HYPERCALL_OP_VAPIC_POLL_IRQ:
127 uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
128 break;
129
130 default:
131 break;
132 }
133
134 /*
135 * Place the result in rax/eax.
136 */
137 pCtx->rax = uHyperRet & uAndMask;
138 return rc;
139}
140
141
142/**
143 * Returns whether the guest has configured and enabled the use of KVM's
144 * hypercall interface.
145 *
146 * @returns true if hypercalls are enabled, false otherwise.
147 * @param pVCpu The cross context virtual CPU structure.
148 */
149VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu)
150{
151 NOREF(pVCpu);
152 /* KVM paravirt interface doesn't have hypercall control bits (like Hyper-V does)
153 that guests can control, i.e. hypercalls are always enabled. */
154 return true;
155}
156
157
158/**
159 * Returns whether the guest has configured and enabled the use of KVM's
160 * paravirtualized TSC.
161 *
162 * @returns true if paravirt. TSC is enabled, false otherwise.
163 * @param pVM The cross context VM structure.
164 */
165VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVMCC pVM)
166{
167 uint32_t const cCpus = pVM->cCpus;
168 for (uint32_t idCpu = 0; idCpu < cCpus; idCpu++)
169 {
170 PVMCPUCC pVCpu = pVM->CTX_SUFF(apCpus)[idCpu];
171 PGIMKVMCPU pGimKvmCpu = &pVCpu->gim.s.u.KvmCpu;
172 if (MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pGimKvmCpu->u64SystemTimeMsr))
173 return true;
174 }
175 return false;
176}
177
178
179/**
180 * MSR read handler for KVM.
181 *
182 * @returns Strict VBox status code like CPUMQueryGuestMsr().
183 * @retval VINF_CPUM_R3_MSR_READ
184 * @retval VERR_CPUM_RAISE_GP_0
185 *
186 * @param pVCpu The cross context virtual CPU structure.
187 * @param idMsr The MSR being read.
188 * @param pRange The range this MSR belongs to.
189 * @param puValue Where to store the MSR value read.
190 */
191VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
192{
193 NOREF(pRange);
194 PVM pVM = pVCpu->CTX_SUFF(pVM);
195 PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
196 PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
197
198 switch (idMsr)
199 {
200 case MSR_GIM_KVM_SYSTEM_TIME:
201 case MSR_GIM_KVM_SYSTEM_TIME_OLD:
202 *puValue = pKvmCpu->u64SystemTimeMsr;
203 return VINF_SUCCESS;
204
205 case MSR_GIM_KVM_WALL_CLOCK:
206 case MSR_GIM_KVM_WALL_CLOCK_OLD:
207 *puValue = pKvm->u64WallClockMsr;
208 return VINF_SUCCESS;
209
210 default:
211 {
212#ifdef IN_RING3
213 static uint32_t s_cTimes = 0;
214 if (s_cTimes++ < 20)
215 LogRel(("GIM: KVM: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
216#endif
217 LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
218 break;
219 }
220 }
221
222 return VERR_CPUM_RAISE_GP_0;
223}
224
225
226/**
227 * MSR write handler for KVM.
228 *
229 * @returns Strict VBox status code like CPUMSetGuestMsr().
230 * @retval VINF_CPUM_R3_MSR_WRITE
231 * @retval VERR_CPUM_RAISE_GP_0
232 *
233 * @param pVCpu The cross context virtual CPU structure.
234 * @param idMsr The MSR being written.
235 * @param pRange The range this MSR belongs to.
236 * @param uRawValue The raw value with the ignored bits not masked.
237 */
238VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
239{
240 NOREF(pRange);
241 switch (idMsr)
242 {
243 case MSR_GIM_KVM_SYSTEM_TIME:
244 case MSR_GIM_KVM_SYSTEM_TIME_OLD:
245 {
246#ifndef IN_RING3
247 RT_NOREF2(pVCpu, uRawValue);
248 return VINF_CPUM_R3_MSR_WRITE;
249#else
250 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
251 PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
252 if (uRawValue & MSR_GIM_KVM_SYSTEM_TIME_ENABLE_BIT)
253 gimR3KvmEnableSystemTime(pVM, pVCpu, uRawValue);
254 else
255 gimR3KvmDisableSystemTime(pVM);
256
257 pKvmCpu->u64SystemTimeMsr = uRawValue;
258 return VINF_SUCCESS;
259#endif /* IN_RING3 */
260 }
261
262 case MSR_GIM_KVM_WALL_CLOCK:
263 case MSR_GIM_KVM_WALL_CLOCK_OLD:
264 {
265#ifndef IN_RING3
266 RT_NOREF2(pVCpu, uRawValue);
267 return VINF_CPUM_R3_MSR_WRITE;
268#else
269 /* Enable the wall-clock struct. */
270 RTGCPHYS GCPhysWallClock = MSR_GIM_KVM_WALL_CLOCK_GUEST_GPA(uRawValue);
271 if (RT_LIKELY(RT_ALIGN_64(GCPhysWallClock, 4) == GCPhysWallClock))
272 {
273 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
274 int rc = gimR3KvmEnableWallClock(pVM, GCPhysWallClock);
275 if (RT_SUCCESS(rc))
276 {
277 PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
278 pKvm->u64WallClockMsr = uRawValue;
279 return VINF_SUCCESS;
280 }
281 }
282 return VERR_CPUM_RAISE_GP_0;
283#endif /* IN_RING3 */
284 }
285
286 default:
287 {
288#ifdef IN_RING3
289 static uint32_t s_cTimes = 0;
290 if (s_cTimes++ < 20)
291 LogRel(("GIM: KVM: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
292 uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
293#endif
294 LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
295 break;
296 }
297 }
298
299 return VERR_CPUM_RAISE_GP_0;
300}
301
302
303/**
304 * Whether we need to trap \#UD exceptions in the guest.
305 *
306 * On AMD-V we need to trap them because paravirtualized Linux/KVM guests use
307 * the Intel VMCALL instruction to make hypercalls and we need to trap and
308 * optionally patch them to the AMD-V VMMCALL instruction and handle the
309 * hypercall.
310 *
311 * I guess this was done so that guest teleporation between an AMD and an Intel
312 * machine would working without any changes at the time of teleporation.
313 * However, this also means we -always- need to intercept \#UD exceptions on one
314 * of the two CPU models (Intel or AMD). Hyper-V solves this problem more
315 * elegantly by letting the hypervisor supply an opaque hypercall page.
316 *
317 * For raw-mode VMs, this function will always return true. See gimR3KvmInit().
318 *
319 * @param pVM The cross context VM structure.
320 */
321VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVM pVM)
322{
323 return pVM->gim.s.u.Kvm.fTrapXcptUD;
324}
325
326
327/**
328 * Checks the instruction and executes the hypercall if it's a valid hypercall
329 * instruction.
330 *
331 * This interface is used by \#UD handlers and IEM.
332 *
333 * @returns Strict VBox status code.
334 * @param pVCpu The cross context virtual CPU structure.
335 * @param pCtx Pointer to the guest-CPU context.
336 * @param uDisOpcode The disassembler opcode.
337 * @param cbInstr The instruction length.
338 *
339 * @thread EMT(pVCpu).
340 */
341VMM_INT_DECL(VBOXSTRICTRC) gimKvmHypercallEx(PVMCPUCC pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr)
342{
343 Assert(pVCpu);
344 Assert(pCtx);
345 VMCPU_ASSERT_EMT(pVCpu);
346
347 /*
348 * If the instruction at RIP is the Intel VMCALL instruction or
349 * the AMD VMMCALL instruction handle it as a hypercall.
350 *
351 * Linux/KVM guests always uses the Intel VMCALL instruction but we patch
352 * it to the host-native one whenever we encounter it so subsequent calls
353 * will not require disassembly (when coming from HM).
354 */
355 if ( uDisOpcode == OP_VMCALL
356 || uDisOpcode == OP_VMMCALL)
357 {
358 /*
359 * Perform the hypercall.
360 *
361 * For HM, we can simply resume guest execution without performing the hypercall now and
362 * do it on the next VMCALL/VMMCALL exit handler on the patched instruction.
363 *
364 * For raw-mode we need to do this now anyway. So we do it here regardless with an added
365 * advantage is that it saves one world-switch for the HM case.
366 */
367 VBOXSTRICTRC rcStrict = gimKvmHypercall(pVCpu, pCtx);
368 if (rcStrict == VINF_SUCCESS)
369 {
370 /*
371 * Patch the instruction to so we don't have to spend time disassembling it each time.
372 * Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
373 */
374 PVM pVM = pVCpu->CTX_SUFF(pVM);
375 PCGIMKVM pKvm = &pVM->gim.s.u.Kvm;
376 if ( uDisOpcode != pKvm->uOpcodeNative
377 && cbInstr == sizeof(pKvm->abOpcodeNative) )
378 {
379 /** @todo r=ramshankar: we probably should be doing this in an
380 * EMT rendezvous. */
381 /** @todo Add stats for patching. */
382 int rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, pKvm->abOpcodeNative, sizeof(pKvm->abOpcodeNative));
383 AssertRC(rc);
384 }
385 }
386 else
387 {
388 /* The KVM provider doesn't have any concept of continuing hypercalls. */
389 Assert(rcStrict != VINF_GIM_HYPERCALL_CONTINUING);
390#ifdef IN_RING3
391 Assert(rcStrict != VINF_GIM_R3_HYPERCALL);
392#endif
393 }
394 return rcStrict;
395 }
396
397 return VERR_GIM_INVALID_HYPERCALL_INSTR;
398}
399
400
401/**
402 * Exception handler for \#UD.
403 *
404 * @returns Strict VBox status code.
405 * @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
406 * failed).
407 * @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
408 * @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
409 * @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
410 * hypercall instruction.
411 *
412 * @param pVM The cross context VM structure.
413 * @param pVCpu The cross context virtual CPU structure.
414 * @param pCtx Pointer to the guest-CPU context.
415 * @param pDis Pointer to the disassembled instruction state at RIP.
416 * Optional, can be NULL.
417 * @param pcbInstr Where to store the instruction length of the hypercall
418 * instruction. Optional, can be NULL.
419 *
420 * @thread EMT(pVCpu).
421 */
422VMM_INT_DECL(VBOXSTRICTRC) gimKvmXcptUD(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
423{
424 VMCPU_ASSERT_EMT(pVCpu);
425
426 /*
427 * If we didn't ask for #UD to be trapped, bail.
428 */
429 if (RT_UNLIKELY(!pVM->gim.s.u.Kvm.fTrapXcptUD))
430 return VERR_GIM_IPE_3;
431
432 if (!pDis)
433 {
434 unsigned cbInstr;
435 DISCPUSTATE Dis;
436 int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbInstr);
437 if (RT_SUCCESS(rc))
438 {
439 if (pcbInstr)
440 *pcbInstr = (uint8_t)cbInstr;
441 return gimKvmHypercallEx(pVCpu, pCtx, Dis.pCurInstr->uOpcode, Dis.cbInstr);
442 }
443
444 Log(("GIM: KVM: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
445 return rc;
446 }
447
448 return gimKvmHypercallEx(pVCpu, pCtx, pDis->pCurInstr->uOpcode, pDis->cbInstr);
449}
450
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette