GIMAllHv.cpp@ 59899

Last change on this file since 59899 was 59899, checked in by vboxsync, 9 years ago
GIM/Hyper: Fix missing return code in read MSR.
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1	/* $Id: GIMAllHv.cpp 59899 2016-03-02 13:34:10Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include "GIMHvInternal.h"
24	#include "GIMInternal.h"
25
26	#include <iprt/asm-amd64-x86.h>
27	#ifdef IN_RING3
28	# include <iprt/mem.h>
29	#endif
30
31	#include <VBox/err.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/hm.h>
34	#include <VBox/vmm/tm.h>
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/pdmdev.h>
38	#include <VBox/vmm/pdmapi.h>
39
40
41	#ifdef IN_RING3
42	/**
43	* Read and validate slow hypercall parameters.
44	*
45	* @returns VBox status code.
46	* @param pVM The cross context VM structure.
47	* @param pCtx Pointer to the guest-CPU context.
48	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
49	* @param enmParam The hypercall parameter type.
50	* @param prcHv Where to store the Hyper-V status code. Only valid
51	* to the caller when this function returns
52	* VINF_SUCCESS.
53	*/
54	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
55	{
56	int rc = VINF_SUCCESS;
57	PGIMHV pHv = &pVM->gim.s.u.Hv;
58	RTGCPHYS GCPhysParam;
59	void *pvDst;
60	if (enmParam == GIMHVHYPERCALLPARAM_IN)
61	{
62	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
63	pvDst = pHv->pbHypercallIn;
64	pHv->GCPhysHypercallIn = GCPhysParam;
65	}
66	else
67	{
68	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
69	pvDst = pHv->pbHypercallOut;
70	pHv->GCPhysHypercallOut = GCPhysParam;
71	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
72	}
73
74	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
75	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
76	{
77	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
78	{
79	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
80	if (RT_SUCCESS(rc))
81	{
82	*prcHv = GIM_HV_STATUS_SUCCESS;
83	return VINF_SUCCESS;
84	}
85	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
86	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
87	}
88	else
89	{
90	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
91	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
92	}
93	}
94	else
95	{
96	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
97	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
98	}
99	return rc;
100	}
101
102
103	/**
104	* Helper for reading and validating slow hypercall input and output parameters.
105	*
106	* @returns VBox status code.
107	* @param pVM The cross context VM structure.
108	* @param pCtx Pointer to the guest-CPU context.
109	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
110	* @param prcHv Where to store the Hyper-V status code. Only valid
111	* to the caller when this function returns
112	* VINF_SUCCESS.
113	*/
114	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
115	{
116	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
117	if ( RT_SUCCESS(rc)
118	&& *prcHv == GIM_HV_STATUS_SUCCESS)
119	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
120	return rc;
121	}
122	#endif
123
124
125	/**
126	* Handles all Hyper-V hypercalls.
127	*
128	* @returns VBox status code.
129	* @param pVCpu The cross context virtual CPU structure.
130	* @param pCtx Pointer to the guest-CPU context.
131	*
132	* @thread EMT.
133	*/
134	VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
135	{
136	#ifndef IN_RING3
137	return VINF_GIM_R3_HYPERCALL;
138	#else
139	PVM pVM = pVCpu->CTX_SUFF(pVM);
140
141	/*
142	* Verify that hypercalls are enabled.
143	*/
144	if (!gimHvAreHypercallsEnabled(pVCpu))
145	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
146
147	/*
148	* Verify guest is in ring-0 protected mode.
149	*/
150	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
151	if ( uCpl
152	\|\| CPUMIsGuestInRealModeEx(pCtx))
153	{
154	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
155	}
156
157	/*
158	* Get the hypercall operation code and modes.
159	*/
160	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
161	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
162	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
163	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
164	const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn);
165	const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn);
166	uint64_t cHyperRepsDone = 0;
167
168	int rc = VINF_SUCCESS;
169	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
170	PGIMHV pHv = &pVM->gim.s.u.Hv;
171
172	/*
173	* Validate common hypercall input parameters.
174	*/
175	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
176	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
177	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
178	{
179	/*
180	* Perform the hypercall.
181	*/
182	switch (uHyperOp)
183	{
184	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
185	{
186	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
187	{
188	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
189	if ( RT_SUCCESS(rc)
190	&& rcHv == GIM_HV_STATUS_SUCCESS)
191	{
192	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
193	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
194	if (RT_FAILURE(rc))
195	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
196	}
197	}
198	else
199	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
200	break;
201	}
202
203	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
204	{
205	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
206	{
207	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
208	if ( RT_SUCCESS(rc)
209	&& rcHv == GIM_HV_STATUS_SUCCESS)
210	{
211	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
212	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
213	if (RT_FAILURE(rc))
214	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
215	}
216	}
217	else
218	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
219	break;
220	}
221
222	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
223	{
224	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
225	{
226	uint32_t fFlags = 0;
227	if (!fHyperFast)
228	{
229	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
230	if ( RT_SUCCESS(rc)
231	&& rcHv == GIM_HV_STATUS_SUCCESS)
232	{
233	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
234	fFlags = pIn->fFlags;
235	}
236	}
237	else
238	{
239	rcHv = GIM_HV_STATUS_SUCCESS;
240	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
241	}
242
243	/*
244	* Nothing to flush on the sending side as we don't maintain our own buffers.
245	*/
246	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
247	if (rcHv == GIM_HV_STATUS_SUCCESS)
248	{
249	if (fFlags)
250	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
251	else
252	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
253	}
254	}
255	else
256	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
257	break;
258	}
259
260	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
261	{
262	if (pHv->fIsInterfaceVs)
263	{
264	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
265	if ( RT_SUCCESS(rc)
266	&& rcHv == GIM_HV_STATUS_SUCCESS)
267	{
268	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
269	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
270	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
271	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
272	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->uSint2Msr)
273	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
274	{
275	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
276	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
277	{
278	/*
279	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
280	*/
281	GIMHVMSG HvMsg;
282	RT_ZERO(HvMsg);
283	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
284	HvMsg.MsgHdr.cbPayload = 0xf;
285	HvMsg.aPayload[0] = 0xf;
286	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
287	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
288	if (RT_SUCCESS(rc2))
289	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
290	else
291	{
292	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
293	offMsg, rc));
294	}
295	}
296	}
297
298	/*
299	* Make the call fail after updating the SIMP, so the guest can go back to using
300	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
301	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
302	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
303	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
304	*/
305	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
306	}
307	else
308	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
309	}
310	else
311	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
312	break;
313	}
314
315	default:
316	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
317	break;
318	}
319	}
320	else
321	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
322
323	/*
324	* Update the guest with results of the hypercall.
325	*/
326	if (RT_SUCCESS(rc))
327	{
328	if (fIs64BitMode)
329	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
330	else
331	{
332	pCtx->edx = cHyperRepsDone;
333	pCtx->eax = rcHv;
334	}
335	}
336
337	return rc;
338	#endif
339	}
340
341
342	/**
343	* Returns whether the guest has configured and enabled the use of Hyper-V's
344	* hypercall interface.
345	*
346	* @returns true if hypercalls are enabled, false otherwise.
347	* @param pVCpu The cross context virtual CPU structure.
348	*/
349	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
350	{
351	return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
352	}
353
354
355	/**
356	* Returns whether the guest has configured and enabled the use of Hyper-V's
357	* paravirtualized TSC.
358	*
359	* @returns true if paravirt. TSC is enabled, false otherwise.
360	* @param pVM The cross context VM structure.
361	*/
362	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
363	{
364	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
365	}
366
367
368	#ifdef IN_RING3
369	/**
370	* Gets the descriptive OS ID variant as identified via the
371	* MSR_GIM_HV_GUEST_OS_ID MSR.
372	*
373	* @returns The name.
374	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
375	*/
376	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
377	{
378	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
379	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
380	if (uVendor == 1 /* Microsoft */)
381	{
382	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
383	switch (uOsVariant)
384	{
385	case 0: return "Undefined";
386	case 1: return "MS-DOS";
387	case 2: return "Windows 3.x";
388	case 3: return "Windows 9x";
389	case 4: return "Windows NT or derivative";
390	case 5: return "Windows CE";
391	default: return "Unknown";
392	}
393	}
394	return "Unknown";
395	}
396	#endif
397
398
399	/**
400	* MSR read handler for Hyper-V.
401	*
402	* @returns Strict VBox status code like CPUMQueryGuestMsr().
403	* @retval VINF_CPUM_R3_MSR_READ
404	* @retval VERR_CPUM_RAISE_GP_0
405	*
406	* @param pVCpu The cross context virtual CPU structure.
407	* @param idMsr The MSR being read.
408	* @param pRange The range this MSR belongs to.
409	* @param puValue Where to store the MSR value read.
410	*
411	* @thread EMT.
412	*/
413	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
414	{
415	NOREF(pRange);
416	PVM pVM = pVCpu->CTX_SUFF(pVM);
417	PGIMHV pHv = &pVM->gim.s.u.Hv;
418
419	switch (idMsr)
420	{
421	case MSR_GIM_HV_TIME_REF_COUNT:
422	{
423	/* Hyper-V reports the time in 100 ns units (10 MHz). */
424	uint64_t u64Tsc = TMCpuTickGet(pVCpu);
425	uint64_t u64TscHz = pHv->cTscTicksPerSecond;
426	uint64_t u64Tsc100Ns = u64TscHz / UINT64_C(10000000); /* 100 ns */
427	*puValue = (u64Tsc / u64Tsc100Ns);
428	return VINF_SUCCESS;
429	}
430
431	case MSR_GIM_HV_VP_INDEX:
432	*puValue = pVCpu->idCpu;
433	return VINF_SUCCESS;
434
435	case MSR_GIM_HV_TPR:
436	return PDMApicReadMSR(pVM, pVCpu->idCpu, MSR_IA32_X2APIC_TPR, puValue);
437
438	case MSR_GIM_HV_EOI:
439	return PDMApicReadMSR(pVM, pVCpu->idCpu, MSR_IA32_X2APIC_EOI, puValue);
440
441	case MSR_GIM_HV_ICR:
442	return PDMApicReadMSR(pVM, pVCpu->idCpu, MSR_IA32_X2APIC_ICR, puValue);
443
444	case MSR_GIM_HV_GUEST_OS_ID:
445	*puValue = pHv->u64GuestOsIdMsr;
446	return VINF_SUCCESS;
447
448	case MSR_GIM_HV_HYPERCALL:
449	*puValue = pHv->u64HypercallMsr;
450	return VINF_SUCCESS;
451
452	case MSR_GIM_HV_REF_TSC:
453	*puValue = pHv->u64TscPageMsr;
454	return VINF_SUCCESS;
455
456	case MSR_GIM_HV_TSC_FREQ:
457	*puValue = TMCpuTicksPerSecond(pVM);
458	return VINF_SUCCESS;
459
460	case MSR_GIM_HV_APIC_FREQ:
461	{
462	int rc = PDMApicGetTimerFreq(pVM, puValue);
463	if (RT_FAILURE(rc))
464	return VERR_CPUM_RAISE_GP_0;
465	return VINF_SUCCESS;
466	}
467
468	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
469	*puValue = pHv->uDbgStatusMsr;
470	return VINF_SUCCESS;
471
472	case MSR_GIM_HV_SINT2:
473	{
474	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
475	*puValue = pHvCpu->uSint2Msr;
476	return VINF_SUCCESS;
477	}
478
479	case MSR_GIM_HV_SIMP:
480	{
481	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
482	*puValue = pHvCpu->uSimpMsr;
483	return VINF_SUCCESS;
484	}
485
486	case MSR_GIM_HV_RESET:
487	*puValue = 0;
488	return VINF_SUCCESS;
489
490	case MSR_GIM_HV_CRASH_CTL:
491	*puValue = pHv->uCrashCtlMsr;
492	return VINF_SUCCESS;
493
494	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
495	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
496	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
497	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
498	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
499
500	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
501	{
502	if (pHv->fIsVendorMsHv)
503	{
504	#ifndef IN_RING3
505	return VINF_CPUM_R3_MSR_READ;
506	#else
507	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
508	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
509	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
510	return VINF_SUCCESS;
511	#endif
512	}
513	return VERR_CPUM_RAISE_GP_0;
514	}
515
516	default:
517	{
518	#ifdef IN_RING3
519	static uint32_t s_cTimes = 0;
520	if (s_cTimes++ < 20)
521	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
522	#else
523	return VINF_CPUM_R3_MSR_READ;
524	#endif
525	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
526	break;
527	}
528	}
529
530	return VERR_CPUM_RAISE_GP_0;
531	}
532
533
534	/**
535	* MSR write handler for Hyper-V.
536	*
537	* @returns Strict VBox status code like CPUMSetGuestMsr().
538	* @retval VINF_CPUM_R3_MSR_WRITE
539	* @retval VERR_CPUM_RAISE_GP_0
540	*
541	* @param pVCpu The cross context virtual CPU structure.
542	* @param idMsr The MSR being written.
543	* @param pRange The range this MSR belongs to.
544	* @param uRawValue The raw value with the ignored bits not masked.
545	*
546	* @thread EMT.
547	*/
548	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
549	{
550	NOREF(pRange);
551	PVM pVM = pVCpu->CTX_SUFF(pVM);
552	PGIMHV pHv = &pVM->gim.s.u.Hv;
553
554	switch (idMsr)
555	{
556	case MSR_GIM_HV_TPR:
557	return PDMApicWriteMSR(pVM, pVCpu->idCpu, MSR_IA32_X2APIC_TPR, uRawValue);
558
559	case MSR_GIM_HV_EOI:
560	return PDMApicWriteMSR(pVM, pVCpu->idCpu, MSR_IA32_X2APIC_EOI, uRawValue);
561
562	case MSR_GIM_HV_ICR:
563	return PDMApicWriteMSR(pVM, pVCpu->idCpu, MSR_IA32_X2APIC_ICR, uRawValue);
564
565	case MSR_GIM_HV_GUEST_OS_ID:
566	{
567	#ifndef IN_RING3
568	return VINF_CPUM_R3_MSR_WRITE;
569	#else
570	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
571	if (!uRawValue)
572	{
573	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
574	{
575	gimR3HvDisableHypercallPage(pVM);
576	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT;
577	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
578	}
579	}
580	else
581	{
582	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
583	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
584	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
585	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
586	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
587	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
588
589	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
590	CPUMCPUIDLEAF HyperLeaf;
591	RT_ZERO(HyperLeaf);
592	HyperLeaf.uLeaf = UINT32_C(0x40000002);
593	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
594	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
595	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
596	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
597	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
598	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
599	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
600	AssertRC(rc2);
601	}
602
603	pHv->u64GuestOsIdMsr = uRawValue;
604
605	/*
606	* Notify VMM that hypercalls are now disabled/enabled.
607	*/
608	for (VMCPUID i = 0; i < pVM->cCpus; i++)
609	{
610	if (uRawValue)
611	VMMHypercallsEnable(&pVM->aCpus[i]);
612	else
613	VMMHypercallsDisable(&pVM->aCpus[i]);
614	}
615
616	return VINF_SUCCESS;
617	#endif /* IN_RING3 */
618	}
619
620	case MSR_GIM_HV_HYPERCALL:
621	{
622	#ifndef IN_RING3
623	return VINF_CPUM_R3_MSR_WRITE;
624	#else
625	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
626	* see @bugref{7270#c116}. */
627	/* First, update all but the hypercall page enable bit. */
628	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);
629
630	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
631	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);
632	if ( fEnable
633	&& !gimHvAreHypercallsEnabled(pVCpu))
634	{
635	return VINF_SUCCESS;
636	}
637
638	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
639	if (!fEnable)
640	{
641	gimR3HvDisableHypercallPage(pVM);
642	pHv->u64HypercallMsr = uRawValue;
643	return VINF_SUCCESS;
644	}
645
646	/* Enable the hypercall-page. */
647	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
648	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
649	if (RT_SUCCESS(rc))
650	{
651	pHv->u64HypercallMsr = uRawValue;
652	return VINF_SUCCESS;
653	}
654
655	return VERR_CPUM_RAISE_GP_0;
656	#endif
657	}
658
659	case MSR_GIM_HV_REF_TSC:
660	{
661	#ifndef IN_RING3
662	return VINF_CPUM_R3_MSR_WRITE;
663	#else /* IN_RING3 */
664	/* First, update all but the TSC-page enable bit. */
665	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE_BIT);
666
667	/* Is the guest disabling the TSC-page? */
668	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_REF_TSC_ENABLE_BIT);
669	if (!fEnable)
670	{
671	gimR3HvDisableTscPage(pVM);
672	pHv->u64TscPageMsr = uRawValue;
673	return VINF_SUCCESS;
674	}
675
676	/* Enable the TSC-page. */
677	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
678	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
679	if (RT_SUCCESS(rc))
680	{
681	pHv->u64TscPageMsr = uRawValue;
682	return VINF_SUCCESS;
683	}
684
685	return VERR_CPUM_RAISE_GP_0;
686	#endif /* IN_RING3 */
687	}
688
689	case MSR_GIM_HV_RESET:
690	{
691	#ifndef IN_RING3
692	return VINF_CPUM_R3_MSR_WRITE;
693	#else
694	if (MSR_GIM_HV_RESET_IS_SET(uRawValue))
695	{
696	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
697	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3);
698	AssertRC(rc);
699	}
700	/* else: Ignore writes to other bits. */
701	return VINF_SUCCESS;
702	#endif /* IN_RING3 */
703	}
704
705	case MSR_GIM_HV_CRASH_CTL:
706	{
707	#ifndef IN_RING3
708	return VINF_CPUM_R3_MSR_WRITE;
709	#else
710	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY_BIT)
711	{
712	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
713	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
714	}
715	return VINF_SUCCESS;
716	#endif
717	}
718
719	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
720	{
721	if (!pHv->fDbgEnabled)
722	return VERR_CPUM_RAISE_GP_0;
723	#ifndef IN_RING3
724	return VINF_CPUM_R3_MSR_WRITE;
725	#else
726	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
727	pHv->uDbgSendBufferMsr = GCPhysBuffer;
728	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
729	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
730	else
731	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
732	pHv->uDbgSendBufferMsr = uRawValue;
733	return VINF_SUCCESS;
734	#endif
735	}
736
737	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
738	{
739	if (!pHv->fDbgEnabled)
740	return VERR_CPUM_RAISE_GP_0;
741	#ifndef IN_RING3
742	return VINF_CPUM_R3_MSR_WRITE;
743	#else
744	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
745	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
746	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
747	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
748	else
749	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
750	return VINF_SUCCESS;
751	#endif
752	}
753
754	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
755	{
756	if (!pHv->fDbgEnabled)
757	return VERR_CPUM_RAISE_GP_0;
758	#ifndef IN_RING3
759	return VINF_CPUM_R3_MSR_WRITE;
760	#else
761	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
762	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
763	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
764	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
765	else
766	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
767	return VINF_SUCCESS;
768	#endif
769	}
770
771	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
772	{
773	if (!pHv->fDbgEnabled)
774	return VERR_CPUM_RAISE_GP_0;
775	#ifndef IN_RING3
776	return VINF_CPUM_R3_MSR_WRITE;
777	#else
778	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
779	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
780	{
781	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
782	return VERR_CPUM_RAISE_GP_0;
783	}
784
785	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
786	{
787	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
788	if ( cbWrite > 0
789	&& cbWrite < GIM_HV_PAGE_SIZE)
790	{
791	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
792	{
793	Assert(pHv->pvDbgBuffer);
794	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
795	if (RT_SUCCESS(rc))
796	{
797	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
798	uint32_t cbWritten = 0;
799	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
800	if ( RT_SUCCESS(rc)
801	&& cbWrite == cbWritten)
802	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS_BIT;
803	else
804	pHv->uDbgStatusMsr = 0;
805	}
806	else
807	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
808	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
809	}
810	else
811	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
812	(RTGCPHYS)pHv->uDbgSendBufferMsr));
813	}
814	else
815	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
816	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
817	}
818	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
819	{
820	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
821	{
822	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
823	uint32_t cbReallyRead;
824	Assert(pHv->pvDbgBuffer);
825	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, PAGE_SIZE, PAGE_SIZE, &cbReallyRead, 0, false /fUdpPkt/);
826	if ( RT_SUCCESS(rc)
827	&& cbReallyRead > 0)
828	{
829	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
830	if (RT_SUCCESS(rc))
831	{
832	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
833	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS_BIT;
834	}
835	else
836	{
837	pHv->uDbgStatusMsr = 0;
838	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
839	}
840	}
841	else
842	pHv->uDbgStatusMsr = 0;
843	}
844	else
845	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n"));
846	}
847	return VINF_SUCCESS;
848	#endif
849	}
850
851	case MSR_GIM_HV_SINT2:
852	{
853	if (!pHv->fDbgEnabled)
854	return VERR_CPUM_RAISE_GP_0;
855	#ifndef IN_RING3
856	return VINF_CPUM_R3_MSR_WRITE;
857	#else
858	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
859	uint8_t uVector = MSR_GIM_HV_SINT_VECTOR(uRawValue);
860	if ( !MSR_GIM_HV_SINT_IS_MASKED(uRawValue)
861	&& uVector < 16)
862	{
863	LogRel(("GIM: HyperV: Programmed an invalid vector in SINT2, uVector=%u -> #GP(0)\n", uVector));
864	return VERR_CPUM_RAISE_GP_0;
865	}
866
867	pHvCpu->uSint2Msr = uRawValue;
868	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
869	LogRel(("GIM: HyperV: Masked SINT2\n"));
870	else
871	LogRel(("GIM: HyperV: Unmasked SINT2, uVector=%u\n", uVector));
872	return VINF_SUCCESS;
873	#endif
874	}
875
876	case MSR_GIM_HV_SIMP:
877	{
878	if (!pHv->fDbgEnabled)
879	return VERR_CPUM_RAISE_GP_0;
880	#ifndef IN_RING3
881	return VINF_CPUM_R3_MSR_WRITE;
882	#else
883	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
884	pHvCpu->uSimpMsr = uRawValue;
885	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
886	{
887	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
888	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
889	{
890	uint8_t abSimp[PAGE_SIZE];
891	RT_ZERO(abSimp);
892	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
893	if (RT_SUCCESS(rc2))
894	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at %#RGp\n", GCPhysSimp));
895	else
896	{
897	LogRel(("GIM: HyperV: WrMsr on MSR_GIM_HV_SIMP failed to update SIMP at %#RGp rc=%Rrc -> #GP(0)\n",
898	GCPhysSimp, rc2));
899	return VERR_CPUM_RAISE_GP_0;
900	}
901	}
902	else
903	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n",GCPhysSimp));
904	}
905	else
906	LogRel(("GIM: HyperV: Disabled synthetic interrupt message page\n"));
907	return VINF_SUCCESS;
908	#endif
909	}
910
911	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
912	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
913	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
914	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
915	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
916
917	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
918	case MSR_GIM_HV_VP_INDEX:
919	case MSR_GIM_HV_TSC_FREQ:
920	case MSR_GIM_HV_APIC_FREQ:
921	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
922	return VERR_CPUM_RAISE_GP_0;
923
924	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
925	{
926	if (pHv->fIsVendorMsHv)
927	{
928	#ifndef IN_RING3
929	return VINF_CPUM_R3_MSR_WRITE;
930	#else
931	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
932	return VINF_SUCCESS;
933	#endif
934	}
935	return VERR_CPUM_RAISE_GP_0;
936	}
937
938	default:
939	{
940	#ifdef IN_RING3
941	static uint32_t s_cTimes = 0;
942	if (s_cTimes++ < 20)
943	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
944	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
945	#else
946	return VINF_CPUM_R3_MSR_WRITE;
947	#endif
948	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
949	break;
950	}
951	}
952
953	return VERR_CPUM_RAISE_GP_0;
954	}
955
956
957	/**
958	* Whether we need to trap \#UD exceptions in the guest.
959	*
960	* We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
961	* enabled. For HM VMs, the hypercall would be handled via the
962	* VMCALL/VMMCALL VM-exit.
963	*
964	* @param pVCpu The cross context virtual CPU structure.
965	*/
966	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
967	{
968	PVM pVM = pVCpu->CTX_SUFF(pVM);
969	if ( !HMIsEnabled(pVM)
970	&& gimHvAreHypercallsEnabled(pVCpu))
971	return true;
972	return false;
973	}
974
975
976	/**
977	* Exception handler for \#UD.
978	*
979	* @param pVCpu The cross context virtual CPU structure.
980	* @param pCtx Pointer to the guest-CPU context.
981	* @param pDis Pointer to the disassembled instruction state at RIP.
982	* Optional, can be NULL.
983	*
984	* @thread EMT.
985	*/
986	VMM_INT_DECL(int) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
987	{
988	/*
989	* If we didn't ask for #UD to be trapped, bail.
990	*/
991	PVM pVM = pVCpu->CTX_SUFF(pVM);
992	if (!gimHvShouldTrapXcptUD(pVCpu))
993	return VERR_GIM_OPERATION_FAILED;
994
995	int rc = VINF_SUCCESS;
996	if (!pDis)
997	{
998	/*
999	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1000	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1001	*/
1002	DISCPUSTATE Dis;
1003	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL /* pcbInstr */);
1004	pDis = &Dis;
1005	}
1006
1007	if (RT_SUCCESS(rc))
1008	{
1009	CPUMCPUVENDOR enmGuestCpuVendor = CPUMGetGuestCpuVendor(pVM);
1010	if ( ( pDis->pCurInstr->uOpcode == OP_VMCALL
1011	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1012	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA))
1013	\|\| ( pDis->pCurInstr->uOpcode == OP_VMMCALL
1014	&& enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
1015	{
1016	/*
1017	* Make sure guest ring-0 is the one making the hypercall.
1018	*/
1019	if (CPUMGetGuestCPL(pVCpu))
1020	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
1021
1022	/*
1023	* Update RIP and perform the hypercall.
1024	*/
1025	/** @todo pre-incrementing of RIP will break when we implement continuing hypercalls. */
1026	pCtx->rip += pDis->cbInstr;
1027	rc = gimHvHypercall(pVCpu, pCtx);
1028	}
1029	else
1030	rc = VERR_GIM_OPERATION_FAILED;
1031	}
1032	return rc;
1033	}
1034

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 59899

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