1 | /* $Id: GIMAllHv.cpp 58116 2015-10-08 14:51:53Z vboxsync $ */
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2 | /** @file
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3 | * GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2014-2015 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | /*********************************************************************************************************************************
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20 | * Header Files *
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21 | *********************************************************************************************************************************/
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22 | #define LOG_GROUP LOG_GROUP_GIM
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23 | #include "GIMHvInternal.h"
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24 | #include "GIMInternal.h"
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25 |
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26 | #include <iprt/asm-amd64-x86.h>
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27 | #ifdef IN_RING3
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28 | # include <iprt/mem.h>
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29 | #endif
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30 |
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31 | #include <VBox/err.h>
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32 | #include <VBox/vmm/em.h>
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33 | #include <VBox/vmm/hm.h>
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34 | #include <VBox/vmm/tm.h>
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35 | #include <VBox/vmm/vm.h>
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36 | #include <VBox/vmm/pgm.h>
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37 | #include <VBox/vmm/pdmdev.h>
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38 | #include <VBox/vmm/pdmapi.h>
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39 |
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40 |
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41 | #ifdef IN_RING3
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42 | /**
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43 | * Helper for reading and validating slow hypercall input/output parameters.
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44 | *
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45 | * A 'slow' hypercall is one that passes parameters pointers through guest
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46 | * memory as opposed to a 'fast' hypercall which passes parameters through guest
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47 | * general-purpose registers.
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48 | *
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49 | * @returns VBox status code.
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50 | * @param pVM Pointer to the VM.
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51 | * @param pCtx Pointer to the guest-CPU context.
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52 | * @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
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53 | * @param pGCPhysIn Where to store the guest-physical address of the
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54 | * hypercall input page. Optional, can be NULL.
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55 | * @param pGCPhysOut Where to store the guest-physical address of the
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56 | * hypercall output page. Optional, can be NULL.
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57 | * @param prcHv Where to store the Hyper-V status code. Only valid
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58 | * to the caller when this function returns
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59 | * VINF_SUCCESS.
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60 | */
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61 | static int gimHvReadSlowHypercallParams(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, PRTGCPHYS pGCPhysIn, PRTGCPHYS pGCPhysOut,
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62 | int *prcHv)
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63 | {
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64 | int rc = VINF_SUCCESS;
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65 | RTGCPHYS GCPhysIn = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) | pCtx->ecx;
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66 | RTGCPHYS GCPhysOut = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) | pCtx->esi;
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67 | if (pGCPhysIn)
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68 | *pGCPhysIn = GCPhysIn;
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69 | if (pGCPhysOut)
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70 | *pGCPhysOut = GCPhysOut;
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71 | if ( RT_ALIGN_64(GCPhysIn, 8) == GCPhysIn
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72 | && RT_ALIGN_64(GCPhysOut, 8) == GCPhysOut)
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73 | {
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74 | if ( PGMPhysIsGCPhysNormal(pVM, GCPhysIn)
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75 | && PGMPhysIsGCPhysNormal(pVM, GCPhysOut))
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76 | {
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77 | PGIMHV pHv = &pVM->gim.s.u.Hv;
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78 | rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pbHypercallIn, GCPhysIn, GIM_HV_PAGE_SIZE);
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79 | if (RT_SUCCESS(rc))
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80 | {
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81 | rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pbHypercallOut, GCPhysOut, GIM_HV_PAGE_SIZE);
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82 | if (RT_SUCCESS(rc))
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83 | {
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84 | *prcHv = GIM_HV_STATUS_SUCCESS;
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85 | return VINF_SUCCESS;
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86 | }
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87 | Log(("GIM: HyperV: gimHvReadSlowHypercallParams reading GCPhysOut=%#RGp failed. rc=%Rrc\n", GCPhysOut, rc));
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88 | rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
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89 | }
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90 | else
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91 | {
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92 | Log(("GIM: HyperV: gimHvReadSlowHypercallParams reading GCPhysIn=%#RGp failed. rc=%Rrc\n", GCPhysIn,rc));
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93 | rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
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94 | }
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95 | }
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96 | else
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97 | *prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
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98 | }
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99 | else
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100 | *prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
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101 | return rc;
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102 | }
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103 | #endif
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104 |
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105 |
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106 | /**
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107 | * Handles all Hyper-V hypercalls.
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108 | *
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109 | * @returns VBox status code.
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110 | * @param pVCpu Pointer to the VMCPU.
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111 | * @param pCtx Pointer to the guest-CPU context.
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112 | *
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113 | * @thread EMT.
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114 | * @remarks Guest RIP may or may not have been incremented at this point.
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115 | */
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116 | VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
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117 | {
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118 | #ifndef IN_RING3
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119 | return VINF_GIM_R3_HYPERCALL;
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120 | #else
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121 | PVM pVM = pVCpu->CTX_SUFF(pVM);
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122 |
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123 | /*
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124 | * Verify that hypercalls are enabled.
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125 | */
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126 | if (!gimHvAreHypercallsEnabled(pVCpu))
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127 | return VERR_GIM_HYPERCALLS_NOT_ENABLED;
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128 |
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129 | /*
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130 | * Verify guest is in ring-0 protected mode.
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131 | */
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132 | uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
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133 | if ( uCpl
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134 | || CPUMIsGuestInRealModeEx(pCtx))
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135 | {
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136 | return VERR_GIM_HYPERCALL_ACCESS_DENIED;
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137 | }
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138 |
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139 | /*
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140 | * Get the hypercall operation code and modes.
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141 | */
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142 | const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
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143 | const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) | pCtx->eax;
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144 | const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
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145 | const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
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146 | const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn);
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147 | const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn);
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148 | uint64_t cHyperRepsDone = 0;
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149 |
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150 | int rc = VINF_SUCCESS;
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151 | int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
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152 | PGIMHV pHv = &pVM->gim.s.u.Hv;
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153 |
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154 | /*
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155 | * Validate common hypercall input parameters.
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156 | */
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157 | if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
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158 | && !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
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159 | && !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
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160 | {
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161 | /*
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162 | * Perform the hypercall.
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163 | */
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164 | switch (uHyperOp)
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165 | {
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166 | case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
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167 | {
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168 | if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
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169 | {
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170 | RTGCPHYS GCPhysOut;
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171 | rc = gimHvReadSlowHypercallParams(pVM, pCtx, fIs64BitMode, NULL /*pGCPhysIn*/, &GCPhysOut, &rcHv);
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172 | if ( RT_SUCCESS(rc)
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173 | && rcHv == GIM_HV_STATUS_SUCCESS)
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174 | {
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175 | LogRelMax(1, ("GIM: HyperV: Guest initiated debug data reception\n"));
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176 | rc = gimR3HvHypercallRetrieveDebugData(pVM, GCPhysOut, &rcHv);
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177 | if (RT_FAILURE(rc))
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178 | LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
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179 | }
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180 | }
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181 | else
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182 | rcHv = GIM_HV_STATUS_ACCESS_DENIED;
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183 | break;
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184 | }
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185 |
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186 | case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
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187 | {
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188 | if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
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189 | {
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190 | RTGCPHYS GCPhysOut;
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191 | rc = gimHvReadSlowHypercallParams(pVM, pCtx, fIs64BitMode, NULL /*pGCPhysIn*/, &GCPhysOut, &rcHv);
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192 | if ( RT_SUCCESS(rc)
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193 | && rcHv == GIM_HV_STATUS_SUCCESS)
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194 | {
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195 | LogRelMax(1, ("GIM: HyperV: Guest initiated debug data transmission\n"));
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196 | rc = gimR3HvHypercallPostDebugData(pVM, GCPhysOut, &rcHv);
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197 | if (RT_FAILURE(rc))
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198 | LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
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199 | }
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200 | }
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201 | else
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202 | rcHv = GIM_HV_STATUS_ACCESS_DENIED;
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203 | break;
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204 | }
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205 |
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206 | case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
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207 | {
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208 | if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
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209 | {
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210 | uint32_t fFlags = 0;
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211 | if (!fHyperFast)
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212 | {
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213 | rc = gimHvReadSlowHypercallParams(pVM, pCtx, fIs64BitMode, NULL /*pGCPhysIn*/, NULL /*pGCPhysOut*/,
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214 | &rcHv);
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215 | if ( RT_SUCCESS(rc)
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216 | && rcHv == GIM_HV_STATUS_SUCCESS)
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217 | {
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218 | PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
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219 | fFlags = pIn->fFlags;
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220 | }
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221 | }
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222 | else
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223 | {
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224 | rcHv = GIM_HV_STATUS_SUCCESS;
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225 | fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
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226 | }
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227 |
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228 | /*
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229 | * Since we don't really maintain our own buffers for the debug
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230 | * communication channel, we don't have anything to flush.
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231 | */
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232 | if (rcHv == GIM_HV_STATUS_SUCCESS)
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233 | {
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234 | if (!fFlags)
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235 | rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
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236 | else
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237 | LogRelMax(1, ("GIM: HyperV: Guest resetting debug session\n"));
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238 | }
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239 | }
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240 | else
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241 | rcHv = GIM_HV_STATUS_ACCESS_DENIED;
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242 | break;
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243 | }
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244 |
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245 | default:
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246 | rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
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247 | break;
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248 | }
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249 | }
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250 | else
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251 | rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
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252 |
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253 | /*
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254 | * Update the guest with results of the hypercall.
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255 | */
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256 | if (RT_SUCCESS(rc))
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257 | {
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258 | if (fIs64BitMode)
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259 | pCtx->rax = (cHyperRepsDone << 32) | rcHv;
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260 | else
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261 | {
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262 | pCtx->edx = cHyperRepsDone;
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263 | pCtx->eax = rcHv;
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264 | }
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265 | }
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266 |
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267 | return rc;
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268 | #endif
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269 | }
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270 |
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271 |
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272 | /**
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273 | * Returns whether the guest has configured and enabled the use of Hyper-V's
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274 | * hypercall interface.
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275 | *
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276 | * @returns true if hypercalls are enabled, false otherwise.
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277 | * @param pVCpu Pointer to the VMCPU.
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278 | */
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279 | VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
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280 | {
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281 | return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
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282 | }
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283 |
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284 |
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285 | /**
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286 | * Returns whether the guest has configured and enabled the use of Hyper-V's
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287 | * paravirtualized TSC.
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288 | *
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289 | * @returns true if paravirt. TSC is enabled, false otherwise.
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290 | * @param pVM Pointer to the VM.
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291 | */
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292 | VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
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293 | {
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294 | return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
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295 | }
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296 |
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297 |
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298 | #ifdef IN_RING3
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299 | /**
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300 | * Gets the descriptive OS ID variant as identified via the
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301 | * MSR_GIM_HV_GUEST_OS_ID MSR.
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302 | *
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303 | * @returns The name.
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304 | * @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
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305 | */
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306 | static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
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307 | {
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308 | /* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
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309 | uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
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310 | if (uVendor == 1 /* Microsoft */)
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311 | {
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312 | uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
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313 | switch (uOsVariant)
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314 | {
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315 | case 0: return "Undefined";
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316 | case 1: return "MS-DOS";
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317 | case 2: return "Windows 3.x";
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318 | case 3: return "Windows 9x";
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319 | case 4: return "Windows NT or derivative";
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320 | case 5: return "Windows CE";
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321 | default: return "Unknown";
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322 | }
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323 | }
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324 | return "Unknown";
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325 | }
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326 | #endif
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327 |
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328 |
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329 | /**
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330 | * MSR read handler for Hyper-V.
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331 | *
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332 | * @returns Strict VBox status code like CPUMQueryGuestMsr().
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333 | * @retval VINF_CPUM_R3_MSR_READ
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334 | * @retval VERR_CPUM_RAISE_GP_0
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335 | *
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336 | * @param pVCpu Pointer to the VMCPU.
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337 | * @param idMsr The MSR being read.
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338 | * @param pRange The range this MSR belongs to.
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339 | * @param puValue Where to store the MSR value read.
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340 | *
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341 | * @thread EMT.
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342 | */
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343 | VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
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344 | {
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345 | NOREF(pRange);
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346 | PVM pVM = pVCpu->CTX_SUFF(pVM);
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347 | PGIMHV pHv = &pVM->gim.s.u.Hv;
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348 |
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349 | switch (idMsr)
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350 | {
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351 | case MSR_GIM_HV_TIME_REF_COUNT:
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352 | {
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353 | /* Hyper-V reports the time in 100 ns units (10 MHz). */
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354 | uint64_t u64Tsc = TMCpuTickGet(pVCpu);
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355 | uint64_t u64TscHz = pHv->cTscTicksPerSecond;
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356 | uint64_t u64Tsc100Ns = u64TscHz / UINT64_C(10000000); /* 100 ns */
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357 | *puValue = (u64Tsc / u64Tsc100Ns);
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358 | return VINF_SUCCESS;
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359 | }
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360 |
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361 | case MSR_GIM_HV_VP_INDEX:
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362 | *puValue = pVCpu->idCpu;
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363 | return VINF_SUCCESS;
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364 |
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365 | case MSR_GIM_HV_TPR:
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366 | PDMApicReadMSR(pVM, pVCpu->idCpu, 0x80, puValue);
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367 | return VINF_SUCCESS;
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368 |
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369 | case MSR_GIM_HV_EOI:
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370 | PDMApicReadMSR(pVM, pVCpu->idCpu, 0x0B, puValue);
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371 | return VINF_SUCCESS;
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372 |
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373 | case MSR_GIM_HV_ICR:
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374 | PDMApicReadMSR(pVM, pVCpu->idCpu, 0x30, puValue);
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375 | return VINF_SUCCESS;
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376 |
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377 | case MSR_GIM_HV_GUEST_OS_ID:
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378 | *puValue = pHv->u64GuestOsIdMsr;
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379 | return VINF_SUCCESS;
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380 |
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381 | case MSR_GIM_HV_HYPERCALL:
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382 | *puValue = pHv->u64HypercallMsr;
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383 | return VINF_SUCCESS;
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384 |
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385 | case MSR_GIM_HV_REF_TSC:
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386 | *puValue = pHv->u64TscPageMsr;
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387 | return VINF_SUCCESS;
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388 |
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389 | case MSR_GIM_HV_TSC_FREQ:
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390 | *puValue = TMCpuTicksPerSecond(pVM);
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391 | return VINF_SUCCESS;
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392 |
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393 | case MSR_GIM_HV_APIC_FREQ:
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394 | {
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395 | int rc = PDMApicGetTimerFreq(pVM, puValue);
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396 | if (RT_FAILURE(rc))
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397 | return VERR_CPUM_RAISE_GP_0;
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398 | return VINF_SUCCESS;
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399 | }
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400 |
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401 | case MSR_GIM_HV_RESET:
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402 | *puValue = 0;
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403 | return VINF_SUCCESS;
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404 |
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405 | case MSR_GIM_HV_CRASH_CTL:
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406 | *puValue = pHv->uCrashCtl;
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407 | return VINF_SUCCESS;
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408 |
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409 | case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0; return VINF_SUCCESS;
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410 | case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1; return VINF_SUCCESS;
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411 | case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2; return VINF_SUCCESS;
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412 | case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3; return VINF_SUCCESS;
|
---|
413 | case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4; return VINF_SUCCESS;
|
---|
414 |
|
---|
415 | case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
|
---|
416 | {
|
---|
417 | if (pHv->fIsVendorMsHv)
|
---|
418 | {
|
---|
419 | #ifndef IN_RING3
|
---|
420 | return VINF_CPUM_R3_MSR_READ;
|
---|
421 | #else
|
---|
422 | LogRelMax(1, ("GIM: HyperV: Guest querying debug options MSR, returning %#x\n", GIM_HV_DEBUG_OPTIONS_MSR_ENABLE));
|
---|
423 | *puValue = GIM_HV_DEBUG_OPTIONS_MSR_ENABLE;
|
---|
424 | return VINF_SUCCESS;
|
---|
425 | #endif
|
---|
426 | }
|
---|
427 | return VERR_CPUM_RAISE_GP_0;
|
---|
428 | }
|
---|
429 |
|
---|
430 | default:
|
---|
431 | {
|
---|
432 | #ifdef IN_RING3
|
---|
433 | static uint32_t s_cTimes = 0;
|
---|
434 | if (s_cTimes++ < 20)
|
---|
435 | LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
|
---|
436 | #else
|
---|
437 | return VINF_CPUM_R3_MSR_READ;
|
---|
438 | #endif
|
---|
439 | LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
|
---|
440 | break;
|
---|
441 | }
|
---|
442 | }
|
---|
443 |
|
---|
444 | return VERR_CPUM_RAISE_GP_0;
|
---|
445 | }
|
---|
446 |
|
---|
447 |
|
---|
448 | /**
|
---|
449 | * MSR write handler for Hyper-V.
|
---|
450 | *
|
---|
451 | * @returns Strict VBox status code like CPUMSetGuestMsr().
|
---|
452 | * @retval VINF_CPUM_R3_MSR_WRITE
|
---|
453 | * @retval VERR_CPUM_RAISE_GP_0
|
---|
454 | *
|
---|
455 | * @param pVCpu Pointer to the VMCPU.
|
---|
456 | * @param idMsr The MSR being written.
|
---|
457 | * @param pRange The range this MSR belongs to.
|
---|
458 | * @param uRawValue The raw value with the ignored bits not masked.
|
---|
459 | *
|
---|
460 | * @thread EMT.
|
---|
461 | */
|
---|
462 | VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
|
---|
463 | {
|
---|
464 | NOREF(pRange);
|
---|
465 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
466 | PGIMHV pHv = &pVM->gim.s.u.Hv;
|
---|
467 |
|
---|
468 | switch (idMsr)
|
---|
469 | {
|
---|
470 | case MSR_GIM_HV_TPR:
|
---|
471 | PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x80, uRawValue);
|
---|
472 | return VINF_SUCCESS;
|
---|
473 |
|
---|
474 | case MSR_GIM_HV_EOI:
|
---|
475 | PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x0B, uRawValue);
|
---|
476 | return VINF_SUCCESS;
|
---|
477 |
|
---|
478 | case MSR_GIM_HV_ICR:
|
---|
479 | PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x30, uRawValue);
|
---|
480 | return VINF_SUCCESS;
|
---|
481 |
|
---|
482 | case MSR_GIM_HV_GUEST_OS_ID:
|
---|
483 | {
|
---|
484 | #ifndef IN_RING3
|
---|
485 | return VINF_CPUM_R3_MSR_WRITE;
|
---|
486 | #else
|
---|
487 | /* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
|
---|
488 | if (!uRawValue)
|
---|
489 | {
|
---|
490 | if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
|
---|
491 | {
|
---|
492 | gimR3HvDisableHypercallPage(pVM);
|
---|
493 | pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT;
|
---|
494 | LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
|
---|
495 | }
|
---|
496 | }
|
---|
497 | else
|
---|
498 | {
|
---|
499 | LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
|
---|
500 | LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
|
---|
501 | MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
|
---|
502 | MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
|
---|
503 | MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
|
---|
504 | MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
|
---|
505 |
|
---|
506 | /* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
|
---|
507 | CPUMCPUIDLEAF HyperLeaf;
|
---|
508 | RT_ZERO(HyperLeaf);
|
---|
509 | HyperLeaf.uLeaf = UINT32_C(0x40000002);
|
---|
510 | HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
|
---|
511 | HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
|
---|
512 | | (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
|
---|
513 | HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
|
---|
514 | HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
|
---|
515 | | (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
|
---|
516 | int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
|
---|
517 | AssertRC(rc2);
|
---|
518 | }
|
---|
519 |
|
---|
520 | pHv->u64GuestOsIdMsr = uRawValue;
|
---|
521 |
|
---|
522 | /*
|
---|
523 | * Notify VMM that hypercalls are now disabled/enabled.
|
---|
524 | */
|
---|
525 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
526 | {
|
---|
527 | if (uRawValue)
|
---|
528 | VMMHypercallsEnable(&pVM->aCpus[i]);
|
---|
529 | else
|
---|
530 | VMMHypercallsDisable(&pVM->aCpus[i]);
|
---|
531 | }
|
---|
532 |
|
---|
533 | return VINF_SUCCESS;
|
---|
534 | #endif /* IN_RING3 */
|
---|
535 | }
|
---|
536 |
|
---|
537 | case MSR_GIM_HV_HYPERCALL:
|
---|
538 | {
|
---|
539 | #ifndef IN_RING3
|
---|
540 | return VINF_CPUM_R3_MSR_WRITE;
|
---|
541 | #else /* IN_RING3 */
|
---|
542 | # if 0
|
---|
543 | /*
|
---|
544 | * For now ignore writes to the hypercall MSR (i.e. keeps it disabled).
|
---|
545 | * This is required to boot FreeBSD 10.1 (with Hyper-V enabled ofc),
|
---|
546 | * see @bugref{7270#c116}.
|
---|
547 | */
|
---|
548 | return VINF_SUCCESS;
|
---|
549 | # else
|
---|
550 | /* First, update all but the hypercall page enable bit. */
|
---|
551 | pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);
|
---|
552 |
|
---|
553 | /* Hypercall page can only be enabled when the guest has enabled hypercalls. */
|
---|
554 | bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);
|
---|
555 | if ( fEnable
|
---|
556 | && !gimHvAreHypercallsEnabled(pVCpu))
|
---|
557 | {
|
---|
558 | return VINF_SUCCESS;
|
---|
559 | }
|
---|
560 |
|
---|
561 | /* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
|
---|
562 | if (!fEnable)
|
---|
563 | {
|
---|
564 | gimR3HvDisableHypercallPage(pVM);
|
---|
565 | pHv->u64HypercallMsr = uRawValue;
|
---|
566 | return VINF_SUCCESS;
|
---|
567 | }
|
---|
568 |
|
---|
569 | /* Enable the hypercall-page. */
|
---|
570 | RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
|
---|
571 | int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
|
---|
572 | if (RT_SUCCESS(rc))
|
---|
573 | {
|
---|
574 | pHv->u64HypercallMsr = uRawValue;
|
---|
575 | return VINF_SUCCESS;
|
---|
576 | }
|
---|
577 |
|
---|
578 | return VERR_CPUM_RAISE_GP_0;
|
---|
579 | # endif
|
---|
580 | #endif /* IN_RING3 */
|
---|
581 | }
|
---|
582 |
|
---|
583 | case MSR_GIM_HV_REF_TSC:
|
---|
584 | {
|
---|
585 | #ifndef IN_RING3
|
---|
586 | return VINF_CPUM_R3_MSR_WRITE;
|
---|
587 | #else /* IN_RING3 */
|
---|
588 | /* First, update all but the TSC-page enable bit. */
|
---|
589 | pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE_BIT);
|
---|
590 |
|
---|
591 | /* Is the guest disabling the TSC-page? */
|
---|
592 | bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_REF_TSC_ENABLE_BIT);
|
---|
593 | if (!fEnable)
|
---|
594 | {
|
---|
595 | gimR3HvDisableTscPage(pVM);
|
---|
596 | pHv->u64TscPageMsr = uRawValue;
|
---|
597 | return VINF_SUCCESS;
|
---|
598 | }
|
---|
599 |
|
---|
600 | /* Enable the TSC-page. */
|
---|
601 | RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
|
---|
602 | int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence */, 0 /* uTscSequence */);
|
---|
603 | if (RT_SUCCESS(rc))
|
---|
604 | {
|
---|
605 | pHv->u64TscPageMsr = uRawValue;
|
---|
606 | return VINF_SUCCESS;
|
---|
607 | }
|
---|
608 |
|
---|
609 | return VERR_CPUM_RAISE_GP_0;
|
---|
610 | #endif /* IN_RING3 */
|
---|
611 | }
|
---|
612 |
|
---|
613 | case MSR_GIM_HV_RESET:
|
---|
614 | {
|
---|
615 | #ifndef IN_RING3
|
---|
616 | return VINF_CPUM_R3_MSR_WRITE;
|
---|
617 | #else
|
---|
618 | if (MSR_GIM_HV_RESET_IS_SET(uRawValue))
|
---|
619 | {
|
---|
620 | LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
|
---|
621 | int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3);
|
---|
622 | AssertRC(rc);
|
---|
623 | }
|
---|
624 | /* else: Ignore writes to other bits. */
|
---|
625 | return VINF_SUCCESS;
|
---|
626 | #endif /* IN_RING3 */
|
---|
627 | }
|
---|
628 |
|
---|
629 | case MSR_GIM_HV_CRASH_CTL:
|
---|
630 | {
|
---|
631 | #ifndef IN_RING3
|
---|
632 | return VINF_CPUM_R3_MSR_WRITE;
|
---|
633 | #else
|
---|
634 | if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY_BIT)
|
---|
635 | {
|
---|
636 | LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
|
---|
637 | pHv->uCrashP0, pHv->uCrashP1, pHv->uCrashP2, pHv->uCrashP3, pHv->uCrashP4));
|
---|
638 | }
|
---|
639 | return VINF_SUCCESS;
|
---|
640 | #endif
|
---|
641 | }
|
---|
642 |
|
---|
643 | case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0 = uRawValue; return VINF_SUCCESS;
|
---|
644 | case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1 = uRawValue; return VINF_SUCCESS;
|
---|
645 | case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2 = uRawValue; return VINF_SUCCESS;
|
---|
646 | case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3 = uRawValue; return VINF_SUCCESS;
|
---|
647 | case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4 = uRawValue; return VINF_SUCCESS;
|
---|
648 |
|
---|
649 | case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
|
---|
650 | case MSR_GIM_HV_VP_INDEX:
|
---|
651 | case MSR_GIM_HV_TSC_FREQ:
|
---|
652 | case MSR_GIM_HV_APIC_FREQ:
|
---|
653 | LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
|
---|
654 | return VERR_CPUM_RAISE_GP_0;
|
---|
655 |
|
---|
656 | case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
|
---|
657 | {
|
---|
658 | if (pHv->fIsVendorMsHv)
|
---|
659 | {
|
---|
660 | #ifndef IN_RING3
|
---|
661 | return VINF_CPUM_R3_MSR_WRITE;
|
---|
662 | #else
|
---|
663 | LogRelMax(1, ("GIM: HyperV: Guest setting debug options MSR to %#RX64, ignoring\n", uRawValue));
|
---|
664 | return VINF_SUCCESS;
|
---|
665 | #endif
|
---|
666 | }
|
---|
667 | return VERR_CPUM_RAISE_GP_0;
|
---|
668 | }
|
---|
669 |
|
---|
670 | default:
|
---|
671 | {
|
---|
672 | #ifdef IN_RING3
|
---|
673 | static uint32_t s_cTimes = 0;
|
---|
674 | if (s_cTimes++ < 20)
|
---|
675 | LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
|
---|
676 | uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
|
---|
677 | #else
|
---|
678 | return VINF_CPUM_R3_MSR_WRITE;
|
---|
679 | #endif
|
---|
680 | LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
|
---|
681 | break;
|
---|
682 | }
|
---|
683 | }
|
---|
684 |
|
---|
685 | return VERR_CPUM_RAISE_GP_0;
|
---|
686 | }
|
---|
687 |
|
---|
688 |
|
---|
689 | /**
|
---|
690 | * Whether we need to trap \#UD exceptions in the guest.
|
---|
691 | *
|
---|
692 | * We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
|
---|
693 | * enabled. For HM VMs, the hypercall would be handled via the
|
---|
694 | * VMCALL/VMMCALL VM-exit.
|
---|
695 | *
|
---|
696 | * @param pVCpu Pointer to the VMCPU.
|
---|
697 | */
|
---|
698 | VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
|
---|
699 | {
|
---|
700 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
701 | if ( !HMIsEnabled(pVM)
|
---|
702 | && gimHvAreHypercallsEnabled(pVCpu))
|
---|
703 | return true;
|
---|
704 | return false;
|
---|
705 | }
|
---|
706 |
|
---|
707 |
|
---|
708 | /**
|
---|
709 | * Exception handler for \#UD.
|
---|
710 | *
|
---|
711 | * @param pVCpu Pointer to the VMCPU.
|
---|
712 | * @param pCtx Pointer to the guest-CPU context.
|
---|
713 | * @param pDis Pointer to the disassembled instruction state at RIP.
|
---|
714 | * Optional, can be NULL.
|
---|
715 | *
|
---|
716 | * @thread EMT.
|
---|
717 | */
|
---|
718 | VMM_INT_DECL(int) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
|
---|
719 | {
|
---|
720 | /*
|
---|
721 | * If we didn't ask for #UD to be trapped, bail.
|
---|
722 | */
|
---|
723 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
724 | if (!gimHvShouldTrapXcptUD(pVCpu))
|
---|
725 | return VERR_GIM_OPERATION_FAILED;
|
---|
726 |
|
---|
727 | int rc = VINF_SUCCESS;
|
---|
728 | if (!pDis)
|
---|
729 | {
|
---|
730 | /*
|
---|
731 | * Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
|
---|
732 | * or the AMD VMMCALL instruction and if so, handle it as a hypercall.
|
---|
733 | */
|
---|
734 | DISCPUSTATE Dis;
|
---|
735 | rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL /* pcbInstr */);
|
---|
736 | pDis = &Dis;
|
---|
737 | }
|
---|
738 |
|
---|
739 | if (RT_SUCCESS(rc))
|
---|
740 | {
|
---|
741 | CPUMCPUVENDOR enmGuestCpuVendor = CPUMGetGuestCpuVendor(pVM);
|
---|
742 | if ( ( pDis->pCurInstr->uOpcode == OP_VMCALL
|
---|
743 | && ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
|
---|
744 | || enmGuestCpuVendor == CPUMCPUVENDOR_VIA))
|
---|
745 | || ( pDis->pCurInstr->uOpcode == OP_VMMCALL
|
---|
746 | && enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
|
---|
747 | {
|
---|
748 | /*
|
---|
749 | * Make sure guest ring-0 is the one making the hypercall.
|
---|
750 | */
|
---|
751 | if (CPUMGetGuestCPL(pVCpu))
|
---|
752 | return VERR_GIM_HYPERCALL_ACCESS_DENIED;
|
---|
753 |
|
---|
754 | /*
|
---|
755 | * Perform the hypercall and update RIP.
|
---|
756 | */
|
---|
757 | rc = gimHvHypercall(pVCpu, pCtx);
|
---|
758 | pCtx->rip += pDis->cbInstr;
|
---|
759 | return rc;
|
---|
760 | }
|
---|
761 | return VERR_GIM_OPERATION_FAILED;
|
---|
762 | }
|
---|
763 | return VERR_GIM_OPERATION_FAILED;
|
---|
764 | }
|
---|
765 |
|
---|