GIMAllHv.cpp@ 94620

Last change on this file since 94620 was 93725, checked in by vboxsync, 3 years ago
VMM: More arm64 adjustments. bugref:9898
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1	/* $Id: GIMAllHv.cpp 93725 2022-02-14 13:46:16Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include <VBox/vmm/gim.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/tm.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include <VBox/vmm/pgm.h>
31	#include <VBox/vmm/apic.h>
32	#include <VBox/vmm/em.h>
33	#include "GIMHvInternal.h"
34	#include "GIMInternal.h"
35	#include <VBox/vmm/vmcc.h>
36
37	#include <VBox/err.h>
38
39	#ifdef IN_RING3
40	# include <iprt/mem.h>
41	#endif
42
43
44	#ifdef IN_RING3
45	/**
46	* Read and validate slow hypercall parameters.
47	*
48	* @returns VBox status code.
49	* @param pVM The cross context VM structure.
50	* @param pCtx Pointer to the guest-CPU context.
51	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
52	* @param enmParam The hypercall parameter type.
53	* @param prcHv Where to store the Hyper-V status code. Only valid
54	* to the caller when this function returns
55	* VINF_SUCCESS.
56	*/
57	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
58	{
59	int rc = VINF_SUCCESS;
60	PGIMHV pHv = &pVM->gim.s.u.Hv;
61	RTGCPHYS GCPhysParam;
62	void *pvDst;
63	if (enmParam == GIMHVHYPERCALLPARAM_IN)
64	{
65	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
66	pvDst = pHv->pbHypercallIn;
67	pHv->GCPhysHypercallIn = GCPhysParam;
68	}
69	else
70	{
71	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
72	pvDst = pHv->pbHypercallOut;
73	pHv->GCPhysHypercallOut = GCPhysParam;
74	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
75	}
76
77	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
78	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
79	{
80	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
81	{
82	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
83	if (RT_SUCCESS(rc))
84	{
85	*prcHv = GIM_HV_STATUS_SUCCESS;
86	return VINF_SUCCESS;
87	}
88	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
89	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
90	}
91	else
92	{
93	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
94	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
95	}
96	}
97	else
98	{
99	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
100	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
101	}
102	return rc;
103	}
104
105
106	/**
107	* Helper for reading and validating slow hypercall input and output parameters.
108	*
109	* @returns VBox status code.
110	* @param pVM The cross context VM structure.
111	* @param pCtx Pointer to the guest-CPU context.
112	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
113	* @param prcHv Where to store the Hyper-V status code. Only valid
114	* to the caller when this function returns
115	* VINF_SUCCESS.
116	*/
117	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
118	{
119	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
120	if ( RT_SUCCESS(rc)
121	&& *prcHv == GIM_HV_STATUS_SUCCESS)
122	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
123	return rc;
124	}
125	#endif
126
127
128	/**
129	* Handles all Hyper-V hypercalls.
130	*
131	* @returns Strict VBox status code.
132	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
133	* failed).
134	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
135	* @retval VERR_GIM_HYPERCALLS_NOT_ENABLED hypercalls are disabled by the
136	* guest.
137	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
138	* @retval VERR_GIM_HYPERCALL_MEMORY_READ_FAILED hypercall failed while reading
139	* memory.
140	* @retval VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED hypercall failed while
141	* writing memory.
142	*
143	* @param pVCpu The cross context virtual CPU structure.
144	* @param pCtx Pointer to the guest-CPU context.
145	*
146	* @thread EMT(pVCpu).
147	*/
148	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPUCC pVCpu, PCPUMCTX pCtx)
149	{
150	VMCPU_ASSERT_EMT(pVCpu);
151
152	#ifndef IN_RING3
153	RT_NOREF_PV(pVCpu);
154	RT_NOREF_PV(pCtx);
155	return VINF_GIM_R3_HYPERCALL;
156	#else
157	PVM pVM = pVCpu->CTX_SUFF(pVM);
158	STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
159
160	/*
161	* Verify that hypercalls are enabled by the guest.
162	*/
163	if (!gimHvAreHypercallsEnabled(pVM))
164	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
165
166	/*
167	* Verify guest is in ring-0 protected mode.
168	*/
169	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
170	if ( uCpl
171	\|\| CPUMIsGuestInRealModeEx(pCtx))
172	{
173	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
174	}
175
176	/*
177	* Get the hypercall operation code and modes.
178	* Fast hypercalls have only two or fewer inputs but no output parameters.
179	*/
180	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
181	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
182	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
183	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
184	const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn);
185	const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn);
186	uint64_t cHyperRepsDone = 0;
187
188	/* Currently no repeating hypercalls are supported. */
189	RT_NOREF2(cHyperReps, idxHyperRepStart);
190
191	int rc = VINF_SUCCESS;
192	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
193	PGIMHV pHv = &pVM->gim.s.u.Hv;
194
195	/*
196	* Validate common hypercall input parameters.
197	*/
198	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
199	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
200	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
201	{
202	/*
203	* Perform the hypercall.
204	*/
205	switch (uHyperOp)
206	{
207	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
208	{
209	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
210	{
211	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
212	if ( RT_SUCCESS(rc)
213	&& rcHv == GIM_HV_STATUS_SUCCESS)
214	{
215	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
216	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
217	if (RT_FAILURE(rc))
218	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
219	}
220	}
221	else
222	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
223	break;
224	}
225
226	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
227	{
228	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
229	{
230	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
231	if ( RT_SUCCESS(rc)
232	&& rcHv == GIM_HV_STATUS_SUCCESS)
233	{
234	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
235	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
236	if (RT_FAILURE(rc))
237	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
238	}
239	}
240	else
241	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
242	break;
243	}
244
245	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
246	{
247	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
248	{
249	uint32_t fFlags = 0;
250	if (!fHyperFast)
251	{
252	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
253	if ( RT_SUCCESS(rc)
254	&& rcHv == GIM_HV_STATUS_SUCCESS)
255	{
256	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
257	fFlags = pIn->fFlags;
258	}
259	}
260	else
261	{
262	rcHv = GIM_HV_STATUS_SUCCESS;
263	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
264	}
265
266	/*
267	* Nothing to flush on the sending side as we don't maintain our own buffers.
268	*/
269	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
270	if (rcHv == GIM_HV_STATUS_SUCCESS)
271	{
272	if (fFlags)
273	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
274	else
275	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
276	}
277	}
278	else
279	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
280	break;
281	}
282
283	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
284	{
285	if (pHv->fIsInterfaceVs)
286	{
287	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
288	if ( RT_SUCCESS(rc)
289	&& rcHv == GIM_HV_STATUS_SUCCESS)
290	{
291	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
292	PCGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
293	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
294	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
295	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->auSintMsrs[GIM_HV_VMBUS_MSG_SINT])
296	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
297	{
298	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
299	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
300	{
301	/*
302	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
303	*/
304	GIMHVMSG HvMsg;
305	RT_ZERO(HvMsg);
306	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
307	HvMsg.MsgHdr.cbPayload = 0xf;
308	HvMsg.aPayload[0] = 0xf;
309	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
310	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
311	if (RT_SUCCESS(rc2))
312	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
313	else
314	{
315	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
316	offMsg, rc));
317	}
318	}
319	}
320
321	/*
322	* Make the call fail after updating the SIMP, so the guest can go back to using
323	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
324	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
325	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
326	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
327	*/
328	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
329	}
330	else
331	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
332	}
333	else
334	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
335	break;
336	}
337
338	case GIM_HV_EXT_HYPERCALL_OP_QUERY_CAP: /* Non-rep, extended hypercall. */
339	{
340	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS)
341	{
342	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, &rcHv);
343	if ( RT_SUCCESS(rc)
344	&& rcHv == GIM_HV_STATUS_SUCCESS)
345	{
346	rc = gimR3HvHypercallExtQueryCap(pVM, &rcHv);
347	}
348	}
349	else
350	{
351	LogRel(("GIM: HyperV: Denied HvExtCallQueryCapabilities when the feature is not exposed\n"));
352	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
353	}
354	break;
355	}
356
357	case GIM_HV_EXT_HYPERCALL_OP_GET_BOOT_ZEROED_MEM: /* Non-rep, extended hypercall. */
358	{
359	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS)
360	{
361	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, &rcHv);
362	if ( RT_SUCCESS(rc)
363	&& rcHv == GIM_HV_STATUS_SUCCESS)
364	{
365	rc = gimR3HvHypercallExtGetBootZeroedMem(pVM, &rcHv);
366	}
367	}
368	else
369	{
370	LogRel(("GIM: HyperV: Denied HvExtCallGetBootZeroedMemory when the feature is not exposed\n"));
371	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
372	}
373	break;
374	}
375
376	default:
377	{
378	LogRel(("GIM: HyperV: Unknown/invalid hypercall opcode %#x (%u)\n", uHyperOp, uHyperOp));
379	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
380	break;
381	}
382	}
383	}
384	else
385	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
386
387	/*
388	* Update the guest with results of the hypercall.
389	*/
390	if (RT_SUCCESS(rc))
391	{
392	if (fIs64BitMode)
393	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
394	else
395	{
396	pCtx->edx = cHyperRepsDone;
397	pCtx->eax = rcHv;
398	}
399	}
400
401	return rc;
402	#endif
403	}
404
405
406	/**
407	* Returns a pointer to the MMIO2 regions supported by Hyper-V.
408	*
409	* @returns Pointer to an array of MMIO2 regions.
410	* @param pVM The cross context VM structure.
411	* @param pcRegions Where to store the number of regions in the array.
412	*/
413	VMM_INT_DECL(PGIMMMIO2REGION) gimHvGetMmio2Regions(PVM pVM, uint32_t *pcRegions)
414	{
415	Assert(GIMIsEnabled(pVM));
416	PGIMHV pHv = &pVM->gim.s.u.Hv;
417
418	AssertCompile(RT_ELEMENTS(pHv->aMmio2Regions) <= 8);
419	*pcRegions = RT_ELEMENTS(pHv->aMmio2Regions);
420	return pHv->aMmio2Regions;
421	}
422
423
424	/**
425	* Returns whether the guest has configured and enabled the use of Hyper-V's
426	* hypercall interface.
427	*
428	* @returns true if hypercalls are enabled, false otherwise.
429	* @param pVM The cross context VM structure.
430	*/
431	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PCVM pVM)
432	{
433	return RT_BOOL(pVM->gim.s.u.Hv.u64GuestOsIdMsr != 0);
434	}
435
436
437	/**
438	* Returns whether the guest has configured and enabled the use of Hyper-V's
439	* paravirtualized TSC.
440	*
441	* @returns true if paravirt. TSC is enabled, false otherwise.
442	* @param pVM The cross context VM structure.
443	*/
444	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
445	{
446	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
447	}
448
449
450	#ifdef IN_RING3
451	/**
452	* Gets the descriptive OS ID variant as identified via the
453	* MSR_GIM_HV_GUEST_OS_ID MSR.
454	*
455	* @returns The name.
456	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
457	*/
458	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
459	{
460	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
461	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
462	if (uVendor == 1 /* Microsoft */)
463	{
464	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
465	switch (uOsVariant)
466	{
467	case 0: return "Undefined";
468	case 1: return "MS-DOS";
469	case 2: return "Windows 3.x";
470	case 3: return "Windows 9x";
471	case 4: return "Windows NT or derivative";
472	case 5: return "Windows CE";
473	default: return "Unknown";
474	}
475	}
476	return "Unknown";
477	}
478	#endif
479
480	/**
481	* Gets the time reference count for the current VM.
482	*
483	* @returns The time reference count.
484	* @param pVCpu The cross context virtual CPU structure.
485	*/
486	DECLINLINE(uint64_t) gimHvGetTimeRefCount(PVMCPUCC pVCpu)
487	{
488	/* Hyper-V reports the time in 100 ns units (10 MHz). */
489	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
490	PCGIMHV pHv = &pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv;
491	uint64_t const u64Tsc = TMCpuTickGet(pVCpu); /** @todo should we be passing VCPU0 always? */
492	uint64_t const u64TscHz = pHv->cTscTicksPerSecond;
493	uint64_t const u64Tsc100NS = u64TscHz / UINT64_C(10000000); /* 100 ns */
494	uint64_t const uTimeRefCount = (u64Tsc / u64Tsc100NS);
495	return uTimeRefCount;
496	}
497
498
499	/**
500	* Starts the synthetic timer.
501	*
502	* @param pVCpu The cross context virtual CPU structure.
503	* @param pHvStimer Pointer to the Hyper-V synthetic timer.
504	*
505	* @remarks Caller needs to hold the timer critical section.
506	* @thread Any.
507	*/
508	VMM_INT_DECL(void) gimHvStartStimer(PVMCPUCC pVCpu, PCGIMHVSTIMER pHvStimer)
509	{
510	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
511	TMTIMERHANDLE hTimer = pHvStimer->hTimer;
512	Assert(TMTimerIsLockOwner(pVM, hTimer));
513
514	uint64_t const uTimerCount = pHvStimer->uStimerCountMsr;
515	if (uTimerCount)
516	{
517	uint64_t const uTimerCountNS = uTimerCount * 100;
518
519	/* For periodic timers, 'uTimerCountNS' represents the relative interval. */
520	if (MSR_GIM_HV_STIMER_IS_PERIODIC(pHvStimer->uStimerConfigMsr))
521	{
522	TMTimerSetNano(pVM, hTimer, uTimerCountNS);
523	LogFlow(("GIM%u: HyperV: Started relative periodic STIMER%u with uTimerCountNS=%RU64\n", pVCpu->idCpu,
524	pHvStimer->idxStimer, uTimerCountNS));
525	}
526	else
527	{
528	/* For one-shot timers, 'uTimerCountNS' represents an absolute expiration wrt to Hyper-V reference time,
529	we convert it to a relative time and program the timer. */
530	uint64_t const uCurRefTimeNS = gimHvGetTimeRefCount(pVCpu) * 100;
531	if (uTimerCountNS > uCurRefTimeNS)
532	{
533	uint64_t const uRelativeNS = uTimerCountNS - uCurRefTimeNS;
534	TMTimerSetNano(pVM, hTimer, uRelativeNS);
535	LogFlow(("GIM%u: HyperV: Started one-shot relative STIMER%u with uRelativeNS=%RU64\n", pVCpu->idCpu,
536	pHvStimer->idxStimer, uRelativeNS));
537	}
538	}
539	/** @todo frequency hinting? */
540	}
541	}
542
543
544	/**
545	* Stops the synthetic timer for the given VCPU.
546	*
547	* @param pVCpu The cross context virtual CPU structure.
548	* @param pHvStimer Pointer to the Hyper-V synthetic timer.
549	*
550	* @remarks Caller needs to the hold the timer critical section.
551	* @thread EMT(pVCpu).
552	*/
553	static void gimHvStopStimer(PVMCPUCC pVCpu, PGIMHVSTIMER pHvStimer)
554	{
555	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
556	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
557
558	TMTIMERHANDLE hTimer = pHvStimer->hTimer;
559	Assert(TMTimerIsLockOwner(pVM, hTimer));
560
561	if (TMTimerIsActive(pVM, hTimer))
562	TMTimerStop(pVM, hTimer);
563	}
564
565
566	/**
567	* MSR read handler for Hyper-V.
568	*
569	* @returns Strict VBox status code like CPUMQueryGuestMsr().
570	* @retval VINF_CPUM_R3_MSR_READ
571	* @retval VERR_CPUM_RAISE_GP_0
572	*
573	* @param pVCpu The cross context virtual CPU structure.
574	* @param idMsr The MSR being read.
575	* @param pRange The range this MSR belongs to.
576	* @param puValue Where to store the MSR value read.
577	*
578	* @thread EMT.
579	*/
580	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
581	{
582	NOREF(pRange);
583	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
584	PCGIMHV pHv = &pVM->gim.s.u.Hv;
585
586	switch (idMsr)
587	{
588	case MSR_GIM_HV_TIME_REF_COUNT:
589	*puValue = gimHvGetTimeRefCount(pVCpu);
590	return VINF_SUCCESS;
591
592	case MSR_GIM_HV_VP_INDEX:
593	*puValue = pVCpu->idCpu;
594	return VINF_SUCCESS;
595
596	case MSR_GIM_HV_TPR:
597	*puValue = APICHvGetTpr(pVCpu);
598	return VINF_SUCCESS;
599
600	case MSR_GIM_HV_ICR:
601	*puValue = APICHvGetIcr(pVCpu);
602	return VINF_SUCCESS;
603
604	case MSR_GIM_HV_GUEST_OS_ID:
605	*puValue = pHv->u64GuestOsIdMsr;
606	return VINF_SUCCESS;
607
608	case MSR_GIM_HV_HYPERCALL:
609	*puValue = pHv->u64HypercallMsr;
610	return VINF_SUCCESS;
611
612	case MSR_GIM_HV_REF_TSC:
613	*puValue = pHv->u64TscPageMsr;
614	return VINF_SUCCESS;
615
616	case MSR_GIM_HV_TSC_FREQ:
617	*puValue = TMCpuTicksPerSecond(pVM);
618	return VINF_SUCCESS;
619
620	case MSR_GIM_HV_APIC_FREQ:
621	{
622	int rc = APICGetTimerFreq(pVM, puValue);
623	if (RT_FAILURE(rc))
624	return VERR_CPUM_RAISE_GP_0;
625	return VINF_SUCCESS;
626	}
627
628	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
629	*puValue = pHv->uDbgStatusMsr;
630	return VINF_SUCCESS;
631
632	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
633	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
634	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
635	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
636	{
637	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
638	*puValue = pHvCpu->auSintMsrs[idMsr - MSR_GIM_HV_SINT0];
639	return VINF_SUCCESS;
640	}
641
642	case MSR_GIM_HV_STIMER0_CONFIG:
643	case MSR_GIM_HV_STIMER1_CONFIG:
644	case MSR_GIM_HV_STIMER2_CONFIG:
645	case MSR_GIM_HV_STIMER3_CONFIG:
646	{
647	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
648	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
649	PCGIMHVSTIMER pcHvStimer = &pHvCpu->aStimers[idxStimer];
650	*puValue = pcHvStimer->uStimerConfigMsr;
651	return VINF_SUCCESS;
652	}
653
654	case MSR_GIM_HV_STIMER0_COUNT:
655	case MSR_GIM_HV_STIMER1_COUNT:
656	case MSR_GIM_HV_STIMER2_COUNT:
657	case MSR_GIM_HV_STIMER3_COUNT:
658	{
659	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
660	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_COUNT) >> 1;
661	PCGIMHVSTIMER pcHvStimer = &pHvCpu->aStimers[idxStimer];
662	*puValue = pcHvStimer->uStimerCountMsr;
663	return VINF_SUCCESS;
664	}
665
666	case MSR_GIM_HV_EOM:
667	{
668	*puValue = 0;
669	return VINF_SUCCESS;
670	}
671
672	case MSR_GIM_HV_SCONTROL:
673	{
674	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
675	*puValue = pHvCpu->uSControlMsr;
676	return VINF_SUCCESS;
677	}
678
679	case MSR_GIM_HV_SIMP:
680	{
681	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
682	*puValue = pHvCpu->uSimpMsr;
683	return VINF_SUCCESS;
684	}
685
686	case MSR_GIM_HV_SVERSION:
687	*puValue = GIM_HV_SVERSION;
688	return VINF_SUCCESS;
689
690	case MSR_GIM_HV_RESET:
691	*puValue = 0;
692	return VINF_SUCCESS;
693
694	case MSR_GIM_HV_CRASH_CTL:
695	*puValue = pHv->uCrashCtlMsr;
696	return VINF_SUCCESS;
697
698	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
699	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
700	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
701	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
702	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
703
704	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
705	{
706	if (pHv->fIsVendorMsHv)
707	{
708	#ifndef IN_RING3
709	return VINF_CPUM_R3_MSR_READ;
710	#else
711	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
712	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
713	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
714	return VINF_SUCCESS;
715	#endif
716	}
717	break;
718	}
719
720	/* Write-only MSRs: */
721	case MSR_GIM_HV_EOI:
722	/* Reserved/unknown MSRs: */
723	default:
724	{
725	#ifdef IN_RING3
726	static uint32_t s_cTimes = 0;
727	if (s_cTimes++ < 20)
728	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
729	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
730	break;
731	#else
732	return VINF_CPUM_R3_MSR_READ;
733	#endif
734	}
735	}
736
737	return VERR_CPUM_RAISE_GP_0;
738	}
739
740
741	/**
742	* MSR write handler for Hyper-V.
743	*
744	* @returns Strict VBox status code like CPUMSetGuestMsr().
745	* @retval VINF_CPUM_R3_MSR_WRITE
746	* @retval VERR_CPUM_RAISE_GP_0
747	*
748	* @param pVCpu The cross context virtual CPU structure.
749	* @param idMsr The MSR being written.
750	* @param pRange The range this MSR belongs to.
751	* @param uRawValue The raw value with the ignored bits not masked.
752	*
753	* @thread EMT.
754	*/
755	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
756	{
757	NOREF(pRange);
758	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
759	PGIMHV pHv = &pVM->gim.s.u.Hv;
760
761	switch (idMsr)
762	{
763	case MSR_GIM_HV_TPR:
764	return APICHvSetTpr(pVCpu, uRawValue);
765
766	case MSR_GIM_HV_EOI:
767	return APICHvSetEoi(pVCpu, uRawValue);
768
769	case MSR_GIM_HV_ICR:
770	return APICHvSetIcr(pVCpu, uRawValue);
771
772	case MSR_GIM_HV_GUEST_OS_ID:
773	{
774	#ifndef IN_RING3
775	return VINF_CPUM_R3_MSR_WRITE;
776	#else
777	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
778	if (!uRawValue)
779	{
780	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
781	{
782	gimR3HvDisableHypercallPage(pVM);
783	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE;
784	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
785	}
786	}
787	else
788	{
789	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
790	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
791	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
792	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
793	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
794	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
795
796	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
797	CPUMCPUIDLEAF HyperLeaf;
798	RT_ZERO(HyperLeaf);
799	HyperLeaf.uLeaf = UINT32_C(0x40000002);
800	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
801	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
802	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
803	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
804	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
805	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
806	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
807	AssertRC(rc2);
808	}
809
810	pHv->u64GuestOsIdMsr = uRawValue;
811
812	/*
813	* Update EM on hypercall instruction enabled state.
814	*/
815	if (uRawValue)
816	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
817	EMSetHypercallInstructionsEnabled(pVM->CTX_SUFF(apCpus)[idCpu], true);
818	else
819	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
820	EMSetHypercallInstructionsEnabled(pVM->CTX_SUFF(apCpus)[idCpu], false);
821
822	return VINF_SUCCESS;
823	#endif /* IN_RING3 */
824	}
825
826	case MSR_GIM_HV_HYPERCALL:
827	{
828	#ifndef IN_RING3
829	return VINF_CPUM_R3_MSR_WRITE;
830	#else
831	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
832	* see @bugref{7270#c116}. */
833	/* First, update all but the hypercall page enable bit. */
834	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE);
835
836	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
837	bool fEnable = MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(uRawValue);
838	if ( fEnable
839	&& !gimHvAreHypercallsEnabled(pVM))
840	{
841	return VINF_SUCCESS;
842	}
843
844	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
845	if (!fEnable)
846	{
847	gimR3HvDisableHypercallPage(pVM);
848	pHv->u64HypercallMsr = uRawValue;
849	return VINF_SUCCESS;
850	}
851
852	/* Enable the hypercall-page. */
853	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << GUEST_PAGE_SHIFT;
854	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
855	if (RT_SUCCESS(rc))
856	{
857	pHv->u64HypercallMsr = uRawValue;
858	return VINF_SUCCESS;
859	}
860
861	return VERR_CPUM_RAISE_GP_0;
862	#endif
863	}
864
865	case MSR_GIM_HV_REF_TSC:
866	{
867	#ifndef IN_RING3
868	return VINF_CPUM_R3_MSR_WRITE;
869	#else /* IN_RING3 */
870	/* First, update all but the TSC page enable bit. */
871	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE);
872
873	/* Is the guest disabling the TSC page? */
874	bool fEnable = MSR_GIM_HV_REF_TSC_IS_ENABLED(uRawValue);
875	if (!fEnable)
876	{
877	gimR3HvDisableTscPage(pVM);
878	pHv->u64TscPageMsr = uRawValue;
879	return VINF_SUCCESS;
880	}
881
882	/* Enable the TSC page. */
883	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << GUEST_PAGE_SHIFT;
884	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
885	if (RT_SUCCESS(rc))
886	{
887	pHv->u64TscPageMsr = uRawValue;
888	return VINF_SUCCESS;
889	}
890
891	return VERR_CPUM_RAISE_GP_0;
892	#endif /* IN_RING3 */
893	}
894
895	case MSR_GIM_HV_APIC_ASSIST_PAGE:
896	{
897	#ifndef IN_RING3
898	return VINF_CPUM_R3_MSR_WRITE;
899	#else /* IN_RING3 */
900	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
901	pHvCpu->uApicAssistPageMsr = uRawValue;
902
903	if (MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(uRawValue))
904	{
905	RTGCPHYS GCPhysApicAssistPage = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << GUEST_PAGE_SHIFT;
906	if (PGMPhysIsGCPhysNormal(pVM, GCPhysApicAssistPage))
907	{
908	int rc = gimR3HvEnableApicAssistPage(pVCpu, GCPhysApicAssistPage);
909	if (RT_SUCCESS(rc))
910	{
911	pHvCpu->uApicAssistPageMsr = uRawValue;
912	return VINF_SUCCESS;
913	}
914	}
915	else
916	{
917	LogRelMax(5, ("GIM%u: HyperV: APIC-assist page address %#RGp invalid!\n", pVCpu->idCpu,
918	GCPhysApicAssistPage));
919	}
920	}
921	else
922	gimR3HvDisableApicAssistPage(pVCpu);
923
924	return VERR_CPUM_RAISE_GP_0;
925	#endif /* IN_RING3 */
926	}
927
928	case MSR_GIM_HV_RESET:
929	{
930	#ifndef IN_RING3
931	return VINF_CPUM_R3_MSR_WRITE;
932	#else
933	if (MSR_GIM_HV_RESET_IS_ENABLED(uRawValue))
934	{
935	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
936	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3, PDMVMRESET_F_GIM);
937	AssertRC(rc); /* Note! Not allowed to return VINF_EM_RESET / VINF_EM_HALT here, so ignore them. */
938	}
939	/* else: Ignore writes to other bits. */
940	return VINF_SUCCESS;
941	#endif /* IN_RING3 */
942	}
943
944	case MSR_GIM_HV_CRASH_CTL:
945	{
946	#ifndef IN_RING3
947	return VINF_CPUM_R3_MSR_WRITE;
948	#else
949	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY)
950	{
951	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
952	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
953	DBGFR3ReportBugCheck(pVM, pVCpu, DBGFEVENT_BSOD_MSR, pHv->uCrashP0Msr, pHv->uCrashP1Msr,
954	pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr);
955	/* (Do not try pass VINF_EM_DBG_EVENT, doesn't work from here!) */
956	}
957	return VINF_SUCCESS;
958	#endif
959	}
960
961	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
962	{
963	if (!pHv->fDbgEnabled)
964	return VERR_CPUM_RAISE_GP_0;
965	#ifndef IN_RING3
966	return VINF_CPUM_R3_MSR_WRITE;
967	#else
968	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
969	pHv->uDbgSendBufferMsr = GCPhysBuffer;
970	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
971	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
972	else
973	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
974	pHv->uDbgSendBufferMsr = uRawValue;
975	return VINF_SUCCESS;
976	#endif
977	}
978
979	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
980	{
981	if (!pHv->fDbgEnabled)
982	return VERR_CPUM_RAISE_GP_0;
983	#ifndef IN_RING3
984	return VINF_CPUM_R3_MSR_WRITE;
985	#else
986	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
987	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
988	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
989	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
990	else
991	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
992	return VINF_SUCCESS;
993	#endif
994	}
995
996	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
997	{
998	if (!pHv->fDbgEnabled)
999	return VERR_CPUM_RAISE_GP_0;
1000	#ifndef IN_RING3
1001	return VINF_CPUM_R3_MSR_WRITE;
1002	#else
1003	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
1004	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
1005	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
1006	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
1007	else
1008	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
1009	return VINF_SUCCESS;
1010	#endif
1011	}
1012
1013	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
1014	{
1015	if (!pHv->fDbgEnabled)
1016	return VERR_CPUM_RAISE_GP_0;
1017	#ifndef IN_RING3
1018	return VINF_CPUM_R3_MSR_WRITE;
1019	#else
1020	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
1021	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
1022	{
1023	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
1024	return VERR_CPUM_RAISE_GP_0;
1025	}
1026
1027	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
1028	{
1029	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
1030	if ( cbWrite > 0
1031	&& cbWrite < GIM_HV_PAGE_SIZE)
1032	{
1033	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
1034	{
1035	Assert(pHv->pvDbgBuffer);
1036	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
1037	if (RT_SUCCESS(rc))
1038	{
1039	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
1040	uint32_t cbWritten = 0;
1041	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
1042	if ( RT_SUCCESS(rc)
1043	&& cbWrite == cbWritten)
1044	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS;
1045	else
1046	pHv->uDbgStatusMsr = 0;
1047	}
1048	else
1049	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
1050	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
1051	}
1052	else
1053	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
1054	(RTGCPHYS)pHv->uDbgSendBufferMsr));
1055	}
1056	else
1057	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
1058	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
1059	}
1060	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
1061	{
1062	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
1063	{
1064	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
1065	uint32_t cbReallyRead;
1066	Assert(pHv->pvDbgBuffer);
1067	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, GIM_HV_PAGE_SIZE, GIM_HV_PAGE_SIZE,
1068	&cbReallyRead, 0, false /fUdpPkt/);
1069	if ( RT_SUCCESS(rc)
1070	&& cbReallyRead > 0)
1071	{
1072	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
1073	if (RT_SUCCESS(rc))
1074	{
1075	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
1076	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS;
1077	}
1078	else
1079	{
1080	pHv->uDbgStatusMsr = 0;
1081	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
1082	}
1083	}
1084	else
1085	pHv->uDbgStatusMsr = 0;
1086	}
1087	else
1088	{
1089	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n",
1090	(RTGCPHYS)pHv->uDbgRecvBufferMsr));
1091	}
1092	}
1093	return VINF_SUCCESS;
1094	#endif
1095	}
1096
1097	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
1098	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
1099	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
1100	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
1101	{
1102	uint8_t uVector = MSR_GIM_HV_SINT_GET_VECTOR(uRawValue);
1103	bool const fVMBusMsg = RT_BOOL(idMsr == GIM_HV_VMBUS_MSG_SINT);
1104	size_t const idxSintMsr = idMsr - MSR_GIM_HV_SINT0;
1105	const char *pszDesc = fVMBusMsg ? "VMBus Message" : "Generic";
1106	if (uVector < GIM_HV_SINT_VECTOR_VALID_MIN)
1107	{
1108	LogRel(("GIM%u: HyperV: Programmed an invalid vector in SINT%u (%s), uVector=%u -> #GP(0)\n", pVCpu->idCpu,
1109	idxSintMsr, pszDesc, uVector));
1110	return VERR_CPUM_RAISE_GP_0;
1111	}
1112
1113	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1114	pHvCpu->auSintMsrs[idxSintMsr] = uRawValue;
1115	if (fVMBusMsg)
1116	{
1117	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
1118	Log(("GIM%u: HyperV: Masked SINT%u (%s)\n", pVCpu->idCpu, idxSintMsr, pszDesc));
1119	else
1120	Log(("GIM%u: HyperV: Unmasked SINT%u (%s), uVector=%u\n", pVCpu->idCpu, idxSintMsr, pszDesc, uVector));
1121	}
1122	Log(("GIM%u: HyperV: Written SINT%u=%#RX64\n", pVCpu->idCpu, idxSintMsr, uRawValue));
1123	return VINF_SUCCESS;
1124	}
1125
1126	case MSR_GIM_HV_SCONTROL:
1127	{
1128	#ifndef IN_RING3
1129	/** @todo make this RZ later? */
1130	return VINF_CPUM_R3_MSR_WRITE;
1131	#else
1132	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1133	pHvCpu->uSControlMsr = uRawValue;
1134	if (MSR_GIM_HV_SCONTROL_IS_ENABLED(uRawValue))
1135	LogRel(("GIM%u: HyperV: Synthetic interrupt control enabled\n", pVCpu->idCpu));
1136	else
1137	LogRel(("GIM%u: HyperV: Synthetic interrupt control disabled\n", pVCpu->idCpu));
1138	return VINF_SUCCESS;
1139	#endif
1140	}
1141
1142	case MSR_GIM_HV_STIMER0_CONFIG:
1143	case MSR_GIM_HV_STIMER1_CONFIG:
1144	case MSR_GIM_HV_STIMER2_CONFIG:
1145	case MSR_GIM_HV_STIMER3_CONFIG:
1146	{
1147	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1148	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
1149
1150	/* Validate the writable bits. */
1151	if (RT_LIKELY(!(uRawValue & ~MSR_GIM_HV_STIMER_RW_VALID)))
1152	{
1153	Assert(idxStimer < RT_ELEMENTS(pHvCpu->aStimers));
1154	PGIMHVSTIMER pHvStimer = &pHvCpu->aStimers[idxStimer];
1155
1156	/* Lock to prevent concurrent access from the timer callback. */
1157	int rc = TMTimerLock(pVM, pHvStimer->hTimer, VERR_IGNORED);
1158	if (rc == VINF_SUCCESS)
1159	{
1160	/* Update the MSR value. */
1161	pHvStimer->uStimerConfigMsr = uRawValue;
1162	Log(("GIM%u: HyperV: Set STIMER_CONFIG%u=%#RX64\n", pVCpu->idCpu, idxStimer, uRawValue));
1163
1164	/* Process the MSR bits. */
1165	if ( !MSR_GIM_HV_STIMER_GET_SINTX(uRawValue) /* Writing SINTx as 0 causes the timer to be disabled. */
1166	\|\| !MSR_GIM_HV_STIMER_IS_ENABLED(uRawValue))
1167	{
1168	pHvStimer->uStimerConfigMsr &= ~MSR_GIM_HV_STIMER_ENABLE;
1169	gimHvStopStimer(pVCpu, pHvStimer);
1170	Log(("GIM%u: HyperV: Disabled STIMER_CONFIG%u\n", pVCpu->idCpu, idxStimer));
1171	}
1172	else if (MSR_GIM_HV_STIMER_IS_ENABLED(uRawValue))
1173	{
1174	/* Auto-enable implies writing to the STIMERx_COUNT MSR is what starts the timer. */
1175	if (!MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(uRawValue))
1176	{
1177	if (!TMTimerIsActive(pVM, pHvStimer->hTimer))
1178	{
1179	gimHvStartStimer(pVCpu, pHvStimer);
1180	Log(("GIM%u: HyperV: Started STIMER%u\n", pVCpu->idCpu, idxStimer));
1181	}
1182	else
1183	{
1184	/*
1185	* Enabling a timer that's already enabled is undefined behaviour,
1186	* see Hyper-V spec. 15.3.1 "Synthetic Timer Configuration Register".
1187	*
1188	* Our implementation just re-starts the timer. Guests that comform to
1189	* the Hyper-V specs. should not be doing this anyway.
1190	*/
1191	AssertFailed();
1192	gimHvStopStimer(pVCpu, pHvStimer);
1193	gimHvStartStimer(pVCpu, pHvStimer);
1194	}
1195	}
1196	}
1197
1198	TMTimerUnlock(pVM, pHvStimer->hTimer);
1199	}
1200	return rc;
1201	}
1202	#ifndef IN_RING3
1203	return VINF_CPUM_R3_MSR_WRITE;
1204	#else
1205	LogRel(("GIM%u: HyperV: Setting reserved bits of STIMER%u MSR (uRawValue=%#RX64) -> #GP(0)\n", pVCpu->idCpu,
1206	idxStimer, uRawValue));
1207	return VERR_CPUM_RAISE_GP_0;
1208	#endif
1209	}
1210
1211	case MSR_GIM_HV_STIMER0_COUNT:
1212	case MSR_GIM_HV_STIMER1_COUNT:
1213	case MSR_GIM_HV_STIMER2_COUNT:
1214	case MSR_GIM_HV_STIMER3_COUNT:
1215	{
1216	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1217	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
1218	Assert(idxStimer < RT_ELEMENTS(pHvCpu->aStimers));
1219	PGIMHVSTIMER pHvStimer = &pHvCpu->aStimers[idxStimer];
1220	int const rcBusy = VINF_CPUM_R3_MSR_WRITE;
1221
1222	/*
1223	* Writing zero to this MSR disables the timer regardless of whether the auto-enable
1224	* flag is set in the config MSR corresponding to the timer.
1225	*/
1226	if (!uRawValue)
1227	{
1228	gimHvStopStimer(pVCpu, pHvStimer);
1229	pHvStimer->uStimerCountMsr = 0;
1230	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64, stopped timer\n", pVCpu->idCpu, idxStimer, uRawValue));
1231	return VINF_SUCCESS;
1232	}
1233
1234	/*
1235	* Concurrent writes to the config. MSR can't happen as it's serialized by way
1236	* of being done on the same EMT as this.
1237	*/
1238	if (MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(pHvStimer->uStimerConfigMsr))
1239	{
1240	int rc = TMTimerLock(pVM, pHvStimer->hTimer, rcBusy);
1241	if (rc == VINF_SUCCESS)
1242	{
1243	pHvStimer->uStimerCountMsr = uRawValue;
1244	gimHvStartStimer(pVCpu, pHvStimer);
1245	TMTimerUnlock(pVM, pHvStimer->hTimer);
1246	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64 %RU64 msec, auto-started timer\n", pVCpu->idCpu, idxStimer,
1247	uRawValue, (uRawValue * 100) / RT_NS_1MS_64));
1248	}
1249	return rc;
1250	}
1251
1252	/* Simple update of the counter without any timer start/stop side-effects. */
1253	pHvStimer->uStimerCountMsr = uRawValue;
1254	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64\n", pVCpu->idCpu, idxStimer, uRawValue));
1255	return VINF_SUCCESS;
1256	}
1257
1258	case MSR_GIM_HV_EOM:
1259	{
1260	/** @todo implement EOM. */
1261	Log(("GIM%u: HyperV: EOM\n", pVCpu->idCpu));
1262	return VINF_SUCCESS;
1263	}
1264
1265	case MSR_GIM_HV_SIEFP:
1266	{
1267	#ifndef IN_RING3
1268	return VINF_CPUM_R3_MSR_WRITE;
1269	#else
1270	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1271	pHvCpu->uSiefpMsr = uRawValue;
1272	if (MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(uRawValue))
1273	{
1274	RTGCPHYS GCPhysSiefPage = MSR_GIM_HV_SIEF_GUEST_PFN(uRawValue) << GUEST_PAGE_SHIFT;
1275	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSiefPage))
1276	{
1277	int rc = gimR3HvEnableSiefPage(pVCpu, GCPhysSiefPage);
1278	if (RT_SUCCESS(rc))
1279	{
1280	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt event flags page at %#RGp\n", pVCpu->idCpu,
1281	GCPhysSiefPage));
1282	/** @todo SIEF setup. */
1283	return VINF_SUCCESS;
1284	}
1285	}
1286	else
1287	LogRelMax(5, ("GIM%u: HyperV: SIEF page address %#RGp invalid!\n", pVCpu->idCpu, GCPhysSiefPage));
1288	}
1289	else
1290	gimR3HvDisableSiefPage(pVCpu);
1291
1292	return VERR_CPUM_RAISE_GP_0;
1293	#endif
1294	break;
1295	}
1296
1297	case MSR_GIM_HV_SIMP:
1298	{
1299	#ifndef IN_RING3
1300	return VINF_CPUM_R3_MSR_WRITE;
1301	#else
1302	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1303	pHvCpu->uSimpMsr = uRawValue;
1304	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
1305	{
1306	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
1307	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
1308	{
1309	uint8_t abSimp[GIM_HV_PAGE_SIZE];
1310	RT_ZERO(abSimp);
1311	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
1312	if (RT_SUCCESS(rc2))
1313	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt message page at %#RGp\n", pVCpu->idCpu, GCPhysSimp));
1314	else
1315	{
1316	LogRel(("GIM%u: HyperV: Failed to update synthetic interrupt message page at %#RGp. uSimpMsr=%#RX64 rc=%Rrc\n",
1317	pVCpu->idCpu, pHvCpu->uSimpMsr, GCPhysSimp, rc2));
1318	return VERR_CPUM_RAISE_GP_0;
1319	}
1320	}
1321	else
1322	{
1323	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n", pVCpu->idCpu,
1324	GCPhysSimp));
1325	}
1326	}
1327	else
1328	LogRel(("GIM%u: HyperV: Disabled synthetic interrupt message page\n", pVCpu->idCpu));
1329	return VINF_SUCCESS;
1330	#endif
1331	}
1332
1333	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
1334	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
1335	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
1336	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
1337	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
1338
1339	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
1340	case MSR_GIM_HV_VP_INDEX:
1341	case MSR_GIM_HV_TSC_FREQ:
1342	case MSR_GIM_HV_APIC_FREQ:
1343	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
1344	break;
1345
1346	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
1347	{
1348	if (pHv->fIsVendorMsHv)
1349	{
1350	#ifndef IN_RING3
1351	return VINF_CPUM_R3_MSR_WRITE;
1352	#else
1353	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
1354	return VINF_SUCCESS;
1355	#endif
1356	}
1357	return VERR_CPUM_RAISE_GP_0;
1358	}
1359
1360	default:
1361	{
1362	#ifdef IN_RING3
1363	static uint32_t s_cTimes = 0;
1364	if (s_cTimes++ < 20)
1365	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
1366	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
1367	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
1368	break;
1369	#else
1370	return VINF_CPUM_R3_MSR_WRITE;
1371	#endif
1372	}
1373	}
1374
1375	return VERR_CPUM_RAISE_GP_0;
1376	}
1377
1378
1379	/**
1380	* Whether we need to trap \#UD exceptions in the guest.
1381	*
1382	* We only needed to trap \#UD exceptions for the old raw-mode guests when
1383	* hypercalls are enabled. For HM VMs, the hypercall would be handled via the
1384	* VMCALL/VMMCALL VM-exit.
1385	*
1386	* @param pVCpu The cross context virtual CPU structure.
1387	*/
1388	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
1389	{
1390	RT_NOREF(pVCpu);
1391	return false;
1392	}
1393
1394
1395	/**
1396	* Checks the instruction and executes the hypercall if it's a valid hypercall
1397	* instruction.
1398	*
1399	* This interface is used by \#UD handlers and IEM.
1400	*
1401	* @returns Strict VBox status code.
1402	* @param pVCpu The cross context virtual CPU structure.
1403	* @param pCtx Pointer to the guest-CPU context.
1404	* @param uDisOpcode The disassembler opcode.
1405	* @param cbInstr The instruction length.
1406	*
1407	* @thread EMT(pVCpu).
1408	*/
1409	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercallEx(PVMCPUCC pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr)
1410	{
1411	Assert(pVCpu);
1412	Assert(pCtx);
1413	VMCPU_ASSERT_EMT(pVCpu);
1414
1415	PVM pVM = pVCpu->CTX_SUFF(pVM);
1416	CPUMCPUVENDOR const enmGuestCpuVendor = (CPUMCPUVENDOR)pVM->cpum.ro.GuestFeatures.enmCpuVendor;
1417	if ( ( uDisOpcode == OP_VMCALL
1418	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1419	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA
1420	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_SHANGHAI))
1421	\|\| ( uDisOpcode == OP_VMMCALL
1422	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_AMD
1423	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_HYGON)) )
1424	return gimHvHypercall(pVCpu, pCtx);
1425
1426	RT_NOREF_PV(cbInstr);
1427	return VERR_GIM_INVALID_HYPERCALL_INSTR;
1428	}
1429
1430
1431	/**
1432	* Exception handler for \#UD.
1433	*
1434	* @returns Strict VBox status code.
1435	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
1436	* failed).
1437	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
1438	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
1439	* RIP.
1440	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
1441	* @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
1442	* hypercall instruction.
1443	*
1444	* @param pVCpu The cross context virtual CPU structure.
1445	* @param pCtx Pointer to the guest-CPU context.
1446	* @param pDis Pointer to the disassembled instruction state at RIP.
1447	* Optional, can be NULL.
1448	* @param pcbInstr Where to store the instruction length of the hypercall
1449	* instruction. Optional, can be NULL.
1450	*
1451	* @thread EMT(pVCpu).
1452	*/
1453	VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPUCC pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
1454	{
1455	VMCPU_ASSERT_EMT(pVCpu);
1456
1457	/*
1458	* If we didn't ask for #UD to be trapped, bail.
1459	*/
1460	if (!gimHvShouldTrapXcptUD(pVCpu))
1461	return VERR_GIM_IPE_1;
1462
1463	if (!pDis)
1464	{
1465	/*
1466	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1467	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1468	*/
1469	unsigned cbInstr;
1470	DISCPUSTATE Dis;
1471	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, &Dis, &cbInstr);
1472	if (RT_SUCCESS(rc))
1473	{
1474	if (pcbInstr)
1475	*pcbInstr = (uint8_t)cbInstr;
1476	return gimHvHypercallEx(pVCpu, pCtx, Dis.pCurInstr->uOpcode, Dis.cbInstr);
1477	}
1478
1479	Log(("GIM: HyperV: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
1480	return rc;
1481	}
1482
1483	return gimHvHypercallEx(pVCpu, pCtx, pDis->pCurInstr->uOpcode, pDis->cbInstr);
1484	}
1485

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 94620

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