GIMAllHv.cpp@ 62596

Last change on this file since 62596 was 62540, checked in by vboxsync, 8 years ago
VMM/GIM/HyperV: Synthetic interrupt controller bits.
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1	/* $Id: GIMAllHv.cpp 62540 2016-07-25 09:31:02Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include <VBox/vmm/gim.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/tm.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include <VBox/vmm/pgm.h>
31	#include "GIMHvInternal.h"
32	#include "GIMInternal.h"
33	#include <VBox/vmm/vm.h>
34
35	#include <VBox/err.h>
36
37	#include <iprt/asm-amd64-x86.h>
38	#ifdef IN_RING3
39	# include <iprt/mem.h>
40	#endif
41
42
43	#ifdef IN_RING3
44	/**
45	* Read and validate slow hypercall parameters.
46	*
47	* @returns VBox status code.
48	* @param pVM The cross context VM structure.
49	* @param pCtx Pointer to the guest-CPU context.
50	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
51	* @param enmParam The hypercall parameter type.
52	* @param prcHv Where to store the Hyper-V status code. Only valid
53	* to the caller when this function returns
54	* VINF_SUCCESS.
55	*/
56	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
57	{
58	int rc = VINF_SUCCESS;
59	PGIMHV pHv = &pVM->gim.s.u.Hv;
60	RTGCPHYS GCPhysParam;
61	void *pvDst;
62	if (enmParam == GIMHVHYPERCALLPARAM_IN)
63	{
64	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
65	pvDst = pHv->pbHypercallIn;
66	pHv->GCPhysHypercallIn = GCPhysParam;
67	}
68	else
69	{
70	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
71	pvDst = pHv->pbHypercallOut;
72	pHv->GCPhysHypercallOut = GCPhysParam;
73	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
74	}
75
76	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
77	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
78	{
79	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
80	{
81	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
82	if (RT_SUCCESS(rc))
83	{
84	*prcHv = GIM_HV_STATUS_SUCCESS;
85	return VINF_SUCCESS;
86	}
87	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
88	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
89	}
90	else
91	{
92	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
93	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
94	}
95	}
96	else
97	{
98	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
99	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
100	}
101	return rc;
102	}
103
104
105	/**
106	* Helper for reading and validating slow hypercall input and output parameters.
107	*
108	* @returns VBox status code.
109	* @param pVM The cross context VM structure.
110	* @param pCtx Pointer to the guest-CPU context.
111	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
112	* @param prcHv Where to store the Hyper-V status code. Only valid
113	* to the caller when this function returns
114	* VINF_SUCCESS.
115	*/
116	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
117	{
118	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
119	if ( RT_SUCCESS(rc)
120	&& *prcHv == GIM_HV_STATUS_SUCCESS)
121	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
122	return rc;
123	}
124	#endif
125
126
127	/**
128	* Handles all Hyper-V hypercalls.
129	*
130	* @returns Strict VBox status code.
131	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
132	* failed).
133	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
134	* @retval VERR_GIM_HYPERCALLS_NOT_ENABLED hypercalls are disabled by the
135	* guest.
136	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
137	* @retval VERR_GIM_HYPERCALL_MEMORY_READ_FAILED hypercall failed while reading
138	* memory.
139	* @retval VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED hypercall failed while
140	* writing memory.
141	*
142	* @param pVCpu The cross context virtual CPU structure.
143	* @param pCtx Pointer to the guest-CPU context.
144	*
145	* @thread EMT(pVCpu).
146	*/
147	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
148	{
149	VMCPU_ASSERT_EMT(pVCpu);
150
151	#ifndef IN_RING3
152	return VINF_GIM_R3_HYPERCALL;
153	#else
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
156
157	/*
158	* Verify that hypercalls are enabled by the guest.
159	*/
160	if (!gimHvAreHypercallsEnabled(pVCpu))
161	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
162
163	/*
164	* Verify guest is in ring-0 protected mode.
165	*/
166	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
167	if ( uCpl
168	\|\| CPUMIsGuestInRealModeEx(pCtx))
169	{
170	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
171	}
172
173	/*
174	* Get the hypercall operation code and modes.
175	*/
176	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
177	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
178	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
179	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
180	const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn);
181	const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn);
182	uint64_t cHyperRepsDone = 0;
183
184	int rc = VINF_SUCCESS;
185	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
186	PGIMHV pHv = &pVM->gim.s.u.Hv;
187
188	/*
189	* Validate common hypercall input parameters.
190	*/
191	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
192	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
193	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
194	{
195	/*
196	* Perform the hypercall.
197	*/
198	switch (uHyperOp)
199	{
200	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
201	{
202	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
203	{
204	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
205	if ( RT_SUCCESS(rc)
206	&& rcHv == GIM_HV_STATUS_SUCCESS)
207	{
208	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
209	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
210	if (RT_FAILURE(rc))
211	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
212	}
213	}
214	else
215	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
216	break;
217	}
218
219	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
220	{
221	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
222	{
223	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
224	if ( RT_SUCCESS(rc)
225	&& rcHv == GIM_HV_STATUS_SUCCESS)
226	{
227	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
228	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
229	if (RT_FAILURE(rc))
230	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
231	}
232	}
233	else
234	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
235	break;
236	}
237
238	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
239	{
240	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
241	{
242	uint32_t fFlags = 0;
243	if (!fHyperFast)
244	{
245	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
246	if ( RT_SUCCESS(rc)
247	&& rcHv == GIM_HV_STATUS_SUCCESS)
248	{
249	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
250	fFlags = pIn->fFlags;
251	}
252	}
253	else
254	{
255	rcHv = GIM_HV_STATUS_SUCCESS;
256	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
257	}
258
259	/*
260	* Nothing to flush on the sending side as we don't maintain our own buffers.
261	*/
262	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
263	if (rcHv == GIM_HV_STATUS_SUCCESS)
264	{
265	if (fFlags)
266	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
267	else
268	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
269	}
270	}
271	else
272	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
273	break;
274	}
275
276	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
277	{
278	if (pHv->fIsInterfaceVs)
279	{
280	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
281	if ( RT_SUCCESS(rc)
282	&& rcHv == GIM_HV_STATUS_SUCCESS)
283	{
284	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
285	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
286	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
287	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
288	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->auSintXMsr[GIM_HV_VMBUS_MSG_SINT])
289	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
290	{
291	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
292	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
293	{
294	/*
295	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
296	*/
297	GIMHVMSG HvMsg;
298	RT_ZERO(HvMsg);
299	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
300	HvMsg.MsgHdr.cbPayload = 0xf;
301	HvMsg.aPayload[0] = 0xf;
302	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
303	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
304	if (RT_SUCCESS(rc2))
305	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
306	else
307	{
308	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
309	offMsg, rc));
310	}
311	}
312	}
313
314	/*
315	* Make the call fail after updating the SIMP, so the guest can go back to using
316	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
317	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
318	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
319	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
320	*/
321	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
322	}
323	else
324	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
325	}
326	else
327	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
328	break;
329	}
330
331	default:
332	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
333	break;
334	}
335	}
336	else
337	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
338
339	/*
340	* Update the guest with results of the hypercall.
341	*/
342	if (RT_SUCCESS(rc))
343	{
344	if (fIs64BitMode)
345	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
346	else
347	{
348	pCtx->edx = cHyperRepsDone;
349	pCtx->eax = rcHv;
350	}
351	}
352
353	return rc;
354	#endif
355	}
356
357
358	/**
359	* Returns whether the guest has configured and enabled the use of Hyper-V's
360	* hypercall interface.
361	*
362	* @returns true if hypercalls are enabled, false otherwise.
363	* @param pVCpu The cross context virtual CPU structure.
364	*/
365	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
366	{
367	return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
368	}
369
370
371	/**
372	* Returns whether the guest has configured and enabled the use of Hyper-V's
373	* paravirtualized TSC.
374	*
375	* @returns true if paravirt. TSC is enabled, false otherwise.
376	* @param pVM The cross context VM structure.
377	*/
378	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
379	{
380	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
381	}
382
383
384	#ifdef IN_RING3
385	/**
386	* Gets the descriptive OS ID variant as identified via the
387	* MSR_GIM_HV_GUEST_OS_ID MSR.
388	*
389	* @returns The name.
390	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
391	*/
392	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
393	{
394	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
395	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
396	if (uVendor == 1 /* Microsoft */)
397	{
398	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
399	switch (uOsVariant)
400	{
401	case 0: return "Undefined";
402	case 1: return "MS-DOS";
403	case 2: return "Windows 3.x";
404	case 3: return "Windows 9x";
405	case 4: return "Windows NT or derivative";
406	case 5: return "Windows CE";
407	default: return "Unknown";
408	}
409	}
410	return "Unknown";
411	}
412	#endif
413
414
415	/**
416	* MSR read handler for Hyper-V.
417	*
418	* @returns Strict VBox status code like CPUMQueryGuestMsr().
419	* @retval VINF_CPUM_R3_MSR_READ
420	* @retval VERR_CPUM_RAISE_GP_0
421	*
422	* @param pVCpu The cross context virtual CPU structure.
423	* @param idMsr The MSR being read.
424	* @param pRange The range this MSR belongs to.
425	* @param puValue Where to store the MSR value read.
426	*
427	* @thread EMT.
428	*/
429	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
430	{
431	NOREF(pRange);
432	PVM pVM = pVCpu->CTX_SUFF(pVM);
433	PGIMHV pHv = &pVM->gim.s.u.Hv;
434
435	switch (idMsr)
436	{
437	case MSR_GIM_HV_TIME_REF_COUNT:
438	{
439	/* Hyper-V reports the time in 100 ns units (10 MHz). */
440	uint64_t u64Tsc = TMCpuTickGet(pVCpu);
441	uint64_t u64TscHz = pHv->cTscTicksPerSecond;
442	uint64_t u64Tsc100Ns = u64TscHz / UINT64_C(10000000); /* 100 ns */
443	*puValue = (u64Tsc / u64Tsc100Ns);
444	return VINF_SUCCESS;
445	}
446
447	case MSR_GIM_HV_VP_INDEX:
448	*puValue = pVCpu->idCpu;
449	return VINF_SUCCESS;
450
451	case MSR_GIM_HV_TPR:
452	return PDMApicReadMsr(pVCpu, MSR_IA32_X2APIC_TPR, puValue);
453
454	case MSR_GIM_HV_ICR:
455	return PDMApicReadMsr(pVCpu, MSR_IA32_X2APIC_ICR, puValue);
456
457	case MSR_GIM_HV_GUEST_OS_ID:
458	*puValue = pHv->u64GuestOsIdMsr;
459	return VINF_SUCCESS;
460
461	case MSR_GIM_HV_HYPERCALL:
462	*puValue = pHv->u64HypercallMsr;
463	return VINF_SUCCESS;
464
465	case MSR_GIM_HV_REF_TSC:
466	*puValue = pHv->u64TscPageMsr;
467	return VINF_SUCCESS;
468
469	case MSR_GIM_HV_TSC_FREQ:
470	*puValue = TMCpuTicksPerSecond(pVM);
471	return VINF_SUCCESS;
472
473	case MSR_GIM_HV_APIC_FREQ:
474	{
475	int rc = PDMApicGetTimerFreq(pVM, puValue);
476	if (RT_FAILURE(rc))
477	return VERR_CPUM_RAISE_GP_0;
478	return VINF_SUCCESS;
479	}
480
481	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
482	*puValue = pHv->uDbgStatusMsr;
483	return VINF_SUCCESS;
484
485	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
486	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
487	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
488	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
489	{
490	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
491	*puValue = pHvCpu->auSintXMsr[idMsr - MSR_GIM_HV_SINT0];
492	return VINF_SUCCESS;
493	}
494
495	case MSR_GIM_HV_SIMP:
496	{
497	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
498	*puValue = pHvCpu->uSimpMsr;
499	return VINF_SUCCESS;
500	}
501
502	case MSR_GIM_HV_SVERSION:
503	*puValue = GIM_HV_SVERSION;
504	return VINF_SUCCESS;
505
506	case MSR_GIM_HV_RESET:
507	*puValue = 0;
508	return VINF_SUCCESS;
509
510	case MSR_GIM_HV_CRASH_CTL:
511	*puValue = pHv->uCrashCtlMsr;
512	return VINF_SUCCESS;
513
514	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
515	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
516	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
517	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
518	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
519
520	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
521	{
522	if (pHv->fIsVendorMsHv)
523	{
524	#ifndef IN_RING3
525	return VINF_CPUM_R3_MSR_READ;
526	#else
527	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
528	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
529	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
530	return VINF_SUCCESS;
531	#endif
532	}
533	break;
534	}
535
536	/* Write-only MSRs: */
537	case MSR_GIM_HV_EOI:
538	/* Reserved/unknown MSRs: */
539	default:
540	{
541	#ifdef IN_RING3
542	static uint32_t s_cTimes = 0;
543	if (s_cTimes++ < 20)
544	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
545	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
546	break;
547	#else
548	return VINF_CPUM_R3_MSR_READ;
549	#endif
550	}
551	}
552
553	return VERR_CPUM_RAISE_GP_0;
554	}
555
556
557	/**
558	* MSR write handler for Hyper-V.
559	*
560	* @returns Strict VBox status code like CPUMSetGuestMsr().
561	* @retval VINF_CPUM_R3_MSR_WRITE
562	* @retval VERR_CPUM_RAISE_GP_0
563	*
564	* @param pVCpu The cross context virtual CPU structure.
565	* @param idMsr The MSR being written.
566	* @param pRange The range this MSR belongs to.
567	* @param uRawValue The raw value with the ignored bits not masked.
568	*
569	* @thread EMT.
570	*/
571	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
572	{
573	NOREF(pRange);
574	PVM pVM = pVCpu->CTX_SUFF(pVM);
575	PGIMHV pHv = &pVM->gim.s.u.Hv;
576
577	switch (idMsr)
578	{
579	case MSR_GIM_HV_TPR:
580	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_TPR, uRawValue);
581
582	case MSR_GIM_HV_EOI:
583	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_EOI, uRawValue);
584
585	case MSR_GIM_HV_ICR:
586	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_ICR, uRawValue);
587
588	case MSR_GIM_HV_GUEST_OS_ID:
589	{
590	#ifndef IN_RING3
591	return VINF_CPUM_R3_MSR_WRITE;
592	#else
593	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
594	if (!uRawValue)
595	{
596	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
597	{
598	gimR3HvDisableHypercallPage(pVM);
599	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE;
600	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
601	}
602	}
603	else
604	{
605	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
606	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
607	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
608	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
609	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
610	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
611
612	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
613	CPUMCPUIDLEAF HyperLeaf;
614	RT_ZERO(HyperLeaf);
615	HyperLeaf.uLeaf = UINT32_C(0x40000002);
616	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
617	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
618	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
619	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
620	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
621	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
622	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
623	AssertRC(rc2);
624	}
625
626	pHv->u64GuestOsIdMsr = uRawValue;
627
628	/*
629	* Notify VMM that hypercalls are now disabled/enabled.
630	*/
631	for (VMCPUID i = 0; i < pVM->cCpus; i++)
632	{
633	if (uRawValue)
634	VMMHypercallsEnable(&pVM->aCpus[i]);
635	else
636	VMMHypercallsDisable(&pVM->aCpus[i]);
637	}
638
639	return VINF_SUCCESS;
640	#endif /* IN_RING3 */
641	}
642
643	case MSR_GIM_HV_HYPERCALL:
644	{
645	#ifndef IN_RING3
646	return VINF_CPUM_R3_MSR_WRITE;
647	#else
648	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
649	* see @bugref{7270#c116}. */
650	/* First, update all but the hypercall page enable bit. */
651	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE);
652
653	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
654	bool fEnable = MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(uRawValue);
655	if ( fEnable
656	&& !gimHvAreHypercallsEnabled(pVCpu))
657	{
658	return VINF_SUCCESS;
659	}
660
661	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
662	if (!fEnable)
663	{
664	gimR3HvDisableHypercallPage(pVM);
665	pHv->u64HypercallMsr = uRawValue;
666	return VINF_SUCCESS;
667	}
668
669	/* Enable the hypercall-page. */
670	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
671	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
672	if (RT_SUCCESS(rc))
673	{
674	pHv->u64HypercallMsr = uRawValue;
675	return VINF_SUCCESS;
676	}
677
678	return VERR_CPUM_RAISE_GP_0;
679	#endif
680	}
681
682	case MSR_GIM_HV_REF_TSC:
683	{
684	#ifndef IN_RING3
685	return VINF_CPUM_R3_MSR_WRITE;
686	#else /* IN_RING3 */
687	/* First, update all but the TSC page enable bit. */
688	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE);
689
690	/* Is the guest disabling the TSC page? */
691	bool fEnable = MSR_GIM_HV_REF_TSC_IS_ENABLED(uRawValue);
692	if (!fEnable)
693	{
694	gimR3HvDisableTscPage(pVM);
695	pHv->u64TscPageMsr = uRawValue;
696	return VINF_SUCCESS;
697	}
698
699	/* Enable the TSC page. */
700	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
701	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
702	if (RT_SUCCESS(rc))
703	{
704	pHv->u64TscPageMsr = uRawValue;
705	return VINF_SUCCESS;
706	}
707
708	return VERR_CPUM_RAISE_GP_0;
709	#endif /* IN_RING3 */
710	}
711
712	case MSR_GIM_HV_APIC_ASSIST_PAGE:
713	{
714	#ifndef IN_RING3
715	return VINF_CPUM_R3_MSR_WRITE;
716	#else /* IN_RING3 */
717	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
718	pHvCpu->uApicAssistPageMsr = uRawValue;
719
720	if (MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(uRawValue))
721	{
722	RTGCPHYS GCPhysApicAssistPage = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << PAGE_SHIFT;
723	if (PGMPhysIsGCPhysNormal(pVM, GCPhysApicAssistPage))
724	{
725	int rc = gimR3HvEnableApicAssistPage(pVCpu, GCPhysApicAssistPage);
726	if (RT_SUCCESS(rc))
727	{
728	pHvCpu->uApicAssistPageMsr = uRawValue;
729	return VINF_SUCCESS;
730	}
731	}
732	else
733	{
734	LogRelMax(5, ("GIM: HyperV%u: APIC-assist page address %#RGp invalid!\n", pVCpu->idCpu,
735	GCPhysApicAssistPage));
736	}
737	}
738	else
739	gimR3HvDisableApicAssistPage(pVCpu);
740
741	return VERR_CPUM_RAISE_GP_0;
742	#endif /* IN_RING3 */
743	}
744
745	case MSR_GIM_HV_RESET:
746	{
747	#ifndef IN_RING3
748	return VINF_CPUM_R3_MSR_WRITE;
749	#else
750	if (MSR_GIM_HV_RESET_IS_ENABLED(uRawValue))
751	{
752	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
753	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3, PDMVMRESET_F_GIM);
754	AssertRC(rc); /* Note! Not allowed to return VINF_EM_RESET / VINF_EM_HALT here, so ignore them. */
755	}
756	/* else: Ignore writes to other bits. */
757	return VINF_SUCCESS;
758	#endif /* IN_RING3 */
759	}
760
761	case MSR_GIM_HV_CRASH_CTL:
762	{
763	#ifndef IN_RING3
764	return VINF_CPUM_R3_MSR_WRITE;
765	#else
766	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY)
767	{
768	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
769	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
770
771	if (DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_BSOD_MSR))
772	DBGFEventGenericWithArg(pVM, pVCpu, DBGFEVENT_BSOD_MSR, pHv->uCrashP0Msr, DBGFEVENTCTX_OTHER);
773	/* (Do not try pass VINF_EM_DBG_EVENT, doesn't work from here!) */
774	}
775	return VINF_SUCCESS;
776	#endif
777	}
778
779	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
780	{
781	if (!pHv->fDbgEnabled)
782	return VERR_CPUM_RAISE_GP_0;
783	#ifndef IN_RING3
784	return VINF_CPUM_R3_MSR_WRITE;
785	#else
786	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
787	pHv->uDbgSendBufferMsr = GCPhysBuffer;
788	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
789	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
790	else
791	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
792	pHv->uDbgSendBufferMsr = uRawValue;
793	return VINF_SUCCESS;
794	#endif
795	}
796
797	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
798	{
799	if (!pHv->fDbgEnabled)
800	return VERR_CPUM_RAISE_GP_0;
801	#ifndef IN_RING3
802	return VINF_CPUM_R3_MSR_WRITE;
803	#else
804	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
805	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
806	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
807	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
808	else
809	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
810	return VINF_SUCCESS;
811	#endif
812	}
813
814	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
815	{
816	if (!pHv->fDbgEnabled)
817	return VERR_CPUM_RAISE_GP_0;
818	#ifndef IN_RING3
819	return VINF_CPUM_R3_MSR_WRITE;
820	#else
821	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
822	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
823	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
824	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
825	else
826	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
827	return VINF_SUCCESS;
828	#endif
829	}
830
831	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
832	{
833	if (!pHv->fDbgEnabled)
834	return VERR_CPUM_RAISE_GP_0;
835	#ifndef IN_RING3
836	return VINF_CPUM_R3_MSR_WRITE;
837	#else
838	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
839	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
840	{
841	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
842	return VERR_CPUM_RAISE_GP_0;
843	}
844
845	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
846	{
847	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
848	if ( cbWrite > 0
849	&& cbWrite < GIM_HV_PAGE_SIZE)
850	{
851	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
852	{
853	Assert(pHv->pvDbgBuffer);
854	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
855	if (RT_SUCCESS(rc))
856	{
857	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
858	uint32_t cbWritten = 0;
859	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
860	if ( RT_SUCCESS(rc)
861	&& cbWrite == cbWritten)
862	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS;
863	else
864	pHv->uDbgStatusMsr = 0;
865	}
866	else
867	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
868	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
869	}
870	else
871	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
872	(RTGCPHYS)pHv->uDbgSendBufferMsr));
873	}
874	else
875	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
876	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
877	}
878	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
879	{
880	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
881	{
882	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
883	uint32_t cbReallyRead;
884	Assert(pHv->pvDbgBuffer);
885	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, PAGE_SIZE, PAGE_SIZE, &cbReallyRead, 0, false /fUdpPkt/);
886	if ( RT_SUCCESS(rc)
887	&& cbReallyRead > 0)
888	{
889	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
890	if (RT_SUCCESS(rc))
891	{
892	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
893	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS;
894	}
895	else
896	{
897	pHv->uDbgStatusMsr = 0;
898	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
899	}
900	}
901	else
902	pHv->uDbgStatusMsr = 0;
903	}
904	else
905	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n", (RTGCPHYS)pHv->uDbgRecvBufferMsr));
906	}
907	return VINF_SUCCESS;
908	#endif
909	}
910
911	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
912	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
913	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
914	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
915	{
916	#ifndef IN_RING3
917	/** @todo make this RZ later? */
918	return VINF_CPUM_R3_MSR_WRITE;
919	#else
920	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
921	uint8_t uVector = MSR_GIM_HV_SINT_VECTOR(uRawValue);
922	bool const fVMBusMsg = RT_BOOL(idMsr == GIM_HV_VMBUS_MSG_SINT);
923	size_t const idxSintMsr = idMsr - MSR_GIM_HV_SINT0;
924	const char *pszDesc = fVMBusMsg ? "VMBus Message" : "Generic";
925	if (uVector < GIM_HV_SINT_VECTOR_VALID_MIN)
926	{
927	LogRel(("GIM: HyperV%u: Programmed an invalid vector in SINT%u (%s), uVector=%u -> #GP(0)\n", pVCpu->idCpu,
928	idxSintMsr, pszDesc, uVector));
929	return VERR_CPUM_RAISE_GP_0;
930	}
931
932	pHvCpu->auSintXMsr[idxSintMsr] = uRawValue;
933	if (fVMBusMsg)
934	{
935	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
936	LogRel(("GIM: HyperV%u: Masked SINT%u (%s)\n", pVCpu->idCpu, idxSintMsr, pszDesc));
937	else
938	LogRel(("GIM: HyperV%u: Unmasked SINT%u (%s), uVector=%u\n", pVCpu->idCpu, idxSintMsr, pszDesc, uVector));
939	}
940	return VINF_SUCCESS;
941	#endif
942	}
943
944	case MSR_GIM_HV_SIEFP:
945	{
946	#ifndef IN_RING3
947	return VINF_CPUM_R3_MSR_WRITE;
948	#else
949	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
950	pHvCpu->uSiefpMsr = uRawValue;
951	if (MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(uRawValue))
952	{
953	RTGCPHYS GCPhysSiefPage = MSR_GIM_HV_SIEF_GUEST_PFN(uRawValue) << PAGE_SHIFT;
954	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSiefPage))
955	{
956	int rc = gimR3HvEnableSiefPage(pVCpu, GCPhysSiefPage);
957	if (RT_SUCCESS(rc))
958	{
959	/** @todo SIEF setup. */
960	return VINF_SUCCESS;
961	}
962	}
963	else
964	LogRelMax(5, ("GIM: HyperV%u: SIEF page address %#RGp invalid!\n", pVCpu->idCpu, GCPhysSiefPage));
965	}
966	else
967	gimR3HvDisableSiefPage(pVCpu);
968
969	return VERR_CPUM_RAISE_GP_0;
970	#endif
971	break;
972	}
973
974	case MSR_GIM_HV_SIMP:
975	{
976	if (!pHv->fDbgEnabled)
977	return VERR_CPUM_RAISE_GP_0;
978	#ifndef IN_RING3
979	return VINF_CPUM_R3_MSR_WRITE;
980	#else
981	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
982	pHvCpu->uSimpMsr = uRawValue;
983	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
984	{
985	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
986	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
987	{
988	uint8_t abSimp[PAGE_SIZE];
989	RT_ZERO(abSimp);
990	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
991	if (RT_SUCCESS(rc2))
992	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at %#RGp\n", GCPhysSimp));
993	else
994	{
995	LogRel(("GIM: HyperV: WrMsr on MSR_GIM_HV_SIMP failed to update SIMP at %#RGp rc=%Rrc -> #GP(0)\n",
996	GCPhysSimp, rc2));
997	return VERR_CPUM_RAISE_GP_0;
998	}
999	}
1000	else
1001	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n",GCPhysSimp));
1002	}
1003	else
1004	LogRel(("GIM: HyperV: Disabled synthetic interrupt message page\n"));
1005	return VINF_SUCCESS;
1006	#endif
1007	}
1008
1009	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
1010	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
1011	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
1012	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
1013	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
1014
1015	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
1016	case MSR_GIM_HV_VP_INDEX:
1017	case MSR_GIM_HV_TSC_FREQ:
1018	case MSR_GIM_HV_APIC_FREQ:
1019	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
1020	break;
1021
1022	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
1023	{
1024	if (pHv->fIsVendorMsHv)
1025	{
1026	#ifndef IN_RING3
1027	return VINF_CPUM_R3_MSR_WRITE;
1028	#else
1029	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
1030	return VINF_SUCCESS;
1031	#endif
1032	}
1033	return VERR_CPUM_RAISE_GP_0;
1034	}
1035
1036	default:
1037	{
1038	#ifdef IN_RING3
1039	static uint32_t s_cTimes = 0;
1040	if (s_cTimes++ < 20)
1041	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
1042	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
1043	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
1044	break;
1045	#else
1046	return VINF_CPUM_R3_MSR_WRITE;
1047	#endif
1048	}
1049	}
1050
1051	return VERR_CPUM_RAISE_GP_0;
1052	}
1053
1054
1055	/**
1056	* Whether we need to trap \#UD exceptions in the guest.
1057	*
1058	* We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
1059	* enabled. For HM VMs, the hypercall would be handled via the
1060	* VMCALL/VMMCALL VM-exit.
1061	*
1062	* @param pVCpu The cross context virtual CPU structure.
1063	*/
1064	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
1065	{
1066	PVM pVM = pVCpu->CTX_SUFF(pVM);
1067	if ( !HMIsEnabled(pVM)
1068	&& gimHvAreHypercallsEnabled(pVCpu))
1069	return true;
1070	return false;
1071	}
1072
1073
1074	/**
1075	* Checks the currently disassembled instruction and executes the hypercall if
1076	* it's a hypercall instruction.
1077	*
1078	* @returns Strict VBox status code.
1079	* @param pVCpu The cross context virtual CPU structure.
1080	* @param pCtx Pointer to the guest-CPU context.
1081	* @param pDis Pointer to the disassembled instruction state at RIP.
1082	*
1083	* @thread EMT(pVCpu).
1084	*
1085	* @todo Make this function static when @bugref{7270#c168} is addressed.
1086	*/
1087	VMM_INT_DECL(VBOXSTRICTRC) gimHvExecHypercallInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
1088	{
1089	Assert(pVCpu);
1090	Assert(pCtx);
1091	Assert(pDis);
1092	VMCPU_ASSERT_EMT(pVCpu);
1093
1094	PVM pVM = pVCpu->CTX_SUFF(pVM);
1095	CPUMCPUVENDOR const enmGuestCpuVendor = CPUMGetGuestCpuVendor(pVM);
1096	if ( ( pDis->pCurInstr->uOpcode == OP_VMCALL
1097	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1098	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA))
1099	\|\| ( pDis->pCurInstr->uOpcode == OP_VMMCALL
1100	&& enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
1101	{
1102	return gimHvHypercall(pVCpu, pCtx);
1103	}
1104
1105	return VERR_GIM_INVALID_HYPERCALL_INSTR;
1106	}
1107
1108
1109	/**
1110	* Exception handler for \#UD.
1111	*
1112	* @returns Strict VBox status code.
1113	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
1114	* failed).
1115	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
1116	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
1117	* RIP.
1118	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
1119	* @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
1120	* hypercall instruction.
1121	*
1122	* @param pVCpu The cross context virtual CPU structure.
1123	* @param pCtx Pointer to the guest-CPU context.
1124	* @param pDis Pointer to the disassembled instruction state at RIP.
1125	* Optional, can be NULL.
1126	* @param pcbInstr Where to store the instruction length of the hypercall
1127	* instruction. Optional, can be NULL.
1128	*
1129	* @thread EMT(pVCpu).
1130	*/
1131	VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
1132	{
1133	VMCPU_ASSERT_EMT(pVCpu);
1134
1135	/*
1136	* If we didn't ask for #UD to be trapped, bail.
1137	*/
1138	if (!gimHvShouldTrapXcptUD(pVCpu))
1139	return VERR_GIM_IPE_1;
1140
1141	if (!pDis)
1142	{
1143	/*
1144	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1145	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1146	*/
1147	unsigned cbInstr;
1148	DISCPUSTATE Dis;
1149	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, &Dis, &cbInstr);
1150	if (RT_SUCCESS(rc))
1151	{
1152	if (pcbInstr)
1153	*pcbInstr = (uint8_t)cbInstr;
1154	return gimHvExecHypercallInstr(pVCpu, pCtx, &Dis);
1155	}
1156
1157	Log(("GIM: HyperV: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
1158	return rc;
1159	}
1160
1161	return gimHvExecHypercallInstr(pVCpu, pCtx, pDis);
1162	}
1163

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 62596

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