EMAll.cpp@ 60185

Last change on this file since 60185 was 58126, checked in by vboxsync, 9 years ago
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1	/* $Id: EMAll.cpp 58126 2015-10-08 20:59:48Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/selm.h>
26	#include <VBox/vmm/patm.h>
27	#include <VBox/vmm/csam.h>
28	#include <VBox/vmm/pgm.h>
29	#ifdef VBOX_WITH_IEM
30	# include <VBox/vmm/iem.h>
31	#endif
32	#include <VBox/vmm/iom.h>
33	#include <VBox/vmm/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/vmm.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/tm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42	#include <VBox/dis.h>
43	#include <VBox/disopcode.h>
44	#include <VBox/log.h>
45	#include "internal/pgm.h"
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50	#ifndef IN_RC
51	#undef VBOX_WITH_IEM
52	#endif
53	#ifdef VBOX_WITH_IEM
54	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
55	//# define VBOX_SAME_AS_EM
56	//# define VBOX_COMPARE_IEM_LAST
57	#endif
58
59	#ifdef VBOX_WITH_RAW_RING1
60	# define EM_EMULATE_SMSW
61	#endif
62
63
64	/*********************************************************************************************************************************
65	* Defined Constants And Macros *
66	*********************************************************************************************************************************/
67	/** @def EM_ASSERT_FAULT_RETURN
68	* Safety check.
69	*
70	* Could in theory misfire on a cross page boundary access...
71	*
72	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
73	* turns up an alias page instead of the original faulting one and annoying the
74	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
75	*/
76	#if 0
77	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
78	#else
79	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
80	#endif
81
82
83	/*********************************************************************************************************************************
84	* Internal Functions *
85	*********************************************************************************************************************************/
86	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
87	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
88	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
89	#endif
90
91
92	/*********************************************************************************************************************************
93	* Global Variables *
94	*********************************************************************************************************************************/
95	#ifdef VBOX_COMPARE_IEM_AND_EM
96	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
97	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
98	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
99	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
100	static uint32_t g_fIncomingFFs;
101	static CPUMCTX g_IncomingCtx;
102	static bool g_fIgnoreRaxRdx = false;
103
104	static uint32_t g_fEmFFs;
105	static CPUMCTX g_EmCtx;
106	static uint8_t g_abEmWrote[256];
107	static size_t g_cbEmWrote;
108
109	static uint32_t g_fIemFFs;
110	static CPUMCTX g_IemCtx;
111	extern uint8_t g_abIemWrote[256];
112	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
113	extern size_t g_cbIemWrote;
114	#else
115	static size_t g_cbIemWrote;
116	#endif
117	#endif
118
119
120	/**
121	* Get the current execution manager status.
122	*
123	* @returns Current status.
124	* @param pVCpu The cross context virtual CPU structure.
125	*/
126	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
127	{
128	return pVCpu->em.s.enmState;
129	}
130
131
132	/**
133	* Sets the current execution manager status. (use only when you know what you're doing!)
134	*
135	* @param pVCpu The cross context virtual CPU structure.
136	* @param enmNewState The new state, EMSTATE_WAIT_SIPI or EMSTATE_HALTED.
137	*/
138	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
139	{
140	/* Only allowed combination: */
141	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
142	pVCpu->em.s.enmState = enmNewState;
143	}
144
145
146	/**
147	* Sets the PC for which interrupts should be inhibited.
148	*
149	* @param pVCpu The cross context virtual CPU structure.
150	* @param PC The PC.
151	*/
152	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
153	{
154	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
155	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
156	}
157
158
159	/**
160	* Gets the PC for which interrupts should be inhibited.
161	*
162	* There are a few instructions which inhibits or delays interrupts
163	* for the instruction following them. These instructions are:
164	* - STI
165	* - MOV SS, r/m16
166	* - POP SS
167	*
168	* @returns The PC for which interrupts should be inhibited.
169	* @param pVCpu The cross context virtual CPU structure.
170	*
171	*/
172	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
173	{
174	return pVCpu->em.s.GCPtrInhibitInterrupts;
175	}
176
177
178	/**
179	* Prepare an MWAIT - essentials of the MONITOR instruction.
180	*
181	* @returns VINF_SUCCESS
182	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
183	* @param rax The content of RAX.
184	* @param rcx The content of RCX.
185	* @param rdx The content of RDX.
186	* @param GCPhys The physical address corresponding to rax.
187	*/
188	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
189	{
190	pVCpu->em.s.MWait.uMonitorRAX = rax;
191	pVCpu->em.s.MWait.uMonitorRCX = rcx;
192	pVCpu->em.s.MWait.uMonitorRDX = rdx;
193	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
194	/** @todo Make use of GCPhys. */
195	NOREF(GCPhys);
196	/** @todo Complete MONITOR implementation. */
197	return VINF_SUCCESS;
198	}
199
200
201	/**
202	* Performs an MWAIT.
203	*
204	* @returns VINF_SUCCESS
205	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
206	* @param rax The content of RAX.
207	* @param rcx The content of RCX.
208	*/
209	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
210	{
211	pVCpu->em.s.MWait.uMWaitRAX = rax;
212	pVCpu->em.s.MWait.uMWaitRCX = rcx;
213	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
214	if (rcx)
215	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
216	else
217	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
218	/** @todo not completely correct?? */
219	return VINF_EM_HALT;
220	}
221
222
223
224	/**
225	* Determine if we should continue after encountering a mwait instruction.
226	*
227	* Clears MWAIT flags if returning @c true.
228	*
229	* @returns true if we should continue, false if we should halt.
230	* @param pVCpu The cross context virtual CPU structure.
231	* @param pCtx Current CPU context.
232	*/
233	VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
234	{
235	if ( pCtx->eflags.Bits.u1IF
236	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
237	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
238	{
239	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
240	{
241	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
242	return true;
243	}
244	}
245
246	return false;
247	}
248
249
250	/**
251	* Determine if we should continue after encountering a hlt instruction.
252	*
253	* @returns true if we should continue, false if we should halt.
254	* @param pVCpu The cross context virtual CPU structure.
255	* @param pCtx Current CPU context.
256	*/
257	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
258	{
259	if (pCtx->eflags.Bits.u1IF)
260	return !!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
261	return false;
262	}
263
264
265	/**
266	* Locks REM execution to a single VCPU.
267	*
268	* @param pVM The cross context VM structure.
269	*/
270	VMMDECL(void) EMRemLock(PVM pVM)
271	{
272	#ifdef VBOX_WITH_REM
273	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
274	return; /* early init */
275
276	Assert(!PGMIsLockOwner(pVM));
277	Assert(!IOMIsLockWriteOwner(pVM));
278	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
279	AssertRCSuccess(rc);
280	#endif
281	}
282
283
284	/**
285	* Unlocks REM execution
286	*
287	* @param pVM The cross context VM structure.
288	*/
289	VMMDECL(void) EMRemUnlock(PVM pVM)
290	{
291	#ifdef VBOX_WITH_REM
292	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
293	return; /* early init */
294
295	PDMCritSectLeave(&pVM->em.s.CritSectREM);
296	#endif
297	}
298
299
300	/**
301	* Check if this VCPU currently owns the REM lock.
302	*
303	* @returns bool owner/not owner
304	* @param pVM The cross context VM structure.
305	*/
306	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
307	{
308	#ifdef VBOX_WITH_REM
309	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
310	return true; /* early init */
311
312	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
313	#else
314	return true;
315	#endif
316	}
317
318
319	/**
320	* Try to acquire the REM lock.
321	*
322	* @returns VBox status code
323	* @param pVM The cross context VM structure.
324	*/
325	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
326	{
327	#ifdef VBOX_WITH_REM
328	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
329	return VINF_SUCCESS; /* early init */
330
331	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
332	#else
333	return VINF_SUCCESS;
334	#endif
335	}
336
337
338	/**
339	* @callback_method_impl{FNDISREADBYTES}
340	*/
341	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
342	{
343	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
344	#if defined(IN_RC) \|\| defined(IN_RING3)
345	PVM pVM = pVCpu->CTX_SUFF(pVM);
346	#endif
347	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
348	int rc;
349
350	/*
351	* Figure how much we can or must read.
352	*/
353	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
354	if (cbToRead > cbMaxRead)
355	cbToRead = cbMaxRead;
356	else if (cbToRead < cbMinRead)
357	cbToRead = cbMinRead;
358
359	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
360	/*
361	* We might be called upon to interpret an instruction in a patch.
362	*/
363	if (PATMIsPatchGCAddr(pVCpu->CTX_SUFF(pVM), uSrcAddr))
364	{
365	# ifdef IN_RC
366	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
367	# else
368	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVCpu->CTX_SUFF(pVM), uSrcAddr), cbToRead);
369	# endif
370	rc = VINF_SUCCESS;
371	}
372	else
373	#endif
374	{
375	# ifdef IN_RC
376	/*
377	* Try access it thru the shadow page tables first. Fall back on the
378	* slower PGM method if it fails because the TLB or page table was
379	* modified recently.
380	*/
381	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
382	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
383	{
384	cbToRead = cbMinRead;
385	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
386	}
387	if (rc == VERR_ACCESS_DENIED)
388	#endif
389	{
390	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
391	if (RT_FAILURE(rc))
392	{
393	if (cbToRead > cbMinRead)
394	{
395	cbToRead = cbMinRead;
396	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
397	}
398	if (RT_FAILURE(rc))
399	{
400	#ifndef IN_RC
401	/*
402	* If we fail to find the page via the guest's page tables
403	* we invalidate the page in the host TLB (pertaining to
404	* the guest in the NestedPaging case). See @bugref{6043}.
405	*/
406	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
407	{
408	HMInvalidatePage(pVCpu, uSrcAddr);
409	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
410	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
411	}
412	#endif
413	}
414	}
415	}
416	}
417
418	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
419	return rc;
420	}
421
422
423	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
424	{
425	NOREF(pVM);
426	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
427	}
428
429
430	/**
431	* Disassembles the current instruction.
432	*
433	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
434	* details.
435	*
436	* @param pVM The cross context VM structure.
437	* @param pVCpu The cross context virtual CPU structure.
438	* @param pDis Where to return the parsed instruction info.
439	* @param pcbInstr Where to return the instruction size. (optional)
440	*/
441	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
442	{
443	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
444	RTGCPTR GCPtrInstr;
445	#if 0
446	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
447	#else
448	/** @todo Get the CPU mode as well while we're at it! */
449	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
450	pCtxCore->rip, &GCPtrInstr);
451	#endif
452	if (RT_FAILURE(rc))
453	{
454	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
455	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
456	return rc;
457	}
458	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
459	}
460
461
462	/**
463	* Disassembles one instruction.
464	*
465	* This is used by internally by the interpreter and by trap/access handlers.
466	*
467	* @returns VBox status code.
468	*
469	* @param pVM The cross context VM structure.
470	* @param pVCpu The cross context virtual CPU structure.
471	* @param GCPtrInstr The flat address of the instruction.
472	* @param pCtxCore The context core (used to determine the cpu mode).
473	* @param pDis Where to return the parsed instruction info.
474	* @param pcbInstr Where to return the instruction size. (optional)
475	*/
476	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
477	PDISCPUSTATE pDis, unsigned *pcbInstr)
478	{
479	NOREF(pVM);
480	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu)); NOREF(pCtxCore);
481	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
482	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
483	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
484	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
485	if (RT_SUCCESS(rc))
486	return VINF_SUCCESS;
487	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
488	return rc;
489	}
490
491
492	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
493	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
494	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
495	uint32_t cbEm, uint32_t cbIem)
496	{
497	/* Quick compare. */
498	if ( rcEm == rcIem
499	&& cbEm == cbIem
500	&& g_cbEmWrote == g_cbIemWrote
501	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
502	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
503	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
504	)
505	return;
506
507	/* Report exact differences. */
508	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
509	if (rcEm != rcIem)
510	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
511	else if (cbEm != cbIem)
512	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
513
514	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
515	{
516	if (g_cbIemWrote != g_cbEmWrote)
517	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
518	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
519	{
520	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
521	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
522	}
523
524	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
525	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
526	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
527
528	# define CHECK_FIELD(a_Field) \
529	do \
530	{ \
531	if (pEmCtx->a_Field != pIemCtx->a_Field) \
532	{ \
533	switch (sizeof(pEmCtx->a_Field)) \
534	{ \
535	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
536	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
537	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
538	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
539	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
540	} \
541	cDiffs++; \
542	} \
543	} while (0)
544
545	# define CHECK_BIT_FIELD(a_Field) \
546	do \
547	{ \
548	if (pEmCtx->a_Field != pIemCtx->a_Field) \
549	{ \
550	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
551	cDiffs++; \
552	} \
553	} while (0)
554
555	# define CHECK_SEL(a_Sel) \
556	do \
557	{ \
558	CHECK_FIELD(a_Sel.Sel); \
559	CHECK_FIELD(a_Sel.Attr.u); \
560	CHECK_FIELD(a_Sel.u64Base); \
561	CHECK_FIELD(a_Sel.u32Limit); \
562	CHECK_FIELD(a_Sel.fFlags); \
563	} while (0)
564
565	unsigned cDiffs = 0;
566	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
567	{
568	RTLogPrintf(" the FPU state differs\n");
569	cDiffs++;
570	CHECK_FIELD(fpu.FCW);
571	CHECK_FIELD(fpu.FSW);
572	CHECK_FIELD(fpu.FTW);
573	CHECK_FIELD(fpu.FOP);
574	CHECK_FIELD(fpu.FPUIP);
575	CHECK_FIELD(fpu.CS);
576	CHECK_FIELD(fpu.Rsrvd1);
577	CHECK_FIELD(fpu.FPUDP);
578	CHECK_FIELD(fpu.DS);
579	CHECK_FIELD(fpu.Rsrvd2);
580	CHECK_FIELD(fpu.MXCSR);
581	CHECK_FIELD(fpu.MXCSR_MASK);
582	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
583	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
584	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
585	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
586	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
587	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
588	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
589	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
590	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
591	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
592	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
593	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
594	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
595	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
596	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
597	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
598	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
599	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
600	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
601	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
602	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
603	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
604	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
605	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
606	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
607	CHECK_FIELD(fpu.au32RsrvdRest[i]);
608	}
609	CHECK_FIELD(rip);
610	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
611	{
612	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
613	CHECK_BIT_FIELD(rflags.Bits.u1CF);
614	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
615	CHECK_BIT_FIELD(rflags.Bits.u1PF);
616	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
617	CHECK_BIT_FIELD(rflags.Bits.u1AF);
618	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
619	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
620	CHECK_BIT_FIELD(rflags.Bits.u1SF);
621	CHECK_BIT_FIELD(rflags.Bits.u1TF);
622	CHECK_BIT_FIELD(rflags.Bits.u1IF);
623	CHECK_BIT_FIELD(rflags.Bits.u1DF);
624	CHECK_BIT_FIELD(rflags.Bits.u1OF);
625	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
626	CHECK_BIT_FIELD(rflags.Bits.u1NT);
627	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
628	CHECK_BIT_FIELD(rflags.Bits.u1RF);
629	CHECK_BIT_FIELD(rflags.Bits.u1VM);
630	CHECK_BIT_FIELD(rflags.Bits.u1AC);
631	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
632	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
633	CHECK_BIT_FIELD(rflags.Bits.u1ID);
634	}
635
636	if (!g_fIgnoreRaxRdx)
637	CHECK_FIELD(rax);
638	CHECK_FIELD(rcx);
639	if (!g_fIgnoreRaxRdx)
640	CHECK_FIELD(rdx);
641	CHECK_FIELD(rbx);
642	CHECK_FIELD(rsp);
643	CHECK_FIELD(rbp);
644	CHECK_FIELD(rsi);
645	CHECK_FIELD(rdi);
646	CHECK_FIELD(r8);
647	CHECK_FIELD(r9);
648	CHECK_FIELD(r10);
649	CHECK_FIELD(r11);
650	CHECK_FIELD(r12);
651	CHECK_FIELD(r13);
652	CHECK_SEL(cs);
653	CHECK_SEL(ss);
654	CHECK_SEL(ds);
655	CHECK_SEL(es);
656	CHECK_SEL(fs);
657	CHECK_SEL(gs);
658	CHECK_FIELD(cr0);
659	CHECK_FIELD(cr2);
660	CHECK_FIELD(cr3);
661	CHECK_FIELD(cr4);
662	CHECK_FIELD(dr[0]);
663	CHECK_FIELD(dr[1]);
664	CHECK_FIELD(dr[2]);
665	CHECK_FIELD(dr[3]);
666	CHECK_FIELD(dr[6]);
667	CHECK_FIELD(dr[7]);
668	CHECK_FIELD(gdtr.cbGdt);
669	CHECK_FIELD(gdtr.pGdt);
670	CHECK_FIELD(idtr.cbIdt);
671	CHECK_FIELD(idtr.pIdt);
672	CHECK_SEL(ldtr);
673	CHECK_SEL(tr);
674	CHECK_FIELD(SysEnter.cs);
675	CHECK_FIELD(SysEnter.eip);
676	CHECK_FIELD(SysEnter.esp);
677	CHECK_FIELD(msrEFER);
678	CHECK_FIELD(msrSTAR);
679	CHECK_FIELD(msrPAT);
680	CHECK_FIELD(msrLSTAR);
681	CHECK_FIELD(msrCSTAR);
682	CHECK_FIELD(msrSFMASK);
683	CHECK_FIELD(msrKERNELGSBASE);
684
685	# undef CHECK_FIELD
686	# undef CHECK_BIT_FIELD
687	}
688	}
689	#endif /* VBOX_COMPARE_IEM_AND_EM */
690
691
692	/**
693	* Interprets the current instruction.
694	*
695	* @returns VBox status code.
696	* @retval VINF_* Scheduling instructions.
697	* @retval VERR_EM_INTERPRETER Something we can't cope with.
698	* @retval VERR_* Fatal errors.
699	*
700	* @param pVCpu The cross context virtual CPU structure.
701	* @param pRegFrame The register frame.
702	* Updates the EIP if an instruction was executed successfully.
703	* @param pvFault The fault address (CR2).
704	*
705	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
706	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
707	* to worry about e.g. invalid modrm combinations (!)
708	*/
709	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
710	{
711	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
712	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
713	#ifdef VBOX_WITH_IEM
714	NOREF(pvFault);
715
716	# ifdef VBOX_COMPARE_IEM_AND_EM
717	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
718	g_IncomingCtx = *pCtx;
719	g_fIncomingFFs = pVCpu->fLocalForcedActions;
720	g_cbEmWrote = g_cbIemWrote = 0;
721
722	# ifdef VBOX_COMPARE_IEM_FIRST
723	/* IEM */
724	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
725	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
726	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
727	rcIem = VERR_EM_INTERPRETER;
728	g_IemCtx = *pCtx;
729	g_fIemFFs = pVCpu->fLocalForcedActions;
730	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
731	*pCtx = g_IncomingCtx;
732	# endif
733
734	/* EM */
735	RTGCPTR pbCode;
736	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
737	if (RT_SUCCESS(rcEm))
738	{
739	uint32_t cbOp;
740	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
741	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
742	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
743	if (RT_SUCCESS(rcEm))
744	{
745	Assert(cbOp == pDis->cbInstr);
746	uint32_t cbIgnored;
747	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
748	if (RT_SUCCESS(rcEm))
749	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
750
751	}
752	rcEm = VERR_EM_INTERPRETER;
753	}
754	else
755	rcEm = VERR_EM_INTERPRETER;
756	# ifdef VBOX_SAME_AS_EM
757	if (rcEm == VERR_EM_INTERPRETER)
758	{
759	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
760	return rcEm;
761	}
762	# endif
763	g_EmCtx = *pCtx;
764	g_fEmFFs = pVCpu->fLocalForcedActions;
765	VBOXSTRICTRC rc = rcEm;
766
767	# ifdef VBOX_COMPARE_IEM_LAST
768	/* IEM */
769	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
770	*pCtx = g_IncomingCtx;
771	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
772	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
773	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
774	rcIem = VERR_EM_INTERPRETER;
775	g_IemCtx = *pCtx;
776	g_fIemFFs = pVCpu->fLocalForcedActions;
777	rc = rcIem;
778	# endif
779
780	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
781	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
782	# endif
783
784	# else
785	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
786	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
787	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
788	rc = VERR_EM_INTERPRETER;
789	# endif
790	if (rc != VINF_SUCCESS)
791	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
792
793	return rc;
794	#else
795	RTGCPTR pbCode;
796	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
797	if (RT_SUCCESS(rc))
798	{
799	uint32_t cbOp;
800	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
801	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
802	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
803	if (RT_SUCCESS(rc))
804	{
805	Assert(cbOp == pDis->cbInstr);
806	uint32_t cbIgnored;
807	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
808	if (RT_SUCCESS(rc))
809	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
810
811	return rc;
812	}
813	}
814	return VERR_EM_INTERPRETER;
815	#endif
816	}
817
818
819	/**
820	* Interprets the current instruction.
821	*
822	* @returns VBox status code.
823	* @retval VINF_* Scheduling instructions.
824	* @retval VERR_EM_INTERPRETER Something we can't cope with.
825	* @retval VERR_* Fatal errors.
826	*
827	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
828	* @param pRegFrame The register frame.
829	* Updates the EIP if an instruction was executed successfully.
830	* @param pvFault The fault address (CR2).
831	* @param pcbWritten Size of the write (if applicable).
832	*
833	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
834	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
835	* to worry about e.g. invalid modrm combinations (!)
836	*/
837	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
838	{
839	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
840	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
841	#ifdef VBOX_WITH_IEM
842	NOREF(pvFault);
843
844	# ifdef VBOX_COMPARE_IEM_AND_EM
845	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
846	g_IncomingCtx = *pCtx;
847	g_fIncomingFFs = pVCpu->fLocalForcedActions;
848	g_cbEmWrote = g_cbIemWrote = 0;
849
850	# ifdef VBOX_COMPARE_IEM_FIRST
851	/* IEM */
852	uint32_t cbIemWritten = 0;
853	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
854	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
855	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
856	rcIem = VERR_EM_INTERPRETER;
857	g_IemCtx = *pCtx;
858	g_fIemFFs = pVCpu->fLocalForcedActions;
859	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
860	*pCtx = g_IncomingCtx;
861	# endif
862
863	/* EM */
864	uint32_t cbEmWritten = 0;
865	RTGCPTR pbCode;
866	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
867	if (RT_SUCCESS(rcEm))
868	{
869	uint32_t cbOp;
870	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
871	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
872	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
873	if (RT_SUCCESS(rcEm))
874	{
875	Assert(cbOp == pDis->cbInstr);
876	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
877	if (RT_SUCCESS(rcEm))
878	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
879
880	}
881	else
882	rcEm = VERR_EM_INTERPRETER;
883	}
884	else
885	rcEm = VERR_EM_INTERPRETER;
886	# ifdef VBOX_SAME_AS_EM
887	if (rcEm == VERR_EM_INTERPRETER)
888	{
889	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
890	return rcEm;
891	}
892	# endif
893	g_EmCtx = *pCtx;
894	g_fEmFFs = pVCpu->fLocalForcedActions;
895	*pcbWritten = cbEmWritten;
896	VBOXSTRICTRC rc = rcEm;
897
898	# ifdef VBOX_COMPARE_IEM_LAST
899	/* IEM */
900	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
901	*pCtx = g_IncomingCtx;
902	uint32_t cbIemWritten = 0;
903	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
904	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
905	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
906	rcIem = VERR_EM_INTERPRETER;
907	g_IemCtx = *pCtx;
908	g_fIemFFs = pVCpu->fLocalForcedActions;
909	*pcbWritten = cbIemWritten;
910	rc = rcIem;
911	# endif
912
913	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
914	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
915	# endif
916
917	# else
918	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
919	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
920	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
921	rc = VERR_EM_INTERPRETER;
922	# endif
923	if (rc != VINF_SUCCESS)
924	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
925
926	return rc;
927	#else
928	RTGCPTR pbCode;
929	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
930	if (RT_SUCCESS(rc))
931	{
932	uint32_t cbOp;
933	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
934	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
935	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
936	if (RT_SUCCESS(rc))
937	{
938	Assert(cbOp == pDis->cbInstr);
939	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
940	if (RT_SUCCESS(rc))
941	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
942
943	return rc;
944	}
945	}
946	return VERR_EM_INTERPRETER;
947	#endif
948	}
949
950
951	/**
952	* Interprets the current instruction using the supplied DISCPUSTATE structure.
953	*
954	* IP/EIP/RIP IS updated!
955	*
956	* @returns VBox strict status code.
957	* @retval VINF_* Scheduling instructions. When these are returned, it
958	* starts to get a bit tricky to know whether code was
959	* executed or not... We'll address this when it becomes a problem.
960	* @retval VERR_EM_INTERPRETER Something we can't cope with.
961	* @retval VERR_* Fatal errors.
962	*
963	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
964	* @param pDis The disassembler cpu state for the instruction to be
965	* interpreted.
966	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
967	* @param pvFault The fault address (CR2).
968	* @param enmCodeType Code type (user/supervisor)
969	*
970	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
971	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
972	* to worry about e.g. invalid modrm combinations (!)
973	*
974	* @todo At this time we do NOT check if the instruction overwrites vital information.
975	* Make sure this can't happen!! (will add some assertions/checks later)
976	*/
977	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
978	RTGCPTR pvFault, EMCODETYPE enmCodeType)
979	{
980	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
981	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
982	#ifdef VBOX_WITH_IEM
983	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
984
985	# ifdef VBOX_COMPARE_IEM_AND_EM
986	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
987	g_IncomingCtx = *pCtx;
988	g_fIncomingFFs = pVCpu->fLocalForcedActions;
989	g_cbEmWrote = g_cbIemWrote = 0;
990
991	# ifdef VBOX_COMPARE_IEM_FIRST
992	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
993	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
994	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
995	rcIem = VERR_EM_INTERPRETER;
996	g_IemCtx = *pCtx;
997	g_fIemFFs = pVCpu->fLocalForcedActions;
998	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
999	*pCtx = g_IncomingCtx;
1000	# endif
1001
1002	/* EM */
1003	uint32_t cbIgnored;
1004	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1005	if (RT_SUCCESS(rcEm))
1006	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1007	# ifdef VBOX_SAME_AS_EM
1008	if (rcEm == VERR_EM_INTERPRETER)
1009	{
1010	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
1011	return rcEm;
1012	}
1013	# endif
1014	g_EmCtx = *pCtx;
1015	g_fEmFFs = pVCpu->fLocalForcedActions;
1016	VBOXSTRICTRC rc = rcEm;
1017
1018	# ifdef VBOX_COMPARE_IEM_LAST
1019	/* IEM */
1020	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1021	*pCtx = g_IncomingCtx;
1022	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1023	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1024	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1025	rcIem = VERR_EM_INTERPRETER;
1026	g_IemCtx = *pCtx;
1027	g_fIemFFs = pVCpu->fLocalForcedActions;
1028	rc = rcIem;
1029	# endif
1030
1031	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1032	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1033	# endif
1034
1035	# else
1036	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1037	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1038	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1039	rc = VERR_EM_INTERPRETER;
1040	# endif
1041
1042	if (rc != VINF_SUCCESS)
1043	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1044
1045	return rc;
1046	#else
1047	uint32_t cbIgnored;
1048	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1049	if (RT_SUCCESS(rc))
1050	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1051	return rc;
1052	#endif
1053	}
1054
1055	#ifdef IN_RC
1056
1057	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1058	{
1059	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1060	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1061	return rc;
1062	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1063	}
1064
1065
1066	/**
1067	* Interpret IRET (currently only to V86 code) - PATM only.
1068	*
1069	* @returns VBox status code.
1070	* @param pVM The cross context VM structure.
1071	* @param pVCpu The cross context virtual CPU structure.
1072	* @param pRegFrame The register frame.
1073	*
1074	*/
1075	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1076	{
1077	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1078	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1079	int rc;
1080
1081	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1082	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1083	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1084	* this function. Fear that it may guru on us, thus not converted to
1085	* IEM. */
1086
1087	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1088	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1089	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1090	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1091	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1092
1093	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1094	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1095	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1096	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1097	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1098	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1099	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1100
1101	pRegFrame->eip = eip & 0xffff;
1102	pRegFrame->cs.Sel = cs;
1103
1104	/* Mask away all reserved bits */
1105	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1106	eflags &= uMask;
1107
1108	CPUMRawSetEFlags(pVCpu, eflags);
1109	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1110
1111	pRegFrame->esp = esp;
1112	pRegFrame->ss.Sel = ss;
1113	pRegFrame->ds.Sel = ds;
1114	pRegFrame->es.Sel = es;
1115	pRegFrame->fs.Sel = fs;
1116	pRegFrame->gs.Sel = gs;
1117
1118	return VINF_SUCCESS;
1119	}
1120
1121	/**
1122	* IRET Emulation.
1123	*/
1124	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1125	{
1126	#ifdef VBOX_WITH_RAW_RING1
1127	NOREF(pvFault); NOREF(pcbSize);
1128	if (EMIsRawRing1Enabled(pVM))
1129	{
1130	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1131	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1132	int rc;
1133	uint32_t cpl, rpl;
1134
1135	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1136	/* @todo: we don't verify all the edge cases that generate #GP faults */
1137
1138	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1139	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1140	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1141	* this function. Fear that it may guru on us, thus not converted to
1142	* IEM. */
1143
1144	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1145	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1146	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1147	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1148	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1149
1150	/* Deal with V86 above. */
1151	if (eflags & X86_EFL_VM)
1152	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1153
1154	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1155	rpl = cs & X86_SEL_RPL;
1156
1157	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1158	if (rpl != cpl)
1159	{
1160	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1161	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1162	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1163	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1164	Log(("emInterpretIret: SS:ESP=%04x:%08x\n", ss, esp));
1165	pRegFrame->ss.Sel = ss;
1166	pRegFrame->esp = esp;
1167	}
1168	pRegFrame->cs.Sel = cs;
1169	pRegFrame->eip = eip;
1170
1171	/* Adjust CS & SS as required. */
1172	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1173
1174	/* Mask away all reserved bits */
1175	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1176	eflags &= uMask;
1177
1178	CPUMRawSetEFlags(pVCpu, eflags);
1179	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1180	return VINF_SUCCESS;
1181	}
1182	#else
1183	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1184	#endif
1185	return VERR_EM_INTERPRETER;
1186	}
1187
1188	#endif /* IN_RC */
1189
1190
1191
1192	/*
1193	*
1194	* Old interpreter primitives used by HM, move/eliminate later.
1195	* Old interpreter primitives used by HM, move/eliminate later.
1196	* Old interpreter primitives used by HM, move/eliminate later.
1197	* Old interpreter primitives used by HM, move/eliminate later.
1198	* Old interpreter primitives used by HM, move/eliminate later.
1199	*
1200	*/
1201
1202
1203	/**
1204	* Interpret CPUID given the parameters in the CPU context.
1205	*
1206	* @returns VBox status code.
1207	* @param pVM The cross context VM structure.
1208	* @param pVCpu The cross context virtual CPU structure.
1209	* @param pRegFrame The register frame.
1210	*
1211	*/
1212	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1213	{
1214	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1215	uint32_t iLeaf = pRegFrame->eax;
1216	uint32_t iSubLeaf = pRegFrame->ecx;
1217	NOREF(pVM);
1218
1219	/* cpuid clears the high dwords of the affected 64 bits registers. */
1220	pRegFrame->rax = 0;
1221	pRegFrame->rbx = 0;
1222	pRegFrame->rcx = 0;
1223	pRegFrame->rdx = 0;
1224
1225	/* Note: operates the same in 64 and non-64 bits mode. */
1226	CPUMGetGuestCpuId(pVCpu, iLeaf, iSubLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1227	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1228	return VINF_SUCCESS;
1229	}
1230
1231
1232	/**
1233	* Interpret RDTSC.
1234	*
1235	* @returns VBox status code.
1236	* @param pVM The cross context VM structure.
1237	* @param pVCpu The cross context virtual CPU structure.
1238	* @param pRegFrame The register frame.
1239	*
1240	*/
1241	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1242	{
1243	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1244	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1245
1246	if (uCR4 & X86_CR4_TSD)
1247	return VERR_EM_INTERPRETER; /* genuine #GP */
1248
1249	uint64_t uTicks = TMCpuTickGet(pVCpu);
1250
1251	/* Same behaviour in 32 & 64 bits mode */
1252	pRegFrame->rax = (uint32_t)uTicks;
1253	pRegFrame->rdx = (uTicks >> 32ULL);
1254	#ifdef VBOX_COMPARE_IEM_AND_EM
1255	g_fIgnoreRaxRdx = true;
1256	#endif
1257
1258	NOREF(pVM);
1259	return VINF_SUCCESS;
1260	}
1261
1262	/**
1263	* Interpret RDTSCP.
1264	*
1265	* @returns VBox status code.
1266	* @param pVM The cross context VM structure.
1267	* @param pVCpu The cross context virtual CPU structure.
1268	* @param pCtx The CPU context.
1269	*
1270	*/
1271	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1272	{
1273	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1274	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1275
1276	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1277	{
1278	AssertFailed();
1279	return VERR_EM_INTERPRETER; /* genuine #UD */
1280	}
1281
1282	if (uCR4 & X86_CR4_TSD)
1283	return VERR_EM_INTERPRETER; /* genuine #GP */
1284
1285	uint64_t uTicks = TMCpuTickGet(pVCpu);
1286
1287	/* Same behaviour in 32 & 64 bits mode */
1288	pCtx->rax = (uint32_t)uTicks;
1289	pCtx->rdx = (uTicks >> 32ULL);
1290	#ifdef VBOX_COMPARE_IEM_AND_EM
1291	g_fIgnoreRaxRdx = true;
1292	#endif
1293	/* Low dword of the TSC_AUX msr only. */
1294	VBOXSTRICTRC rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx); Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
1295	pCtx->rcx &= UINT32_C(0xffffffff);
1296
1297	return VINF_SUCCESS;
1298	}
1299
1300	/**
1301	* Interpret RDPMC.
1302	*
1303	* @returns VBox status code.
1304	* @param pVM The cross context VM structure.
1305	* @param pVCpu The cross context virtual CPU structure.
1306	* @param pRegFrame The register frame.
1307	*
1308	*/
1309	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1310	{
1311	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1312	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1313
1314	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1315	if ( !(uCR4 & X86_CR4_PCE)
1316	&& CPUMGetGuestCPL(pVCpu) != 0)
1317	{
1318	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1319	return VERR_EM_INTERPRETER; /* genuine #GP */
1320	}
1321
1322	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1323	pRegFrame->rax = 0;
1324	pRegFrame->rdx = 0;
1325	/** @todo We should trigger a \#GP here if the CPU doesn't support the index in
1326	* ecx but see @bugref{3472}! */
1327
1328	NOREF(pVM);
1329	return VINF_SUCCESS;
1330	}
1331
1332
1333	/**
1334	* MWAIT Emulation.
1335	*/
1336	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1337	{
1338	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1339	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1340	NOREF(pVM);
1341
1342	/* Get the current privilege level. */
1343	cpl = CPUMGetGuestCPL(pVCpu);
1344	if (cpl != 0)
1345	return VERR_EM_INTERPRETER; /* supervisor only */
1346
1347	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1348	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1349	return VERR_EM_INTERPRETER; /* not supported */
1350
1351	/*
1352	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1353	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1354	*/
1355	CPUMGetGuestCpuId(pVCpu, 5, 0, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1356	if (pRegFrame->ecx > 1)
1357	{
1358	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1359	return VERR_EM_INTERPRETER; /* illegal value. */
1360	}
1361
1362	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1363	{
1364	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1365	return VERR_EM_INTERPRETER; /* illegal value. */
1366	}
1367
1368	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1369	}
1370
1371
1372	/**
1373	* MONITOR Emulation.
1374	*/
1375	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1376	{
1377	uint32_t u32Dummy, u32ExtFeatures, cpl;
1378	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1379	NOREF(pVM);
1380
1381	if (pRegFrame->ecx != 0)
1382	{
1383	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1384	return VERR_EM_INTERPRETER; /* illegal value. */
1385	}
1386
1387	/* Get the current privilege level. */
1388	cpl = CPUMGetGuestCPL(pVCpu);
1389	if (cpl != 0)
1390	return VERR_EM_INTERPRETER; /* supervisor only */
1391
1392	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1393	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1394	return VERR_EM_INTERPRETER; /* not supported */
1395
1396	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/* VT-x only: */
1402
1403	/**
1404	* Interpret INVLPG.
1405	*
1406	* @returns VBox status code.
1407	* @param pVM The cross context VM structure.
1408	* @param pVCpu The cross context virtual CPU structure.
1409	* @param pRegFrame The register frame.
1410	* @param pAddrGC Operand address.
1411	*
1412	*/
1413	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1414	{
1415	/** @todo is addr always a flat linear address or ds based
1416	* (in absence of segment override prefixes)????
1417	*/
1418	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1419	NOREF(pVM); NOREF(pRegFrame);
1420	#ifdef IN_RC
1421	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1422	#endif
1423	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1424	if ( rc == VINF_SUCCESS
1425	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1426	return VINF_SUCCESS;
1427	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1428	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1429	VERR_EM_INTERPRETER);
1430	return rc;
1431	}
1432
1433
1434	/**
1435	* Update CRx.
1436	*
1437	* @returns VBox status code.
1438	* @param pVM The cross context VM structure.
1439	* @param pVCpu The cross context virtual CPU structure.
1440	* @param pRegFrame The register frame.
1441	* @param DestRegCrx CRx register index (DISUSE_REG_CR*)
1442	* @param val New CRx value
1443	*
1444	*/
1445	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
1446	{
1447	uint64_t oldval;
1448	uint64_t msrEFER;
1449	uint32_t fValid;
1450	int rc, rc2;
1451	NOREF(pVM);
1452
1453	/** @todo Clean up this mess. */
1454	LogFlow(("emInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
1455	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1456	switch (DestRegCrx)
1457	{
1458	case DISCREG_CR0:
1459	oldval = CPUMGetGuestCR0(pVCpu);
1460	#ifdef IN_RC
1461	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1462	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1463	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1464	return VERR_EM_INTERPRETER;
1465	#endif
1466	rc = VINF_SUCCESS;
1467	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1468	CPUMSetGuestCR0(pVCpu, val);
1469	#else
1470	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
1471	#endif
1472	val = CPUMGetGuestCR0(pVCpu);
1473	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1474	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1475	{
1476	/* global flush */
1477	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1478	AssertRCReturn(rc, rc);
1479	}
1480
1481	/* Deal with long mode enabling/disabling. */
1482	msrEFER = CPUMGetGuestEFER(pVCpu);
1483	if (msrEFER & MSR_K6_EFER_LME)
1484	{
1485	if ( !(oldval & X86_CR0_PG)
1486	&& (val & X86_CR0_PG))
1487	{
1488	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1489	if (pRegFrame->cs.Attr.n.u1Long)
1490	{
1491	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1492	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
1493	}
1494
1495	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1496	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
1497	{
1498	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1499	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
1500	}
1501	msrEFER \|= MSR_K6_EFER_LMA;
1502	}
1503	else
1504	if ( (oldval & X86_CR0_PG)
1505	&& !(val & X86_CR0_PG))
1506	{
1507	msrEFER &= ~MSR_K6_EFER_LMA;
1508	/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1509	}
1510	CPUMSetGuestEFER(pVCpu, msrEFER);
1511	}
1512	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1513	return rc2 == VINF_SUCCESS ? rc : rc2;
1514
1515	case DISCREG_CR2:
1516	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
1517	return VINF_SUCCESS;
1518
1519	case DISCREG_CR3:
1520	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1521	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
1522	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
1523	{
1524	/* flush */
1525	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
1526	AssertRC(rc);
1527	}
1528	return rc;
1529
1530	case DISCREG_CR4:
1531	oldval = CPUMGetGuestCR4(pVCpu);
1532	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
1533	val = CPUMGetGuestCR4(pVCpu);
1534
1535	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1536	msrEFER = CPUMGetGuestEFER(pVCpu);
1537	if ( (msrEFER & MSR_K6_EFER_LMA)
1538	&& (oldval & X86_CR4_PAE)
1539	&& !(val & X86_CR4_PAE))
1540	{
1541	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
1542	}
1543
1544	/* From IEM iemCImpl_load_CrX. */
1545	/** @todo Check guest CPUID bits for determining corresponding valid bits. */
1546	fValid = X86_CR4_VME \| X86_CR4_PVI
1547	\| X86_CR4_TSD \| X86_CR4_DE
1548	\| X86_CR4_PSE \| X86_CR4_PAE
1549	\| X86_CR4_MCE \| X86_CR4_PGE
1550	\| X86_CR4_PCE \| X86_CR4_OSFXSR
1551	\| X86_CR4_OSXMMEEXCPT;
1552	//if (xxx)
1553	// fValid \|= X86_CR4_VMXE;
1554	//if (xxx)
1555	// fValid \|= X86_CR4_OSXSAVE;
1556	if (val & ~(uint64_t)fValid)
1557	{
1558	Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", val, val & ~(uint64_t)fValid));
1559	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
1560	}
1561
1562	rc = VINF_SUCCESS;
1563	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1564	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1565	{
1566	/* global flush */
1567	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1568	AssertRCReturn(rc, rc);
1569	}
1570
1571	/* Feeling extremely lazy. */
1572	# ifdef IN_RC
1573	if ( (oldval & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1574	!= (val & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1575	{
1576	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1577	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
1578	}
1579	# endif
1580	# ifdef VBOX_WITH_RAW_MODE
1581	if (((val ^ oldval) & X86_CR4_VME) && !HMIsEnabled(pVM))
1582	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1583	# endif
1584
1585	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1586	return rc2 == VINF_SUCCESS ? rc : rc2;
1587
1588	case DISCREG_CR8:
1589	return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1590
1591	default:
1592	AssertFailed();
1593	case DISCREG_CR1: /* illegal op */
1594	break;
1595	}
1596	return VERR_EM_INTERPRETER;
1597	}
1598
1599
1600	/**
1601	* Interpret CRx write.
1602	*
1603	* @returns VBox status code.
1604	* @param pVM The cross context VM structure.
1605	* @param pVCpu The cross context virtual CPU structure.
1606	* @param pRegFrame The register frame.
1607	* @param DestRegCrx CRx register index (DISUSE_REG_CR*)
1608	* @param SrcRegGen General purpose register index (USE_REG_E**))
1609	*
1610	*/
1611	static int emInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1612	{
1613	uint64_t val;
1614	int rc;
1615	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1616
1617	if (CPUMIsGuestIn64BitCode(pVCpu))
1618	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1619	else
1620	{
1621	uint32_t val32;
1622	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1623	val = val32;
1624	}
1625
1626	if (RT_SUCCESS(rc))
1627	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
1628
1629	return VERR_EM_INTERPRETER;
1630	}
1631
1632
1633	#ifdef LOG_ENABLED
1634	static const char *emMSRtoString(uint32_t uMsr)
1635	{
1636	switch (uMsr)
1637	{
1638	case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
1639	case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
1640	case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
1641	case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
1642	case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
1643	case MSR_K6_EFER: return "MSR_K6_EFER";
1644	case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
1645	case MSR_K6_STAR: return "MSR_K6_STAR";
1646	case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
1647	case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
1648	case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
1649	case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
1650	case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
1651	case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
1652	case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
1653	case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
1654	case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
1655	case MSR_IA32_TSC: return "MSR_IA32_TSC";
1656	case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
1657	case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
1658	case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
1659	case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
1660	case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
1661	case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
1662	case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
1663	case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
1664	case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
1665	case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
1666	case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
1667	case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
1668	case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
1669	case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
1670	case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
1671	case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
1672	case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
1673	case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
1674	case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
1675	case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
1676	case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
1677	case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
1678	case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
1679	case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
1680	case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
1681	}
1682	return "Unknown MSR";
1683	}
1684	#endif /* LOG_ENABLED */
1685
1686
1687	/**
1688	* Interpret RDMSR
1689	*
1690	* @returns VBox status code.
1691	* @param pVM The cross context VM structure.
1692	* @param pVCpu The cross context virtual CPU structure.
1693	* @param pRegFrame The register frame.
1694	*/
1695	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1696	{
1697	NOREF(pVM);
1698
1699	/* Get the current privilege level. */
1700	if (CPUMGetGuestCPL(pVCpu) != 0)
1701	{
1702	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
1703	return VERR_EM_INTERPRETER; /* supervisor only */
1704	}
1705
1706	uint64_t uValue;
1707	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
1708	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1709	{
1710	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1711	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_READ);
1712	return VERR_EM_INTERPRETER;
1713	}
1714	pRegFrame->rax = (uint32_t) uValue;
1715	pRegFrame->rdx = (uint32_t)(uValue >> 32);
1716	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
1717	return VINF_SUCCESS;
1718	}
1719
1720
1721	/**
1722	* Interpret WRMSR
1723	*
1724	* @returns VBox status code.
1725	* @param pVM The cross context VM structure.
1726	* @param pVCpu The cross context virtual CPU structure.
1727	* @param pRegFrame The register frame.
1728	*/
1729	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1730	{
1731	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1732
1733	/* Check the current privilege level, this instruction is supervisor only. */
1734	if (CPUMGetGuestCPL(pVCpu) != 0)
1735	{
1736	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
1737	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
1738	}
1739
1740	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
1741	if (rcStrict != VINF_SUCCESS)
1742	{
1743	Log4(("EM: Refuse WRMSR: CPUMSetGuestMsr returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1744	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_WRITE);
1745	return VERR_EM_INTERPRETER;
1746	}
1747	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
1748	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
1749	NOREF(pVM);
1750	return VINF_SUCCESS;
1751	}
1752
1753
1754	/**
1755	* Interpret CRx read.
1756	*
1757	* @returns VBox status code.
1758	* @param pVM The cross context VM structure.
1759	* @param pVCpu The cross context virtual CPU structure.
1760	* @param pRegFrame The register frame.
1761	* @param DestRegGen General purpose register index (USE_REG_E**))
1762	* @param SrcRegCrx CRx register index (DISUSE_REG_CR*)
1763	*
1764	*/
1765	static int emInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1766	{
1767	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1768	uint64_t val64;
1769	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1770	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1771	NOREF(pVM);
1772
1773	if (CPUMIsGuestIn64BitCode(pVCpu))
1774	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1775	else
1776	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1777
1778	if (RT_SUCCESS(rc))
1779	{
1780	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1781	return VINF_SUCCESS;
1782	}
1783	return VERR_EM_INTERPRETER;
1784	}
1785
1786
1787	/**
1788	* Interpret DRx write.
1789	*
1790	* @returns VBox status code.
1791	* @param pVM The cross context VM structure.
1792	* @param pVCpu The cross context virtual CPU structure.
1793	* @param pRegFrame The register frame.
1794	* @param DestRegDrx DRx register index (USE_REG_DR*)
1795	* @param SrcRegGen General purpose register index (USE_REG_E**))
1796	*
1797	*/
1798	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1799	{
1800	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1801	uint64_t uNewDrX;
1802	int rc;
1803	NOREF(pVM);
1804
1805	if (CPUMIsGuestIn64BitCode(pVCpu))
1806	rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1807	else
1808	{
1809	uint32_t val32;
1810	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1811	uNewDrX = val32;
1812	}
1813
1814	if (RT_SUCCESS(rc))
1815	{
1816	if (DestRegDrx == 6)
1817	{
1818	uNewDrX \|= X86_DR6_RA1_MASK;
1819	uNewDrX &= ~X86_DR6_RAZ_MASK;
1820	}
1821	else if (DestRegDrx == 7)
1822	{
1823	uNewDrX \|= X86_DR7_RA1_MASK;
1824	uNewDrX &= ~X86_DR7_RAZ_MASK;
1825	}
1826
1827	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1828	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1829	if (RT_SUCCESS(rc))
1830	return rc;
1831	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1832	}
1833	return VERR_EM_INTERPRETER;
1834	}
1835
1836
1837	/**
1838	* Interpret DRx read.
1839	*
1840	* @returns VBox status code.
1841	* @param pVM The cross context VM structure.
1842	* @param pVCpu The cross context virtual CPU structure.
1843	* @param pRegFrame The register frame.
1844	* @param DestRegGen General purpose register index (USE_REG_E**))
1845	* @param SrcRegDrx DRx register index (USE_REG_DR*)
1846	*/
1847	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1848	{
1849	uint64_t val64;
1850	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1851	NOREF(pVM);
1852
1853	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1854	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1855	if (CPUMIsGuestIn64BitCode(pVCpu))
1856	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1857	else
1858	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1859
1860	if (RT_SUCCESS(rc))
1861	return VINF_SUCCESS;
1862
1863	return VERR_EM_INTERPRETER;
1864	}
1865
1866
1867	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1868
1869
1870
1871
1872
1873
1874	/*
1875	*
1876	* The old interpreter.
1877	* The old interpreter.
1878	* The old interpreter.
1879	* The old interpreter.
1880	* The old interpreter.
1881	*
1882	*/
1883
1884	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1885	{
1886	#ifdef IN_RC
1887	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1888	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1889	return rc;
1890	/*
1891	* The page pool cache may end up here in some cases because it
1892	* flushed one of the shadow mappings used by the trapping
1893	* instruction and it either flushed the TLB or the CPU reused it.
1894	*/
1895	#else
1896	NOREF(pVM);
1897	#endif
1898	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1899	}
1900
1901
1902	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1903	{
1904	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1905	pages or write monitored pages. */
1906	NOREF(pVM);
1907	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1908	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1909	#else
1910	int rc = VINF_SUCCESS;
1911	#endif
1912	#ifdef VBOX_COMPARE_IEM_AND_EM
1913	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1914	g_cbEmWrote = cb;
1915	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1916	#endif
1917	return rc;
1918	}
1919
1920
1921	/** Convert sel:addr to a flat GC address. */
1922	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1923	{
1924	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1925	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1926	}
1927
1928
1929	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1930	/**
1931	* Get the mnemonic for the disassembled instruction.
1932	*
1933	* GC/R0 doesn't include the strings in the DIS tables because
1934	* of limited space.
1935	*/
1936	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1937	{
1938	switch (pDis->pCurInstr->uOpcode)
1939	{
1940	case OP_XCHG: return "Xchg";
1941	case OP_DEC: return "Dec";
1942	case OP_INC: return "Inc";
1943	case OP_POP: return "Pop";
1944	case OP_OR: return "Or";
1945	case OP_AND: return "And";
1946	case OP_MOV: return "Mov";
1947	case OP_INVLPG: return "InvlPg";
1948	case OP_CPUID: return "CpuId";
1949	case OP_MOV_CR: return "MovCRx";
1950	case OP_MOV_DR: return "MovDRx";
1951	case OP_LLDT: return "LLdt";
1952	case OP_LGDT: return "LGdt";
1953	case OP_LIDT: return "LIdt";
1954	case OP_CLTS: return "Clts";
1955	case OP_MONITOR: return "Monitor";
1956	case OP_MWAIT: return "MWait";
1957	case OP_RDMSR: return "Rdmsr";
1958	case OP_WRMSR: return "Wrmsr";
1959	case OP_ADD: return "Add";
1960	case OP_ADC: return "Adc";
1961	case OP_SUB: return "Sub";
1962	case OP_SBB: return "Sbb";
1963	case OP_RDTSC: return "Rdtsc";
1964	case OP_STI: return "Sti";
1965	case OP_CLI: return "Cli";
1966	case OP_XADD: return "XAdd";
1967	case OP_HLT: return "Hlt";
1968	case OP_IRET: return "Iret";
1969	case OP_MOVNTPS: return "MovNTPS";
1970	case OP_STOSWD: return "StosWD";
1971	case OP_WBINVD: return "WbInvd";
1972	case OP_XOR: return "Xor";
1973	case OP_BTR: return "Btr";
1974	case OP_BTS: return "Bts";
1975	case OP_BTC: return "Btc";
1976	case OP_LMSW: return "Lmsw";
1977	case OP_SMSW: return "Smsw";
1978	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
1979	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
1980
1981	default:
1982	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
1983	return "???";
1984	}
1985	}
1986	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
1987
1988
1989	/**
1990	* XCHG instruction emulation.
1991	*/
1992	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1993	{
1994	DISQPVPARAMVAL param1, param2;
1995	NOREF(pvFault);
1996
1997	/* Source to make DISQueryParamVal read the register value - ugly hack */
1998	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
1999	if(RT_FAILURE(rc))
2000	return VERR_EM_INTERPRETER;
2001
2002	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2003	if(RT_FAILURE(rc))
2004	return VERR_EM_INTERPRETER;
2005
2006	#ifdef IN_RC
2007	if (TRPMHasTrap(pVCpu))
2008	{
2009	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2010	{
2011	#endif
2012	RTGCPTR pParam1 = 0, pParam2 = 0;
2013	uint64_t valpar1, valpar2;
2014
2015	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2016	switch(param1.type)
2017	{
2018	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2019	valpar1 = param1.val.val64;
2020	break;
2021
2022	case DISQPV_TYPE_ADDRESS:
2023	pParam1 = (RTGCPTR)param1.val.val64;
2024	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2025	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2026	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2027	if (RT_FAILURE(rc))
2028	{
2029	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2030	return VERR_EM_INTERPRETER;
2031	}
2032	break;
2033
2034	default:
2035	AssertFailed();
2036	return VERR_EM_INTERPRETER;
2037	}
2038
2039	switch(param2.type)
2040	{
2041	case DISQPV_TYPE_ADDRESS:
2042	pParam2 = (RTGCPTR)param2.val.val64;
2043	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
2044	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
2045	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
2046	if (RT_FAILURE(rc))
2047	{
2048	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2049	}
2050	break;
2051
2052	case DISQPV_TYPE_IMMEDIATE:
2053	valpar2 = param2.val.val64;
2054	break;
2055
2056	default:
2057	AssertFailed();
2058	return VERR_EM_INTERPRETER;
2059	}
2060
2061	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
2062	if (pParam1 == 0)
2063	{
2064	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2065	switch(param1.size)
2066	{
2067	case 1: //special case for AH etc
2068	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
2069	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
2070	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
2071	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
2072	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2073	}
2074	if (RT_FAILURE(rc))
2075	return VERR_EM_INTERPRETER;
2076	}
2077	else
2078	{
2079	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
2080	if (RT_FAILURE(rc))
2081	{
2082	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2083	return VERR_EM_INTERPRETER;
2084	}
2085	}
2086
2087	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
2088	if (pParam2 == 0)
2089	{
2090	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2091	switch(param2.size)
2092	{
2093	case 1: //special case for AH etc
2094	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
2095	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
2096	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
2097	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
2098	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2099	}
2100	if (RT_FAILURE(rc))
2101	return VERR_EM_INTERPRETER;
2102	}
2103	else
2104	{
2105	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
2106	if (RT_FAILURE(rc))
2107	{
2108	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2109	return VERR_EM_INTERPRETER;
2110	}
2111	}
2112
2113	*pcbSize = param2.size;
2114	return VINF_SUCCESS;
2115	#ifdef IN_RC
2116	}
2117	}
2118	return VERR_EM_INTERPRETER;
2119	#endif
2120	}
2121
2122
2123	/**
2124	* INC and DEC emulation.
2125	*/
2126	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2127	PFNEMULATEPARAM2 pfnEmulate)
2128	{
2129	DISQPVPARAMVAL param1;
2130	NOREF(pvFault);
2131
2132	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2133	if(RT_FAILURE(rc))
2134	return VERR_EM_INTERPRETER;
2135
2136	#ifdef IN_RC
2137	if (TRPMHasTrap(pVCpu))
2138	{
2139	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2140	{
2141	#endif
2142	RTGCPTR pParam1 = 0;
2143	uint64_t valpar1;
2144
2145	if (param1.type == DISQPV_TYPE_ADDRESS)
2146	{
2147	pParam1 = (RTGCPTR)param1.val.val64;
2148	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2149	#ifdef IN_RC
2150	/* Safety check (in theory it could cross a page boundary and fault there though) */
2151	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2152	#endif
2153	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2154	if (RT_FAILURE(rc))
2155	{
2156	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2157	return VERR_EM_INTERPRETER;
2158	}
2159	}
2160	else
2161	{
2162	AssertFailed();
2163	return VERR_EM_INTERPRETER;
2164	}
2165
2166	uint32_t eflags;
2167
2168	eflags = pfnEmulate(&valpar1, param1.size);
2169
2170	/* Write result back */
2171	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2172	if (RT_FAILURE(rc))
2173	{
2174	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2175	return VERR_EM_INTERPRETER;
2176	}
2177
2178	/* Update guest's eflags and finish. */
2179	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2180	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2181
2182	/* All done! */
2183	*pcbSize = param1.size;
2184	return VINF_SUCCESS;
2185	#ifdef IN_RC
2186	}
2187	}
2188	return VERR_EM_INTERPRETER;
2189	#endif
2190	}
2191
2192
2193	/**
2194	* POP Emulation.
2195	*/
2196	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2197	{
2198	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2199	DISQPVPARAMVAL param1;
2200	NOREF(pvFault);
2201
2202	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2203	if(RT_FAILURE(rc))
2204	return VERR_EM_INTERPRETER;
2205
2206	#ifdef IN_RC
2207	if (TRPMHasTrap(pVCpu))
2208	{
2209	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2210	{
2211	#endif
2212	RTGCPTR pParam1 = 0;
2213	uint32_t valpar1;
2214	RTGCPTR pStackVal;
2215
2216	/* Read stack value first */
2217	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2218	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2219
2220	/* Convert address; don't bother checking limits etc, as we only read here */
2221	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2222	if (pStackVal == 0)
2223	return VERR_EM_INTERPRETER;
2224
2225	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2226	if (RT_FAILURE(rc))
2227	{
2228	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2229	return VERR_EM_INTERPRETER;
2230	}
2231
2232	if (param1.type == DISQPV_TYPE_ADDRESS)
2233	{
2234	pParam1 = (RTGCPTR)param1.val.val64;
2235
2236	/* pop [esp+xx] uses esp after the actual pop! */
2237	AssertCompile(DISGREG_ESP == DISGREG_SP);
2238	if ( (pDis->Param1.fUse & DISUSE_BASE)
2239	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2240	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2241	)
2242	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2243
2244	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2245	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2246	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2247	if (RT_FAILURE(rc))
2248	{
2249	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2250	return VERR_EM_INTERPRETER;
2251	}
2252
2253	/* Update ESP as the last step */
2254	pRegFrame->esp += param1.size;
2255	}
2256	else
2257	{
2258	#ifndef DEBUG_bird // annoying assertion.
2259	AssertFailed();
2260	#endif
2261	return VERR_EM_INTERPRETER;
2262	}
2263
2264	/* All done! */
2265	*pcbSize = param1.size;
2266	return VINF_SUCCESS;
2267	#ifdef IN_RC
2268	}
2269	}
2270	return VERR_EM_INTERPRETER;
2271	#endif
2272	}
2273
2274
2275	/**
2276	* XOR/OR/AND Emulation.
2277	*/
2278	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2279	PFNEMULATEPARAM3 pfnEmulate)
2280	{
2281	DISQPVPARAMVAL param1, param2;
2282	NOREF(pvFault);
2283
2284	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2285	if(RT_FAILURE(rc))
2286	return VERR_EM_INTERPRETER;
2287
2288	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2289	if(RT_FAILURE(rc))
2290	return VERR_EM_INTERPRETER;
2291
2292	#ifdef IN_RC
2293	if (TRPMHasTrap(pVCpu))
2294	{
2295	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2296	{
2297	#endif
2298	RTGCPTR pParam1;
2299	uint64_t valpar1, valpar2;
2300
2301	if (pDis->Param1.cb != pDis->Param2.cb)
2302	{
2303	if (pDis->Param1.cb < pDis->Param2.cb)
2304	{
2305	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2306	return VERR_EM_INTERPRETER;
2307	}
2308	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2309	pDis->Param2.cb = pDis->Param1.cb;
2310	param2.size = param1.size;
2311	}
2312
2313	/* The destination is always a virtual address */
2314	if (param1.type == DISQPV_TYPE_ADDRESS)
2315	{
2316	pParam1 = (RTGCPTR)param1.val.val64;
2317	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2318	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2319	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2320	if (RT_FAILURE(rc))
2321	{
2322	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2323	return VERR_EM_INTERPRETER;
2324	}
2325	}
2326	else
2327	{
2328	AssertFailed();
2329	return VERR_EM_INTERPRETER;
2330	}
2331
2332	/* Register or immediate data */
2333	switch(param2.type)
2334	{
2335	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2336	valpar2 = param2.val.val64;
2337	break;
2338
2339	default:
2340	AssertFailed();
2341	return VERR_EM_INTERPRETER;
2342	}
2343
2344	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2345
2346	/* Data read, emulate instruction. */
2347	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2348
2349	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2350
2351	/* Update guest's eflags and finish. */
2352	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2353	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2354
2355	/* And write it back */
2356	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2357	if (RT_SUCCESS(rc))
2358	{
2359	/* All done! */
2360	*pcbSize = param2.size;
2361	return VINF_SUCCESS;
2362	}
2363	#ifdef IN_RC
2364	}
2365	}
2366	#endif
2367	return VERR_EM_INTERPRETER;
2368	}
2369
2370
2371	#ifndef VBOX_COMPARE_IEM_AND_EM
2372	/**
2373	* LOCK XOR/OR/AND Emulation.
2374	*/
2375	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2376	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2377	{
2378	void *pvParam1;
2379	DISQPVPARAMVAL param1, param2;
2380	NOREF(pvFault);
2381
2382	#if HC_ARCH_BITS == 32
2383	Assert(pDis->Param1.cb <= 4);
2384	#endif
2385
2386	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2387	if(RT_FAILURE(rc))
2388	return VERR_EM_INTERPRETER;
2389
2390	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2391	if(RT_FAILURE(rc))
2392	return VERR_EM_INTERPRETER;
2393
2394	if (pDis->Param1.cb != pDis->Param2.cb)
2395	{
2396	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2397	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2398	VERR_EM_INTERPRETER);
2399
2400	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2401	pDis->Param2.cb = pDis->Param1.cb;
2402	param2.size = param1.size;
2403	}
2404
2405	#ifdef IN_RC
2406	/* Safety check (in theory it could cross a page boundary and fault there though) */
2407	Assert( TRPMHasTrap(pVCpu)
2408	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2409	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2410	#endif
2411
2412	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2413	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2414	RTGCUINTREG ValPar2 = param2.val.val64;
2415
2416	/* The destination is always a virtual address */
2417	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2418
2419	RTGCPTR GCPtrPar1 = param1.val.val64;
2420	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2421	PGMPAGEMAPLOCK Lock;
2422	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2423	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2424
2425	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2426	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2427
2428	RTGCUINTREG32 eflags = 0;
2429	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2430	PGMPhysReleasePageMappingLock(pVM, &Lock);
2431	if (RT_FAILURE(rc))
2432	{
2433	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2434	return VERR_EM_INTERPRETER;
2435	}
2436
2437	/* Update guest's eflags and finish. */
2438	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2439	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2440
2441	*pcbSize = param2.size;
2442	return VINF_SUCCESS;
2443	}
2444	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2445
2446
2447	/**
2448	* ADD, ADC & SUB Emulation.
2449	*/
2450	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2451	PFNEMULATEPARAM3 pfnEmulate)
2452	{
2453	NOREF(pvFault);
2454	DISQPVPARAMVAL param1, param2;
2455	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2456	if(RT_FAILURE(rc))
2457	return VERR_EM_INTERPRETER;
2458
2459	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2460	if(RT_FAILURE(rc))
2461	return VERR_EM_INTERPRETER;
2462
2463	#ifdef IN_RC
2464	if (TRPMHasTrap(pVCpu))
2465	{
2466	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2467	{
2468	#endif
2469	RTGCPTR pParam1;
2470	uint64_t valpar1, valpar2;
2471
2472	if (pDis->Param1.cb != pDis->Param2.cb)
2473	{
2474	if (pDis->Param1.cb < pDis->Param2.cb)
2475	{
2476	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2477	return VERR_EM_INTERPRETER;
2478	}
2479	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2480	pDis->Param2.cb = pDis->Param1.cb;
2481	param2.size = param1.size;
2482	}
2483
2484	/* The destination is always a virtual address */
2485	if (param1.type == DISQPV_TYPE_ADDRESS)
2486	{
2487	pParam1 = (RTGCPTR)param1.val.val64;
2488	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2489	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2490	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2491	if (RT_FAILURE(rc))
2492	{
2493	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2494	return VERR_EM_INTERPRETER;
2495	}
2496	}
2497	else
2498	{
2499	#ifndef DEBUG_bird
2500	AssertFailed();
2501	#endif
2502	return VERR_EM_INTERPRETER;
2503	}
2504
2505	/* Register or immediate data */
2506	switch(param2.type)
2507	{
2508	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2509	valpar2 = param2.val.val64;
2510	break;
2511
2512	default:
2513	AssertFailed();
2514	return VERR_EM_INTERPRETER;
2515	}
2516
2517	/* Data read, emulate instruction. */
2518	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2519
2520	/* Update guest's eflags and finish. */
2521	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2522	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2523
2524	/* And write it back */
2525	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2526	if (RT_SUCCESS(rc))
2527	{
2528	/* All done! */
2529	*pcbSize = param2.size;
2530	return VINF_SUCCESS;
2531	}
2532	#ifdef IN_RC
2533	}
2534	}
2535	#endif
2536	return VERR_EM_INTERPRETER;
2537	}
2538
2539
2540	/**
2541	* ADC Emulation.
2542	*/
2543	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2544	{
2545	if (pRegFrame->eflags.Bits.u1CF)
2546	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2547	else
2548	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2549	}
2550
2551
2552	/**
2553	* BTR/C/S Emulation.
2554	*/
2555	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2556	PFNEMULATEPARAM2UINT32 pfnEmulate)
2557	{
2558	DISQPVPARAMVAL param1, param2;
2559	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2560	if(RT_FAILURE(rc))
2561	return VERR_EM_INTERPRETER;
2562
2563	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2564	if(RT_FAILURE(rc))
2565	return VERR_EM_INTERPRETER;
2566
2567	#ifdef IN_RC
2568	if (TRPMHasTrap(pVCpu))
2569	{
2570	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2571	{
2572	#endif
2573	RTGCPTR pParam1;
2574	uint64_t valpar1 = 0, valpar2;
2575	uint32_t eflags;
2576
2577	/* The destination is always a virtual address */
2578	if (param1.type != DISQPV_TYPE_ADDRESS)
2579	return VERR_EM_INTERPRETER;
2580
2581	pParam1 = (RTGCPTR)param1.val.val64;
2582	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2583
2584	/* Register or immediate data */
2585	switch(param2.type)
2586	{
2587	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2588	valpar2 = param2.val.val64;
2589	break;
2590
2591	default:
2592	AssertFailed();
2593	return VERR_EM_INTERPRETER;
2594	}
2595
2596	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2597	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2598	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER); NOREF(pvFault);
2599	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2600	if (RT_FAILURE(rc))
2601	{
2602	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2603	return VERR_EM_INTERPRETER;
2604	}
2605
2606	Log2(("emInterpretBtx: val=%x\n", valpar1));
2607	/* Data read, emulate bit test instruction. */
2608	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2609
2610	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2611
2612	/* Update guest's eflags and finish. */
2613	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2614	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2615
2616	/* And write it back */
2617	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2618	if (RT_SUCCESS(rc))
2619	{
2620	/* All done! */
2621	*pcbSize = 1;
2622	return VINF_SUCCESS;
2623	}
2624	#ifdef IN_RC
2625	}
2626	}
2627	#endif
2628	return VERR_EM_INTERPRETER;
2629	}
2630
2631
2632	#ifndef VBOX_COMPARE_IEM_AND_EM
2633	/**
2634	* LOCK BTR/C/S Emulation.
2635	*/
2636	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2637	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2638	{
2639	void *pvParam1;
2640
2641	DISQPVPARAMVAL param1, param2;
2642	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2643	if(RT_FAILURE(rc))
2644	return VERR_EM_INTERPRETER;
2645
2646	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2647	if(RT_FAILURE(rc))
2648	return VERR_EM_INTERPRETER;
2649
2650	/* The destination is always a virtual address */
2651	if (param1.type != DISQPV_TYPE_ADDRESS)
2652	return VERR_EM_INTERPRETER;
2653
2654	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2655	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2656	uint64_t ValPar2 = param2.val.val64;
2657
2658	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2659	RTGCPTR GCPtrPar1 = param1.val.val64;
2660	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2661	ValPar2 &= 7;
2662
2663	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2664	#ifdef IN_RC
2665	Assert(TRPMHasTrap(pVCpu));
2666	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2667	#endif
2668
2669	PGMPAGEMAPLOCK Lock;
2670	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2671	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2672
2673	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2674	NOREF(pvFault);
2675
2676	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2677	RTGCUINTREG32 eflags = 0;
2678	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2679	PGMPhysReleasePageMappingLock(pVM, &Lock);
2680	if (RT_FAILURE(rc))
2681	{
2682	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2683	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2684	return VERR_EM_INTERPRETER;
2685	}
2686
2687	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2688
2689	/* Update guest's eflags and finish. */
2690	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2691	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2692
2693	*pcbSize = 1;
2694	return VINF_SUCCESS;
2695	}
2696	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2697
2698
2699	/**
2700	* MOV emulation.
2701	*/
2702	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2703	{
2704	NOREF(pvFault);
2705	DISQPVPARAMVAL param1, param2;
2706	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2707	if(RT_FAILURE(rc))
2708	return VERR_EM_INTERPRETER;
2709
2710	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2711	if(RT_FAILURE(rc))
2712	return VERR_EM_INTERPRETER;
2713
2714	/* If destination is a segment register, punt. We can't handle it here.
2715	* NB: Source can be a register and still trigger a #PF!
2716	*/
2717	if (RT_UNLIKELY(pDis->Param1.fUse == DISUSE_REG_SEG))
2718	return VERR_EM_INTERPRETER;
2719
2720	if (param1.type == DISQPV_TYPE_ADDRESS)
2721	{
2722	RTGCPTR pDest;
2723	uint64_t val64;
2724
2725	switch(param1.type)
2726	{
2727	case DISQPV_TYPE_IMMEDIATE:
2728	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2729	return VERR_EM_INTERPRETER;
2730	/* fallthru */
2731
2732	case DISQPV_TYPE_ADDRESS:
2733	pDest = (RTGCPTR)param1.val.val64;
2734	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2735	break;
2736
2737	default:
2738	AssertFailed();
2739	return VERR_EM_INTERPRETER;
2740	}
2741
2742	switch(param2.type)
2743	{
2744	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2745	val64 = param2.val.val64;
2746	break;
2747
2748	default:
2749	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2750	return VERR_EM_INTERPRETER;
2751	}
2752	#ifdef LOG_ENABLED
2753	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2754	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2755	else
2756	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2757	#endif
2758
2759	Assert(param2.size <= 8 && param2.size > 0);
2760	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2761	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2762	if (RT_FAILURE(rc))
2763	return VERR_EM_INTERPRETER;
2764
2765	*pcbSize = param2.size;
2766	}
2767	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2768	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2769	else if ( param1.type == DISQPV_TYPE_REGISTER
2770	&& param2.type == DISQPV_TYPE_REGISTER)
2771	{
2772	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2773	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2774	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2775
2776	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2777	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2778
2779	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2780	switch (param1.size)
2781	{
2782	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2783	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2784	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2785	default:
2786	AssertFailed();
2787	return VERR_EM_INTERPRETER;
2788	}
2789	AssertRCReturn(rc, rc);
2790	}
2791	#endif
2792	else
2793	{ /* read fault */
2794	RTGCPTR pSrc;
2795	uint64_t val64;
2796
2797	/* Source */
2798	switch(param2.type)
2799	{
2800	case DISQPV_TYPE_IMMEDIATE:
2801	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2802	return VERR_EM_INTERPRETER;
2803	/* fallthru */
2804
2805	case DISQPV_TYPE_ADDRESS:
2806	pSrc = (RTGCPTR)param2.val.val64;
2807	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2808	break;
2809
2810	default:
2811	return VERR_EM_INTERPRETER;
2812	}
2813
2814	Assert(param1.size <= 8 && param1.size > 0);
2815	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2816	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2817	if (RT_FAILURE(rc))
2818	return VERR_EM_INTERPRETER;
2819
2820	/* Destination */
2821	switch(param1.type)
2822	{
2823	case DISQPV_TYPE_REGISTER:
2824	switch(param1.size)
2825	{
2826	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2827	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2828	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2829	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2830	default:
2831	return VERR_EM_INTERPRETER;
2832	}
2833	if (RT_FAILURE(rc))
2834	return rc;
2835	break;
2836
2837	default:
2838	return VERR_EM_INTERPRETER;
2839	}
2840	#ifdef LOG_ENABLED
2841	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2842	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2843	else
2844	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2845	#endif
2846	}
2847	return VINF_SUCCESS;
2848	}
2849
2850
2851	#ifndef IN_RC
2852	/**
2853	* [REP] STOSWD emulation
2854	*/
2855	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2856	{
2857	int rc;
2858	RTGCPTR GCDest, GCOffset;
2859	uint32_t cbSize;
2860	uint64_t cTransfers;
2861	int offIncrement;
2862	NOREF(pvFault);
2863
2864	/* Don't support any but these three prefix bytes. */
2865	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2866	return VERR_EM_INTERPRETER;
2867
2868	switch (pDis->uAddrMode)
2869	{
2870	case DISCPUMODE_16BIT:
2871	GCOffset = pRegFrame->di;
2872	cTransfers = pRegFrame->cx;
2873	break;
2874	case DISCPUMODE_32BIT:
2875	GCOffset = pRegFrame->edi;
2876	cTransfers = pRegFrame->ecx;
2877	break;
2878	case DISCPUMODE_64BIT:
2879	GCOffset = pRegFrame->rdi;
2880	cTransfers = pRegFrame->rcx;
2881	break;
2882	default:
2883	AssertFailed();
2884	return VERR_EM_INTERPRETER;
2885	}
2886
2887	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2888	switch (pDis->uOpMode)
2889	{
2890	case DISCPUMODE_16BIT:
2891	cbSize = 2;
2892	break;
2893	case DISCPUMODE_32BIT:
2894	cbSize = 4;
2895	break;
2896	case DISCPUMODE_64BIT:
2897	cbSize = 8;
2898	break;
2899	default:
2900	AssertFailed();
2901	return VERR_EM_INTERPRETER;
2902	}
2903
2904	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2905
2906	if (!(pDis->fPrefix & DISPREFIX_REP))
2907	{
2908	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2909
2910	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2911	if (RT_FAILURE(rc))
2912	return VERR_EM_INTERPRETER;
2913	Assert(rc == VINF_SUCCESS);
2914
2915	/* Update (e/r)di. */
2916	switch (pDis->uAddrMode)
2917	{
2918	case DISCPUMODE_16BIT:
2919	pRegFrame->di += offIncrement;
2920	break;
2921	case DISCPUMODE_32BIT:
2922	pRegFrame->edi += offIncrement;
2923	break;
2924	case DISCPUMODE_64BIT:
2925	pRegFrame->rdi += offIncrement;
2926	break;
2927	default:
2928	AssertFailed();
2929	return VERR_EM_INTERPRETER;
2930	}
2931
2932	}
2933	else
2934	{
2935	if (!cTransfers)
2936	return VINF_SUCCESS;
2937
2938	/*
2939	* Do not try emulate cross page stuff here because we don't know what might
2940	* be waiting for us on the subsequent pages. The caller has only asked us to
2941	* ignore access handlers fro the current page.
2942	* This also fends off big stores which would quickly kill PGMR0DynMap.
2943	*/
2944	if ( cbSize > PAGE_SIZE
2945	\|\| cTransfers > PAGE_SIZE
2946	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2947	{
2948	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2949	GCDest, cbSize, offIncrement, cTransfers));
2950	return VERR_EM_INTERPRETER;
2951	}
2952
2953	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2954	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2955	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2956	cTransfers * cbSize,
2957	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
2958	if (rc != VINF_SUCCESS)
2959	{
2960	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
2961	return VERR_EM_INTERPRETER;
2962	}
2963
2964	/* REP case */
2965	while (cTransfers)
2966	{
2967	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2968	if (RT_FAILURE(rc))
2969	{
2970	rc = VERR_EM_INTERPRETER;
2971	break;
2972	}
2973
2974	Assert(rc == VINF_SUCCESS);
2975	GCOffset += offIncrement;
2976	GCDest += offIncrement;
2977	cTransfers--;
2978	}
2979
2980	/* Update the registers. */
2981	switch (pDis->uAddrMode)
2982	{
2983	case DISCPUMODE_16BIT:
2984	pRegFrame->di = GCOffset;
2985	pRegFrame->cx = cTransfers;
2986	break;
2987	case DISCPUMODE_32BIT:
2988	pRegFrame->edi = GCOffset;
2989	pRegFrame->ecx = cTransfers;
2990	break;
2991	case DISCPUMODE_64BIT:
2992	pRegFrame->rdi = GCOffset;
2993	pRegFrame->rcx = cTransfers;
2994	break;
2995	default:
2996	AssertFailed();
2997	return VERR_EM_INTERPRETER;
2998	}
2999	}
3000
3001	*pcbSize = cbSize;
3002	return rc;
3003	}
3004	#endif /* !IN_RC */
3005
3006
3007	/**
3008	* [LOCK] CMPXCHG emulation.
3009	*/
3010	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3011	{
3012	DISQPVPARAMVAL param1, param2;
3013	NOREF(pvFault);
3014
3015	#if HC_ARCH_BITS == 32
3016	Assert(pDis->Param1.cb <= 4);
3017	#endif
3018
3019	/* Source to make DISQueryParamVal read the register value - ugly hack */
3020	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3021	if(RT_FAILURE(rc))
3022	return VERR_EM_INTERPRETER;
3023
3024	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
3025	if(RT_FAILURE(rc))
3026	return VERR_EM_INTERPRETER;
3027
3028	uint64_t valpar;
3029	switch(param2.type)
3030	{
3031	case DISQPV_TYPE_IMMEDIATE: /* register actually */
3032	valpar = param2.val.val64;
3033	break;
3034
3035	default:
3036	return VERR_EM_INTERPRETER;
3037	}
3038
3039	PGMPAGEMAPLOCK Lock;
3040	RTGCPTR GCPtrPar1;
3041	void *pvParam1;
3042	uint64_t eflags;
3043
3044	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3045	switch(param1.type)
3046	{
3047	case DISQPV_TYPE_ADDRESS:
3048	GCPtrPar1 = param1.val.val64;
3049	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3050
3051	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3052	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3053	break;
3054
3055	default:
3056	return VERR_EM_INTERPRETER;
3057	}
3058
3059	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
3060
3061	#ifndef VBOX_COMPARE_IEM_AND_EM
3062	if (pDis->fPrefix & DISPREFIX_LOCK)
3063	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3064	else
3065	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3066	#else /* VBOX_COMPARE_IEM_AND_EM */
3067	uint64_t u64;
3068	switch (pDis->Param2.cb)
3069	{
3070	case 1: u64 = (uint8_t )pvParam1; break;
3071	case 2: u64 = (uint16_t )pvParam1; break;
3072	case 4: u64 = (uint32_t )pvParam1; break;
3073	default:
3074	case 8: u64 = (uint64_t )pvParam1; break;
3075	}
3076	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
3077	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3078	#endif /* VBOX_COMPARE_IEM_AND_EM */
3079
3080	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
3081
3082	/* Update guest's eflags and finish. */
3083	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3084	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3085
3086	*pcbSize = param2.size;
3087	PGMPhysReleasePageMappingLock(pVM, &Lock);
3088	return VINF_SUCCESS;
3089	}
3090
3091
3092	/**
3093	* [LOCK] CMPXCHG8B emulation.
3094	*/
3095	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3096	{
3097	DISQPVPARAMVAL param1;
3098	NOREF(pvFault);
3099
3100	/* Source to make DISQueryParamVal read the register value - ugly hack */
3101	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3102	if(RT_FAILURE(rc))
3103	return VERR_EM_INTERPRETER;
3104
3105	RTGCPTR GCPtrPar1;
3106	void *pvParam1;
3107	uint64_t eflags;
3108	PGMPAGEMAPLOCK Lock;
3109
3110	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
3111	switch(param1.type)
3112	{
3113	case DISQPV_TYPE_ADDRESS:
3114	GCPtrPar1 = param1.val.val64;
3115	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3116
3117	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3118	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3119	break;
3120
3121	default:
3122	return VERR_EM_INTERPRETER;
3123	}
3124
3125	LogFlow(("%s %RGv=%p eax=%08x\n", emGetMnemonic(pDis), GCPtrPar1, pvParam1, pRegFrame->eax));
3126
3127	#ifndef VBOX_COMPARE_IEM_AND_EM
3128	if (pDis->fPrefix & DISPREFIX_LOCK)
3129	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3130	else
3131	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3132	#else /* VBOX_COMPARE_IEM_AND_EM */
3133	uint64_t u64 = (uint64_t )pvParam1;
3134	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3135	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
3136	#endif /* VBOX_COMPARE_IEM_AND_EM */
3137
3138	LogFlow(("%s %RGv=%p eax=%08x ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
3139
3140	/* Update guest's eflags and finish; note that only ZF is affected. */
3141	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
3142	\| (eflags & (X86_EFL_ZF));
3143
3144	*pcbSize = 8;
3145	PGMPhysReleasePageMappingLock(pVM, &Lock);
3146	return VINF_SUCCESS;
3147	}
3148
3149
3150	#ifdef IN_RC /** @todo test+enable for HM as well. */
3151	/**
3152	* [LOCK] XADD emulation.
3153	*/
3154	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3155	{
3156	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
3157	DISQPVPARAMVAL param1;
3158	void *pvParamReg2;
3159	size_t cbParamReg2;
3160	NOREF(pvFault);
3161
3162	/* Source to make DISQueryParamVal read the register value - ugly hack */
3163	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3164	if(RT_FAILURE(rc))
3165	return VERR_EM_INTERPRETER;
3166
3167	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3168	Assert(cbParamReg2 <= 4);
3169	if(RT_FAILURE(rc))
3170	return VERR_EM_INTERPRETER;
3171
3172	#ifdef IN_RC
3173	if (TRPMHasTrap(pVCpu))
3174	{
3175	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3176	{
3177	#endif
3178	RTGCPTR GCPtrPar1;
3179	void *pvParam1;
3180	uint32_t eflags;
3181	PGMPAGEMAPLOCK Lock;
3182
3183	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3184	switch(param1.type)
3185	{
3186	case DISQPV_TYPE_ADDRESS:
3187	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3188	#ifdef IN_RC
3189	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3190	#endif
3191
3192	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3193	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3194	break;
3195
3196	default:
3197	return VERR_EM_INTERPRETER;
3198	}
3199
3200	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3201
3202	#ifndef VBOX_COMPARE_IEM_AND_EM
3203	if (pDis->fPrefix & DISPREFIX_LOCK)
3204	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3205	else
3206	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3207	#else /* VBOX_COMPARE_IEM_AND_EM */
3208	uint64_t u64;
3209	switch (cbParamReg2)
3210	{
3211	case 1: u64 = (uint8_t )pvParam1; break;
3212	case 2: u64 = (uint16_t )pvParam1; break;
3213	case 4: u64 = (uint32_t )pvParam1; break;
3214	default:
3215	case 8: u64 = (uint64_t )pvParam1; break;
3216	}
3217	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3218	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3219	#endif /* VBOX_COMPARE_IEM_AND_EM */
3220
3221	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3222
3223	/* Update guest's eflags and finish. */
3224	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3225	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3226
3227	*pcbSize = cbParamReg2;
3228	PGMPhysReleasePageMappingLock(pVM, &Lock);
3229	return VINF_SUCCESS;
3230	#ifdef IN_RC
3231	}
3232	}
3233
3234	return VERR_EM_INTERPRETER;
3235	#endif
3236	}
3237	#endif /* IN_RC */
3238
3239
3240	/**
3241	* WBINVD Emulation.
3242	*/
3243	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3244	{
3245	/* Nothing to do. */
3246	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3247	return VINF_SUCCESS;
3248	}
3249
3250
3251	/**
3252	* INVLPG Emulation.
3253	*/
3254	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3255	{
3256	DISQPVPARAMVAL param1;
3257	RTGCPTR addr;
3258	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3259
3260	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3261	if(RT_FAILURE(rc))
3262	return VERR_EM_INTERPRETER;
3263
3264	switch(param1.type)
3265	{
3266	case DISQPV_TYPE_IMMEDIATE:
3267	case DISQPV_TYPE_ADDRESS:
3268	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3269	return VERR_EM_INTERPRETER;
3270	addr = (RTGCPTR)param1.val.val64;
3271	break;
3272
3273	default:
3274	return VERR_EM_INTERPRETER;
3275	}
3276
3277	/** @todo is addr always a flat linear address or ds based
3278	* (in absence of segment override prefixes)????
3279	*/
3280	#ifdef IN_RC
3281	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3282	#endif
3283	rc = PGMInvalidatePage(pVCpu, addr);
3284	if ( rc == VINF_SUCCESS
3285	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3286	return VINF_SUCCESS;
3287	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3288	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3289	VERR_EM_INTERPRETER);
3290	return rc;
3291	}
3292
3293	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3294
3295	/**
3296	* CPUID Emulation.
3297	*/
3298	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3299	{
3300	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3301	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3302	return rc;
3303	}
3304
3305
3306	/**
3307	* CLTS Emulation.
3308	*/
3309	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3310	{
3311	NOREF(pVM); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3312
3313	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3314	if (!(cr0 & X86_CR0_TS))
3315	return VINF_SUCCESS;
3316	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
3317	}
3318
3319
3320	/**
3321	* LMSW Emulation.
3322	*/
3323	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3324	{
3325	DISQPVPARAMVAL param1;
3326	uint32_t val;
3327	NOREF(pvFault); NOREF(pcbSize);
3328	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3329
3330	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3331	if(RT_FAILURE(rc))
3332	return VERR_EM_INTERPRETER;
3333
3334	switch(param1.type)
3335	{
3336	case DISQPV_TYPE_IMMEDIATE:
3337	case DISQPV_TYPE_ADDRESS:
3338	if(!(param1.flags & DISQPV_FLAG_16))
3339	return VERR_EM_INTERPRETER;
3340	val = param1.val.val32;
3341	break;
3342
3343	default:
3344	return VERR_EM_INTERPRETER;
3345	}
3346
3347	LogFlow(("emInterpretLmsw %x\n", val));
3348	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
3349
3350	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
3351	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
3352	\| (val & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
3353
3354	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
3355
3356	}
3357
3358	#ifdef EM_EMULATE_SMSW
3359	/**
3360	* SMSW Emulation.
3361	*/
3362	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3363	{
3364	NOREF(pvFault); NOREF(pcbSize);
3365	DISQPVPARAMVAL param1;
3366	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3367
3368	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3369	if(RT_FAILURE(rc))
3370	return VERR_EM_INTERPRETER;
3371
3372	switch(param1.type)
3373	{
3374	case DISQPV_TYPE_IMMEDIATE:
3375	if(param1.size != sizeof(uint16_t))
3376	return VERR_EM_INTERPRETER;
3377	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3378	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3379	break;
3380
3381	case DISQPV_TYPE_ADDRESS:
3382	{
3383	RTGCPTR pParam1;
3384
3385	/* Actually forced to 16 bits regardless of the operand size. */
3386	if(param1.size != sizeof(uint16_t))
3387	return VERR_EM_INTERPRETER;
3388
3389	pParam1 = (RTGCPTR)param1.val.val64;
3390	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3391	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3392
3393	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3394	if (RT_FAILURE(rc))
3395	{
3396	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3397	return VERR_EM_INTERPRETER;
3398	}
3399	break;
3400	}
3401
3402	default:
3403	return VERR_EM_INTERPRETER;
3404	}
3405
3406	LogFlow(("emInterpretSmsw %x\n", cr0));
3407	return rc;
3408	}
3409	#endif
3410
3411	/**
3412	* MOV CRx
3413	*/
3414	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3415	{
3416	NOREF(pvFault); NOREF(pcbSize);
3417	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3418	return emInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3419
3420	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3421	return emInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3422
3423	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3424	}
3425
3426
3427	/**
3428	* MOV DRx
3429	*/
3430	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3431	{
3432	int rc = VERR_EM_INTERPRETER;
3433	NOREF(pvFault); NOREF(pcbSize);
3434
3435	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3436	{
3437	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3438	}
3439	else
3440	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3441	{
3442	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3443	}
3444	else
3445	AssertMsgFailed(("Unexpected debug register move\n"));
3446
3447	return rc;
3448	}
3449
3450
3451	/**
3452	* LLDT Emulation.
3453	*/
3454	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3455	{
3456	DISQPVPARAMVAL param1;
3457	RTSEL sel;
3458	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3459
3460	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3461	if(RT_FAILURE(rc))
3462	return VERR_EM_INTERPRETER;
3463
3464	switch(param1.type)
3465	{
3466	case DISQPV_TYPE_ADDRESS:
3467	return VERR_EM_INTERPRETER; //feeling lazy right now
3468
3469	case DISQPV_TYPE_IMMEDIATE:
3470	if(!(param1.flags & DISQPV_FLAG_16))
3471	return VERR_EM_INTERPRETER;
3472	sel = (RTSEL)param1.val.val16;
3473	break;
3474
3475	default:
3476	return VERR_EM_INTERPRETER;
3477	}
3478
3479	#ifdef IN_RING0
3480	/* Only for the VT-x real-mode emulation case. */
3481	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3482	CPUMSetGuestLDTR(pVCpu, sel);
3483	return VINF_SUCCESS;
3484	#else
3485	if (sel == 0)
3486	{
3487	if (CPUMGetHyperLDTR(pVCpu) == 0)
3488	{
3489	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3490	return VINF_SUCCESS;
3491	}
3492	}
3493	//still feeling lazy
3494	return VERR_EM_INTERPRETER;
3495	#endif
3496	}
3497
3498	#ifdef IN_RING0
3499	/**
3500	* LIDT/LGDT Emulation.
3501	*/
3502	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3503	{
3504	DISQPVPARAMVAL param1;
3505	RTGCPTR pParam1;
3506	X86XDTR32 dtr32;
3507	NOREF(pvFault); NOREF(pcbSize);
3508
3509	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3510
3511	/* Only for the VT-x real-mode emulation case. */
3512	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3513
3514	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3515	if(RT_FAILURE(rc))
3516	return VERR_EM_INTERPRETER;
3517
3518	switch(param1.type)
3519	{
3520	case DISQPV_TYPE_ADDRESS:
3521	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3522	break;
3523
3524	default:
3525	return VERR_EM_INTERPRETER;
3526	}
3527
3528	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3529	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3530
3531	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3532	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3533
3534	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3535	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3536	else
3537	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3538
3539	return VINF_SUCCESS;
3540	}
3541	#endif
3542
3543
3544	#ifdef IN_RC
3545	/**
3546	* STI Emulation.
3547	*
3548	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3549	*/
3550	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3551	{
3552	NOREF(pcbSize);
3553	PPATMGCSTATE pGCState = PATMGetGCState(pVM);
3554
3555	if(!pGCState)
3556	{
3557	Assert(pGCState);
3558	return VERR_EM_INTERPRETER;
3559	}
3560	pGCState->uVMFlags \|= X86_EFL_IF;
3561
3562	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3563	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3564
3565	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3566	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3567
3568	return VINF_SUCCESS;
3569	}
3570	#endif /* IN_RC */
3571
3572
3573	/**
3574	* HLT Emulation.
3575	*/
3576	static VBOXSTRICTRC
3577	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3578	{
3579	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3580	return VINF_EM_HALT;
3581	}
3582
3583
3584	/**
3585	* RDTSC Emulation.
3586	*/
3587	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3588	{
3589	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3590	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3591	}
3592
3593	/**
3594	* RDPMC Emulation
3595	*/
3596	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3597	{
3598	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3599	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3600	}
3601
3602
3603	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3604	{
3605	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3606	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3607	}
3608
3609
3610	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3611	{
3612	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3613	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3614	}
3615
3616
3617	/**
3618	* RDMSR Emulation.
3619	*/
3620	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3621	{
3622	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3623	different, so we play safe by completely disassembling the instruction. */
3624	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3625	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3626	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3627	}
3628
3629
3630	/**
3631	* WRMSR Emulation.
3632	*/
3633	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3634	{
3635	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3636	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3637	}
3638
3639
3640	/**
3641	* Internal worker.
3642	* @copydoc emInterpretInstructionCPUOuter
3643	* @param pVM The cross context VM structure.
3644	*/
3645	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3646	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3647	{
3648	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3649	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3650	Assert(pcbSize);
3651	*pcbSize = 0;
3652
3653	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3654	{
3655	/*
3656	* Only supervisor guest code!!
3657	* And no complicated prefixes.
3658	*/
3659	/* Get the current privilege level. */
3660	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3661	#ifdef VBOX_WITH_RAW_RING1
3662	if ( !EMIsRawRing1Enabled(pVM)
3663	\|\| cpl > 1
3664	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3665	)
3666	#endif
3667	{
3668	if ( cpl != 0
3669	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3670	{
3671	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3672	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3673	return VERR_EM_INTERPRETER;
3674	}
3675	}
3676	}
3677	else
3678	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3679
3680	#ifdef IN_RC
3681	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3682	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3683	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3684	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3685	&& pDis->pCurInstr->uOpcode != OP_XADD
3686	&& pDis->pCurInstr->uOpcode != OP_OR
3687	&& pDis->pCurInstr->uOpcode != OP_AND
3688	&& pDis->pCurInstr->uOpcode != OP_XOR
3689	&& pDis->pCurInstr->uOpcode != OP_BTR
3690	)
3691	)
3692	#else
3693	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3694	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3695	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3696	)
3697	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3698	&& pDis->pCurInstr->uOpcode != OP_OR
3699	&& pDis->pCurInstr->uOpcode != OP_AND
3700	&& pDis->pCurInstr->uOpcode != OP_XOR
3701	&& pDis->pCurInstr->uOpcode != OP_BTR
3702	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3703	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3704	)
3705	)
3706	#endif
3707	{
3708	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3709	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3710	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3711	return VERR_EM_INTERPRETER;
3712	}
3713
3714	#if HC_ARCH_BITS == 32
3715	/*
3716	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3717	* Whitelisted instructions are safe.
3718	*/
3719	if ( pDis->Param1.cb > 4
3720	&& CPUMIsGuestIn64BitCode(pVCpu))
3721	{
3722	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3723	if ( uOpCode != OP_STOSWD
3724	&& uOpCode != OP_MOV
3725	&& uOpCode != OP_CMPXCHG8B
3726	&& uOpCode != OP_XCHG
3727	&& uOpCode != OP_BTS
3728	&& uOpCode != OP_BTR
3729	&& uOpCode != OP_BTC
3730	)
3731	{
3732	# ifdef VBOX_WITH_STATISTICS
3733	switch (pDis->pCurInstr->uOpcode)
3734	{
3735	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3736	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3737	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3738	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3739	INTERPRET_FAILED_CASE(OP_INC,Inc);
3740	INTERPRET_FAILED_CASE(OP_POP,Pop);
3741	INTERPRET_FAILED_CASE(OP_OR, Or);
3742	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3743	INTERPRET_FAILED_CASE(OP_AND,And);
3744	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3745	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3746	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3747	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3748	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3749	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3750	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3751	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3752	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3753	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3754	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3755	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3756	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3757	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3758	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3759	INTERPRET_FAILED_CASE(OP_ADD,Add);
3760	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3761	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3762	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3763	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3764	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3765	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3766	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3767	INTERPRET_FAILED_CASE(OP_STI, Sti);
3768	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3769	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3770	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3771	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3772	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3773	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3774	# undef INTERPRET_FAILED_CASE
3775	default:
3776	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3777	break;
3778	}
3779	# endif /* VBOX_WITH_STATISTICS */
3780	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3781	return VERR_EM_INTERPRETER;
3782	}
3783	}
3784	#endif
3785
3786	VBOXSTRICTRC rc;
3787	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3788	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3789	#endif
3790	switch (pDis->pCurInstr->uOpcode)
3791	{
3792	/*
3793	* Macros for generating the right case statements.
3794	*/
3795	# ifndef VBOX_COMPARE_IEM_AND_EM
3796	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3797	case opcode:\
3798	if (pDis->fPrefix & DISPREFIX_LOCK) \
3799	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3800	else \
3801	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3802	if (RT_SUCCESS(rc)) \
3803	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3804	else \
3805	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3806	return rc
3807	# else /* VBOX_COMPARE_IEM_AND_EM */
3808	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3809	case opcode:\
3810	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3811	if (RT_SUCCESS(rc)) \
3812	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3813	else \
3814	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3815	return rc
3816	# endif /* VBOX_COMPARE_IEM_AND_EM */
3817
3818	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3819	case opcode:\
3820	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3821	if (RT_SUCCESS(rc)) \
3822	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3823	else \
3824	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3825	return rc
3826
3827	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3828	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3829	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3830	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3831
3832	#define INTERPRET_CASE(opcode, Instr) \
3833	case opcode:\
3834	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3835	if (RT_SUCCESS(rc)) \
3836	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3837	else \
3838	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3839	return rc
3840
3841	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3842	case opcode:\
3843	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3844	if (RT_SUCCESS(rc)) \
3845	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3846	else \
3847	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3848	return rc
3849
3850	#define INTERPRET_STAT_CASE(opcode, Instr) \
3851	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3852
3853	/*
3854	* The actual case statements.
3855	*/
3856	INTERPRET_CASE(OP_XCHG,Xchg);
3857	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3858	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3859	INTERPRET_CASE(OP_POP,Pop);
3860	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3861	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3862	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3863	INTERPRET_CASE(OP_MOV,Mov);
3864	#ifndef IN_RC
3865	INTERPRET_CASE(OP_STOSWD,StosWD);
3866	#endif
3867	INTERPRET_CASE(OP_INVLPG,InvlPg);
3868	INTERPRET_CASE(OP_CPUID,CpuId);
3869	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3870	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3871	#ifdef IN_RING0
3872	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3873	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3874	#endif
3875	INTERPRET_CASE(OP_LLDT,LLdt);
3876	INTERPRET_CASE(OP_LMSW,Lmsw);
3877	#ifdef EM_EMULATE_SMSW
3878	INTERPRET_CASE(OP_SMSW,Smsw);
3879	#endif
3880	INTERPRET_CASE(OP_CLTS,Clts);
3881	INTERPRET_CASE(OP_MONITOR, Monitor);
3882	INTERPRET_CASE(OP_MWAIT, MWait);
3883	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3884	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3885	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3886	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3887	INTERPRET_CASE(OP_ADC,Adc);
3888	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3889	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3890	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3891	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3892	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3893	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3894	#ifdef IN_RC
3895	INTERPRET_CASE(OP_STI,Sti);
3896	INTERPRET_CASE(OP_XADD, XAdd);
3897	INTERPRET_CASE(OP_IRET,Iret);
3898	#endif
3899	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3900	INTERPRET_CASE(OP_HLT,Hlt);
3901	INTERPRET_CASE(OP_WBINVD,WbInvd);
3902	#ifdef VBOX_WITH_STATISTICS
3903	# ifndef IN_RC
3904	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3905	# endif
3906	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3907	#endif
3908
3909	default:
3910	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3911	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3912	return VERR_EM_INTERPRETER;
3913
3914	#undef INTERPRET_CASE_EX_PARAM2
3915	#undef INTERPRET_STAT_CASE
3916	#undef INTERPRET_CASE_EX
3917	#undef INTERPRET_CASE
3918	} /* switch (opcode) */
3919	/* not reached */
3920	}
3921
3922	/**
3923	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3924	*
3925	* EIP is NOT updated!
3926	*
3927	* @returns VBox strict status code.
3928	* @retval VINF_* Scheduling instructions. When these are returned, it
3929	* starts to get a bit tricky to know whether code was
3930	* executed or not... We'll address this when it becomes a problem.
3931	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3932	* @retval VERR_* Fatal errors.
3933	*
3934	* @param pVCpu The cross context virtual CPU structure.
3935	* @param pDis The disassembler cpu state for the instruction to be
3936	* interpreted.
3937	* @param pRegFrame The register frame. EIP is NOT changed!
3938	* @param pvFault The fault address (CR2).
3939	* @param pcbSize Size of the write (if applicable).
3940	* @param enmCodeType Code type (user/supervisor)
3941	*
3942	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
3943	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
3944	* to worry about e.g. invalid modrm combinations (!)
3945	*
3946	* @todo At this time we do NOT check if the instruction overwrites vital information.
3947	* Make sure this can't happen!! (will add some assertions/checks later)
3948	*/
3949	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3950	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3951	{
3952	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3953	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
3954	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3955	if (RT_SUCCESS(rc))
3956	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3957	else
3958	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
3959	return rc;
3960	}
3961
3962
3963	#endif /* !VBOX_WITH_IEM */

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 60185

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