EMAll.cpp@ 56287

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1	/* $Id: EMAll.cpp 56287 2015-06-09 11:15:22Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_EM
22	#include <VBox/vmm/em.h>
23	#include <VBox/vmm/mm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/pgm.h>
28	#ifdef VBOX_WITH_IEM
29	# include <VBox/vmm/iem.h>
30	#endif
31	#include <VBox/vmm/iom.h>
32	#include <VBox/vmm/stam.h>
33	#include "EMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/vmm.h>
36	#include <VBox/vmm/hm.h>
37	#include <VBox/vmm/tm.h>
38	#include <VBox/vmm/pdmapi.h>
39	#include <VBox/param.h>
40	#include <VBox/err.h>
41	#include <VBox/dis.h>
42	#include <VBox/disopcode.h>
43	#include <VBox/log.h>
44	#include "internal/pgm.h"
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49	#ifndef IN_RC
50	#undef VBOX_WITH_IEM
51	#endif
52	#ifdef VBOX_WITH_IEM
53	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
54	//# define VBOX_SAME_AS_EM
55	//# define VBOX_COMPARE_IEM_LAST
56	#endif
57
58	#ifdef VBOX_WITH_RAW_RING1
59	# define EM_EMULATE_SMSW
60	#endif
61
62
63	/*******************************************************************************
64	* Defined Constants And Macros *
65	*******************************************************************************/
66	/** @def EM_ASSERT_FAULT_RETURN
67	* Safety check.
68	*
69	* Could in theory misfire on a cross page boundary access...
70	*
71	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
72	* turns up an alias page instead of the original faulting one and annoying the
73	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
74	*/
75	#if 0
76	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
77	#else
78	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
79	#endif
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
86	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
87	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
88	#endif
89
90
91	/*******************************************************************************
92	* Global Variables *
93	*******************************************************************************/
94	#ifdef VBOX_COMPARE_IEM_AND_EM
95	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
96	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
97	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
98	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
99	static uint32_t g_fIncomingFFs;
100	static CPUMCTX g_IncomingCtx;
101	static bool g_fIgnoreRaxRdx = false;
102
103	static uint32_t g_fEmFFs;
104	static CPUMCTX g_EmCtx;
105	static uint8_t g_abEmWrote[256];
106	static size_t g_cbEmWrote;
107
108	static uint32_t g_fIemFFs;
109	static CPUMCTX g_IemCtx;
110	extern uint8_t g_abIemWrote[256];
111	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
112	extern size_t g_cbIemWrote;
113	#else
114	static size_t g_cbIemWrote;
115	#endif
116	#endif
117
118
119	/**
120	* Get the current execution manager status.
121	*
122	* @returns Current status.
123	* @param pVCpu Pointer to the VMCPU.
124	*/
125	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
126	{
127	return pVCpu->em.s.enmState;
128	}
129
130	/**
131	* Sets the current execution manager status. (use only when you know what you're doing!)
132	*
133	* @param pVCpu Pointer to the VMCPU.
134	*/
135	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
136	{
137	/* Only allowed combination: */
138	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
139	pVCpu->em.s.enmState = enmNewState;
140	}
141
142
143	/**
144	* Sets the PC for which interrupts should be inhibited.
145	*
146	* @param pVCpu Pointer to the VMCPU.
147	* @param PC The PC.
148	*/
149	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
150	{
151	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
152	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
153	}
154
155
156	/**
157	* Gets the PC for which interrupts should be inhibited.
158	*
159	* There are a few instructions which inhibits or delays interrupts
160	* for the instruction following them. These instructions are:
161	* - STI
162	* - MOV SS, r/m16
163	* - POP SS
164	*
165	* @returns The PC for which interrupts should be inhibited.
166	* @param pVCpu Pointer to the VMCPU.
167	*
168	*/
169	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
170	{
171	return pVCpu->em.s.GCPtrInhibitInterrupts;
172	}
173
174
175	/**
176	* Prepare an MWAIT - essentials of the MONITOR instruction.
177	*
178	* @returns VINF_SUCCESS
179	* @param pVCpu The current CPU.
180	* @param rax The content of RAX.
181	* @param rcx The content of RCX.
182	* @param rdx The content of RDX.
183	* @param GCPhys The physical address corresponding to rax.
184	*/
185	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
186	{
187	pVCpu->em.s.MWait.uMonitorRAX = rax;
188	pVCpu->em.s.MWait.uMonitorRCX = rcx;
189	pVCpu->em.s.MWait.uMonitorRDX = rdx;
190	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
191	/** @todo Make use of GCPhys. */
192	NOREF(GCPhys);
193	/** @todo Complete MONITOR implementation. */
194	return VINF_SUCCESS;
195	}
196
197
198	/**
199	* Performs an MWAIT.
200	*
201	* @returns VINF_SUCCESS
202	* @param pVCpu The current CPU.
203	* @param rax The content of RAX.
204	* @param rcx The content of RCX.
205	*/
206	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
207	{
208	pVCpu->em.s.MWait.uMWaitRAX = rax;
209	pVCpu->em.s.MWait.uMWaitRCX = rcx;
210	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
211	if (rcx)
212	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
213	else
214	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
215	/** @todo not completely correct?? */
216	return VINF_EM_HALT;
217	}
218
219
220
221	/**
222	* Determine if we should continue after encountering a mwait instruction.
223	*
224	* Clears MWAIT flags if returning @c true.
225	*
226	* @returns true if we should continue, false if we should halt.
227	* @param pVCpu Pointer to the VMCPU.
228	* @param pCtx Current CPU context.
229	*/
230	VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
231	{
232	if ( pCtx->eflags.Bits.u1IF
233	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
234	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
235	{
236	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
237	{
238	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
239	return true;
240	}
241	}
242
243	return false;
244	}
245
246
247	/**
248	* Determine if we should continue after encountering a hlt instruction.
249	*
250	* @returns true if we should continue, false if we should halt.
251	* @param pVCpu Pointer to the VMCPU.
252	* @param pCtx Current CPU context.
253	*/
254	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
255	{
256	if (pCtx->eflags.Bits.u1IF)
257	return !!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
258	return false;
259	}
260
261
262	/**
263	* Locks REM execution to a single VCPU.
264	*
265	* @param pVM Pointer to the VM.
266	*/
267	VMMDECL(void) EMRemLock(PVM pVM)
268	{
269	#ifdef VBOX_WITH_REM
270	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
271	return; /* early init */
272
273	Assert(!PGMIsLockOwner(pVM));
274	Assert(!IOMIsLockWriteOwner(pVM));
275	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
276	AssertRCSuccess(rc);
277	#endif
278	}
279
280
281	/**
282	* Unlocks REM execution
283	*
284	* @param pVM Pointer to the VM.
285	*/
286	VMMDECL(void) EMRemUnlock(PVM pVM)
287	{
288	#ifdef VBOX_WITH_REM
289	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
290	return; /* early init */
291
292	PDMCritSectLeave(&pVM->em.s.CritSectREM);
293	#endif
294	}
295
296
297	/**
298	* Check if this VCPU currently owns the REM lock.
299	*
300	* @returns bool owner/not owner
301	* @param pVM Pointer to the VM.
302	*/
303	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
304	{
305	#ifdef VBOX_WITH_REM
306	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
307	return true; /* early init */
308
309	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
310	#else
311	return true;
312	#endif
313	}
314
315
316	/**
317	* Try to acquire the REM lock.
318	*
319	* @returns VBox status code
320	* @param pVM Pointer to the VM.
321	*/
322	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
323	{
324	#ifdef VBOX_WITH_REM
325	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
326	return VINF_SUCCESS; /* early init */
327
328	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
329	#else
330	return VINF_SUCCESS;
331	#endif
332	}
333
334
335	/**
336	* @callback_method_impl{FNDISREADBYTES}
337	*/
338	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
339	{
340	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
341	#if defined(IN_RC) \|\| defined(IN_RING3)
342	PVM pVM = pVCpu->CTX_SUFF(pVM);
343	#endif
344	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
345	int rc;
346
347	/*
348	* Figure how much we can or must read.
349	*/
350	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
351	if (cbToRead > cbMaxRead)
352	cbToRead = cbMaxRead;
353	else if (cbToRead < cbMinRead)
354	cbToRead = cbMinRead;
355
356	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
357	/*
358	* We might be called upon to interpret an instruction in a patch.
359	*/
360	if (PATMIsPatchGCAddr(pVCpu->CTX_SUFF(pVM), uSrcAddr))
361	{
362	# ifdef IN_RC
363	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
364	# else
365	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVCpu->CTX_SUFF(pVM), uSrcAddr), cbToRead);
366	# endif
367	rc = VINF_SUCCESS;
368	}
369	else
370	#endif
371	{
372	# ifdef IN_RC
373	/*
374	* Try access it thru the shadow page tables first. Fall back on the
375	* slower PGM method if it fails because the TLB or page table was
376	* modified recently.
377	*/
378	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
379	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
380	{
381	cbToRead = cbMinRead;
382	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
383	}
384	if (rc == VERR_ACCESS_DENIED)
385	#endif
386	{
387	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
388	if (RT_FAILURE(rc))
389	{
390	if (cbToRead > cbMinRead)
391	{
392	cbToRead = cbMinRead;
393	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
394	}
395	if (RT_FAILURE(rc))
396	{
397	#ifndef IN_RC
398	/*
399	* If we fail to find the page via the guest's page tables
400	* we invalidate the page in the host TLB (pertaining to
401	* the guest in the NestedPaging case). See @bugref{6043}.
402	*/
403	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
404	{
405	HMInvalidatePage(pVCpu, uSrcAddr);
406	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
407	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
408	}
409	#endif
410	}
411	}
412	}
413	}
414
415	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
416	return rc;
417	}
418
419
420	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
421	{
422	NOREF(pVM);
423	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
424	}
425
426
427	/**
428	* Disassembles the current instruction.
429	*
430	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
431	* details.
432	*
433	* @param pVM Pointer to the VM.
434	* @param pVCpu Pointer to the VMCPU.
435	* @param pDis Where to return the parsed instruction info.
436	* @param pcbInstr Where to return the instruction size. (optional)
437	*/
438	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
439	{
440	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
441	RTGCPTR GCPtrInstr;
442	#if 0
443	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
444	#else
445	/** @todo Get the CPU mode as well while we're at it! */
446	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
447	pCtxCore->rip, &GCPtrInstr);
448	#endif
449	if (RT_FAILURE(rc))
450	{
451	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
452	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
453	return rc;
454	}
455	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
456	}
457
458
459	/**
460	* Disassembles one instruction.
461	*
462	* This is used by internally by the interpreter and by trap/access handlers.
463	*
464	* @returns VBox status code.
465	*
466	* @param pVM Pointer to the VM.
467	* @param pVCpu Pointer to the VMCPU.
468	* @param GCPtrInstr The flat address of the instruction.
469	* @param pCtxCore The context core (used to determine the cpu mode).
470	* @param pDis Where to return the parsed instruction info.
471	* @param pcbInstr Where to return the instruction size. (optional)
472	*/
473	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
474	PDISCPUSTATE pDis, unsigned *pcbInstr)
475	{
476	NOREF(pVM);
477	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu));
478	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
479	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
480	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
481	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
482	if (RT_SUCCESS(rc))
483	return VINF_SUCCESS;
484	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
485	return rc;
486	}
487
488
489	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
490	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
491	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
492	uint32_t cbEm, uint32_t cbIem)
493	{
494	/* Quick compare. */
495	if ( rcEm == rcIem
496	&& cbEm == cbIem
497	&& g_cbEmWrote == g_cbIemWrote
498	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
499	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
500	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
501	)
502	return;
503
504	/* Report exact differences. */
505	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
506	if (rcEm != rcIem)
507	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
508	else if (cbEm != cbIem)
509	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
510
511	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
512	{
513	if (g_cbIemWrote != g_cbEmWrote)
514	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
515	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
516	{
517	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
518	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
519	}
520
521	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
522	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
523	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
524
525	# define CHECK_FIELD(a_Field) \
526	do \
527	{ \
528	if (pEmCtx->a_Field != pIemCtx->a_Field) \
529	{ \
530	switch (sizeof(pEmCtx->a_Field)) \
531	{ \
532	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
533	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
534	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
535	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
536	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
537	} \
538	cDiffs++; \
539	} \
540	} while (0)
541
542	# define CHECK_BIT_FIELD(a_Field) \
543	do \
544	{ \
545	if (pEmCtx->a_Field != pIemCtx->a_Field) \
546	{ \
547	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
548	cDiffs++; \
549	} \
550	} while (0)
551
552	# define CHECK_SEL(a_Sel) \
553	do \
554	{ \
555	CHECK_FIELD(a_Sel.Sel); \
556	CHECK_FIELD(a_Sel.Attr.u); \
557	CHECK_FIELD(a_Sel.u64Base); \
558	CHECK_FIELD(a_Sel.u32Limit); \
559	CHECK_FIELD(a_Sel.fFlags); \
560	} while (0)
561
562	unsigned cDiffs = 0;
563	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
564	{
565	RTLogPrintf(" the FPU state differs\n");
566	cDiffs++;
567	CHECK_FIELD(fpu.FCW);
568	CHECK_FIELD(fpu.FSW);
569	CHECK_FIELD(fpu.FTW);
570	CHECK_FIELD(fpu.FOP);
571	CHECK_FIELD(fpu.FPUIP);
572	CHECK_FIELD(fpu.CS);
573	CHECK_FIELD(fpu.Rsrvd1);
574	CHECK_FIELD(fpu.FPUDP);
575	CHECK_FIELD(fpu.DS);
576	CHECK_FIELD(fpu.Rsrvd2);
577	CHECK_FIELD(fpu.MXCSR);
578	CHECK_FIELD(fpu.MXCSR_MASK);
579	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
580	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
581	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
582	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
583	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
584	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
585	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
586	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
587	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
588	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
589	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
590	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
591	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
592	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
593	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
594	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
595	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
596	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
597	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
598	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
599	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
600	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
601	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
602	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
603	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
604	CHECK_FIELD(fpu.au32RsrvdRest[i]);
605	}
606	CHECK_FIELD(rip);
607	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
608	{
609	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
610	CHECK_BIT_FIELD(rflags.Bits.u1CF);
611	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
612	CHECK_BIT_FIELD(rflags.Bits.u1PF);
613	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
614	CHECK_BIT_FIELD(rflags.Bits.u1AF);
615	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
616	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
617	CHECK_BIT_FIELD(rflags.Bits.u1SF);
618	CHECK_BIT_FIELD(rflags.Bits.u1TF);
619	CHECK_BIT_FIELD(rflags.Bits.u1IF);
620	CHECK_BIT_FIELD(rflags.Bits.u1DF);
621	CHECK_BIT_FIELD(rflags.Bits.u1OF);
622	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
623	CHECK_BIT_FIELD(rflags.Bits.u1NT);
624	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
625	CHECK_BIT_FIELD(rflags.Bits.u1RF);
626	CHECK_BIT_FIELD(rflags.Bits.u1VM);
627	CHECK_BIT_FIELD(rflags.Bits.u1AC);
628	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
629	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
630	CHECK_BIT_FIELD(rflags.Bits.u1ID);
631	}
632
633	if (!g_fIgnoreRaxRdx)
634	CHECK_FIELD(rax);
635	CHECK_FIELD(rcx);
636	if (!g_fIgnoreRaxRdx)
637	CHECK_FIELD(rdx);
638	CHECK_FIELD(rbx);
639	CHECK_FIELD(rsp);
640	CHECK_FIELD(rbp);
641	CHECK_FIELD(rsi);
642	CHECK_FIELD(rdi);
643	CHECK_FIELD(r8);
644	CHECK_FIELD(r9);
645	CHECK_FIELD(r10);
646	CHECK_FIELD(r11);
647	CHECK_FIELD(r12);
648	CHECK_FIELD(r13);
649	CHECK_SEL(cs);
650	CHECK_SEL(ss);
651	CHECK_SEL(ds);
652	CHECK_SEL(es);
653	CHECK_SEL(fs);
654	CHECK_SEL(gs);
655	CHECK_FIELD(cr0);
656	CHECK_FIELD(cr2);
657	CHECK_FIELD(cr3);
658	CHECK_FIELD(cr4);
659	CHECK_FIELD(dr[0]);
660	CHECK_FIELD(dr[1]);
661	CHECK_FIELD(dr[2]);
662	CHECK_FIELD(dr[3]);
663	CHECK_FIELD(dr[6]);
664	CHECK_FIELD(dr[7]);
665	CHECK_FIELD(gdtr.cbGdt);
666	CHECK_FIELD(gdtr.pGdt);
667	CHECK_FIELD(idtr.cbIdt);
668	CHECK_FIELD(idtr.pIdt);
669	CHECK_SEL(ldtr);
670	CHECK_SEL(tr);
671	CHECK_FIELD(SysEnter.cs);
672	CHECK_FIELD(SysEnter.eip);
673	CHECK_FIELD(SysEnter.esp);
674	CHECK_FIELD(msrEFER);
675	CHECK_FIELD(msrSTAR);
676	CHECK_FIELD(msrPAT);
677	CHECK_FIELD(msrLSTAR);
678	CHECK_FIELD(msrCSTAR);
679	CHECK_FIELD(msrSFMASK);
680	CHECK_FIELD(msrKERNELGSBASE);
681
682	# undef CHECK_FIELD
683	# undef CHECK_BIT_FIELD
684	}
685	}
686	#endif /* VBOX_COMPARE_IEM_AND_EM */
687
688
689	/**
690	* Interprets the current instruction.
691	*
692	* @returns VBox status code.
693	* @retval VINF_* Scheduling instructions.
694	* @retval VERR_EM_INTERPRETER Something we can't cope with.
695	* @retval VERR_* Fatal errors.
696	*
697	* @param pVCpu Pointer to the VMCPU.
698	* @param pRegFrame The register frame.
699	* Updates the EIP if an instruction was executed successfully.
700	* @param pvFault The fault address (CR2).
701	* @param pcbSize Size of the write (if applicable).
702	*
703	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
704	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
705	* to worry about e.g. invalid modrm combinations (!)
706	*/
707	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
708	{
709	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
710	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
711	#ifdef VBOX_WITH_IEM
712	NOREF(pvFault);
713
714	# ifdef VBOX_COMPARE_IEM_AND_EM
715	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
716	g_IncomingCtx = *pCtx;
717	g_fIncomingFFs = pVCpu->fLocalForcedActions;
718	g_cbEmWrote = g_cbIemWrote = 0;
719
720	# ifdef VBOX_COMPARE_IEM_FIRST
721	/* IEM */
722	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
723	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
724	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
725	rcIem = VERR_EM_INTERPRETER;
726	g_IemCtx = *pCtx;
727	g_fIemFFs = pVCpu->fLocalForcedActions;
728	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
729	*pCtx = g_IncomingCtx;
730	# endif
731
732	/* EM */
733	RTGCPTR pbCode;
734	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
735	if (RT_SUCCESS(rcEm))
736	{
737	uint32_t cbOp;
738	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
739	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
740	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
741	if (RT_SUCCESS(rcEm))
742	{
743	Assert(cbOp == pDis->cbInstr);
744	uint32_t cbIgnored;
745	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
746	if (RT_SUCCESS(rcEm))
747	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
748
749	}
750	rcEm = VERR_EM_INTERPRETER;
751	}
752	else
753	rcEm = VERR_EM_INTERPRETER;
754	# ifdef VBOX_SAME_AS_EM
755	if (rcEm == VERR_EM_INTERPRETER)
756	{
757	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
758	return rcEm;
759	}
760	# endif
761	g_EmCtx = *pCtx;
762	g_fEmFFs = pVCpu->fLocalForcedActions;
763	VBOXSTRICTRC rc = rcEm;
764
765	# ifdef VBOX_COMPARE_IEM_LAST
766	/* IEM */
767	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
768	*pCtx = g_IncomingCtx;
769	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
770	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
771	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
772	rcIem = VERR_EM_INTERPRETER;
773	g_IemCtx = *pCtx;
774	g_fIemFFs = pVCpu->fLocalForcedActions;
775	rc = rcIem;
776	# endif
777
778	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
779	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
780	# endif
781
782	# else
783	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
784	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
785	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
786	rc = VERR_EM_INTERPRETER;
787	# endif
788	if (rc != VINF_SUCCESS)
789	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
790
791	return rc;
792	#else
793	RTGCPTR pbCode;
794	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
795	if (RT_SUCCESS(rc))
796	{
797	uint32_t cbOp;
798	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
799	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
800	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
801	if (RT_SUCCESS(rc))
802	{
803	Assert(cbOp == pDis->cbInstr);
804	uint32_t cbIgnored;
805	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
806	if (RT_SUCCESS(rc))
807	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
808
809	return rc;
810	}
811	}
812	return VERR_EM_INTERPRETER;
813	#endif
814	}
815
816
817	/**
818	* Interprets the current instruction.
819	*
820	* @returns VBox status code.
821	* @retval VINF_* Scheduling instructions.
822	* @retval VERR_EM_INTERPRETER Something we can't cope with.
823	* @retval VERR_* Fatal errors.
824	*
825	* @param pVM Pointer to the VM.
826	* @param pVCpu Pointer to the VMCPU.
827	* @param pRegFrame The register frame.
828	* Updates the EIP if an instruction was executed successfully.
829	* @param pvFault The fault address (CR2).
830	* @param pcbWritten Size of the write (if applicable).
831	*
832	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
833	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
834	* to worry about e.g. invalid modrm combinations (!)
835	*/
836	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
837	{
838	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
839	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
840	#ifdef VBOX_WITH_IEM
841	NOREF(pvFault);
842
843	# ifdef VBOX_COMPARE_IEM_AND_EM
844	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
845	g_IncomingCtx = *pCtx;
846	g_fIncomingFFs = pVCpu->fLocalForcedActions;
847	g_cbEmWrote = g_cbIemWrote = 0;
848
849	# ifdef VBOX_COMPARE_IEM_FIRST
850	/* IEM */
851	uint32_t cbIemWritten = 0;
852	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
853	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
854	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
855	rcIem = VERR_EM_INTERPRETER;
856	g_IemCtx = *pCtx;
857	g_fIemFFs = pVCpu->fLocalForcedActions;
858	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
859	*pCtx = g_IncomingCtx;
860	# endif
861
862	/* EM */
863	uint32_t cbEmWritten = 0;
864	RTGCPTR pbCode;
865	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
866	if (RT_SUCCESS(rcEm))
867	{
868	uint32_t cbOp;
869	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
870	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
871	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
872	if (RT_SUCCESS(rcEm))
873	{
874	Assert(cbOp == pDis->cbInstr);
875	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
876	if (RT_SUCCESS(rcEm))
877	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
878
879	}
880	else
881	rcEm = VERR_EM_INTERPRETER;
882	}
883	else
884	rcEm = VERR_EM_INTERPRETER;
885	# ifdef VBOX_SAME_AS_EM
886	if (rcEm == VERR_EM_INTERPRETER)
887	{
888	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
889	return rcEm;
890	}
891	# endif
892	g_EmCtx = *pCtx;
893	g_fEmFFs = pVCpu->fLocalForcedActions;
894	*pcbWritten = cbEmWritten;
895	VBOXSTRICTRC rc = rcEm;
896
897	# ifdef VBOX_COMPARE_IEM_LAST
898	/* IEM */
899	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
900	*pCtx = g_IncomingCtx;
901	uint32_t cbIemWritten = 0;
902	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
903	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
904	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
905	rcIem = VERR_EM_INTERPRETER;
906	g_IemCtx = *pCtx;
907	g_fIemFFs = pVCpu->fLocalForcedActions;
908	*pcbWritten = cbIemWritten;
909	rc = rcIem;
910	# endif
911
912	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
913	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
914	# endif
915
916	# else
917	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
918	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
919	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
920	rc = VERR_EM_INTERPRETER;
921	# endif
922	if (rc != VINF_SUCCESS)
923	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
924
925	return rc;
926	#else
927	RTGCPTR pbCode;
928	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
929	if (RT_SUCCESS(rc))
930	{
931	uint32_t cbOp;
932	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
933	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
934	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
935	if (RT_SUCCESS(rc))
936	{
937	Assert(cbOp == pDis->cbInstr);
938	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
939	if (RT_SUCCESS(rc))
940	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
941
942	return rc;
943	}
944	}
945	return VERR_EM_INTERPRETER;
946	#endif
947	}
948
949
950	/**
951	* Interprets the current instruction using the supplied DISCPUSTATE structure.
952	*
953	* IP/EIP/RIP IS updated!
954	*
955	* @returns VBox strict status code.
956	* @retval VINF_* Scheduling instructions. When these are returned, it
957	* starts to get a bit tricky to know whether code was
958	* executed or not... We'll address this when it becomes a problem.
959	* @retval VERR_EM_INTERPRETER Something we can't cope with.
960	* @retval VERR_* Fatal errors.
961	*
962	* @param pVM Pointer to the VM.
963	* @param pVCpu Pointer to the VMCPU.
964	* @param pDis The disassembler cpu state for the instruction to be
965	* interpreted.
966	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
967	* @param pvFault The fault address (CR2).
968	* @param pcbSize Size of the write (if applicable).
969	* @param enmCodeType Code type (user/supervisor)
970	*
971	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
972	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
973	* to worry about e.g. invalid modrm combinations (!)
974	*
975	* @todo At this time we do NOT check if the instruction overwrites vital information.
976	* Make sure this can't happen!! (will add some assertions/checks later)
977	*/
978	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
979	RTGCPTR pvFault, EMCODETYPE enmCodeType)
980	{
981	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
982	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
983	#ifdef VBOX_WITH_IEM
984	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
985
986	# ifdef VBOX_COMPARE_IEM_AND_EM
987	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
988	g_IncomingCtx = *pCtx;
989	g_fIncomingFFs = pVCpu->fLocalForcedActions;
990	g_cbEmWrote = g_cbIemWrote = 0;
991
992	# ifdef VBOX_COMPARE_IEM_FIRST
993	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
994	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
995	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
996	rcIem = VERR_EM_INTERPRETER;
997	g_IemCtx = *pCtx;
998	g_fIemFFs = pVCpu->fLocalForcedActions;
999	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1000	*pCtx = g_IncomingCtx;
1001	# endif
1002
1003	/* EM */
1004	uint32_t cbIgnored;
1005	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1006	if (RT_SUCCESS(rcEm))
1007	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1008	# ifdef VBOX_SAME_AS_EM
1009	if (rcEm == VERR_EM_INTERPRETER)
1010	{
1011	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
1012	return rcEm;
1013	}
1014	# endif
1015	g_EmCtx = *pCtx;
1016	g_fEmFFs = pVCpu->fLocalForcedActions;
1017	VBOXSTRICTRC rc = rcEm;
1018
1019	# ifdef VBOX_COMPARE_IEM_LAST
1020	/* IEM */
1021	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1022	*pCtx = g_IncomingCtx;
1023	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1024	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1025	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1026	rcIem = VERR_EM_INTERPRETER;
1027	g_IemCtx = *pCtx;
1028	g_fIemFFs = pVCpu->fLocalForcedActions;
1029	rc = rcIem;
1030	# endif
1031
1032	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1033	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1034	# endif
1035
1036	# else
1037	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1038	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1039	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1040	rc = VERR_EM_INTERPRETER;
1041	# endif
1042
1043	if (rc != VINF_SUCCESS)
1044	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1045
1046	return rc;
1047	#else
1048	uint32_t cbIgnored;
1049	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1050	if (RT_SUCCESS(rc))
1051	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1052	return rc;
1053	#endif
1054	}
1055
1056	#ifdef IN_RC
1057
1058	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1059	{
1060	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1061	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1062	return rc;
1063	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1064	}
1065
1066
1067	/**
1068	* Interpret IRET (currently only to V86 code) - PATM only.
1069	*
1070	* @returns VBox status code.
1071	* @param pVM Pointer to the VM.
1072	* @param pVCpu Pointer to the VMCPU.
1073	* @param pRegFrame The register frame.
1074	*
1075	*/
1076	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1077	{
1078	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1079	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1080	int rc;
1081
1082	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1083	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1084	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1085	* this function. Fear that it may guru on us, thus not converted to
1086	* IEM. */
1087
1088	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1089	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1090	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1091	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1092	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1093
1094	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1095	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1096	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1097	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1098	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1099	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1100	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1101
1102	pRegFrame->eip = eip & 0xffff;
1103	pRegFrame->cs.Sel = cs;
1104
1105	/* Mask away all reserved bits */
1106	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1107	eflags &= uMask;
1108
1109	CPUMRawSetEFlags(pVCpu, eflags);
1110	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1111
1112	pRegFrame->esp = esp;
1113	pRegFrame->ss.Sel = ss;
1114	pRegFrame->ds.Sel = ds;
1115	pRegFrame->es.Sel = es;
1116	pRegFrame->fs.Sel = fs;
1117	pRegFrame->gs.Sel = gs;
1118
1119	return VINF_SUCCESS;
1120	}
1121
1122	/**
1123	* IRET Emulation.
1124	*/
1125	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1126	{
1127	#ifdef VBOX_WITH_RAW_RING1
1128	NOREF(pvFault); NOREF(pcbSize);
1129	if (EMIsRawRing1Enabled(pVM))
1130	{
1131	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1132	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1133	int rc;
1134	uint32_t cpl, rpl;
1135
1136	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1137	/* @todo: we don't verify all the edge cases that generate #GP faults */
1138
1139	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1140	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1141	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1142	* this function. Fear that it may guru on us, thus not converted to
1143	* IEM. */
1144
1145	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1146	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1147	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1148	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1149	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1150
1151	/* Deal with V86 above. */
1152	if (eflags & X86_EFL_VM)
1153	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1154
1155	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1156	rpl = cs & X86_SEL_RPL;
1157
1158	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1159	if (rpl != cpl)
1160	{
1161	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1162	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1163	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1164	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1165	Log(("emInterpretIret: SS:ESP=%04X:08X\n", ss, esp));
1166	pRegFrame->ss.Sel = ss;
1167	pRegFrame->esp = esp;
1168	}
1169	pRegFrame->cs.Sel = cs;
1170	pRegFrame->eip = eip;
1171
1172	/* Adjust CS & SS as required. */
1173	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1174
1175	/* Mask away all reserved bits */
1176	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1177	eflags &= uMask;
1178
1179	CPUMRawSetEFlags(pVCpu, eflags);
1180	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1181	return VINF_SUCCESS;
1182	}
1183	#else
1184	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1185	#endif
1186	return VERR_EM_INTERPRETER;
1187	}
1188
1189	#endif /* IN_RC */
1190
1191
1192
1193	/*
1194	*
1195	* Old interpreter primitives used by HM, move/eliminate later.
1196	* Old interpreter primitives used by HM, move/eliminate later.
1197	* Old interpreter primitives used by HM, move/eliminate later.
1198	* Old interpreter primitives used by HM, move/eliminate later.
1199	* Old interpreter primitives used by HM, move/eliminate later.
1200	*
1201	*/
1202
1203
1204	/**
1205	* Interpret CPUID given the parameters in the CPU context.
1206	*
1207	* @returns VBox status code.
1208	* @param pVM Pointer to the VM.
1209	* @param pVCpu Pointer to the VMCPU.
1210	* @param pRegFrame The register frame.
1211	*
1212	*/
1213	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1214	{
1215	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1216	uint32_t iLeaf = pRegFrame->eax;
1217	uint32_t iSubLeaf = pRegFrame->ecx;
1218	NOREF(pVM);
1219
1220	/* cpuid clears the high dwords of the affected 64 bits registers. */
1221	pRegFrame->rax = 0;
1222	pRegFrame->rbx = 0;
1223	pRegFrame->rcx = 0;
1224	pRegFrame->rdx = 0;
1225
1226	/* Note: operates the same in 64 and non-64 bits mode. */
1227	CPUMGetGuestCpuId(pVCpu, iLeaf, iSubLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1228	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1229	return VINF_SUCCESS;
1230	}
1231
1232
1233	/**
1234	* Interpret RDTSC.
1235	*
1236	* @returns VBox status code.
1237	* @param pVM Pointer to the VM.
1238	* @param pVCpu Pointer to the VMCPU.
1239	* @param pRegFrame The register frame.
1240	*
1241	*/
1242	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1243	{
1244	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1245	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1246
1247	if (uCR4 & X86_CR4_TSD)
1248	return VERR_EM_INTERPRETER; /* genuine #GP */
1249
1250	uint64_t uTicks = TMCpuTickGet(pVCpu);
1251
1252	/* Same behaviour in 32 & 64 bits mode */
1253	pRegFrame->rax = (uint32_t)uTicks;
1254	pRegFrame->rdx = (uTicks >> 32ULL);
1255	#ifdef VBOX_COMPARE_IEM_AND_EM
1256	g_fIgnoreRaxRdx = true;
1257	#endif
1258
1259	NOREF(pVM);
1260	return VINF_SUCCESS;
1261	}
1262
1263	/**
1264	* Interpret RDTSCP.
1265	*
1266	* @returns VBox status code.
1267	* @param pVM Pointer to the VM.
1268	* @param pVCpu Pointer to the VMCPU.
1269	* @param pCtx The CPU context.
1270	*
1271	*/
1272	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1273	{
1274	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1275	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1276
1277	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1278	{
1279	AssertFailed();
1280	return VERR_EM_INTERPRETER; /* genuine #UD */
1281	}
1282
1283	if (uCR4 & X86_CR4_TSD)
1284	return VERR_EM_INTERPRETER; /* genuine #GP */
1285
1286	uint64_t uTicks = TMCpuTickGet(pVCpu);
1287
1288	/* Same behaviour in 32 & 64 bits mode */
1289	pCtx->rax = (uint32_t)uTicks;
1290	pCtx->rdx = (uTicks >> 32ULL);
1291	#ifdef VBOX_COMPARE_IEM_AND_EM
1292	g_fIgnoreRaxRdx = true;
1293	#endif
1294	/* Low dword of the TSC_AUX msr only. */
1295	VBOXSTRICTRC rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx); Assert(rc2 == VINF_SUCCESS);
1296	pCtx->rcx &= UINT32_C(0xffffffff);
1297
1298	return VINF_SUCCESS;
1299	}
1300
1301	/**
1302	* Interpret RDPMC.
1303	*
1304	* @returns VBox status code.
1305	* @param pVM Pointer to the VM.
1306	* @param pVCpu Pointer to the VMCPU.
1307	* @param pRegFrame The register frame.
1308	*
1309	*/
1310	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1311	{
1312	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1313	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1314
1315	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1316	if ( !(uCR4 & X86_CR4_PCE)
1317	&& CPUMGetGuestCPL(pVCpu) != 0)
1318	{
1319	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1320	return VERR_EM_INTERPRETER; /* genuine #GP */
1321	}
1322
1323	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1324	pRegFrame->rax = 0;
1325	pRegFrame->rdx = 0;
1326	/** @todo We should trigger a #GP here if the CPU doesn't support the index in ecx
1327	* but see @bugref{3472}! */
1328
1329	NOREF(pVM);
1330	return VINF_SUCCESS;
1331	}
1332
1333
1334	/**
1335	* MWAIT Emulation.
1336	*/
1337	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1338	{
1339	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1340	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1341	NOREF(pVM);
1342
1343	/* Get the current privilege level. */
1344	cpl = CPUMGetGuestCPL(pVCpu);
1345	if (cpl != 0)
1346	return VERR_EM_INTERPRETER; /* supervisor only */
1347
1348	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1349	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1350	return VERR_EM_INTERPRETER; /* not supported */
1351
1352	/*
1353	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1354	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1355	*/
1356	CPUMGetGuestCpuId(pVCpu, 5, 0, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1357	if (pRegFrame->ecx > 1)
1358	{
1359	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1360	return VERR_EM_INTERPRETER; /* illegal value. */
1361	}
1362
1363	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1364	{
1365	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1366	return VERR_EM_INTERPRETER; /* illegal value. */
1367	}
1368
1369	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1370	}
1371
1372
1373	/**
1374	* MONITOR Emulation.
1375	*/
1376	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1377	{
1378	uint32_t u32Dummy, u32ExtFeatures, cpl;
1379	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1380	NOREF(pVM);
1381
1382	if (pRegFrame->ecx != 0)
1383	{
1384	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1385	return VERR_EM_INTERPRETER; /* illegal value. */
1386	}
1387
1388	/* Get the current privilege level. */
1389	cpl = CPUMGetGuestCPL(pVCpu);
1390	if (cpl != 0)
1391	return VERR_EM_INTERPRETER; /* supervisor only */
1392
1393	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1394	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1395	return VERR_EM_INTERPRETER; /* not supported */
1396
1397	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1398	return VINF_SUCCESS;
1399	}
1400
1401
1402	/* VT-x only: */
1403
1404	/**
1405	* Interpret INVLPG.
1406	*
1407	* @returns VBox status code.
1408	* @param pVM Pointer to the VM.
1409	* @param pVCpu Pointer to the VMCPU.
1410	* @param pRegFrame The register frame.
1411	* @param pAddrGC Operand address.
1412	*
1413	*/
1414	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1415	{
1416	/** @todo is addr always a flat linear address or ds based
1417	* (in absence of segment override prefixes)????
1418	*/
1419	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1420	NOREF(pVM); NOREF(pRegFrame);
1421	#ifdef IN_RC
1422	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1423	#endif
1424	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1425	if ( rc == VINF_SUCCESS
1426	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1427	return VINF_SUCCESS;
1428	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1429	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1430	VERR_EM_INTERPRETER);
1431	return rc;
1432	}
1433
1434
1435	/**
1436	* Update CRx.
1437	*
1438	* @returns VBox status code.
1439	* @param pVM Pointer to the VM.
1440	* @param pVCpu Pointer to the VMCPU.
1441	* @param pRegFrame The register frame.
1442	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1443	* @param val New CRx value
1444	*
1445	*/
1446	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
1447	{
1448	uint64_t oldval;
1449	uint64_t msrEFER;
1450	uint32_t fValid;
1451	int rc, rc2;
1452	NOREF(pVM);
1453
1454	/** @todo Clean up this mess. */
1455	LogFlow(("emInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
1456	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1457	switch (DestRegCrx)
1458	{
1459	case DISCREG_CR0:
1460	oldval = CPUMGetGuestCR0(pVCpu);
1461	#ifdef IN_RC
1462	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1463	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1464	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1465	return VERR_EM_INTERPRETER;
1466	#endif
1467	rc = VINF_SUCCESS;
1468	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1469	CPUMSetGuestCR0(pVCpu, val);
1470	#else
1471	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
1472	#endif
1473	val = CPUMGetGuestCR0(pVCpu);
1474	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1475	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1476	{
1477	/* global flush */
1478	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1479	AssertRCReturn(rc, rc);
1480	}
1481
1482	/* Deal with long mode enabling/disabling. */
1483	msrEFER = CPUMGetGuestEFER(pVCpu);
1484	if (msrEFER & MSR_K6_EFER_LME)
1485	{
1486	if ( !(oldval & X86_CR0_PG)
1487	&& (val & X86_CR0_PG))
1488	{
1489	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1490	if (pRegFrame->cs.Attr.n.u1Long)
1491	{
1492	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1493	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1494	}
1495
1496	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1497	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
1498	{
1499	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1500	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1501	}
1502	msrEFER \|= MSR_K6_EFER_LMA;
1503	}
1504	else
1505	if ( (oldval & X86_CR0_PG)
1506	&& !(val & X86_CR0_PG))
1507	{
1508	msrEFER &= ~MSR_K6_EFER_LMA;
1509	/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1510	}
1511	CPUMSetGuestEFER(pVCpu, msrEFER);
1512	}
1513	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1514	return rc2 == VINF_SUCCESS ? rc : rc2;
1515
1516	case DISCREG_CR2:
1517	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
1518	return VINF_SUCCESS;
1519
1520	case DISCREG_CR3:
1521	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1522	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
1523	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
1524	{
1525	/* flush */
1526	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
1527	AssertRC(rc);
1528	}
1529	return rc;
1530
1531	case DISCREG_CR4:
1532	oldval = CPUMGetGuestCR4(pVCpu);
1533	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
1534	val = CPUMGetGuestCR4(pVCpu);
1535
1536	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1537	msrEFER = CPUMGetGuestEFER(pVCpu);
1538	if ( (msrEFER & MSR_K6_EFER_LMA)
1539	&& (oldval & X86_CR4_PAE)
1540	&& !(val & X86_CR4_PAE))
1541	{
1542	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1543	}
1544
1545	/* From IEM iemCImpl_load_CrX. */
1546	/** @todo Check guest CPUID bits for determining corresponding valid bits. */
1547	fValid = X86_CR4_VME \| X86_CR4_PVI
1548	\| X86_CR4_TSD \| X86_CR4_DE
1549	\| X86_CR4_PSE \| X86_CR4_PAE
1550	\| X86_CR4_MCE \| X86_CR4_PGE
1551	\| X86_CR4_PCE \| X86_CR4_OSFXSR
1552	\| X86_CR4_OSXMMEEXCPT;
1553	//if (xxx)
1554	// fValid \|= X86_CR4_VMXE;
1555	//if (xxx)
1556	// fValid \|= X86_CR4_OSXSAVE;
1557	if (val & ~(uint64_t)fValid)
1558	{
1559	Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", val, val & ~(uint64_t)fValid));
1560	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1561	}
1562
1563	rc = VINF_SUCCESS;
1564	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1565	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1566	{
1567	/* global flush */
1568	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1569	AssertRCReturn(rc, rc);
1570	}
1571
1572	/* Feeling extremely lazy. */
1573	# ifdef IN_RC
1574	if ( (oldval & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1575	!= (val & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1576	{
1577	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1578	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
1579	}
1580	# endif
1581	# ifdef VBOX_WITH_RAW_MODE
1582	if (((val ^ oldval) & X86_CR4_VME) && !HMIsEnabled(pVM))
1583	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1584	# endif
1585
1586	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1587	return rc2 == VINF_SUCCESS ? rc : rc2;
1588
1589	case DISCREG_CR8:
1590	return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1591
1592	default:
1593	AssertFailed();
1594	case DISCREG_CR1: /* illegal op */
1595	break;
1596	}
1597	return VERR_EM_INTERPRETER;
1598	}
1599
1600
1601	/**
1602	* Interpret CRx write.
1603	*
1604	* @returns VBox status code.
1605	* @param pVM Pointer to the VM.
1606	* @param pVCpu Pointer to the VMCPU.
1607	* @param pRegFrame The register frame.
1608	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1609	* @param SrcRegGen General purpose register index (USE_REG_E**))
1610	*
1611	*/
1612	static int emInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1613	{
1614	uint64_t val;
1615	int rc;
1616	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1617
1618	if (CPUMIsGuestIn64BitCode(pVCpu))
1619	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1620	else
1621	{
1622	uint32_t val32;
1623	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1624	val = val32;
1625	}
1626
1627	if (RT_SUCCESS(rc))
1628	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
1629
1630	return VERR_EM_INTERPRETER;
1631	}
1632
1633
1634	#ifdef LOG_ENABLED
1635	static const char *emMSRtoString(uint32_t uMsr)
1636	{
1637	switch (uMsr)
1638	{
1639	case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
1640	case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
1641	case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
1642	case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
1643	case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
1644	case MSR_K6_EFER: return "MSR_K6_EFER";
1645	case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
1646	case MSR_K6_STAR: return "MSR_K6_STAR";
1647	case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
1648	case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
1649	case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
1650	case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
1651	case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
1652	case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
1653	case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
1654	case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
1655	case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
1656	case MSR_IA32_TSC: return "MSR_IA32_TSC";
1657	case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
1658	case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
1659	case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
1660	case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
1661	case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
1662	case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
1663	case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
1664	case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
1665	case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
1666	case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
1667	case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
1668	case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
1669	case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
1670	case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
1671	case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
1672	case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
1673	case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
1674	case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
1675	case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
1676	case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
1677	case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
1678	case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
1679	case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
1680	case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
1681	case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
1682	}
1683	return "Unknown MSR";
1684	}
1685	#endif /* LOG_ENABLED */
1686
1687
1688	/**
1689	* Interpret RDMSR
1690	*
1691	* @returns VBox status code.
1692	* @param pVM Pointer to the VM.
1693	* @param pVCpu Pointer to the VMCPU.
1694	* @param pRegFrame The register frame.
1695	*/
1696	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1697	{
1698	NOREF(pVM);
1699
1700	/* Get the current privilege level. */
1701	if (CPUMGetGuestCPL(pVCpu) != 0)
1702	{
1703	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
1704	return VERR_EM_INTERPRETER; /* supervisor only */
1705	}
1706
1707	uint64_t uValue;
1708	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
1709	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1710	{
1711	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1712	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_READ);
1713	return VERR_EM_INTERPRETER;
1714	}
1715	pRegFrame->rax = (uint32_t) uValue;
1716	pRegFrame->rdx = (uint32_t)(uValue >> 32);
1717	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
1718	return VINF_SUCCESS;
1719	}
1720
1721
1722	/**
1723	* Interpret WRMSR
1724	*
1725	* @returns VBox status code.
1726	* @param pVM Pointer to the VM.
1727	* @param pVCpu Pointer to the VMCPU.
1728	* @param pRegFrame The register frame.
1729	*/
1730	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1731	{
1732	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1733
1734	/* Check the current privilege level, this instruction is supervisor only. */
1735	if (CPUMGetGuestCPL(pVCpu) != 0)
1736	{
1737	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
1738	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
1739	}
1740
1741	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
1742	if (rcStrict != VINF_SUCCESS)
1743	{
1744	Log4(("EM: Refuse WRMSR: CPUMSetGuestMsr returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1745	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_WRITE);
1746	return VERR_EM_INTERPRETER;
1747	}
1748	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
1749	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
1750	NOREF(pVM);
1751	return VINF_SUCCESS;
1752	}
1753
1754
1755	/**
1756	* Interpret CRx read.
1757	*
1758	* @returns VBox status code.
1759	* @param pVM Pointer to the VM.
1760	* @param pVCpu Pointer to the VMCPU.
1761	* @param pRegFrame The register frame.
1762	* @param DestRegGen General purpose register index (USE_REG_E**))
1763	* @param SrcRegCRx CRx register index (DISUSE_REG_CR*)
1764	*
1765	*/
1766	static int emInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1767	{
1768	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1769	uint64_t val64;
1770	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1771	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1772	NOREF(pVM);
1773
1774	if (CPUMIsGuestIn64BitCode(pVCpu))
1775	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1776	else
1777	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1778
1779	if (RT_SUCCESS(rc))
1780	{
1781	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1782	return VINF_SUCCESS;
1783	}
1784	return VERR_EM_INTERPRETER;
1785	}
1786
1787
1788	/**
1789	* Interpret DRx write.
1790	*
1791	* @returns VBox status code.
1792	* @param pVM Pointer to the VM.
1793	* @param pVCpu Pointer to the VMCPU.
1794	* @param pRegFrame The register frame.
1795	* @param DestRegDRx DRx register index (USE_REG_DR*)
1796	* @param SrcRegGen General purpose register index (USE_REG_E**))
1797	*
1798	*/
1799	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1800	{
1801	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1802	uint64_t uNewDrX;
1803	int rc;
1804	NOREF(pVM);
1805
1806	if (CPUMIsGuestIn64BitCode(pVCpu))
1807	rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1808	else
1809	{
1810	uint32_t val32;
1811	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1812	uNewDrX = val32;
1813	}
1814
1815	if (RT_SUCCESS(rc))
1816	{
1817	if (DestRegDrx == 6)
1818	{
1819	uNewDrX \|= X86_DR6_RA1_MASK;
1820	uNewDrX &= ~X86_DR6_RAZ_MASK;
1821	}
1822	else if (DestRegDrx == 7)
1823	{
1824	uNewDrX \|= X86_DR7_RA1_MASK;
1825	uNewDrX &= ~X86_DR7_RAZ_MASK;
1826	}
1827
1828	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1829	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1830	if (RT_SUCCESS(rc))
1831	return rc;
1832	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1833	}
1834	return VERR_EM_INTERPRETER;
1835	}
1836
1837
1838	/**
1839	* Interpret DRx read.
1840	*
1841	* @returns VBox status code.
1842	* @param pVM Pointer to the VM.
1843	* @param pVCpu Pointer to the VMCPU.
1844	* @param pRegFrame The register frame.
1845	* @param DestRegGen General purpose register index (USE_REG_E**))
1846	* @param SrcRegDRx DRx register index (USE_REG_DR*)
1847	*
1848	*/
1849	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1850	{
1851	uint64_t val64;
1852	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1853	NOREF(pVM);
1854
1855	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1856	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1857	if (CPUMIsGuestIn64BitCode(pVCpu))
1858	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1859	else
1860	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1861
1862	if (RT_SUCCESS(rc))
1863	return VINF_SUCCESS;
1864
1865	return VERR_EM_INTERPRETER;
1866	}
1867
1868
1869	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1870
1871
1872
1873
1874
1875
1876	/*
1877	*
1878	* The old interpreter.
1879	* The old interpreter.
1880	* The old interpreter.
1881	* The old interpreter.
1882	* The old interpreter.
1883	*
1884	*/
1885
1886	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1887	{
1888	#ifdef IN_RC
1889	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1890	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1891	return rc;
1892	/*
1893	* The page pool cache may end up here in some cases because it
1894	* flushed one of the shadow mappings used by the trapping
1895	* instruction and it either flushed the TLB or the CPU reused it.
1896	*/
1897	#else
1898	NOREF(pVM);
1899	#endif
1900	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1901	}
1902
1903
1904	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1905	{
1906	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1907	pages or write monitored pages. */
1908	NOREF(pVM);
1909	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1910	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1911	#else
1912	int rc = VINF_SUCCESS;
1913	#endif
1914	#ifdef VBOX_COMPARE_IEM_AND_EM
1915	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1916	g_cbEmWrote = cb;
1917	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1918	#endif
1919	return rc;
1920	}
1921
1922
1923	/** Convert sel:addr to a flat GC address. */
1924	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1925	{
1926	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1927	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1928	}
1929
1930
1931	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1932	/**
1933	* Get the mnemonic for the disassembled instruction.
1934	*
1935	* GC/R0 doesn't include the strings in the DIS tables because
1936	* of limited space.
1937	*/
1938	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1939	{
1940	switch (pDis->pCurInstr->uOpcode)
1941	{
1942	case OP_XCHG: return "Xchg";
1943	case OP_DEC: return "Dec";
1944	case OP_INC: return "Inc";
1945	case OP_POP: return "Pop";
1946	case OP_OR: return "Or";
1947	case OP_AND: return "And";
1948	case OP_MOV: return "Mov";
1949	case OP_INVLPG: return "InvlPg";
1950	case OP_CPUID: return "CpuId";
1951	case OP_MOV_CR: return "MovCRx";
1952	case OP_MOV_DR: return "MovDRx";
1953	case OP_LLDT: return "LLdt";
1954	case OP_LGDT: return "LGdt";
1955	case OP_LIDT: return "LIdt";
1956	case OP_CLTS: return "Clts";
1957	case OP_MONITOR: return "Monitor";
1958	case OP_MWAIT: return "MWait";
1959	case OP_RDMSR: return "Rdmsr";
1960	case OP_WRMSR: return "Wrmsr";
1961	case OP_ADD: return "Add";
1962	case OP_ADC: return "Adc";
1963	case OP_SUB: return "Sub";
1964	case OP_SBB: return "Sbb";
1965	case OP_RDTSC: return "Rdtsc";
1966	case OP_STI: return "Sti";
1967	case OP_CLI: return "Cli";
1968	case OP_XADD: return "XAdd";
1969	case OP_HLT: return "Hlt";
1970	case OP_IRET: return "Iret";
1971	case OP_MOVNTPS: return "MovNTPS";
1972	case OP_STOSWD: return "StosWD";
1973	case OP_WBINVD: return "WbInvd";
1974	case OP_XOR: return "Xor";
1975	case OP_BTR: return "Btr";
1976	case OP_BTS: return "Bts";
1977	case OP_BTC: return "Btc";
1978	case OP_LMSW: return "Lmsw";
1979	case OP_SMSW: return "Smsw";
1980	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
1981	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
1982
1983	default:
1984	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
1985	return "???";
1986	}
1987	}
1988	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
1989
1990
1991	/**
1992	* XCHG instruction emulation.
1993	*/
1994	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1995	{
1996	DISQPVPARAMVAL param1, param2;
1997	NOREF(pvFault);
1998
1999	/* Source to make DISQueryParamVal read the register value - ugly hack */
2000	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2001	if(RT_FAILURE(rc))
2002	return VERR_EM_INTERPRETER;
2003
2004	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2005	if(RT_FAILURE(rc))
2006	return VERR_EM_INTERPRETER;
2007
2008	#ifdef IN_RC
2009	if (TRPMHasTrap(pVCpu))
2010	{
2011	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2012	{
2013	#endif
2014	RTGCPTR pParam1 = 0, pParam2 = 0;
2015	uint64_t valpar1, valpar2;
2016
2017	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2018	switch(param1.type)
2019	{
2020	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2021	valpar1 = param1.val.val64;
2022	break;
2023
2024	case DISQPV_TYPE_ADDRESS:
2025	pParam1 = (RTGCPTR)param1.val.val64;
2026	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2027	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2028	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2029	if (RT_FAILURE(rc))
2030	{
2031	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2032	return VERR_EM_INTERPRETER;
2033	}
2034	break;
2035
2036	default:
2037	AssertFailed();
2038	return VERR_EM_INTERPRETER;
2039	}
2040
2041	switch(param2.type)
2042	{
2043	case DISQPV_TYPE_ADDRESS:
2044	pParam2 = (RTGCPTR)param2.val.val64;
2045	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
2046	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
2047	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
2048	if (RT_FAILURE(rc))
2049	{
2050	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2051	}
2052	break;
2053
2054	case DISQPV_TYPE_IMMEDIATE:
2055	valpar2 = param2.val.val64;
2056	break;
2057
2058	default:
2059	AssertFailed();
2060	return VERR_EM_INTERPRETER;
2061	}
2062
2063	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
2064	if (pParam1 == 0)
2065	{
2066	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2067	switch(param1.size)
2068	{
2069	case 1: //special case for AH etc
2070	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
2071	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
2072	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
2073	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
2074	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2075	}
2076	if (RT_FAILURE(rc))
2077	return VERR_EM_INTERPRETER;
2078	}
2079	else
2080	{
2081	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
2082	if (RT_FAILURE(rc))
2083	{
2084	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2085	return VERR_EM_INTERPRETER;
2086	}
2087	}
2088
2089	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
2090	if (pParam2 == 0)
2091	{
2092	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2093	switch(param2.size)
2094	{
2095	case 1: //special case for AH etc
2096	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
2097	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
2098	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
2099	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
2100	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2101	}
2102	if (RT_FAILURE(rc))
2103	return VERR_EM_INTERPRETER;
2104	}
2105	else
2106	{
2107	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
2108	if (RT_FAILURE(rc))
2109	{
2110	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2111	return VERR_EM_INTERPRETER;
2112	}
2113	}
2114
2115	*pcbSize = param2.size;
2116	return VINF_SUCCESS;
2117	#ifdef IN_RC
2118	}
2119	}
2120	return VERR_EM_INTERPRETER;
2121	#endif
2122	}
2123
2124
2125	/**
2126	* INC and DEC emulation.
2127	*/
2128	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2129	PFNEMULATEPARAM2 pfnEmulate)
2130	{
2131	DISQPVPARAMVAL param1;
2132	NOREF(pvFault);
2133
2134	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2135	if(RT_FAILURE(rc))
2136	return VERR_EM_INTERPRETER;
2137
2138	#ifdef IN_RC
2139	if (TRPMHasTrap(pVCpu))
2140	{
2141	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2142	{
2143	#endif
2144	RTGCPTR pParam1 = 0;
2145	uint64_t valpar1;
2146
2147	if (param1.type == DISQPV_TYPE_ADDRESS)
2148	{
2149	pParam1 = (RTGCPTR)param1.val.val64;
2150	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2151	#ifdef IN_RC
2152	/* Safety check (in theory it could cross a page boundary and fault there though) */
2153	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2154	#endif
2155	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2156	if (RT_FAILURE(rc))
2157	{
2158	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2159	return VERR_EM_INTERPRETER;
2160	}
2161	}
2162	else
2163	{
2164	AssertFailed();
2165	return VERR_EM_INTERPRETER;
2166	}
2167
2168	uint32_t eflags;
2169
2170	eflags = pfnEmulate(&valpar1, param1.size);
2171
2172	/* Write result back */
2173	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2174	if (RT_FAILURE(rc))
2175	{
2176	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2177	return VERR_EM_INTERPRETER;
2178	}
2179
2180	/* Update guest's eflags and finish. */
2181	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2182	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2183
2184	/* All done! */
2185	*pcbSize = param1.size;
2186	return VINF_SUCCESS;
2187	#ifdef IN_RC
2188	}
2189	}
2190	return VERR_EM_INTERPRETER;
2191	#endif
2192	}
2193
2194
2195	/**
2196	* POP Emulation.
2197	*/
2198	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2199	{
2200	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2201	DISQPVPARAMVAL param1;
2202	NOREF(pvFault);
2203
2204	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2205	if(RT_FAILURE(rc))
2206	return VERR_EM_INTERPRETER;
2207
2208	#ifdef IN_RC
2209	if (TRPMHasTrap(pVCpu))
2210	{
2211	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2212	{
2213	#endif
2214	RTGCPTR pParam1 = 0;
2215	uint32_t valpar1;
2216	RTGCPTR pStackVal;
2217
2218	/* Read stack value first */
2219	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2220	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2221
2222	/* Convert address; don't bother checking limits etc, as we only read here */
2223	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2224	if (pStackVal == 0)
2225	return VERR_EM_INTERPRETER;
2226
2227	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2228	if (RT_FAILURE(rc))
2229	{
2230	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2231	return VERR_EM_INTERPRETER;
2232	}
2233
2234	if (param1.type == DISQPV_TYPE_ADDRESS)
2235	{
2236	pParam1 = (RTGCPTR)param1.val.val64;
2237
2238	/* pop [esp+xx] uses esp after the actual pop! */
2239	AssertCompile(DISGREG_ESP == DISGREG_SP);
2240	if ( (pDis->Param1.fUse & DISUSE_BASE)
2241	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2242	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2243	)
2244	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2245
2246	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2247	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2248	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2249	if (RT_FAILURE(rc))
2250	{
2251	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2252	return VERR_EM_INTERPRETER;
2253	}
2254
2255	/* Update ESP as the last step */
2256	pRegFrame->esp += param1.size;
2257	}
2258	else
2259	{
2260	#ifndef DEBUG_bird // annoying assertion.
2261	AssertFailed();
2262	#endif
2263	return VERR_EM_INTERPRETER;
2264	}
2265
2266	/* All done! */
2267	*pcbSize = param1.size;
2268	return VINF_SUCCESS;
2269	#ifdef IN_RC
2270	}
2271	}
2272	return VERR_EM_INTERPRETER;
2273	#endif
2274	}
2275
2276
2277	/**
2278	* XOR/OR/AND Emulation.
2279	*/
2280	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2281	PFNEMULATEPARAM3 pfnEmulate)
2282	{
2283	DISQPVPARAMVAL param1, param2;
2284	NOREF(pvFault);
2285
2286	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2287	if(RT_FAILURE(rc))
2288	return VERR_EM_INTERPRETER;
2289
2290	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2291	if(RT_FAILURE(rc))
2292	return VERR_EM_INTERPRETER;
2293
2294	#ifdef IN_RC
2295	if (TRPMHasTrap(pVCpu))
2296	{
2297	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2298	{
2299	#endif
2300	RTGCPTR pParam1;
2301	uint64_t valpar1, valpar2;
2302
2303	if (pDis->Param1.cb != pDis->Param2.cb)
2304	{
2305	if (pDis->Param1.cb < pDis->Param2.cb)
2306	{
2307	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2308	return VERR_EM_INTERPRETER;
2309	}
2310	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2311	pDis->Param2.cb = pDis->Param1.cb;
2312	param2.size = param1.size;
2313	}
2314
2315	/* The destination is always a virtual address */
2316	if (param1.type == DISQPV_TYPE_ADDRESS)
2317	{
2318	pParam1 = (RTGCPTR)param1.val.val64;
2319	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2320	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2321	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2322	if (RT_FAILURE(rc))
2323	{
2324	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2325	return VERR_EM_INTERPRETER;
2326	}
2327	}
2328	else
2329	{
2330	AssertFailed();
2331	return VERR_EM_INTERPRETER;
2332	}
2333
2334	/* Register or immediate data */
2335	switch(param2.type)
2336	{
2337	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2338	valpar2 = param2.val.val64;
2339	break;
2340
2341	default:
2342	AssertFailed();
2343	return VERR_EM_INTERPRETER;
2344	}
2345
2346	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2347
2348	/* Data read, emulate instruction. */
2349	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2350
2351	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2352
2353	/* Update guest's eflags and finish. */
2354	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2355	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2356
2357	/* And write it back */
2358	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2359	if (RT_SUCCESS(rc))
2360	{
2361	/* All done! */
2362	*pcbSize = param2.size;
2363	return VINF_SUCCESS;
2364	}
2365	#ifdef IN_RC
2366	}
2367	}
2368	#endif
2369	return VERR_EM_INTERPRETER;
2370	}
2371
2372
2373	#ifndef VBOX_COMPARE_IEM_AND_EM
2374	/**
2375	* LOCK XOR/OR/AND Emulation.
2376	*/
2377	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2378	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2379	{
2380	void *pvParam1;
2381	DISQPVPARAMVAL param1, param2;
2382	NOREF(pvFault);
2383
2384	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
2385	Assert(pDis->Param1.cb <= 4);
2386	#endif
2387
2388	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2389	if(RT_FAILURE(rc))
2390	return VERR_EM_INTERPRETER;
2391
2392	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2393	if(RT_FAILURE(rc))
2394	return VERR_EM_INTERPRETER;
2395
2396	if (pDis->Param1.cb != pDis->Param2.cb)
2397	{
2398	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2399	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2400	VERR_EM_INTERPRETER);
2401
2402	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2403	pDis->Param2.cb = pDis->Param1.cb;
2404	param2.size = param1.size;
2405	}
2406
2407	#ifdef IN_RC
2408	/* Safety check (in theory it could cross a page boundary and fault there though) */
2409	Assert( TRPMHasTrap(pVCpu)
2410	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2411	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2412	#endif
2413
2414	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2415	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2416	RTGCUINTREG ValPar2 = param2.val.val64;
2417
2418	/* The destination is always a virtual address */
2419	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2420
2421	RTGCPTR GCPtrPar1 = param1.val.val64;
2422	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2423	PGMPAGEMAPLOCK Lock;
2424	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2425	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2426
2427	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2428	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2429
2430	RTGCUINTREG32 eflags = 0;
2431	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2432	PGMPhysReleasePageMappingLock(pVM, &Lock);
2433	if (RT_FAILURE(rc))
2434	{
2435	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2436	return VERR_EM_INTERPRETER;
2437	}
2438
2439	/* Update guest's eflags and finish. */
2440	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2441	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2442
2443	*pcbSize = param2.size;
2444	return VINF_SUCCESS;
2445	}
2446	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2447
2448
2449	/**
2450	* ADD, ADC & SUB Emulation.
2451	*/
2452	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2453	PFNEMULATEPARAM3 pfnEmulate)
2454	{
2455	NOREF(pvFault);
2456	DISQPVPARAMVAL param1, param2;
2457	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2458	if(RT_FAILURE(rc))
2459	return VERR_EM_INTERPRETER;
2460
2461	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2462	if(RT_FAILURE(rc))
2463	return VERR_EM_INTERPRETER;
2464
2465	#ifdef IN_RC
2466	if (TRPMHasTrap(pVCpu))
2467	{
2468	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2469	{
2470	#endif
2471	RTGCPTR pParam1;
2472	uint64_t valpar1, valpar2;
2473
2474	if (pDis->Param1.cb != pDis->Param2.cb)
2475	{
2476	if (pDis->Param1.cb < pDis->Param2.cb)
2477	{
2478	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2479	return VERR_EM_INTERPRETER;
2480	}
2481	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2482	pDis->Param2.cb = pDis->Param1.cb;
2483	param2.size = param1.size;
2484	}
2485
2486	/* The destination is always a virtual address */
2487	if (param1.type == DISQPV_TYPE_ADDRESS)
2488	{
2489	pParam1 = (RTGCPTR)param1.val.val64;
2490	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2491	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2492	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2493	if (RT_FAILURE(rc))
2494	{
2495	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2496	return VERR_EM_INTERPRETER;
2497	}
2498	}
2499	else
2500	{
2501	#ifndef DEBUG_bird
2502	AssertFailed();
2503	#endif
2504	return VERR_EM_INTERPRETER;
2505	}
2506
2507	/* Register or immediate data */
2508	switch(param2.type)
2509	{
2510	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2511	valpar2 = param2.val.val64;
2512	break;
2513
2514	default:
2515	AssertFailed();
2516	return VERR_EM_INTERPRETER;
2517	}
2518
2519	/* Data read, emulate instruction. */
2520	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2521
2522	/* Update guest's eflags and finish. */
2523	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2524	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2525
2526	/* And write it back */
2527	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2528	if (RT_SUCCESS(rc))
2529	{
2530	/* All done! */
2531	*pcbSize = param2.size;
2532	return VINF_SUCCESS;
2533	}
2534	#ifdef IN_RC
2535	}
2536	}
2537	#endif
2538	return VERR_EM_INTERPRETER;
2539	}
2540
2541
2542	/**
2543	* ADC Emulation.
2544	*/
2545	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2546	{
2547	if (pRegFrame->eflags.Bits.u1CF)
2548	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2549	else
2550	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2551	}
2552
2553
2554	/**
2555	* BTR/C/S Emulation.
2556	*/
2557	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2558	PFNEMULATEPARAM2UINT32 pfnEmulate)
2559	{
2560	DISQPVPARAMVAL param1, param2;
2561	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2562	if(RT_FAILURE(rc))
2563	return VERR_EM_INTERPRETER;
2564
2565	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2566	if(RT_FAILURE(rc))
2567	return VERR_EM_INTERPRETER;
2568
2569	#ifdef IN_RC
2570	if (TRPMHasTrap(pVCpu))
2571	{
2572	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2573	{
2574	#endif
2575	RTGCPTR pParam1;
2576	uint64_t valpar1 = 0, valpar2;
2577	uint32_t eflags;
2578
2579	/* The destination is always a virtual address */
2580	if (param1.type != DISQPV_TYPE_ADDRESS)
2581	return VERR_EM_INTERPRETER;
2582
2583	pParam1 = (RTGCPTR)param1.val.val64;
2584	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2585
2586	/* Register or immediate data */
2587	switch(param2.type)
2588	{
2589	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2590	valpar2 = param2.val.val64;
2591	break;
2592
2593	default:
2594	AssertFailed();
2595	return VERR_EM_INTERPRETER;
2596	}
2597
2598	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2599	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2600	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
2601	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2602	if (RT_FAILURE(rc))
2603	{
2604	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2605	return VERR_EM_INTERPRETER;
2606	}
2607
2608	Log2(("emInterpretBtx: val=%x\n", valpar1));
2609	/* Data read, emulate bit test instruction. */
2610	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2611
2612	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2613
2614	/* Update guest's eflags and finish. */
2615	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2616	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2617
2618	/* And write it back */
2619	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2620	if (RT_SUCCESS(rc))
2621	{
2622	/* All done! */
2623	*pcbSize = 1;
2624	return VINF_SUCCESS;
2625	}
2626	#ifdef IN_RC
2627	}
2628	}
2629	#endif
2630	return VERR_EM_INTERPRETER;
2631	}
2632
2633
2634	#ifndef VBOX_COMPARE_IEM_AND_EM
2635	/**
2636	* LOCK BTR/C/S Emulation.
2637	*/
2638	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2639	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2640	{
2641	void *pvParam1;
2642
2643	DISQPVPARAMVAL param1, param2;
2644	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2645	if(RT_FAILURE(rc))
2646	return VERR_EM_INTERPRETER;
2647
2648	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2649	if(RT_FAILURE(rc))
2650	return VERR_EM_INTERPRETER;
2651
2652	/* The destination is always a virtual address */
2653	if (param1.type != DISQPV_TYPE_ADDRESS)
2654	return VERR_EM_INTERPRETER;
2655
2656	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2657	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2658	uint64_t ValPar2 = param2.val.val64;
2659
2660	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2661	RTGCPTR GCPtrPar1 = param1.val.val64;
2662	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2663	ValPar2 &= 7;
2664
2665	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2666	#ifdef IN_RC
2667	Assert(TRPMHasTrap(pVCpu));
2668	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2669	#endif
2670
2671	PGMPAGEMAPLOCK Lock;
2672	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2673	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2674
2675	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2676
2677	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2678	RTGCUINTREG32 eflags = 0;
2679	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2680	PGMPhysReleasePageMappingLock(pVM, &Lock);
2681	if (RT_FAILURE(rc))
2682	{
2683	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2684	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2685	return VERR_EM_INTERPRETER;
2686	}
2687
2688	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2689
2690	/* Update guest's eflags and finish. */
2691	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2692	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2693
2694	*pcbSize = 1;
2695	return VINF_SUCCESS;
2696	}
2697	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2698
2699
2700	/**
2701	* MOV emulation.
2702	*/
2703	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2704	{
2705	NOREF(pvFault);
2706	DISQPVPARAMVAL param1, param2;
2707	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2708	if(RT_FAILURE(rc))
2709	return VERR_EM_INTERPRETER;
2710
2711	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2712	if(RT_FAILURE(rc))
2713	return VERR_EM_INTERPRETER;
2714
2715	/* If destination is a segment register, punt. We can't handle it here.
2716	* NB: Source can be a register and still trigger a #PF!
2717	*/
2718	if (RT_UNLIKELY(pDis->Param1.fUse == DISUSE_REG_SEG))
2719	return VERR_EM_INTERPRETER;
2720
2721	if (param1.type == DISQPV_TYPE_ADDRESS)
2722	{
2723	RTGCPTR pDest;
2724	uint64_t val64;
2725
2726	switch(param1.type)
2727	{
2728	case DISQPV_TYPE_IMMEDIATE:
2729	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2730	return VERR_EM_INTERPRETER;
2731	/* fallthru */
2732
2733	case DISQPV_TYPE_ADDRESS:
2734	pDest = (RTGCPTR)param1.val.val64;
2735	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2736	break;
2737
2738	default:
2739	AssertFailed();
2740	return VERR_EM_INTERPRETER;
2741	}
2742
2743	switch(param2.type)
2744	{
2745	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2746	val64 = param2.val.val64;
2747	break;
2748
2749	default:
2750	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2751	return VERR_EM_INTERPRETER;
2752	}
2753	#ifdef LOG_ENABLED
2754	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2755	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2756	else
2757	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2758	#endif
2759
2760	Assert(param2.size <= 8 && param2.size > 0);
2761	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2762	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2763	if (RT_FAILURE(rc))
2764	return VERR_EM_INTERPRETER;
2765
2766	*pcbSize = param2.size;
2767	}
2768	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2769	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2770	else if ( param1.type == DISQPV_TYPE_REGISTER
2771	&& param2.type == DISQPV_TYPE_REGISTER)
2772	{
2773	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2774	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2775	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2776
2777	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2778	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2779
2780	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2781	switch (param1.size)
2782	{
2783	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2784	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2785	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2786	default:
2787	AssertFailed();
2788	return VERR_EM_INTERPRETER;
2789	}
2790	AssertRCReturn(rc, rc);
2791	}
2792	#endif
2793	else
2794	{ /* read fault */
2795	RTGCPTR pSrc;
2796	uint64_t val64;
2797
2798	/* Source */
2799	switch(param2.type)
2800	{
2801	case DISQPV_TYPE_IMMEDIATE:
2802	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2803	return VERR_EM_INTERPRETER;
2804	/* fallthru */
2805
2806	case DISQPV_TYPE_ADDRESS:
2807	pSrc = (RTGCPTR)param2.val.val64;
2808	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2809	break;
2810
2811	default:
2812	return VERR_EM_INTERPRETER;
2813	}
2814
2815	Assert(param1.size <= 8 && param1.size > 0);
2816	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2817	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2818	if (RT_FAILURE(rc))
2819	return VERR_EM_INTERPRETER;
2820
2821	/* Destination */
2822	switch(param1.type)
2823	{
2824	case DISQPV_TYPE_REGISTER:
2825	switch(param1.size)
2826	{
2827	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2828	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2829	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2830	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2831	default:
2832	return VERR_EM_INTERPRETER;
2833	}
2834	if (RT_FAILURE(rc))
2835	return rc;
2836	break;
2837
2838	default:
2839	return VERR_EM_INTERPRETER;
2840	}
2841	#ifdef LOG_ENABLED
2842	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2843	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2844	else
2845	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2846	#endif
2847	}
2848	return VINF_SUCCESS;
2849	}
2850
2851
2852	#ifndef IN_RC
2853	/**
2854	* [REP] STOSWD emulation
2855	*/
2856	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2857	{
2858	int rc;
2859	RTGCPTR GCDest, GCOffset;
2860	uint32_t cbSize;
2861	uint64_t cTransfers;
2862	int offIncrement;
2863	NOREF(pvFault);
2864
2865	/* Don't support any but these three prefix bytes. */
2866	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2867	return VERR_EM_INTERPRETER;
2868
2869	switch (pDis->uAddrMode)
2870	{
2871	case DISCPUMODE_16BIT:
2872	GCOffset = pRegFrame->di;
2873	cTransfers = pRegFrame->cx;
2874	break;
2875	case DISCPUMODE_32BIT:
2876	GCOffset = pRegFrame->edi;
2877	cTransfers = pRegFrame->ecx;
2878	break;
2879	case DISCPUMODE_64BIT:
2880	GCOffset = pRegFrame->rdi;
2881	cTransfers = pRegFrame->rcx;
2882	break;
2883	default:
2884	AssertFailed();
2885	return VERR_EM_INTERPRETER;
2886	}
2887
2888	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2889	switch (pDis->uOpMode)
2890	{
2891	case DISCPUMODE_16BIT:
2892	cbSize = 2;
2893	break;
2894	case DISCPUMODE_32BIT:
2895	cbSize = 4;
2896	break;
2897	case DISCPUMODE_64BIT:
2898	cbSize = 8;
2899	break;
2900	default:
2901	AssertFailed();
2902	return VERR_EM_INTERPRETER;
2903	}
2904
2905	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2906
2907	if (!(pDis->fPrefix & DISPREFIX_REP))
2908	{
2909	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2910
2911	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2912	if (RT_FAILURE(rc))
2913	return VERR_EM_INTERPRETER;
2914	Assert(rc == VINF_SUCCESS);
2915
2916	/* Update (e/r)di. */
2917	switch (pDis->uAddrMode)
2918	{
2919	case DISCPUMODE_16BIT:
2920	pRegFrame->di += offIncrement;
2921	break;
2922	case DISCPUMODE_32BIT:
2923	pRegFrame->edi += offIncrement;
2924	break;
2925	case DISCPUMODE_64BIT:
2926	pRegFrame->rdi += offIncrement;
2927	break;
2928	default:
2929	AssertFailed();
2930	return VERR_EM_INTERPRETER;
2931	}
2932
2933	}
2934	else
2935	{
2936	if (!cTransfers)
2937	return VINF_SUCCESS;
2938
2939	/*
2940	* Do not try emulate cross page stuff here because we don't know what might
2941	* be waiting for us on the subsequent pages. The caller has only asked us to
2942	* ignore access handlers fro the current page.
2943	* This also fends off big stores which would quickly kill PGMR0DynMap.
2944	*/
2945	if ( cbSize > PAGE_SIZE
2946	\|\| cTransfers > PAGE_SIZE
2947	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2948	{
2949	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2950	GCDest, cbSize, offIncrement, cTransfers));
2951	return VERR_EM_INTERPRETER;
2952	}
2953
2954	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2955	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2956	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2957	cTransfers * cbSize,
2958	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
2959	if (rc != VINF_SUCCESS)
2960	{
2961	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
2962	return VERR_EM_INTERPRETER;
2963	}
2964
2965	/* REP case */
2966	while (cTransfers)
2967	{
2968	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2969	if (RT_FAILURE(rc))
2970	{
2971	rc = VERR_EM_INTERPRETER;
2972	break;
2973	}
2974
2975	Assert(rc == VINF_SUCCESS);
2976	GCOffset += offIncrement;
2977	GCDest += offIncrement;
2978	cTransfers--;
2979	}
2980
2981	/* Update the registers. */
2982	switch (pDis->uAddrMode)
2983	{
2984	case DISCPUMODE_16BIT:
2985	pRegFrame->di = GCOffset;
2986	pRegFrame->cx = cTransfers;
2987	break;
2988	case DISCPUMODE_32BIT:
2989	pRegFrame->edi = GCOffset;
2990	pRegFrame->ecx = cTransfers;
2991	break;
2992	case DISCPUMODE_64BIT:
2993	pRegFrame->rdi = GCOffset;
2994	pRegFrame->rcx = cTransfers;
2995	break;
2996	default:
2997	AssertFailed();
2998	return VERR_EM_INTERPRETER;
2999	}
3000	}
3001
3002	*pcbSize = cbSize;
3003	return rc;
3004	}
3005	#endif /* !IN_RC */
3006
3007
3008	/**
3009	* [LOCK] CMPXCHG emulation.
3010	*/
3011	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3012	{
3013	DISQPVPARAMVAL param1, param2;
3014	NOREF(pvFault);
3015
3016	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
3017	Assert(pDis->Param1.cb <= 4);
3018	#endif
3019
3020	/* Source to make DISQueryParamVal read the register value - ugly hack */
3021	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3022	if(RT_FAILURE(rc))
3023	return VERR_EM_INTERPRETER;
3024
3025	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
3026	if(RT_FAILURE(rc))
3027	return VERR_EM_INTERPRETER;
3028
3029	uint64_t valpar;
3030	switch(param2.type)
3031	{
3032	case DISQPV_TYPE_IMMEDIATE: /* register actually */
3033	valpar = param2.val.val64;
3034	break;
3035
3036	default:
3037	return VERR_EM_INTERPRETER;
3038	}
3039
3040	PGMPAGEMAPLOCK Lock;
3041	RTGCPTR GCPtrPar1;
3042	void *pvParam1;
3043	uint64_t eflags;
3044
3045	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3046	switch(param1.type)
3047	{
3048	case DISQPV_TYPE_ADDRESS:
3049	GCPtrPar1 = param1.val.val64;
3050	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3051
3052	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3053	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3054	break;
3055
3056	default:
3057	return VERR_EM_INTERPRETER;
3058	}
3059
3060	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
3061
3062	#ifndef VBOX_COMPARE_IEM_AND_EM
3063	if (pDis->fPrefix & DISPREFIX_LOCK)
3064	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3065	else
3066	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3067	#else /* VBOX_COMPARE_IEM_AND_EM */
3068	uint64_t u64;
3069	switch (pDis->Param2.cb)
3070	{
3071	case 1: u64 = (uint8_t )pvParam1; break;
3072	case 2: u64 = (uint16_t )pvParam1; break;
3073	case 4: u64 = (uint32_t )pvParam1; break;
3074	default:
3075	case 8: u64 = (uint64_t )pvParam1; break;
3076	}
3077	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
3078	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3079	#endif /* VBOX_COMPARE_IEM_AND_EM */
3080
3081	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
3082
3083	/* Update guest's eflags and finish. */
3084	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3085	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3086
3087	*pcbSize = param2.size;
3088	PGMPhysReleasePageMappingLock(pVM, &Lock);
3089	return VINF_SUCCESS;
3090	}
3091
3092
3093	/**
3094	* [LOCK] CMPXCHG8B emulation.
3095	*/
3096	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3097	{
3098	DISQPVPARAMVAL param1;
3099	NOREF(pvFault);
3100
3101	/* Source to make DISQueryParamVal read the register value - ugly hack */
3102	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3103	if(RT_FAILURE(rc))
3104	return VERR_EM_INTERPRETER;
3105
3106	RTGCPTR GCPtrPar1;
3107	void *pvParam1;
3108	uint64_t eflags;
3109	PGMPAGEMAPLOCK Lock;
3110
3111	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
3112	switch(param1.type)
3113	{
3114	case DISQPV_TYPE_ADDRESS:
3115	GCPtrPar1 = param1.val.val64;
3116	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3117
3118	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3119	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3120	break;
3121
3122	default:
3123	return VERR_EM_INTERPRETER;
3124	}
3125
3126	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax));
3127
3128	#ifndef VBOX_COMPARE_IEM_AND_EM
3129	if (pDis->fPrefix & DISPREFIX_LOCK)
3130	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3131	else
3132	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3133	#else /* VBOX_COMPARE_IEM_AND_EM */
3134	uint64_t u64 = (uint64_t )pvParam1;
3135	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3136	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
3137	#endif /* VBOX_COMPARE_IEM_AND_EM */
3138
3139	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
3140
3141	/* Update guest's eflags and finish; note that only ZF is affected. */
3142	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
3143	\| (eflags & (X86_EFL_ZF));
3144
3145	*pcbSize = 8;
3146	PGMPhysReleasePageMappingLock(pVM, &Lock);
3147	return VINF_SUCCESS;
3148	}
3149
3150
3151	#ifdef IN_RC /** @todo test+enable for HM as well. */
3152	/**
3153	* [LOCK] XADD emulation.
3154	*/
3155	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3156	{
3157	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
3158	DISQPVPARAMVAL param1;
3159	void *pvParamReg2;
3160	size_t cbParamReg2;
3161	NOREF(pvFault);
3162
3163	/* Source to make DISQueryParamVal read the register value - ugly hack */
3164	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3165	if(RT_FAILURE(rc))
3166	return VERR_EM_INTERPRETER;
3167
3168	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3169	Assert(cbParamReg2 <= 4);
3170	if(RT_FAILURE(rc))
3171	return VERR_EM_INTERPRETER;
3172
3173	#ifdef IN_RC
3174	if (TRPMHasTrap(pVCpu))
3175	{
3176	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3177	{
3178	#endif
3179	RTGCPTR GCPtrPar1;
3180	void *pvParam1;
3181	uint32_t eflags;
3182	PGMPAGEMAPLOCK Lock;
3183
3184	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3185	switch(param1.type)
3186	{
3187	case DISQPV_TYPE_ADDRESS:
3188	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3189	#ifdef IN_RC
3190	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3191	#endif
3192
3193	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3194	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3195	break;
3196
3197	default:
3198	return VERR_EM_INTERPRETER;
3199	}
3200
3201	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3202
3203	#ifndef VBOX_COMPARE_IEM_AND_EM
3204	if (pDis->fPrefix & DISPREFIX_LOCK)
3205	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3206	else
3207	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3208	#else /* VBOX_COMPARE_IEM_AND_EM */
3209	uint64_t u64;
3210	switch (cbParamReg2)
3211	{
3212	case 1: u64 = (uint8_t )pvParam1; break;
3213	case 2: u64 = (uint16_t )pvParam1; break;
3214	case 4: u64 = (uint32_t )pvParam1; break;
3215	default:
3216	case 8: u64 = (uint64_t )pvParam1; break;
3217	}
3218	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3219	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3220	#endif /* VBOX_COMPARE_IEM_AND_EM */
3221
3222	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3223
3224	/* Update guest's eflags and finish. */
3225	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3226	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3227
3228	*pcbSize = cbParamReg2;
3229	PGMPhysReleasePageMappingLock(pVM, &Lock);
3230	return VINF_SUCCESS;
3231	#ifdef IN_RC
3232	}
3233	}
3234
3235	return VERR_EM_INTERPRETER;
3236	#endif
3237	}
3238	#endif /* IN_RC */
3239
3240
3241	/**
3242	* WBINVD Emulation.
3243	*/
3244	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3245	{
3246	/* Nothing to do. */
3247	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3248	return VINF_SUCCESS;
3249	}
3250
3251
3252	/**
3253	* INVLPG Emulation.
3254	*/
3255	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3256	{
3257	DISQPVPARAMVAL param1;
3258	RTGCPTR addr;
3259	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3260
3261	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3262	if(RT_FAILURE(rc))
3263	return VERR_EM_INTERPRETER;
3264
3265	switch(param1.type)
3266	{
3267	case DISQPV_TYPE_IMMEDIATE:
3268	case DISQPV_TYPE_ADDRESS:
3269	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3270	return VERR_EM_INTERPRETER;
3271	addr = (RTGCPTR)param1.val.val64;
3272	break;
3273
3274	default:
3275	return VERR_EM_INTERPRETER;
3276	}
3277
3278	/** @todo is addr always a flat linear address or ds based
3279	* (in absence of segment override prefixes)????
3280	*/
3281	#ifdef IN_RC
3282	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3283	#endif
3284	rc = PGMInvalidatePage(pVCpu, addr);
3285	if ( rc == VINF_SUCCESS
3286	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3287	return VINF_SUCCESS;
3288	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3289	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3290	VERR_EM_INTERPRETER);
3291	return rc;
3292	}
3293
3294	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3295
3296	/**
3297	* CPUID Emulation.
3298	*/
3299	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3300	{
3301	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3302	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3303	return rc;
3304	}
3305
3306
3307	/**
3308	* CLTS Emulation.
3309	*/
3310	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3311	{
3312	NOREF(pVM); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3313
3314	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3315	if (!(cr0 & X86_CR0_TS))
3316	return VINF_SUCCESS;
3317	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
3318	}
3319
3320
3321	/**
3322	* LMSW Emulation.
3323	*/
3324	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3325	{
3326	DISQPVPARAMVAL param1;
3327	uint32_t val;
3328	NOREF(pvFault); NOREF(pcbSize);
3329	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3330
3331	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3332	if(RT_FAILURE(rc))
3333	return VERR_EM_INTERPRETER;
3334
3335	switch(param1.type)
3336	{
3337	case DISQPV_TYPE_IMMEDIATE:
3338	case DISQPV_TYPE_ADDRESS:
3339	if(!(param1.flags & DISQPV_FLAG_16))
3340	return VERR_EM_INTERPRETER;
3341	val = param1.val.val32;
3342	break;
3343
3344	default:
3345	return VERR_EM_INTERPRETER;
3346	}
3347
3348	LogFlow(("emInterpretLmsw %x\n", val));
3349	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
3350
3351	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
3352	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
3353	\| (val & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
3354
3355	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
3356
3357	}
3358
3359	#ifdef EM_EMULATE_SMSW
3360	/**
3361	* SMSW Emulation.
3362	*/
3363	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3364	{
3365	NOREF(pvFault); NOREF(pcbSize);
3366	DISQPVPARAMVAL param1;
3367	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3368
3369	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3370	if(RT_FAILURE(rc))
3371	return VERR_EM_INTERPRETER;
3372
3373	switch(param1.type)
3374	{
3375	case DISQPV_TYPE_IMMEDIATE:
3376	if(param1.size != sizeof(uint16_t))
3377	return VERR_EM_INTERPRETER;
3378	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3379	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3380	break;
3381
3382	case DISQPV_TYPE_ADDRESS:
3383	{
3384	RTGCPTR pParam1;
3385
3386	/* Actually forced to 16 bits regardless of the operand size. */
3387	if(param1.size != sizeof(uint16_t))
3388	return VERR_EM_INTERPRETER;
3389
3390	pParam1 = (RTGCPTR)param1.val.val64;
3391	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3392	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3393
3394	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3395	if (RT_FAILURE(rc))
3396	{
3397	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3398	return VERR_EM_INTERPRETER;
3399	}
3400	break;
3401	}
3402
3403	default:
3404	return VERR_EM_INTERPRETER;
3405	}
3406
3407	LogFlow(("emInterpretSmsw %x\n", cr0));
3408	return rc;
3409	}
3410	#endif
3411
3412	/**
3413	* MOV CRx
3414	*/
3415	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3416	{
3417	NOREF(pvFault); NOREF(pcbSize);
3418	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3419	return emInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3420
3421	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3422	return emInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3423
3424	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3425	}
3426
3427
3428	/**
3429	* MOV DRx
3430	*/
3431	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3432	{
3433	int rc = VERR_EM_INTERPRETER;
3434	NOREF(pvFault); NOREF(pcbSize);
3435
3436	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3437	{
3438	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3439	}
3440	else
3441	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3442	{
3443	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3444	}
3445	else
3446	AssertMsgFailed(("Unexpected debug register move\n"));
3447
3448	return rc;
3449	}
3450
3451
3452	/**
3453	* LLDT Emulation.
3454	*/
3455	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3456	{
3457	DISQPVPARAMVAL param1;
3458	RTSEL sel;
3459	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3460
3461	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3462	if(RT_FAILURE(rc))
3463	return VERR_EM_INTERPRETER;
3464
3465	switch(param1.type)
3466	{
3467	case DISQPV_TYPE_ADDRESS:
3468	return VERR_EM_INTERPRETER; //feeling lazy right now
3469
3470	case DISQPV_TYPE_IMMEDIATE:
3471	if(!(param1.flags & DISQPV_FLAG_16))
3472	return VERR_EM_INTERPRETER;
3473	sel = (RTSEL)param1.val.val16;
3474	break;
3475
3476	default:
3477	return VERR_EM_INTERPRETER;
3478	}
3479
3480	#ifdef IN_RING0
3481	/* Only for the VT-x real-mode emulation case. */
3482	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3483	CPUMSetGuestLDTR(pVCpu, sel);
3484	return VINF_SUCCESS;
3485	#else
3486	if (sel == 0)
3487	{
3488	if (CPUMGetHyperLDTR(pVCpu) == 0)
3489	{
3490	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3491	return VINF_SUCCESS;
3492	}
3493	}
3494	//still feeling lazy
3495	return VERR_EM_INTERPRETER;
3496	#endif
3497	}
3498
3499	#ifdef IN_RING0
3500	/**
3501	* LIDT/LGDT Emulation.
3502	*/
3503	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3504	{
3505	DISQPVPARAMVAL param1;
3506	RTGCPTR pParam1;
3507	X86XDTR32 dtr32;
3508	NOREF(pvFault); NOREF(pcbSize);
3509
3510	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3511
3512	/* Only for the VT-x real-mode emulation case. */
3513	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3514
3515	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3516	if(RT_FAILURE(rc))
3517	return VERR_EM_INTERPRETER;
3518
3519	switch(param1.type)
3520	{
3521	case DISQPV_TYPE_ADDRESS:
3522	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3523	break;
3524
3525	default:
3526	return VERR_EM_INTERPRETER;
3527	}
3528
3529	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3530	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3531
3532	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3533	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3534
3535	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3536	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3537	else
3538	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3539
3540	return VINF_SUCCESS;
3541	}
3542	#endif
3543
3544
3545	#ifdef IN_RC
3546	/**
3547	* STI Emulation.
3548	*
3549	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3550	*/
3551	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3552	{
3553	NOREF(pcbSize);
3554	PPATMGCSTATE pGCState = PATMGetGCState(pVM);
3555
3556	if(!pGCState)
3557	{
3558	Assert(pGCState);
3559	return VERR_EM_INTERPRETER;
3560	}
3561	pGCState->uVMFlags \|= X86_EFL_IF;
3562
3563	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3564	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3565
3566	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3567	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3568
3569	return VINF_SUCCESS;
3570	}
3571	#endif /* IN_RC */
3572
3573
3574	/**
3575	* HLT Emulation.
3576	*/
3577	static VBOXSTRICTRC
3578	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3579	{
3580	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3581	return VINF_EM_HALT;
3582	}
3583
3584
3585	/**
3586	* RDTSC Emulation.
3587	*/
3588	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3589	{
3590	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3591	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3592	}
3593
3594	/**
3595	* RDPMC Emulation
3596	*/
3597	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3598	{
3599	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3600	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3601	}
3602
3603
3604	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3605	{
3606	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3607	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3608	}
3609
3610
3611	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3612	{
3613	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3614	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3615	}
3616
3617
3618	/**
3619	* RDMSR Emulation.
3620	*/
3621	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3622	{
3623	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3624	different, so we play safe by completely disassembling the instruction. */
3625	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3626	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3627	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3628	}
3629
3630
3631	/**
3632	* WRMSR Emulation.
3633	*/
3634	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3635	{
3636	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3637	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3638	}
3639
3640
3641	/**
3642	* Internal worker.
3643	* @copydoc emInterpretInstructionCPUOuter
3644	*/
3645	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3646	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3647	{
3648	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3649	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3650	Assert(pcbSize);
3651	*pcbSize = 0;
3652
3653	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3654	{
3655	/*
3656	* Only supervisor guest code!!
3657	* And no complicated prefixes.
3658	*/
3659	/* Get the current privilege level. */
3660	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3661	#ifdef VBOX_WITH_RAW_RING1
3662	if ( !EMIsRawRing1Enabled(pVM)
3663	\|\| cpl > 1
3664	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3665	)
3666	#endif
3667	{
3668	if ( cpl != 0
3669	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3670	{
3671	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3672	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3673	return VERR_EM_INTERPRETER;
3674	}
3675	}
3676	}
3677	else
3678	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3679
3680	#ifdef IN_RC
3681	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3682	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3683	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3684	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3685	&& pDis->pCurInstr->uOpcode != OP_XADD
3686	&& pDis->pCurInstr->uOpcode != OP_OR
3687	&& pDis->pCurInstr->uOpcode != OP_AND
3688	&& pDis->pCurInstr->uOpcode != OP_XOR
3689	&& pDis->pCurInstr->uOpcode != OP_BTR
3690	)
3691	)
3692	#else
3693	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3694	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3695	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3696	)
3697	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3698	&& pDis->pCurInstr->uOpcode != OP_OR
3699	&& pDis->pCurInstr->uOpcode != OP_AND
3700	&& pDis->pCurInstr->uOpcode != OP_XOR
3701	&& pDis->pCurInstr->uOpcode != OP_BTR
3702	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3703	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3704	)
3705	)
3706	#endif
3707	{
3708	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3709	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3710	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3711	return VERR_EM_INTERPRETER;
3712	}
3713
3714	#if HC_ARCH_BITS == 32
3715	/*
3716	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3717	* Whitelisted instructions are safe.
3718	*/
3719	if ( pDis->Param1.cb > 4
3720	&& CPUMIsGuestIn64BitCode(pVCpu))
3721	{
3722	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3723	if ( uOpCode != OP_STOSWD
3724	&& uOpCode != OP_MOV
3725	&& uOpCode != OP_CMPXCHG8B
3726	&& uOpCode != OP_XCHG
3727	&& uOpCode != OP_BTS
3728	&& uOpCode != OP_BTR
3729	&& uOpCode != OP_BTC
3730	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3731	&& uOpCode != OP_CMPXCHG /* solaris */
3732	&& uOpCode != OP_AND /* windows */
3733	&& uOpCode != OP_OR /* windows */
3734	&& uOpCode != OP_XOR /* because we can */
3735	&& uOpCode != OP_ADD /* windows (dripple) */
3736	&& uOpCode != OP_ADC /* because we can */
3737	&& uOpCode != OP_SUB /* because we can */
3738	/** @todo OP_BTS or is that a different kind of failure? */
3739	# endif
3740	)
3741	{
3742	# ifdef VBOX_WITH_STATISTICS
3743	switch (pDis->pCurInstr->uOpcode)
3744	{
3745	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3746	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3747	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3748	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3749	INTERPRET_FAILED_CASE(OP_INC,Inc);
3750	INTERPRET_FAILED_CASE(OP_POP,Pop);
3751	INTERPRET_FAILED_CASE(OP_OR, Or);
3752	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3753	INTERPRET_FAILED_CASE(OP_AND,And);
3754	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3755	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3756	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3757	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3758	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3759	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3760	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3761	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3762	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3763	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3764	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3765	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3766	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3767	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3768	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3769	INTERPRET_FAILED_CASE(OP_ADD,Add);
3770	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3771	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3772	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3773	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3774	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3775	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3776	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3777	INTERPRET_FAILED_CASE(OP_STI, Sti);
3778	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3779	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3780	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3781	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3782	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3783	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3784	# undef INTERPRET_FAILED_CASE
3785	default:
3786	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3787	break;
3788	}
3789	# endif /* VBOX_WITH_STATISTICS */
3790	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3791	return VERR_EM_INTERPRETER;
3792	}
3793	}
3794	#endif
3795
3796	VBOXSTRICTRC rc;
3797	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3798	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3799	#endif
3800	switch (pDis->pCurInstr->uOpcode)
3801	{
3802	/*
3803	* Macros for generating the right case statements.
3804	*/
3805	# ifndef VBOX_COMPARE_IEM_AND_EM
3806	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3807	case opcode:\
3808	if (pDis->fPrefix & DISPREFIX_LOCK) \
3809	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3810	else \
3811	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3812	if (RT_SUCCESS(rc)) \
3813	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3814	else \
3815	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3816	return rc
3817	# else /* VBOX_COMPARE_IEM_AND_EM */
3818	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3819	case opcode:\
3820	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3821	if (RT_SUCCESS(rc)) \
3822	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3823	else \
3824	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3825	return rc
3826	# endif /* VBOX_COMPARE_IEM_AND_EM */
3827
3828	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3829	case opcode:\
3830	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3831	if (RT_SUCCESS(rc)) \
3832	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3833	else \
3834	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3835	return rc
3836
3837	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3838	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3839	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3840	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3841
3842	#define INTERPRET_CASE(opcode, Instr) \
3843	case opcode:\
3844	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3845	if (RT_SUCCESS(rc)) \
3846	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3847	else \
3848	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3849	return rc
3850
3851	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3852	case opcode:\
3853	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3854	if (RT_SUCCESS(rc)) \
3855	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3856	else \
3857	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3858	return rc
3859
3860	#define INTERPRET_STAT_CASE(opcode, Instr) \
3861	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3862
3863	/*
3864	* The actual case statements.
3865	*/
3866	INTERPRET_CASE(OP_XCHG,Xchg);
3867	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3868	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3869	INTERPRET_CASE(OP_POP,Pop);
3870	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3871	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3872	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3873	INTERPRET_CASE(OP_MOV,Mov);
3874	#ifndef IN_RC
3875	INTERPRET_CASE(OP_STOSWD,StosWD);
3876	#endif
3877	INTERPRET_CASE(OP_INVLPG,InvlPg);
3878	INTERPRET_CASE(OP_CPUID,CpuId);
3879	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3880	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3881	#ifdef IN_RING0
3882	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3883	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3884	#endif
3885	INTERPRET_CASE(OP_LLDT,LLdt);
3886	INTERPRET_CASE(OP_LMSW,Lmsw);
3887	#ifdef EM_EMULATE_SMSW
3888	INTERPRET_CASE(OP_SMSW,Smsw);
3889	#endif
3890	INTERPRET_CASE(OP_CLTS,Clts);
3891	INTERPRET_CASE(OP_MONITOR, Monitor);
3892	INTERPRET_CASE(OP_MWAIT, MWait);
3893	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3894	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3895	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3896	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3897	INTERPRET_CASE(OP_ADC,Adc);
3898	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3899	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3900	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3901	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3902	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3903	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3904	#ifdef IN_RC
3905	INTERPRET_CASE(OP_STI,Sti);
3906	INTERPRET_CASE(OP_XADD, XAdd);
3907	INTERPRET_CASE(OP_IRET,Iret);
3908	#endif
3909	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3910	INTERPRET_CASE(OP_HLT,Hlt);
3911	INTERPRET_CASE(OP_WBINVD,WbInvd);
3912	#ifdef VBOX_WITH_STATISTICS
3913	# ifndef IN_RC
3914	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3915	# endif
3916	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3917	#endif
3918
3919	default:
3920	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3921	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3922	return VERR_EM_INTERPRETER;
3923
3924	#undef INTERPRET_CASE_EX_PARAM2
3925	#undef INTERPRET_STAT_CASE
3926	#undef INTERPRET_CASE_EX
3927	#undef INTERPRET_CASE
3928	} /* switch (opcode) */
3929	/* not reached */
3930	}
3931
3932	/**
3933	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3934	*
3935	* EIP is NOT updated!
3936	*
3937	* @returns VBox strict status code.
3938	* @retval VINF_* Scheduling instructions. When these are returned, it
3939	* starts to get a bit tricky to know whether code was
3940	* executed or not... We'll address this when it becomes a problem.
3941	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3942	* @retval VERR_* Fatal errors.
3943	*
3944	* @param pVCpu Pointer to the VMCPU.
3945	* @param pDis The disassembler cpu state for the instruction to be
3946	* interpreted.
3947	* @param pRegFrame The register frame. EIP is NOT changed!
3948	* @param pvFault The fault address (CR2).
3949	* @param pcbSize Size of the write (if applicable).
3950	* @param enmCodeType Code type (user/supervisor)
3951	*
3952	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
3953	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
3954	* to worry about e.g. invalid modrm combinations (!)
3955	*
3956	* @todo At this time we do NOT check if the instruction overwrites vital information.
3957	* Make sure this can't happen!! (will add some assertions/checks later)
3958	*/
3959	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3960	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3961	{
3962	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3963	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
3964	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3965	if (RT_SUCCESS(rc))
3966	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3967	else
3968	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
3969	return rc;
3970	}
3971
3972
3973	#endif /* !VBOX_WITH_IEM */

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 56287

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