DBGFAll.cpp@ 98029

Last change on this file since 98029 was 98029, checked in by vboxsync, 22 months ago
VMM/DBGF: Adjust DR6 for instruction breakpoints on AMD, only enabled BPs are flagged. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 22.2 KB

Line
1	/* $Id: DBGFAll.cpp 98029 2023-01-09 10:58:23Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, All Context Code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DBGF
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/dbgf.h>
35	#include "DBGFInternal.h"
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/vmcc.h>
38	#include <VBox/err.h>
39	#include <iprt/assert.h>
40	#include <iprt/asm.h>
41	#include <iprt/stdarg.h>
42
43
44	/*
45	* Check the read-only VM members.
46	*/
47	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
48	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
49	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
50	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
51	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
52	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
53
54
55	/**
56	* Gets the hardware breakpoint configuration as DR7.
57	*
58	* @returns DR7 from the DBGF point of view.
59	* @param pVM The cross context VM structure.
60	*/
61	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
62	{
63	RTGCUINTREG uDr7 = X86_DR7_GD \| X86_DR7_GE \| X86_DR7_LE \| X86_DR7_RA1_MASK;
64	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); i++)
65	{
66	if ( pVM->dbgf.s.aHwBreakpoints[i].fEnabled
67	&& pVM->dbgf.s.aHwBreakpoints[i].hBp != NIL_DBGFBP)
68	{
69	static const uint8_t s_au8Sizes[8] =
70	{
71	X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
72	X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
73	};
74	uDr7 \|= X86_DR7_G(i)
75	\| X86_DR7_RW(i, pVM->dbgf.s.aHwBreakpoints[i].fType)
76	\| X86_DR7_LEN(i, s_au8Sizes[pVM->dbgf.s.aHwBreakpoints[i].cb]);
77	}
78	}
79	return uDr7;
80	}
81
82
83	/**
84	* Gets the address of the hardware breakpoint number 0.
85	*
86	* @returns DR0 from the DBGF point of view.
87	* @param pVM The cross context VM structure.
88	*/
89	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
90	{
91	return pVM->dbgf.s.aHwBreakpoints[0].GCPtr;
92	}
93
94
95	/**
96	* Gets the address of the hardware breakpoint number 1.
97	*
98	* @returns DR1 from the DBGF point of view.
99	* @param pVM The cross context VM structure.
100	*/
101	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
102	{
103	return pVM->dbgf.s.aHwBreakpoints[1].GCPtr;
104	}
105
106
107	/**
108	* Gets the address of the hardware breakpoint number 2.
109	*
110	* @returns DR2 from the DBGF point of view.
111	* @param pVM The cross context VM structure.
112	*/
113	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
114	{
115	return pVM->dbgf.s.aHwBreakpoints[2].GCPtr;
116	}
117
118
119	/**
120	* Gets the address of the hardware breakpoint number 3.
121	*
122	* @returns DR3 from the DBGF point of view.
123	* @param pVM The cross context VM structure.
124	*/
125	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
126	{
127	return pVM->dbgf.s.aHwBreakpoints[3].GCPtr;
128	}
129
130
131	/**
132	* Checks if any of the hardware breakpoints are armed.
133	*
134	* @returns true if armed, false if not.
135	* @param pVM The cross context VM structure.
136	* @remarks Don't call this from CPUMRecalcHyperDRx!
137	*/
138	VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
139	{
140	return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
141	}
142
143
144	/**
145	* Checks if any of the hardware I/O breakpoints are armed.
146	*
147	* @returns true if armed, false if not.
148	* @param pVM The cross context VM structure.
149	* @remarks Don't call this from CPUMRecalcHyperDRx!
150	*/
151	VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
152	{
153	return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
154	}
155
156
157	/**
158	* Checks if any INT3 breakpoints are armed.
159	*
160	* @returns true if armed, false if not.
161	* @param pVM The cross context VM structure.
162	* @remarks Don't call this from CPUMRecalcHyperDRx!
163	*/
164	VMM_INT_DECL(bool) DBGFBpIsInt3Armed(PVM pVM)
165	{
166	/** @todo There was a todo here and returning false when I (bird) removed
167	* VBOX_WITH_LOTS_OF_DBGF_BPS, so this might not be correct. */
168	return pVM->dbgf.s.cEnabledInt3Breakpoints > 0;
169	}
170
171
172	/**
173	* Checks instruction boundrary for guest or hypervisor hardware breakpoints.
174	*
175	* @returns Strict VBox status code. May return DRx register import errors in
176	* addition to the ones detailed.
177	* @retval VINF_SUCCESS no breakpoint.
178	* @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
179	* @retval VINF_EM_RAW_GUEST_TRAP caller must trigger \#DB trap, DR6 and DR7
180	* have been updated appropriately.
181	*
182	* @param pVM The cross context VM structure.
183	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
184	* @param GCPtrPC The unsegmented PC address.
185	*/
186	VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckInstruction(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrPC)
187	{
188	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
189
190	/*
191	* Check hyper breakpoints first as the VMM debugger has priority over
192	* the guest.
193	*/
194	/** @todo we need some kind of resume flag for these. */
195	if (pVM->dbgf.s.cEnabledHwBreakpoints > 0)
196	for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
197	{
198	if ( pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr != GCPtrPC
199	\|\| pVM->dbgf.s.aHwBreakpoints[iBp].fType != X86_DR7_RW_EO
200	\|\| pVM->dbgf.s.aHwBreakpoints[iBp].cb != 1
201	\|\| !pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
202	\|\| pVM->dbgf.s.aHwBreakpoints[iBp].hBp == NIL_DBGFBP)
203	{ /likely/ }
204	else
205	{
206	/* (See also DBGFRZTrap01Handler.) */
207	pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
208	pVCpu->dbgf.s.fSingleSteppingRaw = false;
209
210	LogFlow(("DBGFBpCheckInstruction: hit hw breakpoint %u at %04x:%RGv (%RGv)\n",
211	iBp, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPtrPC));
212	return VINF_EM_DBG_BREAKPOINT;
213	}
214	}
215
216	/*
217	* Check the guest.
218	*/
219	uint32_t const fDr7 = (uint32_t)pVCpu->cpum.GstCtx.dr[7];
220	if (X86_DR7_ANY_EO_ENABLED(fDr7) && !pVCpu->cpum.GstCtx.eflags.Bits.u1RF)
221	{
222	/*
223	* The CPU (10980XE & 6700K at least) will set the DR6.BPx bits for any
224	* DRx that matches the current PC and is configured as an execution
225	* breakpoint (RWx=EO, LENx=1byte). They don't have to be enabled,
226	* however one that is enabled must match for the #DB to be raised and
227	* DR6 to be modified, of course.
228	*/
229	CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
230	uint32_t fMatched = 0;
231	uint32_t fEnabled = 0;
232	for (unsigned iBp = 0, uBpMask = 1; iBp < 4; iBp++, uBpMask <<= 1)
233	if (X86_DR7_IS_EO_CFG(fDr7, iBp))
234	{
235	if (fDr7 & X86_DR7_L_G(iBp))
236	fEnabled \|= uBpMask;
237	if (pVCpu->cpum.GstCtx.dr[iBp] == GCPtrPC)
238	fMatched \|= uBpMask;
239	}
240	if (!(fEnabled & fMatched))
241	{ /likely/ }
242	else if (fEnabled & fMatched)
243	{
244	/*
245	* Update DR6 and DR7.
246	*
247	* See "AMD64 Architecture Programmer's Manual Volume 2", chapter
248	* 13.1.1.3 for details on DR6 bits. The basics is that the B0..B3
249	* bits are always cleared while the others must be cleared by software.
250	*
251	* The following sub chapters says the GD bit is always cleared when
252	* generating a #DB so the handler can safely access the debug registers.
253	*/
254	CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_DR6);
255	pVCpu->cpum.GstCtx.dr[6] &= ~X86_DR6_B_MASK;
256	if (pVM->cpum.ro.GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INTEL)
257	pVCpu->cpum.GstCtx.dr[6] \|= fMatched & fEnabled;
258	else
259	pVCpu->cpum.GstCtx.dr[6] \|= fMatched; /* Intel: All matched, regardless of whether they're enabled or not */
260	pVCpu->cpum.GstCtx.dr[7] &= ~X86_DR7_GD;
261	LogFlow(("DBGFBpCheckInstruction: hit hw breakpoints %#x at %04x:%RGv (%RGv)\n",
262	fMatched, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPtrPC));
263	return VINF_EM_RAW_GUEST_TRAP;
264	}
265	}
266	return VINF_SUCCESS;
267	}
268
269
270	/**
271	* Checks I/O access for guest or hypervisor hardware breakpoints.
272	*
273	* @returns Strict VBox status code
274	* @retval VINF_SUCCESS no breakpoint.
275	* @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
276	* @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
277	* been updated appropriately.
278	*
279	* @param pVM The cross context VM structure.
280	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
281	* @param pCtx The CPU context for the calling EMT.
282	* @param uIoPort The I/O port being accessed.
283	* @param cbValue The size/width of the access, in bytes.
284	*/
285	VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
286	{
287	uint32_t const uIoPortFirst = uIoPort;
288	uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
289
290	/*
291	* Check hyper breakpoints first as the VMM debugger has priority over
292	* the guest.
293	*/
294	if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
295	{
296	for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
297	{
298	if ( pVM->dbgf.s.aHwBreakpoints[iBp].fType == X86_DR7_RW_IO
299	&& pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
300	&& pVM->dbgf.s.aHwBreakpoints[iBp].hBp != NIL_DBGFBP)
301	{
302	uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
303	uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
304	uint64_t uDrXLast = uDrXFirst + cbReg - 1;
305	if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
306	{
307	/* (See also DBGFRZTrap01Handler.) */
308	pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
309	pVCpu->dbgf.s.fSingleSteppingRaw = false;
310
311	LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
312	iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
313	return VINF_EM_DBG_BREAKPOINT;
314	}
315	}
316	}
317	}
318
319	/*
320	* Check the guest.
321	*/
322	uint32_t const uDr7 = pCtx->dr[7];
323	if ( (uDr7 & X86_DR7_ENABLED_MASK)
324	&& X86_DR7_ANY_RW_IO(uDr7)
325	&& (pCtx->cr4 & X86_CR4_DE) )
326	{
327	for (unsigned iBp = 0; iBp < 4; iBp++)
328	{
329	if ( (uDr7 & X86_DR7_L_G(iBp))
330	&& X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
331	{
332	/* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
333	static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
334	uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
335	uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
336	uint64_t uDrXLast = uDrXFirst + cbInvAlign;
337
338	if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
339	{
340	/*
341	* Update DR6 and DR7.
342	*
343	* See "AMD64 Architecture Programmer's Manual Volume 2",
344	* chapter 13.1.1.3 for details on DR6 bits. The basics is
345	* that the B0..B3 bits are always cleared while the others
346	* must be cleared by software.
347	*
348	* The following sub chapters says the GD bit is always
349	* cleared when generating a #DB so the handler can safely
350	* access the debug registers.
351	*/
352	pCtx->dr[6] &= ~X86_DR6_B_MASK;
353	pCtx->dr[6] \|= X86_DR6_B(iBp);
354	pCtx->dr[7] &= ~X86_DR7_GD;
355	LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
356	iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
357	return VINF_EM_RAW_GUEST_TRAP;
358	}
359	}
360	}
361	}
362	return VINF_SUCCESS;
363	}
364
365
366	/**
367	* Checks I/O access for guest or hypervisor hardware breakpoints.
368	*
369	* Caller must make sure DR0-3 and DR7 are present in the CPU context before
370	* calling this function.
371	*
372	* @returns CPUMCTX_DBG_DBGF_BP, CPUMCTX_DBG_HIT_DRX_MASK, or 0 (no match).
373	*
374	* @param pVM The cross context VM structure.
375	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
376	* @param uIoPort The I/O port being accessed.
377	* @param cbValue The size/width of the access, in bytes.
378	*/
379	VMM_INT_DECL(uint32_t) DBGFBpCheckIo2(PVMCC pVM, PVMCPUCC pVCpu, RTIOPORT uIoPort, uint8_t cbValue)
380	{
381	uint32_t const uIoPortFirst = uIoPort;
382	uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
383
384	/*
385	* Check hyper breakpoints first as the VMM debugger has priority over
386	* the guest.
387	*/
388	if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
389	for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
390	{
391	if ( pVM->dbgf.s.aHwBreakpoints[iBp].fType == X86_DR7_RW_IO
392	&& pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
393	&& pVM->dbgf.s.aHwBreakpoints[iBp].hBp != NIL_DBGFBP)
394	{
395	uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
396	uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
397	uint64_t uDrXLast = uDrXFirst + cbReg - 1;
398	if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
399	{
400	/* (See also DBGFRZTrap01Handler.) */
401	pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
402	pVCpu->dbgf.s.fSingleSteppingRaw = false;
403
404	LogFlow(("DBGFBpCheckIo2: hit hw breakpoint %d at %04x:%RGv (iop %#x L %u)\n",
405	iBp, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uIoPort, cbValue));
406	return CPUMCTX_DBG_DBGF_BP;
407	}
408	}
409	}
410
411	/*
412	* Check the guest.
413	*/
414	uint32_t const fDr7 = pVCpu->cpum.GstCtx.dr[7];
415	if ( (fDr7 & X86_DR7_ENABLED_MASK)
416	&& X86_DR7_ANY_RW_IO(fDr7)
417	&& (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
418	{
419	uint32_t fEnabled = 0;
420	uint32_t fMatched = 0;
421	for (unsigned iBp = 0, uBpMask = 1; iBp < 4; iBp++, uBpMask <<= 1)
422	{
423	if (fDr7 & X86_DR7_L_G(iBp))
424	fEnabled \|= uBpMask;
425	if (X86_DR7_GET_RW(fDr7, iBp) == X86_DR7_RW_IO)
426	{
427	/* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
428	static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
429	uint8_t const cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(fDr7, iBp)];
430	uint64_t const uDrXFirst = pVCpu->cpum.GstCtx.dr[iBp] & ~(uint64_t)cbInvAlign;
431	uint64_t const uDrXLast = uDrXFirst + cbInvAlign;
432	if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
433	fMatched \|= uBpMask;
434	}
435	}
436	if (fEnabled & fMatched)
437	{
438	LogFlow(("DBGFBpCheckIo2: hit hw breakpoint %#x at %04x:%RGv (iop %#x L %u)\n",
439	fMatched, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uIoPort, cbValue));
440	return fMatched << CPUMCTX_DBG_HIT_DRX_SHIFT;
441	}
442	}
443
444	return 0;
445	}
446
447
448	/**
449	* Returns the single stepping state for a virtual CPU.
450	*
451	* @returns stepping (true) or not (false).
452	*
453	* @param pVCpu The cross context virtual CPU structure.
454	*/
455	VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
456	{
457	return pVCpu->dbgf.s.fSingleSteppingRaw;
458	}
459
460
461	/**
462	* Checks if the specified generic event is enabled or not.
463	*
464	* @returns true / false.
465	* @param pVM The cross context VM structure.
466	* @param enmEvent The generic event being raised.
467	* @param uEventArg The argument of that event.
468	*/
469	DECLINLINE(bool) dbgfEventIsGenericWithArgEnabled(PVM pVM, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
470	{
471	if (DBGF_IS_EVENT_ENABLED(pVM, enmEvent))
472	{
473	switch (enmEvent)
474	{
475	case DBGFEVENT_INTERRUPT_HARDWARE:
476	AssertReturn(uEventArg < 256, false);
477	return ASMBitTest(pVM->dbgf.s.bmHardIntBreakpoints, (uint32_t)uEventArg);
478
479	case DBGFEVENT_INTERRUPT_SOFTWARE:
480	AssertReturn(uEventArg < 256, false);
481	return ASMBitTest(pVM->dbgf.s.bmSoftIntBreakpoints, (uint32_t)uEventArg);
482
483	default:
484	return true;
485
486	}
487	}
488	return false;
489	}
490
491
492	/**
493	* Raises a generic debug event if enabled and not being ignored.
494	*
495	* @returns Strict VBox status code.
496	* @retval VINF_EM_DBG_EVENT if the event was raised and the caller should
497	* return ASAP to the debugger (via EM). We set VMCPU_FF_DBGF so, it
498	* is okay not to pass this along in some situations.
499	* @retval VINF_SUCCESS if the event was disabled or ignored.
500	*
501	* @param pVM The cross context VM structure.
502	* @param pVCpu The cross context virtual CPU structure.
503	* @param enmEvent The generic event being raised.
504	* @param enmCtx The context in which this event is being raised.
505	* @param cArgs Number of arguments (0 - 6).
506	* @param ... Event arguments.
507	*
508	* @thread EMT(pVCpu)
509	*/
510	VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArgs(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, DBGFEVENTCTX enmCtx,
511	unsigned cArgs, ...)
512	{
513	Assert(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[0].Event.u.Generic.auArgs));
514
515	/*
516	* Is it enabled.
517	*/
518	va_list va;
519	va_start(va, cArgs);
520	uint64_t uEventArg0 = cArgs ? va_arg(va, uint64_t) : 0;
521	if (dbgfEventIsGenericWithArgEnabled(pVM, enmEvent, uEventArg0))
522	{
523	/*
524	* Any events on the stack. Should the incoming event be ignored?
525	*/
526	uint64_t const rip = CPUMGetGuestRIP(pVCpu);
527	uint32_t i = pVCpu->dbgf.s.cEvents;
528	if (i > 0)
529	{
530	while (i-- > 0)
531	{
532	if ( pVCpu->dbgf.s.aEvents[i].Event.enmType == enmEvent
533	&& pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE
534	&& pVCpu->dbgf.s.aEvents[i].rip == rip)
535	{
536	pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_RESTORABLE;
537	va_end(va);
538	return VINF_SUCCESS;
539	}
540	Assert(pVCpu->dbgf.s.aEvents[i].enmState != DBGFEVENTSTATE_CURRENT);
541	}
542
543	/*
544	* Trim the event stack.
545	*/
546	i = pVCpu->dbgf.s.cEvents;
547	while (i-- > 0)
548	{
549	if ( pVCpu->dbgf.s.aEvents[i].rip == rip
550	&& ( pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_RESTORABLE
551	\|\| pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE) )
552	pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_IGNORE;
553	else
554	{
555	if (i + 1 != pVCpu->dbgf.s.cEvents)
556	memmove(&pVCpu->dbgf.s.aEvents[i], &pVCpu->dbgf.s.aEvents[i + 1],
557	(pVCpu->dbgf.s.cEvents - i) * sizeof(pVCpu->dbgf.s.aEvents));
558	pVCpu->dbgf.s.cEvents--;
559	}
560	}
561
562	i = pVCpu->dbgf.s.cEvents;
563	AssertStmt(i < RT_ELEMENTS(pVCpu->dbgf.s.aEvents), i = RT_ELEMENTS(pVCpu->dbgf.s.aEvents) - 1);
564	}
565
566	/*
567	* Push the event.
568	*/
569	pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_CURRENT;
570	pVCpu->dbgf.s.aEvents[i].rip = rip;
571	pVCpu->dbgf.s.aEvents[i].Event.enmType = enmEvent;
572	pVCpu->dbgf.s.aEvents[i].Event.enmCtx = enmCtx;
573	pVCpu->dbgf.s.aEvents[i].Event.u.Generic.cArgs = cArgs;
574	pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[0] = uEventArg0;
575	if (cArgs > 1)
576	{
577	AssertStmt(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs),
578	cArgs = RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs));
579	for (unsigned iArg = 1; iArg < cArgs; iArg++)
580	pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[iArg] = va_arg(va, uint64_t);
581	}
582	pVCpu->dbgf.s.cEvents = i + 1;
583
584	VMCPU_FF_SET(pVCpu, VMCPU_FF_DBGF);
585	va_end(va);
586	return VINF_EM_DBG_EVENT;
587	}
588
589	va_end(va);
590	return VINF_SUCCESS;
591	}
592

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp@ 98029

Download in other formats: