VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp@ 87778

Last change on this file since 87778 was 87594, checked in by vboxsync, 4 years ago

VMM/DBGF,Debugger: Removed the !defined(VBOX_WITH_LOTS_OF_DBGF_BPS) code. bugref:9837
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File size: 14.2 KB
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1/* $Id: DBGFAll.cpp 87594 2021-02-03 20:23:46Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, All Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/dbgf.h>
24#include "DBGFInternal.h"
25#include <VBox/vmm/vmcc.h>
26#include <VBox/err.h>
27#include <iprt/assert.h>
28#include <iprt/asm.h>
29#include <iprt/stdarg.h>
30
31
32/*
33 * Check the read-only VM members.
34 */
35AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
36AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
37AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
38AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
39AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
40AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
41
42
43/**
44 * Gets the hardware breakpoint configuration as DR7.
45 *
46 * @returns DR7 from the DBGF point of view.
47 * @param pVM The cross context VM structure.
48 */
49VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
50{
51 RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
52 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); i++)
53 {
54 if ( pVM->dbgf.s.aHwBreakpoints[i].fEnabled
55 && pVM->dbgf.s.aHwBreakpoints[i].hBp != NIL_DBGFBP)
56 {
57 static const uint8_t s_au8Sizes[8] =
58 {
59 X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
60 X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
61 };
62 uDr7 |= X86_DR7_G(i)
63 | X86_DR7_RW(i, pVM->dbgf.s.aHwBreakpoints[i].fType)
64 | X86_DR7_LEN(i, s_au8Sizes[pVM->dbgf.s.aHwBreakpoints[i].cb]);
65 }
66 }
67 return uDr7;
68}
69
70
71/**
72 * Gets the address of the hardware breakpoint number 0.
73 *
74 * @returns DR0 from the DBGF point of view.
75 * @param pVM The cross context VM structure.
76 */
77VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
78{
79 return pVM->dbgf.s.aHwBreakpoints[0].GCPtr;
80}
81
82
83/**
84 * Gets the address of the hardware breakpoint number 1.
85 *
86 * @returns DR1 from the DBGF point of view.
87 * @param pVM The cross context VM structure.
88 */
89VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
90{
91 return pVM->dbgf.s.aHwBreakpoints[1].GCPtr;
92}
93
94
95/**
96 * Gets the address of the hardware breakpoint number 2.
97 *
98 * @returns DR2 from the DBGF point of view.
99 * @param pVM The cross context VM structure.
100 */
101VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
102{
103 return pVM->dbgf.s.aHwBreakpoints[2].GCPtr;
104}
105
106
107/**
108 * Gets the address of the hardware breakpoint number 3.
109 *
110 * @returns DR3 from the DBGF point of view.
111 * @param pVM The cross context VM structure.
112 */
113VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
114{
115 return pVM->dbgf.s.aHwBreakpoints[3].GCPtr;
116}
117
118
119/**
120 * Checks if any of the hardware breakpoints are armed.
121 *
122 * @returns true if armed, false if not.
123 * @param pVM The cross context VM structure.
124 * @remarks Don't call this from CPUMRecalcHyperDRx!
125 */
126VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
127{
128 return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
129}
130
131
132/**
133 * Checks if any of the hardware I/O breakpoints are armed.
134 *
135 * @returns true if armed, false if not.
136 * @param pVM The cross context VM structure.
137 * @remarks Don't call this from CPUMRecalcHyperDRx!
138 */
139VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
140{
141 return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
142}
143
144
145/**
146 * Checks if any INT3 breakpoints are armed.
147 *
148 * @returns true if armed, false if not.
149 * @param pVM The cross context VM structure.
150 * @remarks Don't call this from CPUMRecalcHyperDRx!
151 */
152VMM_INT_DECL(bool) DBGFBpIsInt3Armed(PVM pVM)
153{
154 /** @todo There was a todo here and returning false when I (bird) removed
155 * VBOX_WITH_LOTS_OF_DBGF_BPS, so this might not be correct. */
156 return pVM->dbgf.s.cEnabledInt3Breakpoints > 0;
157}
158
159
160/**
161 * Checks I/O access for guest or hypervisor breakpoints.
162 *
163 * @returns Strict VBox status code
164 * @retval VINF_SUCCESS no breakpoint.
165 * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
166 * @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
167 * been updated appropriately.
168 *
169 * @param pVM The cross context VM structure.
170 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
171 * @param pCtx The CPU context for the calling EMT.
172 * @param uIoPort The I/O port being accessed.
173 * @param cbValue The size/width of the access, in bytes.
174 */
175VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
176{
177 uint32_t const uIoPortFirst = uIoPort;
178 uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
179
180 /*
181 * Check hyper breakpoints first as the VMM debugger has priority over
182 * the guest.
183 */
184 if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
185 {
186 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
187 {
188 if ( pVM->dbgf.s.aHwBreakpoints[iBp].fType == X86_DR7_RW_IO
189 && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
190 && pVM->dbgf.s.aHwBreakpoints[iBp].hBp == NIL_DBGFBP) /** @todo r=bird: this cannot be right... */
191 {
192 uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
193 uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
194 uint64_t uDrXLast = uDrXFirst + cbReg - 1;
195 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
196 {
197 /* (See also DBGFRZTrap01Handler.) */
198 pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
199 pVCpu->dbgf.s.fSingleSteppingRaw = false;
200
201 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
202 iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
203 return VINF_EM_DBG_BREAKPOINT;
204 }
205 }
206 }
207 }
208
209 /*
210 * Check the guest.
211 */
212 uint32_t const uDr7 = pCtx->dr[7];
213 if ( (uDr7 & X86_DR7_ENABLED_MASK)
214 && X86_DR7_ANY_RW_IO(uDr7)
215 && (pCtx->cr4 & X86_CR4_DE) )
216 {
217 for (unsigned iBp = 0; iBp < 4; iBp++)
218 {
219 if ( (uDr7 & X86_DR7_L_G(iBp))
220 && X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
221 {
222 /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
223 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
224 uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
225 uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
226 uint64_t uDrXLast = uDrXFirst + cbInvAlign;
227
228 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
229 {
230 /*
231 * Update DR6 and DR7.
232 *
233 * See "AMD64 Architecture Programmer's Manual Volume 2",
234 * chapter 13.1.1.3 for details on DR6 bits. The basics is
235 * that the B0..B3 bits are always cleared while the others
236 * must be cleared by software.
237 *
238 * The following sub chapters says the GD bit is always
239 * cleared when generating a #DB so the handler can safely
240 * access the debug registers.
241 */
242 pCtx->dr[6] &= ~X86_DR6_B_MASK;
243 pCtx->dr[6] |= X86_DR6_B(iBp);
244 pCtx->dr[7] &= ~X86_DR7_GD;
245 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
246 iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
247 return VINF_EM_RAW_GUEST_TRAP;
248 }
249 }
250 }
251 }
252 return VINF_SUCCESS;
253}
254
255
256/**
257 * Returns the single stepping state for a virtual CPU.
258 *
259 * @returns stepping (true) or not (false).
260 *
261 * @param pVCpu The cross context virtual CPU structure.
262 */
263VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
264{
265 return pVCpu->dbgf.s.fSingleSteppingRaw;
266}
267
268
269/**
270 * Checks if the specified generic event is enabled or not.
271 *
272 * @returns true / false.
273 * @param pVM The cross context VM structure.
274 * @param enmEvent The generic event being raised.
275 * @param uEventArg The argument of that event.
276 */
277DECLINLINE(bool) dbgfEventIsGenericWithArgEnabled(PVM pVM, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
278{
279 if (DBGF_IS_EVENT_ENABLED(pVM, enmEvent))
280 {
281 switch (enmEvent)
282 {
283 case DBGFEVENT_INTERRUPT_HARDWARE:
284 AssertReturn(uEventArg < 256, false);
285 return ASMBitTest(pVM->dbgf.s.bmHardIntBreakpoints, (uint32_t)uEventArg);
286
287 case DBGFEVENT_INTERRUPT_SOFTWARE:
288 AssertReturn(uEventArg < 256, false);
289 return ASMBitTest(pVM->dbgf.s.bmSoftIntBreakpoints, (uint32_t)uEventArg);
290
291 default:
292 return true;
293
294 }
295 }
296 return false;
297}
298
299
300/**
301 * Raises a generic debug event if enabled and not being ignored.
302 *
303 * @returns Strict VBox status code.
304 * @retval VINF_EM_DBG_EVENT if the event was raised and the caller should
305 * return ASAP to the debugger (via EM). We set VMCPU_FF_DBGF so, it
306 * is okay not to pass this along in some situations.
307 * @retval VINF_SUCCESS if the event was disabled or ignored.
308 *
309 * @param pVM The cross context VM structure.
310 * @param pVCpu The cross context virtual CPU structure.
311 * @param enmEvent The generic event being raised.
312 * @param enmCtx The context in which this event is being raised.
313 * @param cArgs Number of arguments (0 - 6).
314 * @param ... Event arguments.
315 *
316 * @thread EMT(pVCpu)
317 */
318VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArgs(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, DBGFEVENTCTX enmCtx,
319 unsigned cArgs, ...)
320{
321 Assert(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[0].Event.u.Generic.auArgs));
322
323 /*
324 * Is it enabled.
325 */
326 va_list va;
327 va_start(va, cArgs);
328 uint64_t uEventArg0 = cArgs ? va_arg(va, uint64_t) : 0;
329 if (dbgfEventIsGenericWithArgEnabled(pVM, enmEvent, uEventArg0))
330 {
331 /*
332 * Any events on the stack. Should the incoming event be ignored?
333 */
334 uint64_t const rip = CPUMGetGuestRIP(pVCpu);
335 uint32_t i = pVCpu->dbgf.s.cEvents;
336 if (i > 0)
337 {
338 while (i-- > 0)
339 {
340 if ( pVCpu->dbgf.s.aEvents[i].Event.enmType == enmEvent
341 && pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE
342 && pVCpu->dbgf.s.aEvents[i].rip == rip)
343 {
344 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_RESTORABLE;
345 va_end(va);
346 return VINF_SUCCESS;
347 }
348 Assert(pVCpu->dbgf.s.aEvents[i].enmState != DBGFEVENTSTATE_CURRENT);
349 }
350
351 /*
352 * Trim the event stack.
353 */
354 i = pVCpu->dbgf.s.cEvents;
355 while (i-- > 0)
356 {
357 if ( pVCpu->dbgf.s.aEvents[i].rip == rip
358 && ( pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_RESTORABLE
359 || pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE) )
360 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_IGNORE;
361 else
362 {
363 if (i + 1 != pVCpu->dbgf.s.cEvents)
364 memmove(&pVCpu->dbgf.s.aEvents[i], &pVCpu->dbgf.s.aEvents[i + 1],
365 (pVCpu->dbgf.s.cEvents - i) * sizeof(pVCpu->dbgf.s.aEvents));
366 pVCpu->dbgf.s.cEvents--;
367 }
368 }
369
370 i = pVCpu->dbgf.s.cEvents;
371 AssertStmt(i < RT_ELEMENTS(pVCpu->dbgf.s.aEvents), i = RT_ELEMENTS(pVCpu->dbgf.s.aEvents) - 1);
372 }
373
374 /*
375 * Push the event.
376 */
377 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_CURRENT;
378 pVCpu->dbgf.s.aEvents[i].rip = rip;
379 pVCpu->dbgf.s.aEvents[i].Event.enmType = enmEvent;
380 pVCpu->dbgf.s.aEvents[i].Event.enmCtx = enmCtx;
381 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.cArgs = cArgs;
382 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[0] = uEventArg0;
383 if (cArgs > 1)
384 {
385 AssertStmt(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs),
386 cArgs = RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs));
387 for (unsigned iArg = 1; iArg < cArgs; iArg++)
388 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[iArg] = va_arg(va, uint64_t);
389 }
390 pVCpu->dbgf.s.cEvents = i + 1;
391
392 VMCPU_FF_SET(pVCpu, VMCPU_FF_DBGF);
393 va_end(va);
394 return VINF_EM_DBG_EVENT;
395 }
396
397 va_end(va);
398 return VINF_SUCCESS;
399}
400
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