VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp@ 58998

Last change on this file since 58998 was 58998, checked in by vboxsync, 9 years ago

HM: Implemented 69 new dtrace probes and DBGF events in the VT-x code.
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File size: 9.3 KB
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1/* $Id: DBGFAll.cpp 58998 2015-12-04 17:09:04Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, All Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/dbgf.h>
24#include "DBGFInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/err.h>
27#include <iprt/assert.h>
28
29
30/*
31 * Check the read-only VM members.
32 */
33AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
34AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
35AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
36AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
37AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
38AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
39
40
41/**
42 * Gets the hardware breakpoint configuration as DR7.
43 *
44 * @returns DR7 from the DBGF point of view.
45 * @param pVM The cross context VM structure.
46 */
47VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
48{
49 RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
50 PDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
51 unsigned cLeft = RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints);
52 while (cLeft-- > 0)
53 {
54 if ( pBp->enmType == DBGFBPTYPE_REG
55 && pBp->fEnabled)
56 {
57 static const uint8_t s_au8Sizes[8] =
58 {
59 X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
60 X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
61 };
62 uDr7 |= X86_DR7_G(pBp->u.Reg.iReg)
63 | X86_DR7_RW(pBp->u.Reg.iReg, pBp->u.Reg.fType)
64 | X86_DR7_LEN(pBp->u.Reg.iReg, s_au8Sizes[pBp->u.Reg.cb]);
65 }
66 pBp++;
67 }
68 return uDr7;
69}
70
71
72/**
73 * Gets the address of the hardware breakpoint number 0.
74 *
75 * @returns DR0 from the DBGF point of view.
76 * @param pVM The cross context VM structure.
77 */
78VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
79{
80 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
81 Assert(pBp->u.Reg.iReg == 0);
82 return pBp->u.Reg.GCPtr;
83}
84
85
86/**
87 * Gets the address of the hardware breakpoint number 1.
88 *
89 * @returns DR1 from the DBGF point of view.
90 * @param pVM The cross context VM structure.
91 */
92VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
93{
94 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[1];
95 Assert(pBp->u.Reg.iReg == 1);
96 return pBp->u.Reg.GCPtr;
97}
98
99
100/**
101 * Gets the address of the hardware breakpoint number 2.
102 *
103 * @returns DR2 from the DBGF point of view.
104 * @param pVM The cross context VM structure.
105 */
106VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
107{
108 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[2];
109 Assert(pBp->u.Reg.iReg == 2);
110 return pBp->u.Reg.GCPtr;
111}
112
113
114/**
115 * Gets the address of the hardware breakpoint number 3.
116 *
117 * @returns DR3 from the DBGF point of view.
118 * @param pVM The cross context VM structure.
119 */
120VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
121{
122 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[3];
123 Assert(pBp->u.Reg.iReg == 3);
124 return pBp->u.Reg.GCPtr;
125}
126
127
128/**
129 * Checks if any of the hardware breakpoints are armed.
130 *
131 * @returns true if armed, false if not.
132 * @param pVM The cross context VM structure.
133 * @remarks Don't call this from CPUMRecalcHyperDRx!
134 */
135VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
136{
137 return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
138}
139
140
141/**
142 * Checks if any of the hardware I/O breakpoints are armed.
143 *
144 * @returns true if armed, false if not.
145 * @param pVM The cross context VM structure.
146 * @remarks Don't call this from CPUMRecalcHyperDRx!
147 */
148VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
149{
150 return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
151}
152
153
154/**
155 * Checks I/O access for guest or hypervisor breakpoints.
156 *
157 * @returns Strict VBox status code
158 * @retval VINF_SUCCESS no breakpoint.
159 * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
160 * @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
161 * been updated appropriately.
162 *
163 * @param pVM The cross context VM structure.
164 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
165 * @param pCtx The CPU context for the calling EMT.
166 * @param uIoPort The I/O port being accessed.
167 * @param cbValue The size/width of the access, in bytes.
168 */
169VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
170{
171 uint32_t const uIoPortFirst = uIoPort;
172 uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
173
174
175 /*
176 * Check hyper breakpoints first as the VMM debugger has priority over
177 * the guest.
178 */
179 if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
180 {
181 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
182 {
183 if ( pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.fType == X86_DR7_RW_IO
184 && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
185 && pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG )
186 {
187 uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
188 uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.GCPtr & ~(uint64_t)(cbReg - 1);
189 uint64_t uDrXLast = uDrXFirst + cbReg - 1;
190 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
191 {
192 /* (See also DBGFRZTrap01Handler.) */
193 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
194 pVCpu->dbgf.s.fSingleSteppingRaw = false;
195
196 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
197 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
198 return VINF_EM_DBG_BREAKPOINT;
199 }
200 }
201 }
202 }
203
204 /*
205 * Check the guest.
206 */
207 uint32_t const uDr7 = pCtx->dr[7];
208 if ( (uDr7 & X86_DR7_ENABLED_MASK)
209 && X86_DR7_ANY_RW_IO(uDr7)
210 && (pCtx->cr4 & X86_CR4_DE) )
211 {
212 for (unsigned iBp = 0; iBp < 4; iBp++)
213 {
214 if ( (uDr7 & X86_DR7_L_G(iBp))
215 && X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
216 {
217 /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
218 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
219 uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
220 uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
221 uint64_t uDrXLast = uDrXFirst + cbInvAlign;
222
223 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
224 {
225 /*
226 * Update DR6 and DR7.
227 *
228 * See "AMD64 Architecture Programmer's Manual Volume 2",
229 * chapter 13.1.1.3 for details on DR6 bits. The basics is
230 * that the B0..B3 bits are always cleared while the others
231 * must be cleared by software.
232 *
233 * The following sub chapters says the GD bit is always
234 * cleared when generating a #DB so the handler can safely
235 * access the debug registers.
236 */
237 pCtx->dr[6] &= ~X86_DR6_B_MASK;
238 pCtx->dr[6] |= X86_DR6_B(iBp);
239 pCtx->dr[7] &= ~X86_DR7_GD;
240 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
241 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
242 return VINF_EM_RAW_GUEST_TRAP;
243 }
244 }
245 }
246 }
247 return VINF_SUCCESS;
248}
249
250
251/**
252 * Returns the single stepping state for a virtual CPU.
253 *
254 * @returns stepping (true) or not (false).
255 *
256 * @param pVCpu The cross context virtual CPU structure.
257 */
258VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
259{
260 return pVCpu->dbgf.s.fSingleSteppingRaw;
261}
262
263
264VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArg(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
265{
266 return VINF_SUCCESS;
267}
268
269
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