1 | /* $Id: DBGFAll.cpp 62478 2016-07-22 18:29:06Z vboxsync $ */
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2 | /** @file
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3 | * DBGF - Debugger Facility, All Context Code.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2016 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | /*********************************************************************************************************************************
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20 | * Header Files *
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21 | *********************************************************************************************************************************/
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22 | #define LOG_GROUP LOG_GROUP_DBGF
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23 | #include <VBox/vmm/dbgf.h>
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24 | #include "DBGFInternal.h"
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25 | #include <VBox/vmm/vm.h>
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26 | #include <VBox/err.h>
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27 | #include <iprt/assert.h>
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28 | #include <iprt/asm.h>
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29 |
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30 |
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31 | /*
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32 | * Check the read-only VM members.
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33 | */
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34 | AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
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35 | AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
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36 | AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
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37 | AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
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38 | AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
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39 | AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
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40 |
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41 |
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42 | /**
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43 | * Gets the hardware breakpoint configuration as DR7.
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44 | *
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45 | * @returns DR7 from the DBGF point of view.
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46 | * @param pVM The cross context VM structure.
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47 | */
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48 | VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
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49 | {
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50 | RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
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51 | PDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
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52 | unsigned cLeft = RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints);
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53 | while (cLeft-- > 0)
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54 | {
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55 | if ( pBp->enmType == DBGFBPTYPE_REG
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56 | && pBp->fEnabled)
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57 | {
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58 | static const uint8_t s_au8Sizes[8] =
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59 | {
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60 | X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
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61 | X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
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62 | };
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63 | uDr7 |= X86_DR7_G(pBp->u.Reg.iReg)
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64 | | X86_DR7_RW(pBp->u.Reg.iReg, pBp->u.Reg.fType)
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65 | | X86_DR7_LEN(pBp->u.Reg.iReg, s_au8Sizes[pBp->u.Reg.cb]);
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66 | }
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67 | pBp++;
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68 | }
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69 | return uDr7;
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70 | }
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71 |
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72 |
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73 | /**
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74 | * Gets the address of the hardware breakpoint number 0.
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75 | *
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76 | * @returns DR0 from the DBGF point of view.
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77 | * @param pVM The cross context VM structure.
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78 | */
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79 | VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
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80 | {
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81 | PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
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82 | Assert(pBp->u.Reg.iReg == 0);
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83 | return pBp->u.Reg.GCPtr;
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84 | }
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85 |
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86 |
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87 | /**
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88 | * Gets the address of the hardware breakpoint number 1.
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89 | *
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90 | * @returns DR1 from the DBGF point of view.
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91 | * @param pVM The cross context VM structure.
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92 | */
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93 | VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
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94 | {
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95 | PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[1];
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96 | Assert(pBp->u.Reg.iReg == 1);
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97 | return pBp->u.Reg.GCPtr;
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98 | }
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99 |
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100 |
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101 | /**
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102 | * Gets the address of the hardware breakpoint number 2.
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103 | *
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104 | * @returns DR2 from the DBGF point of view.
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105 | * @param pVM The cross context VM structure.
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106 | */
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107 | VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
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108 | {
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109 | PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[2];
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110 | Assert(pBp->u.Reg.iReg == 2);
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111 | return pBp->u.Reg.GCPtr;
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112 | }
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113 |
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114 |
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115 | /**
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116 | * Gets the address of the hardware breakpoint number 3.
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117 | *
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118 | * @returns DR3 from the DBGF point of view.
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119 | * @param pVM The cross context VM structure.
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120 | */
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121 | VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
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122 | {
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123 | PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[3];
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124 | Assert(pBp->u.Reg.iReg == 3);
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125 | return pBp->u.Reg.GCPtr;
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126 | }
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127 |
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128 |
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129 | /**
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130 | * Checks if any of the hardware breakpoints are armed.
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131 | *
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132 | * @returns true if armed, false if not.
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133 | * @param pVM The cross context VM structure.
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134 | * @remarks Don't call this from CPUMRecalcHyperDRx!
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135 | */
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136 | VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
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137 | {
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138 | return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
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139 | }
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140 |
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141 |
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142 | /**
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143 | * Checks if any of the hardware I/O breakpoints are armed.
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144 | *
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145 | * @returns true if armed, false if not.
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146 | * @param pVM The cross context VM structure.
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147 | * @remarks Don't call this from CPUMRecalcHyperDRx!
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148 | */
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149 | VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
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150 | {
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151 | return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
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152 | }
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153 |
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154 |
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155 | /**
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156 | * Checks I/O access for guest or hypervisor breakpoints.
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157 | *
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158 | * @returns Strict VBox status code
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159 | * @retval VINF_SUCCESS no breakpoint.
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160 | * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
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161 | * @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
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162 | * been updated appropriately.
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163 | *
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164 | * @param pVM The cross context VM structure.
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165 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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166 | * @param pCtx The CPU context for the calling EMT.
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167 | * @param uIoPort The I/O port being accessed.
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168 | * @param cbValue The size/width of the access, in bytes.
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169 | */
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170 | VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
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171 | {
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172 | uint32_t const uIoPortFirst = uIoPort;
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173 | uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
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174 |
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175 |
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176 | /*
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177 | * Check hyper breakpoints first as the VMM debugger has priority over
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178 | * the guest.
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179 | */
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180 | if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
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181 | {
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182 | for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
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183 | {
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184 | if ( pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.fType == X86_DR7_RW_IO
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185 | && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
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186 | && pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG )
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187 | {
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188 | uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
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189 | uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.GCPtr & ~(uint64_t)(cbReg - 1);
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190 | uint64_t uDrXLast = uDrXFirst + cbReg - 1;
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191 | if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
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192 | {
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193 | /* (See also DBGFRZTrap01Handler.) */
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194 | pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
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195 | pVCpu->dbgf.s.fSingleSteppingRaw = false;
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196 |
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197 | LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
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198 | pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
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199 | return VINF_EM_DBG_BREAKPOINT;
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200 | }
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201 | }
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202 | }
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203 | }
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204 |
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205 | /*
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206 | * Check the guest.
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207 | */
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208 | uint32_t const uDr7 = pCtx->dr[7];
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209 | if ( (uDr7 & X86_DR7_ENABLED_MASK)
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210 | && X86_DR7_ANY_RW_IO(uDr7)
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211 | && (pCtx->cr4 & X86_CR4_DE) )
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212 | {
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213 | for (unsigned iBp = 0; iBp < 4; iBp++)
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214 | {
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215 | if ( (uDr7 & X86_DR7_L_G(iBp))
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216 | && X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
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217 | {
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218 | /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
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219 | static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
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220 | uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
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221 | uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
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222 | uint64_t uDrXLast = uDrXFirst + cbInvAlign;
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223 |
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224 | if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
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225 | {
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226 | /*
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227 | * Update DR6 and DR7.
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228 | *
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229 | * See "AMD64 Architecture Programmer's Manual Volume 2",
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230 | * chapter 13.1.1.3 for details on DR6 bits. The basics is
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231 | * that the B0..B3 bits are always cleared while the others
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232 | * must be cleared by software.
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233 | *
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234 | * The following sub chapters says the GD bit is always
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235 | * cleared when generating a #DB so the handler can safely
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236 | * access the debug registers.
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237 | */
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238 | pCtx->dr[6] &= ~X86_DR6_B_MASK;
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239 | pCtx->dr[6] |= X86_DR6_B(iBp);
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240 | pCtx->dr[7] &= ~X86_DR7_GD;
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241 | LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
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242 | pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
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243 | return VINF_EM_RAW_GUEST_TRAP;
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244 | }
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245 | }
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246 | }
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247 | }
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248 | return VINF_SUCCESS;
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249 | }
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250 |
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251 |
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252 | /**
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253 | * Returns the single stepping state for a virtual CPU.
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254 | *
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255 | * @returns stepping (true) or not (false).
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256 | *
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257 | * @param pVCpu The cross context virtual CPU structure.
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258 | */
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259 | VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
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260 | {
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261 | return pVCpu->dbgf.s.fSingleSteppingRaw;
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262 | }
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263 |
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264 |
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265 | /**
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266 | * Checks if the specified generic event is enabled or not.
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267 | *
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268 | * @returns true / false.
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269 | * @param pVM The cross context VM structure.
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270 | * @param enmEvent The generic event being raised.
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271 | * @param uEventArg The argument of that event.
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272 | */
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273 | DECLINLINE(bool) dbgfEventIsGenericWithArgEnabled(PVM pVM, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
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274 | {
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275 | if (DBGF_IS_EVENT_ENABLED(pVM, enmEvent))
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276 | {
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277 | switch (enmEvent)
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278 | {
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279 | case DBGFEVENT_INTERRUPT_HARDWARE:
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280 | AssertReturn(uEventArg < 256, false);
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281 | return ASMBitTest(pVM->dbgf.s.bmHardIntBreakpoints, (uint32_t)uEventArg);
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282 |
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283 | case DBGFEVENT_INTERRUPT_SOFTWARE:
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284 | AssertReturn(uEventArg < 256, false);
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285 | return ASMBitTest(pVM->dbgf.s.bmSoftIntBreakpoints, (uint32_t)uEventArg);
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286 |
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287 | default:
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288 | return true;
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289 |
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290 | }
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291 | }
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292 | return false;
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293 | }
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294 |
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295 |
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296 | /**
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297 | * Raises a generic debug event if enabled and not being ignored.
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298 | *
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299 | * @returns Strict VBox status code.
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300 | * @retval VINF_EM_DBG_EVENT if the event was raised and the caller should
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301 | * return ASAP to the debugger (via EM). We set VMCPU_FF_DBGF so, it
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302 | * is okay not to pass this along in some situations .
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303 | * @retval VINF_SUCCESS if the event was disabled or ignored.
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304 | *
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305 | * @param pVM The cross context VM structure.
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306 | * @param pVCpu The cross context virtual CPU structure.
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307 | * @param enmEvent The generic event being raised.
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308 | * @param uEventArg The argument of that event.
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309 | * @param enmCtx The context in which this event is being raised.
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310 | *
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311 | * @thread EMT(pVCpu)
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312 | */
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313 | VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArg(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, uint64_t uEventArg,
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314 | DBGFEVENTCTX enmCtx)
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315 | {
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316 | /*
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317 | * Is it enabled.
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318 | */
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319 | if (dbgfEventIsGenericWithArgEnabled(pVM, enmEvent, uEventArg))
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320 | {
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321 | /*
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322 | * Any events on the stack. Should the incoming event be ignored?
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323 | */
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324 | uint64_t const rip = CPUMGetGuestRIP(pVCpu);
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325 | uint32_t i = pVCpu->dbgf.s.cEvents;
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326 | if (i > 0)
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327 | {
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328 | while (i-- > 0)
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329 | {
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330 | if ( pVCpu->dbgf.s.aEvents[i].Event.enmType == enmEvent
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331 | && pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE
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332 | && pVCpu->dbgf.s.aEvents[i].rip == rip)
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333 | {
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334 | pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_RESTORABLE;
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335 | return VINF_SUCCESS;
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336 | }
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337 | Assert(pVCpu->dbgf.s.aEvents[i].enmState != DBGFEVENTSTATE_CURRENT);
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338 | }
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339 |
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340 | /*
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341 | * Trim the event stack.
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342 | */
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343 | i = pVCpu->dbgf.s.cEvents;
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344 | while (i-- > 0)
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345 | {
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346 | if ( pVCpu->dbgf.s.aEvents[i].rip == rip
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347 | && ( pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_RESTORABLE
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348 | || pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE) )
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349 | pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_IGNORE;
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350 | else
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351 | {
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352 | if (i + 1 != pVCpu->dbgf.s.cEvents)
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353 | memmove(&pVCpu->dbgf.s.aEvents[i], &pVCpu->dbgf.s.aEvents[i + 1],
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354 | (pVCpu->dbgf.s.cEvents - i) * sizeof(pVCpu->dbgf.s.aEvents));
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355 | pVCpu->dbgf.s.cEvents--;
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356 | }
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357 | }
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358 |
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359 | i = pVCpu->dbgf.s.cEvents;
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360 | AssertStmt(i < RT_ELEMENTS(pVCpu->dbgf.s.aEvents), i = RT_ELEMENTS(pVCpu->dbgf.s.aEvents) - 1);
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361 | }
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362 |
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363 | /*
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364 | * Push the event.
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365 | */
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366 | pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_CURRENT;
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367 | pVCpu->dbgf.s.aEvents[i].rip = rip;
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368 | pVCpu->dbgf.s.aEvents[i].Event.enmType = enmEvent;
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369 | pVCpu->dbgf.s.aEvents[i].Event.enmCtx = enmCtx;
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370 | pVCpu->dbgf.s.aEvents[i].Event.u.Generic.uArg = uEventArg;
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371 | pVCpu->dbgf.s.cEvents = i + 1;
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372 |
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373 | VMCPU_FF_SET(pVCpu, VMCPU_FF_DBGF);
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374 | return VINF_EM_DBG_EVENT;
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375 | }
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376 |
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377 | return VINF_SUCCESS;
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378 | }
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379 |
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