1 | /* $Id: CPUMAllSysRegs-armv8.cpp 107031 2024-11-18 15:00:29Z vboxsync $ */
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2 | /** @file
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3 | * CPUM - ARMv8 CPU System Registers.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2023-2024 Oracle and/or its affiliates.
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8 | *
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9 | * This file is part of VirtualBox base platform packages, as
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10 | * available from https://www.virtualbox.org.
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11 | *
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12 | * This program is free software; you can redistribute it and/or
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13 | * modify it under the terms of the GNU General Public License
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14 | * as published by the Free Software Foundation, in version 3 of the
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15 | * License.
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16 | *
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17 | * This program is distributed in the hope that it will be useful, but
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18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | * General Public License for more details.
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21 | *
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22 | * You should have received a copy of the GNU General Public License
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23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | *
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25 | * SPDX-License-Identifier: GPL-3.0-only
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26 | */
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27 |
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28 |
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29 | /*********************************************************************************************************************************
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30 | * Header Files *
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31 | *********************************************************************************************************************************/
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32 | #define LOG_GROUP LOG_GROUP_CPUM
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33 | #include <VBox/vmm/cpum.h>
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34 | #include "CPUMInternal-armv8.h"
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35 | #include <VBox/vmm/gic.h>
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36 | #include <VBox/vmm/pmu.h>
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37 | #include <VBox/vmm/vmcc.h>
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38 | #include <VBox/err.h>
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39 |
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40 | #include <iprt/armv8.h>
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41 |
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42 |
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43 | /*********************************************************************************************************************************
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44 | * Defined Constants And Macros *
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45 | *********************************************************************************************************************************/
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46 | /**
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47 | * Validates the CPUMSYSREGRANGE::offCpumCpu value and declares a local variable
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48 | * pointing to it.
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49 | *
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50 | * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
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51 | * correctly.
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52 | */
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53 | #define CPUM_SYSREG_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
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54 | AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
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55 | && (a_pRange)->offCpumCpu < sizeof(CPUMCTX) \
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56 | && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
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57 | , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
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58 | VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
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59 | a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s.Guest + (a_pRange)->offCpumCpu)
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60 |
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61 |
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62 | /*********************************************************************************************************************************
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63 | * Structures and Typedefs *
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64 | *********************************************************************************************************************************/
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65 |
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66 | /**
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67 | * Implements reading one or more system registers.
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68 | *
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69 | * @returns VBox status code.
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70 | * @retval VINF_SUCCESS on success.
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71 | * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
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72 | * current context (raw-mode or ring-0).
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73 | * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid system register).
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74 | *
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75 | * @param pVCpu The cross context virtual CPU structure.
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76 | * @param idSysReg The system register we're reading.
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77 | * @param pRange The system register range descriptor.
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78 | * @param puValue Where to return the value.
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79 | */
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80 | typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMRDSYSREG,(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue));
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81 | /** Pointer to a MRS worker for a specific system register or range of system registers. */
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82 | typedef FNCPUMRDSYSREG *PFNCPUMRDSYSREG;
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83 |
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84 |
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85 | /**
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86 | * Implements writing one or more system registers.
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87 | *
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88 | * @retval VINF_SUCCESS on success.
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89 | * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
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90 | * current context (raw-mode or ring-0).
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91 | * @retval VERR_CPUM_RAISE_GP_0 on failure.
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92 | *
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93 | * @param pVCpu The cross context virtual CPU structure.
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94 | * @param idSysReg The system register we're writing.
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95 | * @param pRange The system register range descriptor.
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96 | * @param uValue The value to set, ignored bits masked.
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97 | * @param uRawValue The raw value with the ignored bits not masked.
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98 | */
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99 | typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMWRSYSREG,(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange,
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100 | uint64_t uValue, uint64_t uRawValue));
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101 | /** Pointer to a MSR worker for a specific system register or range of system registers. */
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102 | typedef FNCPUMWRSYSREG *PFNCPUMWRSYSREG;
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103 |
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104 |
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105 |
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106 | /*
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107 | * Generic functions.
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108 | * Generic functions.
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109 | * Generic functions.
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110 | */
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111 |
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112 |
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113 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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114 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_FixedValue(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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115 | {
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116 | RT_NOREF_PV(pVCpu); RT_NOREF_PV(idSysReg);
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117 | *puValue = pRange->uValue;
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118 | return VINF_SUCCESS;
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119 | }
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120 |
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121 |
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122 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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123 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_IgnoreWrite(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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124 | {
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125 | RT_NOREF_PV(pVCpu); RT_NOREF_PV(idSysReg); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
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126 | Log(("CPUM: Ignoring MSR %#x (%s), %#llx\n", idSysReg, pRange->szName, uValue));
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127 | return VINF_SUCCESS;
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128 | }
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129 |
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130 |
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131 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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132 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_WriteOnly(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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133 | {
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134 | RT_NOREF_PV(pVCpu); RT_NOREF_PV(idSysReg); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
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135 | return VERR_CPUM_RAISE_GP_0;
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136 | }
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137 |
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138 |
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139 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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140 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_ReadOnly(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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141 | {
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142 | RT_NOREF_PV(pVCpu); RT_NOREF_PV(idSysReg); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
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143 | Assert(pRange->fWrExcpMask == UINT64_MAX);
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144 | return VERR_CPUM_RAISE_GP_0;
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145 | }
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146 |
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147 |
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148 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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149 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_ReadCpumOff(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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150 | {
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151 | RT_NOREF(idSysReg);
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152 |
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153 | CPUM_SYSREG_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, CPUMCTXSYSREG, pSysReg);
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154 | *puValue = pSysReg->u64;
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155 | return VINF_SUCCESS;
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156 | }
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157 |
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158 |
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159 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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160 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_WriteCpumOff(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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161 | {
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162 | RT_NOREF(idSysReg, uRawValue);
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163 |
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164 | CPUM_SYSREG_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, CPUMCTXSYSREG, pSysReg);
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165 | pSysReg->u64 = uValue;
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166 | return VINF_SUCCESS;
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167 | }
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168 |
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169 |
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170 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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171 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_GicV3Icc(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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172 | {
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173 | RT_NOREF_PV(pRange);
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174 | return GICReadSysReg(pVCpu, idSysReg, puValue);
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175 | }
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176 |
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177 |
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178 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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179 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_GicV3Icc(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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180 | {
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181 | RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
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182 | return GICWriteSysReg(pVCpu, idSysReg, uValue);
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183 | }
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184 |
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185 |
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186 |
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187 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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188 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_OslsrEl1(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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189 | {
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190 | RT_NOREF(idSysReg, pRange);
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191 | *puValue = pVCpu->cpum.s.Guest.fOsLck ? ARMV8_OSLSR_EL1_AARCH64_OSLK : 0;
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192 | return VINF_SUCCESS;
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193 | }
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194 |
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195 |
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196 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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197 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_OslarEl1(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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198 | {
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199 | RT_NOREF(idSysReg, pRange, uRawValue);
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200 | Assert(!(uValue & ~ARMV8_OSLAR_EL1_AARCH64_OSLK));
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201 | pVCpu->cpum.s.Guest.fOsLck = RT_BOOL(uValue);
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202 | return VINF_SUCCESS;
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203 | }
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204 |
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205 |
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206 |
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207 | /** @callback_method_impl{FNCPUMRDSYSREG} */
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208 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_Pmu(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
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209 | {
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210 | RT_NOREF_PV(pRange);
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211 | return PMUReadSysReg(pVCpu, idSysReg, puValue);
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212 | }
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213 |
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214 |
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215 | /** @callback_method_impl{FNCPUMWRSYSREG} */
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216 | static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_Pmu(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
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217 | {
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218 | RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
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219 | return PMUWriteSysReg(pVCpu, idSysReg, uValue);
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220 | }
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221 |
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222 |
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223 | /**
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224 | * System register read function table.
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225 | */
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226 | static const struct READSYSREGCLANG11WEIRDNOTHROW { PFNCPUMRDSYSREG pfnRdSysReg; } g_aCpumRdSysRegFns[kCpumSysRegRdFn_End] =
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227 | {
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228 | { NULL }, /* Invalid */
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229 | { cpumSysRegRd_FixedValue },
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230 | { NULL }, /* Alias */
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231 | { cpumSysRegRd_WriteOnly },
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232 | { cpumSysRegRd_ReadCpumOff },
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233 | { cpumSysRegRd_GicV3Icc },
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234 | { cpumSysRegRd_OslsrEl1 },
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235 | { cpumSysRegRd_Pmu }
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236 | };
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237 |
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238 |
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239 | /**
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240 | * System register write function table.
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241 | */
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242 | static const struct WRITESYSREGCLANG11WEIRDNOTHROW { PFNCPUMWRSYSREG pfnWrSysReg; } g_aCpumWrSysRegFns[kCpumSysRegWrFn_End] =
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243 | {
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244 | { NULL }, /* Invalid */
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245 | { cpumSysRegWr_IgnoreWrite },
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246 | { cpumSysRegWr_ReadOnly },
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247 | { NULL }, /* Alias */
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248 | { cpumSysRegWr_WriteCpumOff },
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249 | { cpumSysRegWr_GicV3Icc },
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250 | { cpumSysRegWr_OslarEl1 },
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251 | { cpumSysRegWr_Pmu }
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252 | };
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253 |
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254 |
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255 | /**
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256 | * Looks up the range for the given system register.
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257 | *
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258 | * @returns Pointer to the range if found, NULL if not.
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259 | * @param pVM The cross context VM structure.
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260 | * @param idSysReg The system register to look up.
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261 | */
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262 | # ifndef IN_RING3
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263 | static
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264 | # endif
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265 | PCPUMSYSREGRANGE cpumLookupSysRegRange(PVM pVM, uint32_t idSysReg)
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266 | {
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267 | /*
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268 | * Binary lookup.
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269 | */
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270 | uint32_t cRanges = RT_MIN(pVM->cpum.s.GuestInfo.cSysRegRanges, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aSysRegRanges));
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271 | if (!cRanges)
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272 | return NULL;
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273 | PCPUMSYSREGRANGE paRanges = pVM->cpum.s.GuestInfo.aSysRegRanges;
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274 | for (;;)
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275 | {
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276 | uint32_t i = cRanges / 2;
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277 | if (idSysReg < paRanges[i].uFirst)
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278 | {
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279 | if (i == 0)
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280 | break;
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281 | cRanges = i;
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282 | }
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283 | else if (idSysReg > paRanges[i].uLast)
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284 | {
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285 | i++;
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286 | if (i >= cRanges)
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287 | break;
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288 | cRanges -= i;
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289 | paRanges = &paRanges[i];
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290 | }
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291 | else
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292 | {
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293 | if (paRanges[i].enmRdFn == kCpumSysRegRdFn_Alias)
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294 | return cpumLookupSysRegRange(pVM, paRanges[i].uValue);
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295 | return &paRanges[i];
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296 | }
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297 | }
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298 |
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299 | # ifdef VBOX_STRICT
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300 | /*
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301 | * Linear lookup to verify the above binary search.
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302 | */
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303 | uint32_t cLeft = RT_MIN(pVM->cpum.s.GuestInfo.cSysRegRanges, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aSysRegRanges));
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304 | PCPUMSYSREGRANGE pCur = pVM->cpum.s.GuestInfo.aSysRegRanges;
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305 | while (cLeft-- > 0)
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306 | {
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307 | if (idSysReg >= pCur->uFirst && idSysReg <= pCur->uLast)
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308 | {
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309 | AssertFailed();
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310 | if (pCur->enmRdFn == kCpumSysRegRdFn_Alias)
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311 | return cpumLookupSysRegRange(pVM, pCur->uValue);
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312 | return pCur;
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313 | }
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314 | pCur++;
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315 | }
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316 | # endif
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317 | return NULL;
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318 | }
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319 |
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320 |
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321 | /**
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322 | * Query a guest system register.
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323 | *
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324 | * The caller is responsible for checking privilege if the call is the result of
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325 | * a MRS instruction. We'll do the rest.
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326 | *
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327 | * @retval VINF_SUCCESS on success.
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328 | * @retval VINF_CPUM_R3_MSR_READ if the system register read could not be serviced in the
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329 | * current context (raw-mode or ring-0).
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330 | * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid system register), the caller is
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331 | * expected to take the appropriate actions. @a *puValue is set to 0.
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332 | * @param pVCpu The cross context virtual CPU structure.
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333 | * @param idSysReg The system register.
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334 | * @param puValue Where to return the value.
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335 | *
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336 | * @remarks This will always return the right values, even when we're in the
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337 | * recompiler.
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338 | */
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339 | VMMDECL(VBOXSTRICTRC) CPUMQueryGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t *puValue)
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340 | {
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341 | *puValue = 0;
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342 |
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343 | VBOXSTRICTRC rcStrict;
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344 | PVM pVM = pVCpu->CTX_SUFF(pVM);
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345 | PCPUMSYSREGRANGE pRange = cpumLookupSysRegRange(pVM, idSysReg);
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346 | if (pRange)
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347 | {
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348 | CPUMSYSREGRDFN enmRdFn = (CPUMSYSREGRDFN)pRange->enmRdFn;
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349 | AssertReturn(enmRdFn > kCpumSysRegRdFn_Invalid && enmRdFn < kCpumSysRegRdFn_End, VERR_CPUM_IPE_1);
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350 |
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351 | PFNCPUMRDSYSREG pfnRdSysReg = g_aCpumRdSysRegFns[enmRdFn].pfnRdSysReg;
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352 | AssertReturn(pfnRdSysReg, VERR_CPUM_IPE_2);
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353 |
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354 | STAM_COUNTER_INC(&pRange->cReads);
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355 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegReads);
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356 |
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357 | rcStrict = pfnRdSysReg(pVCpu, idSysReg, pRange, puValue);
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358 | if (rcStrict == VINF_SUCCESS)
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359 | Log2(("CPUM: MRS %#x (%s) -> %#llx\n", idSysReg, pRange->szName, *puValue));
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360 | else if (rcStrict == VERR_CPUM_RAISE_GP_0)
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361 | {
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362 | Log(("CPUM: MRS %#x (%s) -> #GP(0)\n", idSysReg, pRange->szName));
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363 | STAM_COUNTER_INC(&pRange->cExcp);
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364 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegReadsRaiseExcp);
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365 | }
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366 | #ifndef IN_RING3
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367 | else if (rcStrict == VINF_CPUM_R3_MSR_READ)
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368 | Log(("CPUM: MRS %#x (%s) -> ring-3\n", idSysReg, pRange->szName));
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369 | #endif
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370 | else
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371 | {
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372 | Log(("CPUM: MRS %#x (%s) -> rcStrict=%Rrc\n", idSysReg, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
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373 | AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idSysReg=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idSysReg),
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374 | rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
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375 | Assert(rcStrict != VERR_EM_INTERPRETER);
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376 | }
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377 | }
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378 | else
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379 | {
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380 | Log(("CPUM: Unknown MRS %#x -> Ignore\n", idSysReg));
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381 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegReads);
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382 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegReadsUnknown);
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383 | *puValue = 0;
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384 | rcStrict = VINF_SUCCESS;
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385 | }
|
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386 | return rcStrict;
|
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387 | }
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388 |
|
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389 |
|
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390 | /**
|
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391 | * Writes to a guest system register.
|
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392 | *
|
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393 | * The caller is responsible for checking privilege if the call is the result of
|
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394 | * a MSR instruction. We'll do the rest.
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395 | *
|
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396 | * @retval VINF_SUCCESS on success.
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397 | * @retval VINF_CPUM_R3_MSR_WRITE if the system register write could not be serviced in the
|
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398 | * current context (raw-mode or ring-0).
|
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399 | * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
|
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400 | * appropriate actions.
|
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401 | *
|
---|
402 | * @param pVCpu The cross context virtual CPU structure.
|
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403 | * @param idSysReg The system register id.
|
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404 | * @param uValue The value to set.
|
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405 | *
|
---|
406 | * @remarks Everyone changing system register values, shall do it
|
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407 | * by calling this method. This makes sure we have current values and
|
---|
408 | * that we trigger all the right actions when something changes.
|
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409 | */
|
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410 | VMMDECL(VBOXSTRICTRC) CPUMSetGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t uValue)
|
---|
411 | {
|
---|
412 | VBOXSTRICTRC rcStrict;
|
---|
413 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
414 | PCPUMSYSREGRANGE pRange = cpumLookupSysRegRange(pVM, idSysReg);
|
---|
415 | if (pRange)
|
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416 | {
|
---|
417 | STAM_COUNTER_INC(&pRange->cWrites);
|
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418 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWrites);
|
---|
419 |
|
---|
420 | if (!(uValue & pRange->fWrExcpMask))
|
---|
421 | {
|
---|
422 | CPUMSYSREGWRFN enmWrFn = (CPUMSYSREGWRFN)pRange->enmWrFn;
|
---|
423 | AssertReturn(enmWrFn > kCpumSysRegWrFn_Invalid && enmWrFn < kCpumSysRegWrFn_End, VERR_CPUM_IPE_1);
|
---|
424 |
|
---|
425 | PFNCPUMWRSYSREG pfnWrSysReg = g_aCpumWrSysRegFns[enmWrFn].pfnWrSysReg;
|
---|
426 | AssertReturn(pfnWrSysReg, VERR_CPUM_IPE_2);
|
---|
427 |
|
---|
428 | uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
|
---|
429 | if (uValueAdjusted != uValue)
|
---|
430 | {
|
---|
431 | STAM_COUNTER_INC(&pRange->cIgnoredBits);
|
---|
432 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesToIgnoredBits);
|
---|
433 | }
|
---|
434 |
|
---|
435 | rcStrict = pfnWrSysReg(pVCpu, idSysReg, pRange, uValueAdjusted, uValue);
|
---|
436 | if (rcStrict == VINF_SUCCESS)
|
---|
437 | Log2(("CPUM: MSR %#x (%s), %#llx [%#llx]\n", idSysReg, pRange->szName, uValueAdjusted, uValue));
|
---|
438 | else if (rcStrict == VERR_CPUM_RAISE_GP_0)
|
---|
439 | {
|
---|
440 | Log(("CPUM: MSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idSysReg, pRange->szName, uValueAdjusted, uValue));
|
---|
441 | STAM_COUNTER_INC(&pRange->cExcp);
|
---|
442 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesRaiseExcp);
|
---|
443 | }
|
---|
444 | #ifndef IN_RING3
|
---|
445 | else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
|
---|
446 | Log(("CPUM: MSR %#x (%s), %#llx [%#llx] -> ring-3\n", idSysReg, pRange->szName, uValueAdjusted, uValue));
|
---|
447 | #endif
|
---|
448 | else
|
---|
449 | {
|
---|
450 | Log(("CPUM: MSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
|
---|
451 | idSysReg, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
|
---|
452 | AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idSysReg=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idSysReg),
|
---|
453 | rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
|
---|
454 | Assert(rcStrict != VERR_EM_INTERPRETER);
|
---|
455 | }
|
---|
456 | }
|
---|
457 | else
|
---|
458 | {
|
---|
459 | Log(("CPUM: MSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
|
---|
460 | idSysReg, pRange->szName, uValue, uValue & pRange->fWrExcpMask));
|
---|
461 | STAM_COUNTER_INC(&pRange->cExcp);
|
---|
462 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesRaiseExcp);
|
---|
463 | rcStrict = VERR_CPUM_RAISE_GP_0;
|
---|
464 | }
|
---|
465 | }
|
---|
466 | else
|
---|
467 | {
|
---|
468 | Log(("CPUM: Unknown MSR %#x, %#llx -> #GP(0)\n", idSysReg, uValue));
|
---|
469 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWrites);
|
---|
470 | STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesUnknown);
|
---|
471 | rcStrict = VERR_CPUM_RAISE_GP_0; /** @todo Better status code. */
|
---|
472 | }
|
---|
473 | return rcStrict;
|
---|
474 | }
|
---|
475 |
|
---|
476 |
|
---|
477 | #if defined(VBOX_STRICT) && defined(IN_RING3)
|
---|
478 | /**
|
---|
479 | * Performs some checks on the static data related to MSRs.
|
---|
480 | *
|
---|
481 | * @returns VINF_SUCCESS on success, error on failure.
|
---|
482 | */
|
---|
483 | DECLHIDDEN(int) cpumR3SysRegStrictInitChecks(void)
|
---|
484 | {
|
---|
485 | #define CPUM_ASSERT_RD_SYSREG_FN(a_Register) \
|
---|
486 | AssertReturn(g_aCpumRdSysRegFns[kCpumSysRegRdFn_##a_Register].pfnRdSysReg == cpumSysRegRd_##a_Register, VERR_CPUM_IPE_2);
|
---|
487 | #define CPUM_ASSERT_WR_SYSREG_FN(a_Register) \
|
---|
488 | AssertReturn(g_aCpumWrSysRegFns[kCpumSysRegWrFn_##a_Register].pfnWrSysReg == cpumSysRegWr_##a_Register, VERR_CPUM_IPE_2);
|
---|
489 |
|
---|
490 | AssertReturn(g_aCpumRdSysRegFns[kCpumSysRegRdFn_Invalid].pfnRdSysReg == NULL, VERR_CPUM_IPE_2);
|
---|
491 | CPUM_ASSERT_RD_SYSREG_FN(FixedValue);
|
---|
492 | CPUM_ASSERT_RD_SYSREG_FN(WriteOnly);
|
---|
493 | CPUM_ASSERT_RD_SYSREG_FN(ReadCpumOff);
|
---|
494 | CPUM_ASSERT_RD_SYSREG_FN(GicV3Icc);
|
---|
495 | CPUM_ASSERT_RD_SYSREG_FN(OslsrEl1);
|
---|
496 | CPUM_ASSERT_RD_SYSREG_FN(Pmu);
|
---|
497 |
|
---|
498 | AssertReturn(g_aCpumWrSysRegFns[kCpumSysRegWrFn_Invalid].pfnWrSysReg == NULL, VERR_CPUM_IPE_2);
|
---|
499 | CPUM_ASSERT_WR_SYSREG_FN(IgnoreWrite);
|
---|
500 | CPUM_ASSERT_WR_SYSREG_FN(ReadOnly);
|
---|
501 | CPUM_ASSERT_WR_SYSREG_FN(WriteCpumOff);
|
---|
502 | CPUM_ASSERT_WR_SYSREG_FN(GicV3Icc);
|
---|
503 | CPUM_ASSERT_WR_SYSREG_FN(OslarEl1);
|
---|
504 | CPUM_ASSERT_WR_SYSREG_FN(Pmu);
|
---|
505 |
|
---|
506 | return VINF_SUCCESS;
|
---|
507 | }
|
---|
508 | #endif /* VBOX_STRICT && IN_RING3 */
|
---|