VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 97178

Last change on this file since 97178 was 97178, checked in by vboxsync, 2 years ago

VMM/CPUM,EM,HM,IEM,++: Moved VMCPU_FF_INHIBIT_INTERRUPTS and VMCPU_FF_BLOCK_NMIS to CPUMCTX::fInhibit. Moved ldtr and tr up to the CPUMCTXCORE area in hope for better cache alignment of rip, rflags and crX register fields. bugref:9941
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 98.5 KB
Line 
1/* $Id: CPUMAllRegs.cpp 97178 2022-10-17 21:06:03Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_CPUM
33#include <VBox/vmm/cpum.h>
34#include <VBox/vmm/dbgf.h>
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/pgm.h>
37#include <VBox/vmm/mm.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/nem.h>
40#include <VBox/vmm/hm.h>
41#include "CPUMInternal.h"
42#include <VBox/vmm/vmcc.h>
43#include <VBox/err.h>
44#include <VBox/dis.h>
45#include <VBox/log.h>
46#include <VBox/vmm/hm.h>
47#include <VBox/vmm/tm.h>
48#include <iprt/assert.h>
49#include <iprt/asm.h>
50#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
51# include <iprt/asm-amd64-x86.h>
52#endif
53#ifdef IN_RING3
54# include <iprt/thread.h>
55#endif
56
57/** Disable stack frame pointer generation here. */
58#if defined(_MSC_VER) && !defined(DEBUG) && defined(RT_ARCH_X86)
59# pragma optimize("y", off)
60#endif
61
62AssertCompile2MemberOffsets(VM, cpum.s.GuestFeatures, cpum.ro.GuestFeatures);
63
64
65/*********************************************************************************************************************************
66* Defined Constants And Macros *
67*********************************************************************************************************************************/
68/**
69 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
70 *
71 * @returns Pointer to the Virtual CPU.
72 * @param a_pGuestCtx Pointer to the guest context.
73 */
74#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
75
76/**
77 * Lazily loads the hidden parts of a selector register when using raw-mode.
78 */
79#define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
80 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg))
81
82/** @def CPUM_INT_ASSERT_NOT_EXTRN
83 * Macro for asserting that @a a_fNotExtrn are present.
84 *
85 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
86 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
87 */
88#define CPUM_INT_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
89 AssertMsg(!((a_pVCpu)->cpum.s.Guest.fExtrn & (a_fNotExtrn)), \
90 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.s.Guest.fExtrn, (a_fNotExtrn)))
91
92
93VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
94{
95 pVCpu->cpum.s.Hyper.cr3 = cr3;
96}
97
98VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
99{
100 return pVCpu->cpum.s.Hyper.cr3;
101}
102
103
104/** @def MAYBE_LOAD_DRx
105 * Macro for updating DRx values in raw-mode and ring-0 contexts.
106 */
107#ifdef IN_RING0
108# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { a_fnLoad(a_uValue); } while (0)
109#else
110# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
111#endif
112
113VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
114{
115 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
116 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
117}
118
119
120VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
121{
122 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
123 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
124}
125
126
127VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
128{
129 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
130 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
131}
132
133
134VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
135{
136 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
137 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
138}
139
140
141VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
142{
143 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
144}
145
146
147VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
148{
149 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
150}
151
152
153VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
154{
155 return pVCpu->cpum.s.Hyper.dr[0];
156}
157
158
159VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
160{
161 return pVCpu->cpum.s.Hyper.dr[1];
162}
163
164
165VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
166{
167 return pVCpu->cpum.s.Hyper.dr[2];
168}
169
170
171VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
172{
173 return pVCpu->cpum.s.Hyper.dr[3];
174}
175
176
177VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
178{
179 return pVCpu->cpum.s.Hyper.dr[6];
180}
181
182
183VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
184{
185 return pVCpu->cpum.s.Hyper.dr[7];
186}
187
188
189/**
190 * Gets the pointer to the internal CPUMCTXCORE structure.
191 * This is only for reading in order to save a few calls.
192 *
193 * @param pVCpu The cross context virtual CPU structure.
194 */
195VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
196{
197 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
198}
199
200
201/**
202 * Queries the pointer to the internal CPUMCTX structure.
203 *
204 * @returns The CPUMCTX pointer.
205 * @param pVCpu The cross context virtual CPU structure.
206 */
207VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
208{
209 return &pVCpu->cpum.s.Guest;
210}
211
212
213/**
214 * Queries the pointer to the internal CPUMCTXMSRS structure.
215 *
216 * This is for NEM only.
217 *
218 * @returns The CPUMCTX pointer.
219 * @param pVCpu The cross context virtual CPU structure.
220 */
221VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu)
222{
223 return &pVCpu->cpum.s.GuestMsrs;
224}
225
226
227VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
228{
229 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
230 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
231 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_GDTR;
232 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
233 return VINF_SUCCESS; /* formality, consider it void. */
234}
235
236
237VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
238{
239 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
240 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
241 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_IDTR;
242 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
243 return VINF_SUCCESS; /* formality, consider it void. */
244}
245
246
247VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
248{
249 pVCpu->cpum.s.Guest.tr.Sel = tr;
250 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
251 return VINF_SUCCESS; /* formality, consider it void. */
252}
253
254
255VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
256{
257 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
258 /* The caller will set more hidden bits if it has them. */
259 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
260 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
261 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
262 return VINF_SUCCESS; /* formality, consider it void. */
263}
264
265
266/**
267 * Set the guest CR0.
268 *
269 * When called in GC, the hyper CR0 may be updated if that is
270 * required. The caller only has to take special action if AM,
271 * WP, PG or PE changes.
272 *
273 * @returns VINF_SUCCESS (consider it void).
274 * @param pVCpu The cross context virtual CPU structure.
275 * @param cr0 The new CR0 value.
276 */
277VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0)
278{
279 /*
280 * Check for changes causing TLB flushes (for REM).
281 * The caller is responsible for calling PGM when appropriate.
282 */
283 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
284 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
285 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
286 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
287
288 /*
289 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
290 */
291 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
292 PGMCr0WpEnabled(pVCpu);
293
294 /* The ET flag is settable on a 386 and hardwired on 486+. */
295 if ( !(cr0 & X86_CR0_ET)
296 && pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386)
297 cr0 |= X86_CR0_ET;
298
299 pVCpu->cpum.s.Guest.cr0 = cr0;
300 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR0;
301 return VINF_SUCCESS;
302}
303
304
305VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
306{
307 pVCpu->cpum.s.Guest.cr2 = cr2;
308 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR2;
309 return VINF_SUCCESS;
310}
311
312
313VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
314{
315 pVCpu->cpum.s.Guest.cr3 = cr3;
316 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
317 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
318 return VINF_SUCCESS;
319}
320
321
322VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
323{
324 /* Note! We don't bother with OSXSAVE and legacy CPUID patches. */
325
326 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
327 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
328 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
329
330 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
331 pVCpu->cpum.s.Guest.cr4 = cr4;
332 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR4;
333 return VINF_SUCCESS;
334}
335
336
337VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
338{
339 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
340 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
341 return VINF_SUCCESS;
342}
343
344
345VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
346{
347 pVCpu->cpum.s.Guest.eip = eip;
348 return VINF_SUCCESS;
349}
350
351
352VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
353{
354 pVCpu->cpum.s.Guest.eax = eax;
355 return VINF_SUCCESS;
356}
357
358
359VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
360{
361 pVCpu->cpum.s.Guest.ebx = ebx;
362 return VINF_SUCCESS;
363}
364
365
366VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
367{
368 pVCpu->cpum.s.Guest.ecx = ecx;
369 return VINF_SUCCESS;
370}
371
372
373VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
374{
375 pVCpu->cpum.s.Guest.edx = edx;
376 return VINF_SUCCESS;
377}
378
379
380VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
381{
382 pVCpu->cpum.s.Guest.esp = esp;
383 return VINF_SUCCESS;
384}
385
386
387VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
388{
389 pVCpu->cpum.s.Guest.ebp = ebp;
390 return VINF_SUCCESS;
391}
392
393
394VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
395{
396 pVCpu->cpum.s.Guest.esi = esi;
397 return VINF_SUCCESS;
398}
399
400
401VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
402{
403 pVCpu->cpum.s.Guest.edi = edi;
404 return VINF_SUCCESS;
405}
406
407
408VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
409{
410 pVCpu->cpum.s.Guest.ss.Sel = ss;
411 return VINF_SUCCESS;
412}
413
414
415VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
416{
417 pVCpu->cpum.s.Guest.cs.Sel = cs;
418 return VINF_SUCCESS;
419}
420
421
422VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
423{
424 pVCpu->cpum.s.Guest.ds.Sel = ds;
425 return VINF_SUCCESS;
426}
427
428
429VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
430{
431 pVCpu->cpum.s.Guest.es.Sel = es;
432 return VINF_SUCCESS;
433}
434
435
436VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
437{
438 pVCpu->cpum.s.Guest.fs.Sel = fs;
439 return VINF_SUCCESS;
440}
441
442
443VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
444{
445 pVCpu->cpum.s.Guest.gs.Sel = gs;
446 return VINF_SUCCESS;
447}
448
449
450VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
451{
452 pVCpu->cpum.s.Guest.msrEFER = val;
453 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_EFER;
454}
455
456
457VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit)
458{
459 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_IDTR);
460 if (pcbLimit)
461 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
462 return pVCpu->cpum.s.Guest.idtr.pIdt;
463}
464
465
466VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden)
467{
468 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_TR);
469 if (pHidden)
470 *pHidden = pVCpu->cpum.s.Guest.tr;
471 return pVCpu->cpum.s.Guest.tr.Sel;
472}
473
474
475VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu)
476{
477 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS);
478 return pVCpu->cpum.s.Guest.cs.Sel;
479}
480
481
482VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu)
483{
484 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DS);
485 return pVCpu->cpum.s.Guest.ds.Sel;
486}
487
488
489VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu)
490{
491 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ES);
492 return pVCpu->cpum.s.Guest.es.Sel;
493}
494
495
496VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu)
497{
498 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_FS);
499 return pVCpu->cpum.s.Guest.fs.Sel;
500}
501
502
503VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu)
504{
505 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GS);
506 return pVCpu->cpum.s.Guest.gs.Sel;
507}
508
509
510VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu)
511{
512 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SS);
513 return pVCpu->cpum.s.Guest.ss.Sel;
514}
515
516
517VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu)
518{
519 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
520 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
521 if ( !CPUMIsGuestInLongMode(pVCpu)
522 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
523 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.cs.u64Base;
524 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.cs.u64Base;
525}
526
527
528VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu)
529{
530 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
531 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
532 if ( !CPUMIsGuestInLongMode(pVCpu)
533 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
534 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.ss.u64Base;
535 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.ss.u64Base;
536}
537
538
539VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu)
540{
541 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
542 return pVCpu->cpum.s.Guest.ldtr.Sel;
543}
544
545
546VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
547{
548 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
549 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
550 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
551 return pVCpu->cpum.s.Guest.ldtr.Sel;
552}
553
554
555VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu)
556{
557 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
558 return pVCpu->cpum.s.Guest.cr0;
559}
560
561
562VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu)
563{
564 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
565 return pVCpu->cpum.s.Guest.cr2;
566}
567
568
569VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu)
570{
571 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
572 return pVCpu->cpum.s.Guest.cr3;
573}
574
575
576VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu)
577{
578 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
579 return pVCpu->cpum.s.Guest.cr4;
580}
581
582
583VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu)
584{
585 uint64_t u64;
586 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
587 if (RT_FAILURE(rc))
588 u64 = 0;
589 return u64;
590}
591
592
593VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR)
594{
595 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GDTR);
596 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
597}
598
599
600VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu)
601{
602 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
603 return pVCpu->cpum.s.Guest.eip;
604}
605
606
607VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu)
608{
609 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
610 return pVCpu->cpum.s.Guest.rip;
611}
612
613
614VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu)
615{
616 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RAX);
617 return pVCpu->cpum.s.Guest.eax;
618}
619
620
621VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu)
622{
623 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBX);
624 return pVCpu->cpum.s.Guest.ebx;
625}
626
627
628VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu)
629{
630 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RCX);
631 return pVCpu->cpum.s.Guest.ecx;
632}
633
634
635VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu)
636{
637 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDX);
638 return pVCpu->cpum.s.Guest.edx;
639}
640
641
642VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu)
643{
644 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSI);
645 return pVCpu->cpum.s.Guest.esi;
646}
647
648
649VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu)
650{
651 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDI);
652 return pVCpu->cpum.s.Guest.edi;
653}
654
655
656VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu)
657{
658 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP);
659 return pVCpu->cpum.s.Guest.esp;
660}
661
662
663VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu)
664{
665 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBP);
666 return pVCpu->cpum.s.Guest.ebp;
667}
668
669
670VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu)
671{
672 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RFLAGS);
673 return pVCpu->cpum.s.Guest.eflags.u32;
674}
675
676
677VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue)
678{
679 switch (iReg)
680 {
681 case DISCREG_CR0:
682 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
683 *pValue = pVCpu->cpum.s.Guest.cr0;
684 break;
685
686 case DISCREG_CR2:
687 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
688 *pValue = pVCpu->cpum.s.Guest.cr2;
689 break;
690
691 case DISCREG_CR3:
692 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
693 *pValue = pVCpu->cpum.s.Guest.cr3;
694 break;
695
696 case DISCREG_CR4:
697 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
698 *pValue = pVCpu->cpum.s.Guest.cr4;
699 break;
700
701 case DISCREG_CR8:
702 {
703 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
704 uint8_t u8Tpr;
705 int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
706 if (RT_FAILURE(rc))
707 {
708 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
709 *pValue = 0;
710 return rc;
711 }
712 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0 */
713 break;
714 }
715
716 default:
717 return VERR_INVALID_PARAMETER;
718 }
719 return VINF_SUCCESS;
720}
721
722
723VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu)
724{
725 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
726 return pVCpu->cpum.s.Guest.dr[0];
727}
728
729
730VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu)
731{
732 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
733 return pVCpu->cpum.s.Guest.dr[1];
734}
735
736
737VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu)
738{
739 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
740 return pVCpu->cpum.s.Guest.dr[2];
741}
742
743
744VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu)
745{
746 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
747 return pVCpu->cpum.s.Guest.dr[3];
748}
749
750
751VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu)
752{
753 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR6);
754 return pVCpu->cpum.s.Guest.dr[6];
755}
756
757
758VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu)
759{
760 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
761 return pVCpu->cpum.s.Guest.dr[7];
762}
763
764
765VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
766{
767 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR_MASK);
768 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
769 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
770 if (iReg == 4 || iReg == 5)
771 iReg += 2;
772 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
773 return VINF_SUCCESS;
774}
775
776
777VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu)
778{
779 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
780 return pVCpu->cpum.s.Guest.msrEFER;
781}
782
783
784/**
785 * Looks up a CPUID leaf in the CPUID leaf array, no subleaf.
786 *
787 * @returns Pointer to the leaf if found, NULL if not.
788 *
789 * @param pVM The cross context VM structure.
790 * @param uLeaf The leaf to get.
791 */
792PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf)
793{
794 unsigned iEnd = RT_MIN(pVM->cpum.s.GuestInfo.cCpuIdLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves));
795 if (iEnd)
796 {
797 unsigned iStart = 0;
798 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.aCpuIdLeaves;
799 for (;;)
800 {
801 unsigned i = iStart + (iEnd - iStart) / 2U;
802 if (uLeaf < paLeaves[i].uLeaf)
803 {
804 if (i <= iStart)
805 return NULL;
806 iEnd = i;
807 }
808 else if (uLeaf > paLeaves[i].uLeaf)
809 {
810 i += 1;
811 if (i >= iEnd)
812 return NULL;
813 iStart = i;
814 }
815 else
816 {
817 if (RT_LIKELY(paLeaves[i].fSubLeafMask == 0 && paLeaves[i].uSubLeaf == 0))
818 return &paLeaves[i];
819
820 /* This shouldn't normally happen. But in case the it does due
821 to user configuration overrids or something, just return the
822 first sub-leaf. */
823 AssertMsgFailed(("uLeaf=%#x fSubLeafMask=%#x uSubLeaf=%#x\n",
824 uLeaf, paLeaves[i].fSubLeafMask, paLeaves[i].uSubLeaf));
825 while ( paLeaves[i].uSubLeaf != 0
826 && i > 0
827 && uLeaf == paLeaves[i - 1].uLeaf)
828 i--;
829 return &paLeaves[i];
830 }
831 }
832 }
833
834 return NULL;
835}
836
837
838/**
839 * Looks up a CPUID leaf in the CPUID leaf array.
840 *
841 * @returns Pointer to the leaf if found, NULL if not.
842 *
843 * @param pVM The cross context VM structure.
844 * @param uLeaf The leaf to get.
845 * @param uSubLeaf The subleaf, if applicable. Just pass 0 if it
846 * isn't.
847 * @param pfExactSubLeafHit Whether we've got an exact subleaf hit or not.
848 */
849PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit)
850{
851 unsigned iEnd = RT_MIN(pVM->cpum.s.GuestInfo.cCpuIdLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves));
852 if (iEnd)
853 {
854 unsigned iStart = 0;
855 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.aCpuIdLeaves;
856 for (;;)
857 {
858 unsigned i = iStart + (iEnd - iStart) / 2U;
859 if (uLeaf < paLeaves[i].uLeaf)
860 {
861 if (i <= iStart)
862 return NULL;
863 iEnd = i;
864 }
865 else if (uLeaf > paLeaves[i].uLeaf)
866 {
867 i += 1;
868 if (i >= iEnd)
869 return NULL;
870 iStart = i;
871 }
872 else
873 {
874 uSubLeaf &= paLeaves[i].fSubLeafMask;
875 if (uSubLeaf == paLeaves[i].uSubLeaf)
876 *pfExactSubLeafHit = true;
877 else
878 {
879 /* Find the right subleaf. We return the last one before
880 uSubLeaf if we don't find an exact match. */
881 if (uSubLeaf < paLeaves[i].uSubLeaf)
882 while ( i > 0
883 && uLeaf == paLeaves[i - 1].uLeaf
884 && uSubLeaf <= paLeaves[i - 1].uSubLeaf)
885 i--;
886 else
887 while ( i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves
888 && uLeaf == paLeaves[i + 1].uLeaf
889 && uSubLeaf >= paLeaves[i + 1].uSubLeaf)
890 i++;
891 *pfExactSubLeafHit = uSubLeaf == paLeaves[i].uSubLeaf;
892 }
893 return &paLeaves[i];
894 }
895 }
896 }
897
898 *pfExactSubLeafHit = false;
899 return NULL;
900}
901
902
903/**
904 * Gets a CPUID leaf.
905 *
906 * @param pVCpu The cross context virtual CPU structure.
907 * @param uLeaf The CPUID leaf to get.
908 * @param uSubLeaf The CPUID sub-leaf to get, if applicable.
909 * @param f64BitMode A tristate indicate if the caller is in 64-bit mode or
910 * not: 1=true, 0=false, 1=whatever. This affect how the
911 * X86_CPUID_EXT_FEATURE_EDX_SYSCALL flag is returned on
912 * Intel CPUs, where it's only returned in 64-bit mode.
913 * @param pEax Where to store the EAX value.
914 * @param pEbx Where to store the EBX value.
915 * @param pEcx Where to store the ECX value.
916 * @param pEdx Where to store the EDX value.
917 */
918VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t uLeaf, uint32_t uSubLeaf, int f64BitMode,
919 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
920{
921 bool fExactSubLeafHit;
922 PVM pVM = pVCpu->CTX_SUFF(pVM);
923 PCCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, uSubLeaf, &fExactSubLeafHit);
924 if (pLeaf)
925 {
926 AssertMsg(pLeaf->uLeaf == uLeaf, ("%#x %#x\n", pLeaf->uLeaf, uLeaf));
927 if (fExactSubLeafHit)
928 {
929 *pEax = pLeaf->uEax;
930 *pEbx = pLeaf->uEbx;
931 *pEcx = pLeaf->uEcx;
932 *pEdx = pLeaf->uEdx;
933
934 /*
935 * Deal with CPU specific information.
936 */
937 if (pLeaf->fFlags & ( CPUMCPUIDLEAF_F_CONTAINS_APIC_ID
938 | CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
939 | CPUMCPUIDLEAF_F_CONTAINS_APIC ))
940 {
941 if (uLeaf == 1)
942 {
943 /* EBX: Bits 31-24: Initial APIC ID. */
944 Assert(pVCpu->idCpu <= 255);
945 AssertMsg((pLeaf->uEbx >> 24) == 0, ("%#x\n", pLeaf->uEbx)); /* raw-mode assumption */
946 *pEbx = (pLeaf->uEbx & UINT32_C(0x00ffffff)) | (pVCpu->idCpu << 24);
947
948 /* EDX: Bit 9: AND with APICBASE.EN. */
949 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
950 *pEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
951
952 /* ECX: Bit 27: CR4.OSXSAVE mirror. */
953 *pEcx = (pLeaf->uEcx & ~X86_CPUID_FEATURE_ECX_OSXSAVE)
954 | (pVCpu->cpum.s.Guest.cr4 & X86_CR4_OSXSAVE ? X86_CPUID_FEATURE_ECX_OSXSAVE : 0);
955 }
956 else if (uLeaf == 0xb)
957 {
958 /* EDX: Initial extended APIC ID. */
959 AssertMsg(pLeaf->uEdx == 0, ("%#x\n", pLeaf->uEdx)); /* raw-mode assumption */
960 *pEdx = pVCpu->idCpu;
961 Assert(!(pLeaf->fFlags & ~(CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)));
962 }
963 else if (uLeaf == UINT32_C(0x8000001e))
964 {
965 /* EAX: Initial extended APIC ID. */
966 AssertMsg(pLeaf->uEax == 0, ("%#x\n", pLeaf->uEax)); /* raw-mode assumption */
967 *pEax = pVCpu->idCpu;
968 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID));
969 }
970 else if (uLeaf == UINT32_C(0x80000001))
971 {
972 /* EDX: Bit 9: AND with APICBASE.EN. */
973 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible)
974 *pEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
975 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC));
976 }
977 else
978 AssertMsgFailed(("uLeaf=%#x\n", uLeaf));
979 }
980
981 /* Intel CPUs supresses the SYSCALL bit when not executing in 64-bit mode: */
982 if ( uLeaf == UINT32_C(0x80000001)
983 && f64BitMode == false
984 && (*pEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
985 && ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
986 || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA /*?*/
987 || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_SHANGHAI /*?*/ ) )
988 *pEdx &= ~X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
989
990 }
991 /*
992 * Out of range sub-leaves aren't quite as easy and pretty as we emulate
993 * them here, but we do the best we can here...
994 */
995 else
996 {
997 *pEax = *pEbx = *pEcx = *pEdx = 0;
998 if (pLeaf->fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
999 {
1000 *pEcx = uSubLeaf & 0xff;
1001 *pEdx = pVCpu->idCpu;
1002 }
1003 }
1004 }
1005 else
1006 {
1007 /*
1008 * Different CPUs have different ways of dealing with unknown CPUID leaves.
1009 */
1010 switch (pVM->cpum.s.GuestInfo.enmUnknownCpuIdMethod)
1011 {
1012 default:
1013 AssertFailed();
1014 RT_FALL_THRU();
1015 case CPUMUNKNOWNCPUID_DEFAULTS:
1016 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: /* ASSUME this is executed */
1017 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: /** @todo Implement CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX */
1018 *pEax = pVM->cpum.s.GuestInfo.DefCpuId.uEax;
1019 *pEbx = pVM->cpum.s.GuestInfo.DefCpuId.uEbx;
1020 *pEcx = pVM->cpum.s.GuestInfo.DefCpuId.uEcx;
1021 *pEdx = pVM->cpum.s.GuestInfo.DefCpuId.uEdx;
1022 break;
1023 case CPUMUNKNOWNCPUID_PASSTHRU:
1024 *pEax = uLeaf;
1025 *pEbx = 0;
1026 *pEcx = uSubLeaf;
1027 *pEdx = 0;
1028 break;
1029 }
1030 }
1031 Log2(("CPUMGetGuestCpuId: uLeaf=%#010x/%#010x %RX32 %RX32 %RX32 %RX32\n", uLeaf, uSubLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1032}
1033
1034
1035/**
1036 * Sets the visibility of the X86_CPUID_FEATURE_EDX_APIC and
1037 * X86_CPUID_AMD_FEATURE_EDX_APIC CPUID bits.
1038 *
1039 * @returns Previous value.
1040 * @param pVCpu The cross context virtual CPU structure to make the
1041 * change on. Usually the calling EMT.
1042 * @param fVisible Whether to make it visible (true) or hide it (false).
1043 *
1044 * @remarks This is "VMMDECL" so that it still links with
1045 * the old APIC code which is in VBoxDD2 and not in
1046 * the VMM module.
1047 */
1048VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible)
1049{
1050 bool fOld = pVCpu->cpum.s.fCpuIdApicFeatureVisible;
1051 pVCpu->cpum.s.fCpuIdApicFeatureVisible = fVisible;
1052 return fOld;
1053}
1054
1055
1056/**
1057 * Gets the host CPU vendor.
1058 *
1059 * @returns CPU vendor.
1060 * @param pVM The cross context VM structure.
1061 */
1062VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1063{
1064 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor;
1065}
1066
1067
1068/**
1069 * Gets the host CPU microarchitecture.
1070 *
1071 * @returns CPU microarchitecture.
1072 * @param pVM The cross context VM structure.
1073 */
1074VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM)
1075{
1076 return pVM->cpum.s.HostFeatures.enmMicroarch;
1077}
1078
1079
1080/**
1081 * Gets the guest CPU vendor.
1082 *
1083 * @returns CPU vendor.
1084 * @param pVM The cross context VM structure.
1085 */
1086VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1087{
1088 return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor;
1089}
1090
1091
1092/**
1093 * Gets the guest CPU microarchitecture.
1094 *
1095 * @returns CPU microarchitecture.
1096 * @param pVM The cross context VM structure.
1097 */
1098VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM)
1099{
1100 return pVM->cpum.s.GuestFeatures.enmMicroarch;
1101}
1102
1103
1104/**
1105 * Gets the maximum number of physical and linear address bits supported by the
1106 * guest.
1107 *
1108 * @param pVM The cross context VM structure.
1109 * @param pcPhysAddrWidth Where to store the physical address width.
1110 * @param pcLinearAddrWidth Where to store the linear address width.
1111 */
1112VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t *pcPhysAddrWidth, uint8_t *pcLinearAddrWidth)
1113{
1114 AssertPtr(pVM);
1115 AssertReturnVoid(pcPhysAddrWidth);
1116 AssertReturnVoid(pcLinearAddrWidth);
1117 *pcPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
1118 *pcLinearAddrWidth = pVM->cpum.s.GuestFeatures.cMaxLinearAddrWidth;
1119}
1120
1121
1122VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0)
1123{
1124 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1125 return CPUMRecalcHyperDRx(pVCpu, 0);
1126}
1127
1128
1129VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1)
1130{
1131 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1132 return CPUMRecalcHyperDRx(pVCpu, 1);
1133}
1134
1135
1136VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2)
1137{
1138 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1139 return CPUMRecalcHyperDRx(pVCpu, 2);
1140}
1141
1142
1143VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3)
1144{
1145 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1146 return CPUMRecalcHyperDRx(pVCpu, 3);
1147}
1148
1149
1150VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1151{
1152 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1153 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR6;
1154 return VINF_SUCCESS; /* No need to recalc. */
1155}
1156
1157
1158VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7)
1159{
1160 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1161 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR7;
1162 return CPUMRecalcHyperDRx(pVCpu, 7);
1163}
1164
1165
1166VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value)
1167{
1168 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1169 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1170 if (iReg == 4 || iReg == 5)
1171 iReg += 2;
1172 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1173 return CPUMRecalcHyperDRx(pVCpu, iReg);
1174}
1175
1176
1177/**
1178 * Recalculates the hypervisor DRx register values based on current guest
1179 * registers and DBGF breakpoints, updating changed registers depending on the
1180 * context.
1181 *
1182 * This is called whenever a guest DRx register is modified (any context) and
1183 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
1184 *
1185 * In raw-mode context this function will reload any (hyper) DRx registers which
1186 * comes out with a different value. It may also have to save the host debug
1187 * registers if that haven't been done already. In this context though, we'll
1188 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
1189 * are only important when breakpoints are actually enabled.
1190 *
1191 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
1192 * reloaded by the HM code if it changes. Further more, we will only use the
1193 * combined register set when the VBox debugger is actually using hardware BPs,
1194 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
1195 * concern us here).
1196 *
1197 * In ring-3 we won't be loading anything, so well calculate hypervisor values
1198 * all the time.
1199 *
1200 * @returns VINF_SUCCESS.
1201 * @param pVCpu The cross context virtual CPU structure.
1202 * @param iGstReg The guest debug register number that was modified.
1203 * UINT8_MAX if not guest register.
1204 */
1205VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg)
1206{
1207 PVM pVM = pVCpu->CTX_SUFF(pVM);
1208#ifndef IN_RING0
1209 RT_NOREF_PV(iGstReg);
1210#endif
1211
1212 /*
1213 * Compare the DR7s first.
1214 *
1215 * We only care about the enabled flags. GD is virtualized when we
1216 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
1217 * always have the LE and GE bits set, so no need to check and disable
1218 * stuff if they're cleared like we have to for the guest DR7.
1219 */
1220 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1221 /** @todo This isn't correct. BPs work without setting LE and GE under AMD-V. They are also documented as unsupported by P6+. */
1222 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
1223 uGstDr7 = 0;
1224 else if (!(uGstDr7 & X86_DR7_LE))
1225 uGstDr7 &= ~X86_DR7_LE_ALL;
1226 else if (!(uGstDr7 & X86_DR7_GE))
1227 uGstDr7 &= ~X86_DR7_GE_ALL;
1228
1229 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1230 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1231 {
1232 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1233
1234 /*
1235 * Ok, something is enabled. Recalc each of the breakpoints, taking
1236 * the VM debugger ones of the guest ones. In raw-mode context we will
1237 * not allow breakpoints with values inside the hypervisor area.
1238 */
1239 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
1240
1241 /* bp 0 */
1242 RTGCUINTREG uNewDr0;
1243 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1244 {
1245 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1246 uNewDr0 = DBGFBpGetDR0(pVM);
1247 }
1248 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1249 {
1250 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1251 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1252 }
1253 else
1254 uNewDr0 = 0;
1255
1256 /* bp 1 */
1257 RTGCUINTREG uNewDr1;
1258 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1259 {
1260 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1261 uNewDr1 = DBGFBpGetDR1(pVM);
1262 }
1263 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1264 {
1265 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1266 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1267 }
1268 else
1269 uNewDr1 = 0;
1270
1271 /* bp 2 */
1272 RTGCUINTREG uNewDr2;
1273 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1274 {
1275 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1276 uNewDr2 = DBGFBpGetDR2(pVM);
1277 }
1278 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1279 {
1280 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1281 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1282 }
1283 else
1284 uNewDr2 = 0;
1285
1286 /* bp 3 */
1287 RTGCUINTREG uNewDr3;
1288 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1289 {
1290 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1291 uNewDr3 = DBGFBpGetDR3(pVM);
1292 }
1293 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1294 {
1295 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1296 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1297 }
1298 else
1299 uNewDr3 = 0;
1300
1301 /*
1302 * Apply the updates.
1303 */
1304 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
1305 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1306 CPUMSetHyperDR3(pVCpu, uNewDr3);
1307 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1308 CPUMSetHyperDR2(pVCpu, uNewDr2);
1309 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1310 CPUMSetHyperDR1(pVCpu, uNewDr1);
1311 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1312 CPUMSetHyperDR0(pVCpu, uNewDr0);
1313 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1314 CPUMSetHyperDR7(pVCpu, uNewDr7);
1315 }
1316#ifdef IN_RING0
1317 else if (CPUMIsGuestDebugStateActive(pVCpu))
1318 {
1319 /*
1320 * Reload the register that was modified. Normally this won't happen
1321 * as we won't intercept DRx writes when not having the hyper debug
1322 * state loaded, but in case we do for some reason we'll simply deal
1323 * with it.
1324 */
1325 switch (iGstReg)
1326 {
1327 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
1328 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
1329 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
1330 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
1331 default:
1332 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
1333 }
1334 }
1335#endif
1336 else
1337 {
1338 /*
1339 * No active debug state any more. In raw-mode this means we have to
1340 * make sure DR7 has everything disabled now, if we armed it already.
1341 * In ring-0 we might end up here when just single stepping.
1342 */
1343#ifdef IN_RING0
1344 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
1345 {
1346 if (pVCpu->cpum.s.Hyper.dr[0])
1347 ASMSetDR0(0);
1348 if (pVCpu->cpum.s.Hyper.dr[1])
1349 ASMSetDR1(0);
1350 if (pVCpu->cpum.s.Hyper.dr[2])
1351 ASMSetDR2(0);
1352 if (pVCpu->cpum.s.Hyper.dr[3])
1353 ASMSetDR3(0);
1354 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
1355 }
1356#endif
1357 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
1358
1359 /* Clear all the registers. */
1360 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
1361 pVCpu->cpum.s.Hyper.dr[3] = 0;
1362 pVCpu->cpum.s.Hyper.dr[2] = 0;
1363 pVCpu->cpum.s.Hyper.dr[1] = 0;
1364 pVCpu->cpum.s.Hyper.dr[0] = 0;
1365
1366 }
1367 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1368 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1369 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1370 pVCpu->cpum.s.Hyper.dr[7]));
1371
1372 return VINF_SUCCESS;
1373}
1374
1375
1376/**
1377 * Set the guest XCR0 register.
1378 *
1379 * Will load additional state if the FPU state is already loaded (in ring-0 &
1380 * raw-mode context).
1381 *
1382 * @returns VINF_SUCCESS on success, VERR_CPUM_RAISE_GP_0 on invalid input
1383 * value.
1384 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1385 * @param uNewValue The new value.
1386 * @thread EMT(pVCpu)
1387 */
1388VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue)
1389{
1390 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_XCRx);
1391 if ( (uNewValue & ~pVCpu->CTX_SUFF(pVM)->cpum.s.fXStateGuestMask) == 0
1392 /* The X87 bit cannot be cleared. */
1393 && (uNewValue & XSAVE_C_X87)
1394 /* AVX requires SSE. */
1395 && (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM
1396 /* AVX-512 requires YMM, SSE and all of its three components to be enabled. */
1397 && ( (uNewValue & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1398 || (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1399 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI) )
1400 )
1401 {
1402 pVCpu->cpum.s.Guest.aXcr[0] = uNewValue;
1403
1404 /* If more state components are enabled, we need to take care to load
1405 them if the FPU/SSE state is already loaded. May otherwise leak
1406 host state to the guest. */
1407 uint64_t fNewComponents = ~pVCpu->cpum.s.Guest.fXStateMask & uNewValue;
1408 if (fNewComponents)
1409 {
1410#ifdef IN_RING0
1411 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
1412 {
1413 if (pVCpu->cpum.s.Guest.fXStateMask != 0)
1414 /* Adding more components. */
1415 ASMXRstor(&pVCpu->cpum.s.Guest.XState, fNewComponents);
1416 else
1417 {
1418 /* We're switching from FXSAVE/FXRSTOR to XSAVE/XRSTOR. */
1419 pVCpu->cpum.s.Guest.fXStateMask |= XSAVE_C_X87 | XSAVE_C_SSE;
1420 if (uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE))
1421 ASMXRstor(&pVCpu->cpum.s.Guest.XState, uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE));
1422 }
1423 }
1424#endif
1425 pVCpu->cpum.s.Guest.fXStateMask |= uNewValue;
1426 }
1427 return VINF_SUCCESS;
1428 }
1429 return VERR_CPUM_RAISE_GP_0;
1430}
1431
1432
1433/**
1434 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1435 *
1436 * @returns true if in real mode, otherwise false.
1437 * @param pVCpu The cross context virtual CPU structure.
1438 */
1439VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu)
1440{
1441 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1442 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
1443}
1444
1445
1446/**
1447 * Tests if the guest has the Page Size Extension enabled (PSE).
1448 *
1449 * @returns true if in real mode, otherwise false.
1450 * @param pVCpu The cross context virtual CPU structure.
1451 */
1452VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu)
1453{
1454 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
1455 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
1456 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
1457}
1458
1459
1460/**
1461 * Tests if the guest has the paging enabled (PG).
1462 *
1463 * @returns true if in real mode, otherwise false.
1464 * @param pVCpu The cross context virtual CPU structure.
1465 */
1466VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu)
1467{
1468 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1469 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
1470}
1471
1472
1473/**
1474 * Tests if the guest has the paging enabled (PG).
1475 *
1476 * @returns true if in real mode, otherwise false.
1477 * @param pVCpu The cross context virtual CPU structure.
1478 */
1479VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu)
1480{
1481 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1482 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
1483}
1484
1485
1486/**
1487 * Tests if the guest is running in real mode or not.
1488 *
1489 * @returns true if in real mode, otherwise false.
1490 * @param pVCpu The cross context virtual CPU structure.
1491 */
1492VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu)
1493{
1494 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1495 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1496}
1497
1498
1499/**
1500 * Tests if the guest is running in real or virtual 8086 mode.
1501 *
1502 * @returns @c true if it is, @c false if not.
1503 * @param pVCpu The cross context virtual CPU structure.
1504 */
1505VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu)
1506{
1507 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS);
1508 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1509 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
1510}
1511
1512
1513/**
1514 * Tests if the guest is running in protected or not.
1515 *
1516 * @returns true if in protected mode, otherwise false.
1517 * @param pVCpu The cross context virtual CPU structure.
1518 */
1519VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu)
1520{
1521 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1522 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1523}
1524
1525
1526/**
1527 * Tests if the guest is running in paged protected or not.
1528 *
1529 * @returns true if in paged protected mode, otherwise false.
1530 * @param pVCpu The cross context virtual CPU structure.
1531 */
1532VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu)
1533{
1534 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1535 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1536}
1537
1538
1539/**
1540 * Tests if the guest is running in long mode or not.
1541 *
1542 * @returns true if in long mode, otherwise false.
1543 * @param pVCpu The cross context virtual CPU structure.
1544 */
1545VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu)
1546{
1547 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1548 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1549}
1550
1551
1552/**
1553 * Tests if the guest is running in PAE mode or not.
1554 *
1555 * @returns true if in PAE mode, otherwise false.
1556 * @param pVCpu The cross context virtual CPU structure.
1557 */
1558VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu)
1559{
1560 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1561 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1562 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1563 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
1564 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
1565 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
1566}
1567
1568
1569/**
1570 * Tests if the guest is running in 64 bits mode or not.
1571 *
1572 * @returns true if in 64 bits protected mode, otherwise false.
1573 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1574 */
1575VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
1576{
1577 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
1578 if (!CPUMIsGuestInLongMode(pVCpu))
1579 return false;
1580 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1581 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
1582}
1583
1584
1585/**
1586 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
1587 * registers.
1588 *
1589 * @returns true if in 64 bits protected mode, otherwise false.
1590 * @param pCtx Pointer to the current guest CPU context.
1591 */
1592VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
1593{
1594 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
1595}
1596
1597
1598/**
1599 * Sets the specified changed flags (CPUM_CHANGED_*).
1600 *
1601 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1602 * @param fChangedAdd The changed flags to add.
1603 */
1604VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd)
1605{
1606 pVCpu->cpum.s.fChanged |= fChangedAdd;
1607}
1608
1609
1610/**
1611 * Checks if the CPU supports the XSAVE and XRSTOR instruction.
1612 *
1613 * @returns true if supported.
1614 * @returns false if not supported.
1615 * @param pVM The cross context VM structure.
1616 */
1617VMMDECL(bool) CPUMSupportsXSave(PVM pVM)
1618{
1619 return pVM->cpum.s.HostFeatures.fXSaveRstor != 0;
1620}
1621
1622
1623/**
1624 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1625 * @returns true if used.
1626 * @returns false if not used.
1627 * @param pVM The cross context VM structure.
1628 */
1629VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1630{
1631 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
1632}
1633
1634
1635/**
1636 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1637 * @returns true if used.
1638 * @returns false if not used.
1639 * @param pVM The cross context VM structure.
1640 */
1641VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1642{
1643 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
1644}
1645
1646
1647/**
1648 * Checks if we activated the FPU/XMM state of the guest OS.
1649 *
1650 * Obsolete: This differs from CPUMIsGuestFPUStateLoaded() in that it refers to
1651 * the next time we'll be executing guest code, so it may return true for
1652 * 64-on-32 when we still haven't actually loaded the FPU status, just scheduled
1653 * it to be loaded the next time we go thru the world switcher
1654 * (CPUM_SYNC_FPU_STATE).
1655 *
1656 * @returns true / false.
1657 * @param pVCpu The cross context virtual CPU structure.
1658 */
1659VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
1660{
1661 bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1662 AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
1663 return fRet;
1664}
1665
1666
1667/**
1668 * Checks if we've really loaded the FPU/XMM state of the guest OS.
1669 *
1670 * @returns true / false.
1671 * @param pVCpu The cross context virtual CPU structure.
1672 */
1673VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu)
1674{
1675 bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1676 AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
1677 return fRet;
1678}
1679
1680
1681/**
1682 * Checks if we saved the FPU/XMM state of the host OS.
1683 *
1684 * @returns true / false.
1685 * @param pVCpu The cross context virtual CPU structure.
1686 */
1687VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu)
1688{
1689 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST);
1690}
1691
1692
1693/**
1694 * Checks if the guest debug state is active.
1695 *
1696 * @returns boolean
1697 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1698 */
1699VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
1700{
1701 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
1702}
1703
1704
1705/**
1706 * Checks if the hyper debug state is active.
1707 *
1708 * @returns boolean
1709 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1710 */
1711VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
1712{
1713 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
1714}
1715
1716
1717/**
1718 * Mark the guest's debug state as inactive.
1719 *
1720 * @returns boolean
1721 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1722 * @todo This API doesn't make sense any more.
1723 */
1724VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
1725{
1726 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
1727 NOREF(pVCpu);
1728}
1729
1730
1731/**
1732 * Get the current privilege level of the guest.
1733 *
1734 * @returns CPL
1735 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1736 */
1737VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
1738{
1739 /*
1740 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
1741 *
1742 * Note! We used to check CS.DPL here, assuming it was always equal to
1743 * CPL even if a conforming segment was loaded. But this turned out to
1744 * only apply to older AMD-V. With VT-x we had an ACP2 regression
1745 * during install after a far call to ring 2 with VT-x. Then on newer
1746 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
1747 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
1748 *
1749 * So, forget CS.DPL, always use SS.DPL.
1750 *
1751 * Note! The SS RPL is always equal to the CPL, while the CS RPL
1752 * isn't necessarily equal if the segment is conforming.
1753 * See section 4.11.1 in the AMD manual.
1754 *
1755 * Update: Where the heck does it say CS.RPL can differ from CPL other than
1756 * right after real->prot mode switch and when in V8086 mode? That
1757 * section says the RPL specified in a direct transfere (call, jmp,
1758 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
1759 * it would be impossible for an exception handle or the iret
1760 * instruction to figure out whether SS:ESP are part of the frame
1761 * or not. VBox or qemu bug must've lead to this misconception.
1762 *
1763 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
1764 * selector into SS with an RPL other than the CPL when CPL != 3 and
1765 * we're in 64-bit mode. The intel dev box doesn't allow this, on
1766 * RPL = CPL. Weird.
1767 */
1768 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
1769 uint32_t uCpl;
1770 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1771 {
1772 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1773 {
1774 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
1775 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
1776 else
1777 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
1778 }
1779 else
1780 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
1781 }
1782 else
1783 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
1784 return uCpl;
1785}
1786
1787
1788/**
1789 * Gets the current guest CPU mode.
1790 *
1791 * If paging mode is what you need, check out PGMGetGuestMode().
1792 *
1793 * @returns The CPU mode.
1794 * @param pVCpu The cross context virtual CPU structure.
1795 */
1796VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
1797{
1798 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1799 CPUMMODE enmMode;
1800 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1801 enmMode = CPUMMODE_REAL;
1802 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1803 enmMode = CPUMMODE_PROTECTED;
1804 else
1805 enmMode = CPUMMODE_LONG;
1806
1807 return enmMode;
1808}
1809
1810
1811/**
1812 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
1813 *
1814 * @returns 16, 32 or 64.
1815 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1816 */
1817VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
1818{
1819 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1820
1821 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1822 return 16;
1823
1824 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1825 {
1826 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1827 return 16;
1828 }
1829
1830 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1831 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1832 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1833 return 64;
1834
1835 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1836 return 32;
1837
1838 return 16;
1839}
1840
1841
1842VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
1843{
1844 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1845
1846 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1847 return DISCPUMODE_16BIT;
1848
1849 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1850 {
1851 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1852 return DISCPUMODE_16BIT;
1853 }
1854
1855 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1856 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1857 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1858 return DISCPUMODE_64BIT;
1859
1860 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1861 return DISCPUMODE_32BIT;
1862
1863 return DISCPUMODE_16BIT;
1864}
1865
1866
1867/**
1868 * Gets the guest MXCSR_MASK value.
1869 *
1870 * This does not access the x87 state, but the value we determined at VM
1871 * initialization.
1872 *
1873 * @returns MXCSR mask.
1874 * @param pVM The cross context VM structure.
1875 */
1876VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM)
1877{
1878 return pVM->cpum.s.GuestInfo.fMxCsrMask;
1879}
1880
1881
1882/**
1883 * Returns whether the guest has physical interrupts enabled.
1884 *
1885 * @returns @c true if interrupts are enabled, @c false otherwise.
1886 * @param pVCpu The cross context virtual CPU structure.
1887 *
1888 * @remarks Warning! This function does -not- take into account the global-interrupt
1889 * flag (GIF).
1890 */
1891VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu)
1892{
1893 switch (CPUMGetGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest))
1894 {
1895 case CPUMHWVIRT_NONE:
1896 default:
1897 return pVCpu->cpum.s.Guest.eflags.Bits.u1IF;
1898 case CPUMHWVIRT_VMX:
1899 return CPUMIsGuestVmxPhysIntrEnabled(&pVCpu->cpum.s.Guest);
1900 case CPUMHWVIRT_SVM:
1901 return CPUMIsGuestSvmPhysIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
1902 }
1903}
1904
1905
1906/**
1907 * Returns whether the nested-guest has virtual interrupts enabled.
1908 *
1909 * @returns @c true if interrupts are enabled, @c false otherwise.
1910 * @param pVCpu The cross context virtual CPU structure.
1911 *
1912 * @remarks Warning! This function does -not- take into account the global-interrupt
1913 * flag (GIF).
1914 */
1915VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu)
1916{
1917 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1918 Assert(CPUMIsGuestInNestedHwvirtMode(pCtx));
1919
1920 if (CPUMIsGuestInVmxNonRootMode(pCtx))
1921 return CPUMIsGuestVmxVirtIntrEnabled(pCtx);
1922
1923 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1924 return CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
1925}
1926
1927
1928/**
1929 * Calculates the interruptiblity of the guest.
1930 *
1931 * @returns Interruptibility level.
1932 * @param pVCpu The cross context virtual CPU structure.
1933 */
1934VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu)
1935{
1936#if 1
1937 /* Global-interrupt flag blocks pretty much everything we care about here. */
1938 if (CPUMGetGuestGif(&pVCpu->cpum.s.Guest))
1939 {
1940 /*
1941 * Physical interrupts are primarily blocked using EFLAGS. However, we cannot access
1942 * it directly here. If and how EFLAGS are used depends on the context (nested-guest
1943 * or raw-mode). Hence we use the function below which handles the details.
1944 */
1945 if ( pVCpu->cpum.s.Guest.fInhibit == 0
1946 || ( !(pVCpu->cpum.s.Guest.fInhibit & CPUMCTX_INHIBIT_NMI)
1947 && pVCpu->cpum.s.Guest.uRipInhibitInt != pVCpu->cpum.s.Guest.rip))
1948 {
1949 /** @todo OPT: this next call should be inlined! */
1950 if (CPUMIsGuestPhysIntrEnabled(pVCpu))
1951 {
1952 /** @todo OPT: type this out as it repeats tests. */
1953 if ( !CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest)
1954 || CPUMIsGuestVirtIntrEnabled(pVCpu))
1955 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1956
1957 /* Physical interrupts are enabled, but nested-guest virtual interrupts are disabled. */
1958 return CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED;
1959 }
1960 return CPUMINTERRUPTIBILITY_INT_DISABLED;
1961 }
1962
1963 /*
1964 * Blocking the delivery of NMIs during an interrupt shadow is CPU implementation
1965 * specific. Therefore, in practice, we can't deliver an NMI in an interrupt shadow.
1966 * However, there is some uncertainity regarding the converse, i.e. whether
1967 * NMI-blocking until IRET blocks delivery of physical interrupts.
1968 *
1969 * See Intel spec. 25.4.1 "Event Blocking".
1970 */
1971 /** @todo r=bird: The above comment mixes up VMX root-mode and non-root. Section
1972 * 25.4.1 is only applicable to VMX non-root mode. In root mode /
1973 * non-VMX mode, I have not see any evidence in the intel manuals that
1974 * NMIs are not blocked when in an interrupt shadow. Section "6.7
1975 * NONMASKABLE INTERRUPT (NMI)" in SDM 3A seems pretty clear to me.
1976 */
1977 if (!(pVCpu->cpum.s.Guest.fInhibit & CPUMCTX_INHIBIT_NMI))
1978 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1979 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1980 }
1981 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1982#else
1983 if (pVCpu->cpum.s.Guest.rflags.Bits.u1IF)
1984 {
1985 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
1986 {
1987 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
1988 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1989
1990 /** @todo does blocking NMIs mean interrupts are also inhibited? */
1991 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1992 {
1993 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1994 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1995 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1996 }
1997 AssertFailed();
1998 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1999 }
2000 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
2001 }
2002 else
2003 {
2004 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
2005 {
2006 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2007 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
2008 return CPUMINTERRUPTIBILITY_INT_DISABLED;
2009 }
2010 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
2011 }
2012#endif
2013}
2014
2015
2016/**
2017 * Checks whether the SVM nested-guest has physical interrupts enabled.
2018 *
2019 * @returns true if interrupts are enabled, false otherwise.
2020 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2021 * @param pCtx The guest-CPU context.
2022 *
2023 * @remarks This does -not- take into account the global-interrupt flag.
2024 */
2025VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2026{
2027 /** @todo Optimization: Avoid this function call and use a pointer to the
2028 * relevant eflags instead (setup during VMRUN instruction emulation). */
2029 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2030
2031 X86EFLAGS fEFlags;
2032 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, pCtx))
2033 fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
2034 else
2035 fEFlags.u = pCtx->eflags.u;
2036
2037 return fEFlags.Bits.u1IF;
2038}
2039
2040
2041/**
2042 * Checks whether the SVM nested-guest is in a state to receive virtual (setup
2043 * for injection by VMRUN instruction) interrupts.
2044 *
2045 * @returns VBox status code.
2046 * @retval true if it's ready, false otherwise.
2047 *
2048 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2049 * @param pCtx The guest-CPU context.
2050 */
2051VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2052{
2053 RT_NOREF(pVCpu);
2054 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2055
2056 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.Vmcb.ctrl;
2057 PCSVMINTCTRL pVmcbIntCtrl = &pVmcbCtrl->IntCtrl;
2058 Assert(!pVmcbIntCtrl->n.u1VGifEnable); /* We don't support passing virtual-GIF feature to the guest yet. */
2059 if ( !pVmcbIntCtrl->n.u1IgnoreTPR
2060 && pVmcbIntCtrl->n.u4VIntrPrio <= pVmcbIntCtrl->n.u8VTPR)
2061 return false;
2062
2063 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2064}
2065
2066
2067/**
2068 * Gets the pending SVM nested-guest interruptvector.
2069 *
2070 * @returns The nested-guest interrupt to inject.
2071 * @param pCtx The guest-CPU context.
2072 */
2073VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx)
2074{
2075 return pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u8VIntrVector;
2076}
2077
2078
2079/**
2080 * Restores the host-state from the host-state save area as part of a \#VMEXIT.
2081 *
2082 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2083 * @param pCtx The guest-CPU context.
2084 */
2085VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx)
2086{
2087 /*
2088 * Reload the guest's "host state".
2089 */
2090 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2091 pCtx->es = pHostState->es;
2092 pCtx->cs = pHostState->cs;
2093 pCtx->ss = pHostState->ss;
2094 pCtx->ds = pHostState->ds;
2095 pCtx->gdtr = pHostState->gdtr;
2096 pCtx->idtr = pHostState->idtr;
2097 CPUMSetGuestEferMsrNoChecks(pVCpu, pCtx->msrEFER, pHostState->uEferMsr);
2098 CPUMSetGuestCR0(pVCpu, pHostState->uCr0 | X86_CR0_PE);
2099 pCtx->cr3 = pHostState->uCr3;
2100 CPUMSetGuestCR4(pVCpu, pHostState->uCr4);
2101 pCtx->rflags = pHostState->rflags;
2102 pCtx->rflags.Bits.u1VM = 0;
2103 pCtx->rip = pHostState->uRip;
2104 pCtx->rsp = pHostState->uRsp;
2105 pCtx->rax = pHostState->uRax;
2106 pCtx->dr[7] &= ~(X86_DR7_ENABLED_MASK | X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2107 pCtx->dr[7] |= X86_DR7_RA1_MASK;
2108 Assert(pCtx->ss.Attr.n.u2Dpl == 0);
2109
2110 /** @todo if RIP is not canonical or outside the CS segment limit, we need to
2111 * raise \#GP(0) in the guest. */
2112
2113 /** @todo check the loaded host-state for consistency. Figure out what
2114 * exactly this involves? */
2115}
2116
2117
2118/**
2119 * Saves the host-state to the host-state save area as part of a VMRUN.
2120 *
2121 * @param pCtx The guest-CPU context.
2122 * @param cbInstr The length of the VMRUN instruction in bytes.
2123 */
2124VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr)
2125{
2126 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2127 pHostState->es = pCtx->es;
2128 pHostState->cs = pCtx->cs;
2129 pHostState->ss = pCtx->ss;
2130 pHostState->ds = pCtx->ds;
2131 pHostState->gdtr = pCtx->gdtr;
2132 pHostState->idtr = pCtx->idtr;
2133 pHostState->uEferMsr = pCtx->msrEFER;
2134 pHostState->uCr0 = pCtx->cr0;
2135 pHostState->uCr3 = pCtx->cr3;
2136 pHostState->uCr4 = pCtx->cr4;
2137 pHostState->rflags = pCtx->rflags;
2138 pHostState->uRip = pCtx->rip + cbInstr;
2139 pHostState->uRsp = pCtx->rsp;
2140 pHostState->uRax = pCtx->rax;
2141}
2142
2143
2144/**
2145 * Applies the TSC offset of a nested-guest if any and returns the TSC value for the
2146 * nested-guest.
2147 *
2148 * @returns The TSC offset after applying any nested-guest TSC offset.
2149 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2150 * @param uTscValue The guest TSC.
2151 *
2152 * @sa CPUMRemoveNestedGuestTscOffset.
2153 */
2154VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2155{
2156 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2157 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2158 {
2159 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2160 return uTscValue + pCtx->hwvirt.vmx.Vmcs.u64TscOffset.u;
2161 return uTscValue;
2162 }
2163
2164 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2165 {
2166 uint64_t offTsc;
2167 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2168 offTsc = pCtx->hwvirt.svm.Vmcb.ctrl.u64TSCOffset;
2169 return uTscValue + offTsc;
2170 }
2171 return uTscValue;
2172}
2173
2174
2175/**
2176 * Removes the TSC offset of a nested-guest if any and returns the TSC value for the
2177 * guest.
2178 *
2179 * @returns The TSC offset after removing any nested-guest TSC offset.
2180 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2181 * @param uTscValue The nested-guest TSC.
2182 *
2183 * @sa CPUMApplyNestedGuestTscOffset.
2184 */
2185VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2186{
2187 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2188 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2189 {
2190 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2191 return uTscValue - pCtx->hwvirt.vmx.Vmcs.u64TscOffset.u;
2192 return uTscValue;
2193 }
2194
2195 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2196 {
2197 uint64_t offTsc;
2198 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2199 offTsc = pCtx->hwvirt.svm.Vmcb.ctrl.u64TSCOffset;
2200 return uTscValue - offTsc;
2201 }
2202 return uTscValue;
2203}
2204
2205
2206/**
2207 * Used to dynamically imports state residing in NEM or HM.
2208 *
2209 * This is a worker for the CPUM_IMPORT_EXTRN_RET() macro and various IEM ones.
2210 *
2211 * @returns VBox status code.
2212 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2213 * @param fExtrnImport The fields to import.
2214 * @thread EMT(pVCpu)
2215 */
2216VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport)
2217{
2218 VMCPU_ASSERT_EMT(pVCpu);
2219 if (pVCpu->cpum.s.Guest.fExtrn & fExtrnImport)
2220 {
2221 switch (pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_KEEPER_MASK)
2222 {
2223 case CPUMCTX_EXTRN_KEEPER_NEM:
2224 {
2225 int rc = NEMImportStateOnDemand(pVCpu, fExtrnImport);
2226 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2227 return rc;
2228 }
2229
2230 case CPUMCTX_EXTRN_KEEPER_HM:
2231 {
2232#ifdef IN_RING0
2233 int rc = HMR0ImportStateOnDemand(pVCpu, fExtrnImport);
2234 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2235 return rc;
2236#else
2237 AssertLogRelMsgFailed(("TODO Fetch HM state: %#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport));
2238 return VINF_SUCCESS;
2239#endif
2240 }
2241 default:
2242 AssertLogRelMsgFailedReturn(("%#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport), VERR_CPUM_IPE_2);
2243 }
2244 }
2245 return VINF_SUCCESS;
2246}
2247
2248
2249/**
2250 * Gets valid CR4 bits for the guest.
2251 *
2252 * @returns Valid CR4 bits.
2253 * @param pVM The cross context VM structure.
2254 */
2255VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM)
2256{
2257 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
2258 uint64_t fMask = X86_CR4_VME | X86_CR4_PVI
2259 | X86_CR4_TSD | X86_CR4_DE
2260 | X86_CR4_MCE | X86_CR4_PCE;
2261 if (pGuestFeatures->fPae)
2262 fMask |= X86_CR4_PAE;
2263 if (pGuestFeatures->fPge)
2264 fMask |= X86_CR4_PGE;
2265 if (pGuestFeatures->fPse)
2266 fMask |= X86_CR4_PSE;
2267 if (pGuestFeatures->fFxSaveRstor)
2268 fMask |= X86_CR4_OSFXSR;
2269 if (pGuestFeatures->fVmx)
2270 fMask |= X86_CR4_VMXE;
2271 if (pGuestFeatures->fXSaveRstor)
2272 fMask |= X86_CR4_OSXSAVE;
2273 if (pGuestFeatures->fPcid)
2274 fMask |= X86_CR4_PCIDE;
2275 if (pGuestFeatures->fFsGsBase)
2276 fMask |= X86_CR4_FSGSBASE;
2277 if (pGuestFeatures->fSse)
2278 fMask |= X86_CR4_OSXMMEEXCPT;
2279 return fMask;
2280}
2281
2282
2283/**
2284 * Sets the PAE PDPEs for the guest.
2285 *
2286 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2287 * @param paPaePdpes The PAE PDPEs to set.
2288 */
2289VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes)
2290{
2291 Assert(paPaePdpes);
2292 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
2293 pVCpu->cpum.s.Guest.aPaePdpes[i].u = paPaePdpes[i].u;
2294 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
2295}
2296
2297
2298/**
2299 * Gets the PAE PDPTEs for the guest.
2300 *
2301 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2302 * @param paPaePdpes Where to store the PAE PDPEs.
2303 */
2304VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes)
2305{
2306 Assert(paPaePdpes);
2307 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
2308 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
2309 paPaePdpes[i].u = pVCpu->cpum.s.Guest.aPaePdpes[i].u;
2310}
2311
2312
2313/**
2314 * Starts a VMX-preemption timer to expire as specified by the nested hypervisor.
2315 *
2316 * @returns VBox status code.
2317 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2318 * @param uTimer The VMCS preemption timer value.
2319 * @param cShift The VMX-preemption timer shift (usually based on guest
2320 * VMX MSR rate).
2321 * @param pu64EntryTick Where to store the current tick when the timer is
2322 * programmed.
2323 * @thread EMT(pVCpu)
2324 */
2325VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick)
2326{
2327 Assert(uTimer);
2328 Assert(cShift <= 31);
2329 Assert(pu64EntryTick);
2330 VMCPU_ASSERT_EMT(pVCpu);
2331 uint64_t const cTicksToNext = uTimer << cShift;
2332 return TMTimerSetRelative(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.hNestedVmxPreemptTimer, cTicksToNext, pu64EntryTick);
2333}
2334
2335
2336/**
2337 * Stops the VMX-preemption timer from firing.
2338 *
2339 * @returns VBox status code.
2340 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2341 * @thread EMT.
2342 *
2343 * @remarks This can be called during VM reset, so we cannot assume it will be on
2344 * the EMT corresponding to @c pVCpu.
2345 */
2346VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu)
2347{
2348 /*
2349 * CPUM gets initialized before TM, so we defer creation of timers till CPUMR3InitCompleted().
2350 * However, we still get called during CPUMR3Init() and hence we need to check if we have
2351 * a valid timer object before trying to stop it.
2352 */
2353 int rc;
2354 TMTIMERHANDLE hTimer = pVCpu->cpum.s.hNestedVmxPreemptTimer;
2355 if (hTimer != NIL_TMTIMERHANDLE)
2356 {
2357 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2358 rc = TMTimerLock(pVM, hTimer, VERR_IGNORED);
2359 if (rc == VINF_SUCCESS)
2360 {
2361 if (TMTimerIsActive(pVM, hTimer))
2362 TMTimerStop(pVM, hTimer);
2363 TMTimerUnlock(pVM, hTimer);
2364 }
2365 }
2366 else
2367 rc = VERR_NOT_FOUND;
2368 return rc;
2369}
2370
2371
2372/**
2373 * Gets the read and write permission bits for an MSR in an MSR bitmap.
2374 *
2375 * @returns VMXMSRPM_XXX - the MSR permission.
2376 * @param pvMsrBitmap Pointer to the MSR bitmap.
2377 * @param idMsr The MSR to get permissions for.
2378 *
2379 * @sa hmR0VmxSetMsrPermission.
2380 */
2381VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr)
2382{
2383 AssertPtrReturn(pvMsrBitmap, VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR);
2384
2385 uint8_t const * const pbMsrBitmap = (uint8_t const * const)pvMsrBitmap;
2386
2387 /*
2388 * MSR Layout:
2389 * Byte index MSR range Interpreted as
2390 * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
2391 * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
2392 * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
2393 * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
2394 *
2395 * A bit corresponding to an MSR within the above range causes a VM-exit
2396 * if the bit is 1 on executions of RDMSR/WRMSR. If an MSR falls out of
2397 * the MSR range, it always cause a VM-exit.
2398 *
2399 * See Intel spec. 24.6.9 "MSR-Bitmap Address".
2400 */
2401 uint32_t const offBitmapRead = 0;
2402 uint32_t const offBitmapWrite = 0x800;
2403 uint32_t offMsr;
2404 uint32_t iBit;
2405 if (idMsr <= UINT32_C(0x00001fff))
2406 {
2407 offMsr = 0;
2408 iBit = idMsr;
2409 }
2410 else if (idMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
2411 {
2412 offMsr = 0x400;
2413 iBit = idMsr - UINT32_C(0xc0000000);
2414 }
2415 else
2416 {
2417 LogFunc(("Warning! Out of range MSR %#RX32\n", idMsr));
2418 return VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR;
2419 }
2420
2421 /*
2422 * Get the MSR read permissions.
2423 */
2424 uint32_t fRet;
2425 uint32_t const offMsrRead = offBitmapRead + offMsr;
2426 Assert(offMsrRead + (iBit >> 3) < offBitmapWrite);
2427 if (ASMBitTest(pbMsrBitmap, (offMsrRead << 3) + iBit))
2428 fRet = VMXMSRPM_EXIT_RD;
2429 else
2430 fRet = VMXMSRPM_ALLOW_RD;
2431
2432 /*
2433 * Get the MSR write permissions.
2434 */
2435 uint32_t const offMsrWrite = offBitmapWrite + offMsr;
2436 Assert(offMsrWrite + (iBit >> 3) < X86_PAGE_4K_SIZE);
2437 if (ASMBitTest(pbMsrBitmap, (offMsrWrite << 3) + iBit))
2438 fRet |= VMXMSRPM_EXIT_WR;
2439 else
2440 fRet |= VMXMSRPM_ALLOW_WR;
2441
2442 Assert(VMXMSRPM_IS_FLAG_VALID(fRet));
2443 return fRet;
2444}
2445
2446
2447/**
2448 * Checks the permission bits for the specified I/O port from the given I/O bitmap
2449 * to see if causes a VM-exit.
2450 *
2451 * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
2452 * @param pbIoBitmap Pointer to I/O bitmap.
2453 * @param uPort The I/O port being accessed.
2454 * @param cbAccess e size of the I/O access in bytes (1, 2 or 4 bytes).
2455 */
2456static bool cpumGetVmxIoBitmapPermission(uint8_t const *pbIoBitmap, uint16_t uPort, uint8_t cbAccess)
2457{
2458 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
2459
2460 /*
2461 * If the I/O port access wraps around the 16-bit port I/O space, we must cause a
2462 * VM-exit.
2463 *
2464 * Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc are valid and do not
2465 * constitute a wrap around. However, reading 2 bytes at port 0xffff or 4 bytes
2466 * from port 0xffff/0xfffe/0xfffd constitute a wrap around. In other words, any
2467 * access to -both- ports 0xffff and port 0 is a wrap around.
2468 *
2469 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2470 */
2471 uint32_t const uPortLast = uPort + cbAccess;
2472 if (uPortLast > 0x10000)
2473 return true;
2474
2475 /*
2476 * If any bit corresponding to the I/O access is set, we must cause a VM-exit.
2477 */
2478 uint16_t const offPerm = uPort >> 3; /* Byte offset of the port. */
2479 uint16_t const idxPermBit = uPort - (offPerm << 3); /* Bit offset within byte. */
2480 Assert(idxPermBit < 8);
2481 static const uint8_t s_afMask[] = { 0x0, 0x1, 0x3, 0x7, 0xf }; /* Bit-mask for all access sizes. */
2482 uint16_t const fMask = s_afMask[cbAccess] << idxPermBit; /* Bit-mask of the access. */
2483
2484 /* Fetch 8 or 16-bits depending on whether the access spans 8-bit boundary. */
2485 RTUINT16U uPerm;
2486 uPerm.s.Lo = pbIoBitmap[offPerm];
2487 if (idxPermBit + cbAccess > 8)
2488 uPerm.s.Hi = pbIoBitmap[offPerm + 1];
2489 else
2490 uPerm.s.Hi = 0;
2491
2492 /* If any bit for the access is 1, we must cause a VM-exit. */
2493 if (uPerm.u & fMask)
2494 return true;
2495
2496 return false;
2497}
2498
2499
2500/**
2501 * Returns whether the given VMCS field is valid and supported for the guest.
2502 *
2503 * @param pVM The cross context VM structure.
2504 * @param u64VmcsField The VMCS field.
2505 *
2506 * @remarks This takes into account the CPU features exposed to the guest.
2507 */
2508VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField)
2509{
2510 uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
2511 uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
2512 if (!uFieldEncHi)
2513 { /* likely */ }
2514 else
2515 return false;
2516
2517 PCCPUMFEATURES pFeat = &pVM->cpum.s.GuestFeatures;
2518 switch (uFieldEncLo)
2519 {
2520 /*
2521 * 16-bit fields.
2522 */
2523 /* Control fields. */
2524 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
2525 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
2526 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
2527
2528 /* Guest-state fields. */
2529 case VMX_VMCS16_GUEST_ES_SEL:
2530 case VMX_VMCS16_GUEST_CS_SEL:
2531 case VMX_VMCS16_GUEST_SS_SEL:
2532 case VMX_VMCS16_GUEST_DS_SEL:
2533 case VMX_VMCS16_GUEST_FS_SEL:
2534 case VMX_VMCS16_GUEST_GS_SEL:
2535 case VMX_VMCS16_GUEST_LDTR_SEL:
2536 case VMX_VMCS16_GUEST_TR_SEL: return true;
2537 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
2538 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
2539
2540 /* Host-state fields. */
2541 case VMX_VMCS16_HOST_ES_SEL:
2542 case VMX_VMCS16_HOST_CS_SEL:
2543 case VMX_VMCS16_HOST_SS_SEL:
2544 case VMX_VMCS16_HOST_DS_SEL:
2545 case VMX_VMCS16_HOST_FS_SEL:
2546 case VMX_VMCS16_HOST_GS_SEL:
2547 case VMX_VMCS16_HOST_TR_SEL: return true;
2548
2549 /*
2550 * 64-bit fields.
2551 */
2552 /* Control fields. */
2553 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
2554 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
2555 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
2556 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
2557 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
2558 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
2559 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
2560 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
2561 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
2562 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
2563 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
2564 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
2565 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
2566 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
2567 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
2568 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
2569 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
2570 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
2571 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
2572 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
2573 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
2574 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
2575 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
2576 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
2577 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
2578 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
2579 case VMX_VMCS64_CTRL_EPTP_FULL:
2580 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
2581 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
2582 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
2583 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
2584 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
2585 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
2586 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
2587 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
2588 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
2589 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
2590 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
2591 {
2592 PCVMCPU pVCpu = pVM->CTX_SUFF(apCpus)[0];
2593 uint64_t const uVmFuncMsr = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
2594 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
2595 }
2596 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
2597 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
2598 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
2599 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
2600 case VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL:
2601 case VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
2602 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
2603 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
2604 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
2605 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
2606 case VMX_VMCS64_CTRL_PROC_EXEC3_FULL:
2607 case VMX_VMCS64_CTRL_PROC_EXEC3_HIGH: return pFeat->fVmxTertiaryExecCtls;
2608
2609 /* Read-only data fields. */
2610 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
2611 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
2612
2613 /* Guest-state fields. */
2614 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
2615 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
2616 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
2617 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
2618 case VMX_VMCS64_GUEST_PAT_FULL:
2619 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
2620 case VMX_VMCS64_GUEST_EFER_FULL:
2621 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
2622 case VMX_VMCS64_GUEST_PDPTE0_FULL:
2623 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
2624 case VMX_VMCS64_GUEST_PDPTE1_FULL:
2625 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
2626 case VMX_VMCS64_GUEST_PDPTE2_FULL:
2627 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
2628 case VMX_VMCS64_GUEST_PDPTE3_FULL:
2629 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
2630
2631 /* Host-state fields. */
2632 case VMX_VMCS64_HOST_PAT_FULL:
2633 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
2634 case VMX_VMCS64_HOST_EFER_FULL:
2635 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
2636
2637 /*
2638 * 32-bit fields.
2639 */
2640 /* Control fields. */
2641 case VMX_VMCS32_CTRL_PIN_EXEC:
2642 case VMX_VMCS32_CTRL_PROC_EXEC:
2643 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
2644 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
2645 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
2646 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
2647 case VMX_VMCS32_CTRL_EXIT:
2648 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
2649 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
2650 case VMX_VMCS32_CTRL_ENTRY:
2651 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
2652 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
2653 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
2654 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
2655 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
2656 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
2657 case VMX_VMCS32_CTRL_PLE_GAP:
2658 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
2659
2660 /* Read-only data fields. */
2661 case VMX_VMCS32_RO_VM_INSTR_ERROR:
2662 case VMX_VMCS32_RO_EXIT_REASON:
2663 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
2664 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
2665 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
2666 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
2667 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
2668 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
2669
2670 /* Guest-state fields. */
2671 case VMX_VMCS32_GUEST_ES_LIMIT:
2672 case VMX_VMCS32_GUEST_CS_LIMIT:
2673 case VMX_VMCS32_GUEST_SS_LIMIT:
2674 case VMX_VMCS32_GUEST_DS_LIMIT:
2675 case VMX_VMCS32_GUEST_FS_LIMIT:
2676 case VMX_VMCS32_GUEST_GS_LIMIT:
2677 case VMX_VMCS32_GUEST_LDTR_LIMIT:
2678 case VMX_VMCS32_GUEST_TR_LIMIT:
2679 case VMX_VMCS32_GUEST_GDTR_LIMIT:
2680 case VMX_VMCS32_GUEST_IDTR_LIMIT:
2681 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
2682 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
2683 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
2684 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
2685 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
2686 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
2687 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
2688 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
2689 case VMX_VMCS32_GUEST_INT_STATE:
2690 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
2691 case VMX_VMCS32_GUEST_SMBASE:
2692 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
2693 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
2694
2695 /* Host-state fields. */
2696 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
2697
2698 /*
2699 * Natural-width fields.
2700 */
2701 /* Control fields. */
2702 case VMX_VMCS_CTRL_CR0_MASK:
2703 case VMX_VMCS_CTRL_CR4_MASK:
2704 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
2705 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
2706 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
2707 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
2708 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
2709 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
2710
2711 /* Read-only data fields. */
2712 case VMX_VMCS_RO_EXIT_QUALIFICATION:
2713 case VMX_VMCS_RO_IO_RCX:
2714 case VMX_VMCS_RO_IO_RSI:
2715 case VMX_VMCS_RO_IO_RDI:
2716 case VMX_VMCS_RO_IO_RIP:
2717 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
2718
2719 /* Guest-state fields. */
2720 case VMX_VMCS_GUEST_CR0:
2721 case VMX_VMCS_GUEST_CR3:
2722 case VMX_VMCS_GUEST_CR4:
2723 case VMX_VMCS_GUEST_ES_BASE:
2724 case VMX_VMCS_GUEST_CS_BASE:
2725 case VMX_VMCS_GUEST_SS_BASE:
2726 case VMX_VMCS_GUEST_DS_BASE:
2727 case VMX_VMCS_GUEST_FS_BASE:
2728 case VMX_VMCS_GUEST_GS_BASE:
2729 case VMX_VMCS_GUEST_LDTR_BASE:
2730 case VMX_VMCS_GUEST_TR_BASE:
2731 case VMX_VMCS_GUEST_GDTR_BASE:
2732 case VMX_VMCS_GUEST_IDTR_BASE:
2733 case VMX_VMCS_GUEST_DR7:
2734 case VMX_VMCS_GUEST_RSP:
2735 case VMX_VMCS_GUEST_RIP:
2736 case VMX_VMCS_GUEST_RFLAGS:
2737 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
2738 case VMX_VMCS_GUEST_SYSENTER_ESP:
2739 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
2740
2741 /* Host-state fields. */
2742 case VMX_VMCS_HOST_CR0:
2743 case VMX_VMCS_HOST_CR3:
2744 case VMX_VMCS_HOST_CR4:
2745 case VMX_VMCS_HOST_FS_BASE:
2746 case VMX_VMCS_HOST_GS_BASE:
2747 case VMX_VMCS_HOST_TR_BASE:
2748 case VMX_VMCS_HOST_GDTR_BASE:
2749 case VMX_VMCS_HOST_IDTR_BASE:
2750 case VMX_VMCS_HOST_SYSENTER_ESP:
2751 case VMX_VMCS_HOST_SYSENTER_EIP:
2752 case VMX_VMCS_HOST_RSP:
2753 case VMX_VMCS_HOST_RIP: return true;
2754 }
2755
2756 return false;
2757}
2758
2759
2760/**
2761 * Checks whether the given I/O access should cause a nested-guest VM-exit.
2762 *
2763 * @returns @c true if it causes a VM-exit, @c false otherwise.
2764 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2765 * @param u16Port The I/O port being accessed.
2766 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
2767 */
2768VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
2769{
2770 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2771 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_UNCOND_IO_EXIT))
2772 return true;
2773
2774 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_IO_BITMAPS))
2775 return cpumGetVmxIoBitmapPermission(pCtx->hwvirt.vmx.abIoBitmap, u16Port, cbAccess);
2776
2777 return false;
2778}
2779
2780
2781/**
2782 * Checks whether the Mov-to-CR3 instruction causes a nested-guest VM-exit.
2783 *
2784 * @returns @c true if it causes a VM-exit, @c false otherwise.
2785 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2786 * @param uNewCr3 The CR3 value being written.
2787 */
2788VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3)
2789{
2790 /*
2791 * If the CR3-load exiting control is set and the new CR3 value does not
2792 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
2793 *
2794 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2795 */
2796 PCCPUMCTX const pCtx = &pVCpu->cpum.s.Guest;
2797 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_CR3_LOAD_EXIT))
2798 {
2799 uint32_t const uCr3TargetCount = pCtx->hwvirt.vmx.Vmcs.u32Cr3TargetCount;
2800 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
2801
2802 /* If the CR3-target count is 0, cause a VM-exit. */
2803 if (uCr3TargetCount == 0)
2804 return true;
2805
2806 /* If the CR3 being written doesn't match any of the target values, cause a VM-exit. */
2807 AssertCompile(VMX_V_CR3_TARGET_COUNT == 4);
2808 if ( uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target0.u
2809 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target1.u
2810 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target2.u
2811 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target3.u)
2812 return true;
2813 }
2814 return false;
2815}
2816
2817
2818/**
2819 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field causes a
2820 * VM-exit or not.
2821 *
2822 * @returns @c true if the VMREAD/VMWRITE is intercepted, @c false otherwise.
2823 * @param pVCpu The cross context virtual CPU structure.
2824 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
2825 * VMX_EXIT_VMREAD).
2826 * @param u64VmcsField The VMCS field.
2827 */
2828VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64VmcsField)
2829{
2830 Assert(CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest));
2831 Assert( uExitReason == VMX_EXIT_VMREAD
2832 || uExitReason == VMX_EXIT_VMWRITE);
2833
2834 /*
2835 * Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted.
2836 */
2837 if (!CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VMCS_SHADOWING))
2838 return true;
2839
2840 /*
2841 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE
2842 * is intercepted. This excludes any reserved bits in the valid parts of the field
2843 * encoding (i.e. bit 12).
2844 */
2845 if (u64VmcsField & VMX_VMCSFIELD_RSVD_MASK)
2846 return true;
2847
2848 /*
2849 * Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not.
2850 */
2851 uint32_t const u32VmcsField = RT_LO_U32(u64VmcsField);
2852 uint8_t const * const pbBitmap = uExitReason == VMX_EXIT_VMREAD
2853 ? &pVCpu->cpum.s.Guest.hwvirt.vmx.abVmreadBitmap[0]
2854 : &pVCpu->cpum.s.Guest.hwvirt.vmx.abVmwriteBitmap[0];
2855 Assert(pbBitmap);
2856 Assert(u32VmcsField >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2857 return ASMBitTest(pbBitmap, (u32VmcsField << 3) + (u32VmcsField & 7));
2858}
2859
2860
2861
2862/**
2863 * Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
2864 *
2865 * @param pvIoBitmap Pointer to the nested-guest IO bitmap.
2866 * @param u16Port The IO port being accessed.
2867 * @param enmIoType The type of IO access.
2868 * @param cbReg The IO operand size in bytes.
2869 * @param cAddrSizeBits The address size bits (for 16, 32 or 64).
2870 * @param iEffSeg The effective segment number.
2871 * @param fRep Whether this is a repeating IO instruction (REP prefix).
2872 * @param fStrIo Whether this is a string IO instruction.
2873 * @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
2874 * Optional, can be NULL.
2875 */
2876VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
2877 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
2878 PSVMIOIOEXITINFO pIoExitInfo)
2879{
2880 Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64);
2881 Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8);
2882
2883 /*
2884 * The IOPM layout:
2885 * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
2886 * two 4K pages.
2887 *
2888 * For IO instructions that access more than a single byte, the permission bits
2889 * for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
2890 *
2891 * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
2892 * we need 3 extra bits beyond the second 4K page.
2893 */
2894 static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
2895
2896 uint16_t const offIopm = u16Port >> 3;
2897 uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
2898 uint8_t const cShift = u16Port - (offIopm << 3);
2899 uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift);
2900
2901 uint8_t const *pbIopm = (uint8_t *)pvIoBitmap;
2902 Assert(pbIopm);
2903 pbIopm += offIopm;
2904 uint16_t const u16Iopm = *(uint16_t *)pbIopm;
2905 if (u16Iopm & fIopmMask)
2906 {
2907 if (pIoExitInfo)
2908 {
2909 static const uint32_t s_auIoOpSize[] =
2910 { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
2911
2912 static const uint32_t s_auIoAddrSize[] =
2913 { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
2914
2915 pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
2916 pIoExitInfo->u |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
2917 pIoExitInfo->n.u1Str = fStrIo;
2918 pIoExitInfo->n.u1Rep = fRep;
2919 pIoExitInfo->n.u3Seg = iEffSeg & 7;
2920 pIoExitInfo->n.u1Type = enmIoType;
2921 pIoExitInfo->n.u16Port = u16Port;
2922 }
2923 return true;
2924 }
2925
2926 /** @todo remove later (for debugging as VirtualBox always traps all IO
2927 * intercepts). */
2928 AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
2929 return false;
2930}
2931
2932
2933/**
2934 * Gets the MSR permission bitmap byte and bit offset for the specified MSR.
2935 *
2936 * @returns VBox status code.
2937 * @param idMsr The MSR being requested.
2938 * @param pbOffMsrpm Where to store the byte offset in the MSR permission
2939 * bitmap for @a idMsr.
2940 * @param puMsrpmBit Where to store the bit offset starting at the byte
2941 * returned in @a pbOffMsrpm.
2942 */
2943VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit)
2944{
2945 Assert(pbOffMsrpm);
2946 Assert(puMsrpmBit);
2947
2948 /*
2949 * MSRPM Layout:
2950 * Byte offset MSR range
2951 * 0x000 - 0x7ff 0x00000000 - 0x00001fff
2952 * 0x800 - 0xfff 0xc0000000 - 0xc0001fff
2953 * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
2954 * 0x1800 - 0x1fff Reserved
2955 *
2956 * Each MSR is represented by 2 permission bits (read and write).
2957 */
2958 if (idMsr <= 0x00001fff)
2959 {
2960 /* Pentium-compatible MSRs. */
2961 uint32_t const bitoffMsr = idMsr << 1;
2962 *pbOffMsrpm = bitoffMsr >> 3;
2963 *puMsrpmBit = bitoffMsr & 7;
2964 return VINF_SUCCESS;
2965 }
2966
2967 if ( idMsr >= 0xc0000000
2968 && idMsr <= 0xc0001fff)
2969 {
2970 /* AMD Sixth Generation x86 Processor MSRs. */
2971 uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
2972 *pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
2973 *puMsrpmBit = bitoffMsr & 7;
2974 return VINF_SUCCESS;
2975 }
2976
2977 if ( idMsr >= 0xc0010000
2978 && idMsr <= 0xc0011fff)
2979 {
2980 /* AMD Seventh and Eighth Generation Processor MSRs. */
2981 uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
2982 *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
2983 *puMsrpmBit = bitoffMsr & 7;
2984 return VINF_SUCCESS;
2985 }
2986
2987 *pbOffMsrpm = 0;
2988 *puMsrpmBit = 0;
2989 return VERR_OUT_OF_RANGE;
2990}
2991
2992
2993/**
2994 * Checks whether the guest is in VMX non-root mode and using EPT paging.
2995 *
2996 * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
2997 * @param pVCpu The cross context virtual CPU structure.
2998 */
2999VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu)
3000{
3001 return CPUMIsGuestVmxEptPagingEnabledEx(&pVCpu->cpum.s.Guest);
3002}
3003
3004
3005/**
3006 * Checks whether the guest is in VMX non-root mode and using EPT paging and the
3007 * nested-guest is in PAE mode.
3008 *
3009 * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
3010 * @param pVCpu The cross context virtual CPU structure.
3011 */
3012VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu)
3013{
3014 return CPUMIsGuestVmxEptPagingEnabledEx(&pVCpu->cpum.s.Guest)
3015 && CPUMIsGuestInPAEModeEx(&pVCpu->cpum.s.Guest);
3016}
3017
3018
3019/**
3020 * Returns the guest-physical address of the APIC-access page when executing a
3021 * nested-guest.
3022 *
3023 * @returns The APIC-access page guest-physical address.
3024 * @param pVCpu The cross context virtual CPU structure.
3025 */
3026VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu)
3027{
3028 return CPUMGetGuestVmxApicAccessPageAddrEx(&pVCpu->cpum.s.Guest);
3029}
3030
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette