VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 94959

Last change on this file since 94959 was 94959, checked in by vboxsync, 3 years ago

VMM/CPUM: Hide the public read-only HostFeature member, use g_CpumHostFeatures instead. bugref:10093
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1/* $Id: CPUMAllRegs.cpp 94959 2022-05-09 14:13:11Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/dbgf.h>
25#include <VBox/vmm/apic.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/em.h>
29#include <VBox/vmm/nem.h>
30#include <VBox/vmm/hm.h>
31#include "CPUMInternal.h"
32#include <VBox/vmm/vmcc.h>
33#include <VBox/err.h>
34#include <VBox/dis.h>
35#include <VBox/log.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/tm.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
41# include <iprt/asm-amd64-x86.h>
42#endif
43#ifdef IN_RING3
44# include <iprt/thread.h>
45#endif
46
47/** Disable stack frame pointer generation here. */
48#if defined(_MSC_VER) && !defined(DEBUG) && defined(RT_ARCH_X86)
49# pragma optimize("y", off)
50#endif
51
52AssertCompile2MemberOffsets(VM, cpum.s.GuestFeatures, cpum.ro.GuestFeatures);
53
54
55/*********************************************************************************************************************************
56* Defined Constants And Macros *
57*********************************************************************************************************************************/
58/**
59 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
60 *
61 * @returns Pointer to the Virtual CPU.
62 * @param a_pGuestCtx Pointer to the guest context.
63 */
64#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
65
66/**
67 * Lazily loads the hidden parts of a selector register when using raw-mode.
68 */
69#define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
70 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg))
71
72/** @def CPUM_INT_ASSERT_NOT_EXTRN
73 * Macro for asserting that @a a_fNotExtrn are present.
74 *
75 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
76 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
77 */
78#define CPUM_INT_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
79 AssertMsg(!((a_pVCpu)->cpum.s.Guest.fExtrn & (a_fNotExtrn)), \
80 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.s.Guest.fExtrn, (a_fNotExtrn)))
81
82
83VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
84{
85 pVCpu->cpum.s.Hyper.cr3 = cr3;
86}
87
88VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
89{
90 return pVCpu->cpum.s.Hyper.cr3;
91}
92
93
94/** @def MAYBE_LOAD_DRx
95 * Macro for updating DRx values in raw-mode and ring-0 contexts.
96 */
97#ifdef IN_RING0
98# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { a_fnLoad(a_uValue); } while (0)
99#else
100# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
101#endif
102
103VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
104{
105 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
106 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
107}
108
109
110VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
111{
112 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
113 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
114}
115
116
117VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
118{
119 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
120 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
121}
122
123
124VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
125{
126 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
127 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
128}
129
130
131VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
132{
133 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
134}
135
136
137VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
138{
139 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
140}
141
142
143VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
144{
145 return pVCpu->cpum.s.Hyper.dr[0];
146}
147
148
149VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
150{
151 return pVCpu->cpum.s.Hyper.dr[1];
152}
153
154
155VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
156{
157 return pVCpu->cpum.s.Hyper.dr[2];
158}
159
160
161VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
162{
163 return pVCpu->cpum.s.Hyper.dr[3];
164}
165
166
167VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
168{
169 return pVCpu->cpum.s.Hyper.dr[6];
170}
171
172
173VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
174{
175 return pVCpu->cpum.s.Hyper.dr[7];
176}
177
178
179/**
180 * Gets the pointer to the internal CPUMCTXCORE structure.
181 * This is only for reading in order to save a few calls.
182 *
183 * @param pVCpu The cross context virtual CPU structure.
184 */
185VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
186{
187 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
188}
189
190
191/**
192 * Queries the pointer to the internal CPUMCTX structure.
193 *
194 * @returns The CPUMCTX pointer.
195 * @param pVCpu The cross context virtual CPU structure.
196 */
197VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
198{
199 return &pVCpu->cpum.s.Guest;
200}
201
202
203/**
204 * Queries the pointer to the internal CPUMCTXMSRS structure.
205 *
206 * This is for NEM only.
207 *
208 * @returns The CPUMCTX pointer.
209 * @param pVCpu The cross context virtual CPU structure.
210 */
211VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu)
212{
213 return &pVCpu->cpum.s.GuestMsrs;
214}
215
216
217VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
218{
219 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
220 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
221 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_GDTR;
222 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
223 return VINF_SUCCESS; /* formality, consider it void. */
224}
225
226
227VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
228{
229 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
230 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
231 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_IDTR;
232 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
233 return VINF_SUCCESS; /* formality, consider it void. */
234}
235
236
237VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
238{
239 pVCpu->cpum.s.Guest.tr.Sel = tr;
240 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
241 return VINF_SUCCESS; /* formality, consider it void. */
242}
243
244
245VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
246{
247 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
248 /* The caller will set more hidden bits if it has them. */
249 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
250 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
251 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
252 return VINF_SUCCESS; /* formality, consider it void. */
253}
254
255
256/**
257 * Set the guest CR0.
258 *
259 * When called in GC, the hyper CR0 may be updated if that is
260 * required. The caller only has to take special action if AM,
261 * WP, PG or PE changes.
262 *
263 * @returns VINF_SUCCESS (consider it void).
264 * @param pVCpu The cross context virtual CPU structure.
265 * @param cr0 The new CR0 value.
266 */
267VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0)
268{
269 /*
270 * Check for changes causing TLB flushes (for REM).
271 * The caller is responsible for calling PGM when appropriate.
272 */
273 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
274 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
275 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
276 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
277
278 /*
279 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
280 */
281 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
282 PGMCr0WpEnabled(pVCpu);
283
284 /* The ET flag is settable on a 386 and hardwired on 486+. */
285 if ( !(cr0 & X86_CR0_ET)
286 && pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386)
287 cr0 |= X86_CR0_ET;
288
289 pVCpu->cpum.s.Guest.cr0 = cr0;
290 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR0;
291 return VINF_SUCCESS;
292}
293
294
295VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
296{
297 pVCpu->cpum.s.Guest.cr2 = cr2;
298 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR2;
299 return VINF_SUCCESS;
300}
301
302
303VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
304{
305 pVCpu->cpum.s.Guest.cr3 = cr3;
306 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
307 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
308 return VINF_SUCCESS;
309}
310
311
312VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
313{
314 /* Note! We don't bother with OSXSAVE and legacy CPUID patches. */
315
316 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
317 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
318 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
319
320 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
321 pVCpu->cpum.s.Guest.cr4 = cr4;
322 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR4;
323 return VINF_SUCCESS;
324}
325
326
327VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
328{
329 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
330 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
331 return VINF_SUCCESS;
332}
333
334
335VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
336{
337 pVCpu->cpum.s.Guest.eip = eip;
338 return VINF_SUCCESS;
339}
340
341
342VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
343{
344 pVCpu->cpum.s.Guest.eax = eax;
345 return VINF_SUCCESS;
346}
347
348
349VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
350{
351 pVCpu->cpum.s.Guest.ebx = ebx;
352 return VINF_SUCCESS;
353}
354
355
356VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
357{
358 pVCpu->cpum.s.Guest.ecx = ecx;
359 return VINF_SUCCESS;
360}
361
362
363VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
364{
365 pVCpu->cpum.s.Guest.edx = edx;
366 return VINF_SUCCESS;
367}
368
369
370VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
371{
372 pVCpu->cpum.s.Guest.esp = esp;
373 return VINF_SUCCESS;
374}
375
376
377VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
378{
379 pVCpu->cpum.s.Guest.ebp = ebp;
380 return VINF_SUCCESS;
381}
382
383
384VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
385{
386 pVCpu->cpum.s.Guest.esi = esi;
387 return VINF_SUCCESS;
388}
389
390
391VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
392{
393 pVCpu->cpum.s.Guest.edi = edi;
394 return VINF_SUCCESS;
395}
396
397
398VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
399{
400 pVCpu->cpum.s.Guest.ss.Sel = ss;
401 return VINF_SUCCESS;
402}
403
404
405VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
406{
407 pVCpu->cpum.s.Guest.cs.Sel = cs;
408 return VINF_SUCCESS;
409}
410
411
412VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
413{
414 pVCpu->cpum.s.Guest.ds.Sel = ds;
415 return VINF_SUCCESS;
416}
417
418
419VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
420{
421 pVCpu->cpum.s.Guest.es.Sel = es;
422 return VINF_SUCCESS;
423}
424
425
426VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
427{
428 pVCpu->cpum.s.Guest.fs.Sel = fs;
429 return VINF_SUCCESS;
430}
431
432
433VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
434{
435 pVCpu->cpum.s.Guest.gs.Sel = gs;
436 return VINF_SUCCESS;
437}
438
439
440VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
441{
442 pVCpu->cpum.s.Guest.msrEFER = val;
443 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_EFER;
444}
445
446
447VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit)
448{
449 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_IDTR);
450 if (pcbLimit)
451 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
452 return pVCpu->cpum.s.Guest.idtr.pIdt;
453}
454
455
456VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden)
457{
458 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_TR);
459 if (pHidden)
460 *pHidden = pVCpu->cpum.s.Guest.tr;
461 return pVCpu->cpum.s.Guest.tr.Sel;
462}
463
464
465VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu)
466{
467 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS);
468 return pVCpu->cpum.s.Guest.cs.Sel;
469}
470
471
472VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu)
473{
474 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DS);
475 return pVCpu->cpum.s.Guest.ds.Sel;
476}
477
478
479VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu)
480{
481 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ES);
482 return pVCpu->cpum.s.Guest.es.Sel;
483}
484
485
486VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu)
487{
488 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_FS);
489 return pVCpu->cpum.s.Guest.fs.Sel;
490}
491
492
493VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu)
494{
495 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GS);
496 return pVCpu->cpum.s.Guest.gs.Sel;
497}
498
499
500VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu)
501{
502 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SS);
503 return pVCpu->cpum.s.Guest.ss.Sel;
504}
505
506
507VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu)
508{
509 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
510 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
511 if ( !CPUMIsGuestInLongMode(pVCpu)
512 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
513 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.cs.u64Base;
514 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.cs.u64Base;
515}
516
517
518VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu)
519{
520 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
521 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
522 if ( !CPUMIsGuestInLongMode(pVCpu)
523 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
524 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.ss.u64Base;
525 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.ss.u64Base;
526}
527
528
529VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu)
530{
531 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
532 return pVCpu->cpum.s.Guest.ldtr.Sel;
533}
534
535
536VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
537{
538 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
539 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
540 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
541 return pVCpu->cpum.s.Guest.ldtr.Sel;
542}
543
544
545VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu)
546{
547 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
548 return pVCpu->cpum.s.Guest.cr0;
549}
550
551
552VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu)
553{
554 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
555 return pVCpu->cpum.s.Guest.cr2;
556}
557
558
559VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu)
560{
561 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
562 return pVCpu->cpum.s.Guest.cr3;
563}
564
565
566VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu)
567{
568 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
569 return pVCpu->cpum.s.Guest.cr4;
570}
571
572
573VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu)
574{
575 uint64_t u64;
576 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
577 if (RT_FAILURE(rc))
578 u64 = 0;
579 return u64;
580}
581
582
583VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR)
584{
585 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GDTR);
586 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
587}
588
589
590VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu)
591{
592 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
593 return pVCpu->cpum.s.Guest.eip;
594}
595
596
597VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu)
598{
599 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
600 return pVCpu->cpum.s.Guest.rip;
601}
602
603
604VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu)
605{
606 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RAX);
607 return pVCpu->cpum.s.Guest.eax;
608}
609
610
611VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu)
612{
613 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBX);
614 return pVCpu->cpum.s.Guest.ebx;
615}
616
617
618VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu)
619{
620 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RCX);
621 return pVCpu->cpum.s.Guest.ecx;
622}
623
624
625VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu)
626{
627 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDX);
628 return pVCpu->cpum.s.Guest.edx;
629}
630
631
632VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu)
633{
634 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSI);
635 return pVCpu->cpum.s.Guest.esi;
636}
637
638
639VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu)
640{
641 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDI);
642 return pVCpu->cpum.s.Guest.edi;
643}
644
645
646VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu)
647{
648 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP);
649 return pVCpu->cpum.s.Guest.esp;
650}
651
652
653VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu)
654{
655 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBP);
656 return pVCpu->cpum.s.Guest.ebp;
657}
658
659
660VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu)
661{
662 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RFLAGS);
663 return pVCpu->cpum.s.Guest.eflags.u32;
664}
665
666
667VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue)
668{
669 switch (iReg)
670 {
671 case DISCREG_CR0:
672 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
673 *pValue = pVCpu->cpum.s.Guest.cr0;
674 break;
675
676 case DISCREG_CR2:
677 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
678 *pValue = pVCpu->cpum.s.Guest.cr2;
679 break;
680
681 case DISCREG_CR3:
682 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
683 *pValue = pVCpu->cpum.s.Guest.cr3;
684 break;
685
686 case DISCREG_CR4:
687 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
688 *pValue = pVCpu->cpum.s.Guest.cr4;
689 break;
690
691 case DISCREG_CR8:
692 {
693 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
694 uint8_t u8Tpr;
695 int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
696 if (RT_FAILURE(rc))
697 {
698 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
699 *pValue = 0;
700 return rc;
701 }
702 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0 */
703 break;
704 }
705
706 default:
707 return VERR_INVALID_PARAMETER;
708 }
709 return VINF_SUCCESS;
710}
711
712
713VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu)
714{
715 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
716 return pVCpu->cpum.s.Guest.dr[0];
717}
718
719
720VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu)
721{
722 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
723 return pVCpu->cpum.s.Guest.dr[1];
724}
725
726
727VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu)
728{
729 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
730 return pVCpu->cpum.s.Guest.dr[2];
731}
732
733
734VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu)
735{
736 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
737 return pVCpu->cpum.s.Guest.dr[3];
738}
739
740
741VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu)
742{
743 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR6);
744 return pVCpu->cpum.s.Guest.dr[6];
745}
746
747
748VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu)
749{
750 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
751 return pVCpu->cpum.s.Guest.dr[7];
752}
753
754
755VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
756{
757 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR_MASK);
758 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
759 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
760 if (iReg == 4 || iReg == 5)
761 iReg += 2;
762 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
763 return VINF_SUCCESS;
764}
765
766
767VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu)
768{
769 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
770 return pVCpu->cpum.s.Guest.msrEFER;
771}
772
773
774/**
775 * Looks up a CPUID leaf in the CPUID leaf array, no subleaf.
776 *
777 * @returns Pointer to the leaf if found, NULL if not.
778 *
779 * @param pVM The cross context VM structure.
780 * @param uLeaf The leaf to get.
781 */
782PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf)
783{
784 unsigned iEnd = RT_MIN(pVM->cpum.s.GuestInfo.cCpuIdLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves));
785 if (iEnd)
786 {
787 unsigned iStart = 0;
788 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.aCpuIdLeaves;
789 for (;;)
790 {
791 unsigned i = iStart + (iEnd - iStart) / 2U;
792 if (uLeaf < paLeaves[i].uLeaf)
793 {
794 if (i <= iStart)
795 return NULL;
796 iEnd = i;
797 }
798 else if (uLeaf > paLeaves[i].uLeaf)
799 {
800 i += 1;
801 if (i >= iEnd)
802 return NULL;
803 iStart = i;
804 }
805 else
806 {
807 if (RT_LIKELY(paLeaves[i].fSubLeafMask == 0 && paLeaves[i].uSubLeaf == 0))
808 return &paLeaves[i];
809
810 /* This shouldn't normally happen. But in case the it does due
811 to user configuration overrids or something, just return the
812 first sub-leaf. */
813 AssertMsgFailed(("uLeaf=%#x fSubLeafMask=%#x uSubLeaf=%#x\n",
814 uLeaf, paLeaves[i].fSubLeafMask, paLeaves[i].uSubLeaf));
815 while ( paLeaves[i].uSubLeaf != 0
816 && i > 0
817 && uLeaf == paLeaves[i - 1].uLeaf)
818 i--;
819 return &paLeaves[i];
820 }
821 }
822 }
823
824 return NULL;
825}
826
827
828/**
829 * Looks up a CPUID leaf in the CPUID leaf array.
830 *
831 * @returns Pointer to the leaf if found, NULL if not.
832 *
833 * @param pVM The cross context VM structure.
834 * @param uLeaf The leaf to get.
835 * @param uSubLeaf The subleaf, if applicable. Just pass 0 if it
836 * isn't.
837 * @param pfExactSubLeafHit Whether we've got an exact subleaf hit or not.
838 */
839PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit)
840{
841 unsigned iEnd = RT_MIN(pVM->cpum.s.GuestInfo.cCpuIdLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves));
842 if (iEnd)
843 {
844 unsigned iStart = 0;
845 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.aCpuIdLeaves;
846 for (;;)
847 {
848 unsigned i = iStart + (iEnd - iStart) / 2U;
849 if (uLeaf < paLeaves[i].uLeaf)
850 {
851 if (i <= iStart)
852 return NULL;
853 iEnd = i;
854 }
855 else if (uLeaf > paLeaves[i].uLeaf)
856 {
857 i += 1;
858 if (i >= iEnd)
859 return NULL;
860 iStart = i;
861 }
862 else
863 {
864 uSubLeaf &= paLeaves[i].fSubLeafMask;
865 if (uSubLeaf == paLeaves[i].uSubLeaf)
866 *pfExactSubLeafHit = true;
867 else
868 {
869 /* Find the right subleaf. We return the last one before
870 uSubLeaf if we don't find an exact match. */
871 if (uSubLeaf < paLeaves[i].uSubLeaf)
872 while ( i > 0
873 && uLeaf == paLeaves[i - 1].uLeaf
874 && uSubLeaf <= paLeaves[i - 1].uSubLeaf)
875 i--;
876 else
877 while ( i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves
878 && uLeaf == paLeaves[i + 1].uLeaf
879 && uSubLeaf >= paLeaves[i + 1].uSubLeaf)
880 i++;
881 *pfExactSubLeafHit = uSubLeaf == paLeaves[i].uSubLeaf;
882 }
883 return &paLeaves[i];
884 }
885 }
886 }
887
888 *pfExactSubLeafHit = false;
889 return NULL;
890}
891
892
893/**
894 * Gets a CPUID leaf.
895 *
896 * @param pVCpu The cross context virtual CPU structure.
897 * @param uLeaf The CPUID leaf to get.
898 * @param uSubLeaf The CPUID sub-leaf to get, if applicable.
899 * @param pEax Where to store the EAX value.
900 * @param pEbx Where to store the EBX value.
901 * @param pEcx Where to store the ECX value.
902 * @param pEdx Where to store the EDX value.
903 */
904VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t uLeaf, uint32_t uSubLeaf,
905 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
906{
907 bool fExactSubLeafHit;
908 PVM pVM = pVCpu->CTX_SUFF(pVM);
909 PCCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, uSubLeaf, &fExactSubLeafHit);
910 if (pLeaf)
911 {
912 AssertMsg(pLeaf->uLeaf == uLeaf, ("%#x %#x\n", pLeaf->uLeaf, uLeaf));
913 if (fExactSubLeafHit)
914 {
915 *pEax = pLeaf->uEax;
916 *pEbx = pLeaf->uEbx;
917 *pEcx = pLeaf->uEcx;
918 *pEdx = pLeaf->uEdx;
919
920 /*
921 * Deal with CPU specific information.
922 */
923 if (pLeaf->fFlags & ( CPUMCPUIDLEAF_F_CONTAINS_APIC_ID
924 | CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
925 | CPUMCPUIDLEAF_F_CONTAINS_APIC ))
926 {
927 if (uLeaf == 1)
928 {
929 /* EBX: Bits 31-24: Initial APIC ID. */
930 Assert(pVCpu->idCpu <= 255);
931 AssertMsg((pLeaf->uEbx >> 24) == 0, ("%#x\n", pLeaf->uEbx)); /* raw-mode assumption */
932 *pEbx = (pLeaf->uEbx & UINT32_C(0x00ffffff)) | (pVCpu->idCpu << 24);
933
934 /* EDX: Bit 9: AND with APICBASE.EN. */
935 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
936 *pEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
937
938 /* ECX: Bit 27: CR4.OSXSAVE mirror. */
939 *pEcx = (pLeaf->uEcx & ~X86_CPUID_FEATURE_ECX_OSXSAVE)
940 | (pVCpu->cpum.s.Guest.cr4 & X86_CR4_OSXSAVE ? X86_CPUID_FEATURE_ECX_OSXSAVE : 0);
941 }
942 else if (uLeaf == 0xb)
943 {
944 /* EDX: Initial extended APIC ID. */
945 AssertMsg(pLeaf->uEdx == 0, ("%#x\n", pLeaf->uEdx)); /* raw-mode assumption */
946 *pEdx = pVCpu->idCpu;
947 Assert(!(pLeaf->fFlags & ~(CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)));
948 }
949 else if (uLeaf == UINT32_C(0x8000001e))
950 {
951 /* EAX: Initial extended APIC ID. */
952 AssertMsg(pLeaf->uEax == 0, ("%#x\n", pLeaf->uEax)); /* raw-mode assumption */
953 *pEax = pVCpu->idCpu;
954 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID));
955 }
956 else if (uLeaf == UINT32_C(0x80000001))
957 {
958 /* EDX: Bit 9: AND with APICBASE.EN. */
959 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible)
960 *pEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
961 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC));
962 }
963 else
964 AssertMsgFailed(("uLeaf=%#x\n", uLeaf));
965 }
966 }
967 /*
968 * Out of range sub-leaves aren't quite as easy and pretty as we emulate
969 * them here, but we do the best we can here...
970 */
971 else
972 {
973 *pEax = *pEbx = *pEcx = *pEdx = 0;
974 if (pLeaf->fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
975 {
976 *pEcx = uSubLeaf & 0xff;
977 *pEdx = pVCpu->idCpu;
978 }
979 }
980 }
981 else
982 {
983 /*
984 * Different CPUs have different ways of dealing with unknown CPUID leaves.
985 */
986 switch (pVM->cpum.s.GuestInfo.enmUnknownCpuIdMethod)
987 {
988 default:
989 AssertFailed();
990 RT_FALL_THRU();
991 case CPUMUNKNOWNCPUID_DEFAULTS:
992 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: /* ASSUME this is executed */
993 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: /** @todo Implement CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX */
994 *pEax = pVM->cpum.s.GuestInfo.DefCpuId.uEax;
995 *pEbx = pVM->cpum.s.GuestInfo.DefCpuId.uEbx;
996 *pEcx = pVM->cpum.s.GuestInfo.DefCpuId.uEcx;
997 *pEdx = pVM->cpum.s.GuestInfo.DefCpuId.uEdx;
998 break;
999 case CPUMUNKNOWNCPUID_PASSTHRU:
1000 *pEax = uLeaf;
1001 *pEbx = 0;
1002 *pEcx = uSubLeaf;
1003 *pEdx = 0;
1004 break;
1005 }
1006 }
1007 Log2(("CPUMGetGuestCpuId: uLeaf=%#010x/%#010x %RX32 %RX32 %RX32 %RX32\n", uLeaf, uSubLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1008}
1009
1010
1011/**
1012 * Sets the visibility of the X86_CPUID_FEATURE_EDX_APIC and
1013 * X86_CPUID_AMD_FEATURE_EDX_APIC CPUID bits.
1014 *
1015 * @returns Previous value.
1016 * @param pVCpu The cross context virtual CPU structure to make the
1017 * change on. Usually the calling EMT.
1018 * @param fVisible Whether to make it visible (true) or hide it (false).
1019 *
1020 * @remarks This is "VMMDECL" so that it still links with
1021 * the old APIC code which is in VBoxDD2 and not in
1022 * the VMM module.
1023 */
1024VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible)
1025{
1026 bool fOld = pVCpu->cpum.s.fCpuIdApicFeatureVisible;
1027 pVCpu->cpum.s.fCpuIdApicFeatureVisible = fVisible;
1028 return fOld;
1029}
1030
1031
1032/**
1033 * Gets the host CPU vendor.
1034 *
1035 * @returns CPU vendor.
1036 * @param pVM The cross context VM structure.
1037 */
1038VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1039{
1040 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor;
1041}
1042
1043
1044/**
1045 * Gets the host CPU microarchitecture.
1046 *
1047 * @returns CPU microarchitecture.
1048 * @param pVM The cross context VM structure.
1049 */
1050VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM)
1051{
1052 return pVM->cpum.s.HostFeatures.enmMicroarch;
1053}
1054
1055
1056/**
1057 * Gets the guest CPU vendor.
1058 *
1059 * @returns CPU vendor.
1060 * @param pVM The cross context VM structure.
1061 */
1062VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1063{
1064 return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor;
1065}
1066
1067
1068/**
1069 * Gets the guest CPU microarchitecture.
1070 *
1071 * @returns CPU microarchitecture.
1072 * @param pVM The cross context VM structure.
1073 */
1074VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM)
1075{
1076 return pVM->cpum.s.GuestFeatures.enmMicroarch;
1077}
1078
1079
1080/**
1081 * Gets the maximum number of physical and linear address bits supported by the
1082 * guest.
1083 *
1084 * @param pVM The cross context VM structure.
1085 * @param pcPhysAddrWidth Where to store the physical address width.
1086 * @param pcLinearAddrWidth Where to store the linear address width.
1087 */
1088VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t *pcPhysAddrWidth, uint8_t *pcLinearAddrWidth)
1089{
1090 AssertPtr(pVM);
1091 AssertReturnVoid(pcPhysAddrWidth);
1092 AssertReturnVoid(pcLinearAddrWidth);
1093 *pcPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
1094 *pcLinearAddrWidth = pVM->cpum.s.GuestFeatures.cMaxLinearAddrWidth;
1095}
1096
1097
1098VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0)
1099{
1100 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1101 return CPUMRecalcHyperDRx(pVCpu, 0);
1102}
1103
1104
1105VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1)
1106{
1107 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1108 return CPUMRecalcHyperDRx(pVCpu, 1);
1109}
1110
1111
1112VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2)
1113{
1114 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1115 return CPUMRecalcHyperDRx(pVCpu, 2);
1116}
1117
1118
1119VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3)
1120{
1121 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1122 return CPUMRecalcHyperDRx(pVCpu, 3);
1123}
1124
1125
1126VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1127{
1128 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1129 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR6;
1130 return VINF_SUCCESS; /* No need to recalc. */
1131}
1132
1133
1134VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7)
1135{
1136 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1137 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR7;
1138 return CPUMRecalcHyperDRx(pVCpu, 7);
1139}
1140
1141
1142VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value)
1143{
1144 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1145 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1146 if (iReg == 4 || iReg == 5)
1147 iReg += 2;
1148 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1149 return CPUMRecalcHyperDRx(pVCpu, iReg);
1150}
1151
1152
1153/**
1154 * Recalculates the hypervisor DRx register values based on current guest
1155 * registers and DBGF breakpoints, updating changed registers depending on the
1156 * context.
1157 *
1158 * This is called whenever a guest DRx register is modified (any context) and
1159 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
1160 *
1161 * In raw-mode context this function will reload any (hyper) DRx registers which
1162 * comes out with a different value. It may also have to save the host debug
1163 * registers if that haven't been done already. In this context though, we'll
1164 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
1165 * are only important when breakpoints are actually enabled.
1166 *
1167 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
1168 * reloaded by the HM code if it changes. Further more, we will only use the
1169 * combined register set when the VBox debugger is actually using hardware BPs,
1170 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
1171 * concern us here).
1172 *
1173 * In ring-3 we won't be loading anything, so well calculate hypervisor values
1174 * all the time.
1175 *
1176 * @returns VINF_SUCCESS.
1177 * @param pVCpu The cross context virtual CPU structure.
1178 * @param iGstReg The guest debug register number that was modified.
1179 * UINT8_MAX if not guest register.
1180 */
1181VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg)
1182{
1183 PVM pVM = pVCpu->CTX_SUFF(pVM);
1184#ifndef IN_RING0
1185 RT_NOREF_PV(iGstReg);
1186#endif
1187
1188 /*
1189 * Compare the DR7s first.
1190 *
1191 * We only care about the enabled flags. GD is virtualized when we
1192 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
1193 * always have the LE and GE bits set, so no need to check and disable
1194 * stuff if they're cleared like we have to for the guest DR7.
1195 */
1196 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1197 /** @todo This isn't correct. BPs work without setting LE and GE under AMD-V. They are also documented as unsupported by P6+. */
1198 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
1199 uGstDr7 = 0;
1200 else if (!(uGstDr7 & X86_DR7_LE))
1201 uGstDr7 &= ~X86_DR7_LE_ALL;
1202 else if (!(uGstDr7 & X86_DR7_GE))
1203 uGstDr7 &= ~X86_DR7_GE_ALL;
1204
1205 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1206 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1207 {
1208 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1209
1210 /*
1211 * Ok, something is enabled. Recalc each of the breakpoints, taking
1212 * the VM debugger ones of the guest ones. In raw-mode context we will
1213 * not allow breakpoints with values inside the hypervisor area.
1214 */
1215 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
1216
1217 /* bp 0 */
1218 RTGCUINTREG uNewDr0;
1219 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1220 {
1221 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1222 uNewDr0 = DBGFBpGetDR0(pVM);
1223 }
1224 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1225 {
1226 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1227 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1228 }
1229 else
1230 uNewDr0 = 0;
1231
1232 /* bp 1 */
1233 RTGCUINTREG uNewDr1;
1234 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1235 {
1236 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1237 uNewDr1 = DBGFBpGetDR1(pVM);
1238 }
1239 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1240 {
1241 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1242 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1243 }
1244 else
1245 uNewDr1 = 0;
1246
1247 /* bp 2 */
1248 RTGCUINTREG uNewDr2;
1249 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1250 {
1251 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1252 uNewDr2 = DBGFBpGetDR2(pVM);
1253 }
1254 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1255 {
1256 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1257 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1258 }
1259 else
1260 uNewDr2 = 0;
1261
1262 /* bp 3 */
1263 RTGCUINTREG uNewDr3;
1264 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1265 {
1266 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1267 uNewDr3 = DBGFBpGetDR3(pVM);
1268 }
1269 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1270 {
1271 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1272 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1273 }
1274 else
1275 uNewDr3 = 0;
1276
1277 /*
1278 * Apply the updates.
1279 */
1280 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
1281 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1282 CPUMSetHyperDR3(pVCpu, uNewDr3);
1283 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1284 CPUMSetHyperDR2(pVCpu, uNewDr2);
1285 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1286 CPUMSetHyperDR1(pVCpu, uNewDr1);
1287 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1288 CPUMSetHyperDR0(pVCpu, uNewDr0);
1289 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1290 CPUMSetHyperDR7(pVCpu, uNewDr7);
1291 }
1292#ifdef IN_RING0
1293 else if (CPUMIsGuestDebugStateActive(pVCpu))
1294 {
1295 /*
1296 * Reload the register that was modified. Normally this won't happen
1297 * as we won't intercept DRx writes when not having the hyper debug
1298 * state loaded, but in case we do for some reason we'll simply deal
1299 * with it.
1300 */
1301 switch (iGstReg)
1302 {
1303 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
1304 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
1305 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
1306 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
1307 default:
1308 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
1309 }
1310 }
1311#endif
1312 else
1313 {
1314 /*
1315 * No active debug state any more. In raw-mode this means we have to
1316 * make sure DR7 has everything disabled now, if we armed it already.
1317 * In ring-0 we might end up here when just single stepping.
1318 */
1319#ifdef IN_RING0
1320 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
1321 {
1322 if (pVCpu->cpum.s.Hyper.dr[0])
1323 ASMSetDR0(0);
1324 if (pVCpu->cpum.s.Hyper.dr[1])
1325 ASMSetDR1(0);
1326 if (pVCpu->cpum.s.Hyper.dr[2])
1327 ASMSetDR2(0);
1328 if (pVCpu->cpum.s.Hyper.dr[3])
1329 ASMSetDR3(0);
1330 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
1331 }
1332#endif
1333 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
1334
1335 /* Clear all the registers. */
1336 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
1337 pVCpu->cpum.s.Hyper.dr[3] = 0;
1338 pVCpu->cpum.s.Hyper.dr[2] = 0;
1339 pVCpu->cpum.s.Hyper.dr[1] = 0;
1340 pVCpu->cpum.s.Hyper.dr[0] = 0;
1341
1342 }
1343 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1344 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1345 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1346 pVCpu->cpum.s.Hyper.dr[7]));
1347
1348 return VINF_SUCCESS;
1349}
1350
1351
1352/**
1353 * Set the guest XCR0 register.
1354 *
1355 * Will load additional state if the FPU state is already loaded (in ring-0 &
1356 * raw-mode context).
1357 *
1358 * @returns VINF_SUCCESS on success, VERR_CPUM_RAISE_GP_0 on invalid input
1359 * value.
1360 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1361 * @param uNewValue The new value.
1362 * @thread EMT(pVCpu)
1363 */
1364VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue)
1365{
1366 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_XCRx);
1367 if ( (uNewValue & ~pVCpu->CTX_SUFF(pVM)->cpum.s.fXStateGuestMask) == 0
1368 /* The X87 bit cannot be cleared. */
1369 && (uNewValue & XSAVE_C_X87)
1370 /* AVX requires SSE. */
1371 && (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM
1372 /* AVX-512 requires YMM, SSE and all of its three components to be enabled. */
1373 && ( (uNewValue & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1374 || (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1375 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI) )
1376 )
1377 {
1378 pVCpu->cpum.s.Guest.aXcr[0] = uNewValue;
1379
1380 /* If more state components are enabled, we need to take care to load
1381 them if the FPU/SSE state is already loaded. May otherwise leak
1382 host state to the guest. */
1383 uint64_t fNewComponents = ~pVCpu->cpum.s.Guest.fXStateMask & uNewValue;
1384 if (fNewComponents)
1385 {
1386#ifdef IN_RING0
1387 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
1388 {
1389 if (pVCpu->cpum.s.Guest.fXStateMask != 0)
1390 /* Adding more components. */
1391 ASMXRstor(&pVCpu->cpum.s.Guest.XState, fNewComponents);
1392 else
1393 {
1394 /* We're switching from FXSAVE/FXRSTOR to XSAVE/XRSTOR. */
1395 pVCpu->cpum.s.Guest.fXStateMask |= XSAVE_C_X87 | XSAVE_C_SSE;
1396 if (uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE))
1397 ASMXRstor(&pVCpu->cpum.s.Guest.XState, uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE));
1398 }
1399 }
1400#endif
1401 pVCpu->cpum.s.Guest.fXStateMask |= uNewValue;
1402 }
1403 return VINF_SUCCESS;
1404 }
1405 return VERR_CPUM_RAISE_GP_0;
1406}
1407
1408
1409/**
1410 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1411 *
1412 * @returns true if in real mode, otherwise false.
1413 * @param pVCpu The cross context virtual CPU structure.
1414 */
1415VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu)
1416{
1417 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1418 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
1419}
1420
1421
1422/**
1423 * Tests if the guest has the Page Size Extension enabled (PSE).
1424 *
1425 * @returns true if in real mode, otherwise false.
1426 * @param pVCpu The cross context virtual CPU structure.
1427 */
1428VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu)
1429{
1430 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
1431 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
1432 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
1433}
1434
1435
1436/**
1437 * Tests if the guest has the paging enabled (PG).
1438 *
1439 * @returns true if in real mode, otherwise false.
1440 * @param pVCpu The cross context virtual CPU structure.
1441 */
1442VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu)
1443{
1444 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1445 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
1446}
1447
1448
1449/**
1450 * Tests if the guest has the paging enabled (PG).
1451 *
1452 * @returns true if in real mode, otherwise false.
1453 * @param pVCpu The cross context virtual CPU structure.
1454 */
1455VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu)
1456{
1457 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1458 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
1459}
1460
1461
1462/**
1463 * Tests if the guest is running in real mode or not.
1464 *
1465 * @returns true if in real mode, otherwise false.
1466 * @param pVCpu The cross context virtual CPU structure.
1467 */
1468VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu)
1469{
1470 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1471 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1472}
1473
1474
1475/**
1476 * Tests if the guest is running in real or virtual 8086 mode.
1477 *
1478 * @returns @c true if it is, @c false if not.
1479 * @param pVCpu The cross context virtual CPU structure.
1480 */
1481VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu)
1482{
1483 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS);
1484 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1485 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
1486}
1487
1488
1489/**
1490 * Tests if the guest is running in protected or not.
1491 *
1492 * @returns true if in protected mode, otherwise false.
1493 * @param pVCpu The cross context virtual CPU structure.
1494 */
1495VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu)
1496{
1497 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1498 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1499}
1500
1501
1502/**
1503 * Tests if the guest is running in paged protected or not.
1504 *
1505 * @returns true if in paged protected mode, otherwise false.
1506 * @param pVCpu The cross context virtual CPU structure.
1507 */
1508VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu)
1509{
1510 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1511 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1512}
1513
1514
1515/**
1516 * Tests if the guest is running in long mode or not.
1517 *
1518 * @returns true if in long mode, otherwise false.
1519 * @param pVCpu The cross context virtual CPU structure.
1520 */
1521VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu)
1522{
1523 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1524 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1525}
1526
1527
1528/**
1529 * Tests if the guest is running in PAE mode or not.
1530 *
1531 * @returns true if in PAE mode, otherwise false.
1532 * @param pVCpu The cross context virtual CPU structure.
1533 */
1534VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu)
1535{
1536 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1537 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1538 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1539 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
1540 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
1541 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
1542}
1543
1544
1545/**
1546 * Tests if the guest is running in 64 bits mode or not.
1547 *
1548 * @returns true if in 64 bits protected mode, otherwise false.
1549 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1550 */
1551VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
1552{
1553 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
1554 if (!CPUMIsGuestInLongMode(pVCpu))
1555 return false;
1556 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1557 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
1558}
1559
1560
1561/**
1562 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
1563 * registers.
1564 *
1565 * @returns true if in 64 bits protected mode, otherwise false.
1566 * @param pCtx Pointer to the current guest CPU context.
1567 */
1568VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
1569{
1570 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
1571}
1572
1573
1574/**
1575 * Sets the specified changed flags (CPUM_CHANGED_*).
1576 *
1577 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1578 * @param fChangedAdd The changed flags to add.
1579 */
1580VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd)
1581{
1582 pVCpu->cpum.s.fChanged |= fChangedAdd;
1583}
1584
1585
1586/**
1587 * Checks if the CPU supports the XSAVE and XRSTOR instruction.
1588 *
1589 * @returns true if supported.
1590 * @returns false if not supported.
1591 * @param pVM The cross context VM structure.
1592 */
1593VMMDECL(bool) CPUMSupportsXSave(PVM pVM)
1594{
1595 return pVM->cpum.s.HostFeatures.fXSaveRstor != 0;
1596}
1597
1598
1599/**
1600 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1601 * @returns true if used.
1602 * @returns false if not used.
1603 * @param pVM The cross context VM structure.
1604 */
1605VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1606{
1607 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
1608}
1609
1610
1611/**
1612 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1613 * @returns true if used.
1614 * @returns false if not used.
1615 * @param pVM The cross context VM structure.
1616 */
1617VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1618{
1619 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
1620}
1621
1622
1623/**
1624 * Checks if we activated the FPU/XMM state of the guest OS.
1625 *
1626 * Obsolete: This differs from CPUMIsGuestFPUStateLoaded() in that it refers to
1627 * the next time we'll be executing guest code, so it may return true for
1628 * 64-on-32 when we still haven't actually loaded the FPU status, just scheduled
1629 * it to be loaded the next time we go thru the world switcher
1630 * (CPUM_SYNC_FPU_STATE).
1631 *
1632 * @returns true / false.
1633 * @param pVCpu The cross context virtual CPU structure.
1634 */
1635VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
1636{
1637 bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1638 AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
1639 return fRet;
1640}
1641
1642
1643/**
1644 * Checks if we've really loaded the FPU/XMM state of the guest OS.
1645 *
1646 * @returns true / false.
1647 * @param pVCpu The cross context virtual CPU structure.
1648 */
1649VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu)
1650{
1651 bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1652 AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
1653 return fRet;
1654}
1655
1656
1657/**
1658 * Checks if we saved the FPU/XMM state of the host OS.
1659 *
1660 * @returns true / false.
1661 * @param pVCpu The cross context virtual CPU structure.
1662 */
1663VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu)
1664{
1665 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST);
1666}
1667
1668
1669/**
1670 * Checks if the guest debug state is active.
1671 *
1672 * @returns boolean
1673 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1674 */
1675VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
1676{
1677 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
1678}
1679
1680
1681/**
1682 * Checks if the hyper debug state is active.
1683 *
1684 * @returns boolean
1685 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1686 */
1687VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
1688{
1689 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
1690}
1691
1692
1693/**
1694 * Mark the guest's debug state as inactive.
1695 *
1696 * @returns boolean
1697 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1698 * @todo This API doesn't make sense any more.
1699 */
1700VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
1701{
1702 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
1703 NOREF(pVCpu);
1704}
1705
1706
1707/**
1708 * Get the current privilege level of the guest.
1709 *
1710 * @returns CPL
1711 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1712 */
1713VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
1714{
1715 /*
1716 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
1717 *
1718 * Note! We used to check CS.DPL here, assuming it was always equal to
1719 * CPL even if a conforming segment was loaded. But this turned out to
1720 * only apply to older AMD-V. With VT-x we had an ACP2 regression
1721 * during install after a far call to ring 2 with VT-x. Then on newer
1722 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
1723 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
1724 *
1725 * So, forget CS.DPL, always use SS.DPL.
1726 *
1727 * Note! The SS RPL is always equal to the CPL, while the CS RPL
1728 * isn't necessarily equal if the segment is conforming.
1729 * See section 4.11.1 in the AMD manual.
1730 *
1731 * Update: Where the heck does it say CS.RPL can differ from CPL other than
1732 * right after real->prot mode switch and when in V8086 mode? That
1733 * section says the RPL specified in a direct transfere (call, jmp,
1734 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
1735 * it would be impossible for an exception handle or the iret
1736 * instruction to figure out whether SS:ESP are part of the frame
1737 * or not. VBox or qemu bug must've lead to this misconception.
1738 *
1739 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
1740 * selector into SS with an RPL other than the CPL when CPL != 3 and
1741 * we're in 64-bit mode. The intel dev box doesn't allow this, on
1742 * RPL = CPL. Weird.
1743 */
1744 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
1745 uint32_t uCpl;
1746 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1747 {
1748 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1749 {
1750 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
1751 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
1752 else
1753 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
1754 }
1755 else
1756 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
1757 }
1758 else
1759 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
1760 return uCpl;
1761}
1762
1763
1764/**
1765 * Gets the current guest CPU mode.
1766 *
1767 * If paging mode is what you need, check out PGMGetGuestMode().
1768 *
1769 * @returns The CPU mode.
1770 * @param pVCpu The cross context virtual CPU structure.
1771 */
1772VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
1773{
1774 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1775 CPUMMODE enmMode;
1776 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1777 enmMode = CPUMMODE_REAL;
1778 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1779 enmMode = CPUMMODE_PROTECTED;
1780 else
1781 enmMode = CPUMMODE_LONG;
1782
1783 return enmMode;
1784}
1785
1786
1787/**
1788 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
1789 *
1790 * @returns 16, 32 or 64.
1791 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1792 */
1793VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
1794{
1795 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1796
1797 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1798 return 16;
1799
1800 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1801 {
1802 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1803 return 16;
1804 }
1805
1806 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1807 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1808 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1809 return 64;
1810
1811 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1812 return 32;
1813
1814 return 16;
1815}
1816
1817
1818VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
1819{
1820 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1821
1822 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1823 return DISCPUMODE_16BIT;
1824
1825 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1826 {
1827 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1828 return DISCPUMODE_16BIT;
1829 }
1830
1831 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1832 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1833 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1834 return DISCPUMODE_64BIT;
1835
1836 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1837 return DISCPUMODE_32BIT;
1838
1839 return DISCPUMODE_16BIT;
1840}
1841
1842
1843/**
1844 * Gets the guest MXCSR_MASK value.
1845 *
1846 * This does not access the x87 state, but the value we determined at VM
1847 * initialization.
1848 *
1849 * @returns MXCSR mask.
1850 * @param pVM The cross context VM structure.
1851 */
1852VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM)
1853{
1854 return pVM->cpum.s.GuestInfo.fMxCsrMask;
1855}
1856
1857
1858/**
1859 * Returns whether the guest has physical interrupts enabled.
1860 *
1861 * @returns @c true if interrupts are enabled, @c false otherwise.
1862 * @param pVCpu The cross context virtual CPU structure.
1863 *
1864 * @remarks Warning! This function does -not- take into account the global-interrupt
1865 * flag (GIF).
1866 */
1867VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu)
1868{
1869 if (!CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest))
1870 {
1871 uint32_t const fEFlags = pVCpu->cpum.s.Guest.eflags.u;
1872 return RT_BOOL(fEFlags & X86_EFL_IF);
1873 }
1874
1875 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
1876 return CPUMIsGuestVmxPhysIntrEnabled(&pVCpu->cpum.s.Guest);
1877
1878 Assert(CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest));
1879 return CPUMIsGuestSvmPhysIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
1880}
1881
1882
1883/**
1884 * Returns whether the nested-guest has virtual interrupts enabled.
1885 *
1886 * @returns @c true if interrupts are enabled, @c false otherwise.
1887 * @param pVCpu The cross context virtual CPU structure.
1888 *
1889 * @remarks Warning! This function does -not- take into account the global-interrupt
1890 * flag (GIF).
1891 */
1892VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu)
1893{
1894 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1895 Assert(CPUMIsGuestInNestedHwvirtMode(pCtx));
1896
1897 if (CPUMIsGuestInVmxNonRootMode(pCtx))
1898 return CPUMIsGuestVmxVirtIntrEnabled(pCtx);
1899
1900 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1901 return CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
1902}
1903
1904
1905/**
1906 * Calculates the interruptiblity of the guest.
1907 *
1908 * @returns Interruptibility level.
1909 * @param pVCpu The cross context virtual CPU structure.
1910 */
1911VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu)
1912{
1913#if 1
1914 /* Global-interrupt flag blocks pretty much everything we care about here. */
1915 if (CPUMGetGuestGif(&pVCpu->cpum.s.Guest))
1916 {
1917 /*
1918 * Physical interrupts are primarily blocked using EFLAGS. However, we cannot access
1919 * it directly here. If and how EFLAGS are used depends on the context (nested-guest
1920 * or raw-mode). Hence we use the function below which handles the details.
1921 */
1922 if ( CPUMIsGuestPhysIntrEnabled(pVCpu)
1923 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
1924 {
1925 if ( !CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest)
1926 || CPUMIsGuestVirtIntrEnabled(pVCpu))
1927 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1928
1929 /* Physical interrupts are enabled, but nested-guest virtual interrupts are disabled. */
1930 return CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED;
1931 }
1932
1933 /*
1934 * Blocking the delivery of NMIs during an interrupt shadow is CPU implementation
1935 * specific. Therefore, in practice, we can't deliver an NMI in an interrupt shadow.
1936 * However, there is some uncertainity regarding the converse, i.e. whether
1937 * NMI-blocking until IRET blocks delivery of physical interrupts.
1938 *
1939 * See Intel spec. 25.4.1 "Event Blocking".
1940 */
1941 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1942 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1943
1944 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1945 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1946
1947 return CPUMINTERRUPTIBILITY_INT_DISABLED;
1948 }
1949 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1950#else
1951 if (pVCpu->cpum.s.Guest.rflags.Bits.u1IF)
1952 {
1953 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
1954 {
1955 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
1956 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1957
1958 /** @todo does blocking NMIs mean interrupts are also inhibited? */
1959 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1960 {
1961 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1962 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1963 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1964 }
1965 AssertFailed();
1966 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1967 }
1968 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1969 }
1970 else
1971 {
1972 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
1973 {
1974 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1975 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1976 return CPUMINTERRUPTIBILITY_INT_DISABLED;
1977 }
1978 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1979 }
1980#endif
1981}
1982
1983
1984/**
1985 * Gets whether the guest (or nested-guest) is currently blocking delivery of NMIs.
1986 *
1987 * @returns @c true if NMIs are blocked, @c false otherwise.
1988 * @param pVCpu The cross context virtual CPU structure.
1989 */
1990VMM_INT_DECL(bool) CPUMIsGuestNmiBlocking(PCVMCPU pVCpu)
1991{
1992 /*
1993 * Return the state of guest-NMI blocking in any of the following cases:
1994 * - We're not executing a nested-guest.
1995 * - We're executing an SVM nested-guest[1].
1996 * - We're executing a VMX nested-guest without virtual-NMIs enabled.
1997 *
1998 * [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
1999 * SVM hypervisors must track NMI blocking themselves by intercepting
2000 * the IRET instruction after injection of an NMI.
2001 */
2002 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2003 if ( !CPUMIsGuestInNestedHwvirtMode(pCtx)
2004 || CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
2005 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
2006 return VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2007
2008 /*
2009 * Return the state of virtual-NMI blocking, if we are executing a
2010 * VMX nested-guest with virtual-NMIs enabled.
2011 */
2012 return CPUMIsGuestVmxVirtNmiBlocking(pCtx);
2013}
2014
2015
2016/**
2017 * Sets blocking delivery of NMIs to the guest.
2018 *
2019 * @param pVCpu The cross context virtual CPU structure.
2020 * @param fBlock Whether NMIs are blocked or not.
2021 */
2022VMM_INT_DECL(void) CPUMSetGuestNmiBlocking(PVMCPU pVCpu, bool fBlock)
2023{
2024 /*
2025 * Set the state of guest-NMI blocking in any of the following cases:
2026 * - We're not executing a nested-guest.
2027 * - We're executing an SVM nested-guest[1].
2028 * - We're executing a VMX nested-guest without virtual-NMIs enabled.
2029 *
2030 * [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
2031 * SVM hypervisors must track NMI blocking themselves by intercepting
2032 * the IRET instruction after injection of an NMI.
2033 */
2034 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2035 if ( !CPUMIsGuestInNestedHwvirtMode(pCtx)
2036 || CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
2037 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
2038 {
2039 if (fBlock)
2040 {
2041 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2042 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2043 }
2044 else
2045 {
2046 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2047 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2048 }
2049 return;
2050 }
2051
2052 /*
2053 * Set the state of virtual-NMI blocking, if we are executing a
2054 * VMX nested-guest with virtual-NMIs enabled.
2055 */
2056 return CPUMSetGuestVmxVirtNmiBlocking(pCtx, fBlock);
2057}
2058
2059
2060/**
2061 * Checks whether the SVM nested-guest has physical interrupts enabled.
2062 *
2063 * @returns true if interrupts are enabled, false otherwise.
2064 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2065 * @param pCtx The guest-CPU context.
2066 *
2067 * @remarks This does -not- take into account the global-interrupt flag.
2068 */
2069VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2070{
2071 /** @todo Optimization: Avoid this function call and use a pointer to the
2072 * relevant eflags instead (setup during VMRUN instruction emulation). */
2073 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2074
2075 X86EFLAGS fEFlags;
2076 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, pCtx))
2077 fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
2078 else
2079 fEFlags.u = pCtx->eflags.u;
2080
2081 return fEFlags.Bits.u1IF;
2082}
2083
2084
2085/**
2086 * Checks whether the SVM nested-guest is in a state to receive virtual (setup
2087 * for injection by VMRUN instruction) interrupts.
2088 *
2089 * @returns VBox status code.
2090 * @retval true if it's ready, false otherwise.
2091 *
2092 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2093 * @param pCtx The guest-CPU context.
2094 */
2095VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2096{
2097 RT_NOREF(pVCpu);
2098 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2099
2100 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.Vmcb.ctrl;
2101 PCSVMINTCTRL pVmcbIntCtrl = &pVmcbCtrl->IntCtrl;
2102 Assert(!pVmcbIntCtrl->n.u1VGifEnable); /* We don't support passing virtual-GIF feature to the guest yet. */
2103 if ( !pVmcbIntCtrl->n.u1IgnoreTPR
2104 && pVmcbIntCtrl->n.u4VIntrPrio <= pVmcbIntCtrl->n.u8VTPR)
2105 return false;
2106
2107 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2108}
2109
2110
2111/**
2112 * Gets the pending SVM nested-guest interruptvector.
2113 *
2114 * @returns The nested-guest interrupt to inject.
2115 * @param pCtx The guest-CPU context.
2116 */
2117VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx)
2118{
2119 return pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u8VIntrVector;
2120}
2121
2122
2123/**
2124 * Restores the host-state from the host-state save area as part of a \#VMEXIT.
2125 *
2126 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2127 * @param pCtx The guest-CPU context.
2128 */
2129VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx)
2130{
2131 /*
2132 * Reload the guest's "host state".
2133 */
2134 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2135 pCtx->es = pHostState->es;
2136 pCtx->cs = pHostState->cs;
2137 pCtx->ss = pHostState->ss;
2138 pCtx->ds = pHostState->ds;
2139 pCtx->gdtr = pHostState->gdtr;
2140 pCtx->idtr = pHostState->idtr;
2141 CPUMSetGuestEferMsrNoChecks(pVCpu, pCtx->msrEFER, pHostState->uEferMsr);
2142 CPUMSetGuestCR0(pVCpu, pHostState->uCr0 | X86_CR0_PE);
2143 pCtx->cr3 = pHostState->uCr3;
2144 CPUMSetGuestCR4(pVCpu, pHostState->uCr4);
2145 pCtx->rflags = pHostState->rflags;
2146 pCtx->rflags.Bits.u1VM = 0;
2147 pCtx->rip = pHostState->uRip;
2148 pCtx->rsp = pHostState->uRsp;
2149 pCtx->rax = pHostState->uRax;
2150 pCtx->dr[7] &= ~(X86_DR7_ENABLED_MASK | X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2151 pCtx->dr[7] |= X86_DR7_RA1_MASK;
2152 Assert(pCtx->ss.Attr.n.u2Dpl == 0);
2153
2154 /** @todo if RIP is not canonical or outside the CS segment limit, we need to
2155 * raise \#GP(0) in the guest. */
2156
2157 /** @todo check the loaded host-state for consistency. Figure out what
2158 * exactly this involves? */
2159}
2160
2161
2162/**
2163 * Saves the host-state to the host-state save area as part of a VMRUN.
2164 *
2165 * @param pCtx The guest-CPU context.
2166 * @param cbInstr The length of the VMRUN instruction in bytes.
2167 */
2168VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr)
2169{
2170 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2171 pHostState->es = pCtx->es;
2172 pHostState->cs = pCtx->cs;
2173 pHostState->ss = pCtx->ss;
2174 pHostState->ds = pCtx->ds;
2175 pHostState->gdtr = pCtx->gdtr;
2176 pHostState->idtr = pCtx->idtr;
2177 pHostState->uEferMsr = pCtx->msrEFER;
2178 pHostState->uCr0 = pCtx->cr0;
2179 pHostState->uCr3 = pCtx->cr3;
2180 pHostState->uCr4 = pCtx->cr4;
2181 pHostState->rflags = pCtx->rflags;
2182 pHostState->uRip = pCtx->rip + cbInstr;
2183 pHostState->uRsp = pCtx->rsp;
2184 pHostState->uRax = pCtx->rax;
2185}
2186
2187
2188/**
2189 * Applies the TSC offset of a nested-guest if any and returns the TSC value for the
2190 * nested-guest.
2191 *
2192 * @returns The TSC offset after applying any nested-guest TSC offset.
2193 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2194 * @param uTscValue The guest TSC.
2195 *
2196 * @sa CPUMRemoveNestedGuestTscOffset.
2197 */
2198VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2199{
2200 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2201 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2202 {
2203 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2204 return uTscValue + pCtx->hwvirt.vmx.Vmcs.u64TscOffset.u;
2205 return uTscValue;
2206 }
2207
2208 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2209 {
2210 uint64_t offTsc;
2211 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2212 offTsc = pCtx->hwvirt.svm.Vmcb.ctrl.u64TSCOffset;
2213 return uTscValue + offTsc;
2214 }
2215 return uTscValue;
2216}
2217
2218
2219/**
2220 * Removes the TSC offset of a nested-guest if any and returns the TSC value for the
2221 * guest.
2222 *
2223 * @returns The TSC offset after removing any nested-guest TSC offset.
2224 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2225 * @param uTscValue The nested-guest TSC.
2226 *
2227 * @sa CPUMApplyNestedGuestTscOffset.
2228 */
2229VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2230{
2231 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2232 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2233 {
2234 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2235 return uTscValue - pCtx->hwvirt.vmx.Vmcs.u64TscOffset.u;
2236 return uTscValue;
2237 }
2238
2239 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2240 {
2241 uint64_t offTsc;
2242 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2243 offTsc = pCtx->hwvirt.svm.Vmcb.ctrl.u64TSCOffset;
2244 return uTscValue - offTsc;
2245 }
2246 return uTscValue;
2247}
2248
2249
2250/**
2251 * Used to dynamically imports state residing in NEM or HM.
2252 *
2253 * This is a worker for the CPUM_IMPORT_EXTRN_RET() macro and various IEM ones.
2254 *
2255 * @returns VBox status code.
2256 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2257 * @param fExtrnImport The fields to import.
2258 * @thread EMT(pVCpu)
2259 */
2260VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport)
2261{
2262 VMCPU_ASSERT_EMT(pVCpu);
2263 if (pVCpu->cpum.s.Guest.fExtrn & fExtrnImport)
2264 {
2265 switch (pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_KEEPER_MASK)
2266 {
2267 case CPUMCTX_EXTRN_KEEPER_NEM:
2268 {
2269 int rc = NEMImportStateOnDemand(pVCpu, fExtrnImport);
2270 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2271 return rc;
2272 }
2273
2274 case CPUMCTX_EXTRN_KEEPER_HM:
2275 {
2276#ifdef IN_RING0
2277 int rc = HMR0ImportStateOnDemand(pVCpu, fExtrnImport);
2278 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2279 return rc;
2280#else
2281 AssertLogRelMsgFailed(("TODO Fetch HM state: %#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport));
2282 return VINF_SUCCESS;
2283#endif
2284 }
2285 default:
2286 AssertLogRelMsgFailedReturn(("%#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport), VERR_CPUM_IPE_2);
2287 }
2288 }
2289 return VINF_SUCCESS;
2290}
2291
2292
2293/**
2294 * Gets valid CR4 bits for the guest.
2295 *
2296 * @returns Valid CR4 bits.
2297 * @param pVM The cross context VM structure.
2298 */
2299VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM)
2300{
2301 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
2302 uint64_t fMask = X86_CR4_VME | X86_CR4_PVI
2303 | X86_CR4_TSD | X86_CR4_DE
2304 | X86_CR4_MCE | X86_CR4_PCE;
2305 if (pGuestFeatures->fPae)
2306 fMask |= X86_CR4_PAE;
2307 if (pGuestFeatures->fPge)
2308 fMask |= X86_CR4_PGE;
2309 if (pGuestFeatures->fPse)
2310 fMask |= X86_CR4_PSE;
2311 if (pGuestFeatures->fFxSaveRstor)
2312 fMask |= X86_CR4_OSFXSR;
2313 if (pGuestFeatures->fVmx)
2314 fMask |= X86_CR4_VMXE;
2315 if (pGuestFeatures->fXSaveRstor)
2316 fMask |= X86_CR4_OSXSAVE;
2317 if (pGuestFeatures->fPcid)
2318 fMask |= X86_CR4_PCIDE;
2319 if (pGuestFeatures->fFsGsBase)
2320 fMask |= X86_CR4_FSGSBASE;
2321 if (pGuestFeatures->fSse)
2322 fMask |= X86_CR4_OSXMMEEXCPT;
2323 return fMask;
2324}
2325
2326
2327/**
2328 * Sets the PAE PDPEs for the guest.
2329 *
2330 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2331 * @param paPaePdpes The PAE PDPEs to set.
2332 */
2333VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes)
2334{
2335 Assert(paPaePdpes);
2336 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
2337 pVCpu->cpum.s.Guest.aPaePdpes[i].u = paPaePdpes[i].u;
2338 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
2339}
2340
2341
2342/**
2343 * Gets the PAE PDPTEs for the guest.
2344 *
2345 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2346 * @param paPaePdpes Where to store the PAE PDPEs.
2347 */
2348VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes)
2349{
2350 Assert(paPaePdpes);
2351 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
2352 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
2353 paPaePdpes[i].u = pVCpu->cpum.s.Guest.aPaePdpes[i].u;
2354}
2355
2356
2357/**
2358 * Starts a VMX-preemption timer to expire as specified by the nested hypervisor.
2359 *
2360 * @returns VBox status code.
2361 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2362 * @param uTimer The VMCS preemption timer value.
2363 * @param cShift The VMX-preemption timer shift (usually based on guest
2364 * VMX MSR rate).
2365 * @param pu64EntryTick Where to store the current tick when the timer is
2366 * programmed.
2367 * @thread EMT(pVCpu)
2368 */
2369VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick)
2370{
2371 Assert(uTimer);
2372 Assert(cShift <= 31);
2373 Assert(pu64EntryTick);
2374 VMCPU_ASSERT_EMT(pVCpu);
2375 uint64_t const cTicksToNext = uTimer << cShift;
2376 return TMTimerSetRelative(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.hNestedVmxPreemptTimer, cTicksToNext, pu64EntryTick);
2377}
2378
2379
2380/**
2381 * Stops the VMX-preemption timer from firing.
2382 *
2383 * @returns VBox status code.
2384 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2385 * @thread EMT.
2386 *
2387 * @remarks This can be called during VM reset, so we cannot assume it will be on
2388 * the EMT corresponding to @c pVCpu.
2389 */
2390VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu)
2391{
2392 /*
2393 * CPUM gets initialized before TM, so we defer creation of timers till CPUMR3InitCompleted().
2394 * However, we still get called during CPUMR3Init() and hence we need to check if we have
2395 * a valid timer object before trying to stop it.
2396 */
2397 int rc;
2398 TMTIMERHANDLE hTimer = pVCpu->cpum.s.hNestedVmxPreemptTimer;
2399 if (hTimer != NIL_TMTIMERHANDLE)
2400 {
2401 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2402 rc = TMTimerLock(pVM, hTimer, VERR_IGNORED);
2403 if (rc == VINF_SUCCESS)
2404 {
2405 if (TMTimerIsActive(pVM, hTimer))
2406 TMTimerStop(pVM, hTimer);
2407 TMTimerUnlock(pVM, hTimer);
2408 }
2409 }
2410 else
2411 rc = VERR_NOT_FOUND;
2412 return rc;
2413}
2414
2415
2416/**
2417 * Gets the read and write permission bits for an MSR in an MSR bitmap.
2418 *
2419 * @returns VMXMSRPM_XXX - the MSR permission.
2420 * @param pvMsrBitmap Pointer to the MSR bitmap.
2421 * @param idMsr The MSR to get permissions for.
2422 *
2423 * @sa hmR0VmxSetMsrPermission.
2424 */
2425VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr)
2426{
2427 AssertPtrReturn(pvMsrBitmap, VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR);
2428
2429 uint8_t const * const pbMsrBitmap = (uint8_t const * const)pvMsrBitmap;
2430
2431 /*
2432 * MSR Layout:
2433 * Byte index MSR range Interpreted as
2434 * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
2435 * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
2436 * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
2437 * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
2438 *
2439 * A bit corresponding to an MSR within the above range causes a VM-exit
2440 * if the bit is 1 on executions of RDMSR/WRMSR. If an MSR falls out of
2441 * the MSR range, it always cause a VM-exit.
2442 *
2443 * See Intel spec. 24.6.9 "MSR-Bitmap Address".
2444 */
2445 uint32_t const offBitmapRead = 0;
2446 uint32_t const offBitmapWrite = 0x800;
2447 uint32_t offMsr;
2448 uint32_t iBit;
2449 if (idMsr <= UINT32_C(0x00001fff))
2450 {
2451 offMsr = 0;
2452 iBit = idMsr;
2453 }
2454 else if (idMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
2455 {
2456 offMsr = 0x400;
2457 iBit = idMsr - UINT32_C(0xc0000000);
2458 }
2459 else
2460 {
2461 LogFunc(("Warning! Out of range MSR %#RX32\n", idMsr));
2462 return VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR;
2463 }
2464
2465 /*
2466 * Get the MSR read permissions.
2467 */
2468 uint32_t fRet;
2469 uint32_t const offMsrRead = offBitmapRead + offMsr;
2470 Assert(offMsrRead + (iBit >> 3) < offBitmapWrite);
2471 if (ASMBitTest(pbMsrBitmap + offMsrRead, iBit))
2472 fRet = VMXMSRPM_EXIT_RD;
2473 else
2474 fRet = VMXMSRPM_ALLOW_RD;
2475
2476 /*
2477 * Get the MSR write permissions.
2478 */
2479 uint32_t const offMsrWrite = offBitmapWrite + offMsr;
2480 Assert(offMsrWrite + (iBit >> 3) < X86_PAGE_4K_SIZE);
2481 if (ASMBitTest(pbMsrBitmap + offMsrWrite, iBit))
2482 fRet |= VMXMSRPM_EXIT_WR;
2483 else
2484 fRet |= VMXMSRPM_ALLOW_WR;
2485
2486 Assert(VMXMSRPM_IS_FLAG_VALID(fRet));
2487 return fRet;
2488}
2489
2490
2491/**
2492 * Checks the permission bits for the specified I/O port from the given I/O bitmap
2493 * to see if causes a VM-exit.
2494 *
2495 * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
2496 * @param pbIoBitmap Pointer to I/O bitmap.
2497 * @param uPort The I/O port being accessed.
2498 * @param cbAccess e size of the I/O access in bytes (1, 2 or 4 bytes).
2499 */
2500static bool cpumGetVmxIoBitmapPermission(uint8_t const *pbIoBitmap, uint16_t uPort, uint8_t cbAccess)
2501{
2502 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
2503
2504 /*
2505 * If the I/O port access wraps around the 16-bit port I/O space, we must cause a
2506 * VM-exit.
2507 *
2508 * Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc are valid and do not
2509 * constitute a wrap around. However, reading 2 bytes at port 0xffff or 4 bytes
2510 * from port 0xffff/0xfffe/0xfffd constitute a wrap around. In other words, any
2511 * access to -both- ports 0xffff and port 0 is a wrap around.
2512 *
2513 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2514 */
2515 uint32_t const uPortLast = uPort + cbAccess;
2516 if (uPortLast > 0x10000)
2517 return true;
2518
2519 /*
2520 * If any bit corresponding to the I/O access is set, we must cause a VM-exit.
2521 */
2522 uint16_t const offPerm = uPort >> 3; /* Byte offset of the port. */
2523 uint16_t const idxPermBit = uPort - (offPerm << 3); /* Bit offset within byte. */
2524 Assert(idxPermBit < 8);
2525 static const uint8_t s_afMask[] = { 0x0, 0x1, 0x3, 0x7, 0xf }; /* Bit-mask for all access sizes. */
2526 uint16_t const fMask = s_afMask[cbAccess] << idxPermBit; /* Bit-mask of the access. */
2527
2528 /* Fetch 8 or 16-bits depending on whether the access spans 8-bit boundary. */
2529 RTUINT16U uPerm;
2530 uPerm.s.Lo = pbIoBitmap[offPerm];
2531 if (idxPermBit + cbAccess > 8)
2532 uPerm.s.Hi = pbIoBitmap[offPerm + 1];
2533 else
2534 uPerm.s.Hi = 0;
2535
2536 /* If any bit for the access is 1, we must cause a VM-exit. */
2537 if (uPerm.u & fMask)
2538 return true;
2539
2540 return false;
2541}
2542
2543
2544/**
2545 * Returns whether the given VMCS field is valid and supported for the guest.
2546 *
2547 * @param pVM The cross context VM structure.
2548 * @param u64VmcsField The VMCS field.
2549 *
2550 * @remarks This takes into account the CPU features exposed to the guest.
2551 */
2552VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField)
2553{
2554 uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
2555 uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
2556 if (!uFieldEncHi)
2557 { /* likely */ }
2558 else
2559 return false;
2560
2561 PCCPUMFEATURES pFeat = &pVM->cpum.s.GuestFeatures;
2562 switch (uFieldEncLo)
2563 {
2564 /*
2565 * 16-bit fields.
2566 */
2567 /* Control fields. */
2568 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
2569 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
2570 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
2571
2572 /* Guest-state fields. */
2573 case VMX_VMCS16_GUEST_ES_SEL:
2574 case VMX_VMCS16_GUEST_CS_SEL:
2575 case VMX_VMCS16_GUEST_SS_SEL:
2576 case VMX_VMCS16_GUEST_DS_SEL:
2577 case VMX_VMCS16_GUEST_FS_SEL:
2578 case VMX_VMCS16_GUEST_GS_SEL:
2579 case VMX_VMCS16_GUEST_LDTR_SEL:
2580 case VMX_VMCS16_GUEST_TR_SEL: return true;
2581 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
2582 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
2583
2584 /* Host-state fields. */
2585 case VMX_VMCS16_HOST_ES_SEL:
2586 case VMX_VMCS16_HOST_CS_SEL:
2587 case VMX_VMCS16_HOST_SS_SEL:
2588 case VMX_VMCS16_HOST_DS_SEL:
2589 case VMX_VMCS16_HOST_FS_SEL:
2590 case VMX_VMCS16_HOST_GS_SEL:
2591 case VMX_VMCS16_HOST_TR_SEL: return true;
2592
2593 /*
2594 * 64-bit fields.
2595 */
2596 /* Control fields. */
2597 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
2598 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
2599 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
2600 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
2601 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
2602 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
2603 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
2604 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
2605 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
2606 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
2607 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
2608 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
2609 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
2610 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
2611 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
2612 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
2613 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
2614 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
2615 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
2616 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
2617 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
2618 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
2619 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
2620 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
2621 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
2622 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
2623 case VMX_VMCS64_CTRL_EPTP_FULL:
2624 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
2625 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
2626 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
2627 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
2628 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
2629 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
2630 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
2631 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
2632 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
2633 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
2634 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
2635 {
2636 PCVMCPU pVCpu = pVM->CTX_SUFF(apCpus)[0];
2637 uint64_t const uVmFuncMsr = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
2638 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
2639 }
2640 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
2641 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
2642 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
2643 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
2644 case VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL:
2645 case VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
2646 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
2647 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
2648 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
2649 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
2650 case VMX_VMCS64_CTRL_PROC_EXEC3_FULL:
2651 case VMX_VMCS64_CTRL_PROC_EXEC3_HIGH: return pFeat->fVmxTertiaryExecCtls;
2652
2653 /* Read-only data fields. */
2654 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
2655 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
2656
2657 /* Guest-state fields. */
2658 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
2659 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
2660 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
2661 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
2662 case VMX_VMCS64_GUEST_PAT_FULL:
2663 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
2664 case VMX_VMCS64_GUEST_EFER_FULL:
2665 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
2666 case VMX_VMCS64_GUEST_PDPTE0_FULL:
2667 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
2668 case VMX_VMCS64_GUEST_PDPTE1_FULL:
2669 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
2670 case VMX_VMCS64_GUEST_PDPTE2_FULL:
2671 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
2672 case VMX_VMCS64_GUEST_PDPTE3_FULL:
2673 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
2674
2675 /* Host-state fields. */
2676 case VMX_VMCS64_HOST_PAT_FULL:
2677 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
2678 case VMX_VMCS64_HOST_EFER_FULL:
2679 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
2680
2681 /*
2682 * 32-bit fields.
2683 */
2684 /* Control fields. */
2685 case VMX_VMCS32_CTRL_PIN_EXEC:
2686 case VMX_VMCS32_CTRL_PROC_EXEC:
2687 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
2688 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
2689 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
2690 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
2691 case VMX_VMCS32_CTRL_EXIT:
2692 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
2693 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
2694 case VMX_VMCS32_CTRL_ENTRY:
2695 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
2696 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
2697 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
2698 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
2699 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
2700 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
2701 case VMX_VMCS32_CTRL_PLE_GAP:
2702 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
2703
2704 /* Read-only data fields. */
2705 case VMX_VMCS32_RO_VM_INSTR_ERROR:
2706 case VMX_VMCS32_RO_EXIT_REASON:
2707 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
2708 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
2709 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
2710 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
2711 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
2712 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
2713
2714 /* Guest-state fields. */
2715 case VMX_VMCS32_GUEST_ES_LIMIT:
2716 case VMX_VMCS32_GUEST_CS_LIMIT:
2717 case VMX_VMCS32_GUEST_SS_LIMIT:
2718 case VMX_VMCS32_GUEST_DS_LIMIT:
2719 case VMX_VMCS32_GUEST_FS_LIMIT:
2720 case VMX_VMCS32_GUEST_GS_LIMIT:
2721 case VMX_VMCS32_GUEST_LDTR_LIMIT:
2722 case VMX_VMCS32_GUEST_TR_LIMIT:
2723 case VMX_VMCS32_GUEST_GDTR_LIMIT:
2724 case VMX_VMCS32_GUEST_IDTR_LIMIT:
2725 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
2726 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
2727 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
2728 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
2729 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
2730 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
2731 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
2732 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
2733 case VMX_VMCS32_GUEST_INT_STATE:
2734 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
2735 case VMX_VMCS32_GUEST_SMBASE:
2736 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
2737 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
2738
2739 /* Host-state fields. */
2740 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
2741
2742 /*
2743 * Natural-width fields.
2744 */
2745 /* Control fields. */
2746 case VMX_VMCS_CTRL_CR0_MASK:
2747 case VMX_VMCS_CTRL_CR4_MASK:
2748 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
2749 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
2750 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
2751 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
2752 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
2753 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
2754
2755 /* Read-only data fields. */
2756 case VMX_VMCS_RO_EXIT_QUALIFICATION:
2757 case VMX_VMCS_RO_IO_RCX:
2758 case VMX_VMCS_RO_IO_RSI:
2759 case VMX_VMCS_RO_IO_RDI:
2760 case VMX_VMCS_RO_IO_RIP:
2761 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
2762
2763 /* Guest-state fields. */
2764 case VMX_VMCS_GUEST_CR0:
2765 case VMX_VMCS_GUEST_CR3:
2766 case VMX_VMCS_GUEST_CR4:
2767 case VMX_VMCS_GUEST_ES_BASE:
2768 case VMX_VMCS_GUEST_CS_BASE:
2769 case VMX_VMCS_GUEST_SS_BASE:
2770 case VMX_VMCS_GUEST_DS_BASE:
2771 case VMX_VMCS_GUEST_FS_BASE:
2772 case VMX_VMCS_GUEST_GS_BASE:
2773 case VMX_VMCS_GUEST_LDTR_BASE:
2774 case VMX_VMCS_GUEST_TR_BASE:
2775 case VMX_VMCS_GUEST_GDTR_BASE:
2776 case VMX_VMCS_GUEST_IDTR_BASE:
2777 case VMX_VMCS_GUEST_DR7:
2778 case VMX_VMCS_GUEST_RSP:
2779 case VMX_VMCS_GUEST_RIP:
2780 case VMX_VMCS_GUEST_RFLAGS:
2781 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
2782 case VMX_VMCS_GUEST_SYSENTER_ESP:
2783 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
2784
2785 /* Host-state fields. */
2786 case VMX_VMCS_HOST_CR0:
2787 case VMX_VMCS_HOST_CR3:
2788 case VMX_VMCS_HOST_CR4:
2789 case VMX_VMCS_HOST_FS_BASE:
2790 case VMX_VMCS_HOST_GS_BASE:
2791 case VMX_VMCS_HOST_TR_BASE:
2792 case VMX_VMCS_HOST_GDTR_BASE:
2793 case VMX_VMCS_HOST_IDTR_BASE:
2794 case VMX_VMCS_HOST_SYSENTER_ESP:
2795 case VMX_VMCS_HOST_SYSENTER_EIP:
2796 case VMX_VMCS_HOST_RSP:
2797 case VMX_VMCS_HOST_RIP: return true;
2798 }
2799
2800 return false;
2801}
2802
2803
2804/**
2805 * Checks whether the given I/O access should cause a nested-guest VM-exit.
2806 *
2807 * @returns @c true if it causes a VM-exit, @c false otherwise.
2808 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2809 * @param u16Port The I/O port being accessed.
2810 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
2811 */
2812VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
2813{
2814 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2815 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_UNCOND_IO_EXIT))
2816 return true;
2817
2818 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_IO_BITMAPS))
2819 return cpumGetVmxIoBitmapPermission(pCtx->hwvirt.vmx.abIoBitmap, u16Port, cbAccess);
2820
2821 return false;
2822}
2823
2824
2825/**
2826 * Checks whether the Mov-to-CR3 instruction causes a nested-guest VM-exit.
2827 *
2828 * @returns @c true if it causes a VM-exit, @c false otherwise.
2829 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2830 * @param uNewCr3 The CR3 value being written.
2831 */
2832VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3)
2833{
2834 /*
2835 * If the CR3-load exiting control is set and the new CR3 value does not
2836 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
2837 *
2838 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2839 */
2840 PCCPUMCTX const pCtx = &pVCpu->cpum.s.Guest;
2841 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_CR3_LOAD_EXIT))
2842 {
2843 uint32_t const uCr3TargetCount = pCtx->hwvirt.vmx.Vmcs.u32Cr3TargetCount;
2844 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
2845
2846 /* If the CR3-target count is 0, cause a VM-exit. */
2847 if (uCr3TargetCount == 0)
2848 return true;
2849
2850 /* If the CR3 being written doesn't match any of the target values, cause a VM-exit. */
2851 AssertCompile(VMX_V_CR3_TARGET_COUNT == 4);
2852 if ( uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target0.u
2853 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target1.u
2854 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target2.u
2855 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target3.u)
2856 return true;
2857 }
2858 return false;
2859}
2860
2861
2862/**
2863 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field causes a
2864 * VM-exit or not.
2865 *
2866 * @returns @c true if the VMREAD/VMWRITE is intercepted, @c false otherwise.
2867 * @param pVCpu The cross context virtual CPU structure.
2868 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
2869 * VMX_EXIT_VMREAD).
2870 * @param u64VmcsField The VMCS field.
2871 */
2872VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64VmcsField)
2873{
2874 Assert(CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest));
2875 Assert( uExitReason == VMX_EXIT_VMREAD
2876 || uExitReason == VMX_EXIT_VMWRITE);
2877
2878 /*
2879 * Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted.
2880 */
2881 if (!CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VMCS_SHADOWING))
2882 return true;
2883
2884 /*
2885 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE
2886 * is intercepted. This excludes any reserved bits in the valid parts of the field
2887 * encoding (i.e. bit 12).
2888 */
2889 if (u64VmcsField & VMX_VMCSFIELD_RSVD_MASK)
2890 return true;
2891
2892 /*
2893 * Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not.
2894 */
2895 uint32_t const u32VmcsField = RT_LO_U32(u64VmcsField);
2896 uint8_t const * const pbBitmap = uExitReason == VMX_EXIT_VMREAD
2897 ? &pVCpu->cpum.s.Guest.hwvirt.vmx.abVmreadBitmap[0]
2898 : &pVCpu->cpum.s.Guest.hwvirt.vmx.abVmwriteBitmap[0];
2899 Assert(pbBitmap);
2900 Assert(u32VmcsField >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2901 return ASMBitTest(&pbBitmap[u32VmcsField >> 3], u32VmcsField & 7);
2902}
2903
2904
2905
2906/**
2907 * Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
2908 *
2909 * @param pvIoBitmap Pointer to the nested-guest IO bitmap.
2910 * @param u16Port The IO port being accessed.
2911 * @param enmIoType The type of IO access.
2912 * @param cbReg The IO operand size in bytes.
2913 * @param cAddrSizeBits The address size bits (for 16, 32 or 64).
2914 * @param iEffSeg The effective segment number.
2915 * @param fRep Whether this is a repeating IO instruction (REP prefix).
2916 * @param fStrIo Whether this is a string IO instruction.
2917 * @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
2918 * Optional, can be NULL.
2919 */
2920VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
2921 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
2922 PSVMIOIOEXITINFO pIoExitInfo)
2923{
2924 Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64);
2925 Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8);
2926
2927 /*
2928 * The IOPM layout:
2929 * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
2930 * two 4K pages.
2931 *
2932 * For IO instructions that access more than a single byte, the permission bits
2933 * for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
2934 *
2935 * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
2936 * we need 3 extra bits beyond the second 4K page.
2937 */
2938 static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
2939
2940 uint16_t const offIopm = u16Port >> 3;
2941 uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
2942 uint8_t const cShift = u16Port - (offIopm << 3);
2943 uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift);
2944
2945 uint8_t const *pbIopm = (uint8_t *)pvIoBitmap;
2946 Assert(pbIopm);
2947 pbIopm += offIopm;
2948 uint16_t const u16Iopm = *(uint16_t *)pbIopm;
2949 if (u16Iopm & fIopmMask)
2950 {
2951 if (pIoExitInfo)
2952 {
2953 static const uint32_t s_auIoOpSize[] =
2954 { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
2955
2956 static const uint32_t s_auIoAddrSize[] =
2957 { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
2958
2959 pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
2960 pIoExitInfo->u |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
2961 pIoExitInfo->n.u1Str = fStrIo;
2962 pIoExitInfo->n.u1Rep = fRep;
2963 pIoExitInfo->n.u3Seg = iEffSeg & 7;
2964 pIoExitInfo->n.u1Type = enmIoType;
2965 pIoExitInfo->n.u16Port = u16Port;
2966 }
2967 return true;
2968 }
2969
2970 /** @todo remove later (for debugging as VirtualBox always traps all IO
2971 * intercepts). */
2972 AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
2973 return false;
2974}
2975
2976
2977/**
2978 * Gets the MSR permission bitmap byte and bit offset for the specified MSR.
2979 *
2980 * @returns VBox status code.
2981 * @param idMsr The MSR being requested.
2982 * @param pbOffMsrpm Where to store the byte offset in the MSR permission
2983 * bitmap for @a idMsr.
2984 * @param puMsrpmBit Where to store the bit offset starting at the byte
2985 * returned in @a pbOffMsrpm.
2986 */
2987VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit)
2988{
2989 Assert(pbOffMsrpm);
2990 Assert(puMsrpmBit);
2991
2992 /*
2993 * MSRPM Layout:
2994 * Byte offset MSR range
2995 * 0x000 - 0x7ff 0x00000000 - 0x00001fff
2996 * 0x800 - 0xfff 0xc0000000 - 0xc0001fff
2997 * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
2998 * 0x1800 - 0x1fff Reserved
2999 *
3000 * Each MSR is represented by 2 permission bits (read and write).
3001 */
3002 if (idMsr <= 0x00001fff)
3003 {
3004 /* Pentium-compatible MSRs. */
3005 uint32_t const bitoffMsr = idMsr << 1;
3006 *pbOffMsrpm = bitoffMsr >> 3;
3007 *puMsrpmBit = bitoffMsr & 7;
3008 return VINF_SUCCESS;
3009 }
3010
3011 if ( idMsr >= 0xc0000000
3012 && idMsr <= 0xc0001fff)
3013 {
3014 /* AMD Sixth Generation x86 Processor MSRs. */
3015 uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
3016 *pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
3017 *puMsrpmBit = bitoffMsr & 7;
3018 return VINF_SUCCESS;
3019 }
3020
3021 if ( idMsr >= 0xc0010000
3022 && idMsr <= 0xc0011fff)
3023 {
3024 /* AMD Seventh and Eighth Generation Processor MSRs. */
3025 uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
3026 *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
3027 *puMsrpmBit = bitoffMsr & 7;
3028 return VINF_SUCCESS;
3029 }
3030
3031 *pbOffMsrpm = 0;
3032 *puMsrpmBit = 0;
3033 return VERR_OUT_OF_RANGE;
3034}
3035
3036
3037/**
3038 * Checks whether the guest is in VMX non-root mode and using EPT paging.
3039 *
3040 * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
3041 * @param pVCpu The cross context virtual CPU structure.
3042 */
3043VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu)
3044{
3045 return CPUMIsGuestVmxEptPagingEnabledEx(&pVCpu->cpum.s.Guest);
3046}
3047
3048
3049/**
3050 * Checks whether the guest is in VMX non-root mode and using EPT paging and the
3051 * nested-guest is in PAE mode.
3052 *
3053 * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
3054 * @param pVCpu The cross context virtual CPU structure.
3055 */
3056VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu)
3057{
3058 return CPUMIsGuestVmxEptPagingEnabledEx(&pVCpu->cpum.s.Guest)
3059 && CPUMIsGuestInPAEModeEx(&pVCpu->cpum.s.Guest);
3060}
3061
3062
3063/**
3064 * Returns the guest-physical address of the APIC-access page when executing a
3065 * nested-guest.
3066 *
3067 * @returns The APIC-access page guest-physical address.
3068 * @param pVCpu The cross context virtual CPU structure.
3069 */
3070VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu)
3071{
3072 return CPUMGetGuestVmxApicAccessPageAddrEx(&pVCpu->cpum.s.Guest);
3073}
3074
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