VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 87633

Last change on this file since 87633 was 87361, checked in by vboxsync, 4 years ago

VMM/CPUM,HMSVM: Mirror the state of fUseFlags[CPUM_USED_FPU_GUEST] in CPUMCTX::fUsedFpuGuest so the HM switcher code can get at it (only relevant for windows) and avoid a call to CPUMIsGuestFPUStateActive/Loaded.
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  • Property svn:keywords set to Id Revision
File size: 97.3 KB
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1/* $Id: CPUMAllRegs.cpp 87361 2021-01-21 21:13:55Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/dbgf.h>
25#include <VBox/vmm/apic.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/em.h>
29#include <VBox/vmm/nem.h>
30#include <VBox/vmm/hm.h>
31#include "CPUMInternal.h"
32#include <VBox/vmm/vmcc.h>
33#include <VBox/err.h>
34#include <VBox/dis.h>
35#include <VBox/log.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/tm.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/asm-amd64-x86.h>
41#ifdef IN_RING3
42# include <iprt/thread.h>
43#endif
44
45/** Disable stack frame pointer generation here. */
46#if defined(_MSC_VER) && !defined(DEBUG) && defined(RT_ARCH_X86)
47# pragma optimize("y", off)
48#endif
49
50AssertCompile2MemberOffsets(VM, cpum.s.HostFeatures, cpum.ro.HostFeatures);
51AssertCompile2MemberOffsets(VM, cpum.s.GuestFeatures, cpum.ro.GuestFeatures);
52
53
54/*********************************************************************************************************************************
55* Defined Constants And Macros *
56*********************************************************************************************************************************/
57/**
58 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
59 *
60 * @returns Pointer to the Virtual CPU.
61 * @param a_pGuestCtx Pointer to the guest context.
62 */
63#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
64
65/**
66 * Lazily loads the hidden parts of a selector register when using raw-mode.
67 */
68#define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
69 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg))
70
71/** @def CPUM_INT_ASSERT_NOT_EXTRN
72 * Macro for asserting that @a a_fNotExtrn are present.
73 *
74 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
75 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
76 */
77#define CPUM_INT_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
78 AssertMsg(!((a_pVCpu)->cpum.s.Guest.fExtrn & (a_fNotExtrn)), \
79 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.s.Guest.fExtrn, (a_fNotExtrn)))
80
81
82VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
83{
84 pVCpu->cpum.s.Hyper.cr3 = cr3;
85}
86
87VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
88{
89 return pVCpu->cpum.s.Hyper.cr3;
90}
91
92
93/** @def MAYBE_LOAD_DRx
94 * Macro for updating DRx values in raw-mode and ring-0 contexts.
95 */
96#ifdef IN_RING0
97# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { a_fnLoad(a_uValue); } while (0)
98#else
99# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
100#endif
101
102VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
103{
104 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
105 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
106}
107
108
109VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
110{
111 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
112 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
113}
114
115
116VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
117{
118 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
119 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
120}
121
122
123VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
124{
125 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
126 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
127}
128
129
130VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
131{
132 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
133}
134
135
136VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
137{
138 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
139}
140
141
142VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
143{
144 return pVCpu->cpum.s.Hyper.dr[0];
145}
146
147
148VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
149{
150 return pVCpu->cpum.s.Hyper.dr[1];
151}
152
153
154VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
155{
156 return pVCpu->cpum.s.Hyper.dr[2];
157}
158
159
160VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
161{
162 return pVCpu->cpum.s.Hyper.dr[3];
163}
164
165
166VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
167{
168 return pVCpu->cpum.s.Hyper.dr[6];
169}
170
171
172VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
173{
174 return pVCpu->cpum.s.Hyper.dr[7];
175}
176
177
178/**
179 * Gets the pointer to the internal CPUMCTXCORE structure.
180 * This is only for reading in order to save a few calls.
181 *
182 * @param pVCpu The cross context virtual CPU structure.
183 */
184VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
185{
186 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
187}
188
189
190/**
191 * Queries the pointer to the internal CPUMCTX structure.
192 *
193 * @returns The CPUMCTX pointer.
194 * @param pVCpu The cross context virtual CPU structure.
195 */
196VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
197{
198 return &pVCpu->cpum.s.Guest;
199}
200
201
202/**
203 * Queries the pointer to the internal CPUMCTXMSRS structure.
204 *
205 * This is for NEM only.
206 *
207 * @returns The CPUMCTX pointer.
208 * @param pVCpu The cross context virtual CPU structure.
209 */
210VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu)
211{
212 return &pVCpu->cpum.s.GuestMsrs;
213}
214
215
216VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
217{
218 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
219 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
220 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_GDTR;
221 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
222 return VINF_SUCCESS; /* formality, consider it void. */
223}
224
225
226VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
227{
228 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
229 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
230 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_IDTR;
231 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
232 return VINF_SUCCESS; /* formality, consider it void. */
233}
234
235
236VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
237{
238 pVCpu->cpum.s.Guest.tr.Sel = tr;
239 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
240 return VINF_SUCCESS; /* formality, consider it void. */
241}
242
243
244VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
245{
246 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
247 /* The caller will set more hidden bits if it has them. */
248 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
249 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
250 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
251 return VINF_SUCCESS; /* formality, consider it void. */
252}
253
254
255/**
256 * Set the guest CR0.
257 *
258 * When called in GC, the hyper CR0 may be updated if that is
259 * required. The caller only has to take special action if AM,
260 * WP, PG or PE changes.
261 *
262 * @returns VINF_SUCCESS (consider it void).
263 * @param pVCpu The cross context virtual CPU structure.
264 * @param cr0 The new CR0 value.
265 */
266VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0)
267{
268 /*
269 * Check for changes causing TLB flushes (for REM).
270 * The caller is responsible for calling PGM when appropriate.
271 */
272 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
273 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
274 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
275 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
276
277 /*
278 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
279 */
280 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
281 PGMCr0WpEnabled(pVCpu);
282
283 /* The ET flag is settable on a 386 and hardwired on 486+. */
284 if ( !(cr0 & X86_CR0_ET)
285 && pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386)
286 cr0 |= X86_CR0_ET;
287
288 pVCpu->cpum.s.Guest.cr0 = cr0;
289 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR0;
290 return VINF_SUCCESS;
291}
292
293
294VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
295{
296 pVCpu->cpum.s.Guest.cr2 = cr2;
297 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR2;
298 return VINF_SUCCESS;
299}
300
301
302VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
303{
304 pVCpu->cpum.s.Guest.cr3 = cr3;
305 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
306 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
307 return VINF_SUCCESS;
308}
309
310
311VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
312{
313 /* Note! We don't bother with OSXSAVE and legacy CPUID patches. */
314
315 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
316 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
317 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
318
319 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
320 pVCpu->cpum.s.Guest.cr4 = cr4;
321 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR4;
322 return VINF_SUCCESS;
323}
324
325
326VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
327{
328 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
329 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
330 return VINF_SUCCESS;
331}
332
333
334VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
335{
336 pVCpu->cpum.s.Guest.eip = eip;
337 return VINF_SUCCESS;
338}
339
340
341VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
342{
343 pVCpu->cpum.s.Guest.eax = eax;
344 return VINF_SUCCESS;
345}
346
347
348VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
349{
350 pVCpu->cpum.s.Guest.ebx = ebx;
351 return VINF_SUCCESS;
352}
353
354
355VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
356{
357 pVCpu->cpum.s.Guest.ecx = ecx;
358 return VINF_SUCCESS;
359}
360
361
362VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
363{
364 pVCpu->cpum.s.Guest.edx = edx;
365 return VINF_SUCCESS;
366}
367
368
369VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
370{
371 pVCpu->cpum.s.Guest.esp = esp;
372 return VINF_SUCCESS;
373}
374
375
376VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
377{
378 pVCpu->cpum.s.Guest.ebp = ebp;
379 return VINF_SUCCESS;
380}
381
382
383VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
384{
385 pVCpu->cpum.s.Guest.esi = esi;
386 return VINF_SUCCESS;
387}
388
389
390VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
391{
392 pVCpu->cpum.s.Guest.edi = edi;
393 return VINF_SUCCESS;
394}
395
396
397VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
398{
399 pVCpu->cpum.s.Guest.ss.Sel = ss;
400 return VINF_SUCCESS;
401}
402
403
404VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
405{
406 pVCpu->cpum.s.Guest.cs.Sel = cs;
407 return VINF_SUCCESS;
408}
409
410
411VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
412{
413 pVCpu->cpum.s.Guest.ds.Sel = ds;
414 return VINF_SUCCESS;
415}
416
417
418VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
419{
420 pVCpu->cpum.s.Guest.es.Sel = es;
421 return VINF_SUCCESS;
422}
423
424
425VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
426{
427 pVCpu->cpum.s.Guest.fs.Sel = fs;
428 return VINF_SUCCESS;
429}
430
431
432VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
433{
434 pVCpu->cpum.s.Guest.gs.Sel = gs;
435 return VINF_SUCCESS;
436}
437
438
439VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
440{
441 pVCpu->cpum.s.Guest.msrEFER = val;
442 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_EFER;
443}
444
445
446VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit)
447{
448 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_IDTR);
449 if (pcbLimit)
450 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
451 return pVCpu->cpum.s.Guest.idtr.pIdt;
452}
453
454
455VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden)
456{
457 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_TR);
458 if (pHidden)
459 *pHidden = pVCpu->cpum.s.Guest.tr;
460 return pVCpu->cpum.s.Guest.tr.Sel;
461}
462
463
464VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu)
465{
466 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS);
467 return pVCpu->cpum.s.Guest.cs.Sel;
468}
469
470
471VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu)
472{
473 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DS);
474 return pVCpu->cpum.s.Guest.ds.Sel;
475}
476
477
478VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu)
479{
480 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ES);
481 return pVCpu->cpum.s.Guest.es.Sel;
482}
483
484
485VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu)
486{
487 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_FS);
488 return pVCpu->cpum.s.Guest.fs.Sel;
489}
490
491
492VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu)
493{
494 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GS);
495 return pVCpu->cpum.s.Guest.gs.Sel;
496}
497
498
499VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu)
500{
501 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SS);
502 return pVCpu->cpum.s.Guest.ss.Sel;
503}
504
505
506VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu)
507{
508 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
509 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
510 if ( !CPUMIsGuestInLongMode(pVCpu)
511 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
512 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.cs.u64Base;
513 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.cs.u64Base;
514}
515
516
517VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu)
518{
519 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
520 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
521 if ( !CPUMIsGuestInLongMode(pVCpu)
522 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
523 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.ss.u64Base;
524 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.ss.u64Base;
525}
526
527
528VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu)
529{
530 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
531 return pVCpu->cpum.s.Guest.ldtr.Sel;
532}
533
534
535VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
536{
537 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
538 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
539 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
540 return pVCpu->cpum.s.Guest.ldtr.Sel;
541}
542
543
544VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu)
545{
546 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
547 return pVCpu->cpum.s.Guest.cr0;
548}
549
550
551VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu)
552{
553 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
554 return pVCpu->cpum.s.Guest.cr2;
555}
556
557
558VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu)
559{
560 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
561 return pVCpu->cpum.s.Guest.cr3;
562}
563
564
565VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu)
566{
567 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
568 return pVCpu->cpum.s.Guest.cr4;
569}
570
571
572VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu)
573{
574 uint64_t u64;
575 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
576 if (RT_FAILURE(rc))
577 u64 = 0;
578 return u64;
579}
580
581
582VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR)
583{
584 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GDTR);
585 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
586}
587
588
589VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu)
590{
591 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
592 return pVCpu->cpum.s.Guest.eip;
593}
594
595
596VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu)
597{
598 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
599 return pVCpu->cpum.s.Guest.rip;
600}
601
602
603VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu)
604{
605 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RAX);
606 return pVCpu->cpum.s.Guest.eax;
607}
608
609
610VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu)
611{
612 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBX);
613 return pVCpu->cpum.s.Guest.ebx;
614}
615
616
617VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu)
618{
619 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RCX);
620 return pVCpu->cpum.s.Guest.ecx;
621}
622
623
624VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu)
625{
626 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDX);
627 return pVCpu->cpum.s.Guest.edx;
628}
629
630
631VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu)
632{
633 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSI);
634 return pVCpu->cpum.s.Guest.esi;
635}
636
637
638VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu)
639{
640 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDI);
641 return pVCpu->cpum.s.Guest.edi;
642}
643
644
645VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu)
646{
647 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP);
648 return pVCpu->cpum.s.Guest.esp;
649}
650
651
652VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu)
653{
654 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBP);
655 return pVCpu->cpum.s.Guest.ebp;
656}
657
658
659VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu)
660{
661 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RFLAGS);
662 return pVCpu->cpum.s.Guest.eflags.u32;
663}
664
665
666VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue)
667{
668 switch (iReg)
669 {
670 case DISCREG_CR0:
671 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
672 *pValue = pVCpu->cpum.s.Guest.cr0;
673 break;
674
675 case DISCREG_CR2:
676 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
677 *pValue = pVCpu->cpum.s.Guest.cr2;
678 break;
679
680 case DISCREG_CR3:
681 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
682 *pValue = pVCpu->cpum.s.Guest.cr3;
683 break;
684
685 case DISCREG_CR4:
686 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
687 *pValue = pVCpu->cpum.s.Guest.cr4;
688 break;
689
690 case DISCREG_CR8:
691 {
692 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
693 uint8_t u8Tpr;
694 int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
695 if (RT_FAILURE(rc))
696 {
697 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
698 *pValue = 0;
699 return rc;
700 }
701 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0 */
702 break;
703 }
704
705 default:
706 return VERR_INVALID_PARAMETER;
707 }
708 return VINF_SUCCESS;
709}
710
711
712VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu)
713{
714 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
715 return pVCpu->cpum.s.Guest.dr[0];
716}
717
718
719VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu)
720{
721 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
722 return pVCpu->cpum.s.Guest.dr[1];
723}
724
725
726VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu)
727{
728 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
729 return pVCpu->cpum.s.Guest.dr[2];
730}
731
732
733VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu)
734{
735 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
736 return pVCpu->cpum.s.Guest.dr[3];
737}
738
739
740VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu)
741{
742 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR6);
743 return pVCpu->cpum.s.Guest.dr[6];
744}
745
746
747VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu)
748{
749 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
750 return pVCpu->cpum.s.Guest.dr[7];
751}
752
753
754VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
755{
756 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR_MASK);
757 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
758 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
759 if (iReg == 4 || iReg == 5)
760 iReg += 2;
761 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
762 return VINF_SUCCESS;
763}
764
765
766VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu)
767{
768 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
769 return pVCpu->cpum.s.Guest.msrEFER;
770}
771
772
773/**
774 * Looks up a CPUID leaf in the CPUID leaf array, no subleaf.
775 *
776 * @returns Pointer to the leaf if found, NULL if not.
777 *
778 * @param pVM The cross context VM structure.
779 * @param uLeaf The leaf to get.
780 */
781PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf)
782{
783 unsigned iEnd = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
784 if (iEnd)
785 {
786 unsigned iStart = 0;
787 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.CTX_SUFF(paCpuIdLeaves);
788 for (;;)
789 {
790 unsigned i = iStart + (iEnd - iStart) / 2U;
791 if (uLeaf < paLeaves[i].uLeaf)
792 {
793 if (i <= iStart)
794 return NULL;
795 iEnd = i;
796 }
797 else if (uLeaf > paLeaves[i].uLeaf)
798 {
799 i += 1;
800 if (i >= iEnd)
801 return NULL;
802 iStart = i;
803 }
804 else
805 {
806 if (RT_LIKELY(paLeaves[i].fSubLeafMask == 0 && paLeaves[i].uSubLeaf == 0))
807 return &paLeaves[i];
808
809 /* This shouldn't normally happen. But in case the it does due
810 to user configuration overrids or something, just return the
811 first sub-leaf. */
812 AssertMsgFailed(("uLeaf=%#x fSubLeafMask=%#x uSubLeaf=%#x\n",
813 uLeaf, paLeaves[i].fSubLeafMask, paLeaves[i].uSubLeaf));
814 while ( paLeaves[i].uSubLeaf != 0
815 && i > 0
816 && uLeaf == paLeaves[i - 1].uLeaf)
817 i--;
818 return &paLeaves[i];
819 }
820 }
821 }
822
823 return NULL;
824}
825
826
827/**
828 * Looks up a CPUID leaf in the CPUID leaf array.
829 *
830 * @returns Pointer to the leaf if found, NULL if not.
831 *
832 * @param pVM The cross context VM structure.
833 * @param uLeaf The leaf to get.
834 * @param uSubLeaf The subleaf, if applicable. Just pass 0 if it
835 * isn't.
836 * @param pfExactSubLeafHit Whether we've got an exact subleaf hit or not.
837 */
838PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit)
839{
840 unsigned iEnd = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
841 if (iEnd)
842 {
843 unsigned iStart = 0;
844 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.CTX_SUFF(paCpuIdLeaves);
845 for (;;)
846 {
847 unsigned i = iStart + (iEnd - iStart) / 2U;
848 if (uLeaf < paLeaves[i].uLeaf)
849 {
850 if (i <= iStart)
851 return NULL;
852 iEnd = i;
853 }
854 else if (uLeaf > paLeaves[i].uLeaf)
855 {
856 i += 1;
857 if (i >= iEnd)
858 return NULL;
859 iStart = i;
860 }
861 else
862 {
863 uSubLeaf &= paLeaves[i].fSubLeafMask;
864 if (uSubLeaf == paLeaves[i].uSubLeaf)
865 *pfExactSubLeafHit = true;
866 else
867 {
868 /* Find the right subleaf. We return the last one before
869 uSubLeaf if we don't find an exact match. */
870 if (uSubLeaf < paLeaves[i].uSubLeaf)
871 while ( i > 0
872 && uLeaf == paLeaves[i - 1].uLeaf
873 && uSubLeaf <= paLeaves[i - 1].uSubLeaf)
874 i--;
875 else
876 while ( i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves
877 && uLeaf == paLeaves[i + 1].uLeaf
878 && uSubLeaf >= paLeaves[i + 1].uSubLeaf)
879 i++;
880 *pfExactSubLeafHit = uSubLeaf == paLeaves[i].uSubLeaf;
881 }
882 return &paLeaves[i];
883 }
884 }
885 }
886
887 *pfExactSubLeafHit = false;
888 return NULL;
889}
890
891
892/**
893 * Gets a CPUID leaf.
894 *
895 * @param pVCpu The cross context virtual CPU structure.
896 * @param uLeaf The CPUID leaf to get.
897 * @param uSubLeaf The CPUID sub-leaf to get, if applicable.
898 * @param pEax Where to store the EAX value.
899 * @param pEbx Where to store the EBX value.
900 * @param pEcx Where to store the ECX value.
901 * @param pEdx Where to store the EDX value.
902 */
903VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t uLeaf, uint32_t uSubLeaf,
904 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
905{
906 bool fExactSubLeafHit;
907 PVM pVM = pVCpu->CTX_SUFF(pVM);
908 PCCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, uSubLeaf, &fExactSubLeafHit);
909 if (pLeaf)
910 {
911 AssertMsg(pLeaf->uLeaf == uLeaf, ("%#x %#x\n", pLeaf->uLeaf, uLeaf));
912 if (fExactSubLeafHit)
913 {
914 *pEax = pLeaf->uEax;
915 *pEbx = pLeaf->uEbx;
916 *pEcx = pLeaf->uEcx;
917 *pEdx = pLeaf->uEdx;
918
919 /*
920 * Deal with CPU specific information.
921 */
922 if (pLeaf->fFlags & ( CPUMCPUIDLEAF_F_CONTAINS_APIC_ID
923 | CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
924 | CPUMCPUIDLEAF_F_CONTAINS_APIC ))
925 {
926 if (uLeaf == 1)
927 {
928 /* EBX: Bits 31-24: Initial APIC ID. */
929 Assert(pVCpu->idCpu <= 255);
930 AssertMsg((pLeaf->uEbx >> 24) == 0, ("%#x\n", pLeaf->uEbx)); /* raw-mode assumption */
931 *pEbx = (pLeaf->uEbx & UINT32_C(0x00ffffff)) | (pVCpu->idCpu << 24);
932
933 /* EDX: Bit 9: AND with APICBASE.EN. */
934 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
935 *pEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
936
937 /* ECX: Bit 27: CR4.OSXSAVE mirror. */
938 *pEcx = (pLeaf->uEcx & ~X86_CPUID_FEATURE_ECX_OSXSAVE)
939 | (pVCpu->cpum.s.Guest.cr4 & X86_CR4_OSXSAVE ? X86_CPUID_FEATURE_ECX_OSXSAVE : 0);
940 }
941 else if (uLeaf == 0xb)
942 {
943 /* EDX: Initial extended APIC ID. */
944 AssertMsg(pLeaf->uEdx == 0, ("%#x\n", pLeaf->uEdx)); /* raw-mode assumption */
945 *pEdx = pVCpu->idCpu;
946 Assert(!(pLeaf->fFlags & ~(CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)));
947 }
948 else if (uLeaf == UINT32_C(0x8000001e))
949 {
950 /* EAX: Initial extended APIC ID. */
951 AssertMsg(pLeaf->uEax == 0, ("%#x\n", pLeaf->uEax)); /* raw-mode assumption */
952 *pEax = pVCpu->idCpu;
953 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID));
954 }
955 else if (uLeaf == UINT32_C(0x80000001))
956 {
957 /* EDX: Bit 9: AND with APICBASE.EN. */
958 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible)
959 *pEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
960 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC));
961 }
962 else
963 AssertMsgFailed(("uLeaf=%#x\n", uLeaf));
964 }
965 }
966 /*
967 * Out of range sub-leaves aren't quite as easy and pretty as we emulate
968 * them here, but we do the best we can here...
969 */
970 else
971 {
972 *pEax = *pEbx = *pEcx = *pEdx = 0;
973 if (pLeaf->fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
974 {
975 *pEcx = uSubLeaf & 0xff;
976 *pEdx = pVCpu->idCpu;
977 }
978 }
979 }
980 else
981 {
982 /*
983 * Different CPUs have different ways of dealing with unknown CPUID leaves.
984 */
985 switch (pVM->cpum.s.GuestInfo.enmUnknownCpuIdMethod)
986 {
987 default:
988 AssertFailed();
989 RT_FALL_THRU();
990 case CPUMUNKNOWNCPUID_DEFAULTS:
991 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: /* ASSUME this is executed */
992 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: /** @todo Implement CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX */
993 *pEax = pVM->cpum.s.GuestInfo.DefCpuId.uEax;
994 *pEbx = pVM->cpum.s.GuestInfo.DefCpuId.uEbx;
995 *pEcx = pVM->cpum.s.GuestInfo.DefCpuId.uEcx;
996 *pEdx = pVM->cpum.s.GuestInfo.DefCpuId.uEdx;
997 break;
998 case CPUMUNKNOWNCPUID_PASSTHRU:
999 *pEax = uLeaf;
1000 *pEbx = 0;
1001 *pEcx = uSubLeaf;
1002 *pEdx = 0;
1003 break;
1004 }
1005 }
1006 Log2(("CPUMGetGuestCpuId: uLeaf=%#010x/%#010x %RX32 %RX32 %RX32 %RX32\n", uLeaf, uSubLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1007}
1008
1009
1010/**
1011 * Sets the visibility of the X86_CPUID_FEATURE_EDX_APIC and
1012 * X86_CPUID_AMD_FEATURE_EDX_APIC CPUID bits.
1013 *
1014 * @returns Previous value.
1015 * @param pVCpu The cross context virtual CPU structure to make the
1016 * change on. Usually the calling EMT.
1017 * @param fVisible Whether to make it visible (true) or hide it (false).
1018 *
1019 * @remarks This is "VMMDECL" so that it still links with
1020 * the old APIC code which is in VBoxDD2 and not in
1021 * the VMM module.
1022 */
1023VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible)
1024{
1025 bool fOld = pVCpu->cpum.s.fCpuIdApicFeatureVisible;
1026 pVCpu->cpum.s.fCpuIdApicFeatureVisible = fVisible;
1027 return fOld;
1028}
1029
1030
1031/**
1032 * Gets the host CPU vendor.
1033 *
1034 * @returns CPU vendor.
1035 * @param pVM The cross context VM structure.
1036 */
1037VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1038{
1039 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor;
1040}
1041
1042
1043/**
1044 * Gets the host CPU microarchitecture.
1045 *
1046 * @returns CPU microarchitecture.
1047 * @param pVM The cross context VM structure.
1048 */
1049VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM)
1050{
1051 return pVM->cpum.s.HostFeatures.enmMicroarch;
1052}
1053
1054
1055/**
1056 * Gets the guest CPU vendor.
1057 *
1058 * @returns CPU vendor.
1059 * @param pVM The cross context VM structure.
1060 */
1061VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1062{
1063 return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor;
1064}
1065
1066
1067/**
1068 * Gets the guest CPU microarchitecture.
1069 *
1070 * @returns CPU microarchitecture.
1071 * @param pVM The cross context VM structure.
1072 */
1073VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM)
1074{
1075 return pVM->cpum.s.GuestFeatures.enmMicroarch;
1076}
1077
1078
1079VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0)
1080{
1081 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1082 return CPUMRecalcHyperDRx(pVCpu, 0);
1083}
1084
1085
1086VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1)
1087{
1088 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1089 return CPUMRecalcHyperDRx(pVCpu, 1);
1090}
1091
1092
1093VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2)
1094{
1095 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1096 return CPUMRecalcHyperDRx(pVCpu, 2);
1097}
1098
1099
1100VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3)
1101{
1102 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1103 return CPUMRecalcHyperDRx(pVCpu, 3);
1104}
1105
1106
1107VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1108{
1109 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1110 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR6;
1111 return VINF_SUCCESS; /* No need to recalc. */
1112}
1113
1114
1115VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7)
1116{
1117 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1118 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR7;
1119 return CPUMRecalcHyperDRx(pVCpu, 7);
1120}
1121
1122
1123VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value)
1124{
1125 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1126 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1127 if (iReg == 4 || iReg == 5)
1128 iReg += 2;
1129 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1130 return CPUMRecalcHyperDRx(pVCpu, iReg);
1131}
1132
1133
1134/**
1135 * Recalculates the hypervisor DRx register values based on current guest
1136 * registers and DBGF breakpoints, updating changed registers depending on the
1137 * context.
1138 *
1139 * This is called whenever a guest DRx register is modified (any context) and
1140 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
1141 *
1142 * In raw-mode context this function will reload any (hyper) DRx registers which
1143 * comes out with a different value. It may also have to save the host debug
1144 * registers if that haven't been done already. In this context though, we'll
1145 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
1146 * are only important when breakpoints are actually enabled.
1147 *
1148 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
1149 * reloaded by the HM code if it changes. Further more, we will only use the
1150 * combined register set when the VBox debugger is actually using hardware BPs,
1151 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
1152 * concern us here).
1153 *
1154 * In ring-3 we won't be loading anything, so well calculate hypervisor values
1155 * all the time.
1156 *
1157 * @returns VINF_SUCCESS.
1158 * @param pVCpu The cross context virtual CPU structure.
1159 * @param iGstReg The guest debug register number that was modified.
1160 * UINT8_MAX if not guest register.
1161 */
1162VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg)
1163{
1164 PVM pVM = pVCpu->CTX_SUFF(pVM);
1165#ifndef IN_RING0
1166 RT_NOREF_PV(iGstReg);
1167#endif
1168
1169 /*
1170 * Compare the DR7s first.
1171 *
1172 * We only care about the enabled flags. GD is virtualized when we
1173 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
1174 * always have the LE and GE bits set, so no need to check and disable
1175 * stuff if they're cleared like we have to for the guest DR7.
1176 */
1177 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1178 /** @todo This isn't correct. BPs work without setting LE and GE under AMD-V. They are also documented as unsupported by P6+. */
1179 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
1180 uGstDr7 = 0;
1181 else if (!(uGstDr7 & X86_DR7_LE))
1182 uGstDr7 &= ~X86_DR7_LE_ALL;
1183 else if (!(uGstDr7 & X86_DR7_GE))
1184 uGstDr7 &= ~X86_DR7_GE_ALL;
1185
1186 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1187 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1188 {
1189 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1190
1191 /*
1192 * Ok, something is enabled. Recalc each of the breakpoints, taking
1193 * the VM debugger ones of the guest ones. In raw-mode context we will
1194 * not allow breakpoints with values inside the hypervisor area.
1195 */
1196 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
1197
1198 /* bp 0 */
1199 RTGCUINTREG uNewDr0;
1200 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1201 {
1202 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1203 uNewDr0 = DBGFBpGetDR0(pVM);
1204 }
1205 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1206 {
1207 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1208 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1209 }
1210 else
1211 uNewDr0 = 0;
1212
1213 /* bp 1 */
1214 RTGCUINTREG uNewDr1;
1215 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1216 {
1217 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1218 uNewDr1 = DBGFBpGetDR1(pVM);
1219 }
1220 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1221 {
1222 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1223 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1224 }
1225 else
1226 uNewDr1 = 0;
1227
1228 /* bp 2 */
1229 RTGCUINTREG uNewDr2;
1230 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1231 {
1232 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1233 uNewDr2 = DBGFBpGetDR2(pVM);
1234 }
1235 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1236 {
1237 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1238 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1239 }
1240 else
1241 uNewDr2 = 0;
1242
1243 /* bp 3 */
1244 RTGCUINTREG uNewDr3;
1245 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1246 {
1247 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1248 uNewDr3 = DBGFBpGetDR3(pVM);
1249 }
1250 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1251 {
1252 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1253 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1254 }
1255 else
1256 uNewDr3 = 0;
1257
1258 /*
1259 * Apply the updates.
1260 */
1261 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
1262 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1263 CPUMSetHyperDR3(pVCpu, uNewDr3);
1264 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1265 CPUMSetHyperDR2(pVCpu, uNewDr2);
1266 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1267 CPUMSetHyperDR1(pVCpu, uNewDr1);
1268 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1269 CPUMSetHyperDR0(pVCpu, uNewDr0);
1270 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1271 CPUMSetHyperDR7(pVCpu, uNewDr7);
1272 }
1273#ifdef IN_RING0
1274 else if (CPUMIsGuestDebugStateActive(pVCpu))
1275 {
1276 /*
1277 * Reload the register that was modified. Normally this won't happen
1278 * as we won't intercept DRx writes when not having the hyper debug
1279 * state loaded, but in case we do for some reason we'll simply deal
1280 * with it.
1281 */
1282 switch (iGstReg)
1283 {
1284 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
1285 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
1286 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
1287 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
1288 default:
1289 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
1290 }
1291 }
1292#endif
1293 else
1294 {
1295 /*
1296 * No active debug state any more. In raw-mode this means we have to
1297 * make sure DR7 has everything disabled now, if we armed it already.
1298 * In ring-0 we might end up here when just single stepping.
1299 */
1300#ifdef IN_RING0
1301 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
1302 {
1303 if (pVCpu->cpum.s.Hyper.dr[0])
1304 ASMSetDR0(0);
1305 if (pVCpu->cpum.s.Hyper.dr[1])
1306 ASMSetDR1(0);
1307 if (pVCpu->cpum.s.Hyper.dr[2])
1308 ASMSetDR2(0);
1309 if (pVCpu->cpum.s.Hyper.dr[3])
1310 ASMSetDR3(0);
1311 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
1312 }
1313#endif
1314 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
1315
1316 /* Clear all the registers. */
1317 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
1318 pVCpu->cpum.s.Hyper.dr[3] = 0;
1319 pVCpu->cpum.s.Hyper.dr[2] = 0;
1320 pVCpu->cpum.s.Hyper.dr[1] = 0;
1321 pVCpu->cpum.s.Hyper.dr[0] = 0;
1322
1323 }
1324 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1325 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1326 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1327 pVCpu->cpum.s.Hyper.dr[7]));
1328
1329 return VINF_SUCCESS;
1330}
1331
1332
1333/**
1334 * Set the guest XCR0 register.
1335 *
1336 * Will load additional state if the FPU state is already loaded (in ring-0 &
1337 * raw-mode context).
1338 *
1339 * @returns VINF_SUCCESS on success, VERR_CPUM_RAISE_GP_0 on invalid input
1340 * value.
1341 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1342 * @param uNewValue The new value.
1343 * @thread EMT(pVCpu)
1344 */
1345VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue)
1346{
1347 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_XCRx);
1348 if ( (uNewValue & ~pVCpu->CTX_SUFF(pVM)->cpum.s.fXStateGuestMask) == 0
1349 /* The X87 bit cannot be cleared. */
1350 && (uNewValue & XSAVE_C_X87)
1351 /* AVX requires SSE. */
1352 && (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM
1353 /* AVX-512 requires YMM, SSE and all of its three components to be enabled. */
1354 && ( (uNewValue & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1355 || (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1356 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI) )
1357 )
1358 {
1359 pVCpu->cpum.s.Guest.aXcr[0] = uNewValue;
1360
1361 /* If more state components are enabled, we need to take care to load
1362 them if the FPU/SSE state is already loaded. May otherwise leak
1363 host state to the guest. */
1364 uint64_t fNewComponents = ~pVCpu->cpum.s.Guest.fXStateMask & uNewValue;
1365 if (fNewComponents)
1366 {
1367#ifdef IN_RING0
1368 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
1369 {
1370 if (pVCpu->cpum.s.Guest.fXStateMask != 0)
1371 /* Adding more components. */
1372 ASMXRstor(pVCpu->cpum.s.Guest.CTX_SUFF(pXState), fNewComponents);
1373 else
1374 {
1375 /* We're switching from FXSAVE/FXRSTOR to XSAVE/XRSTOR. */
1376 pVCpu->cpum.s.Guest.fXStateMask |= XSAVE_C_X87 | XSAVE_C_SSE;
1377 if (uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE))
1378 ASMXRstor(pVCpu->cpum.s.Guest.CTX_SUFF(pXState), uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE));
1379 }
1380 }
1381#endif
1382 pVCpu->cpum.s.Guest.fXStateMask |= uNewValue;
1383 }
1384 return VINF_SUCCESS;
1385 }
1386 return VERR_CPUM_RAISE_GP_0;
1387}
1388
1389
1390/**
1391 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1392 *
1393 * @returns true if in real mode, otherwise false.
1394 * @param pVCpu The cross context virtual CPU structure.
1395 */
1396VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu)
1397{
1398 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1399 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
1400}
1401
1402
1403/**
1404 * Tests if the guest has the Page Size Extension enabled (PSE).
1405 *
1406 * @returns true if in real mode, otherwise false.
1407 * @param pVCpu The cross context virtual CPU structure.
1408 */
1409VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu)
1410{
1411 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
1412 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
1413 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
1414}
1415
1416
1417/**
1418 * Tests if the guest has the paging enabled (PG).
1419 *
1420 * @returns true if in real mode, otherwise false.
1421 * @param pVCpu The cross context virtual CPU structure.
1422 */
1423VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu)
1424{
1425 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1426 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
1427}
1428
1429
1430/**
1431 * Tests if the guest has the paging enabled (PG).
1432 *
1433 * @returns true if in real mode, otherwise false.
1434 * @param pVCpu The cross context virtual CPU structure.
1435 */
1436VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu)
1437{
1438 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1439 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
1440}
1441
1442
1443/**
1444 * Tests if the guest is running in real mode or not.
1445 *
1446 * @returns true if in real mode, otherwise false.
1447 * @param pVCpu The cross context virtual CPU structure.
1448 */
1449VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu)
1450{
1451 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1452 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1453}
1454
1455
1456/**
1457 * Tests if the guest is running in real or virtual 8086 mode.
1458 *
1459 * @returns @c true if it is, @c false if not.
1460 * @param pVCpu The cross context virtual CPU structure.
1461 */
1462VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu)
1463{
1464 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS);
1465 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1466 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
1467}
1468
1469
1470/**
1471 * Tests if the guest is running in protected or not.
1472 *
1473 * @returns true if in protected mode, otherwise false.
1474 * @param pVCpu The cross context virtual CPU structure.
1475 */
1476VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu)
1477{
1478 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1479 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1480}
1481
1482
1483/**
1484 * Tests if the guest is running in paged protected or not.
1485 *
1486 * @returns true if in paged protected mode, otherwise false.
1487 * @param pVCpu The cross context virtual CPU structure.
1488 */
1489VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu)
1490{
1491 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1492 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1493}
1494
1495
1496/**
1497 * Tests if the guest is running in long mode or not.
1498 *
1499 * @returns true if in long mode, otherwise false.
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu)
1503{
1504 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1505 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1506}
1507
1508
1509/**
1510 * Tests if the guest is running in PAE mode or not.
1511 *
1512 * @returns true if in PAE mode, otherwise false.
1513 * @param pVCpu The cross context virtual CPU structure.
1514 */
1515VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu)
1516{
1517 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1518 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1519 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1520 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
1521 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
1522 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
1523}
1524
1525
1526/**
1527 * Tests if the guest is running in 64 bits mode or not.
1528 *
1529 * @returns true if in 64 bits protected mode, otherwise false.
1530 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1531 */
1532VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
1533{
1534 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
1535 if (!CPUMIsGuestInLongMode(pVCpu))
1536 return false;
1537 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1538 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
1539}
1540
1541
1542/**
1543 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
1544 * registers.
1545 *
1546 * @returns true if in 64 bits protected mode, otherwise false.
1547 * @param pCtx Pointer to the current guest CPU context.
1548 */
1549VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
1550{
1551 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
1552}
1553
1554
1555/**
1556 * Sets the specified changed flags (CPUM_CHANGED_*).
1557 *
1558 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1559 * @param fChangedAdd The changed flags to add.
1560 */
1561VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd)
1562{
1563 pVCpu->cpum.s.fChanged |= fChangedAdd;
1564}
1565
1566
1567/**
1568 * Checks if the CPU supports the XSAVE and XRSTOR instruction.
1569 *
1570 * @returns true if supported.
1571 * @returns false if not supported.
1572 * @param pVM The cross context VM structure.
1573 */
1574VMMDECL(bool) CPUMSupportsXSave(PVM pVM)
1575{
1576 return pVM->cpum.s.HostFeatures.fXSaveRstor != 0;
1577}
1578
1579
1580/**
1581 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1582 * @returns true if used.
1583 * @returns false if not used.
1584 * @param pVM The cross context VM structure.
1585 */
1586VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1587{
1588 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
1589}
1590
1591
1592/**
1593 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1594 * @returns true if used.
1595 * @returns false if not used.
1596 * @param pVM The cross context VM structure.
1597 */
1598VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1599{
1600 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
1601}
1602
1603
1604/**
1605 * Checks if we activated the FPU/XMM state of the guest OS.
1606 *
1607 * Obsolete: This differs from CPUMIsGuestFPUStateLoaded() in that it refers to
1608 * the next time we'll be executing guest code, so it may return true for
1609 * 64-on-32 when we still haven't actually loaded the FPU status, just scheduled
1610 * it to be loaded the next time we go thru the world switcher
1611 * (CPUM_SYNC_FPU_STATE).
1612 *
1613 * @returns true / false.
1614 * @param pVCpu The cross context virtual CPU structure.
1615 */
1616VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
1617{
1618 bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1619 AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
1620 return fRet;
1621}
1622
1623
1624/**
1625 * Checks if we've really loaded the FPU/XMM state of the guest OS.
1626 *
1627 * @returns true / false.
1628 * @param pVCpu The cross context virtual CPU structure.
1629 */
1630VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu)
1631{
1632 bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1633 AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
1634 return fRet;
1635}
1636
1637
1638/**
1639 * Checks if we saved the FPU/XMM state of the host OS.
1640 *
1641 * @returns true / false.
1642 * @param pVCpu The cross context virtual CPU structure.
1643 */
1644VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu)
1645{
1646 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST);
1647}
1648
1649
1650/**
1651 * Checks if the guest debug state is active.
1652 *
1653 * @returns boolean
1654 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1655 */
1656VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
1657{
1658 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
1659}
1660
1661
1662/**
1663 * Checks if the hyper debug state is active.
1664 *
1665 * @returns boolean
1666 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1667 */
1668VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
1669{
1670 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
1671}
1672
1673
1674/**
1675 * Mark the guest's debug state as inactive.
1676 *
1677 * @returns boolean
1678 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1679 * @todo This API doesn't make sense any more.
1680 */
1681VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
1682{
1683 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
1684 NOREF(pVCpu);
1685}
1686
1687
1688/**
1689 * Get the current privilege level of the guest.
1690 *
1691 * @returns CPL
1692 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1693 */
1694VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
1695{
1696 /*
1697 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
1698 *
1699 * Note! We used to check CS.DPL here, assuming it was always equal to
1700 * CPL even if a conforming segment was loaded. But this turned out to
1701 * only apply to older AMD-V. With VT-x we had an ACP2 regression
1702 * during install after a far call to ring 2 with VT-x. Then on newer
1703 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
1704 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
1705 *
1706 * So, forget CS.DPL, always use SS.DPL.
1707 *
1708 * Note! The SS RPL is always equal to the CPL, while the CS RPL
1709 * isn't necessarily equal if the segment is conforming.
1710 * See section 4.11.1 in the AMD manual.
1711 *
1712 * Update: Where the heck does it say CS.RPL can differ from CPL other than
1713 * right after real->prot mode switch and when in V8086 mode? That
1714 * section says the RPL specified in a direct transfere (call, jmp,
1715 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
1716 * it would be impossible for an exception handle or the iret
1717 * instruction to figure out whether SS:ESP are part of the frame
1718 * or not. VBox or qemu bug must've lead to this misconception.
1719 *
1720 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
1721 * selector into SS with an RPL other than the CPL when CPL != 3 and
1722 * we're in 64-bit mode. The intel dev box doesn't allow this, on
1723 * RPL = CPL. Weird.
1724 */
1725 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
1726 uint32_t uCpl;
1727 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1728 {
1729 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1730 {
1731 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
1732 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
1733 else
1734 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
1735 }
1736 else
1737 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
1738 }
1739 else
1740 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
1741 return uCpl;
1742}
1743
1744
1745/**
1746 * Gets the current guest CPU mode.
1747 *
1748 * If paging mode is what you need, check out PGMGetGuestMode().
1749 *
1750 * @returns The CPU mode.
1751 * @param pVCpu The cross context virtual CPU structure.
1752 */
1753VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
1754{
1755 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1756 CPUMMODE enmMode;
1757 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1758 enmMode = CPUMMODE_REAL;
1759 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1760 enmMode = CPUMMODE_PROTECTED;
1761 else
1762 enmMode = CPUMMODE_LONG;
1763
1764 return enmMode;
1765}
1766
1767
1768/**
1769 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
1770 *
1771 * @returns 16, 32 or 64.
1772 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1773 */
1774VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
1775{
1776 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1777
1778 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1779 return 16;
1780
1781 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1782 {
1783 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1784 return 16;
1785 }
1786
1787 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1788 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1789 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1790 return 64;
1791
1792 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1793 return 32;
1794
1795 return 16;
1796}
1797
1798
1799VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
1800{
1801 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1802
1803 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1804 return DISCPUMODE_16BIT;
1805
1806 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1807 {
1808 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1809 return DISCPUMODE_16BIT;
1810 }
1811
1812 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1813 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1814 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1815 return DISCPUMODE_64BIT;
1816
1817 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1818 return DISCPUMODE_32BIT;
1819
1820 return DISCPUMODE_16BIT;
1821}
1822
1823
1824/**
1825 * Gets the guest MXCSR_MASK value.
1826 *
1827 * This does not access the x87 state, but the value we determined at VM
1828 * initialization.
1829 *
1830 * @returns MXCSR mask.
1831 * @param pVM The cross context VM structure.
1832 */
1833VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM)
1834{
1835 return pVM->cpum.s.GuestInfo.fMxCsrMask;
1836}
1837
1838
1839/**
1840 * Returns whether the guest has physical interrupts enabled.
1841 *
1842 * @returns @c true if interrupts are enabled, @c false otherwise.
1843 * @param pVCpu The cross context virtual CPU structure.
1844 *
1845 * @remarks Warning! This function does -not- take into account the global-interrupt
1846 * flag (GIF).
1847 */
1848VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu)
1849{
1850 if (!CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest))
1851 {
1852 uint32_t const fEFlags = pVCpu->cpum.s.Guest.eflags.u;
1853 return RT_BOOL(fEFlags & X86_EFL_IF);
1854 }
1855
1856 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
1857 return CPUMIsGuestVmxPhysIntrEnabled(&pVCpu->cpum.s.Guest);
1858
1859 Assert(CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest));
1860 return CPUMIsGuestSvmPhysIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
1861}
1862
1863
1864/**
1865 * Returns whether the nested-guest has virtual interrupts enabled.
1866 *
1867 * @returns @c true if interrupts are enabled, @c false otherwise.
1868 * @param pVCpu The cross context virtual CPU structure.
1869 *
1870 * @remarks Warning! This function does -not- take into account the global-interrupt
1871 * flag (GIF).
1872 */
1873VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu)
1874{
1875 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1876 Assert(CPUMIsGuestInNestedHwvirtMode(pCtx));
1877
1878 if (CPUMIsGuestInVmxNonRootMode(pCtx))
1879 return CPUMIsGuestVmxVirtIntrEnabled(pCtx);
1880
1881 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1882 return CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
1883}
1884
1885
1886/**
1887 * Calculates the interruptiblity of the guest.
1888 *
1889 * @returns Interruptibility level.
1890 * @param pVCpu The cross context virtual CPU structure.
1891 */
1892VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu)
1893{
1894#if 1
1895 /* Global-interrupt flag blocks pretty much everything we care about here. */
1896 if (CPUMGetGuestGif(&pVCpu->cpum.s.Guest))
1897 {
1898 /*
1899 * Physical interrupts are primarily blocked using EFLAGS. However, we cannot access
1900 * it directly here. If and how EFLAGS are used depends on the context (nested-guest
1901 * or raw-mode). Hence we use the function below which handles the details.
1902 */
1903 if ( CPUMIsGuestPhysIntrEnabled(pVCpu)
1904 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
1905 {
1906 if ( !CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest)
1907 || CPUMIsGuestVirtIntrEnabled(pVCpu))
1908 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1909
1910 /* Physical interrupts are enabled, but nested-guest virtual interrupts are disabled. */
1911 return CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED;
1912 }
1913
1914 /*
1915 * Blocking the delivery of NMIs during an interrupt shadow is CPU implementation
1916 * specific. Therefore, in practice, we can't deliver an NMI in an interrupt shadow.
1917 * However, there is some uncertainity regarding the converse, i.e. whether
1918 * NMI-blocking until IRET blocks delivery of physical interrupts.
1919 *
1920 * See Intel spec. 25.4.1 "Event Blocking".
1921 */
1922 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1923 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1924
1925 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1926 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1927
1928 return CPUMINTERRUPTIBILITY_INT_DISABLED;
1929 }
1930 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1931#else
1932 if (pVCpu->cpum.s.Guest.rflags.Bits.u1IF)
1933 {
1934 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
1935 {
1936 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
1937 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1938
1939 /** @todo does blocking NMIs mean interrupts are also inhibited? */
1940 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1941 {
1942 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1943 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1944 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1945 }
1946 AssertFailed();
1947 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1948 }
1949 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1950 }
1951 else
1952 {
1953 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
1954 {
1955 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1956 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1957 return CPUMINTERRUPTIBILITY_INT_DISABLED;
1958 }
1959 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1960 }
1961#endif
1962}
1963
1964
1965/**
1966 * Gets whether the guest (or nested-guest) is currently blocking delivery of NMIs.
1967 *
1968 * @returns @c true if NMIs are blocked, @c false otherwise.
1969 * @param pVCpu The cross context virtual CPU structure.
1970 */
1971VMM_INT_DECL(bool) CPUMIsGuestNmiBlocking(PCVMCPU pVCpu)
1972{
1973 /*
1974 * Return the state of guest-NMI blocking in any of the following cases:
1975 * - We're not executing a nested-guest.
1976 * - We're executing an SVM nested-guest[1].
1977 * - We're executing a VMX nested-guest without virtual-NMIs enabled.
1978 *
1979 * [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
1980 * SVM hypervisors must track NMI blocking themselves by intercepting
1981 * the IRET instruction after injection of an NMI.
1982 */
1983 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1984 if ( !CPUMIsGuestInNestedHwvirtMode(pCtx)
1985 || CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1986 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1987 return VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1988
1989 /*
1990 * Return the state of virtual-NMI blocking, if we are executing a
1991 * VMX nested-guest with virtual-NMIs enabled.
1992 */
1993 return CPUMIsGuestVmxVirtNmiBlocking(pCtx);
1994}
1995
1996
1997/**
1998 * Sets blocking delivery of NMIs to the guest.
1999 *
2000 * @param pVCpu The cross context virtual CPU structure.
2001 * @param fBlock Whether NMIs are blocked or not.
2002 */
2003VMM_INT_DECL(void) CPUMSetGuestNmiBlocking(PVMCPU pVCpu, bool fBlock)
2004{
2005 /*
2006 * Set the state of guest-NMI blocking in any of the following cases:
2007 * - We're not executing a nested-guest.
2008 * - We're executing an SVM nested-guest[1].
2009 * - We're executing a VMX nested-guest without virtual-NMIs enabled.
2010 *
2011 * [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
2012 * SVM hypervisors must track NMI blocking themselves by intercepting
2013 * the IRET instruction after injection of an NMI.
2014 */
2015 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2016 if ( !CPUMIsGuestInNestedHwvirtMode(pCtx)
2017 || CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
2018 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
2019 {
2020 if (fBlock)
2021 {
2022 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2023 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2024 }
2025 else
2026 {
2027 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2028 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2029 }
2030 return;
2031 }
2032
2033 /*
2034 * Set the state of virtual-NMI blocking, if we are executing a
2035 * VMX nested-guest with virtual-NMIs enabled.
2036 */
2037 return CPUMSetGuestVmxVirtNmiBlocking(pCtx, fBlock);
2038}
2039
2040
2041/**
2042 * Checks whether the SVM nested-guest has physical interrupts enabled.
2043 *
2044 * @returns true if interrupts are enabled, false otherwise.
2045 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2046 * @param pCtx The guest-CPU context.
2047 *
2048 * @remarks This does -not- take into account the global-interrupt flag.
2049 */
2050VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2051{
2052 /** @todo Optimization: Avoid this function call and use a pointer to the
2053 * relevant eflags instead (setup during VMRUN instruction emulation). */
2054 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2055
2056 X86EFLAGS fEFlags;
2057 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, pCtx))
2058 fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
2059 else
2060 fEFlags.u = pCtx->eflags.u;
2061
2062 return fEFlags.Bits.u1IF;
2063}
2064
2065
2066/**
2067 * Checks whether the SVM nested-guest is in a state to receive virtual (setup
2068 * for injection by VMRUN instruction) interrupts.
2069 *
2070 * @returns VBox status code.
2071 * @retval true if it's ready, false otherwise.
2072 *
2073 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2074 * @param pCtx The guest-CPU context.
2075 */
2076VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2077{
2078 RT_NOREF(pVCpu);
2079 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2080
2081 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
2082 PCSVMINTCTRL pVmcbIntCtrl = &pVmcbCtrl->IntCtrl;
2083 Assert(!pVmcbIntCtrl->n.u1VGifEnable); /* We don't support passing virtual-GIF feature to the guest yet. */
2084 if ( !pVmcbIntCtrl->n.u1IgnoreTPR
2085 && pVmcbIntCtrl->n.u4VIntrPrio <= pVmcbIntCtrl->n.u8VTPR)
2086 return false;
2087
2088 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2089}
2090
2091
2092/**
2093 * Gets the pending SVM nested-guest interruptvector.
2094 *
2095 * @returns The nested-guest interrupt to inject.
2096 * @param pCtx The guest-CPU context.
2097 */
2098VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx)
2099{
2100 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
2101 return pVmcbCtrl->IntCtrl.n.u8VIntrVector;
2102}
2103
2104
2105/**
2106 * Restores the host-state from the host-state save area as part of a \#VMEXIT.
2107 *
2108 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2109 * @param pCtx The guest-CPU context.
2110 */
2111VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx)
2112{
2113 /*
2114 * Reload the guest's "host state".
2115 */
2116 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2117 pCtx->es = pHostState->es;
2118 pCtx->cs = pHostState->cs;
2119 pCtx->ss = pHostState->ss;
2120 pCtx->ds = pHostState->ds;
2121 pCtx->gdtr = pHostState->gdtr;
2122 pCtx->idtr = pHostState->idtr;
2123 CPUMSetGuestEferMsrNoChecks(pVCpu, pCtx->msrEFER, pHostState->uEferMsr);
2124 CPUMSetGuestCR0(pVCpu, pHostState->uCr0 | X86_CR0_PE);
2125 pCtx->cr3 = pHostState->uCr3;
2126 CPUMSetGuestCR4(pVCpu, pHostState->uCr4);
2127 pCtx->rflags = pHostState->rflags;
2128 pCtx->rflags.Bits.u1VM = 0;
2129 pCtx->rip = pHostState->uRip;
2130 pCtx->rsp = pHostState->uRsp;
2131 pCtx->rax = pHostState->uRax;
2132 pCtx->dr[7] &= ~(X86_DR7_ENABLED_MASK | X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2133 pCtx->dr[7] |= X86_DR7_RA1_MASK;
2134 Assert(pCtx->ss.Attr.n.u2Dpl == 0);
2135
2136 /** @todo if RIP is not canonical or outside the CS segment limit, we need to
2137 * raise \#GP(0) in the guest. */
2138
2139 /** @todo check the loaded host-state for consistency. Figure out what
2140 * exactly this involves? */
2141}
2142
2143
2144/**
2145 * Saves the host-state to the host-state save area as part of a VMRUN.
2146 *
2147 * @param pCtx The guest-CPU context.
2148 * @param cbInstr The length of the VMRUN instruction in bytes.
2149 */
2150VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr)
2151{
2152 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2153 pHostState->es = pCtx->es;
2154 pHostState->cs = pCtx->cs;
2155 pHostState->ss = pCtx->ss;
2156 pHostState->ds = pCtx->ds;
2157 pHostState->gdtr = pCtx->gdtr;
2158 pHostState->idtr = pCtx->idtr;
2159 pHostState->uEferMsr = pCtx->msrEFER;
2160 pHostState->uCr0 = pCtx->cr0;
2161 pHostState->uCr3 = pCtx->cr3;
2162 pHostState->uCr4 = pCtx->cr4;
2163 pHostState->rflags = pCtx->rflags;
2164 pHostState->uRip = pCtx->rip + cbInstr;
2165 pHostState->uRsp = pCtx->rsp;
2166 pHostState->uRax = pCtx->rax;
2167}
2168
2169
2170/**
2171 * Applies the TSC offset of a nested-guest if any and returns the TSC value for the
2172 * nested-guest.
2173 *
2174 * @returns The TSC offset after applying any nested-guest TSC offset.
2175 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2176 * @param uTscValue The guest TSC.
2177 *
2178 * @sa CPUMRemoveNestedGuestTscOffset.
2179 */
2180VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2181{
2182 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2183 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2184 {
2185 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2186 Assert(pVmcs);
2187 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2188 return uTscValue + pVmcs->u64TscOffset.u;
2189 return uTscValue;
2190 }
2191
2192 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2193 {
2194 uint64_t offTsc;
2195 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2196 {
2197 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2198 Assert(pVmcb);
2199 offTsc = pVmcb->ctrl.u64TSCOffset;
2200 }
2201 return uTscValue + offTsc;
2202 }
2203 return uTscValue;
2204}
2205
2206
2207/**
2208 * Removes the TSC offset of a nested-guest if any and returns the TSC value for the
2209 * guest.
2210 *
2211 * @returns The TSC offset after removing any nested-guest TSC offset.
2212 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2213 * @param uTscValue The nested-guest TSC.
2214 *
2215 * @sa CPUMApplyNestedGuestTscOffset.
2216 */
2217VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2218{
2219 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2220 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2221 {
2222 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2223 {
2224 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2225 Assert(pVmcs);
2226 return uTscValue - pVmcs->u64TscOffset.u;
2227 }
2228 return uTscValue;
2229 }
2230
2231 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2232 {
2233 uint64_t offTsc;
2234 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2235 {
2236 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2237 Assert(pVmcb);
2238 offTsc = pVmcb->ctrl.u64TSCOffset;
2239 }
2240 return uTscValue - offTsc;
2241 }
2242 return uTscValue;
2243}
2244
2245
2246/**
2247 * Used to dynamically imports state residing in NEM or HM.
2248 *
2249 * This is a worker for the CPUM_IMPORT_EXTRN_RET() macro and various IEM ones.
2250 *
2251 * @returns VBox status code.
2252 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2253 * @param fExtrnImport The fields to import.
2254 * @thread EMT(pVCpu)
2255 */
2256VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport)
2257{
2258 VMCPU_ASSERT_EMT(pVCpu);
2259 if (pVCpu->cpum.s.Guest.fExtrn & fExtrnImport)
2260 {
2261 switch (pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_KEEPER_MASK)
2262 {
2263 case CPUMCTX_EXTRN_KEEPER_NEM:
2264 {
2265 int rc = NEMImportStateOnDemand(pVCpu, fExtrnImport);
2266 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2267 return rc;
2268 }
2269
2270 case CPUMCTX_EXTRN_KEEPER_HM:
2271 {
2272#ifdef IN_RING0
2273 int rc = HMR0ImportStateOnDemand(pVCpu, fExtrnImport);
2274 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2275 return rc;
2276#else
2277 AssertLogRelMsgFailed(("TODO Fetch HM state: %#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport));
2278 return VINF_SUCCESS;
2279#endif
2280 }
2281 default:
2282 AssertLogRelMsgFailedReturn(("%#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport), VERR_CPUM_IPE_2);
2283 }
2284 }
2285 return VINF_SUCCESS;
2286}
2287
2288
2289/**
2290 * Gets valid CR4 bits for the guest.
2291 *
2292 * @returns Valid CR4 bits.
2293 * @param pVM The cross context VM structure.
2294 */
2295VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM)
2296{
2297 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
2298 uint64_t fMask = X86_CR4_VME | X86_CR4_PVI
2299 | X86_CR4_TSD | X86_CR4_DE
2300 | X86_CR4_PSE | X86_CR4_PAE
2301 | X86_CR4_MCE | X86_CR4_PGE
2302 | X86_CR4_PCE
2303 | X86_CR4_OSXMMEEXCPT; /** @todo r=ramshankar: Introduced in Pentium III along with SSE. Check fSse here? */
2304 if (pGuestFeatures->fFxSaveRstor)
2305 fMask |= X86_CR4_OSFXSR;
2306 if (pGuestFeatures->fVmx)
2307 fMask |= X86_CR4_VMXE;
2308 if (pGuestFeatures->fXSaveRstor)
2309 fMask |= X86_CR4_OSXSAVE;
2310 if (pGuestFeatures->fPcid)
2311 fMask |= X86_CR4_PCIDE;
2312 if (pGuestFeatures->fFsGsBase)
2313 fMask |= X86_CR4_FSGSBASE;
2314 return fMask;
2315}
2316
2317
2318/**
2319 * Starts a VMX-preemption timer to expire as specified by the nested hypervisor.
2320 *
2321 * @returns VBox status code.
2322 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2323 * @param uTimer The VMCS preemption timer value.
2324 * @param cShift The VMX-preemption timer shift (usually based on guest
2325 * VMX MSR rate).
2326 * @param pu64EntryTick Where to store the current tick when the timer is
2327 * programmed.
2328 * @thread EMT(pVCpu)
2329 */
2330VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick)
2331{
2332 Assert(uTimer);
2333 Assert(cShift <= 31);
2334 Assert(pu64EntryTick);
2335 VMCPU_ASSERT_EMT(pVCpu);
2336 uint64_t const cTicksToNext = uTimer << cShift;
2337 return TMTimerSetRelative(pVCpu->cpum.s.CTX_SUFF(pNestedVmxPreemptTimer), cTicksToNext, pu64EntryTick);
2338}
2339
2340
2341/**
2342 * Stops the VMX-preemption timer from firing.
2343 *
2344 * @returns VBox status code.
2345 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2346 * @thread EMT.
2347 *
2348 * @remarks This can be called during VM reset, so we cannot assume it will be on
2349 * the EMT corresponding to @c pVCpu.
2350 */
2351VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu)
2352{
2353 /*
2354 * CPUM gets initialized before TM, so we defer creation of timers till CPUMR3InitCompleted().
2355 * However, we still get called during CPUMR3Init() and hence we need to check if we have
2356 * a valid timer object before trying to stop it.
2357 */
2358 PTMTIMER pTimer = pVCpu->cpum.s.CTX_SUFF(pNestedVmxPreemptTimer);
2359 if (!pTimer)
2360 return VERR_NOT_FOUND;
2361
2362 int rc = TMTimerLock(pTimer, VERR_IGNORED);
2363 if (rc == VINF_SUCCESS)
2364 {
2365 if (TMTimerIsActive(pTimer))
2366 TMTimerStop(pTimer);
2367 TMTimerUnlock(pTimer);
2368 }
2369 return rc;
2370}
2371
2372
2373/**
2374 * Gets the read and write permission bits for an MSR in an MSR bitmap.
2375 *
2376 * @returns VMXMSRPM_XXX - the MSR permission.
2377 * @param pvMsrBitmap Pointer to the MSR bitmap.
2378 * @param idMsr The MSR to get permissions for.
2379 *
2380 * @sa hmR0VmxSetMsrPermission.
2381 */
2382VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr)
2383{
2384 AssertPtrReturn(pvMsrBitmap, VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR);
2385
2386 uint8_t const * const pbMsrBitmap = (uint8_t const * const)pvMsrBitmap;
2387
2388 /*
2389 * MSR Layout:
2390 * Byte index MSR range Interpreted as
2391 * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
2392 * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
2393 * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
2394 * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
2395 *
2396 * A bit corresponding to an MSR within the above range causes a VM-exit
2397 * if the bit is 1 on executions of RDMSR/WRMSR. If an MSR falls out of
2398 * the MSR range, it always cause a VM-exit.
2399 *
2400 * See Intel spec. 24.6.9 "MSR-Bitmap Address".
2401 */
2402 uint32_t const offBitmapRead = 0;
2403 uint32_t const offBitmapWrite = 0x800;
2404 uint32_t offMsr;
2405 uint32_t iBit;
2406 if (idMsr <= UINT32_C(0x00001fff))
2407 {
2408 offMsr = 0;
2409 iBit = idMsr;
2410 }
2411 else if (idMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
2412 {
2413 offMsr = 0x400;
2414 iBit = idMsr - UINT32_C(0xc0000000);
2415 }
2416 else
2417 {
2418 LogFunc(("Warning! Out of range MSR %#RX32\n", idMsr));
2419 return VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR;
2420 }
2421
2422 /*
2423 * Get the MSR read permissions.
2424 */
2425 uint32_t fRet;
2426 uint32_t const offMsrRead = offBitmapRead + offMsr;
2427 Assert(offMsrRead + (iBit >> 3) < offBitmapWrite);
2428 if (ASMBitTest(pbMsrBitmap + offMsrRead, iBit))
2429 fRet = VMXMSRPM_EXIT_RD;
2430 else
2431 fRet = VMXMSRPM_ALLOW_RD;
2432
2433 /*
2434 * Get the MSR write permissions.
2435 */
2436 uint32_t const offMsrWrite = offBitmapWrite + offMsr;
2437 Assert(offMsrWrite + (iBit >> 3) < X86_PAGE_4K_SIZE);
2438 if (ASMBitTest(pbMsrBitmap + offMsrWrite, iBit))
2439 fRet |= VMXMSRPM_EXIT_WR;
2440 else
2441 fRet |= VMXMSRPM_ALLOW_WR;
2442
2443 Assert(VMXMSRPM_IS_FLAG_VALID(fRet));
2444 return fRet;
2445}
2446
2447
2448/**
2449 * Checks the permission bits for the specified I/O port from the given I/O bitmap
2450 * to see if causes a VM-exit.
2451 *
2452 * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
2453 * @param pvIoBitmap Pointer to I/O bitmap.
2454 * @param uPort The I/O port being accessed.
2455 * @param cbAccess e size of the I/O access in bytes (1, 2 or 4 bytes).
2456 */
2457static bool cpumGetVmxIoBitmapPermission(void const *pvIoBitmap, uint16_t uPort, uint8_t cbAccess)
2458{
2459 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
2460
2461 /*
2462 * If the I/O port access wraps around the 16-bit port I/O space, we must cause a
2463 * VM-exit.
2464 *
2465 * Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc are valid and do not
2466 * constitute a wrap around. However, reading 2 bytes at port 0xffff or 4 bytes
2467 * from port 0xffff/0xfffe/0xfffd constitute a wrap around. In other words, any
2468 * access to -both- ports 0xffff and port 0 is a wrap around.
2469 *
2470 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2471 */
2472 uint32_t const uPortLast = uPort + cbAccess;
2473 if (uPortLast > 0x10000)
2474 return true;
2475
2476 /*
2477 * If any bit corresponding to the I/O access is set, we must cause a VM-exit.
2478 */
2479 uint8_t const *pbIoBitmap = (uint8_t const *)pvIoBitmap;
2480 uint16_t const offPerm = uPort >> 3; /* Byte offset of the port. */
2481 uint16_t const idxPermBit = uPort - (offPerm << 3); /* Bit offset within byte. */
2482 Assert(idxPermBit < 8);
2483 static const uint8_t s_afMask[] = { 0x0, 0x1, 0x3, 0x7, 0xf }; /* Bit-mask for all access sizes. */
2484 uint16_t const fMask = s_afMask[cbAccess] << idxPermBit; /* Bit-mask of the access. */
2485
2486 /* Fetch 8 or 16-bits depending on whether the access spans 8-bit boundary. */
2487 RTUINT16U uPerm;
2488 uPerm.s.Lo = *(pbIoBitmap + offPerm);
2489 if (idxPermBit + cbAccess > 8)
2490 uPerm.s.Hi = *(pbIoBitmap + 1 + offPerm);
2491 else
2492 uPerm.s.Hi = 0;
2493
2494 /* If any bit for the access is 1, we must cause a VM-exit. */
2495 if (uPerm.u & fMask)
2496 return true;
2497
2498 return false;
2499}
2500
2501
2502/**
2503 * Returns whether the given VMCS field is valid and supported for the guest.
2504 *
2505 * @param pVM The cross context VM structure.
2506 * @param u64VmcsField The VMCS field.
2507 *
2508 * @remarks This takes into account the CPU features exposed to the guest.
2509 */
2510VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField)
2511{
2512 uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
2513 uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
2514 if (!uFieldEncHi)
2515 { /* likely */ }
2516 else
2517 return false;
2518
2519 PCCPUMFEATURES pFeat = &pVM->cpum.s.GuestFeatures;
2520 switch (uFieldEncLo)
2521 {
2522 /*
2523 * 16-bit fields.
2524 */
2525 /* Control fields. */
2526 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
2527 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
2528 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
2529
2530 /* Guest-state fields. */
2531 case VMX_VMCS16_GUEST_ES_SEL:
2532 case VMX_VMCS16_GUEST_CS_SEL:
2533 case VMX_VMCS16_GUEST_SS_SEL:
2534 case VMX_VMCS16_GUEST_DS_SEL:
2535 case VMX_VMCS16_GUEST_FS_SEL:
2536 case VMX_VMCS16_GUEST_GS_SEL:
2537 case VMX_VMCS16_GUEST_LDTR_SEL:
2538 case VMX_VMCS16_GUEST_TR_SEL: return true;
2539 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
2540 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
2541
2542 /* Host-state fields. */
2543 case VMX_VMCS16_HOST_ES_SEL:
2544 case VMX_VMCS16_HOST_CS_SEL:
2545 case VMX_VMCS16_HOST_SS_SEL:
2546 case VMX_VMCS16_HOST_DS_SEL:
2547 case VMX_VMCS16_HOST_FS_SEL:
2548 case VMX_VMCS16_HOST_GS_SEL:
2549 case VMX_VMCS16_HOST_TR_SEL: return true;
2550
2551 /*
2552 * 64-bit fields.
2553 */
2554 /* Control fields. */
2555 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
2556 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
2557 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
2558 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
2559 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
2560 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
2561 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
2562 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
2563 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
2564 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
2565 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
2566 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
2567 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
2568 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
2569 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
2570 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
2571 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
2572 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
2573 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
2574 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
2575 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
2576 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
2577 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
2578 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
2579 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
2580 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
2581 case VMX_VMCS64_CTRL_EPTP_FULL:
2582 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
2583 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
2584 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
2585 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
2586 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
2587 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
2588 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
2589 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
2590 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
2591 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
2592 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
2593 {
2594 PCVMCPU pVCpu = pVM->CTX_SUFF(apCpus)[0];
2595 uint64_t const uVmFuncMsr = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
2596 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
2597 }
2598 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
2599 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
2600 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
2601 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
2602 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
2603 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
2604 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
2605 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
2606 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
2607 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
2608 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
2609 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
2610
2611 /* Read-only data fields. */
2612 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
2613 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
2614
2615 /* Guest-state fields. */
2616 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
2617 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
2618 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
2619 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
2620 case VMX_VMCS64_GUEST_PAT_FULL:
2621 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
2622 case VMX_VMCS64_GUEST_EFER_FULL:
2623 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
2624 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
2625 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
2626 case VMX_VMCS64_GUEST_PDPTE0_FULL:
2627 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
2628 case VMX_VMCS64_GUEST_PDPTE1_FULL:
2629 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
2630 case VMX_VMCS64_GUEST_PDPTE2_FULL:
2631 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
2632 case VMX_VMCS64_GUEST_PDPTE3_FULL:
2633 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
2634 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
2635 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
2636
2637 /* Host-state fields. */
2638 case VMX_VMCS64_HOST_PAT_FULL:
2639 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
2640 case VMX_VMCS64_HOST_EFER_FULL:
2641 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
2642 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
2643 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
2644
2645 /*
2646 * 32-bit fields.
2647 */
2648 /* Control fields. */
2649 case VMX_VMCS32_CTRL_PIN_EXEC:
2650 case VMX_VMCS32_CTRL_PROC_EXEC:
2651 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
2652 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
2653 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
2654 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
2655 case VMX_VMCS32_CTRL_EXIT:
2656 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
2657 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
2658 case VMX_VMCS32_CTRL_ENTRY:
2659 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
2660 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
2661 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
2662 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
2663 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
2664 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
2665 case VMX_VMCS32_CTRL_PLE_GAP:
2666 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
2667
2668 /* Read-only data fields. */
2669 case VMX_VMCS32_RO_VM_INSTR_ERROR:
2670 case VMX_VMCS32_RO_EXIT_REASON:
2671 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
2672 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
2673 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
2674 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
2675 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
2676 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
2677
2678 /* Guest-state fields. */
2679 case VMX_VMCS32_GUEST_ES_LIMIT:
2680 case VMX_VMCS32_GUEST_CS_LIMIT:
2681 case VMX_VMCS32_GUEST_SS_LIMIT:
2682 case VMX_VMCS32_GUEST_DS_LIMIT:
2683 case VMX_VMCS32_GUEST_FS_LIMIT:
2684 case VMX_VMCS32_GUEST_GS_LIMIT:
2685 case VMX_VMCS32_GUEST_LDTR_LIMIT:
2686 case VMX_VMCS32_GUEST_TR_LIMIT:
2687 case VMX_VMCS32_GUEST_GDTR_LIMIT:
2688 case VMX_VMCS32_GUEST_IDTR_LIMIT:
2689 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
2690 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
2691 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
2692 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
2693 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
2694 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
2695 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
2696 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
2697 case VMX_VMCS32_GUEST_INT_STATE:
2698 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
2699 case VMX_VMCS32_GUEST_SMBASE:
2700 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
2701 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
2702
2703 /* Host-state fields. */
2704 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
2705
2706 /*
2707 * Natural-width fields.
2708 */
2709 /* Control fields. */
2710 case VMX_VMCS_CTRL_CR0_MASK:
2711 case VMX_VMCS_CTRL_CR4_MASK:
2712 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
2713 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
2714 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
2715 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
2716 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
2717 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
2718
2719 /* Read-only data fields. */
2720 case VMX_VMCS_RO_EXIT_QUALIFICATION:
2721 case VMX_VMCS_RO_IO_RCX:
2722 case VMX_VMCS_RO_IO_RSI:
2723 case VMX_VMCS_RO_IO_RDI:
2724 case VMX_VMCS_RO_IO_RIP:
2725 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
2726
2727 /* Guest-state fields. */
2728 case VMX_VMCS_GUEST_CR0:
2729 case VMX_VMCS_GUEST_CR3:
2730 case VMX_VMCS_GUEST_CR4:
2731 case VMX_VMCS_GUEST_ES_BASE:
2732 case VMX_VMCS_GUEST_CS_BASE:
2733 case VMX_VMCS_GUEST_SS_BASE:
2734 case VMX_VMCS_GUEST_DS_BASE:
2735 case VMX_VMCS_GUEST_FS_BASE:
2736 case VMX_VMCS_GUEST_GS_BASE:
2737 case VMX_VMCS_GUEST_LDTR_BASE:
2738 case VMX_VMCS_GUEST_TR_BASE:
2739 case VMX_VMCS_GUEST_GDTR_BASE:
2740 case VMX_VMCS_GUEST_IDTR_BASE:
2741 case VMX_VMCS_GUEST_DR7:
2742 case VMX_VMCS_GUEST_RSP:
2743 case VMX_VMCS_GUEST_RIP:
2744 case VMX_VMCS_GUEST_RFLAGS:
2745 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
2746 case VMX_VMCS_GUEST_SYSENTER_ESP:
2747 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
2748
2749 /* Host-state fields. */
2750 case VMX_VMCS_HOST_CR0:
2751 case VMX_VMCS_HOST_CR3:
2752 case VMX_VMCS_HOST_CR4:
2753 case VMX_VMCS_HOST_FS_BASE:
2754 case VMX_VMCS_HOST_GS_BASE:
2755 case VMX_VMCS_HOST_TR_BASE:
2756 case VMX_VMCS_HOST_GDTR_BASE:
2757 case VMX_VMCS_HOST_IDTR_BASE:
2758 case VMX_VMCS_HOST_SYSENTER_ESP:
2759 case VMX_VMCS_HOST_SYSENTER_EIP:
2760 case VMX_VMCS_HOST_RSP:
2761 case VMX_VMCS_HOST_RIP: return true;
2762 }
2763
2764 return false;
2765}
2766
2767
2768/**
2769 * Checks whether the given I/O access should cause a nested-guest VM-exit.
2770 *
2771 * @returns @c true if it causes a VM-exit, @c false otherwise.
2772 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2773 * @param u16Port The I/O port being accessed.
2774 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
2775 */
2776VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
2777{
2778 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2779 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_UNCOND_IO_EXIT))
2780 return true;
2781
2782 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_IO_BITMAPS))
2783 {
2784 uint8_t const *pbIoBitmap = (uint8_t const *)pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap);
2785 Assert(pbIoBitmap);
2786 return cpumGetVmxIoBitmapPermission(pbIoBitmap, u16Port, cbAccess);
2787 }
2788
2789 return false;
2790}
2791
2792
2793/**
2794 * Checks whether the Mov-to-CR3 instruction causes a nested-guest VM-exit.
2795 *
2796 * @returns @c true if it causes a VM-exit, @c false otherwise.
2797 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2798 * @param uNewCr3 The CR3 value being written.
2799 */
2800VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3)
2801{
2802 /*
2803 * If the CR3-load exiting control is set and the new CR3 value does not
2804 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
2805 *
2806 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2807 */
2808 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2809 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2810 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_CR3_LOAD_EXIT))
2811 {
2812 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
2813 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
2814
2815 /* If the CR3-target count is 0, cause a VM-exit. */
2816 if (uCr3TargetCount == 0)
2817 return true;
2818
2819 /* If the CR3 being written doesn't match any of the target values, cause a VM-exit. */
2820 AssertCompile(VMX_V_CR3_TARGET_COUNT == 4);
2821 if ( uNewCr3 != pVmcs->u64Cr3Target0.u
2822 && uNewCr3 != pVmcs->u64Cr3Target1.u
2823 && uNewCr3 != pVmcs->u64Cr3Target2.u
2824 && uNewCr3 != pVmcs->u64Cr3Target3.u)
2825 return true;
2826 }
2827 return false;
2828}
2829
2830
2831/**
2832 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field causes a
2833 * VM-exit or not.
2834 *
2835 * @returns @c true if the VMREAD/VMWRITE is intercepted, @c false otherwise.
2836 * @param pVCpu The cross context virtual CPU structure.
2837 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
2838 * VMX_EXIT_VMREAD).
2839 * @param u64VmcsField The VMCS field.
2840 */
2841VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64VmcsField)
2842{
2843 Assert(CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest));
2844 Assert( uExitReason == VMX_EXIT_VMREAD
2845 || uExitReason == VMX_EXIT_VMWRITE);
2846
2847 /*
2848 * Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted.
2849 */
2850 if (!CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VMCS_SHADOWING))
2851 return true;
2852
2853 /*
2854 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE
2855 * is intercepted. This excludes any reserved bits in the valid parts of the field
2856 * encoding (i.e. bit 12).
2857 */
2858 if (u64VmcsField & VMX_VMCSFIELD_RSVD_MASK)
2859 return true;
2860
2861 /*
2862 * Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not.
2863 */
2864 uint32_t const u32VmcsField = RT_LO_U32(u64VmcsField);
2865 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
2866 ? (uint8_t const *)pVCpu->cpum.s.Guest.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
2867 : (uint8_t const *)pVCpu->cpum.s.Guest.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
2868 Assert(pbBitmap);
2869 Assert(u32VmcsField >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2870 return ASMBitTest(pbBitmap + (u32VmcsField >> 3), u32VmcsField & 7);
2871}
2872
2873
2874
2875/**
2876 * Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
2877 *
2878 * @param pvIoBitmap Pointer to the nested-guest IO bitmap.
2879 * @param u16Port The IO port being accessed.
2880 * @param enmIoType The type of IO access.
2881 * @param cbReg The IO operand size in bytes.
2882 * @param cAddrSizeBits The address size bits (for 16, 32 or 64).
2883 * @param iEffSeg The effective segment number.
2884 * @param fRep Whether this is a repeating IO instruction (REP prefix).
2885 * @param fStrIo Whether this is a string IO instruction.
2886 * @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
2887 * Optional, can be NULL.
2888 */
2889VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
2890 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
2891 PSVMIOIOEXITINFO pIoExitInfo)
2892{
2893 Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64);
2894 Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8);
2895
2896 /*
2897 * The IOPM layout:
2898 * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
2899 * two 4K pages.
2900 *
2901 * For IO instructions that access more than a single byte, the permission bits
2902 * for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
2903 *
2904 * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
2905 * we need 3 extra bits beyond the second 4K page.
2906 */
2907 static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
2908
2909 uint16_t const offIopm = u16Port >> 3;
2910 uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
2911 uint8_t const cShift = u16Port - (offIopm << 3);
2912 uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift);
2913
2914 uint8_t const *pbIopm = (uint8_t *)pvIoBitmap;
2915 Assert(pbIopm);
2916 pbIopm += offIopm;
2917 uint16_t const u16Iopm = *(uint16_t *)pbIopm;
2918 if (u16Iopm & fIopmMask)
2919 {
2920 if (pIoExitInfo)
2921 {
2922 static const uint32_t s_auIoOpSize[] =
2923 { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
2924
2925 static const uint32_t s_auIoAddrSize[] =
2926 { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
2927
2928 pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
2929 pIoExitInfo->u |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
2930 pIoExitInfo->n.u1Str = fStrIo;
2931 pIoExitInfo->n.u1Rep = fRep;
2932 pIoExitInfo->n.u3Seg = iEffSeg & 7;
2933 pIoExitInfo->n.u1Type = enmIoType;
2934 pIoExitInfo->n.u16Port = u16Port;
2935 }
2936 return true;
2937 }
2938
2939 /** @todo remove later (for debugging as VirtualBox always traps all IO
2940 * intercepts). */
2941 AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
2942 return false;
2943}
2944
2945
2946/**
2947 * Gets the MSR permission bitmap byte and bit offset for the specified MSR.
2948 *
2949 * @returns VBox status code.
2950 * @param idMsr The MSR being requested.
2951 * @param pbOffMsrpm Where to store the byte offset in the MSR permission
2952 * bitmap for @a idMsr.
2953 * @param puMsrpmBit Where to store the bit offset starting at the byte
2954 * returned in @a pbOffMsrpm.
2955 */
2956VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit)
2957{
2958 Assert(pbOffMsrpm);
2959 Assert(puMsrpmBit);
2960
2961 /*
2962 * MSRPM Layout:
2963 * Byte offset MSR range
2964 * 0x000 - 0x7ff 0x00000000 - 0x00001fff
2965 * 0x800 - 0xfff 0xc0000000 - 0xc0001fff
2966 * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
2967 * 0x1800 - 0x1fff Reserved
2968 *
2969 * Each MSR is represented by 2 permission bits (read and write).
2970 */
2971 if (idMsr <= 0x00001fff)
2972 {
2973 /* Pentium-compatible MSRs. */
2974 uint32_t const bitoffMsr = idMsr << 1;
2975 *pbOffMsrpm = bitoffMsr >> 3;
2976 *puMsrpmBit = bitoffMsr & 7;
2977 return VINF_SUCCESS;
2978 }
2979
2980 if ( idMsr >= 0xc0000000
2981 && idMsr <= 0xc0001fff)
2982 {
2983 /* AMD Sixth Generation x86 Processor MSRs. */
2984 uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
2985 *pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
2986 *puMsrpmBit = bitoffMsr & 7;
2987 return VINF_SUCCESS;
2988 }
2989
2990 if ( idMsr >= 0xc0010000
2991 && idMsr <= 0xc0011fff)
2992 {
2993 /* AMD Seventh and Eighth Generation Processor MSRs. */
2994 uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
2995 *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
2996 *puMsrpmBit = bitoffMsr & 7;
2997 return VINF_SUCCESS;
2998 }
2999
3000 *pbOffMsrpm = 0;
3001 *puMsrpmBit = 0;
3002 return VERR_OUT_OF_RANGE;
3003}
3004
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