VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 47705

Last change on this file since 47705 was 47661, checked in by vboxsync, 11 years ago

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1/* $Id: CPUMAllRegs.cpp 47661 2013-08-12 00:51:25Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/em.h>
30#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
31# include <VBox/vmm/selm.h>
32#endif
33#include "CPUMInternal.h"
34#include <VBox/vmm/vm.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/tm.h>
40#include <iprt/assert.h>
41#include <iprt/asm.h>
42#include <iprt/asm-amd64-x86.h>
43#ifdef IN_RING3
44#include <iprt/thread.h>
45#endif
46
47/** Disable stack frame pointer generation here. */
48#if defined(_MSC_VER) && !defined(DEBUG)
49# pragma optimize("y", off)
50#endif
51
52
53/*******************************************************************************
54* Defined Constants And Macros *
55*******************************************************************************/
56/**
57 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
58 *
59 * @returns Pointer to the Virtual CPU.
60 * @param a_pGuestCtx Pointer to the guest context.
61 */
62#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
63
64/**
65 * Lazily loads the hidden parts of a selector register when using raw-mode.
66 */
67#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
68# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
69 do \
70 { \
71 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
72 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
73 } while (0)
74#else
75# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
76 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
77#endif
78
79
80
81#ifdef VBOX_WITH_RAW_MODE_NOT_R0
82
83/**
84 * Does the lazy hidden selector register loading.
85 *
86 * @param pVCpu The current Virtual CPU.
87 * @param pSReg The selector register to lazily load hidden parts of.
88 */
89static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
90{
91 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
92 Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
93 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
94
95 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
96 {
97 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
98 pSReg->Attr.u = 0;
99 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
100 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
101 pSReg->Attr.n.u2Dpl = 3;
102 pSReg->Attr.n.u1Present = 1;
103 pSReg->u32Limit = 0x0000ffff;
104 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
105 pSReg->ValidSel = pSReg->Sel;
106 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
107 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
108 }
109 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
110 {
111 /* Real mode - leave the limit and flags alone here, at least for now. */
112 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
113 pSReg->ValidSel = pSReg->Sel;
114 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
115 }
116 else
117 {
118 /* Protected mode - get it from the selector descriptor tables. */
119 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
120 {
121 Assert(!CPUMIsGuestInLongMode(pVCpu));
122 pSReg->Sel = 0;
123 pSReg->u64Base = 0;
124 pSReg->u32Limit = 0;
125 pSReg->Attr.u = 0;
126 pSReg->ValidSel = 0;
127 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
128 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
129 }
130 else
131 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
132 }
133}
134
135
136/**
137 * Makes sure the hidden CS and SS selector registers are valid, loading them if
138 * necessary.
139 *
140 * @param pVCpu The current virtual CPU.
141 */
142VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
143{
144 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
145 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
146}
147
148
149/**
150 * Loads a the hidden parts of a selector register.
151 *
152 * @param pVCpu The current virtual CPU.
153 */
154VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
155{
156 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
157}
158
159#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
160
161
162/**
163 * Obsolete.
164 *
165 * We don't support nested hypervisor context interrupts or traps. Life is much
166 * simpler when we don't. It's also slightly faster at times.
167 *
168 * @param pVM Handle to the virtual machine.
169 */
170VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
171{
172 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
173}
174
175
176/**
177 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
178 *
179 * @param pVCpu Pointer to the VMCPU.
180 */
181VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
182{
183 return &pVCpu->cpum.s.Hyper;
184}
185
186
187VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
188{
189 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
190 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
191}
192
193
194VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
195{
196 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
197 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
198}
199
200
201VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
202{
203 pVCpu->cpum.s.Hyper.cr3 = cr3;
204
205#ifdef IN_RC
206 /* Update the current CR3. */
207 ASMSetCR3(cr3);
208#endif
209}
210
211VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
212{
213 return pVCpu->cpum.s.Hyper.cr3;
214}
215
216
217VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
218{
219 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
220}
221
222
223VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
224{
225 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
226}
227
228
229VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
230{
231 pVCpu->cpum.s.Hyper.es.Sel = SelES;
232}
233
234
235VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
236{
237 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
238}
239
240
241VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
242{
243 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
244}
245
246
247VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
248{
249 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
250}
251
252
253VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
254{
255 pVCpu->cpum.s.Hyper.esp = u32ESP;
256}
257
258
259VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
260{
261 pVCpu->cpum.s.Hyper.esp = u32ESP;
262}
263
264
265VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
266{
267 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
268 return VINF_SUCCESS;
269}
270
271
272VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
273{
274 pVCpu->cpum.s.Hyper.eip = u32EIP;
275}
276
277
278/**
279 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
280 * EFLAGS and EIP prior to resuming guest execution.
281 *
282 * All general register not given as a parameter will be set to 0. The EFLAGS
283 * register will be set to sane values for C/C++ code execution with interrupts
284 * disabled and IOPL 0.
285 *
286 * @param pVCpu The current virtual CPU.
287 * @param u32EIP The EIP value.
288 * @param u32ESP The ESP value.
289 * @param u32EAX The EAX value.
290 * @param u32EDX The EDX value.
291 */
292VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
293{
294 pVCpu->cpum.s.Hyper.eip = u32EIP;
295 pVCpu->cpum.s.Hyper.esp = u32ESP;
296 pVCpu->cpum.s.Hyper.eax = u32EAX;
297 pVCpu->cpum.s.Hyper.edx = u32EDX;
298 pVCpu->cpum.s.Hyper.ecx = 0;
299 pVCpu->cpum.s.Hyper.ebx = 0;
300 pVCpu->cpum.s.Hyper.ebp = 0;
301 pVCpu->cpum.s.Hyper.esi = 0;
302 pVCpu->cpum.s.Hyper.edi = 0;
303 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
304}
305
306
307VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
308{
309 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
310}
311
312
313VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
314{
315 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
316}
317
318
319/** @MAYBE_LOAD_DRx
320 * Macro for updating DRx values in raw-mode and ring-0 contexts.
321 */
322#ifdef IN_RING0
323# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
324# ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
325# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
326 do { \
327 if (!CPUMIsGuestInLongModeEx(&(a_pVCpu)->cpum.s.Guest)) \
328 a_fnLoad(a_uValue); \
329 else \
330 (a_pVCpu)->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_REGS_HYPER; \
331 } while (0)
332# else
333# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
334 do { \
335 /** @todo we're not loading the correct guest value here! */ \
336 a_fnLoad(a_uValue); \
337 } while (0)
338# endif
339# else
340# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
341 do { \
342 a_fnLoad(a_uValue); \
343 } while (0)
344# endif
345
346#elif defined(IN_RC)
347# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
348 do { \
349 if ((a_pVCpu)->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER) \
350 { a_fnLoad(a_uValue); } \
351 } while (0)
352
353#else
354# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
355#endif
356
357VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
358{
359 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
360 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
361}
362
363
364VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
365{
366 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
367 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
368}
369
370
371VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
372{
373 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
374 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
375}
376
377
378VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
379{
380 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
381 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
382}
383
384
385VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
386{
387 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
388}
389
390
391VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
392{
393 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
394#ifdef IN_RC
395 MAYBE_LOAD_DRx(pVCpu, ASMSetDR7, uDr7);
396#endif
397}
398
399
400VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
401{
402 return pVCpu->cpum.s.Hyper.cs.Sel;
403}
404
405
406VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
407{
408 return pVCpu->cpum.s.Hyper.ds.Sel;
409}
410
411
412VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
413{
414 return pVCpu->cpum.s.Hyper.es.Sel;
415}
416
417
418VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
419{
420 return pVCpu->cpum.s.Hyper.fs.Sel;
421}
422
423
424VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
425{
426 return pVCpu->cpum.s.Hyper.gs.Sel;
427}
428
429
430VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
431{
432 return pVCpu->cpum.s.Hyper.ss.Sel;
433}
434
435
436VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
437{
438 return pVCpu->cpum.s.Hyper.eax;
439}
440
441
442VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
443{
444 return pVCpu->cpum.s.Hyper.ebx;
445}
446
447
448VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
449{
450 return pVCpu->cpum.s.Hyper.ecx;
451}
452
453
454VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
455{
456 return pVCpu->cpum.s.Hyper.edx;
457}
458
459
460VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
461{
462 return pVCpu->cpum.s.Hyper.esi;
463}
464
465
466VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
467{
468 return pVCpu->cpum.s.Hyper.edi;
469}
470
471
472VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
473{
474 return pVCpu->cpum.s.Hyper.ebp;
475}
476
477
478VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
479{
480 return pVCpu->cpum.s.Hyper.esp;
481}
482
483
484VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
485{
486 return pVCpu->cpum.s.Hyper.eflags.u32;
487}
488
489
490VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
491{
492 return pVCpu->cpum.s.Hyper.eip;
493}
494
495
496VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
497{
498 return pVCpu->cpum.s.Hyper.rip;
499}
500
501
502VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
503{
504 if (pcbLimit)
505 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
506 return pVCpu->cpum.s.Hyper.idtr.pIdt;
507}
508
509
510VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
511{
512 if (pcbLimit)
513 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
514 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
515}
516
517
518VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
519{
520 return pVCpu->cpum.s.Hyper.ldtr.Sel;
521}
522
523
524VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
525{
526 return pVCpu->cpum.s.Hyper.dr[0];
527}
528
529
530VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
531{
532 return pVCpu->cpum.s.Hyper.dr[1];
533}
534
535
536VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
537{
538 return pVCpu->cpum.s.Hyper.dr[2];
539}
540
541
542VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
543{
544 return pVCpu->cpum.s.Hyper.dr[3];
545}
546
547
548VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
549{
550 return pVCpu->cpum.s.Hyper.dr[6];
551}
552
553
554VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
555{
556 return pVCpu->cpum.s.Hyper.dr[7];
557}
558
559
560/**
561 * Gets the pointer to the internal CPUMCTXCORE structure.
562 * This is only for reading in order to save a few calls.
563 *
564 * @param pVCpu Handle to the virtual cpu.
565 */
566VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
567{
568 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
569}
570
571
572/**
573 * Queries the pointer to the internal CPUMCTX structure.
574 *
575 * @returns The CPUMCTX pointer.
576 * @param pVCpu Handle to the virtual cpu.
577 */
578VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
579{
580 return &pVCpu->cpum.s.Guest;
581}
582
583VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
584{
585#ifdef VBOX_WITH_IEM
586# ifdef VBOX_WITH_RAW_MODE_NOT_R0
587 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
588 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
589# endif
590#endif
591 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
592 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
593 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
594 return VINF_SUCCESS; /* formality, consider it void. */
595}
596
597VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
598{
599#ifdef VBOX_WITH_IEM
600# ifdef VBOX_WITH_RAW_MODE_NOT_R0
601 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
602 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
603# endif
604#endif
605 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
606 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
607 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
608 return VINF_SUCCESS; /* formality, consider it void. */
609}
610
611VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
612{
613#ifdef VBOX_WITH_IEM
614# ifdef VBOX_WITH_RAW_MODE_NOT_R0
615 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
616 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
617# endif
618#endif
619 pVCpu->cpum.s.Guest.tr.Sel = tr;
620 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
621 return VINF_SUCCESS; /* formality, consider it void. */
622}
623
624VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
625{
626#ifdef VBOX_WITH_IEM
627# ifdef VBOX_WITH_RAW_MODE_NOT_R0
628 if ( ( ldtr != 0
629 || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
630 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
631 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
632# endif
633#endif
634 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
635 /* The caller will set more hidden bits if it has them. */
636 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
637 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
638 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
639 return VINF_SUCCESS; /* formality, consider it void. */
640}
641
642
643/**
644 * Set the guest CR0.
645 *
646 * When called in GC, the hyper CR0 may be updated if that is
647 * required. The caller only has to take special action if AM,
648 * WP, PG or PE changes.
649 *
650 * @returns VINF_SUCCESS (consider it void).
651 * @param pVCpu Handle to the virtual cpu.
652 * @param cr0 The new CR0 value.
653 */
654VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
655{
656#ifdef IN_RC
657 /*
658 * Check if we need to change hypervisor CR0 because
659 * of math stuff.
660 */
661 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
662 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
663 {
664 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
665 {
666 /*
667 * We haven't saved the host FPU state yet, so TS and MT are both set
668 * and EM should be reflecting the guest EM (it always does this).
669 */
670 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
671 {
672 uint32_t HyperCR0 = ASMGetCR0();
673 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
674 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
675 HyperCR0 &= ~X86_CR0_EM;
676 HyperCR0 |= cr0 & X86_CR0_EM;
677 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
678 ASMSetCR0(HyperCR0);
679 }
680# ifdef VBOX_STRICT
681 else
682 {
683 uint32_t HyperCR0 = ASMGetCR0();
684 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
685 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
686 }
687# endif
688 }
689 else
690 {
691 /*
692 * Already saved the state, so we're just mirroring
693 * the guest flags.
694 */
695 uint32_t HyperCR0 = ASMGetCR0();
696 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
697 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
698 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
699 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
700 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
701 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
702 ASMSetCR0(HyperCR0);
703 }
704 }
705#endif /* IN_RC */
706
707 /*
708 * Check for changes causing TLB flushes (for REM).
709 * The caller is responsible for calling PGM when appropriate.
710 */
711 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
712 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
713 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
714 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
715
716 /*
717 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
718 */
719 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
720 PGMCr0WpEnabled(pVCpu);
721
722 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
723 return VINF_SUCCESS;
724}
725
726
727VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
728{
729 pVCpu->cpum.s.Guest.cr2 = cr2;
730 return VINF_SUCCESS;
731}
732
733
734VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
735{
736 pVCpu->cpum.s.Guest.cr3 = cr3;
737 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
738 return VINF_SUCCESS;
739}
740
741
742VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
743{
744 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
745 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
746 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
747 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
748 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
749 cr4 &= ~X86_CR4_OSFSXR;
750 pVCpu->cpum.s.Guest.cr4 = cr4;
751 return VINF_SUCCESS;
752}
753
754
755VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
756{
757 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
758 return VINF_SUCCESS;
759}
760
761
762VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
763{
764 pVCpu->cpum.s.Guest.eip = eip;
765 return VINF_SUCCESS;
766}
767
768
769VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
770{
771 pVCpu->cpum.s.Guest.eax = eax;
772 return VINF_SUCCESS;
773}
774
775
776VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
777{
778 pVCpu->cpum.s.Guest.ebx = ebx;
779 return VINF_SUCCESS;
780}
781
782
783VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
784{
785 pVCpu->cpum.s.Guest.ecx = ecx;
786 return VINF_SUCCESS;
787}
788
789
790VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
791{
792 pVCpu->cpum.s.Guest.edx = edx;
793 return VINF_SUCCESS;
794}
795
796
797VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
798{
799 pVCpu->cpum.s.Guest.esp = esp;
800 return VINF_SUCCESS;
801}
802
803
804VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
805{
806 pVCpu->cpum.s.Guest.ebp = ebp;
807 return VINF_SUCCESS;
808}
809
810
811VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
812{
813 pVCpu->cpum.s.Guest.esi = esi;
814 return VINF_SUCCESS;
815}
816
817
818VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
819{
820 pVCpu->cpum.s.Guest.edi = edi;
821 return VINF_SUCCESS;
822}
823
824
825VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
826{
827 pVCpu->cpum.s.Guest.ss.Sel = ss;
828 return VINF_SUCCESS;
829}
830
831
832VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
833{
834 pVCpu->cpum.s.Guest.cs.Sel = cs;
835 return VINF_SUCCESS;
836}
837
838
839VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
840{
841 pVCpu->cpum.s.Guest.ds.Sel = ds;
842 return VINF_SUCCESS;
843}
844
845
846VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
847{
848 pVCpu->cpum.s.Guest.es.Sel = es;
849 return VINF_SUCCESS;
850}
851
852
853VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
854{
855 pVCpu->cpum.s.Guest.fs.Sel = fs;
856 return VINF_SUCCESS;
857}
858
859
860VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
861{
862 pVCpu->cpum.s.Guest.gs.Sel = gs;
863 return VINF_SUCCESS;
864}
865
866
867VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
868{
869 pVCpu->cpum.s.Guest.msrEFER = val;
870}
871
872
873/**
874 * Query an MSR.
875 *
876 * The caller is responsible for checking privilege if the call is the result
877 * of a RDMSR instruction. We'll do the rest.
878 *
879 * @retval VINF_SUCCESS on success.
880 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
881 * expected to take the appropriate actions. @a *puValue is set to 0.
882 * @param pVCpu Pointer to the VMCPU.
883 * @param idMsr The MSR.
884 * @param puValue Where to return the value.
885 *
886 * @remarks This will always return the right values, even when we're in the
887 * recompiler.
888 */
889VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
890{
891 /*
892 * If we don't indicate MSR support in the CPUID feature bits, indicate
893 * that a #GP(0) should be raised.
894 */
895 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
896 {
897 *puValue = 0;
898 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
899 }
900
901 int rc = VINF_SUCCESS;
902 uint8_t const u8Multiplier = 4;
903 switch (idMsr)
904 {
905 case MSR_IA32_TSC:
906 *puValue = TMCpuTickGet(pVCpu);
907 break;
908
909 case MSR_IA32_APICBASE:
910 {
911 PVM pVM = pVCpu->CTX_SUFF(pVM);
912 if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
913 && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
914 || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
915 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
916 && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
917 || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
918 && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
919 {
920 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
921 }
922 else
923 {
924 *puValue = 0;
925 rc = VERR_CPUM_RAISE_GP_0;
926 }
927 break;
928 }
929
930 case MSR_IA32_CR_PAT:
931 *puValue = pVCpu->cpum.s.Guest.msrPAT;
932 break;
933
934 case MSR_IA32_SYSENTER_CS:
935 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
936 break;
937
938 case MSR_IA32_SYSENTER_EIP:
939 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
940 break;
941
942 case MSR_IA32_SYSENTER_ESP:
943 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
944 break;
945
946 case MSR_IA32_MTRR_CAP:
947 {
948 /* This is currently a bit weird. :-) */
949 uint8_t const cVariableRangeRegs = 0;
950 bool const fSystemManagementRangeRegisters = false;
951 bool const fFixedRangeRegisters = false;
952 bool const fWriteCombiningType = false;
953 *puValue = cVariableRangeRegs
954 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
955 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
956 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
957 break;
958 }
959
960 case MSR_IA32_MTRR_DEF_TYPE:
961 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
962 break;
963
964 case IA32_MTRR_FIX64K_00000:
965 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
966 break;
967 case IA32_MTRR_FIX16K_80000:
968 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
969 break;
970 case IA32_MTRR_FIX16K_A0000:
971 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
972 break;
973 case IA32_MTRR_FIX4K_C0000:
974 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
975 break;
976 case IA32_MTRR_FIX4K_C8000:
977 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
978 break;
979 case IA32_MTRR_FIX4K_D0000:
980 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
981 break;
982 case IA32_MTRR_FIX4K_D8000:
983 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
984 break;
985 case IA32_MTRR_FIX4K_E0000:
986 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
987 break;
988 case IA32_MTRR_FIX4K_E8000:
989 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
990 break;
991 case IA32_MTRR_FIX4K_F0000:
992 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
993 break;
994 case IA32_MTRR_FIX4K_F8000:
995 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
996 break;
997
998 case MSR_K6_EFER:
999 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1000 break;
1001
1002 case MSR_K8_SF_MASK:
1003 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1004 break;
1005
1006 case MSR_K6_STAR:
1007 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1008 break;
1009
1010 case MSR_K8_LSTAR:
1011 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1012 break;
1013
1014 case MSR_K8_CSTAR:
1015 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1016 break;
1017
1018 case MSR_K8_FS_BASE:
1019 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1020 break;
1021
1022 case MSR_K8_GS_BASE:
1023 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1024 break;
1025
1026 case MSR_K8_KERNEL_GS_BASE:
1027 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1028 break;
1029
1030 case MSR_K8_TSC_AUX:
1031 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1032 break;
1033
1034 case MSR_IA32_PERF_STATUS:
1035 /** @todo could really be not exactly correct, maybe use host's values */
1036 *puValue = UINT64_C(1000) /* TSC increment by tick */
1037 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
1038 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
1039 break;
1040
1041 case MSR_IA32_FSB_CLOCK_STS:
1042 /*
1043 * Encoded as:
1044 * 0 - 266
1045 * 1 - 133
1046 * 2 - 200
1047 * 3 - return 166
1048 * 5 - return 100
1049 */
1050 *puValue = (2 << 4);
1051 break;
1052
1053 case MSR_IA32_PLATFORM_INFO:
1054 *puValue = (u8Multiplier << 8) /* Flex ratio max */
1055 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
1056 break;
1057
1058 case MSR_IA32_THERM_STATUS:
1059 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
1060 *puValue = RT_BIT(31) /* validity bit */
1061 | (UINT64_C(20) << 16) /* degrees till TCC */;
1062 break;
1063
1064 case MSR_IA32_MISC_ENABLE:
1065#if 0
1066 /* Needs to be tested more before enabling. */
1067 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
1068#else
1069 /* Currenty we don't allow guests to modify enable MSRs. */
1070 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
1071
1072 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
1073
1074 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
1075 /** @todo: add more cpuid-controlled features this way. */
1076#endif
1077 break;
1078
1079#if 0 /*def IN_RING0 */
1080 case MSR_IA32_PLATFORM_ID:
1081 case MSR_IA32_BIOS_SIGN_ID:
1082 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
1083 {
1084 /* Available since the P6 family. VT-x implies that this feature is present. */
1085 if (idMsr == MSR_IA32_PLATFORM_ID)
1086 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
1087 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
1088 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
1089 break;
1090 }
1091 /* no break */
1092#endif
1093
1094 /*
1095 * Intel specifics MSRs:
1096 */
1097 case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
1098 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1099 /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
1100 case MSR_IA32_MCP_CAP: /* fam/mod >= 6_01 */
1101 /*case MSR_IA32_MCP_STATUS: - indicated as not present in CAP */
1102 /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
1103 case MSR_IA32_MC0_CTL:
1104 case MSR_IA32_MC0_STATUS:
1105 *puValue = 0;
1106 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1107 {
1108 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1109 rc = VERR_CPUM_RAISE_GP_0;
1110 }
1111 break;
1112
1113 default:
1114 /*
1115 * Hand the X2APIC range to PDM and the APIC.
1116 */
1117 if ( idMsr >= MSR_IA32_X2APIC_START
1118 && idMsr <= MSR_IA32_X2APIC_END)
1119 {
1120 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1121 if (RT_SUCCESS(rc))
1122 rc = VINF_SUCCESS;
1123 else
1124 {
1125 *puValue = 0;
1126 rc = VERR_CPUM_RAISE_GP_0;
1127 }
1128 }
1129 else
1130 {
1131 *puValue = 0;
1132 rc = VERR_CPUM_RAISE_GP_0;
1133 }
1134 break;
1135 }
1136
1137 return rc;
1138}
1139
1140
1141/**
1142 * Sets the MSR.
1143 *
1144 * The caller is responsible for checking privilege if the call is the result
1145 * of a WRMSR instruction. We'll do the rest.
1146 *
1147 * @retval VINF_SUCCESS on success.
1148 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
1149 * appropriate actions.
1150 *
1151 * @param pVCpu Pointer to the VMCPU.
1152 * @param idMsr The MSR id.
1153 * @param uValue The value to set.
1154 *
1155 * @remarks Everyone changing MSR values, including the recompiler, shall do it
1156 * by calling this method. This makes sure we have current values and
1157 * that we trigger all the right actions when something changes.
1158 */
1159VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
1160{
1161 /*
1162 * If we don't indicate MSR support in the CPUID feature bits, indicate
1163 * that a #GP(0) should be raised.
1164 */
1165 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
1166 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
1167
1168 int rc = VINF_SUCCESS;
1169 switch (idMsr)
1170 {
1171 case MSR_IA32_MISC_ENABLE:
1172 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
1173 break;
1174
1175 case MSR_IA32_TSC:
1176 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1177 break;
1178
1179 case MSR_IA32_APICBASE:
1180 rc = PDMApicSetBase(pVCpu, uValue);
1181 if (rc != VINF_SUCCESS)
1182 rc = VERR_CPUM_RAISE_GP_0;
1183 break;
1184
1185 case MSR_IA32_CR_PAT:
1186 pVCpu->cpum.s.Guest.msrPAT = uValue;
1187 break;
1188
1189 case MSR_IA32_SYSENTER_CS:
1190 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1191 break;
1192
1193 case MSR_IA32_SYSENTER_EIP:
1194 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1195 break;
1196
1197 case MSR_IA32_SYSENTER_ESP:
1198 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1199 break;
1200
1201 case MSR_IA32_MTRR_CAP:
1202 return VERR_CPUM_RAISE_GP_0;
1203
1204 case MSR_IA32_MTRR_DEF_TYPE:
1205 if ( (uValue & UINT64_C(0xfffffffffffff300))
1206 || ( (uValue & 0xff) != 0
1207 && (uValue & 0xff) != 1
1208 && (uValue & 0xff) != 4
1209 && (uValue & 0xff) != 5
1210 && (uValue & 0xff) != 6) )
1211 {
1212 Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1213 return VERR_CPUM_RAISE_GP_0;
1214 }
1215 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1216 break;
1217
1218 case IA32_MTRR_FIX64K_00000:
1219 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1220 break;
1221 case IA32_MTRR_FIX16K_80000:
1222 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1223 break;
1224 case IA32_MTRR_FIX16K_A0000:
1225 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1226 break;
1227 case IA32_MTRR_FIX4K_C0000:
1228 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1229 break;
1230 case IA32_MTRR_FIX4K_C8000:
1231 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1232 break;
1233 case IA32_MTRR_FIX4K_D0000:
1234 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1235 break;
1236 case IA32_MTRR_FIX4K_D8000:
1237 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1238 break;
1239 case IA32_MTRR_FIX4K_E0000:
1240 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1241 break;
1242 case IA32_MTRR_FIX4K_E8000:
1243 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1244 break;
1245 case IA32_MTRR_FIX4K_F0000:
1246 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1247 break;
1248 case IA32_MTRR_FIX4K_F8000:
1249 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1250 break;
1251
1252 /*
1253 * AMD64 MSRs.
1254 */
1255 case MSR_K6_EFER:
1256 {
1257 PVM pVM = pVCpu->CTX_SUFF(pVM);
1258 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1259 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1260 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1261 : 0;
1262 uint64_t fMask = 0;
1263
1264 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1265 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1266 fMask |= MSR_K6_EFER_NXE;
1267 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1268 fMask |= MSR_K6_EFER_LME;
1269 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1270 fMask |= MSR_K6_EFER_SCE;
1271 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1272 fMask |= MSR_K6_EFER_FFXSR;
1273
1274 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1275 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1276 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1277 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1278 {
1279 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1280 return VERR_CPUM_RAISE_GP_0;
1281 }
1282
1283 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1284 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1285 ("Unexpected value %RX64\n", uValue));
1286 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1287
1288 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1289 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1290 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1291 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1292 {
1293 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1294 HMFlushTLB(pVCpu);
1295
1296 /* Notify PGM about NXE changes. */
1297 if ( (uOldEFER & MSR_K6_EFER_NXE)
1298 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1299 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1300 }
1301 break;
1302 }
1303
1304 case MSR_K8_SF_MASK:
1305 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1306 break;
1307
1308 case MSR_K6_STAR:
1309 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1310 break;
1311
1312 case MSR_K8_LSTAR:
1313 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1314 break;
1315
1316 case MSR_K8_CSTAR:
1317 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1318 break;
1319
1320 case MSR_K8_FS_BASE:
1321 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1322 break;
1323
1324 case MSR_K8_GS_BASE:
1325 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1326 break;
1327
1328 case MSR_K8_KERNEL_GS_BASE:
1329 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1330 break;
1331
1332 case MSR_K8_TSC_AUX:
1333 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1334 break;
1335
1336 /*
1337 * Intel specifics MSRs:
1338 */
1339 /*case MSR_IA32_PLATFORM_ID: - read-only */
1340 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1341 case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
1342 /*case MSR_IA32_MCP_CAP: - read-only */
1343 /*case MSR_IA32_MCP_STATUS: - read-only */
1344 /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
1345 /*case MSR_IA32_MC0_CTL: - read-only? */
1346 /*case MSR_IA32_MC0_STATUS: - read-only? */
1347 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1348 {
1349 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1350 return VERR_CPUM_RAISE_GP_0;
1351 }
1352 /* ignored */
1353 break;
1354
1355 default:
1356 /*
1357 * Hand the X2APIC range to PDM and the APIC.
1358 */
1359 if ( idMsr >= MSR_IA32_X2APIC_START
1360 && idMsr <= MSR_IA32_X2APIC_END)
1361 {
1362 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1363 if (rc != VINF_SUCCESS)
1364 rc = VERR_CPUM_RAISE_GP_0;
1365 }
1366 else
1367 {
1368 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1369 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1370 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1371 }
1372 break;
1373 }
1374 return rc;
1375}
1376
1377
1378VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1379{
1380 if (pcbLimit)
1381 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1382 return pVCpu->cpum.s.Guest.idtr.pIdt;
1383}
1384
1385
1386VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1387{
1388 if (pHidden)
1389 *pHidden = pVCpu->cpum.s.Guest.tr;
1390 return pVCpu->cpum.s.Guest.tr.Sel;
1391}
1392
1393
1394VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1395{
1396 return pVCpu->cpum.s.Guest.cs.Sel;
1397}
1398
1399
1400VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1401{
1402 return pVCpu->cpum.s.Guest.ds.Sel;
1403}
1404
1405
1406VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1407{
1408 return pVCpu->cpum.s.Guest.es.Sel;
1409}
1410
1411
1412VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1413{
1414 return pVCpu->cpum.s.Guest.fs.Sel;
1415}
1416
1417
1418VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1419{
1420 return pVCpu->cpum.s.Guest.gs.Sel;
1421}
1422
1423
1424VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1425{
1426 return pVCpu->cpum.s.Guest.ss.Sel;
1427}
1428
1429
1430VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1431{
1432 return pVCpu->cpum.s.Guest.ldtr.Sel;
1433}
1434
1435
1436VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
1437{
1438 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
1439 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
1440 return pVCpu->cpum.s.Guest.ldtr.Sel;
1441}
1442
1443
1444VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1445{
1446 return pVCpu->cpum.s.Guest.cr0;
1447}
1448
1449
1450VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1451{
1452 return pVCpu->cpum.s.Guest.cr2;
1453}
1454
1455
1456VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1457{
1458 return pVCpu->cpum.s.Guest.cr3;
1459}
1460
1461
1462VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1463{
1464 return pVCpu->cpum.s.Guest.cr4;
1465}
1466
1467
1468VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1469{
1470 uint64_t u64;
1471 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1472 if (RT_FAILURE(rc))
1473 u64 = 0;
1474 return u64;
1475}
1476
1477
1478VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1479{
1480 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1481}
1482
1483
1484VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1485{
1486 return pVCpu->cpum.s.Guest.eip;
1487}
1488
1489
1490VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1491{
1492 return pVCpu->cpum.s.Guest.rip;
1493}
1494
1495
1496VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1497{
1498 return pVCpu->cpum.s.Guest.eax;
1499}
1500
1501
1502VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1503{
1504 return pVCpu->cpum.s.Guest.ebx;
1505}
1506
1507
1508VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1509{
1510 return pVCpu->cpum.s.Guest.ecx;
1511}
1512
1513
1514VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1515{
1516 return pVCpu->cpum.s.Guest.edx;
1517}
1518
1519
1520VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1521{
1522 return pVCpu->cpum.s.Guest.esi;
1523}
1524
1525
1526VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1527{
1528 return pVCpu->cpum.s.Guest.edi;
1529}
1530
1531
1532VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1533{
1534 return pVCpu->cpum.s.Guest.esp;
1535}
1536
1537
1538VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1539{
1540 return pVCpu->cpum.s.Guest.ebp;
1541}
1542
1543
1544VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1545{
1546 return pVCpu->cpum.s.Guest.eflags.u32;
1547}
1548
1549
1550VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1551{
1552 switch (iReg)
1553 {
1554 case DISCREG_CR0:
1555 *pValue = pVCpu->cpum.s.Guest.cr0;
1556 break;
1557
1558 case DISCREG_CR2:
1559 *pValue = pVCpu->cpum.s.Guest.cr2;
1560 break;
1561
1562 case DISCREG_CR3:
1563 *pValue = pVCpu->cpum.s.Guest.cr3;
1564 break;
1565
1566 case DISCREG_CR4:
1567 *pValue = pVCpu->cpum.s.Guest.cr4;
1568 break;
1569
1570 case DISCREG_CR8:
1571 {
1572 uint8_t u8Tpr;
1573 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
1574 if (RT_FAILURE(rc))
1575 {
1576 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1577 *pValue = 0;
1578 return rc;
1579 }
1580 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1581 break;
1582 }
1583
1584 default:
1585 return VERR_INVALID_PARAMETER;
1586 }
1587 return VINF_SUCCESS;
1588}
1589
1590
1591VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1592{
1593 return pVCpu->cpum.s.Guest.dr[0];
1594}
1595
1596
1597VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1598{
1599 return pVCpu->cpum.s.Guest.dr[1];
1600}
1601
1602
1603VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1604{
1605 return pVCpu->cpum.s.Guest.dr[2];
1606}
1607
1608
1609VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1610{
1611 return pVCpu->cpum.s.Guest.dr[3];
1612}
1613
1614
1615VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1616{
1617 return pVCpu->cpum.s.Guest.dr[6];
1618}
1619
1620
1621VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1622{
1623 return pVCpu->cpum.s.Guest.dr[7];
1624}
1625
1626
1627VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1628{
1629 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1630 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1631 if (iReg == 4 || iReg == 5)
1632 iReg += 2;
1633 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1634 return VINF_SUCCESS;
1635}
1636
1637
1638VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1639{
1640 return pVCpu->cpum.s.Guest.msrEFER;
1641}
1642
1643
1644/**
1645 * Gets a CPUID leaf.
1646 *
1647 * @param pVCpu Pointer to the VMCPU.
1648 * @param iLeaf The CPUID leaf to get.
1649 * @param pEax Where to store the EAX value.
1650 * @param pEbx Where to store the EBX value.
1651 * @param pEcx Where to store the ECX value.
1652 * @param pEdx Where to store the EDX value.
1653 */
1654VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1655{
1656 PVM pVM = pVCpu->CTX_SUFF(pVM);
1657
1658 PCCPUMCPUID pCpuId;
1659 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1660 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1661 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1662 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1663 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1664 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1665 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1666 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1667 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1668 else
1669 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1670
1671 uint32_t cCurrentCacheIndex = *pEcx;
1672
1673 *pEax = pCpuId->eax;
1674 *pEbx = pCpuId->ebx;
1675 *pEcx = pCpuId->ecx;
1676 *pEdx = pCpuId->edx;
1677
1678 if ( iLeaf == 1)
1679 {
1680 /* Bits 31-24: Initial APIC ID */
1681 Assert(pVCpu->idCpu <= 255);
1682 *pEbx |= (pVCpu->idCpu << 24);
1683 }
1684
1685 if ( iLeaf == 4
1686 && cCurrentCacheIndex < 3
1687 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1688 {
1689 uint32_t type, level, sharing, linesize,
1690 partitions, associativity, sets, cores;
1691
1692 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1693 partitions = 1;
1694 /* Those are only to shut up compiler, as they will always
1695 get overwritten, and compiler should be able to figure that out */
1696 sets = associativity = sharing = level = 1;
1697 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1698 switch (cCurrentCacheIndex)
1699 {
1700 case 0:
1701 type = 1;
1702 level = 1;
1703 sharing = 1;
1704 linesize = 64;
1705 associativity = 8;
1706 sets = 64;
1707 break;
1708 case 1:
1709 level = 1;
1710 type = 2;
1711 sharing = 1;
1712 linesize = 64;
1713 associativity = 8;
1714 sets = 64;
1715 break;
1716 default: /* shut up gcc.*/
1717 AssertFailed();
1718 case 2:
1719 level = 2;
1720 type = 3;
1721 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1722 linesize = 64;
1723 associativity = 24;
1724 sets = 4096;
1725 break;
1726 }
1727
1728 *pEax |= ((cores - 1) << 26) |
1729 ((sharing - 1) << 14) |
1730 (level << 5) |
1731 1;
1732 *pEbx = (linesize - 1) |
1733 ((partitions - 1) << 12) |
1734 ((associativity - 1) << 22); /* -1 encoding */
1735 *pEcx = sets - 1;
1736 }
1737
1738 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1739}
1740
1741/**
1742 * Gets a number of standard CPUID leafs.
1743 *
1744 * @returns Number of leafs.
1745 * @param pVM Pointer to the VM.
1746 * @remark Intended for PATM.
1747 */
1748VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1749{
1750 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1751}
1752
1753
1754/**
1755 * Gets a number of extended CPUID leafs.
1756 *
1757 * @returns Number of leafs.
1758 * @param pVM Pointer to the VM.
1759 * @remark Intended for PATM.
1760 */
1761VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1762{
1763 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1764}
1765
1766
1767/**
1768 * Gets a number of centaur CPUID leafs.
1769 *
1770 * @returns Number of leafs.
1771 * @param pVM Pointer to the VM.
1772 * @remark Intended for PATM.
1773 */
1774VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1775{
1776 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1777}
1778
1779
1780/**
1781 * Sets a CPUID feature bit.
1782 *
1783 * @param pVM Pointer to the VM.
1784 * @param enmFeature The feature to set.
1785 */
1786VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1787{
1788 switch (enmFeature)
1789 {
1790 /*
1791 * Set the APIC bit in both feature masks.
1792 */
1793 case CPUMCPUIDFEATURE_APIC:
1794 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1795 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1796 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1797 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1798 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1799 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1800 break;
1801
1802 /*
1803 * Set the x2APIC bit in the standard feature mask.
1804 */
1805 case CPUMCPUIDFEATURE_X2APIC:
1806 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1807 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1808 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1809 break;
1810
1811 /*
1812 * Set the sysenter/sysexit bit in the standard feature mask.
1813 * Assumes the caller knows what it's doing! (host must support these)
1814 */
1815 case CPUMCPUIDFEATURE_SEP:
1816 {
1817 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1818 {
1819 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1820 return;
1821 }
1822
1823 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1824 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1825 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1826 break;
1827 }
1828
1829 /*
1830 * Set the syscall/sysret bit in the extended feature mask.
1831 * Assumes the caller knows what it's doing! (host must support these)
1832 */
1833 case CPUMCPUIDFEATURE_SYSCALL:
1834 {
1835 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1836 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1837 {
1838#if HC_ARCH_BITS == 32
1839 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
1840 * Even when the cpu is capable of doing so in 64 bits mode.
1841 */
1842 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1843 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1844 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1845#endif
1846 {
1847 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1848 return;
1849 }
1850 }
1851 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1852 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
1853 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1854 break;
1855 }
1856
1857 /*
1858 * Set the PAE bit in both feature masks.
1859 * Assumes the caller knows what it's doing! (host must support these)
1860 */
1861 case CPUMCPUIDFEATURE_PAE:
1862 {
1863 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1864 {
1865 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1866 return;
1867 }
1868
1869 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1870 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1871 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1872 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1873 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1874 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1875 break;
1876 }
1877
1878 /*
1879 * Set the LONG MODE bit in the extended feature mask.
1880 * Assumes the caller knows what it's doing! (host must support these)
1881 */
1882 case CPUMCPUIDFEATURE_LONG_MODE:
1883 {
1884 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1885 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1886 {
1887 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1888 return;
1889 }
1890
1891 /* Valid for both Intel and AMD. */
1892 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
1893 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1894 break;
1895 }
1896
1897 /*
1898 * Set the NX/XD bit in the extended feature mask.
1899 * Assumes the caller knows what it's doing! (host must support these)
1900 */
1901 case CPUMCPUIDFEATURE_NX:
1902 {
1903 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1904 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
1905 {
1906 LogRel(("WARNING: Can't turn on NX/XD when the host doesn't support it!!\n"));
1907 return;
1908 }
1909
1910 /* Valid for both Intel and AMD. */
1911 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
1912 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NX\n"));
1913 break;
1914 }
1915
1916 /*
1917 * Set the LAHF/SAHF support in 64-bit mode.
1918 * Assumes the caller knows what it's doing! (host must support this)
1919 */
1920 case CPUMCPUIDFEATURE_LAHF:
1921 {
1922 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1923 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
1924 {
1925 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1926 return;
1927 }
1928
1929 /* Valid for both Intel and AMD. */
1930 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
1931 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1932 break;
1933 }
1934
1935 case CPUMCPUIDFEATURE_PAT:
1936 {
1937 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1938 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1939 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1940 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1941 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1942 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAT\n"));
1943 break;
1944 }
1945
1946 /*
1947 * Set the RDTSCP support bit.
1948 * Assumes the caller knows what it's doing! (host must support this)
1949 */
1950 case CPUMCPUIDFEATURE_RDTSCP:
1951 {
1952 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1953 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
1954 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1955 {
1956 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1957 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1958 return;
1959 }
1960
1961 /* Valid for both Intel and AMD. */
1962 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
1963 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1964 break;
1965 }
1966
1967 /*
1968 * Set the Hypervisor Present bit in the standard feature mask.
1969 */
1970 case CPUMCPUIDFEATURE_HVP:
1971 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1972 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
1973 LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
1974 break;
1975
1976 default:
1977 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1978 break;
1979 }
1980 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1981 {
1982 PVMCPU pVCpu = &pVM->aCpus[i];
1983 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1984 }
1985}
1986
1987
1988/**
1989 * Queries a CPUID feature bit.
1990 *
1991 * @returns boolean for feature presence
1992 * @param pVM Pointer to the VM.
1993 * @param enmFeature The feature to query.
1994 */
1995VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1996{
1997 switch (enmFeature)
1998 {
1999 case CPUMCPUIDFEATURE_PAE:
2000 {
2001 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2002 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
2003 break;
2004 }
2005
2006 case CPUMCPUIDFEATURE_NX:
2007 {
2008 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2009 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
2010 }
2011
2012 case CPUMCPUIDFEATURE_SYSCALL:
2013 {
2014 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2015 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
2016 }
2017
2018 case CPUMCPUIDFEATURE_RDTSCP:
2019 {
2020 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2021 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2022 break;
2023 }
2024
2025 case CPUMCPUIDFEATURE_LONG_MODE:
2026 {
2027 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2028 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2029 break;
2030 }
2031
2032 default:
2033 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2034 break;
2035 }
2036 return false;
2037}
2038
2039
2040/**
2041 * Clears a CPUID feature bit.
2042 *
2043 * @param pVM Pointer to the VM.
2044 * @param enmFeature The feature to clear.
2045 */
2046VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2047{
2048 switch (enmFeature)
2049 {
2050 /*
2051 * Set the APIC bit in both feature masks.
2052 */
2053 case CPUMCPUIDFEATURE_APIC:
2054 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2055 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
2056 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2057 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2058 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
2059 Log(("CPUMClearGuestCpuIdFeature: Disabled APIC\n"));
2060 break;
2061
2062 /*
2063 * Clear the x2APIC bit in the standard feature mask.
2064 */
2065 case CPUMCPUIDFEATURE_X2APIC:
2066 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2067 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
2068 Log(("CPUMClearGuestCpuIdFeature: Disabled x2APIC\n"));
2069 break;
2070
2071 case CPUMCPUIDFEATURE_PAE:
2072 {
2073 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2074 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
2075 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2076 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2077 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
2078 Log(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
2079 break;
2080 }
2081
2082 case CPUMCPUIDFEATURE_PAT:
2083 {
2084 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2085 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
2086 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2087 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2088 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
2089 Log(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
2090 break;
2091 }
2092
2093 case CPUMCPUIDFEATURE_LONG_MODE:
2094 {
2095 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2096 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2097 break;
2098 }
2099
2100 case CPUMCPUIDFEATURE_LAHF:
2101 {
2102 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2103 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2104 break;
2105 }
2106
2107 case CPUMCPUIDFEATURE_RDTSCP:
2108 {
2109 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2110 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2111 Log(("CPUMClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
2112 break;
2113 }
2114
2115 case CPUMCPUIDFEATURE_HVP:
2116 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2117 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
2118 break;
2119
2120 default:
2121 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2122 break;
2123 }
2124 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2125 {
2126 PVMCPU pVCpu = &pVM->aCpus[i];
2127 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2128 }
2129}
2130
2131
2132/**
2133 * Gets the host CPU vendor.
2134 *
2135 * @returns CPU vendor.
2136 * @param pVM Pointer to the VM.
2137 */
2138VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
2139{
2140 return pVM->cpum.s.enmHostCpuVendor;
2141}
2142
2143
2144/**
2145 * Gets the CPU vendor.
2146 *
2147 * @returns CPU vendor.
2148 * @param pVM Pointer to the VM.
2149 */
2150VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
2151{
2152 return pVM->cpum.s.enmGuestCpuVendor;
2153}
2154
2155
2156VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
2157{
2158 pVCpu->cpum.s.Guest.dr[0] = uDr0;
2159 return CPUMRecalcHyperDRx(pVCpu, 0);
2160}
2161
2162
2163VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
2164{
2165 pVCpu->cpum.s.Guest.dr[1] = uDr1;
2166 return CPUMRecalcHyperDRx(pVCpu, 1);
2167}
2168
2169
2170VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
2171{
2172 pVCpu->cpum.s.Guest.dr[2] = uDr2;
2173 return CPUMRecalcHyperDRx(pVCpu, 2);
2174}
2175
2176
2177VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
2178{
2179 pVCpu->cpum.s.Guest.dr[3] = uDr3;
2180 return CPUMRecalcHyperDRx(pVCpu, 3);
2181}
2182
2183
2184VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
2185{
2186 pVCpu->cpum.s.Guest.dr[6] = uDr6;
2187 return VINF_SUCCESS; /* No need to recalc. */
2188}
2189
2190
2191VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
2192{
2193 pVCpu->cpum.s.Guest.dr[7] = uDr7;
2194 return CPUMRecalcHyperDRx(pVCpu, 7);
2195}
2196
2197
2198VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
2199{
2200 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
2201 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
2202 if (iReg == 4 || iReg == 5)
2203 iReg += 2;
2204 pVCpu->cpum.s.Guest.dr[iReg] = Value;
2205 return CPUMRecalcHyperDRx(pVCpu, iReg);
2206}
2207
2208
2209/**
2210 * Recalculates the hypervisor DRx register values based on current guest
2211 * registers and DBGF breakpoints, updating changed registers depending on the
2212 * context.
2213 *
2214 * This is called whenever a guest DRx register is modified (any context) and
2215 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
2216 *
2217 * In raw-mode context this function will reload any (hyper) DRx registers which
2218 * comes out with a different value. It may also have to save the host debug
2219 * registers if that haven't been done already. In this context though, we'll
2220 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
2221 * are only important when breakpoints are actually enabled.
2222 *
2223 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
2224 * reloaded by the HM code if it changes. Further more, we will only use the
2225 * combined register set when the VBox debugger is actually using hardware BPs,
2226 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
2227 * concern us here).
2228 *
2229 * In ring-3 we won't be loading anything, so well calculate hypervisor values
2230 * all the time.
2231 *
2232 * @returns VINF_SUCCESS.
2233 * @param pVCpu Pointer to the VMCPU.
2234 * @param iGstReg The guest debug register number that was modified.
2235 * UINT8_MAX if not guest register.
2236 */
2237VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg)
2238{
2239 PVM pVM = pVCpu->CTX_SUFF(pVM);
2240
2241 /*
2242 * Compare the DR7s first.
2243 *
2244 * We only care about the enabled flags. GD is virtualized when we
2245 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
2246 * always have the LE and GE bits set, so no need to check and disable
2247 * stuff if they're cleared like we have to for the guest DR7.
2248 */
2249 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2250 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
2251 uGstDr7 = 0;
2252 else if (!(uGstDr7 & X86_DR7_LE))
2253 uGstDr7 &= ~X86_DR7_LE_ALL;
2254 else if (!(uGstDr7 & X86_DR7_GE))
2255 uGstDr7 &= ~X86_DR7_GE_ALL;
2256
2257 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2258 if ((HMIsEnabled(pVCpu->CTX_SUFF(pVM)) ? uDbgfDr7 : (uGstDr7 | uDbgfDr7)) & X86_DR7_ENABLED_MASK)
2259 {
2260 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2261
2262 /*
2263 * Ok, something is enabled. Recalc each of the breakpoints, taking
2264 * the VM debugger ones of the guest ones. In raw-mode context we will
2265 * not allow breakpoints with values inside the hypervisor area.
2266 */
2267 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
2268
2269 /* bp 0 */
2270 RTGCUINTREG uNewDr0;
2271 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2272 {
2273 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2274 uNewDr0 = DBGFBpGetDR0(pVM);
2275 }
2276 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2277 {
2278 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2279#ifdef IN_RC
2280 if (MMHyperIsInsideArea(pVM, uNewDr0))
2281 uNewDr0 = 0;
2282 else
2283#endif
2284 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2285 }
2286 else
2287 uNewDr0 = 0;
2288
2289 /* bp 1 */
2290 RTGCUINTREG uNewDr1;
2291 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2292 {
2293 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2294 uNewDr1 = DBGFBpGetDR1(pVM);
2295 }
2296 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2297 {
2298 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2299#ifdef IN_RC
2300 if (MMHyperIsInsideArea(pVM, uNewDr1))
2301 uNewDr1 = 0;
2302 else
2303#endif
2304 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2305 }
2306 else
2307 uNewDr1 = 0;
2308
2309 /* bp 2 */
2310 RTGCUINTREG uNewDr2;
2311 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2312 {
2313 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2314 uNewDr2 = DBGFBpGetDR2(pVM);
2315 }
2316 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2317 {
2318 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2319#ifdef IN_RC
2320 if (MMHyperIsInsideArea(pVM, uNewDr2))
2321 uNewDr2 = 0;
2322 else
2323#endif
2324 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2325 }
2326 else
2327 uNewDr2 = 0;
2328
2329 /* bp 3 */
2330 RTGCUINTREG uNewDr3;
2331 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2332 {
2333 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2334 uNewDr3 = DBGFBpGetDR3(pVM);
2335 }
2336 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2337 {
2338 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2339#ifdef IN_RC
2340 if (MMHyperIsInsideArea(pVM, uNewDr3))
2341 uNewDr3 = 0;
2342 else
2343#endif
2344 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2345 }
2346 else
2347 uNewDr3 = 0;
2348
2349 /*
2350 * Apply the updates.
2351 */
2352#ifdef IN_RC
2353 /* Make sure to save host registers first. */
2354 if (!(pVCpu->cpum.s.fUseFlags & (CPUM_USE_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER)))
2355 {
2356 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST));
2357 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
2358 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
2359 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
2360 ASMSetDR6(X86_DR6_INIT_VAL);
2361 }
2362 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST))
2363 {
2364 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
2365 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
2366 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
2367 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
2368 pVCpu->cpum.s.fUseFlags |= CPUM_USED_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HYPER;
2369
2370 /* We haven't loaded any hyper DRxes yet, so we'll have to load them all now. */
2371 pVCpu->cpum.s.Hyper.dr[0] = uNewDr0;
2372 ASMSetDR0(uNewDr0);
2373 pVCpu->cpum.s.Hyper.dr[1] = uNewDr1;
2374 ASMSetDR1(uNewDr1);
2375 pVCpu->cpum.s.Hyper.dr[2] = uNewDr2;
2376 ASMSetDR2(uNewDr2);
2377 pVCpu->cpum.s.Hyper.dr[3] = uNewDr3;
2378 ASMSetDR3(uNewDr3);
2379 pVCpu->cpum.s.Hyper.dr[7] = uNewDr7;
2380 ASMSetDR7(uNewDr7);
2381 }
2382 else
2383#endif
2384 {
2385 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
2386 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2387 CPUMSetHyperDR3(pVCpu, uNewDr3);
2388 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2389 CPUMSetHyperDR2(pVCpu, uNewDr2);
2390 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2391 CPUMSetHyperDR1(pVCpu, uNewDr1);
2392 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2393 CPUMSetHyperDR0(pVCpu, uNewDr0);
2394 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2395 CPUMSetHyperDR7(pVCpu, uNewDr7);
2396 }
2397 }
2398#ifdef IN_RING0
2399 else if (CPUMIsGuestDebugStateActive(pVCpu))
2400 {
2401 /*
2402 * Reload the register that was modified. Normally this won't happen
2403 * as we won't intercept DRx writes when not having the hyper debug
2404 * state loaded, but in case we do for some reason we'll simply deal
2405 * with it.
2406 */
2407 switch (iGstReg)
2408 {
2409 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
2410 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
2411 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
2412 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
2413 default:
2414 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
2415 }
2416 }
2417#endif
2418 else
2419 {
2420 /*
2421 * No active debug state any more. In raw-mode this means we have to
2422 * make sure DR7 has everything disabled now, if we armed it already.
2423 *
2424 * In the ring-0 this only happens when we decided to lazy load the
2425 * debug state because it wasn't active, and that didn't change with
2426 * the latest changes, so nothing to do here.
2427 */
2428#if defined(IN_RC)
2429 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
2430 {
2431 ASMSetDR7(X86_DR7_INIT_VAL);
2432 if (pVCpu->cpum.s.Hyper.dr[0])
2433 ASMSetDR0(0);
2434 if (pVCpu->cpum.s.Hyper.dr[1])
2435 ASMSetDR1(0);
2436 if (pVCpu->cpum.s.Hyper.dr[2])
2437 ASMSetDR2(0);
2438 if (pVCpu->cpum.s.Hyper.dr[3])
2439 ASMSetDR3(0);
2440 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
2441 }
2442
2443#elif defined(IN_RING0)
2444 Assert(!CPUMIsHyperDebugStateActive(pVCpu)); /* (can only change while in ring-3) */
2445#endif
2446 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2447
2448 /* Clear all the registers. */
2449 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
2450 pVCpu->cpum.s.Hyper.dr[3] = 0;
2451 pVCpu->cpum.s.Hyper.dr[2] = 0;
2452 pVCpu->cpum.s.Hyper.dr[1] = 0;
2453 pVCpu->cpum.s.Hyper.dr[0] = 0;
2454
2455 }
2456 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2457 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2458 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2459 pVCpu->cpum.s.Hyper.dr[7]));
2460
2461 return VINF_SUCCESS;
2462}
2463
2464
2465/**
2466 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2467 *
2468 * @returns true if in real mode, otherwise false.
2469 * @param pVCpu Pointer to the VMCPU.
2470 */
2471VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2472{
2473 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2474}
2475
2476
2477/**
2478 * Tests if the guest has the Page Size Extension enabled (PSE).
2479 *
2480 * @returns true if in real mode, otherwise false.
2481 * @param pVCpu Pointer to the VMCPU.
2482 */
2483VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2484{
2485 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2486 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2487}
2488
2489
2490/**
2491 * Tests if the guest has the paging enabled (PG).
2492 *
2493 * @returns true if in real mode, otherwise false.
2494 * @param pVCpu Pointer to the VMCPU.
2495 */
2496VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2497{
2498 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2499}
2500
2501
2502/**
2503 * Tests if the guest has the paging enabled (PG).
2504 *
2505 * @returns true if in real mode, otherwise false.
2506 * @param pVCpu Pointer to the VMCPU.
2507 */
2508VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2509{
2510 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2511}
2512
2513
2514/**
2515 * Tests if the guest is running in real mode or not.
2516 *
2517 * @returns true if in real mode, otherwise false.
2518 * @param pVCpu Pointer to the VMCPU.
2519 */
2520VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2521{
2522 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2523}
2524
2525
2526/**
2527 * Tests if the guest is running in real or virtual 8086 mode.
2528 *
2529 * @returns @c true if it is, @c false if not.
2530 * @param pVCpu Pointer to the VMCPU.
2531 */
2532VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2533{
2534 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2535 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2536}
2537
2538
2539/**
2540 * Tests if the guest is running in protected or not.
2541 *
2542 * @returns true if in protected mode, otherwise false.
2543 * @param pVCpu Pointer to the VMCPU.
2544 */
2545VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2546{
2547 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2548}
2549
2550
2551/**
2552 * Tests if the guest is running in paged protected or not.
2553 *
2554 * @returns true if in paged protected mode, otherwise false.
2555 * @param pVCpu Pointer to the VMCPU.
2556 */
2557VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2558{
2559 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2560}
2561
2562
2563/**
2564 * Tests if the guest is running in long mode or not.
2565 *
2566 * @returns true if in long mode, otherwise false.
2567 * @param pVCpu Pointer to the VMCPU.
2568 */
2569VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2570{
2571 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2572}
2573
2574
2575/**
2576 * Tests if the guest is running in PAE mode or not.
2577 *
2578 * @returns true if in PAE mode, otherwise false.
2579 * @param pVCpu Pointer to the VMCPU.
2580 */
2581VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2582{
2583 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2584 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
2585 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LME);
2586}
2587
2588
2589/**
2590 * Tests if the guest is running in 64 bits mode or not.
2591 *
2592 * @returns true if in 64 bits protected mode, otherwise false.
2593 * @param pVCpu The current virtual CPU.
2594 */
2595VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
2596{
2597 if (!CPUMIsGuestInLongMode(pVCpu))
2598 return false;
2599 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2600 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
2601}
2602
2603
2604/**
2605 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
2606 * registers.
2607 *
2608 * @returns true if in 64 bits protected mode, otherwise false.
2609 * @param pCtx Pointer to the current guest CPU context.
2610 */
2611VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
2612{
2613 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
2614}
2615
2616#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2617
2618/**
2619 *
2620 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
2621 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
2622 * @param pVCpu The current virtual CPU.
2623 */
2624VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
2625{
2626 return pVCpu->cpum.s.fRawEntered;
2627}
2628
2629/**
2630 * Transforms the guest CPU state to raw-ring mode.
2631 *
2632 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
2633 *
2634 * @returns VBox status. (recompiler failure)
2635 * @param pVCpu Pointer to the VMCPU.
2636 * @param pCtxCore The context core (for trap usage).
2637 * @see @ref pg_raw
2638 */
2639VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2640{
2641 PVM pVM = pVCpu->CTX_SUFF(pVM);
2642
2643 Assert(!pVCpu->cpum.s.fRawEntered);
2644 Assert(!pVCpu->cpum.s.fRemEntered);
2645 if (!pCtxCore)
2646 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
2647
2648 /*
2649 * Are we in Ring-0?
2650 */
2651 if ( pCtxCore->ss.Sel
2652 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
2653 && !pCtxCore->eflags.Bits.u1VM)
2654 {
2655 /*
2656 * Enter execution mode.
2657 */
2658 PATMRawEnter(pVM, pCtxCore);
2659
2660 /*
2661 * Set CPL to Ring-1.
2662 */
2663 pCtxCore->ss.Sel |= 1;
2664 if ( pCtxCore->cs.Sel
2665 && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
2666 pCtxCore->cs.Sel |= 1;
2667 }
2668 else
2669 {
2670# ifdef VBOX_WITH_RAW_RING1
2671 if ( EMIsRawRing1Enabled(pVM)
2672 && !pCtxCore->eflags.Bits.u1VM
2673 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
2674 {
2675 /* Set CPL to Ring-2. */
2676 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
2677 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2678 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
2679 }
2680# else
2681 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
2682 ("ring-1 code not supported\n"));
2683# endif
2684 /*
2685 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
2686 */
2687 PATMRawEnter(pVM, pCtxCore);
2688 }
2689
2690 /*
2691 * Assert sanity.
2692 */
2693 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
2694 AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
2695 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2696 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
2697
2698 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
2699
2700 pVCpu->cpum.s.fRawEntered = true;
2701 return VINF_SUCCESS;
2702}
2703
2704
2705/**
2706 * Transforms the guest CPU state from raw-ring mode to correct values.
2707 *
2708 * This function will change any selector registers with DPL=1 to DPL=0.
2709 *
2710 * @returns Adjusted rc.
2711 * @param pVCpu Pointer to the VMCPU.
2712 * @param rc Raw mode return code
2713 * @param pCtxCore The context core (for trap usage).
2714 * @see @ref pg_raw
2715 */
2716VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
2717{
2718 PVM pVM = pVCpu->CTX_SUFF(pVM);
2719
2720 /*
2721 * Don't leave if we've already left (in RC).
2722 */
2723 Assert(!pVCpu->cpum.s.fRemEntered);
2724 if (!pVCpu->cpum.s.fRawEntered)
2725 return rc;
2726 pVCpu->cpum.s.fRawEntered = false;
2727
2728 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2729 if (!pCtxCore)
2730 pCtxCore = CPUMCTX2CORE(pCtx);
2731 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
2732 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
2733 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2734
2735 /*
2736 * Are we executing in raw ring-1?
2737 */
2738 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
2739 && !pCtxCore->eflags.Bits.u1VM)
2740 {
2741 /*
2742 * Leave execution mode.
2743 */
2744 PATMRawLeave(pVM, pCtxCore, rc);
2745 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2746 /** @todo See what happens if we remove this. */
2747 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2748 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2749 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2750 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2751 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2752 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2753 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2754 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2755
2756 /*
2757 * Ring-1 selector => Ring-0.
2758 */
2759 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
2760 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2761 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
2762 }
2763 else
2764 {
2765 /*
2766 * PATM is taking care of the IOPL and IF flags for us.
2767 */
2768 PATMRawLeave(pVM, pCtxCore, rc);
2769 if (!pCtxCore->eflags.Bits.u1VM)
2770 {
2771# ifdef VBOX_WITH_RAW_RING1
2772 if ( EMIsRawRing1Enabled(pVM)
2773 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 2)
2774 {
2775 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2776 /** @todo See what happens if we remove this. */
2777 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 2)
2778 pCtxCore->ds.Sel = (pCtxCore->ds.Sel & ~X86_SEL_RPL) | 1;
2779 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 2)
2780 pCtxCore->es.Sel = (pCtxCore->es.Sel & ~X86_SEL_RPL) | 1;
2781 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 2)
2782 pCtxCore->fs.Sel = (pCtxCore->fs.Sel & ~X86_SEL_RPL) | 1;
2783 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 2)
2784 pCtxCore->gs.Sel = (pCtxCore->gs.Sel & ~X86_SEL_RPL) | 1;
2785
2786 /*
2787 * Ring-2 selector => Ring-1.
2788 */
2789 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 1;
2790 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 2)
2791 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 1;
2792 }
2793 else
2794 {
2795# endif
2796 /** @todo See what happens if we remove this. */
2797 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2798 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2799 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2800 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2801 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2802 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2803 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2804 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2805# ifdef VBOX_WITH_RAW_RING1
2806 }
2807# endif
2808 }
2809 }
2810
2811 return rc;
2812}
2813
2814#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
2815
2816/**
2817 * Updates the EFLAGS while we're in raw-mode.
2818 *
2819 * @param pVCpu Pointer to the VMCPU.
2820 * @param fEfl The new EFLAGS value.
2821 */
2822VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
2823{
2824#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2825 if (pVCpu->cpum.s.fRawEntered)
2826 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
2827 else
2828#endif
2829 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
2830}
2831
2832
2833/**
2834 * Gets the EFLAGS while we're in raw-mode.
2835 *
2836 * @returns The eflags.
2837 * @param pVCpu Pointer to the current virtual CPU.
2838 */
2839VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
2840{
2841#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2842 if (pVCpu->cpum.s.fRawEntered)
2843 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
2844#endif
2845 return pVCpu->cpum.s.Guest.eflags.u32;
2846}
2847
2848
2849/**
2850 * Sets the specified changed flags (CPUM_CHANGED_*).
2851 *
2852 * @param pVCpu Pointer to the current virtual CPU.
2853 */
2854VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2855{
2856 pVCpu->cpum.s.fChanged |= fChangedFlags;
2857}
2858
2859
2860/**
2861 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2862 * @returns true if supported.
2863 * @returns false if not supported.
2864 * @param pVM Pointer to the VM.
2865 */
2866VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2867{
2868 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2869}
2870
2871
2872/**
2873 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2874 * @returns true if used.
2875 * @returns false if not used.
2876 * @param pVM Pointer to the VM.
2877 */
2878VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2879{
2880 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
2881}
2882
2883
2884/**
2885 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2886 * @returns true if used.
2887 * @returns false if not used.
2888 * @param pVM Pointer to the VM.
2889 */
2890VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2891{
2892 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
2893}
2894
2895#ifndef IN_RING3
2896
2897/**
2898 * Lazily sync in the FPU/XMM state.
2899 *
2900 * @returns VBox status code.
2901 * @param pVCpu Pointer to the VMCPU.
2902 */
2903VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2904{
2905 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2906}
2907
2908#endif /* !IN_RING3 */
2909
2910/**
2911 * Checks if we activated the FPU/XMM state of the guest OS.
2912 * @returns true if we did.
2913 * @returns false if not.
2914 * @param pVCpu Pointer to the VMCPU.
2915 */
2916VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2917{
2918 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU);
2919}
2920
2921
2922/**
2923 * Deactivate the FPU/XMM state of the guest OS.
2924 * @param pVCpu Pointer to the VMCPU.
2925 *
2926 * @todo r=bird: Why is this needed? Looks like a workaround for mishandled
2927 * FPU state management.
2928 */
2929VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2930{
2931 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU));
2932 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2933}
2934
2935
2936/**
2937 * Checks if the guest debug state is active.
2938 *
2939 * @returns boolean
2940 * @param pVM Pointer to the VM.
2941 */
2942VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2943{
2944 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
2945}
2946
2947/**
2948 * Checks if the hyper debug state is active.
2949 *
2950 * @returns boolean
2951 * @param pVM Pointer to the VM.
2952 */
2953VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2954{
2955 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
2956}
2957
2958
2959/**
2960 * Mark the guest's debug state as inactive.
2961 *
2962 * @returns boolean
2963 * @param pVM Pointer to the VM.
2964 * @todo This API doesn't make sense any more.
2965 */
2966VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2967{
2968 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
2969}
2970
2971
2972/**
2973 * Get the current privilege level of the guest.
2974 *
2975 * @returns CPL
2976 * @param pVCpu Pointer to the current virtual CPU.
2977 */
2978VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
2979{
2980 /*
2981 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
2982 *
2983 * Note! We used to check CS.DPL here, assuming it was always equal to
2984 * CPL even if a conforming segment was loaded. But this truned out to
2985 * only apply to older AMD-V. With VT-x we had an ACP2 regression
2986 * during install after a far call to ring 2 with VT-x. Then on newer
2987 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
2988 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
2989 *
2990 * So, forget CS.DPL, always use SS.DPL.
2991 *
2992 * Note! The SS RPL is always equal to the CPL, while the CS RPL
2993 * isn't necessarily equal if the segment is conforming.
2994 * See section 4.11.1 in the AMD manual.
2995 *
2996 * Update: Where the heck does it say CS.RPL can differ from CPL other than
2997 * right after real->prot mode switch and when in V8086 mode? That
2998 * section says the RPL specified in a direct transfere (call, jmp,
2999 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
3000 * it would be impossible for an exception handle or the iret
3001 * instruction to figure out whether SS:ESP are part of the frame
3002 * or not. VBox or qemu bug must've lead to this misconception.
3003 *
3004 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
3005 * selector into SS with an RPL other than the CPL when CPL != 3 and
3006 * we're in 64-bit mode. The intel dev box doesn't allow this, on
3007 * RPL = CPL. Weird.
3008 */
3009 uint32_t uCpl;
3010 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
3011 {
3012 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3013 {
3014 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
3015 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
3016 else
3017 {
3018 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
3019#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3020# ifdef VBOX_WITH_RAW_RING1
3021 if (pVCpu->cpum.s.fRawEntered)
3022 {
3023 if ( uCpl == 2
3024 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)))
3025 uCpl = 1;
3026 else if (uCpl == 1)
3027 uCpl = 0;
3028 }
3029 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
3030# else
3031 if (uCpl == 1)
3032 uCpl = 0;
3033# endif
3034#endif
3035 }
3036 }
3037 else
3038 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
3039 }
3040 else
3041 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
3042 return uCpl;
3043}
3044
3045
3046/**
3047 * Gets the current guest CPU mode.
3048 *
3049 * If paging mode is what you need, check out PGMGetGuestMode().
3050 *
3051 * @returns The CPU mode.
3052 * @param pVCpu Pointer to the VMCPU.
3053 */
3054VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
3055{
3056 CPUMMODE enmMode;
3057 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3058 enmMode = CPUMMODE_REAL;
3059 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3060 enmMode = CPUMMODE_PROTECTED;
3061 else
3062 enmMode = CPUMMODE_LONG;
3063
3064 return enmMode;
3065}
3066
3067
3068/**
3069 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
3070 *
3071 * @returns 16, 32 or 64.
3072 * @param pVCpu The current virtual CPU.
3073 */
3074VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
3075{
3076 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3077 return 16;
3078
3079 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3080 {
3081 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3082 return 16;
3083 }
3084
3085 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3086 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3087 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3088 return 64;
3089
3090 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3091 return 32;
3092
3093 return 16;
3094}
3095
3096
3097VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
3098{
3099 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3100 return DISCPUMODE_16BIT;
3101
3102 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3103 {
3104 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3105 return DISCPUMODE_16BIT;
3106 }
3107
3108 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3109 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3110 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3111 return DISCPUMODE_64BIT;
3112
3113 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3114 return DISCPUMODE_32BIT;
3115
3116 return DISCPUMODE_16BIT;
3117}
3118
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