1 | /* $Id: CPUMAllRegs.cpp 46286 2013-05-27 13:44:19Z vboxsync $ */
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2 | /** @file
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3 | * CPUM - CPU Monitor(/Manager) - Getters and Setters.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2012 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | /*******************************************************************************
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20 | * Header Files *
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21 | *******************************************************************************/
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22 | #define LOG_GROUP LOG_GROUP_CPUM
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23 | #include <VBox/vmm/cpum.h>
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24 | #include <VBox/vmm/patm.h>
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25 | #include <VBox/vmm/dbgf.h>
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26 | #include <VBox/vmm/pdm.h>
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27 | #include <VBox/vmm/pgm.h>
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28 | #include <VBox/vmm/mm.h>
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29 | #include <VBox/vmm/em.h>
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30 | #if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
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31 | # include <VBox/vmm/selm.h>
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32 | #endif
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33 | #include "CPUMInternal.h"
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34 | #include <VBox/vmm/vm.h>
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35 | #include <VBox/err.h>
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36 | #include <VBox/dis.h>
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37 | #include <VBox/log.h>
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38 | #include <VBox/vmm/hm.h>
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39 | #include <VBox/vmm/tm.h>
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40 | #include <iprt/assert.h>
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41 | #include <iprt/asm.h>
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42 | #include <iprt/asm-amd64-x86.h>
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43 | #ifdef IN_RING3
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44 | #include <iprt/thread.h>
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45 | #endif
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46 |
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47 | /** Disable stack frame pointer generation here. */
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48 | #if defined(_MSC_VER) && !defined(DEBUG)
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49 | # pragma optimize("y", off)
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50 | #endif
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51 |
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52 |
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53 | /*******************************************************************************
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54 | * Defined Constants And Macros *
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55 | *******************************************************************************/
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56 | /**
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57 | * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
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58 | *
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59 | * @returns Pointer to the Virtual CPU.
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60 | * @param a_pGuestCtx Pointer to the guest context.
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61 | */
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62 | #define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
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63 |
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64 | /**
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65 | * Lazily loads the hidden parts of a selector register when using raw-mode.
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66 | */
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67 | #if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
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68 | # define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
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69 | do \
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70 | { \
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71 | if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
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72 | cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
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73 | } while (0)
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74 | #else
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75 | # define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
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76 | Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
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77 | #endif
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78 |
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79 |
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80 |
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81 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
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82 |
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83 | /**
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84 | * Does the lazy hidden selector register loading.
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85 | *
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86 | * @param pVCpu The current Virtual CPU.
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87 | * @param pSReg The selector register to lazily load hidden parts of.
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88 | */
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89 | static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
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90 | {
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91 | Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
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92 | Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
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93 | Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
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94 |
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95 | if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
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96 | {
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97 | /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
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98 | pSReg->Attr.u = 0;
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99 | pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
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100 | pSReg->Attr.n.u1DescType = 1; /* code/data segment */
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101 | pSReg->Attr.n.u2Dpl = 3;
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102 | pSReg->Attr.n.u1Present = 1;
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103 | pSReg->u32Limit = 0x0000ffff;
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104 | pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
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105 | pSReg->ValidSel = pSReg->Sel;
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106 | pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
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107 | /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
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108 | }
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109 | else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
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110 | {
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111 | /* Real mode - leave the limit and flags alone here, at least for now. */
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112 | pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
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113 | pSReg->ValidSel = pSReg->Sel;
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114 | pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
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115 | }
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116 | else
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117 | {
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118 | /* Protected mode - get it from the selector descriptor tables. */
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119 | if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
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120 | {
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121 | Assert(!CPUMIsGuestInLongMode(pVCpu));
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122 | pSReg->Sel = 0;
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123 | pSReg->u64Base = 0;
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124 | pSReg->u32Limit = 0;
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125 | pSReg->Attr.u = 0;
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126 | pSReg->ValidSel = 0;
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127 | pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
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128 | /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
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129 | }
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130 | else
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131 | SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
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132 | }
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133 | }
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134 |
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135 |
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136 | /**
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137 | * Makes sure the hidden CS and SS selector registers are valid, loading them if
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138 | * necessary.
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139 | *
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140 | * @param pVCpu The current virtual CPU.
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141 | */
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142 | VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
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143 | {
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144 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
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145 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
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146 | }
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147 |
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148 |
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149 | /**
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150 | * Loads a the hidden parts of a selector register.
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151 | *
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152 | * @param pVCpu The current virtual CPU.
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153 | */
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154 | VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
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155 | {
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156 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
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157 | }
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158 |
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159 | #endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
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160 |
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161 |
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162 | /**
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163 | * Obsolete.
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164 | *
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165 | * We don't support nested hypervisor context interrupts or traps. Life is much
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166 | * simpler when we don't. It's also slightly faster at times.
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167 | *
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168 | * @param pVM Handle to the virtual machine.
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169 | */
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170 | VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
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171 | {
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172 | return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
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173 | }
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174 |
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175 |
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176 | /**
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177 | * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
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178 | *
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179 | * @param pVCpu Pointer to the VMCPU.
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180 | */
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181 | VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
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182 | {
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183 | return &pVCpu->cpum.s.Hyper;
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184 | }
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185 |
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186 |
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187 | VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
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188 | {
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189 | pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
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190 | pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
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191 | }
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192 |
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193 |
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194 | VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
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195 | {
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196 | pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
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197 | pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
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198 | }
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199 |
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200 |
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201 | VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
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202 | {
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203 | pVCpu->cpum.s.Hyper.cr3 = cr3;
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204 |
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205 | #ifdef IN_RC
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206 | /* Update the current CR3. */
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207 | ASMSetCR3(cr3);
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208 | #endif
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209 | }
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210 |
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211 | VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
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212 | {
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213 | return pVCpu->cpum.s.Hyper.cr3;
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214 | }
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215 |
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216 |
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217 | VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
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218 | {
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219 | pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
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220 | }
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221 |
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222 |
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223 | VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
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224 | {
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225 | pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
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226 | }
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227 |
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228 |
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229 | VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
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230 | {
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231 | pVCpu->cpum.s.Hyper.es.Sel = SelES;
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232 | }
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233 |
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234 |
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235 | VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
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236 | {
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237 | pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
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238 | }
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239 |
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240 |
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241 | VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
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242 | {
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243 | pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
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244 | }
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245 |
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246 |
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247 | VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
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248 | {
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249 | pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
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250 | }
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251 |
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252 |
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253 | VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
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254 | {
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255 | pVCpu->cpum.s.Hyper.esp = u32ESP;
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256 | }
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257 |
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258 |
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259 | VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
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260 | {
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261 | pVCpu->cpum.s.Hyper.esp = u32ESP;
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262 | }
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263 |
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264 |
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265 | VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
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266 | {
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267 | pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
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268 | return VINF_SUCCESS;
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269 | }
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270 |
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271 |
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272 | VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
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273 | {
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274 | pVCpu->cpum.s.Hyper.eip = u32EIP;
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275 | }
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276 |
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277 |
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278 | /**
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279 | * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
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280 | * EFLAGS and EIP prior to resuming guest execution.
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281 | *
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282 | * All general register not given as a parameter will be set to 0. The EFLAGS
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283 | * register will be set to sane values for C/C++ code execution with interrupts
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284 | * disabled and IOPL 0.
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285 | *
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286 | * @param pVCpu The current virtual CPU.
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287 | * @param u32EIP The EIP value.
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288 | * @param u32ESP The ESP value.
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289 | * @param u32EAX The EAX value.
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290 | * @param u32EDX The EDX value.
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291 | */
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292 | VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
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293 | {
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294 | pVCpu->cpum.s.Hyper.eip = u32EIP;
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295 | pVCpu->cpum.s.Hyper.esp = u32ESP;
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296 | pVCpu->cpum.s.Hyper.eax = u32EAX;
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297 | pVCpu->cpum.s.Hyper.edx = u32EDX;
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298 | pVCpu->cpum.s.Hyper.ecx = 0;
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299 | pVCpu->cpum.s.Hyper.ebx = 0;
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300 | pVCpu->cpum.s.Hyper.ebp = 0;
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301 | pVCpu->cpum.s.Hyper.esi = 0;
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302 | pVCpu->cpum.s.Hyper.edi = 0;
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303 | pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
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304 | }
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305 |
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306 |
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307 | VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
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308 | {
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309 | pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
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310 | }
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311 |
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312 |
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313 | VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
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314 | {
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315 | pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
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316 | }
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317 |
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318 |
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319 | VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
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320 | {
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321 | pVCpu->cpum.s.Hyper.dr[0] = uDr0;
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322 | /** @todo in GC we must load it! */
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323 | }
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324 |
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325 |
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326 | VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
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327 | {
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328 | pVCpu->cpum.s.Hyper.dr[1] = uDr1;
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329 | /** @todo in GC we must load it! */
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330 | }
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331 |
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332 |
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333 | VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
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334 | {
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335 | pVCpu->cpum.s.Hyper.dr[2] = uDr2;
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336 | /** @todo in GC we must load it! */
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337 | }
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338 |
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339 |
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340 | VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
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341 | {
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342 | pVCpu->cpum.s.Hyper.dr[3] = uDr3;
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343 | /** @todo in GC we must load it! */
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344 | }
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345 |
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346 |
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347 | VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
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348 | {
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349 | pVCpu->cpum.s.Hyper.dr[6] = uDr6;
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350 | /** @todo in GC we must load it! */
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351 | }
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352 |
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353 |
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354 | VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
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355 | {
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356 | pVCpu->cpum.s.Hyper.dr[7] = uDr7;
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357 | /** @todo in GC we must load it! */
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358 | }
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359 |
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360 |
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361 | VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
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362 | {
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363 | return pVCpu->cpum.s.Hyper.cs.Sel;
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364 | }
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365 |
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366 |
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367 | VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
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368 | {
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369 | return pVCpu->cpum.s.Hyper.ds.Sel;
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370 | }
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371 |
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372 |
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373 | VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
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374 | {
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375 | return pVCpu->cpum.s.Hyper.es.Sel;
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376 | }
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377 |
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378 |
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379 | VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
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380 | {
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381 | return pVCpu->cpum.s.Hyper.fs.Sel;
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382 | }
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383 |
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384 |
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385 | VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
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386 | {
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387 | return pVCpu->cpum.s.Hyper.gs.Sel;
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388 | }
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389 |
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390 |
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391 | VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
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392 | {
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393 | return pVCpu->cpum.s.Hyper.ss.Sel;
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394 | }
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395 |
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396 |
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397 | VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
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398 | {
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399 | return pVCpu->cpum.s.Hyper.eax;
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400 | }
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401 |
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402 |
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403 | VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
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404 | {
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405 | return pVCpu->cpum.s.Hyper.ebx;
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406 | }
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407 |
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408 |
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409 | VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
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410 | {
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411 | return pVCpu->cpum.s.Hyper.ecx;
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412 | }
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413 |
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414 |
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415 | VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
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416 | {
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417 | return pVCpu->cpum.s.Hyper.edx;
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418 | }
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419 |
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420 |
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421 | VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
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422 | {
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423 | return pVCpu->cpum.s.Hyper.esi;
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424 | }
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425 |
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426 |
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427 | VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
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428 | {
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429 | return pVCpu->cpum.s.Hyper.edi;
|
---|
430 | }
|
---|
431 |
|
---|
432 |
|
---|
433 | VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
|
---|
434 | {
|
---|
435 | return pVCpu->cpum.s.Hyper.ebp;
|
---|
436 | }
|
---|
437 |
|
---|
438 |
|
---|
439 | VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
|
---|
440 | {
|
---|
441 | return pVCpu->cpum.s.Hyper.esp;
|
---|
442 | }
|
---|
443 |
|
---|
444 |
|
---|
445 | VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
|
---|
446 | {
|
---|
447 | return pVCpu->cpum.s.Hyper.eflags.u32;
|
---|
448 | }
|
---|
449 |
|
---|
450 |
|
---|
451 | VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
|
---|
452 | {
|
---|
453 | return pVCpu->cpum.s.Hyper.eip;
|
---|
454 | }
|
---|
455 |
|
---|
456 |
|
---|
457 | VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
|
---|
458 | {
|
---|
459 | return pVCpu->cpum.s.Hyper.rip;
|
---|
460 | }
|
---|
461 |
|
---|
462 |
|
---|
463 | VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
|
---|
464 | {
|
---|
465 | if (pcbLimit)
|
---|
466 | *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
|
---|
467 | return pVCpu->cpum.s.Hyper.idtr.pIdt;
|
---|
468 | }
|
---|
469 |
|
---|
470 |
|
---|
471 | VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
|
---|
472 | {
|
---|
473 | if (pcbLimit)
|
---|
474 | *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
|
---|
475 | return pVCpu->cpum.s.Hyper.gdtr.pGdt;
|
---|
476 | }
|
---|
477 |
|
---|
478 |
|
---|
479 | VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
|
---|
480 | {
|
---|
481 | return pVCpu->cpum.s.Hyper.ldtr.Sel;
|
---|
482 | }
|
---|
483 |
|
---|
484 |
|
---|
485 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
|
---|
486 | {
|
---|
487 | return pVCpu->cpum.s.Hyper.dr[0];
|
---|
488 | }
|
---|
489 |
|
---|
490 |
|
---|
491 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
|
---|
492 | {
|
---|
493 | return pVCpu->cpum.s.Hyper.dr[1];
|
---|
494 | }
|
---|
495 |
|
---|
496 |
|
---|
497 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
|
---|
498 | {
|
---|
499 | return pVCpu->cpum.s.Hyper.dr[2];
|
---|
500 | }
|
---|
501 |
|
---|
502 |
|
---|
503 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
|
---|
504 | {
|
---|
505 | return pVCpu->cpum.s.Hyper.dr[3];
|
---|
506 | }
|
---|
507 |
|
---|
508 |
|
---|
509 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
|
---|
510 | {
|
---|
511 | return pVCpu->cpum.s.Hyper.dr[6];
|
---|
512 | }
|
---|
513 |
|
---|
514 |
|
---|
515 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
|
---|
516 | {
|
---|
517 | return pVCpu->cpum.s.Hyper.dr[7];
|
---|
518 | }
|
---|
519 |
|
---|
520 |
|
---|
521 | /**
|
---|
522 | * Gets the pointer to the internal CPUMCTXCORE structure.
|
---|
523 | * This is only for reading in order to save a few calls.
|
---|
524 | *
|
---|
525 | * @param pVCpu Handle to the virtual cpu.
|
---|
526 | */
|
---|
527 | VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
|
---|
528 | {
|
---|
529 | return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
|
---|
530 | }
|
---|
531 |
|
---|
532 |
|
---|
533 | /**
|
---|
534 | * Queries the pointer to the internal CPUMCTX structure.
|
---|
535 | *
|
---|
536 | * @returns The CPUMCTX pointer.
|
---|
537 | * @param pVCpu Handle to the virtual cpu.
|
---|
538 | */
|
---|
539 | VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
|
---|
540 | {
|
---|
541 | return &pVCpu->cpum.s.Guest;
|
---|
542 | }
|
---|
543 |
|
---|
544 | VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
|
---|
545 | {
|
---|
546 | #ifdef VBOX_WITH_IEM
|
---|
547 | # ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
548 | if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
|
---|
549 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
|
---|
550 | # endif
|
---|
551 | #endif
|
---|
552 | pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
|
---|
553 | pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
|
---|
554 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
|
---|
555 | return VINF_SUCCESS; /* formality, consider it void. */
|
---|
556 | }
|
---|
557 |
|
---|
558 | VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
|
---|
559 | {
|
---|
560 | #ifdef VBOX_WITH_IEM
|
---|
561 | # ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
562 | if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
|
---|
563 | VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
|
---|
564 | # endif
|
---|
565 | #endif
|
---|
566 | pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
|
---|
567 | pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
|
---|
568 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
|
---|
569 | return VINF_SUCCESS; /* formality, consider it void. */
|
---|
570 | }
|
---|
571 |
|
---|
572 | VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
|
---|
573 | {
|
---|
574 | #ifdef VBOX_WITH_IEM
|
---|
575 | # ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
576 | if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
|
---|
577 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
578 | # endif
|
---|
579 | #endif
|
---|
580 | pVCpu->cpum.s.Guest.tr.Sel = tr;
|
---|
581 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
|
---|
582 | return VINF_SUCCESS; /* formality, consider it void. */
|
---|
583 | }
|
---|
584 |
|
---|
585 | VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
|
---|
586 | {
|
---|
587 | #ifdef VBOX_WITH_IEM
|
---|
588 | # ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
589 | if ( ( ldtr != 0
|
---|
590 | || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
|
---|
591 | && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
|
---|
592 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
593 | # endif
|
---|
594 | #endif
|
---|
595 | pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
|
---|
596 | /* The caller will set more hidden bits if it has them. */
|
---|
597 | pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
|
---|
598 | pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
|
---|
599 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
|
---|
600 | return VINF_SUCCESS; /* formality, consider it void. */
|
---|
601 | }
|
---|
602 |
|
---|
603 |
|
---|
604 | /**
|
---|
605 | * Set the guest CR0.
|
---|
606 | *
|
---|
607 | * When called in GC, the hyper CR0 may be updated if that is
|
---|
608 | * required. The caller only has to take special action if AM,
|
---|
609 | * WP, PG or PE changes.
|
---|
610 | *
|
---|
611 | * @returns VINF_SUCCESS (consider it void).
|
---|
612 | * @param pVCpu Handle to the virtual cpu.
|
---|
613 | * @param cr0 The new CR0 value.
|
---|
614 | */
|
---|
615 | VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
|
---|
616 | {
|
---|
617 | #ifdef IN_RC
|
---|
618 | /*
|
---|
619 | * Check if we need to change hypervisor CR0 because
|
---|
620 | * of math stuff.
|
---|
621 | */
|
---|
622 | if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
|
---|
623 | != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
|
---|
624 | {
|
---|
625 | if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
|
---|
626 | {
|
---|
627 | /*
|
---|
628 | * We haven't saved the host FPU state yet, so TS and MT are both set
|
---|
629 | * and EM should be reflecting the guest EM (it always does this).
|
---|
630 | */
|
---|
631 | if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
|
---|
632 | {
|
---|
633 | uint32_t HyperCR0 = ASMGetCR0();
|
---|
634 | AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
|
---|
635 | AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
|
---|
636 | HyperCR0 &= ~X86_CR0_EM;
|
---|
637 | HyperCR0 |= cr0 & X86_CR0_EM;
|
---|
638 | Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
|
---|
639 | ASMSetCR0(HyperCR0);
|
---|
640 | }
|
---|
641 | # ifdef VBOX_STRICT
|
---|
642 | else
|
---|
643 | {
|
---|
644 | uint32_t HyperCR0 = ASMGetCR0();
|
---|
645 | AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
|
---|
646 | AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
|
---|
647 | }
|
---|
648 | # endif
|
---|
649 | }
|
---|
650 | else
|
---|
651 | {
|
---|
652 | /*
|
---|
653 | * Already saved the state, so we're just mirroring
|
---|
654 | * the guest flags.
|
---|
655 | */
|
---|
656 | uint32_t HyperCR0 = ASMGetCR0();
|
---|
657 | AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
|
---|
658 | == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
|
---|
659 | ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
|
---|
660 | HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
|
---|
661 | HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
|
---|
662 | Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
|
---|
663 | ASMSetCR0(HyperCR0);
|
---|
664 | }
|
---|
665 | }
|
---|
666 | #endif /* IN_RC */
|
---|
667 |
|
---|
668 | /*
|
---|
669 | * Check for changes causing TLB flushes (for REM).
|
---|
670 | * The caller is responsible for calling PGM when appropriate.
|
---|
671 | */
|
---|
672 | if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
|
---|
673 | != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
|
---|
674 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
|
---|
675 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
|
---|
676 |
|
---|
677 | /*
|
---|
678 | * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
|
---|
679 | */
|
---|
680 | if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
|
---|
681 | PGMCr0WpEnabled(pVCpu);
|
---|
682 |
|
---|
683 | pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
|
---|
684 | return VINF_SUCCESS;
|
---|
685 | }
|
---|
686 |
|
---|
687 |
|
---|
688 | VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
|
---|
689 | {
|
---|
690 | pVCpu->cpum.s.Guest.cr2 = cr2;
|
---|
691 | return VINF_SUCCESS;
|
---|
692 | }
|
---|
693 |
|
---|
694 |
|
---|
695 | VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
|
---|
696 | {
|
---|
697 | pVCpu->cpum.s.Guest.cr3 = cr3;
|
---|
698 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
|
---|
699 | return VINF_SUCCESS;
|
---|
700 | }
|
---|
701 |
|
---|
702 |
|
---|
703 | VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
|
---|
704 | {
|
---|
705 | if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
|
---|
706 | != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
|
---|
707 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
|
---|
708 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
|
---|
709 | if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
|
---|
710 | cr4 &= ~X86_CR4_OSFSXR;
|
---|
711 | pVCpu->cpum.s.Guest.cr4 = cr4;
|
---|
712 | return VINF_SUCCESS;
|
---|
713 | }
|
---|
714 |
|
---|
715 |
|
---|
716 | VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
|
---|
717 | {
|
---|
718 | pVCpu->cpum.s.Guest.eflags.u32 = eflags;
|
---|
719 | return VINF_SUCCESS;
|
---|
720 | }
|
---|
721 |
|
---|
722 |
|
---|
723 | VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
|
---|
724 | {
|
---|
725 | pVCpu->cpum.s.Guest.eip = eip;
|
---|
726 | return VINF_SUCCESS;
|
---|
727 | }
|
---|
728 |
|
---|
729 |
|
---|
730 | VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
|
---|
731 | {
|
---|
732 | pVCpu->cpum.s.Guest.eax = eax;
|
---|
733 | return VINF_SUCCESS;
|
---|
734 | }
|
---|
735 |
|
---|
736 |
|
---|
737 | VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
|
---|
738 | {
|
---|
739 | pVCpu->cpum.s.Guest.ebx = ebx;
|
---|
740 | return VINF_SUCCESS;
|
---|
741 | }
|
---|
742 |
|
---|
743 |
|
---|
744 | VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
|
---|
745 | {
|
---|
746 | pVCpu->cpum.s.Guest.ecx = ecx;
|
---|
747 | return VINF_SUCCESS;
|
---|
748 | }
|
---|
749 |
|
---|
750 |
|
---|
751 | VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
|
---|
752 | {
|
---|
753 | pVCpu->cpum.s.Guest.edx = edx;
|
---|
754 | return VINF_SUCCESS;
|
---|
755 | }
|
---|
756 |
|
---|
757 |
|
---|
758 | VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
|
---|
759 | {
|
---|
760 | pVCpu->cpum.s.Guest.esp = esp;
|
---|
761 | return VINF_SUCCESS;
|
---|
762 | }
|
---|
763 |
|
---|
764 |
|
---|
765 | VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
|
---|
766 | {
|
---|
767 | pVCpu->cpum.s.Guest.ebp = ebp;
|
---|
768 | return VINF_SUCCESS;
|
---|
769 | }
|
---|
770 |
|
---|
771 |
|
---|
772 | VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
|
---|
773 | {
|
---|
774 | pVCpu->cpum.s.Guest.esi = esi;
|
---|
775 | return VINF_SUCCESS;
|
---|
776 | }
|
---|
777 |
|
---|
778 |
|
---|
779 | VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
|
---|
780 | {
|
---|
781 | pVCpu->cpum.s.Guest.edi = edi;
|
---|
782 | return VINF_SUCCESS;
|
---|
783 | }
|
---|
784 |
|
---|
785 |
|
---|
786 | VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
|
---|
787 | {
|
---|
788 | pVCpu->cpum.s.Guest.ss.Sel = ss;
|
---|
789 | return VINF_SUCCESS;
|
---|
790 | }
|
---|
791 |
|
---|
792 |
|
---|
793 | VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
|
---|
794 | {
|
---|
795 | pVCpu->cpum.s.Guest.cs.Sel = cs;
|
---|
796 | return VINF_SUCCESS;
|
---|
797 | }
|
---|
798 |
|
---|
799 |
|
---|
800 | VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
|
---|
801 | {
|
---|
802 | pVCpu->cpum.s.Guest.ds.Sel = ds;
|
---|
803 | return VINF_SUCCESS;
|
---|
804 | }
|
---|
805 |
|
---|
806 |
|
---|
807 | VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
|
---|
808 | {
|
---|
809 | pVCpu->cpum.s.Guest.es.Sel = es;
|
---|
810 | return VINF_SUCCESS;
|
---|
811 | }
|
---|
812 |
|
---|
813 |
|
---|
814 | VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
|
---|
815 | {
|
---|
816 | pVCpu->cpum.s.Guest.fs.Sel = fs;
|
---|
817 | return VINF_SUCCESS;
|
---|
818 | }
|
---|
819 |
|
---|
820 |
|
---|
821 | VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
|
---|
822 | {
|
---|
823 | pVCpu->cpum.s.Guest.gs.Sel = gs;
|
---|
824 | return VINF_SUCCESS;
|
---|
825 | }
|
---|
826 |
|
---|
827 |
|
---|
828 | VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
|
---|
829 | {
|
---|
830 | pVCpu->cpum.s.Guest.msrEFER = val;
|
---|
831 | }
|
---|
832 |
|
---|
833 |
|
---|
834 | /**
|
---|
835 | * Query an MSR.
|
---|
836 | *
|
---|
837 | * The caller is responsible for checking privilege if the call is the result
|
---|
838 | * of a RDMSR instruction. We'll do the rest.
|
---|
839 | *
|
---|
840 | * @retval VINF_SUCCESS on success.
|
---|
841 | * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
|
---|
842 | * expected to take the appropriate actions. @a *puValue is set to 0.
|
---|
843 | * @param pVCpu Pointer to the VMCPU.
|
---|
844 | * @param idMsr The MSR.
|
---|
845 | * @param puValue Where to return the value.
|
---|
846 | *
|
---|
847 | * @remarks This will always return the right values, even when we're in the
|
---|
848 | * recompiler.
|
---|
849 | */
|
---|
850 | VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
|
---|
851 | {
|
---|
852 | /*
|
---|
853 | * If we don't indicate MSR support in the CPUID feature bits, indicate
|
---|
854 | * that a #GP(0) should be raised.
|
---|
855 | */
|
---|
856 | if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
|
---|
857 | {
|
---|
858 | *puValue = 0;
|
---|
859 | return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
|
---|
860 | }
|
---|
861 |
|
---|
862 | int rc = VINF_SUCCESS;
|
---|
863 | uint8_t const u8Multiplier = 4;
|
---|
864 | switch (idMsr)
|
---|
865 | {
|
---|
866 | case MSR_IA32_TSC:
|
---|
867 | *puValue = TMCpuTickGet(pVCpu);
|
---|
868 | break;
|
---|
869 |
|
---|
870 | case MSR_IA32_APICBASE:
|
---|
871 | {
|
---|
872 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
873 | if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
|
---|
874 | && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
|
---|
875 | || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
|
---|
876 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
|
---|
877 | && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
|
---|
878 | || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
|
---|
879 | && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
|
---|
880 | {
|
---|
881 | *puValue = pVCpu->cpum.s.Guest.msrApicBase;
|
---|
882 | }
|
---|
883 | else
|
---|
884 | {
|
---|
885 | *puValue = 0;
|
---|
886 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
887 | }
|
---|
888 | break;
|
---|
889 | }
|
---|
890 |
|
---|
891 | case MSR_IA32_CR_PAT:
|
---|
892 | *puValue = pVCpu->cpum.s.Guest.msrPAT;
|
---|
893 | break;
|
---|
894 |
|
---|
895 | case MSR_IA32_SYSENTER_CS:
|
---|
896 | *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
|
---|
897 | break;
|
---|
898 |
|
---|
899 | case MSR_IA32_SYSENTER_EIP:
|
---|
900 | *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
|
---|
901 | break;
|
---|
902 |
|
---|
903 | case MSR_IA32_SYSENTER_ESP:
|
---|
904 | *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
|
---|
905 | break;
|
---|
906 |
|
---|
907 | case MSR_IA32_MTRR_CAP:
|
---|
908 | {
|
---|
909 | /* This is currently a bit weird. :-) */
|
---|
910 | uint8_t const cVariableRangeRegs = 0;
|
---|
911 | bool const fSystemManagementRangeRegisters = false;
|
---|
912 | bool const fFixedRangeRegisters = false;
|
---|
913 | bool const fWriteCombiningType = false;
|
---|
914 | *puValue = cVariableRangeRegs
|
---|
915 | | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
|
---|
916 | | (fWriteCombiningType ? RT_BIT_64(10) : 0)
|
---|
917 | | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
|
---|
918 | break;
|
---|
919 | }
|
---|
920 |
|
---|
921 | case MSR_IA32_MTRR_DEF_TYPE:
|
---|
922 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
|
---|
923 | break;
|
---|
924 |
|
---|
925 | case IA32_MTRR_FIX64K_00000:
|
---|
926 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
|
---|
927 | break;
|
---|
928 | case IA32_MTRR_FIX16K_80000:
|
---|
929 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
|
---|
930 | break;
|
---|
931 | case IA32_MTRR_FIX16K_A0000:
|
---|
932 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
|
---|
933 | break;
|
---|
934 | case IA32_MTRR_FIX4K_C0000:
|
---|
935 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
|
---|
936 | break;
|
---|
937 | case IA32_MTRR_FIX4K_C8000:
|
---|
938 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
|
---|
939 | break;
|
---|
940 | case IA32_MTRR_FIX4K_D0000:
|
---|
941 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
|
---|
942 | break;
|
---|
943 | case IA32_MTRR_FIX4K_D8000:
|
---|
944 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
|
---|
945 | break;
|
---|
946 | case IA32_MTRR_FIX4K_E0000:
|
---|
947 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
|
---|
948 | break;
|
---|
949 | case IA32_MTRR_FIX4K_E8000:
|
---|
950 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
|
---|
951 | break;
|
---|
952 | case IA32_MTRR_FIX4K_F0000:
|
---|
953 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
|
---|
954 | break;
|
---|
955 | case IA32_MTRR_FIX4K_F8000:
|
---|
956 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
|
---|
957 | break;
|
---|
958 |
|
---|
959 | case MSR_K6_EFER:
|
---|
960 | *puValue = pVCpu->cpum.s.Guest.msrEFER;
|
---|
961 | break;
|
---|
962 |
|
---|
963 | case MSR_K8_SF_MASK:
|
---|
964 | *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
|
---|
965 | break;
|
---|
966 |
|
---|
967 | case MSR_K6_STAR:
|
---|
968 | *puValue = pVCpu->cpum.s.Guest.msrSTAR;
|
---|
969 | break;
|
---|
970 |
|
---|
971 | case MSR_K8_LSTAR:
|
---|
972 | *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
|
---|
973 | break;
|
---|
974 |
|
---|
975 | case MSR_K8_CSTAR:
|
---|
976 | *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
|
---|
977 | break;
|
---|
978 |
|
---|
979 | case MSR_K8_FS_BASE:
|
---|
980 | *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
|
---|
981 | break;
|
---|
982 |
|
---|
983 | case MSR_K8_GS_BASE:
|
---|
984 | *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
|
---|
985 | break;
|
---|
986 |
|
---|
987 | case MSR_K8_KERNEL_GS_BASE:
|
---|
988 | *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
|
---|
989 | break;
|
---|
990 |
|
---|
991 | case MSR_K8_TSC_AUX:
|
---|
992 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
|
---|
993 | break;
|
---|
994 |
|
---|
995 | case MSR_IA32_PERF_STATUS:
|
---|
996 | /** @todo could really be not exactly correct, maybe use host's values */
|
---|
997 | *puValue = UINT64_C(1000) /* TSC increment by tick */
|
---|
998 | | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
|
---|
999 | | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
|
---|
1000 | break;
|
---|
1001 |
|
---|
1002 | case MSR_IA32_FSB_CLOCK_STS:
|
---|
1003 | /*
|
---|
1004 | * Encoded as:
|
---|
1005 | * 0 - 266
|
---|
1006 | * 1 - 133
|
---|
1007 | * 2 - 200
|
---|
1008 | * 3 - return 166
|
---|
1009 | * 5 - return 100
|
---|
1010 | */
|
---|
1011 | *puValue = (2 << 4);
|
---|
1012 | break;
|
---|
1013 |
|
---|
1014 | case MSR_IA32_PLATFORM_INFO:
|
---|
1015 | *puValue = (u8Multiplier << 8) /* Flex ratio max */
|
---|
1016 | | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
|
---|
1017 | break;
|
---|
1018 |
|
---|
1019 | case MSR_IA32_THERM_STATUS:
|
---|
1020 | /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
|
---|
1021 | *puValue = RT_BIT(31) /* validity bit */
|
---|
1022 | | (UINT64_C(20) << 16) /* degrees till TCC */;
|
---|
1023 | break;
|
---|
1024 |
|
---|
1025 | case MSR_IA32_MISC_ENABLE:
|
---|
1026 | #if 0
|
---|
1027 | /* Needs to be tested more before enabling. */
|
---|
1028 | *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
|
---|
1029 | #else
|
---|
1030 | /* Currenty we don't allow guests to modify enable MSRs. */
|
---|
1031 | *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
|
---|
1032 |
|
---|
1033 | if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
|
---|
1034 |
|
---|
1035 | *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
|
---|
1036 | /** @todo: add more cpuid-controlled features this way. */
|
---|
1037 | #endif
|
---|
1038 | break;
|
---|
1039 |
|
---|
1040 | #if 0 /*def IN_RING0 */
|
---|
1041 | case MSR_IA32_PLATFORM_ID:
|
---|
1042 | case MSR_IA32_BIOS_SIGN_ID:
|
---|
1043 | if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
|
---|
1044 | {
|
---|
1045 | /* Available since the P6 family. VT-x implies that this feature is present. */
|
---|
1046 | if (idMsr == MSR_IA32_PLATFORM_ID)
|
---|
1047 | *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
|
---|
1048 | else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
|
---|
1049 | *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
|
---|
1050 | break;
|
---|
1051 | }
|
---|
1052 | /* no break */
|
---|
1053 | #endif
|
---|
1054 |
|
---|
1055 | /*
|
---|
1056 | * Intel specifics MSRs:
|
---|
1057 | */
|
---|
1058 | case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
|
---|
1059 | case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
|
---|
1060 | /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
|
---|
1061 | case MSR_IA32_MCP_CAP: /* fam/mod >= 6_01 */
|
---|
1062 | /*case MSR_IA32_MCP_STATUS: - indicated as not present in CAP */
|
---|
1063 | /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
|
---|
1064 | case MSR_IA32_MC0_CTL:
|
---|
1065 | case MSR_IA32_MC0_STATUS:
|
---|
1066 | *puValue = 0;
|
---|
1067 | if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
|
---|
1068 | {
|
---|
1069 | Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
|
---|
1070 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
1071 | }
|
---|
1072 | break;
|
---|
1073 |
|
---|
1074 | default:
|
---|
1075 | /*
|
---|
1076 | * Hand the X2APIC range to PDM and the APIC.
|
---|
1077 | */
|
---|
1078 | if ( idMsr >= MSR_IA32_X2APIC_START
|
---|
1079 | && idMsr <= MSR_IA32_X2APIC_END)
|
---|
1080 | {
|
---|
1081 | rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
|
---|
1082 | if (RT_SUCCESS(rc))
|
---|
1083 | rc = VINF_SUCCESS;
|
---|
1084 | else
|
---|
1085 | {
|
---|
1086 | *puValue = 0;
|
---|
1087 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
1088 | }
|
---|
1089 | }
|
---|
1090 | else
|
---|
1091 | {
|
---|
1092 | *puValue = 0;
|
---|
1093 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
1094 | }
|
---|
1095 | break;
|
---|
1096 | }
|
---|
1097 |
|
---|
1098 | return rc;
|
---|
1099 | }
|
---|
1100 |
|
---|
1101 |
|
---|
1102 | /**
|
---|
1103 | * Sets the MSR.
|
---|
1104 | *
|
---|
1105 | * The caller is responsible for checking privilege if the call is the result
|
---|
1106 | * of a WRMSR instruction. We'll do the rest.
|
---|
1107 | *
|
---|
1108 | * @retval VINF_SUCCESS on success.
|
---|
1109 | * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
|
---|
1110 | * appropriate actions.
|
---|
1111 | *
|
---|
1112 | * @param pVCpu Pointer to the VMCPU.
|
---|
1113 | * @param idMsr The MSR id.
|
---|
1114 | * @param uValue The value to set.
|
---|
1115 | *
|
---|
1116 | * @remarks Everyone changing MSR values, including the recompiler, shall do it
|
---|
1117 | * by calling this method. This makes sure we have current values and
|
---|
1118 | * that we trigger all the right actions when something changes.
|
---|
1119 | */
|
---|
1120 | VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
|
---|
1121 | {
|
---|
1122 | /*
|
---|
1123 | * If we don't indicate MSR support in the CPUID feature bits, indicate
|
---|
1124 | * that a #GP(0) should be raised.
|
---|
1125 | */
|
---|
1126 | if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
|
---|
1127 | return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
|
---|
1128 |
|
---|
1129 | int rc = VINF_SUCCESS;
|
---|
1130 | switch (idMsr)
|
---|
1131 | {
|
---|
1132 | case MSR_IA32_MISC_ENABLE:
|
---|
1133 | pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
|
---|
1134 | break;
|
---|
1135 |
|
---|
1136 | case MSR_IA32_TSC:
|
---|
1137 | TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
|
---|
1138 | break;
|
---|
1139 |
|
---|
1140 | case MSR_IA32_APICBASE:
|
---|
1141 | rc = PDMApicSetBase(pVCpu, uValue);
|
---|
1142 | if (rc != VINF_SUCCESS)
|
---|
1143 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
1144 | break;
|
---|
1145 |
|
---|
1146 | case MSR_IA32_CR_PAT:
|
---|
1147 | pVCpu->cpum.s.Guest.msrPAT = uValue;
|
---|
1148 | break;
|
---|
1149 |
|
---|
1150 | case MSR_IA32_SYSENTER_CS:
|
---|
1151 | pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
|
---|
1152 | break;
|
---|
1153 |
|
---|
1154 | case MSR_IA32_SYSENTER_EIP:
|
---|
1155 | pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
|
---|
1156 | break;
|
---|
1157 |
|
---|
1158 | case MSR_IA32_SYSENTER_ESP:
|
---|
1159 | pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
|
---|
1160 | break;
|
---|
1161 |
|
---|
1162 | case MSR_IA32_MTRR_CAP:
|
---|
1163 | return VERR_CPUM_RAISE_GP_0;
|
---|
1164 |
|
---|
1165 | case MSR_IA32_MTRR_DEF_TYPE:
|
---|
1166 | if ( (uValue & UINT64_C(0xfffffffffffff300))
|
---|
1167 | || ( (uValue & 0xff) != 0
|
---|
1168 | && (uValue & 0xff) != 1
|
---|
1169 | && (uValue & 0xff) != 4
|
---|
1170 | && (uValue & 0xff) != 5
|
---|
1171 | && (uValue & 0xff) != 6) )
|
---|
1172 | {
|
---|
1173 | Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
|
---|
1174 | return VERR_CPUM_RAISE_GP_0;
|
---|
1175 | }
|
---|
1176 | pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
|
---|
1177 | break;
|
---|
1178 |
|
---|
1179 | case IA32_MTRR_FIX64K_00000:
|
---|
1180 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
|
---|
1181 | break;
|
---|
1182 | case IA32_MTRR_FIX16K_80000:
|
---|
1183 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
|
---|
1184 | break;
|
---|
1185 | case IA32_MTRR_FIX16K_A0000:
|
---|
1186 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
|
---|
1187 | break;
|
---|
1188 | case IA32_MTRR_FIX4K_C0000:
|
---|
1189 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
|
---|
1190 | break;
|
---|
1191 | case IA32_MTRR_FIX4K_C8000:
|
---|
1192 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
|
---|
1193 | break;
|
---|
1194 | case IA32_MTRR_FIX4K_D0000:
|
---|
1195 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
|
---|
1196 | break;
|
---|
1197 | case IA32_MTRR_FIX4K_D8000:
|
---|
1198 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
|
---|
1199 | break;
|
---|
1200 | case IA32_MTRR_FIX4K_E0000:
|
---|
1201 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
|
---|
1202 | break;
|
---|
1203 | case IA32_MTRR_FIX4K_E8000:
|
---|
1204 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
|
---|
1205 | break;
|
---|
1206 | case IA32_MTRR_FIX4K_F0000:
|
---|
1207 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
|
---|
1208 | break;
|
---|
1209 | case IA32_MTRR_FIX4K_F8000:
|
---|
1210 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
|
---|
1211 | break;
|
---|
1212 |
|
---|
1213 | /*
|
---|
1214 | * AMD64 MSRs.
|
---|
1215 | */
|
---|
1216 | case MSR_K6_EFER:
|
---|
1217 | {
|
---|
1218 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
1219 | uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
|
---|
1220 | uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
1221 | ? pVM->cpum.s.aGuestCpuIdExt[1].edx
|
---|
1222 | : 0;
|
---|
1223 | uint64_t fMask = 0;
|
---|
1224 |
|
---|
1225 | /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
|
---|
1226 | if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
|
---|
1227 | fMask |= MSR_K6_EFER_NXE;
|
---|
1228 | if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
|
---|
1229 | fMask |= MSR_K6_EFER_LME;
|
---|
1230 | if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
|
---|
1231 | fMask |= MSR_K6_EFER_SCE;
|
---|
1232 | if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
|
---|
1233 | fMask |= MSR_K6_EFER_FFXSR;
|
---|
1234 |
|
---|
1235 | /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
|
---|
1236 | paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
|
---|
1237 | if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
|
---|
1238 | && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
|
---|
1239 | {
|
---|
1240 | Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
|
---|
1241 | return VERR_CPUM_RAISE_GP_0;
|
---|
1242 | }
|
---|
1243 |
|
---|
1244 | /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
|
---|
1245 | AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
|
---|
1246 | ("Unexpected value %RX64\n", uValue));
|
---|
1247 | pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
|
---|
1248 |
|
---|
1249 | /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
|
---|
1250 | if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
|
---|
1251 | if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
|
---|
1252 | != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
|
---|
1253 | {
|
---|
1254 | /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
|
---|
1255 | HMFlushTLB(pVCpu);
|
---|
1256 |
|
---|
1257 | /* Notify PGM about NXE changes. */
|
---|
1258 | if ( (uOldEFER & MSR_K6_EFER_NXE)
|
---|
1259 | != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
|
---|
1260 | PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
|
---|
1261 | }
|
---|
1262 | break;
|
---|
1263 | }
|
---|
1264 |
|
---|
1265 | case MSR_K8_SF_MASK:
|
---|
1266 | pVCpu->cpum.s.Guest.msrSFMASK = uValue;
|
---|
1267 | break;
|
---|
1268 |
|
---|
1269 | case MSR_K6_STAR:
|
---|
1270 | pVCpu->cpum.s.Guest.msrSTAR = uValue;
|
---|
1271 | break;
|
---|
1272 |
|
---|
1273 | case MSR_K8_LSTAR:
|
---|
1274 | pVCpu->cpum.s.Guest.msrLSTAR = uValue;
|
---|
1275 | break;
|
---|
1276 |
|
---|
1277 | case MSR_K8_CSTAR:
|
---|
1278 | pVCpu->cpum.s.Guest.msrCSTAR = uValue;
|
---|
1279 | break;
|
---|
1280 |
|
---|
1281 | case MSR_K8_FS_BASE:
|
---|
1282 | pVCpu->cpum.s.Guest.fs.u64Base = uValue;
|
---|
1283 | break;
|
---|
1284 |
|
---|
1285 | case MSR_K8_GS_BASE:
|
---|
1286 | pVCpu->cpum.s.Guest.gs.u64Base = uValue;
|
---|
1287 | break;
|
---|
1288 |
|
---|
1289 | case MSR_K8_KERNEL_GS_BASE:
|
---|
1290 | pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
|
---|
1291 | break;
|
---|
1292 |
|
---|
1293 | case MSR_K8_TSC_AUX:
|
---|
1294 | pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
|
---|
1295 | break;
|
---|
1296 |
|
---|
1297 | /*
|
---|
1298 | * Intel specifics MSRs:
|
---|
1299 | */
|
---|
1300 | /*case MSR_IA32_PLATFORM_ID: - read-only */
|
---|
1301 | case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
|
---|
1302 | case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
|
---|
1303 | /*case MSR_IA32_MCP_CAP: - read-only */
|
---|
1304 | /*case MSR_IA32_MCP_STATUS: - read-only */
|
---|
1305 | /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
|
---|
1306 | /*case MSR_IA32_MC0_CTL: - read-only? */
|
---|
1307 | /*case MSR_IA32_MC0_STATUS: - read-only? */
|
---|
1308 | if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
|
---|
1309 | {
|
---|
1310 | Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
|
---|
1311 | return VERR_CPUM_RAISE_GP_0;
|
---|
1312 | }
|
---|
1313 | /* ignored */
|
---|
1314 | break;
|
---|
1315 |
|
---|
1316 | default:
|
---|
1317 | /*
|
---|
1318 | * Hand the X2APIC range to PDM and the APIC.
|
---|
1319 | */
|
---|
1320 | if ( idMsr >= MSR_IA32_X2APIC_START
|
---|
1321 | && idMsr <= MSR_IA32_X2APIC_END)
|
---|
1322 | {
|
---|
1323 | rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
|
---|
1324 | if (rc != VINF_SUCCESS)
|
---|
1325 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
1326 | }
|
---|
1327 | else
|
---|
1328 | {
|
---|
1329 | /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
|
---|
1330 | /** @todo rc = VERR_CPUM_RAISE_GP_0 */
|
---|
1331 | Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
|
---|
1332 | }
|
---|
1333 | break;
|
---|
1334 | }
|
---|
1335 | return rc;
|
---|
1336 | }
|
---|
1337 |
|
---|
1338 |
|
---|
1339 | VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
|
---|
1340 | {
|
---|
1341 | if (pcbLimit)
|
---|
1342 | *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
|
---|
1343 | return pVCpu->cpum.s.Guest.idtr.pIdt;
|
---|
1344 | }
|
---|
1345 |
|
---|
1346 |
|
---|
1347 | VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
|
---|
1348 | {
|
---|
1349 | if (pHidden)
|
---|
1350 | *pHidden = pVCpu->cpum.s.Guest.tr;
|
---|
1351 | return pVCpu->cpum.s.Guest.tr.Sel;
|
---|
1352 | }
|
---|
1353 |
|
---|
1354 |
|
---|
1355 | VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
|
---|
1356 | {
|
---|
1357 | return pVCpu->cpum.s.Guest.cs.Sel;
|
---|
1358 | }
|
---|
1359 |
|
---|
1360 |
|
---|
1361 | VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
|
---|
1362 | {
|
---|
1363 | return pVCpu->cpum.s.Guest.ds.Sel;
|
---|
1364 | }
|
---|
1365 |
|
---|
1366 |
|
---|
1367 | VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
|
---|
1368 | {
|
---|
1369 | return pVCpu->cpum.s.Guest.es.Sel;
|
---|
1370 | }
|
---|
1371 |
|
---|
1372 |
|
---|
1373 | VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
|
---|
1374 | {
|
---|
1375 | return pVCpu->cpum.s.Guest.fs.Sel;
|
---|
1376 | }
|
---|
1377 |
|
---|
1378 |
|
---|
1379 | VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
|
---|
1380 | {
|
---|
1381 | return pVCpu->cpum.s.Guest.gs.Sel;
|
---|
1382 | }
|
---|
1383 |
|
---|
1384 |
|
---|
1385 | VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
|
---|
1386 | {
|
---|
1387 | return pVCpu->cpum.s.Guest.ss.Sel;
|
---|
1388 | }
|
---|
1389 |
|
---|
1390 |
|
---|
1391 | VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
|
---|
1392 | {
|
---|
1393 | return pVCpu->cpum.s.Guest.ldtr.Sel;
|
---|
1394 | }
|
---|
1395 |
|
---|
1396 |
|
---|
1397 | VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
|
---|
1398 | {
|
---|
1399 | *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
|
---|
1400 | *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
|
---|
1401 | return pVCpu->cpum.s.Guest.ldtr.Sel;
|
---|
1402 | }
|
---|
1403 |
|
---|
1404 |
|
---|
1405 | VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
|
---|
1406 | {
|
---|
1407 | return pVCpu->cpum.s.Guest.cr0;
|
---|
1408 | }
|
---|
1409 |
|
---|
1410 |
|
---|
1411 | VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
|
---|
1412 | {
|
---|
1413 | return pVCpu->cpum.s.Guest.cr2;
|
---|
1414 | }
|
---|
1415 |
|
---|
1416 |
|
---|
1417 | VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
|
---|
1418 | {
|
---|
1419 | return pVCpu->cpum.s.Guest.cr3;
|
---|
1420 | }
|
---|
1421 |
|
---|
1422 |
|
---|
1423 | VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
|
---|
1424 | {
|
---|
1425 | return pVCpu->cpum.s.Guest.cr4;
|
---|
1426 | }
|
---|
1427 |
|
---|
1428 |
|
---|
1429 | VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
|
---|
1430 | {
|
---|
1431 | uint64_t u64;
|
---|
1432 | int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
|
---|
1433 | if (RT_FAILURE(rc))
|
---|
1434 | u64 = 0;
|
---|
1435 | return u64;
|
---|
1436 | }
|
---|
1437 |
|
---|
1438 |
|
---|
1439 | VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
|
---|
1440 | {
|
---|
1441 | *pGDTR = pVCpu->cpum.s.Guest.gdtr;
|
---|
1442 | }
|
---|
1443 |
|
---|
1444 |
|
---|
1445 | VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
|
---|
1446 | {
|
---|
1447 | return pVCpu->cpum.s.Guest.eip;
|
---|
1448 | }
|
---|
1449 |
|
---|
1450 |
|
---|
1451 | VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
|
---|
1452 | {
|
---|
1453 | return pVCpu->cpum.s.Guest.rip;
|
---|
1454 | }
|
---|
1455 |
|
---|
1456 |
|
---|
1457 | VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
|
---|
1458 | {
|
---|
1459 | return pVCpu->cpum.s.Guest.eax;
|
---|
1460 | }
|
---|
1461 |
|
---|
1462 |
|
---|
1463 | VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
|
---|
1464 | {
|
---|
1465 | return pVCpu->cpum.s.Guest.ebx;
|
---|
1466 | }
|
---|
1467 |
|
---|
1468 |
|
---|
1469 | VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
|
---|
1470 | {
|
---|
1471 | return pVCpu->cpum.s.Guest.ecx;
|
---|
1472 | }
|
---|
1473 |
|
---|
1474 |
|
---|
1475 | VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
|
---|
1476 | {
|
---|
1477 | return pVCpu->cpum.s.Guest.edx;
|
---|
1478 | }
|
---|
1479 |
|
---|
1480 |
|
---|
1481 | VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
|
---|
1482 | {
|
---|
1483 | return pVCpu->cpum.s.Guest.esi;
|
---|
1484 | }
|
---|
1485 |
|
---|
1486 |
|
---|
1487 | VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
|
---|
1488 | {
|
---|
1489 | return pVCpu->cpum.s.Guest.edi;
|
---|
1490 | }
|
---|
1491 |
|
---|
1492 |
|
---|
1493 | VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
|
---|
1494 | {
|
---|
1495 | return pVCpu->cpum.s.Guest.esp;
|
---|
1496 | }
|
---|
1497 |
|
---|
1498 |
|
---|
1499 | VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
|
---|
1500 | {
|
---|
1501 | return pVCpu->cpum.s.Guest.ebp;
|
---|
1502 | }
|
---|
1503 |
|
---|
1504 |
|
---|
1505 | VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
|
---|
1506 | {
|
---|
1507 | return pVCpu->cpum.s.Guest.eflags.u32;
|
---|
1508 | }
|
---|
1509 |
|
---|
1510 |
|
---|
1511 | VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
|
---|
1512 | {
|
---|
1513 | switch (iReg)
|
---|
1514 | {
|
---|
1515 | case DISCREG_CR0:
|
---|
1516 | *pValue = pVCpu->cpum.s.Guest.cr0;
|
---|
1517 | break;
|
---|
1518 |
|
---|
1519 | case DISCREG_CR2:
|
---|
1520 | *pValue = pVCpu->cpum.s.Guest.cr2;
|
---|
1521 | break;
|
---|
1522 |
|
---|
1523 | case DISCREG_CR3:
|
---|
1524 | *pValue = pVCpu->cpum.s.Guest.cr3;
|
---|
1525 | break;
|
---|
1526 |
|
---|
1527 | case DISCREG_CR4:
|
---|
1528 | *pValue = pVCpu->cpum.s.Guest.cr4;
|
---|
1529 | break;
|
---|
1530 |
|
---|
1531 | case DISCREG_CR8:
|
---|
1532 | {
|
---|
1533 | uint8_t u8Tpr;
|
---|
1534 | int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
|
---|
1535 | if (RT_FAILURE(rc))
|
---|
1536 | {
|
---|
1537 | AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
|
---|
1538 | *pValue = 0;
|
---|
1539 | return rc;
|
---|
1540 | }
|
---|
1541 | *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
|
---|
1542 | break;
|
---|
1543 | }
|
---|
1544 |
|
---|
1545 | default:
|
---|
1546 | return VERR_INVALID_PARAMETER;
|
---|
1547 | }
|
---|
1548 | return VINF_SUCCESS;
|
---|
1549 | }
|
---|
1550 |
|
---|
1551 |
|
---|
1552 | VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
|
---|
1553 | {
|
---|
1554 | return pVCpu->cpum.s.Guest.dr[0];
|
---|
1555 | }
|
---|
1556 |
|
---|
1557 |
|
---|
1558 | VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
|
---|
1559 | {
|
---|
1560 | return pVCpu->cpum.s.Guest.dr[1];
|
---|
1561 | }
|
---|
1562 |
|
---|
1563 |
|
---|
1564 | VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
|
---|
1565 | {
|
---|
1566 | return pVCpu->cpum.s.Guest.dr[2];
|
---|
1567 | }
|
---|
1568 |
|
---|
1569 |
|
---|
1570 | VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
|
---|
1571 | {
|
---|
1572 | return pVCpu->cpum.s.Guest.dr[3];
|
---|
1573 | }
|
---|
1574 |
|
---|
1575 |
|
---|
1576 | VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
|
---|
1577 | {
|
---|
1578 | return pVCpu->cpum.s.Guest.dr[6];
|
---|
1579 | }
|
---|
1580 |
|
---|
1581 |
|
---|
1582 | VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
|
---|
1583 | {
|
---|
1584 | return pVCpu->cpum.s.Guest.dr[7];
|
---|
1585 | }
|
---|
1586 |
|
---|
1587 |
|
---|
1588 | VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
|
---|
1589 | {
|
---|
1590 | AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
|
---|
1591 | /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
|
---|
1592 | if (iReg == 4 || iReg == 5)
|
---|
1593 | iReg += 2;
|
---|
1594 | *pValue = pVCpu->cpum.s.Guest.dr[iReg];
|
---|
1595 | return VINF_SUCCESS;
|
---|
1596 | }
|
---|
1597 |
|
---|
1598 |
|
---|
1599 | VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
|
---|
1600 | {
|
---|
1601 | return pVCpu->cpum.s.Guest.msrEFER;
|
---|
1602 | }
|
---|
1603 |
|
---|
1604 |
|
---|
1605 | /**
|
---|
1606 | * Gets a CPUID leaf.
|
---|
1607 | *
|
---|
1608 | * @param pVCpu Pointer to the VMCPU.
|
---|
1609 | * @param iLeaf The CPUID leaf to get.
|
---|
1610 | * @param pEax Where to store the EAX value.
|
---|
1611 | * @param pEbx Where to store the EBX value.
|
---|
1612 | * @param pEcx Where to store the ECX value.
|
---|
1613 | * @param pEdx Where to store the EDX value.
|
---|
1614 | */
|
---|
1615 | VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
|
---|
1616 | {
|
---|
1617 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
1618 |
|
---|
1619 | PCCPUMCPUID pCpuId;
|
---|
1620 | if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
|
---|
1621 | pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
|
---|
1622 | else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
|
---|
1623 | pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
|
---|
1624 | else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
|
---|
1625 | && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
|
---|
1626 | pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
|
---|
1627 | else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
|
---|
1628 | pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
|
---|
1629 | else
|
---|
1630 | pCpuId = &pVM->cpum.s.GuestCpuIdDef;
|
---|
1631 |
|
---|
1632 | uint32_t cCurrentCacheIndex = *pEcx;
|
---|
1633 |
|
---|
1634 | *pEax = pCpuId->eax;
|
---|
1635 | *pEbx = pCpuId->ebx;
|
---|
1636 | *pEcx = pCpuId->ecx;
|
---|
1637 | *pEdx = pCpuId->edx;
|
---|
1638 |
|
---|
1639 | if ( iLeaf == 1)
|
---|
1640 | {
|
---|
1641 | /* Bits 31-24: Initial APIC ID */
|
---|
1642 | Assert(pVCpu->idCpu <= 255);
|
---|
1643 | *pEbx |= (pVCpu->idCpu << 24);
|
---|
1644 | }
|
---|
1645 |
|
---|
1646 | if ( iLeaf == 4
|
---|
1647 | && cCurrentCacheIndex < 3
|
---|
1648 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
|
---|
1649 | {
|
---|
1650 | uint32_t type, level, sharing, linesize,
|
---|
1651 | partitions, associativity, sets, cores;
|
---|
1652 |
|
---|
1653 | /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
|
---|
1654 | partitions = 1;
|
---|
1655 | /* Those are only to shut up compiler, as they will always
|
---|
1656 | get overwritten, and compiler should be able to figure that out */
|
---|
1657 | sets = associativity = sharing = level = 1;
|
---|
1658 | cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
|
---|
1659 | switch (cCurrentCacheIndex)
|
---|
1660 | {
|
---|
1661 | case 0:
|
---|
1662 | type = 1;
|
---|
1663 | level = 1;
|
---|
1664 | sharing = 1;
|
---|
1665 | linesize = 64;
|
---|
1666 | associativity = 8;
|
---|
1667 | sets = 64;
|
---|
1668 | break;
|
---|
1669 | case 1:
|
---|
1670 | level = 1;
|
---|
1671 | type = 2;
|
---|
1672 | sharing = 1;
|
---|
1673 | linesize = 64;
|
---|
1674 | associativity = 8;
|
---|
1675 | sets = 64;
|
---|
1676 | break;
|
---|
1677 | default: /* shut up gcc.*/
|
---|
1678 | AssertFailed();
|
---|
1679 | case 2:
|
---|
1680 | level = 2;
|
---|
1681 | type = 3;
|
---|
1682 | sharing = cores; /* our L2 cache is modelled as shared between all cores */
|
---|
1683 | linesize = 64;
|
---|
1684 | associativity = 24;
|
---|
1685 | sets = 4096;
|
---|
1686 | break;
|
---|
1687 | }
|
---|
1688 |
|
---|
1689 | *pEax |= ((cores - 1) << 26) |
|
---|
1690 | ((sharing - 1) << 14) |
|
---|
1691 | (level << 5) |
|
---|
1692 | 1;
|
---|
1693 | *pEbx = (linesize - 1) |
|
---|
1694 | ((partitions - 1) << 12) |
|
---|
1695 | ((associativity - 1) << 22); /* -1 encoding */
|
---|
1696 | *pEcx = sets - 1;
|
---|
1697 | }
|
---|
1698 |
|
---|
1699 | Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
|
---|
1700 | }
|
---|
1701 |
|
---|
1702 | /**
|
---|
1703 | * Gets a number of standard CPUID leafs.
|
---|
1704 | *
|
---|
1705 | * @returns Number of leafs.
|
---|
1706 | * @param pVM Pointer to the VM.
|
---|
1707 | * @remark Intended for PATM.
|
---|
1708 | */
|
---|
1709 | VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
|
---|
1710 | {
|
---|
1711 | return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
|
---|
1712 | }
|
---|
1713 |
|
---|
1714 |
|
---|
1715 | /**
|
---|
1716 | * Gets a number of extended CPUID leafs.
|
---|
1717 | *
|
---|
1718 | * @returns Number of leafs.
|
---|
1719 | * @param pVM Pointer to the VM.
|
---|
1720 | * @remark Intended for PATM.
|
---|
1721 | */
|
---|
1722 | VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
|
---|
1723 | {
|
---|
1724 | return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
|
---|
1725 | }
|
---|
1726 |
|
---|
1727 |
|
---|
1728 | /**
|
---|
1729 | * Gets a number of centaur CPUID leafs.
|
---|
1730 | *
|
---|
1731 | * @returns Number of leafs.
|
---|
1732 | * @param pVM Pointer to the VM.
|
---|
1733 | * @remark Intended for PATM.
|
---|
1734 | */
|
---|
1735 | VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
|
---|
1736 | {
|
---|
1737 | return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
|
---|
1738 | }
|
---|
1739 |
|
---|
1740 |
|
---|
1741 | /**
|
---|
1742 | * Sets a CPUID feature bit.
|
---|
1743 | *
|
---|
1744 | * @param pVM Pointer to the VM.
|
---|
1745 | * @param enmFeature The feature to set.
|
---|
1746 | */
|
---|
1747 | VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
|
---|
1748 | {
|
---|
1749 | switch (enmFeature)
|
---|
1750 | {
|
---|
1751 | /*
|
---|
1752 | * Set the APIC bit in both feature masks.
|
---|
1753 | */
|
---|
1754 | case CPUMCPUIDFEATURE_APIC:
|
---|
1755 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
1756 | pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
|
---|
1757 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
1758 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
1759 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
|
---|
1760 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
|
---|
1761 | break;
|
---|
1762 |
|
---|
1763 | /*
|
---|
1764 | * Set the x2APIC bit in the standard feature mask.
|
---|
1765 | */
|
---|
1766 | case CPUMCPUIDFEATURE_X2APIC:
|
---|
1767 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
1768 | pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
|
---|
1769 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
|
---|
1770 | break;
|
---|
1771 |
|
---|
1772 | /*
|
---|
1773 | * Set the sysenter/sysexit bit in the standard feature mask.
|
---|
1774 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
1775 | */
|
---|
1776 | case CPUMCPUIDFEATURE_SEP:
|
---|
1777 | {
|
---|
1778 | if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
|
---|
1779 | {
|
---|
1780 | AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
|
---|
1781 | return;
|
---|
1782 | }
|
---|
1783 |
|
---|
1784 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
1785 | pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
|
---|
1786 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
|
---|
1787 | break;
|
---|
1788 | }
|
---|
1789 |
|
---|
1790 | /*
|
---|
1791 | * Set the syscall/sysret bit in the extended feature mask.
|
---|
1792 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
1793 | */
|
---|
1794 | case CPUMCPUIDFEATURE_SYSCALL:
|
---|
1795 | {
|
---|
1796 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
1797 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
|
---|
1798 | {
|
---|
1799 | #if HC_ARCH_BITS == 32
|
---|
1800 | /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
|
---|
1801 | * Even when the cpu is capable of doing so in 64 bits mode.
|
---|
1802 | */
|
---|
1803 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
1804 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
|
---|
1805 | || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
|
---|
1806 | #endif
|
---|
1807 | {
|
---|
1808 | LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
|
---|
1809 | return;
|
---|
1810 | }
|
---|
1811 | }
|
---|
1812 | /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
|
---|
1813 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
|
---|
1814 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
|
---|
1815 | break;
|
---|
1816 | }
|
---|
1817 |
|
---|
1818 | /*
|
---|
1819 | * Set the PAE bit in both feature masks.
|
---|
1820 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
1821 | */
|
---|
1822 | case CPUMCPUIDFEATURE_PAE:
|
---|
1823 | {
|
---|
1824 | if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
|
---|
1825 | {
|
---|
1826 | LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
|
---|
1827 | return;
|
---|
1828 | }
|
---|
1829 |
|
---|
1830 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
1831 | pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
|
---|
1832 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
1833 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
1834 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
|
---|
1835 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
|
---|
1836 | break;
|
---|
1837 | }
|
---|
1838 |
|
---|
1839 | /*
|
---|
1840 | * Set the LONG MODE bit in the extended feature mask.
|
---|
1841 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
1842 | */
|
---|
1843 | case CPUMCPUIDFEATURE_LONG_MODE:
|
---|
1844 | {
|
---|
1845 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
1846 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
|
---|
1847 | {
|
---|
1848 | LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
|
---|
1849 | return;
|
---|
1850 | }
|
---|
1851 |
|
---|
1852 | /* Valid for both Intel and AMD. */
|
---|
1853 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
|
---|
1854 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
|
---|
1855 | break;
|
---|
1856 | }
|
---|
1857 |
|
---|
1858 | /*
|
---|
1859 | * Set the NX/XD bit in the extended feature mask.
|
---|
1860 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
1861 | */
|
---|
1862 | case CPUMCPUIDFEATURE_NX:
|
---|
1863 | {
|
---|
1864 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
1865 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
|
---|
1866 | {
|
---|
1867 | LogRel(("WARNING: Can't turn on NX/XD when the host doesn't support it!!\n"));
|
---|
1868 | return;
|
---|
1869 | }
|
---|
1870 |
|
---|
1871 | /* Valid for both Intel and AMD. */
|
---|
1872 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
|
---|
1873 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled NX\n"));
|
---|
1874 | break;
|
---|
1875 | }
|
---|
1876 |
|
---|
1877 | /*
|
---|
1878 | * Set the LAHF/SAHF support in 64-bit mode.
|
---|
1879 | * Assumes the caller knows what it's doing! (host must support this)
|
---|
1880 | */
|
---|
1881 | case CPUMCPUIDFEATURE_LAHF:
|
---|
1882 | {
|
---|
1883 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
1884 | || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
|
---|
1885 | {
|
---|
1886 | LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
|
---|
1887 | return;
|
---|
1888 | }
|
---|
1889 |
|
---|
1890 | /* Valid for both Intel and AMD. */
|
---|
1891 | pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
|
---|
1892 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
|
---|
1893 | break;
|
---|
1894 | }
|
---|
1895 |
|
---|
1896 | case CPUMCPUIDFEATURE_PAT:
|
---|
1897 | {
|
---|
1898 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
1899 | pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
|
---|
1900 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
1901 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
1902 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
|
---|
1903 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAT\n"));
|
---|
1904 | break;
|
---|
1905 | }
|
---|
1906 |
|
---|
1907 | /*
|
---|
1908 | * Set the RDTSCP support bit.
|
---|
1909 | * Assumes the caller knows what it's doing! (host must support this)
|
---|
1910 | */
|
---|
1911 | case CPUMCPUIDFEATURE_RDTSCP:
|
---|
1912 | {
|
---|
1913 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
1914 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
|
---|
1915 | || pVM->cpum.s.u8PortableCpuIdLevel > 0)
|
---|
1916 | {
|
---|
1917 | if (!pVM->cpum.s.u8PortableCpuIdLevel)
|
---|
1918 | LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
|
---|
1919 | return;
|
---|
1920 | }
|
---|
1921 |
|
---|
1922 | /* Valid for both Intel and AMD. */
|
---|
1923 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
|
---|
1924 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
|
---|
1925 | break;
|
---|
1926 | }
|
---|
1927 |
|
---|
1928 | /*
|
---|
1929 | * Set the Hypervisor Present bit in the standard feature mask.
|
---|
1930 | */
|
---|
1931 | case CPUMCPUIDFEATURE_HVP:
|
---|
1932 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
1933 | pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
|
---|
1934 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
|
---|
1935 | break;
|
---|
1936 |
|
---|
1937 | default:
|
---|
1938 | AssertMsgFailed(("enmFeature=%d\n", enmFeature));
|
---|
1939 | break;
|
---|
1940 | }
|
---|
1941 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
1942 | {
|
---|
1943 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
1944 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
|
---|
1945 | }
|
---|
1946 | }
|
---|
1947 |
|
---|
1948 |
|
---|
1949 | /**
|
---|
1950 | * Queries a CPUID feature bit.
|
---|
1951 | *
|
---|
1952 | * @returns boolean for feature presence
|
---|
1953 | * @param pVM Pointer to the VM.
|
---|
1954 | * @param enmFeature The feature to query.
|
---|
1955 | */
|
---|
1956 | VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
|
---|
1957 | {
|
---|
1958 | switch (enmFeature)
|
---|
1959 | {
|
---|
1960 | case CPUMCPUIDFEATURE_PAE:
|
---|
1961 | {
|
---|
1962 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
1963 | return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
|
---|
1964 | break;
|
---|
1965 | }
|
---|
1966 |
|
---|
1967 | case CPUMCPUIDFEATURE_NX:
|
---|
1968 | {
|
---|
1969 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
1970 | return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
|
---|
1971 | }
|
---|
1972 |
|
---|
1973 | case CPUMCPUIDFEATURE_SYSCALL:
|
---|
1974 | {
|
---|
1975 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
1976 | return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
|
---|
1977 | }
|
---|
1978 |
|
---|
1979 | case CPUMCPUIDFEATURE_RDTSCP:
|
---|
1980 | {
|
---|
1981 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
1982 | return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
|
---|
1983 | break;
|
---|
1984 | }
|
---|
1985 |
|
---|
1986 | case CPUMCPUIDFEATURE_LONG_MODE:
|
---|
1987 | {
|
---|
1988 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
1989 | return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
|
---|
1990 | break;
|
---|
1991 | }
|
---|
1992 |
|
---|
1993 | default:
|
---|
1994 | AssertMsgFailed(("enmFeature=%d\n", enmFeature));
|
---|
1995 | break;
|
---|
1996 | }
|
---|
1997 | return false;
|
---|
1998 | }
|
---|
1999 |
|
---|
2000 |
|
---|
2001 | /**
|
---|
2002 | * Clears a CPUID feature bit.
|
---|
2003 | *
|
---|
2004 | * @param pVM Pointer to the VM.
|
---|
2005 | * @param enmFeature The feature to clear.
|
---|
2006 | */
|
---|
2007 | VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
|
---|
2008 | {
|
---|
2009 | switch (enmFeature)
|
---|
2010 | {
|
---|
2011 | /*
|
---|
2012 | * Set the APIC bit in both feature masks.
|
---|
2013 | */
|
---|
2014 | case CPUMCPUIDFEATURE_APIC:
|
---|
2015 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
2016 | pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
|
---|
2017 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
2018 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
2019 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
|
---|
2020 | Log(("CPUMClearGuestCpuIdFeature: Disabled APIC\n"));
|
---|
2021 | break;
|
---|
2022 |
|
---|
2023 | /*
|
---|
2024 | * Clear the x2APIC bit in the standard feature mask.
|
---|
2025 | */
|
---|
2026 | case CPUMCPUIDFEATURE_X2APIC:
|
---|
2027 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
2028 | pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
|
---|
2029 | Log(("CPUMClearGuestCpuIdFeature: Disabled x2APIC\n"));
|
---|
2030 | break;
|
---|
2031 |
|
---|
2032 | case CPUMCPUIDFEATURE_PAE:
|
---|
2033 | {
|
---|
2034 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
2035 | pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
|
---|
2036 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
2037 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
2038 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
|
---|
2039 | Log(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
|
---|
2040 | break;
|
---|
2041 | }
|
---|
2042 |
|
---|
2043 | case CPUMCPUIDFEATURE_PAT:
|
---|
2044 | {
|
---|
2045 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
2046 | pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
|
---|
2047 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
2048 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
2049 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
|
---|
2050 | Log(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
|
---|
2051 | break;
|
---|
2052 | }
|
---|
2053 |
|
---|
2054 | case CPUMCPUIDFEATURE_LONG_MODE:
|
---|
2055 | {
|
---|
2056 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
2057 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
|
---|
2058 | break;
|
---|
2059 | }
|
---|
2060 |
|
---|
2061 | case CPUMCPUIDFEATURE_LAHF:
|
---|
2062 | {
|
---|
2063 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
2064 | pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
|
---|
2065 | break;
|
---|
2066 | }
|
---|
2067 |
|
---|
2068 | case CPUMCPUIDFEATURE_RDTSCP:
|
---|
2069 | {
|
---|
2070 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
2071 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
|
---|
2072 | Log(("CPUMClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
|
---|
2073 | break;
|
---|
2074 | }
|
---|
2075 |
|
---|
2076 | case CPUMCPUIDFEATURE_HVP:
|
---|
2077 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
2078 | pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
|
---|
2079 | break;
|
---|
2080 |
|
---|
2081 | default:
|
---|
2082 | AssertMsgFailed(("enmFeature=%d\n", enmFeature));
|
---|
2083 | break;
|
---|
2084 | }
|
---|
2085 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
2086 | {
|
---|
2087 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
2088 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
|
---|
2089 | }
|
---|
2090 | }
|
---|
2091 |
|
---|
2092 |
|
---|
2093 | /**
|
---|
2094 | * Gets the host CPU vendor.
|
---|
2095 | *
|
---|
2096 | * @returns CPU vendor.
|
---|
2097 | * @param pVM Pointer to the VM.
|
---|
2098 | */
|
---|
2099 | VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
|
---|
2100 | {
|
---|
2101 | return pVM->cpum.s.enmHostCpuVendor;
|
---|
2102 | }
|
---|
2103 |
|
---|
2104 |
|
---|
2105 | /**
|
---|
2106 | * Gets the CPU vendor.
|
---|
2107 | *
|
---|
2108 | * @returns CPU vendor.
|
---|
2109 | * @param pVM Pointer to the VM.
|
---|
2110 | */
|
---|
2111 | VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
|
---|
2112 | {
|
---|
2113 | return pVM->cpum.s.enmGuestCpuVendor;
|
---|
2114 | }
|
---|
2115 |
|
---|
2116 |
|
---|
2117 | VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
|
---|
2118 | {
|
---|
2119 | pVCpu->cpum.s.Guest.dr[0] = uDr0;
|
---|
2120 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
2121 | }
|
---|
2122 |
|
---|
2123 |
|
---|
2124 | VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
|
---|
2125 | {
|
---|
2126 | pVCpu->cpum.s.Guest.dr[1] = uDr1;
|
---|
2127 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
2128 | }
|
---|
2129 |
|
---|
2130 |
|
---|
2131 | VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
|
---|
2132 | {
|
---|
2133 | pVCpu->cpum.s.Guest.dr[2] = uDr2;
|
---|
2134 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
2135 | }
|
---|
2136 |
|
---|
2137 |
|
---|
2138 | VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
|
---|
2139 | {
|
---|
2140 | pVCpu->cpum.s.Guest.dr[3] = uDr3;
|
---|
2141 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
2142 | }
|
---|
2143 |
|
---|
2144 |
|
---|
2145 | VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
|
---|
2146 | {
|
---|
2147 | pVCpu->cpum.s.Guest.dr[6] = uDr6;
|
---|
2148 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
2149 | }
|
---|
2150 |
|
---|
2151 |
|
---|
2152 | VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
|
---|
2153 | {
|
---|
2154 | pVCpu->cpum.s.Guest.dr[7] = uDr7;
|
---|
2155 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
2156 | }
|
---|
2157 |
|
---|
2158 |
|
---|
2159 | VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
|
---|
2160 | {
|
---|
2161 | AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
|
---|
2162 | /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
|
---|
2163 | if (iReg == 4 || iReg == 5)
|
---|
2164 | iReg += 2;
|
---|
2165 | pVCpu->cpum.s.Guest.dr[iReg] = Value;
|
---|
2166 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
2167 | }
|
---|
2168 |
|
---|
2169 |
|
---|
2170 | /**
|
---|
2171 | * Recalculates the hypervisor DRx register values based on
|
---|
2172 | * current guest registers and DBGF breakpoints.
|
---|
2173 | *
|
---|
2174 | * This is called whenever a guest DRx register is modified and when DBGF
|
---|
2175 | * sets a hardware breakpoint. In guest context this function will reload
|
---|
2176 | * any (hyper) DRx registers which comes out with a different value.
|
---|
2177 | *
|
---|
2178 | * @returns VINF_SUCCESS.
|
---|
2179 | * @param pVCpu Pointer to the VMCPU.
|
---|
2180 | */
|
---|
2181 | VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
|
---|
2182 | {
|
---|
2183 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
2184 |
|
---|
2185 | /*
|
---|
2186 | * Compare the DR7s first.
|
---|
2187 | *
|
---|
2188 | * We only care about the enabled flags. The GE and LE flags are always
|
---|
2189 | * set and we don't care if the guest doesn't set them. GD is virtualized
|
---|
2190 | * when we dispatch #DB, we never enable it.
|
---|
2191 | */
|
---|
2192 | const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
|
---|
2193 | #ifdef CPUM_VIRTUALIZE_DRX
|
---|
2194 | const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
|
---|
2195 | #else
|
---|
2196 | const RTGCUINTREG uGstDr7 = 0;
|
---|
2197 | #endif
|
---|
2198 | if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
|
---|
2199 | {
|
---|
2200 | /*
|
---|
2201 | * Ok, something is enabled. Recalc each of the breakpoints.
|
---|
2202 | * Straight forward code, not optimized/minimized in any way.
|
---|
2203 | */
|
---|
2204 | RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
|
---|
2205 |
|
---|
2206 | /* bp 0 */
|
---|
2207 | RTGCUINTREG uNewDr0;
|
---|
2208 | if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
|
---|
2209 | {
|
---|
2210 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
|
---|
2211 | uNewDr0 = DBGFBpGetDR0(pVM);
|
---|
2212 | }
|
---|
2213 | else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
|
---|
2214 | {
|
---|
2215 | uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
|
---|
2216 | uNewDr0 = CPUMGetGuestDR0(pVCpu);
|
---|
2217 | }
|
---|
2218 | else
|
---|
2219 | uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
|
---|
2220 |
|
---|
2221 | /* bp 1 */
|
---|
2222 | RTGCUINTREG uNewDr1;
|
---|
2223 | if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
|
---|
2224 | {
|
---|
2225 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
|
---|
2226 | uNewDr1 = DBGFBpGetDR1(pVM);
|
---|
2227 | }
|
---|
2228 | else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
|
---|
2229 | {
|
---|
2230 | uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
|
---|
2231 | uNewDr1 = CPUMGetGuestDR1(pVCpu);
|
---|
2232 | }
|
---|
2233 | else
|
---|
2234 | uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
|
---|
2235 |
|
---|
2236 | /* bp 2 */
|
---|
2237 | RTGCUINTREG uNewDr2;
|
---|
2238 | if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
|
---|
2239 | {
|
---|
2240 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
|
---|
2241 | uNewDr2 = DBGFBpGetDR2(pVM);
|
---|
2242 | }
|
---|
2243 | else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
|
---|
2244 | {
|
---|
2245 | uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
|
---|
2246 | uNewDr2 = CPUMGetGuestDR2(pVCpu);
|
---|
2247 | }
|
---|
2248 | else
|
---|
2249 | uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
|
---|
2250 |
|
---|
2251 | /* bp 3 */
|
---|
2252 | RTGCUINTREG uNewDr3;
|
---|
2253 | if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
|
---|
2254 | {
|
---|
2255 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
|
---|
2256 | uNewDr3 = DBGFBpGetDR3(pVM);
|
---|
2257 | }
|
---|
2258 | else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
|
---|
2259 | {
|
---|
2260 | uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
|
---|
2261 | uNewDr3 = CPUMGetGuestDR3(pVCpu);
|
---|
2262 | }
|
---|
2263 | else
|
---|
2264 | uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
|
---|
2265 |
|
---|
2266 | /*
|
---|
2267 | * Apply the updates.
|
---|
2268 | */
|
---|
2269 | #ifdef IN_RC
|
---|
2270 | if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
|
---|
2271 | {
|
---|
2272 | /** @todo save host DBx registers. */
|
---|
2273 | }
|
---|
2274 | #endif
|
---|
2275 | /** @todo Should this not be setting CPUM_USE_DEBUG_REGS_HYPER?
|
---|
2276 | * (CPUM_VIRTUALIZE_DRX is never defined). */
|
---|
2277 | pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
|
---|
2278 | if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
|
---|
2279 | CPUMSetHyperDR3(pVCpu, uNewDr3);
|
---|
2280 | if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
|
---|
2281 | CPUMSetHyperDR2(pVCpu, uNewDr2);
|
---|
2282 | if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
|
---|
2283 | CPUMSetHyperDR1(pVCpu, uNewDr1);
|
---|
2284 | if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
|
---|
2285 | CPUMSetHyperDR0(pVCpu, uNewDr0);
|
---|
2286 | if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
|
---|
2287 | CPUMSetHyperDR7(pVCpu, uNewDr7);
|
---|
2288 | }
|
---|
2289 | else
|
---|
2290 | {
|
---|
2291 | #ifdef IN_RC
|
---|
2292 | if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
|
---|
2293 | {
|
---|
2294 | /** @todo restore host DBx registers. */
|
---|
2295 | }
|
---|
2296 | #endif
|
---|
2297 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
|
---|
2298 | }
|
---|
2299 | Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
|
---|
2300 | pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
|
---|
2301 | pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
|
---|
2302 | pVCpu->cpum.s.Hyper.dr[7]));
|
---|
2303 |
|
---|
2304 | return VINF_SUCCESS;
|
---|
2305 | }
|
---|
2306 |
|
---|
2307 |
|
---|
2308 | /**
|
---|
2309 | * Tests if the guest has No-Execute Page Protection Enabled (NXE).
|
---|
2310 | *
|
---|
2311 | * @returns true if in real mode, otherwise false.
|
---|
2312 | * @param pVCpu Pointer to the VMCPU.
|
---|
2313 | */
|
---|
2314 | VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
|
---|
2315 | {
|
---|
2316 | return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
|
---|
2317 | }
|
---|
2318 |
|
---|
2319 |
|
---|
2320 | /**
|
---|
2321 | * Tests if the guest has the Page Size Extension enabled (PSE).
|
---|
2322 | *
|
---|
2323 | * @returns true if in real mode, otherwise false.
|
---|
2324 | * @param pVCpu Pointer to the VMCPU.
|
---|
2325 | */
|
---|
2326 | VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
|
---|
2327 | {
|
---|
2328 | /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
|
---|
2329 | return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
|
---|
2330 | }
|
---|
2331 |
|
---|
2332 |
|
---|
2333 | /**
|
---|
2334 | * Tests if the guest has the paging enabled (PG).
|
---|
2335 | *
|
---|
2336 | * @returns true if in real mode, otherwise false.
|
---|
2337 | * @param pVCpu Pointer to the VMCPU.
|
---|
2338 | */
|
---|
2339 | VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
|
---|
2340 | {
|
---|
2341 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
|
---|
2342 | }
|
---|
2343 |
|
---|
2344 |
|
---|
2345 | /**
|
---|
2346 | * Tests if the guest has the paging enabled (PG).
|
---|
2347 | *
|
---|
2348 | * @returns true if in real mode, otherwise false.
|
---|
2349 | * @param pVCpu Pointer to the VMCPU.
|
---|
2350 | */
|
---|
2351 | VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
|
---|
2352 | {
|
---|
2353 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
|
---|
2354 | }
|
---|
2355 |
|
---|
2356 |
|
---|
2357 | /**
|
---|
2358 | * Tests if the guest is running in real mode or not.
|
---|
2359 | *
|
---|
2360 | * @returns true if in real mode, otherwise false.
|
---|
2361 | * @param pVCpu Pointer to the VMCPU.
|
---|
2362 | */
|
---|
2363 | VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
|
---|
2364 | {
|
---|
2365 | return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
|
---|
2366 | }
|
---|
2367 |
|
---|
2368 |
|
---|
2369 | /**
|
---|
2370 | * Tests if the guest is running in real or virtual 8086 mode.
|
---|
2371 | *
|
---|
2372 | * @returns @c true if it is, @c false if not.
|
---|
2373 | * @param pVCpu Pointer to the VMCPU.
|
---|
2374 | */
|
---|
2375 | VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
|
---|
2376 | {
|
---|
2377 | return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
|
---|
2378 | || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
|
---|
2379 | }
|
---|
2380 |
|
---|
2381 |
|
---|
2382 | /**
|
---|
2383 | * Tests if the guest is running in protected or not.
|
---|
2384 | *
|
---|
2385 | * @returns true if in protected mode, otherwise false.
|
---|
2386 | * @param pVCpu Pointer to the VMCPU.
|
---|
2387 | */
|
---|
2388 | VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
|
---|
2389 | {
|
---|
2390 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
|
---|
2391 | }
|
---|
2392 |
|
---|
2393 |
|
---|
2394 | /**
|
---|
2395 | * Tests if the guest is running in paged protected or not.
|
---|
2396 | *
|
---|
2397 | * @returns true if in paged protected mode, otherwise false.
|
---|
2398 | * @param pVCpu Pointer to the VMCPU.
|
---|
2399 | */
|
---|
2400 | VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
|
---|
2401 | {
|
---|
2402 | return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
|
---|
2403 | }
|
---|
2404 |
|
---|
2405 |
|
---|
2406 | /**
|
---|
2407 | * Tests if the guest is running in long mode or not.
|
---|
2408 | *
|
---|
2409 | * @returns true if in long mode, otherwise false.
|
---|
2410 | * @param pVCpu Pointer to the VMCPU.
|
---|
2411 | */
|
---|
2412 | VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
|
---|
2413 | {
|
---|
2414 | return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
|
---|
2415 | }
|
---|
2416 |
|
---|
2417 |
|
---|
2418 | /**
|
---|
2419 | * Tests if the guest is running in PAE mode or not.
|
---|
2420 | *
|
---|
2421 | * @returns true if in PAE mode, otherwise false.
|
---|
2422 | * @param pVCpu Pointer to the VMCPU.
|
---|
2423 | */
|
---|
2424 | VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
|
---|
2425 | {
|
---|
2426 | #ifdef VBOX_WITH_OLD_VTX_CODE
|
---|
2427 | return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
|
---|
2428 | && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
|
---|
2429 | && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
|
---|
2430 | #else
|
---|
2431 | return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
|
---|
2432 | && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
|
---|
2433 | && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LME);
|
---|
2434 | #endif
|
---|
2435 | }
|
---|
2436 |
|
---|
2437 |
|
---|
2438 | /**
|
---|
2439 | * Tests if the guest is running in 64 bits mode or not.
|
---|
2440 | *
|
---|
2441 | * @returns true if in 64 bits protected mode, otherwise false.
|
---|
2442 | * @param pVCpu The current virtual CPU.
|
---|
2443 | */
|
---|
2444 | VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
|
---|
2445 | {
|
---|
2446 | if (!CPUMIsGuestInLongMode(pVCpu))
|
---|
2447 | return false;
|
---|
2448 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
2449 | return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
|
---|
2450 | }
|
---|
2451 |
|
---|
2452 |
|
---|
2453 | /**
|
---|
2454 | * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
|
---|
2455 | * registers.
|
---|
2456 | *
|
---|
2457 | * @returns true if in 64 bits protected mode, otherwise false.
|
---|
2458 | * @param pCtx Pointer to the current guest CPU context.
|
---|
2459 | */
|
---|
2460 | VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
|
---|
2461 | {
|
---|
2462 | return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
|
---|
2463 | }
|
---|
2464 |
|
---|
2465 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
2466 |
|
---|
2467 | /**
|
---|
2468 | *
|
---|
2469 | * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
|
---|
2470 | * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
|
---|
2471 | * @param pVCpu The current virtual CPU.
|
---|
2472 | */
|
---|
2473 | VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
|
---|
2474 | {
|
---|
2475 | return pVCpu->cpum.s.fRawEntered;
|
---|
2476 | }
|
---|
2477 |
|
---|
2478 | /**
|
---|
2479 | * Transforms the guest CPU state to raw-ring mode.
|
---|
2480 | *
|
---|
2481 | * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
|
---|
2482 | *
|
---|
2483 | * @returns VBox status. (recompiler failure)
|
---|
2484 | * @param pVCpu Pointer to the VMCPU.
|
---|
2485 | * @param pCtxCore The context core (for trap usage).
|
---|
2486 | * @see @ref pg_raw
|
---|
2487 | */
|
---|
2488 | VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
|
---|
2489 | {
|
---|
2490 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
2491 |
|
---|
2492 | Assert(!pVCpu->cpum.s.fRawEntered);
|
---|
2493 | Assert(!pVCpu->cpum.s.fRemEntered);
|
---|
2494 | if (!pCtxCore)
|
---|
2495 | pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
|
---|
2496 |
|
---|
2497 | /*
|
---|
2498 | * Are we in Ring-0?
|
---|
2499 | */
|
---|
2500 | if ( pCtxCore->ss.Sel
|
---|
2501 | && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
|
---|
2502 | && !pCtxCore->eflags.Bits.u1VM)
|
---|
2503 | {
|
---|
2504 | /*
|
---|
2505 | * Enter execution mode.
|
---|
2506 | */
|
---|
2507 | PATMRawEnter(pVM, pCtxCore);
|
---|
2508 |
|
---|
2509 | /*
|
---|
2510 | * Set CPL to Ring-1.
|
---|
2511 | */
|
---|
2512 | pCtxCore->ss.Sel |= 1;
|
---|
2513 | if ( pCtxCore->cs.Sel
|
---|
2514 | && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
|
---|
2515 | pCtxCore->cs.Sel |= 1;
|
---|
2516 | }
|
---|
2517 | else
|
---|
2518 | {
|
---|
2519 | # ifdef VBOX_WITH_RAW_RING1
|
---|
2520 | if ( EMIsRawRing1Enabled(pVM)
|
---|
2521 | && !pCtxCore->eflags.Bits.u1VM
|
---|
2522 | && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
|
---|
2523 | {
|
---|
2524 | /* Set CPL to Ring-2. */
|
---|
2525 | pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
|
---|
2526 | if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
|
---|
2527 | pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
|
---|
2528 | }
|
---|
2529 | # else
|
---|
2530 | AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
|
---|
2531 | ("ring-1 code not supported\n"));
|
---|
2532 | # endif
|
---|
2533 | /*
|
---|
2534 | * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
|
---|
2535 | */
|
---|
2536 | PATMRawEnter(pVM, pCtxCore);
|
---|
2537 | }
|
---|
2538 |
|
---|
2539 | /*
|
---|
2540 | * Assert sanity.
|
---|
2541 | */
|
---|
2542 | AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
|
---|
2543 | AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
|
---|
2544 | ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
|
---|
2545 | Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
|
---|
2546 |
|
---|
2547 | pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
|
---|
2548 |
|
---|
2549 | pVCpu->cpum.s.fRawEntered = true;
|
---|
2550 | return VINF_SUCCESS;
|
---|
2551 | }
|
---|
2552 |
|
---|
2553 |
|
---|
2554 | /**
|
---|
2555 | * Transforms the guest CPU state from raw-ring mode to correct values.
|
---|
2556 | *
|
---|
2557 | * This function will change any selector registers with DPL=1 to DPL=0.
|
---|
2558 | *
|
---|
2559 | * @returns Adjusted rc.
|
---|
2560 | * @param pVCpu Pointer to the VMCPU.
|
---|
2561 | * @param rc Raw mode return code
|
---|
2562 | * @param pCtxCore The context core (for trap usage).
|
---|
2563 | * @see @ref pg_raw
|
---|
2564 | */
|
---|
2565 | VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
|
---|
2566 | {
|
---|
2567 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
2568 |
|
---|
2569 | /*
|
---|
2570 | * Don't leave if we've already left (in RC).
|
---|
2571 | */
|
---|
2572 | Assert(!pVCpu->cpum.s.fRemEntered);
|
---|
2573 | if (!pVCpu->cpum.s.fRawEntered)
|
---|
2574 | return rc;
|
---|
2575 | pVCpu->cpum.s.fRawEntered = false;
|
---|
2576 |
|
---|
2577 | PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
|
---|
2578 | if (!pCtxCore)
|
---|
2579 | pCtxCore = CPUMCTX2CORE(pCtx);
|
---|
2580 | Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
|
---|
2581 | AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
|
---|
2582 | ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
|
---|
2583 |
|
---|
2584 | /*
|
---|
2585 | * Are we executing in raw ring-1?
|
---|
2586 | */
|
---|
2587 | if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
|
---|
2588 | && !pCtxCore->eflags.Bits.u1VM)
|
---|
2589 | {
|
---|
2590 | /*
|
---|
2591 | * Leave execution mode.
|
---|
2592 | */
|
---|
2593 | PATMRawLeave(pVM, pCtxCore, rc);
|
---|
2594 | /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
|
---|
2595 | /** @todo See what happens if we remove this. */
|
---|
2596 | if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
|
---|
2597 | pCtxCore->ds.Sel &= ~X86_SEL_RPL;
|
---|
2598 | if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
|
---|
2599 | pCtxCore->es.Sel &= ~X86_SEL_RPL;
|
---|
2600 | if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
|
---|
2601 | pCtxCore->fs.Sel &= ~X86_SEL_RPL;
|
---|
2602 | if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
|
---|
2603 | pCtxCore->gs.Sel &= ~X86_SEL_RPL;
|
---|
2604 |
|
---|
2605 | /*
|
---|
2606 | * Ring-1 selector => Ring-0.
|
---|
2607 | */
|
---|
2608 | pCtxCore->ss.Sel &= ~X86_SEL_RPL;
|
---|
2609 | if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
|
---|
2610 | pCtxCore->cs.Sel &= ~X86_SEL_RPL;
|
---|
2611 | }
|
---|
2612 | else
|
---|
2613 | {
|
---|
2614 | /*
|
---|
2615 | * PATM is taking care of the IOPL and IF flags for us.
|
---|
2616 | */
|
---|
2617 | PATMRawLeave(pVM, pCtxCore, rc);
|
---|
2618 | if (!pCtxCore->eflags.Bits.u1VM)
|
---|
2619 | {
|
---|
2620 | # ifdef VBOX_WITH_RAW_RING1
|
---|
2621 | if ( EMIsRawRing1Enabled(pVM)
|
---|
2622 | && (pCtxCore->ss.Sel & X86_SEL_RPL) == 2)
|
---|
2623 | {
|
---|
2624 | /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
|
---|
2625 | /** @todo See what happens if we remove this. */
|
---|
2626 | if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 2)
|
---|
2627 | pCtxCore->ds.Sel = (pCtxCore->ds.Sel & ~X86_SEL_RPL) | 1;
|
---|
2628 | if ((pCtxCore->es.Sel & X86_SEL_RPL) == 2)
|
---|
2629 | pCtxCore->es.Sel = (pCtxCore->es.Sel & ~X86_SEL_RPL) | 1;
|
---|
2630 | if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 2)
|
---|
2631 | pCtxCore->fs.Sel = (pCtxCore->fs.Sel & ~X86_SEL_RPL) | 1;
|
---|
2632 | if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 2)
|
---|
2633 | pCtxCore->gs.Sel = (pCtxCore->gs.Sel & ~X86_SEL_RPL) | 1;
|
---|
2634 |
|
---|
2635 | /*
|
---|
2636 | * Ring-2 selector => Ring-1.
|
---|
2637 | */
|
---|
2638 | pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 1;
|
---|
2639 | if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 2)
|
---|
2640 | pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 1;
|
---|
2641 | }
|
---|
2642 | else
|
---|
2643 | {
|
---|
2644 | # endif
|
---|
2645 | /** @todo See what happens if we remove this. */
|
---|
2646 | if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
|
---|
2647 | pCtxCore->ds.Sel &= ~X86_SEL_RPL;
|
---|
2648 | if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
|
---|
2649 | pCtxCore->es.Sel &= ~X86_SEL_RPL;
|
---|
2650 | if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
|
---|
2651 | pCtxCore->fs.Sel &= ~X86_SEL_RPL;
|
---|
2652 | if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
|
---|
2653 | pCtxCore->gs.Sel &= ~X86_SEL_RPL;
|
---|
2654 | # ifdef VBOX_WITH_RAW_RING1
|
---|
2655 | }
|
---|
2656 | # endif
|
---|
2657 | }
|
---|
2658 | }
|
---|
2659 |
|
---|
2660 | return rc;
|
---|
2661 | }
|
---|
2662 |
|
---|
2663 | #endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
|
---|
2664 |
|
---|
2665 | /**
|
---|
2666 | * Updates the EFLAGS while we're in raw-mode.
|
---|
2667 | *
|
---|
2668 | * @param pVCpu Pointer to the VMCPU.
|
---|
2669 | * @param fEfl The new EFLAGS value.
|
---|
2670 | */
|
---|
2671 | VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
|
---|
2672 | {
|
---|
2673 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
2674 | if (pVCpu->cpum.s.fRawEntered)
|
---|
2675 | PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
|
---|
2676 | else
|
---|
2677 | #endif
|
---|
2678 | pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
|
---|
2679 | }
|
---|
2680 |
|
---|
2681 |
|
---|
2682 | /**
|
---|
2683 | * Gets the EFLAGS while we're in raw-mode.
|
---|
2684 | *
|
---|
2685 | * @returns The eflags.
|
---|
2686 | * @param pVCpu Pointer to the current virtual CPU.
|
---|
2687 | */
|
---|
2688 | VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
|
---|
2689 | {
|
---|
2690 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
2691 | if (pVCpu->cpum.s.fRawEntered)
|
---|
2692 | return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
|
---|
2693 | #endif
|
---|
2694 | return pVCpu->cpum.s.Guest.eflags.u32;
|
---|
2695 | }
|
---|
2696 |
|
---|
2697 |
|
---|
2698 | /**
|
---|
2699 | * Sets the specified changed flags (CPUM_CHANGED_*).
|
---|
2700 | *
|
---|
2701 | * @param pVCpu Pointer to the current virtual CPU.
|
---|
2702 | */
|
---|
2703 | VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
|
---|
2704 | {
|
---|
2705 | pVCpu->cpum.s.fChanged |= fChangedFlags;
|
---|
2706 | }
|
---|
2707 |
|
---|
2708 |
|
---|
2709 | /**
|
---|
2710 | * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
|
---|
2711 | * @returns true if supported.
|
---|
2712 | * @returns false if not supported.
|
---|
2713 | * @param pVM Pointer to the VM.
|
---|
2714 | */
|
---|
2715 | VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
|
---|
2716 | {
|
---|
2717 | return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
|
---|
2718 | }
|
---|
2719 |
|
---|
2720 |
|
---|
2721 | /**
|
---|
2722 | * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
|
---|
2723 | * @returns true if used.
|
---|
2724 | * @returns false if not used.
|
---|
2725 | * @param pVM Pointer to the VM.
|
---|
2726 | */
|
---|
2727 | VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
|
---|
2728 | {
|
---|
2729 | return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
|
---|
2730 | }
|
---|
2731 |
|
---|
2732 |
|
---|
2733 | /**
|
---|
2734 | * Checks if the host OS uses the SYSCALL / SYSRET instructions.
|
---|
2735 | * @returns true if used.
|
---|
2736 | * @returns false if not used.
|
---|
2737 | * @param pVM Pointer to the VM.
|
---|
2738 | */
|
---|
2739 | VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
|
---|
2740 | {
|
---|
2741 | return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
|
---|
2742 | }
|
---|
2743 |
|
---|
2744 | #ifndef IN_RING3
|
---|
2745 |
|
---|
2746 | /**
|
---|
2747 | * Lazily sync in the FPU/XMM state.
|
---|
2748 | *
|
---|
2749 | * @returns VBox status code.
|
---|
2750 | * @param pVCpu Pointer to the VMCPU.
|
---|
2751 | */
|
---|
2752 | VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
|
---|
2753 | {
|
---|
2754 | return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
|
---|
2755 | }
|
---|
2756 |
|
---|
2757 | #endif /* !IN_RING3 */
|
---|
2758 |
|
---|
2759 | /**
|
---|
2760 | * Checks if we activated the FPU/XMM state of the guest OS.
|
---|
2761 | * @returns true if we did.
|
---|
2762 | * @returns false if not.
|
---|
2763 | * @param pVCpu Pointer to the VMCPU.
|
---|
2764 | */
|
---|
2765 | VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
|
---|
2766 | {
|
---|
2767 | return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
|
---|
2768 | }
|
---|
2769 |
|
---|
2770 |
|
---|
2771 | /**
|
---|
2772 | * Deactivate the FPU/XMM state of the guest OS.
|
---|
2773 | * @param pVCpu Pointer to the VMCPU.
|
---|
2774 | */
|
---|
2775 | VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
|
---|
2776 | {
|
---|
2777 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
|
---|
2778 | }
|
---|
2779 |
|
---|
2780 |
|
---|
2781 | /**
|
---|
2782 | * Checks if the guest debug state is active.
|
---|
2783 | *
|
---|
2784 | * @returns boolean
|
---|
2785 | * @param pVM Pointer to the VM.
|
---|
2786 | */
|
---|
2787 | VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
|
---|
2788 | {
|
---|
2789 | return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
|
---|
2790 | }
|
---|
2791 |
|
---|
2792 | /**
|
---|
2793 | * Checks if the hyper debug state is active.
|
---|
2794 | *
|
---|
2795 | * @returns boolean
|
---|
2796 | * @param pVM Pointer to the VM.
|
---|
2797 | */
|
---|
2798 | VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
|
---|
2799 | {
|
---|
2800 | return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
|
---|
2801 | }
|
---|
2802 |
|
---|
2803 |
|
---|
2804 | /**
|
---|
2805 | * Mark the guest's debug state as inactive.
|
---|
2806 | *
|
---|
2807 | * @returns boolean
|
---|
2808 | * @param pVM Pointer to the VM.
|
---|
2809 | */
|
---|
2810 | VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
|
---|
2811 | {
|
---|
2812 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
|
---|
2813 | }
|
---|
2814 |
|
---|
2815 |
|
---|
2816 | /**
|
---|
2817 | * Mark the hypervisor's debug state as inactive.
|
---|
2818 | *
|
---|
2819 | * @returns boolean
|
---|
2820 | * @param pVM Pointer to the VM.
|
---|
2821 | */
|
---|
2822 | VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
|
---|
2823 | {
|
---|
2824 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
|
---|
2825 | }
|
---|
2826 |
|
---|
2827 |
|
---|
2828 | /**
|
---|
2829 | * Get the current privilege level of the guest.
|
---|
2830 | *
|
---|
2831 | * @returns CPL
|
---|
2832 | * @param pVCpu Pointer to the current virtual CPU.
|
---|
2833 | */
|
---|
2834 | VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
|
---|
2835 | {
|
---|
2836 | /*
|
---|
2837 | * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
|
---|
2838 | *
|
---|
2839 | * Note! We used to check CS.DPL here, assuming it was always equal to
|
---|
2840 | * CPL even if a conforming segment was loaded. But this truned out to
|
---|
2841 | * only apply to older AMD-V. With VT-x we had an ACP2 regression
|
---|
2842 | * during install after a far call to ring 2 with VT-x. Then on newer
|
---|
2843 | * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
|
---|
2844 | * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
|
---|
2845 | *
|
---|
2846 | * So, forget CS.DPL, always use SS.DPL.
|
---|
2847 | *
|
---|
2848 | * Note! The SS RPL is always equal to the CPL, while the CS RPL
|
---|
2849 | * isn't necessarily equal if the segment is conforming.
|
---|
2850 | * See section 4.11.1 in the AMD manual.
|
---|
2851 | */
|
---|
2852 | uint32_t uCpl;
|
---|
2853 | if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
|
---|
2854 | {
|
---|
2855 | if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
2856 | {
|
---|
2857 | if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
|
---|
2858 | uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
|
---|
2859 | else
|
---|
2860 | {
|
---|
2861 | uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
|
---|
2862 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
2863 | # ifdef VBOX_WITH_RAW_RING1
|
---|
2864 | if (pVCpu->cpum.s.fRawEntered)
|
---|
2865 | {
|
---|
2866 | if ( uCpl == 2
|
---|
2867 | && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)))
|
---|
2868 | uCpl = 1;
|
---|
2869 | else if (uCpl == 1)
|
---|
2870 | uCpl = 0;
|
---|
2871 | }
|
---|
2872 | Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
|
---|
2873 | # else
|
---|
2874 | if (uCpl == 1)
|
---|
2875 | uCpl = 0;
|
---|
2876 | # endif
|
---|
2877 | #endif
|
---|
2878 | }
|
---|
2879 | }
|
---|
2880 | else
|
---|
2881 | uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
|
---|
2882 | }
|
---|
2883 | else
|
---|
2884 | uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
|
---|
2885 | return uCpl;
|
---|
2886 | }
|
---|
2887 |
|
---|
2888 |
|
---|
2889 | /**
|
---|
2890 | * Gets the current guest CPU mode.
|
---|
2891 | *
|
---|
2892 | * If paging mode is what you need, check out PGMGetGuestMode().
|
---|
2893 | *
|
---|
2894 | * @returns The CPU mode.
|
---|
2895 | * @param pVCpu Pointer to the VMCPU.
|
---|
2896 | */
|
---|
2897 | VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
|
---|
2898 | {
|
---|
2899 | CPUMMODE enmMode;
|
---|
2900 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
2901 | enmMode = CPUMMODE_REAL;
|
---|
2902 | else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
2903 | enmMode = CPUMMODE_PROTECTED;
|
---|
2904 | else
|
---|
2905 | enmMode = CPUMMODE_LONG;
|
---|
2906 |
|
---|
2907 | return enmMode;
|
---|
2908 | }
|
---|
2909 |
|
---|
2910 |
|
---|
2911 | /**
|
---|
2912 | * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
|
---|
2913 | *
|
---|
2914 | * @returns 16, 32 or 64.
|
---|
2915 | * @param pVCpu The current virtual CPU.
|
---|
2916 | */
|
---|
2917 | VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
|
---|
2918 | {
|
---|
2919 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
2920 | return 16;
|
---|
2921 |
|
---|
2922 | if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
2923 | {
|
---|
2924 | Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
|
---|
2925 | return 16;
|
---|
2926 | }
|
---|
2927 |
|
---|
2928 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
2929 | if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
|
---|
2930 | && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
2931 | return 64;
|
---|
2932 |
|
---|
2933 | if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
|
---|
2934 | return 32;
|
---|
2935 |
|
---|
2936 | return 16;
|
---|
2937 | }
|
---|
2938 |
|
---|
2939 |
|
---|
2940 | VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
|
---|
2941 | {
|
---|
2942 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
2943 | return DISCPUMODE_16BIT;
|
---|
2944 |
|
---|
2945 | if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
2946 | {
|
---|
2947 | Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
|
---|
2948 | return DISCPUMODE_16BIT;
|
---|
2949 | }
|
---|
2950 |
|
---|
2951 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
2952 | if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
|
---|
2953 | && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
2954 | return DISCPUMODE_64BIT;
|
---|
2955 |
|
---|
2956 | if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
|
---|
2957 | return DISCPUMODE_32BIT;
|
---|
2958 |
|
---|
2959 | return DISCPUMODE_16BIT;
|
---|
2960 | }
|
---|
2961 |
|
---|