VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 41975

Last change on this file since 41975 was 41965, checked in by vboxsync, 13 years ago

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1/* $Id: CPUMAllRegs.cpp 41965 2012-06-29 02:52:49Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include "CPUMInternal.h"
30#include <VBox/vmm/vm.h>
31#include <VBox/err.h>
32#include <VBox/dis.h>
33#include <VBox/log.h>
34#include <VBox/vmm/hwaccm.h>
35#include <VBox/vmm/tm.h>
36#include <iprt/assert.h>
37#include <iprt/asm.h>
38#include <iprt/asm-amd64-x86.h>
39#ifdef IN_RING3
40#include <iprt/thread.h>
41#endif
42
43/** Disable stack frame pointer generation here. */
44#if defined(_MSC_VER) && !defined(DEBUG)
45# pragma optimize("y", off)
46#endif
47
48
49/**
50 * Obsolete.
51 *
52 * We don't support nested hypervisor context interrupts or traps. Life is much
53 * simpler when we don't. It's also slightly faster at times.
54 *
55 * @param pVM Handle to the virtual machine.
56 */
57VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
58{
59 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
60}
61
62
63/**
64 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
65 *
66 * @param pVCpu Pointer to the virtual CPU.
67 */
68VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
69{
70 return &pVCpu->cpum.s.Hyper;
71}
72
73
74VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
75{
76 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
77 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
78}
79
80
81VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
82{
83 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
84 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
85}
86
87
88VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
89{
90 pVCpu->cpum.s.Hyper.cr3 = cr3;
91
92#ifdef IN_RC
93 /* Update the current CR3. */
94 ASMSetCR3(cr3);
95#endif
96}
97
98VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
99{
100 return pVCpu->cpum.s.Hyper.cr3;
101}
102
103
104VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
105{
106 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
107}
108
109
110VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
111{
112 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
113}
114
115
116VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
117{
118 pVCpu->cpum.s.Hyper.es.Sel = SelES;
119}
120
121
122VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
123{
124 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
125}
126
127
128VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
129{
130 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
131}
132
133
134VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
135{
136 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
137}
138
139
140VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
141{
142 pVCpu->cpum.s.Hyper.esp = u32ESP;
143}
144
145
146VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
147{
148 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
149 return VINF_SUCCESS;
150}
151
152
153VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
154{
155 pVCpu->cpum.s.Hyper.eip = u32EIP;
156}
157
158
159VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
160{
161 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
162}
163
164
165VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
166{
167 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
168}
169
170
171VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
172{
173 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
174 /** @todo in GC we must load it! */
175}
176
177
178VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
179{
180 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
181 /** @todo in GC we must load it! */
182}
183
184
185VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
186{
187 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
188 /** @todo in GC we must load it! */
189}
190
191
192VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
193{
194 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
195 /** @todo in GC we must load it! */
196}
197
198
199VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
200{
201 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
202 /** @todo in GC we must load it! */
203}
204
205
206VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
207{
208 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
209 /** @todo in GC we must load it! */
210}
211
212
213VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
214{
215 return pVCpu->cpum.s.Hyper.cs.Sel;
216}
217
218
219VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
220{
221 return pVCpu->cpum.s.Hyper.ds.Sel;
222}
223
224
225VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
226{
227 return pVCpu->cpum.s.Hyper.es.Sel;
228}
229
230
231VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
232{
233 return pVCpu->cpum.s.Hyper.fs.Sel;
234}
235
236
237VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
238{
239 return pVCpu->cpum.s.Hyper.gs.Sel;
240}
241
242
243VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
244{
245 return pVCpu->cpum.s.Hyper.ss.Sel;
246}
247
248
249VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
250{
251 return pVCpu->cpum.s.Hyper.eax;
252}
253
254
255VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
256{
257 return pVCpu->cpum.s.Hyper.ebx;
258}
259
260
261VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
262{
263 return pVCpu->cpum.s.Hyper.ecx;
264}
265
266
267VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
268{
269 return pVCpu->cpum.s.Hyper.edx;
270}
271
272
273VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
274{
275 return pVCpu->cpum.s.Hyper.esi;
276}
277
278
279VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
280{
281 return pVCpu->cpum.s.Hyper.edi;
282}
283
284
285VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
286{
287 return pVCpu->cpum.s.Hyper.ebp;
288}
289
290
291VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
292{
293 return pVCpu->cpum.s.Hyper.esp;
294}
295
296
297VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
298{
299 return pVCpu->cpum.s.Hyper.eflags.u32;
300}
301
302
303VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
304{
305 return pVCpu->cpum.s.Hyper.eip;
306}
307
308
309VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
310{
311 return pVCpu->cpum.s.Hyper.rip;
312}
313
314
315VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
316{
317 if (pcbLimit)
318 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
319 return pVCpu->cpum.s.Hyper.idtr.pIdt;
320}
321
322
323VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
324{
325 if (pcbLimit)
326 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
327 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
328}
329
330
331VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
332{
333 return pVCpu->cpum.s.Hyper.ldtr.Sel;
334}
335
336
337VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
338{
339 return pVCpu->cpum.s.Hyper.dr[0];
340}
341
342
343VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
344{
345 return pVCpu->cpum.s.Hyper.dr[1];
346}
347
348
349VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
350{
351 return pVCpu->cpum.s.Hyper.dr[2];
352}
353
354
355VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
356{
357 return pVCpu->cpum.s.Hyper.dr[3];
358}
359
360
361VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
362{
363 return pVCpu->cpum.s.Hyper.dr[6];
364}
365
366
367VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
368{
369 return pVCpu->cpum.s.Hyper.dr[7];
370}
371
372
373/**
374 * Gets the pointer to the internal CPUMCTXCORE structure.
375 * This is only for reading in order to save a few calls.
376 *
377 * @param pVCpu Handle to the virtual cpu.
378 */
379VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
380{
381 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
382}
383
384
385/**
386 * Queries the pointer to the internal CPUMCTX structure
387 *
388 * @returns The CPUMCTX pointer.
389 * @param pVCpu Handle to the virtual cpu.
390 */
391VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
392{
393 return &pVCpu->cpum.s.Guest;
394}
395
396VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
397{
398 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
399 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
400 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
401 return VINF_SUCCESS;
402}
403
404VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
405{
406 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
407 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
408 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
409 return VINF_SUCCESS;
410}
411
412VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
413{
414 pVCpu->cpum.s.Guest.tr.Sel = tr;
415 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
416 return VINF_SUCCESS;
417}
418
419VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
420{
421 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
422 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
423 return VINF_SUCCESS;
424}
425
426
427/**
428 * Set the guest CR0.
429 *
430 * When called in GC, the hyper CR0 may be updated if that is
431 * required. The caller only has to take special action if AM,
432 * WP, PG or PE changes.
433 *
434 * @returns VINF_SUCCESS (consider it void).
435 * @param pVCpu Handle to the virtual cpu.
436 * @param cr0 The new CR0 value.
437 */
438VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
439{
440#ifdef IN_RC
441 /*
442 * Check if we need to change hypervisor CR0 because
443 * of math stuff.
444 */
445 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
446 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
447 {
448 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
449 {
450 /*
451 * We haven't saved the host FPU state yet, so TS and MT are both set
452 * and EM should be reflecting the guest EM (it always does this).
453 */
454 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
455 {
456 uint32_t HyperCR0 = ASMGetCR0();
457 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
458 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
459 HyperCR0 &= ~X86_CR0_EM;
460 HyperCR0 |= cr0 & X86_CR0_EM;
461 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
462 ASMSetCR0(HyperCR0);
463 }
464# ifdef VBOX_STRICT
465 else
466 {
467 uint32_t HyperCR0 = ASMGetCR0();
468 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
469 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
470 }
471# endif
472 }
473 else
474 {
475 /*
476 * Already saved the state, so we're just mirroring
477 * the guest flags.
478 */
479 uint32_t HyperCR0 = ASMGetCR0();
480 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
481 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
482 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
483 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
484 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
485 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
486 ASMSetCR0(HyperCR0);
487 }
488 }
489#endif /* IN_RC */
490
491 /*
492 * Check for changes causing TLB flushes (for REM).
493 * The caller is responsible for calling PGM when appropriate.
494 */
495 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
496 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
497 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
498 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
499
500 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
501 return VINF_SUCCESS;
502}
503
504
505VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
506{
507 pVCpu->cpum.s.Guest.cr2 = cr2;
508 return VINF_SUCCESS;
509}
510
511
512VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
513{
514 pVCpu->cpum.s.Guest.cr3 = cr3;
515 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
516 return VINF_SUCCESS;
517}
518
519
520VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
521{
522 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
523 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
524 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
525 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
526 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
527 cr4 &= ~X86_CR4_OSFSXR;
528 pVCpu->cpum.s.Guest.cr4 = cr4;
529 return VINF_SUCCESS;
530}
531
532
533VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
534{
535 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
536 return VINF_SUCCESS;
537}
538
539
540VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
541{
542 pVCpu->cpum.s.Guest.eip = eip;
543 return VINF_SUCCESS;
544}
545
546
547VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
548{
549 pVCpu->cpum.s.Guest.eax = eax;
550 return VINF_SUCCESS;
551}
552
553
554VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
555{
556 pVCpu->cpum.s.Guest.ebx = ebx;
557 return VINF_SUCCESS;
558}
559
560
561VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
562{
563 pVCpu->cpum.s.Guest.ecx = ecx;
564 return VINF_SUCCESS;
565}
566
567
568VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
569{
570 pVCpu->cpum.s.Guest.edx = edx;
571 return VINF_SUCCESS;
572}
573
574
575VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
576{
577 pVCpu->cpum.s.Guest.esp = esp;
578 return VINF_SUCCESS;
579}
580
581
582VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
583{
584 pVCpu->cpum.s.Guest.ebp = ebp;
585 return VINF_SUCCESS;
586}
587
588
589VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
590{
591 pVCpu->cpum.s.Guest.esi = esi;
592 return VINF_SUCCESS;
593}
594
595
596VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
597{
598 pVCpu->cpum.s.Guest.edi = edi;
599 return VINF_SUCCESS;
600}
601
602
603VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
604{
605 pVCpu->cpum.s.Guest.ss.Sel = ss;
606 return VINF_SUCCESS;
607}
608
609
610VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
611{
612 pVCpu->cpum.s.Guest.cs.Sel = cs;
613 return VINF_SUCCESS;
614}
615
616
617VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
618{
619 pVCpu->cpum.s.Guest.ds.Sel = ds;
620 return VINF_SUCCESS;
621}
622
623
624VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
625{
626 pVCpu->cpum.s.Guest.es.Sel = es;
627 return VINF_SUCCESS;
628}
629
630
631VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
632{
633 pVCpu->cpum.s.Guest.fs.Sel = fs;
634 return VINF_SUCCESS;
635}
636
637
638VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
639{
640 pVCpu->cpum.s.Guest.gs.Sel = gs;
641 return VINF_SUCCESS;
642}
643
644
645VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
646{
647 pVCpu->cpum.s.Guest.msrEFER = val;
648}
649
650
651/**
652 * Query an MSR.
653 *
654 * The caller is responsible for checking privilege if the call is the result
655 * of a RDMSR instruction. We'll do the rest.
656 *
657 * @retval VINF_SUCCESS on success.
658 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
659 * expected to take the appropriate actions. @a *puValue is set to 0.
660 * @param pVCpu Pointer to the VMCPU.
661 * @param idMsr The MSR.
662 * @param puValue Where to return the value.
663 *
664 * @remarks This will always return the right values, even when we're in the
665 * recompiler.
666 */
667VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
668{
669 /*
670 * If we don't indicate MSR support in the CPUID feature bits, indicate
671 * that a #GP(0) should be raised.
672 */
673 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
674 {
675 *puValue = 0;
676 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
677 }
678
679 int rc = VINF_SUCCESS;
680 uint8_t const u8Multiplier = 4;
681 switch (idMsr)
682 {
683 case MSR_IA32_TSC:
684 *puValue = TMCpuTickGet(pVCpu);
685 break;
686
687 case MSR_IA32_APICBASE:
688 rc = PDMApicGetBase(pVCpu->CTX_SUFF(pVM), puValue);
689 if (RT_SUCCESS(rc))
690 rc = VINF_SUCCESS;
691 else
692 {
693 *puValue = 0;
694 rc = VERR_CPUM_RAISE_GP_0;
695 }
696 break;
697
698 case MSR_IA32_CR_PAT:
699 *puValue = pVCpu->cpum.s.Guest.msrPAT;
700 break;
701
702 case MSR_IA32_SYSENTER_CS:
703 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
704 break;
705
706 case MSR_IA32_SYSENTER_EIP:
707 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
708 break;
709
710 case MSR_IA32_SYSENTER_ESP:
711 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
712 break;
713
714 case MSR_IA32_MTRR_CAP:
715 {
716 /* This is currently a bit weird. :-) */
717 uint8_t const cVariableRangeRegs = 0;
718 bool const fSystemManagementRangeRegisters = false;
719 bool const fFixedRangeRegisters = false;
720 bool const fWriteCombiningType = false;
721 *puValue = cVariableRangeRegs
722 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
723 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
724 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
725 break;
726 }
727
728 case MSR_IA32_MTRR_DEF_TYPE:
729 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
730 break;
731
732 case IA32_MTRR_FIX64K_00000:
733 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
734 break;
735 case IA32_MTRR_FIX16K_80000:
736 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
737 break;
738 case IA32_MTRR_FIX16K_A0000:
739 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
740 break;
741 case IA32_MTRR_FIX4K_C0000:
742 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
743 break;
744 case IA32_MTRR_FIX4K_C8000:
745 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
746 break;
747 case IA32_MTRR_FIX4K_D0000:
748 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
749 break;
750 case IA32_MTRR_FIX4K_D8000:
751 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
752 break;
753 case IA32_MTRR_FIX4K_E0000:
754 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
755 break;
756 case IA32_MTRR_FIX4K_E8000:
757 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
758 break;
759 case IA32_MTRR_FIX4K_F0000:
760 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
761 break;
762 case IA32_MTRR_FIX4K_F8000:
763 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
764 break;
765
766 case MSR_K6_EFER:
767 *puValue = pVCpu->cpum.s.Guest.msrEFER;
768 break;
769
770 case MSR_K8_SF_MASK:
771 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
772 break;
773
774 case MSR_K6_STAR:
775 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
776 break;
777
778 case MSR_K8_LSTAR:
779 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
780 break;
781
782 case MSR_K8_CSTAR:
783 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
784 break;
785
786 case MSR_K8_FS_BASE:
787 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
788 break;
789
790 case MSR_K8_GS_BASE:
791 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
792 break;
793
794 case MSR_K8_KERNEL_GS_BASE:
795 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
796 break;
797
798 case MSR_K8_TSC_AUX:
799 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
800 break;
801
802 case MSR_IA32_PERF_STATUS:
803 /** @todo could really be not exactly correct, maybe use host's values */
804 *puValue = UINT64_C(1000) /* TSC increment by tick */
805 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
806 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
807 break;
808
809 case MSR_IA32_FSB_CLOCK_STS:
810 /*
811 * Encoded as:
812 * 0 - 266
813 * 1 - 133
814 * 2 - 200
815 * 3 - return 166
816 * 5 - return 100
817 */
818 *puValue = (2 << 4);
819 break;
820
821 case MSR_IA32_PLATFORM_INFO:
822 *puValue = (u8Multiplier << 8) /* Flex ratio max */
823 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
824 break;
825
826 case MSR_IA32_THERM_STATUS:
827 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
828 *puValue = RT_BIT(31) /* validity bit */
829 | (UINT64_C(20) << 16) /* degrees till TCC */;
830 break;
831
832 case MSR_IA32_MISC_ENABLE:
833#if 0
834 /* Needs to be tested more before enabling. */
835 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
836#else
837 /* Currenty we don't allow guests to modify enable MSRs. */
838 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
839
840 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
841
842 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
843 /** @todo: add more cpuid-controlled features this way. */
844#endif
845 break;
846
847#if 0 /*def IN_RING0 */
848 case MSR_IA32_PLATFORM_ID:
849 case MSR_IA32_BIOS_SIGN_ID:
850 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
851 {
852 /* Available since the P6 family. VT-x implies that this feature is present. */
853 if (idMsr == MSR_IA32_PLATFORM_ID)
854 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
855 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
856 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
857 break;
858 }
859 /* no break */
860#endif
861
862 default:
863 /* In X2APIC specification this range is reserved for APIC control. */
864 if ( idMsr >= MSR_IA32_APIC_START
865 && idMsr < MSR_IA32_APIC_END)
866 {
867 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
868 if (RT_SUCCESS(rc))
869 rc = VINF_SUCCESS;
870 else
871 {
872 *puValue = 0;
873 rc = VERR_CPUM_RAISE_GP_0;
874 }
875 }
876 else
877 {
878 *puValue = 0;
879 rc = VERR_CPUM_RAISE_GP_0;
880 }
881 break;
882 }
883
884 return rc;
885}
886
887
888/**
889 * Sets the MSR.
890 *
891 * The caller is responsible for checking privilege if the call is the result
892 * of a WRMSR instruction. We'll do the rest.
893 *
894 * @retval VINF_SUCCESS on success.
895 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
896 * appropriate actions.
897 *
898 * @param pVCpu Pointer to the VMCPU.
899 * @param idMsr The MSR id.
900 * @param uValue The value to set.
901 *
902 * @remarks Everyone changing MSR values, including the recompiler, shall do it
903 * by calling this method. This makes sure we have current values and
904 * that we trigger all the right actions when something changes.
905 */
906VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
907{
908 /*
909 * If we don't indicate MSR support in the CPUID feature bits, indicate
910 * that a #GP(0) should be raised.
911 */
912 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
913 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
914
915 int rc = VINF_SUCCESS;
916 switch (idMsr)
917 {
918 case MSR_IA32_MISC_ENABLE:
919 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
920 break;
921
922 case MSR_IA32_TSC:
923 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
924 break;
925
926 case MSR_IA32_APICBASE:
927 rc = PDMApicSetBase(pVCpu->CTX_SUFF(pVM), uValue);
928 if (rc != VINF_SUCCESS)
929 rc = VERR_CPUM_RAISE_GP_0;
930 break;
931
932 case MSR_IA32_CR_PAT:
933 pVCpu->cpum.s.Guest.msrPAT = uValue;
934 break;
935
936 case MSR_IA32_SYSENTER_CS:
937 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
938 break;
939
940 case MSR_IA32_SYSENTER_EIP:
941 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
942 break;
943
944 case MSR_IA32_SYSENTER_ESP:
945 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
946 break;
947
948 case MSR_IA32_MTRR_CAP:
949 return VERR_CPUM_RAISE_GP_0;
950
951 case MSR_IA32_MTRR_DEF_TYPE:
952 if ( (uValue & UINT64_C(0xfffffffffffff300))
953 || ( (uValue & 0xff) != 0
954 && (uValue & 0xff) != 1
955 && (uValue & 0xff) != 4
956 && (uValue & 0xff) != 5
957 && (uValue & 0xff) != 6) )
958 {
959 Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
960 return VERR_CPUM_RAISE_GP_0;
961 }
962 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
963 break;
964
965 case IA32_MTRR_FIX64K_00000:
966 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
967 break;
968 case IA32_MTRR_FIX16K_80000:
969 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
970 break;
971 case IA32_MTRR_FIX16K_A0000:
972 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
973 break;
974 case IA32_MTRR_FIX4K_C0000:
975 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
976 break;
977 case IA32_MTRR_FIX4K_C8000:
978 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
979 break;
980 case IA32_MTRR_FIX4K_D0000:
981 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
982 break;
983 case IA32_MTRR_FIX4K_D8000:
984 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
985 break;
986 case IA32_MTRR_FIX4K_E0000:
987 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
988 break;
989 case IA32_MTRR_FIX4K_E8000:
990 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
991 break;
992 case IA32_MTRR_FIX4K_F0000:
993 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
994 break;
995 case IA32_MTRR_FIX4K_F8000:
996 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
997 break;
998
999 case MSR_K6_EFER:
1000 {
1001 PVM pVM = pVCpu->CTX_SUFF(pVM);
1002 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1003 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1004 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1005 : 0;
1006 uint64_t fMask = 0;
1007
1008 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1009 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_NX)
1010 fMask |= MSR_K6_EFER_NXE;
1011 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1012 fMask |= MSR_K6_EFER_LME;
1013 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_SEP)
1014 fMask |= MSR_K6_EFER_SCE;
1015 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1016 fMask |= MSR_K6_EFER_FFXSR;
1017
1018 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1019 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1020 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1021 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1022 {
1023 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1024 return VERR_CPUM_RAISE_GP_0;
1025 }
1026
1027 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1028 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1029 ("Unexpected value %RX64\n", uValue));
1030 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1031
1032 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1033 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1034 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1035 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1036 {
1037 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1038 HWACCMFlushTLB(pVCpu);
1039
1040 /* Notify PGM about NXE changes. */
1041 if ( (uOldEFER & MSR_K6_EFER_NXE)
1042 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1043 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1044 }
1045 break;
1046 }
1047
1048 case MSR_K8_SF_MASK:
1049 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1050 break;
1051
1052 case MSR_K6_STAR:
1053 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1054 break;
1055
1056 case MSR_K8_LSTAR:
1057 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1058 break;
1059
1060 case MSR_K8_CSTAR:
1061 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1062 break;
1063
1064 case MSR_K8_FS_BASE:
1065 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1066 break;
1067
1068 case MSR_K8_GS_BASE:
1069 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1070 break;
1071
1072 case MSR_K8_KERNEL_GS_BASE:
1073 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1074 break;
1075
1076 case MSR_K8_TSC_AUX:
1077 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1078 break;
1079
1080 default:
1081 /* In X2APIC specification this range is reserved for APIC control. */
1082 if ( idMsr >= MSR_IA32_APIC_START
1083 && idMsr < MSR_IA32_APIC_END)
1084 {
1085 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1086 if (rc != VINF_SUCCESS)
1087 rc = VERR_CPUM_RAISE_GP_0;
1088 }
1089 else
1090 {
1091 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1092 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1093 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1094 }
1095 break;
1096 }
1097 return rc;
1098}
1099
1100
1101VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1102{
1103 if (pcbLimit)
1104 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1105 return pVCpu->cpum.s.Guest.idtr.pIdt;
1106}
1107
1108
1109VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1110{
1111 if (pHidden)
1112 *pHidden = pVCpu->cpum.s.Guest.tr;
1113 return pVCpu->cpum.s.Guest.tr.Sel;
1114}
1115
1116
1117VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1118{
1119 return pVCpu->cpum.s.Guest.cs.Sel;
1120}
1121
1122
1123VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1124{
1125 return pVCpu->cpum.s.Guest.ds.Sel;
1126}
1127
1128
1129VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1130{
1131 return pVCpu->cpum.s.Guest.es.Sel;
1132}
1133
1134
1135VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1136{
1137 return pVCpu->cpum.s.Guest.fs.Sel;
1138}
1139
1140
1141VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1142{
1143 return pVCpu->cpum.s.Guest.gs.Sel;
1144}
1145
1146
1147VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1148{
1149 return pVCpu->cpum.s.Guest.ss.Sel;
1150}
1151
1152
1153VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1154{
1155 return pVCpu->cpum.s.Guest.ldtr.Sel;
1156}
1157
1158
1159VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1160{
1161 return pVCpu->cpum.s.Guest.cr0;
1162}
1163
1164
1165VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1166{
1167 return pVCpu->cpum.s.Guest.cr2;
1168}
1169
1170
1171VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1172{
1173 return pVCpu->cpum.s.Guest.cr3;
1174}
1175
1176
1177VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1178{
1179 return pVCpu->cpum.s.Guest.cr4;
1180}
1181
1182
1183VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1184{
1185 uint64_t u64;
1186 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1187 if (RT_FAILURE(rc))
1188 u64 = 0;
1189 return u64;
1190}
1191
1192
1193VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1194{
1195 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1196}
1197
1198
1199VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1200{
1201 return pVCpu->cpum.s.Guest.eip;
1202}
1203
1204
1205VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1206{
1207 return pVCpu->cpum.s.Guest.rip;
1208}
1209
1210
1211VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1212{
1213 return pVCpu->cpum.s.Guest.eax;
1214}
1215
1216
1217VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1218{
1219 return pVCpu->cpum.s.Guest.ebx;
1220}
1221
1222
1223VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1224{
1225 return pVCpu->cpum.s.Guest.ecx;
1226}
1227
1228
1229VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1230{
1231 return pVCpu->cpum.s.Guest.edx;
1232}
1233
1234
1235VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1236{
1237 return pVCpu->cpum.s.Guest.esi;
1238}
1239
1240
1241VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1242{
1243 return pVCpu->cpum.s.Guest.edi;
1244}
1245
1246
1247VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1248{
1249 return pVCpu->cpum.s.Guest.esp;
1250}
1251
1252
1253VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1254{
1255 return pVCpu->cpum.s.Guest.ebp;
1256}
1257
1258
1259VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1260{
1261 return pVCpu->cpum.s.Guest.eflags.u32;
1262}
1263
1264
1265VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1266{
1267 switch (iReg)
1268 {
1269 case DISCREG_CR0:
1270 *pValue = pVCpu->cpum.s.Guest.cr0;
1271 break;
1272
1273 case DISCREG_CR2:
1274 *pValue = pVCpu->cpum.s.Guest.cr2;
1275 break;
1276
1277 case DISCREG_CR3:
1278 *pValue = pVCpu->cpum.s.Guest.cr3;
1279 break;
1280
1281 case DISCREG_CR4:
1282 *pValue = pVCpu->cpum.s.Guest.cr4;
1283 break;
1284
1285 case DISCREG_CR8:
1286 {
1287 uint8_t u8Tpr;
1288 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /*pfPending*/);
1289 if (RT_FAILURE(rc))
1290 {
1291 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1292 *pValue = 0;
1293 return rc;
1294 }
1295 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1296 break;
1297 }
1298
1299 default:
1300 return VERR_INVALID_PARAMETER;
1301 }
1302 return VINF_SUCCESS;
1303}
1304
1305
1306VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1307{
1308 return pVCpu->cpum.s.Guest.dr[0];
1309}
1310
1311
1312VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1313{
1314 return pVCpu->cpum.s.Guest.dr[1];
1315}
1316
1317
1318VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1319{
1320 return pVCpu->cpum.s.Guest.dr[2];
1321}
1322
1323
1324VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1325{
1326 return pVCpu->cpum.s.Guest.dr[3];
1327}
1328
1329
1330VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1331{
1332 return pVCpu->cpum.s.Guest.dr[6];
1333}
1334
1335
1336VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1337{
1338 return pVCpu->cpum.s.Guest.dr[7];
1339}
1340
1341
1342VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1343{
1344 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1345 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1346 if (iReg == 4 || iReg == 5)
1347 iReg += 2;
1348 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1349 return VINF_SUCCESS;
1350}
1351
1352
1353VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1354{
1355 return pVCpu->cpum.s.Guest.msrEFER;
1356}
1357
1358
1359/**
1360 * Gets a CpuId leaf.
1361 *
1362 * @param pVCpu Pointer to the VMCPU.
1363 * @param iLeaf The CPUID leaf to get.
1364 * @param pEax Where to store the EAX value.
1365 * @param pEbx Where to store the EBX value.
1366 * @param pEcx Where to store the ECX value.
1367 * @param pEdx Where to store the EDX value.
1368 */
1369VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1370{
1371 PVM pVM = pVCpu->CTX_SUFF(pVM);
1372
1373 PCCPUMCPUID pCpuId;
1374 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1375 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1376 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1377 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1378 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1379 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1380 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1381 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1382 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1383 else
1384 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1385
1386 uint32_t cCurrentCacheIndex = *pEcx;
1387
1388 *pEax = pCpuId->eax;
1389 *pEbx = pCpuId->ebx;
1390 *pEcx = pCpuId->ecx;
1391 *pEdx = pCpuId->edx;
1392
1393 if ( iLeaf == 1)
1394 {
1395 /* Bits 31-24: Initial APIC ID */
1396 Assert(pVCpu->idCpu <= 255);
1397 *pEbx |= (pVCpu->idCpu << 24);
1398 }
1399
1400 if ( iLeaf == 4
1401 && cCurrentCacheIndex < 3
1402 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1403 {
1404 uint32_t type, level, sharing, linesize,
1405 partitions, associativity, sets, cores;
1406
1407 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1408 partitions = 1;
1409 /* Those are only to shut up compiler, as they will always
1410 get overwritten, and compiler should be able to figure that out */
1411 sets = associativity = sharing = level = 1;
1412 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1413 switch (cCurrentCacheIndex)
1414 {
1415 case 0:
1416 type = 1;
1417 level = 1;
1418 sharing = 1;
1419 linesize = 64;
1420 associativity = 8;
1421 sets = 64;
1422 break;
1423 case 1:
1424 level = 1;
1425 type = 2;
1426 sharing = 1;
1427 linesize = 64;
1428 associativity = 8;
1429 sets = 64;
1430 break;
1431 default: /* shut up gcc.*/
1432 AssertFailed();
1433 case 2:
1434 level = 2;
1435 type = 3;
1436 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1437 linesize = 64;
1438 associativity = 24;
1439 sets = 4096;
1440 break;
1441 }
1442
1443 *pEax |= ((cores - 1) << 26) |
1444 ((sharing - 1) << 14) |
1445 (level << 5) |
1446 1;
1447 *pEbx = (linesize - 1) |
1448 ((partitions - 1) << 12) |
1449 ((associativity - 1) << 22); /* -1 encoding */
1450 *pEcx = sets - 1;
1451 }
1452
1453 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1454}
1455
1456/**
1457 * Gets a number of standard CPUID leafs.
1458 *
1459 * @returns Number of leafs.
1460 * @param pVM Pointer to the VM.
1461 * @remark Intended for PATM.
1462 */
1463VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1464{
1465 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1466}
1467
1468
1469/**
1470 * Gets a number of extended CPUID leafs.
1471 *
1472 * @returns Number of leafs.
1473 * @param pVM Pointer to the VM.
1474 * @remark Intended for PATM.
1475 */
1476VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1477{
1478 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1479}
1480
1481
1482/**
1483 * Gets a number of centaur CPUID leafs.
1484 *
1485 * @returns Number of leafs.
1486 * @param pVM Pointer to the VM.
1487 * @remark Intended for PATM.
1488 */
1489VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1490{
1491 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1492}
1493
1494
1495/**
1496 * Sets a CPUID feature bit.
1497 *
1498 * @param pVM Pointer to the VM.
1499 * @param enmFeature The feature to set.
1500 */
1501VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1502{
1503 switch (enmFeature)
1504 {
1505 /*
1506 * Set the APIC bit in both feature masks.
1507 */
1508 case CPUMCPUIDFEATURE_APIC:
1509 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1510 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1511 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1512 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1513 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1514 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1515 break;
1516
1517 /*
1518 * Set the x2APIC bit in the standard feature mask.
1519 */
1520 case CPUMCPUIDFEATURE_X2APIC:
1521 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1522 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1523 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1524 break;
1525
1526 /*
1527 * Set the sysenter/sysexit bit in the standard feature mask.
1528 * Assumes the caller knows what it's doing! (host must support these)
1529 */
1530 case CPUMCPUIDFEATURE_SEP:
1531 {
1532 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1533 {
1534 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1535 return;
1536 }
1537
1538 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1539 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1540 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1541 break;
1542 }
1543
1544 /*
1545 * Set the syscall/sysret bit in the extended feature mask.
1546 * Assumes the caller knows what it's doing! (host must support these)
1547 */
1548 case CPUMCPUIDFEATURE_SYSCALL:
1549 {
1550 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1551 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1552 {
1553#if HC_ARCH_BITS == 32
1554 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1555 * Even when the cpu is capable of doing so in 64 bits mode.
1556 */
1557 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1558 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1559 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1560#endif
1561 {
1562 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1563 return;
1564 }
1565 }
1566 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1567 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1568 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1569 break;
1570 }
1571
1572 /*
1573 * Set the PAE bit in both feature masks.
1574 * Assumes the caller knows what it's doing! (host must support these)
1575 */
1576 case CPUMCPUIDFEATURE_PAE:
1577 {
1578 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1579 {
1580 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1581 return;
1582 }
1583
1584 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1585 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1586 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1587 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1588 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1589 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1590 break;
1591 }
1592
1593 /*
1594 * Set the LONG MODE bit in the extended feature mask.
1595 * Assumes the caller knows what it's doing! (host must support these)
1596 */
1597 case CPUMCPUIDFEATURE_LONG_MODE:
1598 {
1599 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1600 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1601 {
1602 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1603 return;
1604 }
1605
1606 /* Valid for both Intel and AMD. */
1607 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1608 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1609 break;
1610 }
1611
1612 /*
1613 * Set the NXE bit in the extended feature mask.
1614 * Assumes the caller knows what it's doing! (host must support these)
1615 */
1616 case CPUMCPUIDFEATURE_NXE:
1617 {
1618 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1619 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1620 {
1621 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1622 return;
1623 }
1624
1625 /* Valid for both Intel and AMD. */
1626 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1627 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1628 break;
1629 }
1630
1631 case CPUMCPUIDFEATURE_LAHF:
1632 {
1633 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1634 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1635 {
1636 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1637 return;
1638 }
1639
1640 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1641 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1642 break;
1643 }
1644
1645 case CPUMCPUIDFEATURE_PAT:
1646 {
1647 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1648 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1649 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1650 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1651 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1652 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1653 break;
1654 }
1655
1656 case CPUMCPUIDFEATURE_RDTSCP:
1657 {
1658 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1659 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP)
1660 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1661 {
1662 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1663 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1664 return;
1665 }
1666
1667 /* Valid for AMD only (for now). */
1668 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1669 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1670 break;
1671 }
1672
1673 /*
1674 * Set the Hypervisor Present bit in the standard feature mask.
1675 */
1676 case CPUMCPUIDFEATURE_HVP:
1677 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1678 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
1679 LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
1680 break;
1681
1682 default:
1683 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1684 break;
1685 }
1686 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1687 {
1688 PVMCPU pVCpu = &pVM->aCpus[i];
1689 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1690 }
1691}
1692
1693
1694/**
1695 * Queries a CPUID feature bit.
1696 *
1697 * @returns boolean for feature presence
1698 * @param pVM Pointer to the VM.
1699 * @param enmFeature The feature to query.
1700 */
1701VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1702{
1703 switch (enmFeature)
1704 {
1705 case CPUMCPUIDFEATURE_PAE:
1706 {
1707 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1708 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1709 break;
1710 }
1711
1712 case CPUMCPUIDFEATURE_NXE:
1713 {
1714 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1715 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_NX);
1716 }
1717
1718 case CPUMCPUIDFEATURE_RDTSCP:
1719 {
1720 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1721 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1722 break;
1723 }
1724
1725 case CPUMCPUIDFEATURE_LONG_MODE:
1726 {
1727 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1728 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1729 break;
1730 }
1731
1732 default:
1733 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1734 break;
1735 }
1736 return false;
1737}
1738
1739
1740/**
1741 * Clears a CPUID feature bit.
1742 *
1743 * @param pVM Pointer to the VM.
1744 * @param enmFeature The feature to clear.
1745 */
1746VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1747{
1748 switch (enmFeature)
1749 {
1750 /*
1751 * Set the APIC bit in both feature masks.
1752 */
1753 case CPUMCPUIDFEATURE_APIC:
1754 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1755 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1756 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1757 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1758 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1759 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1760 break;
1761
1762 /*
1763 * Clear the x2APIC bit in the standard feature mask.
1764 */
1765 case CPUMCPUIDFEATURE_X2APIC:
1766 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1767 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1768 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1769 break;
1770
1771 case CPUMCPUIDFEATURE_PAE:
1772 {
1773 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1774 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1775 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1776 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1777 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1778 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1779 break;
1780 }
1781
1782 case CPUMCPUIDFEATURE_PAT:
1783 {
1784 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1785 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1786 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1787 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1788 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1789 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1790 break;
1791 }
1792
1793 case CPUMCPUIDFEATURE_LONG_MODE:
1794 {
1795 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1796 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1797 break;
1798 }
1799
1800 case CPUMCPUIDFEATURE_LAHF:
1801 {
1802 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1803 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1804 break;
1805 }
1806
1807 case CPUMCPUIDFEATURE_HVP:
1808 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1809 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
1810 break;
1811
1812 default:
1813 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1814 break;
1815 }
1816 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1817 {
1818 PVMCPU pVCpu = &pVM->aCpus[i];
1819 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1820 }
1821}
1822
1823
1824/**
1825 * Gets the host CPU vendor
1826 *
1827 * @returns CPU vendor
1828 * @param pVM Pointer to the VM.
1829 */
1830VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1831{
1832 return pVM->cpum.s.enmHostCpuVendor;
1833}
1834
1835/**
1836 * Gets the CPU vendor
1837 *
1838 * @returns CPU vendor
1839 * @param pVM Pointer to the VM.
1840 */
1841VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1842{
1843 return pVM->cpum.s.enmGuestCpuVendor;
1844}
1845
1846
1847VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1848{
1849 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1850 return CPUMRecalcHyperDRx(pVCpu);
1851}
1852
1853
1854VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1855{
1856 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1857 return CPUMRecalcHyperDRx(pVCpu);
1858}
1859
1860
1861VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1862{
1863 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1864 return CPUMRecalcHyperDRx(pVCpu);
1865}
1866
1867
1868VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1869{
1870 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1871 return CPUMRecalcHyperDRx(pVCpu);
1872}
1873
1874
1875VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1876{
1877 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1878 return CPUMRecalcHyperDRx(pVCpu);
1879}
1880
1881
1882VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1883{
1884 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1885 return CPUMRecalcHyperDRx(pVCpu);
1886}
1887
1888
1889VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1890{
1891 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1892 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1893 if (iReg == 4 || iReg == 5)
1894 iReg += 2;
1895 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1896 return CPUMRecalcHyperDRx(pVCpu);
1897}
1898
1899
1900/**
1901 * Recalculates the hypervisor DRx register values based on
1902 * current guest registers and DBGF breakpoints.
1903 *
1904 * This is called whenever a guest DRx register is modified and when DBGF
1905 * sets a hardware breakpoint. In guest context this function will reload
1906 * any (hyper) DRx registers which comes out with a different value.
1907 *
1908 * @returns VINF_SUCCESS.
1909 * @param pVCpu Pointer to the VMCPU.
1910 */
1911VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1912{
1913 PVM pVM = pVCpu->CTX_SUFF(pVM);
1914
1915 /*
1916 * Compare the DR7s first.
1917 *
1918 * We only care about the enabled flags. The GE and LE flags are always
1919 * set and we don't care if the guest doesn't set them. GD is virtualized
1920 * when we dispatch #DB, we never enable it.
1921 */
1922 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1923#ifdef CPUM_VIRTUALIZE_DRX
1924 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1925#else
1926 const RTGCUINTREG uGstDr7 = 0;
1927#endif
1928 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1929 {
1930 /*
1931 * Ok, something is enabled. Recalc each of the breakpoints.
1932 * Straight forward code, not optimized/minimized in any way.
1933 */
1934 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1935
1936 /* bp 0 */
1937 RTGCUINTREG uNewDr0;
1938 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1939 {
1940 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1941 uNewDr0 = DBGFBpGetDR0(pVM);
1942 }
1943 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1944 {
1945 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1946 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1947 }
1948 else
1949 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
1950
1951 /* bp 1 */
1952 RTGCUINTREG uNewDr1;
1953 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1954 {
1955 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1956 uNewDr1 = DBGFBpGetDR1(pVM);
1957 }
1958 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1959 {
1960 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1961 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1962 }
1963 else
1964 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
1965
1966 /* bp 2 */
1967 RTGCUINTREG uNewDr2;
1968 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1969 {
1970 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1971 uNewDr2 = DBGFBpGetDR2(pVM);
1972 }
1973 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1974 {
1975 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1976 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1977 }
1978 else
1979 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
1980
1981 /* bp 3 */
1982 RTGCUINTREG uNewDr3;
1983 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1984 {
1985 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1986 uNewDr3 = DBGFBpGetDR3(pVM);
1987 }
1988 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1989 {
1990 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1991 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1992 }
1993 else
1994 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
1995
1996 /*
1997 * Apply the updates.
1998 */
1999#ifdef IN_RC
2000 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
2001 {
2002 /** @todo save host DBx registers. */
2003 }
2004#endif
2005 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
2006 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2007 CPUMSetHyperDR3(pVCpu, uNewDr3);
2008 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2009 CPUMSetHyperDR2(pVCpu, uNewDr2);
2010 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2011 CPUMSetHyperDR1(pVCpu, uNewDr1);
2012 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2013 CPUMSetHyperDR0(pVCpu, uNewDr0);
2014 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2015 CPUMSetHyperDR7(pVCpu, uNewDr7);
2016 }
2017 else
2018 {
2019#ifdef IN_RC
2020 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
2021 {
2022 /** @todo restore host DBx registers. */
2023 }
2024#endif
2025 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2026 }
2027 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2028 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2029 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2030 pVCpu->cpum.s.Hyper.dr[7]));
2031
2032 return VINF_SUCCESS;
2033}
2034
2035
2036/**
2037 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2038 *
2039 * @returns true if in real mode, otherwise false.
2040 * @param pVCpu Pointer to the VMCPU.
2041 */
2042VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2043{
2044 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2045}
2046
2047
2048/**
2049 * Tests if the guest has the Page Size Extension enabled (PSE).
2050 *
2051 * @returns true if in real mode, otherwise false.
2052 * @param pVCpu Pointer to the VMCPU.
2053 */
2054VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2055{
2056 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2057 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2058}
2059
2060
2061/**
2062 * Tests if the guest has the paging enabled (PG).
2063 *
2064 * @returns true if in real mode, otherwise false.
2065 * @param pVCpu Pointer to the VMCPU.
2066 */
2067VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2068{
2069 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2070}
2071
2072
2073/**
2074 * Tests if the guest has the paging enabled (PG).
2075 *
2076 * @returns true if in real mode, otherwise false.
2077 * @param pVCpu Pointer to the VMCPU.
2078 */
2079VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2080{
2081 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2082}
2083
2084
2085/**
2086 * Tests if the guest is running in real mode or not.
2087 *
2088 * @returns true if in real mode, otherwise false.
2089 * @param pVCpu Pointer to the VMCPU.
2090 */
2091VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2092{
2093 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2094}
2095
2096
2097/**
2098 * Tests if the guest is running in real or virtual 8086 mode.
2099 *
2100 * @returns @c true if it is, @c false if not.
2101 * @param pVCpu Pointer to the VMCPU.
2102 */
2103VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2104{
2105 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2106 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2107}
2108
2109
2110/**
2111 * Tests if the guest is running in protected or not.
2112 *
2113 * @returns true if in protected mode, otherwise false.
2114 * @param pVCpu Pointer to the VMCPU.
2115 */
2116VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2117{
2118 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2119}
2120
2121
2122/**
2123 * Tests if the guest is running in paged protected or not.
2124 *
2125 * @returns true if in paged protected mode, otherwise false.
2126 * @param pVCpu Pointer to the VMCPU.
2127 */
2128VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2129{
2130 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2131}
2132
2133
2134/**
2135 * Tests if the guest is running in long mode or not.
2136 *
2137 * @returns true if in long mode, otherwise false.
2138 * @param pVCpu Pointer to the VMCPU.
2139 */
2140VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2141{
2142 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2143}
2144
2145
2146/**
2147 * Tests if the guest is running in PAE mode or not.
2148 *
2149 * @returns true if in PAE mode, otherwise false.
2150 * @param pVCpu Pointer to the VMCPU.
2151 */
2152VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2153{
2154 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2155 && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
2156 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
2157}
2158
2159
2160#ifndef IN_RING0
2161/**
2162 * Updates the EFLAGS while we're in raw-mode.
2163 *
2164 * @param pVCpu Pointer to the VMCPU.
2165 * @param fEfl The new EFLAGS value.
2166 */
2167VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
2168{
2169 if (!pVCpu->cpum.s.fRawEntered)
2170 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
2171 else
2172 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
2173}
2174#endif /* !IN_RING0 */
2175
2176
2177/**
2178 * Gets the EFLAGS while we're in raw-mode.
2179 *
2180 * @returns The eflags.
2181 * @param pVCpu Pointer to the current virtual CPU.
2182 */
2183VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
2184{
2185#ifdef IN_RING0
2186 return pVCpu->cpum.s.Guest.eflags.u32;
2187#else
2188
2189 if (!pVCpu->cpum.s.fRawEntered)
2190 return pVCpu->cpum.s.Guest.eflags.u32;
2191 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
2192#endif
2193}
2194
2195
2196/**
2197 * Sets the specified changed flags (CPUM_CHANGED_*).
2198 *
2199 * @param pVCpu Pointer to the current virtual CPU.
2200 */
2201VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2202{
2203 pVCpu->cpum.s.fChanged |= fChangedFlags;
2204}
2205
2206
2207/**
2208 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2209 * @returns true if supported.
2210 * @returns false if not supported.
2211 * @param pVM Pointer to the VM.
2212 */
2213VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2214{
2215 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2216}
2217
2218
2219/**
2220 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2221 * @returns true if used.
2222 * @returns false if not used.
2223 * @param pVM Pointer to the VM.
2224 */
2225VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2226{
2227 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
2228}
2229
2230
2231/**
2232 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2233 * @returns true if used.
2234 * @returns false if not used.
2235 * @param pVM Pointer to the VM.
2236 */
2237VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2238{
2239 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
2240}
2241
2242#ifndef IN_RING3
2243
2244/**
2245 * Lazily sync in the FPU/XMM state
2246 *
2247 * @returns VBox status code.
2248 * @param pVCpu Pointer to the VMCPU.
2249 */
2250VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2251{
2252 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2253}
2254
2255#endif /* !IN_RING3 */
2256
2257/**
2258 * Checks if we activated the FPU/XMM state of the guest OS
2259 * @returns true if we did.
2260 * @returns false if not.
2261 * @param pVCpu Pointer to the VMCPU.
2262 */
2263VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2264{
2265 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
2266}
2267
2268
2269/**
2270 * Deactivate the FPU/XMM state of the guest OS
2271 * @param pVCpu Pointer to the VMCPU.
2272 */
2273VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2274{
2275 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2276}
2277
2278
2279/**
2280 * Checks if the guest debug state is active
2281 *
2282 * @returns boolean
2283 * @param pVM Pointer to the VM.
2284 */
2285VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2286{
2287 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
2288}
2289
2290/**
2291 * Checks if the hyper debug state is active
2292 *
2293 * @returns boolean
2294 * @param pVM Pointer to the VM.
2295 */
2296VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2297{
2298 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2299}
2300
2301
2302/**
2303 * Mark the guest's debug state as inactive.
2304 *
2305 * @returns boolean
2306 * @param pVM Pointer to the VM.
2307 */
2308VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2309{
2310 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2311}
2312
2313
2314/**
2315 * Mark the hypervisor's debug state as inactive.
2316 *
2317 * @returns boolean
2318 * @param pVM Pointer to the VM.
2319 */
2320VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2321{
2322 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2323}
2324
2325/**
2326 * Checks if the hidden selector registers are valid for the specified CPU.
2327 *
2328 * @returns true if they are.
2329 * @returns false if not.
2330 * @param pVCpu Pointer to the VM.
2331 */
2332VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu)
2333{
2334 bool const fRc = !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID);
2335 Assert(fRc || !HWACCMIsEnabled(pVCpu->CTX_SUFF(pVM)));
2336 Assert(!pVCpu->cpum.s.fRemEntered);
2337 return fRc;
2338}
2339
2340
2341
2342/**
2343 * Get the current privilege level of the guest.
2344 *
2345 * @returns CPL
2346 * @param pVCpu Pointer to the current virtual CPU.
2347 */
2348VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
2349{
2350 uint32_t uCpl;
2351
2352 if (CPUMAreHiddenSelRegsValid(pVCpu))
2353 {
2354 /*
2355 * CPL can reliably be found in SS.DPL.
2356 *
2357 * Note! We used to check CS.DPL here, assuming it was always equal to
2358 * CPL even if a conforming segment was loaded. But this truned out to
2359 * only apply to older AMD-V. With VT-x we had an ACP2 regression
2360 * during install after a far call to ring 2 with VT-x. Then on newer
2361 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
2362 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
2363 *
2364 * So, forget CS.DPL, always use SS.DPL.
2365 */
2366 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2367 {
2368 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2369 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
2370 else
2371 uCpl = 3; /* REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
2372 }
2373 else
2374 uCpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2375 }
2376 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2377 {
2378 if (RT_LIKELY(!pVCpu->cpum.s.Guest.eflags.Bits.u1VM))
2379 {
2380 /*
2381 * The SS RPL is always equal to the CPL, while the CS RPL
2382 * isn't necessarily equal if the segment is conforming.
2383 * See section 4.11.1 in the AMD manual.
2384 */
2385 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
2386#ifndef IN_RING0
2387 if (uCpl == 1)
2388 uCpl = 0;
2389#endif
2390 }
2391 else
2392 uCpl = 3;
2393 }
2394 else
2395 uCpl = 0; /* real mode; CPL is zero */
2396
2397 return uCpl;
2398}
2399
2400
2401/**
2402 * Gets the current guest CPU mode.
2403 *
2404 * If paging mode is what you need, check out PGMGetGuestMode().
2405 *
2406 * @returns The CPU mode.
2407 * @param pVCpu Pointer to the VMCPU.
2408 */
2409VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2410{
2411 CPUMMODE enmMode;
2412 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2413 enmMode = CPUMMODE_REAL;
2414 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2415 enmMode = CPUMMODE_PROTECTED;
2416 else
2417 enmMode = CPUMMODE_LONG;
2418
2419 return enmMode;
2420}
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