VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 25576

Last change on this file since 25576 was 24953, checked in by vboxsync, 15 years ago

VMM: functional MSR_IA32_PERF_STATUS implementation

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1/* $Id: CPUMAllRegs.cpp 24953 2009-11-25 14:00:05Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/patm.h>
29#include <VBox/dbgf.h>
30#include <VBox/mm.h>
31#include "CPUMInternal.h"
32#include <VBox/vm.h>
33#include <VBox/err.h>
34#include <VBox/dis.h>
35#include <VBox/log.h>
36#include <VBox/hwaccm.h>
37#include <VBox/tm.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#ifdef IN_RING3
41#include <iprt/thread.h>
42#endif
43
44/** Disable stack frame pointer generation here. */
45#if defined(_MSC_VER) && !defined(DEBUG)
46# pragma optimize("y", off)
47#endif
48
49
50/**
51 * Sets or resets an alternative hypervisor context core.
52 *
53 * This is called when we get a hypervisor trap set switch the context
54 * core with the trap frame on the stack. It is called again to reset
55 * back to the default context core when resuming hypervisor execution.
56 *
57 * @param pVCpu The VMCPU handle.
58 * @param pCtxCore Pointer to the alternative context core or NULL
59 * to go back to the default context core.
60 */
61VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
62{
63 PVM pVM = pVCpu->CTX_SUFF(pVM);
64
65 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVCpu->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
66 if (!pCtxCore)
67 {
68 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
69 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
70 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
71 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_RC_ADDR(pVM, pCtxCore);
72 }
73 else
74 {
75 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
76 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
77 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
78 }
79}
80
81
82/**
83 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
84 * This is only for reading in order to save a few calls.
85 *
86 * @param pVM Handle to the virtual machine.
87 */
88VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
89{
90 return pVCpu->cpum.s.CTX_SUFF(pHyperCore);
91}
92
93
94/**
95 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
96 *
97 * @returns VBox status code.
98 * @param pVM Handle to the virtual machine.
99 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
100 *
101 * @deprecated This will *not* (and has never) given the right picture of the
102 * hypervisor register state. With CPUMHyperSetCtxCore() this is
103 * getting much worse. So, use the individual functions for getting
104 * and esp. setting the hypervisor registers.
105 */
106VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx)
107{
108 *ppCtx = &pVCpu->cpum.s.Hyper;
109 return VINF_SUCCESS;
110}
111
112
113VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
114{
115 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
116 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
117 pVCpu->cpum.s.Hyper.gdtrPadding = 0;
118}
119
120
121VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
122{
123 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
124 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
125 pVCpu->cpum.s.Hyper.idtrPadding = 0;
126}
127
128
129VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
130{
131 pVCpu->cpum.s.Hyper.cr3 = cr3;
132
133#ifdef IN_RC
134 /* Update the current CR3. */
135 ASMSetCR3(cr3);
136#endif
137}
138
139VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
140{
141 return pVCpu->cpum.s.Hyper.cr3;
142}
143
144
145VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
146{
147 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
148}
149
150
151VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
152{
153 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
154}
155
156
157VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
158{
159 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
160}
161
162
163VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
164{
165 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
166}
167
168
169VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
170{
171 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
172}
173
174
175VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
176{
177 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
178}
179
180
181VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
182{
183 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
184}
185
186
187VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
188{
189 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
190 return VINF_SUCCESS;
191}
192
193
194VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
195{
196 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
197}
198
199
200VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
201{
202 pVCpu->cpum.s.Hyper.tr = SelTR;
203}
204
205
206VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
207{
208 pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
209}
210
211
212VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
213{
214 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
215 /** @todo in GC we must load it! */
216}
217
218
219VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
220{
221 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
222 /** @todo in GC we must load it! */
223}
224
225
226VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
227{
228 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
229 /** @todo in GC we must load it! */
230}
231
232
233VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
234{
235 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
236 /** @todo in GC we must load it! */
237}
238
239
240VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
241{
242 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
243 /** @todo in GC we must load it! */
244}
245
246
247VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
248{
249 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
250 /** @todo in GC we must load it! */
251}
252
253
254VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
255{
256 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
257}
258
259
260VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
261{
262 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
263}
264
265
266VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
267{
268 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
269}
270
271
272VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
273{
274 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
275}
276
277
278VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
279{
280 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
281}
282
283
284VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
285{
286 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
287}
288
289
290VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
291{
292 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eax;
293}
294
295
296VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
297{
298 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebx;
299}
300
301
302VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
303{
304 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ecx;
305}
306
307
308VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
309{
310 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edx;
311}
312
313
314VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
315{
316 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esi;
317}
318
319
320VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
321{
322 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edi;
323}
324
325
326VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
327{
328 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebp;
329}
330
331
332VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
333{
334 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp;
335}
336
337
338VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
339{
340 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
341}
342
343
344VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
345{
346 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip;
347}
348
349
350VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
351{
352 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->rip;
353}
354
355
356VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
357{
358 if (pcbLimit)
359 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
360 return pVCpu->cpum.s.Hyper.idtr.pIdt;
361}
362
363
364VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
365{
366 if (pcbLimit)
367 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
368 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
369}
370
371
372VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
373{
374 return pVCpu->cpum.s.Hyper.ldtr;
375}
376
377
378VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
379{
380 return pVCpu->cpum.s.Hyper.dr[0];
381}
382
383
384VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
385{
386 return pVCpu->cpum.s.Hyper.dr[1];
387}
388
389
390VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
391{
392 return pVCpu->cpum.s.Hyper.dr[2];
393}
394
395
396VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
397{
398 return pVCpu->cpum.s.Hyper.dr[3];
399}
400
401
402VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
403{
404 return pVCpu->cpum.s.Hyper.dr[6];
405}
406
407
408VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
409{
410 return pVCpu->cpum.s.Hyper.dr[7];
411}
412
413
414/**
415 * Gets the pointer to the internal CPUMCTXCORE structure.
416 * This is only for reading in order to save a few calls.
417 *
418 * @param pVCpu Handle to the virtual cpu.
419 */
420VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
421{
422 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
423}
424
425
426/**
427 * Sets the guest context core registers.
428 *
429 * @param pVCpu Handle to the virtual cpu.
430 * @param pCtxCore The new context core values.
431 */
432VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore)
433{
434 /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
435
436 PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
437 *pCtxCoreDst = *pCtxCore;
438
439 /* Mask away invalid parts of the cpu context. */
440 if (!CPUMIsGuestInLongMode(pVCpu))
441 {
442 uint64_t u64Mask = UINT64_C(0xffffffff);
443
444 pCtxCoreDst->rip &= u64Mask;
445 pCtxCoreDst->rax &= u64Mask;
446 pCtxCoreDst->rbx &= u64Mask;
447 pCtxCoreDst->rcx &= u64Mask;
448 pCtxCoreDst->rdx &= u64Mask;
449 pCtxCoreDst->rsi &= u64Mask;
450 pCtxCoreDst->rdi &= u64Mask;
451 pCtxCoreDst->rbp &= u64Mask;
452 pCtxCoreDst->rsp &= u64Mask;
453 pCtxCoreDst->rflags.u &= u64Mask;
454
455 pCtxCoreDst->r8 = 0;
456 pCtxCoreDst->r9 = 0;
457 pCtxCoreDst->r10 = 0;
458 pCtxCoreDst->r11 = 0;
459 pCtxCoreDst->r12 = 0;
460 pCtxCoreDst->r13 = 0;
461 pCtxCoreDst->r14 = 0;
462 pCtxCoreDst->r15 = 0;
463 }
464}
465
466
467/**
468 * Queries the pointer to the internal CPUMCTX structure
469 *
470 * @returns The CPUMCTX pointer.
471 * @param pVCpu Handle to the virtual cpu.
472 */
473VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
474{
475 return &pVCpu->cpum.s.Guest;
476}
477
478VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
479{
480 pVCpu->cpum.s.Guest.gdtr.cbGdt = limit;
481 pVCpu->cpum.s.Guest.gdtr.pGdt = addr;
482 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
483 return VINF_SUCCESS;
484}
485
486VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
487{
488 pVCpu->cpum.s.Guest.idtr.cbIdt = limit;
489 pVCpu->cpum.s.Guest.idtr.pIdt = addr;
490 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
491 return VINF_SUCCESS;
492}
493
494VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
495{
496 AssertMsgFailed(("Need to load the hidden bits too!\n"));
497
498 pVCpu->cpum.s.Guest.tr = tr;
499 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
500 return VINF_SUCCESS;
501}
502
503VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
504{
505 pVCpu->cpum.s.Guest.ldtr = ldtr;
506 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
507 return VINF_SUCCESS;
508}
509
510
511/**
512 * Set the guest CR0.
513 *
514 * When called in GC, the hyper CR0 may be updated if that is
515 * required. The caller only has to take special action if AM,
516 * WP, PG or PE changes.
517 *
518 * @returns VINF_SUCCESS (consider it void).
519 * @param pVCpu Handle to the virtual cpu.
520 * @param cr0 The new CR0 value.
521 */
522VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
523{
524#ifdef IN_RC
525 /*
526 * Check if we need to change hypervisor CR0 because
527 * of math stuff.
528 */
529 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
530 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
531 {
532 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
533 {
534 /*
535 * We haven't saved the host FPU state yet, so TS and MT are both set
536 * and EM should be reflecting the guest EM (it always does this).
537 */
538 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
539 {
540 uint32_t HyperCR0 = ASMGetCR0();
541 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
542 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
543 HyperCR0 &= ~X86_CR0_EM;
544 HyperCR0 |= cr0 & X86_CR0_EM;
545 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
546 ASMSetCR0(HyperCR0);
547 }
548# ifdef VBOX_STRICT
549 else
550 {
551 uint32_t HyperCR0 = ASMGetCR0();
552 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
553 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
554 }
555# endif
556 }
557 else
558 {
559 /*
560 * Already saved the state, so we're just mirroring
561 * the guest flags.
562 */
563 uint32_t HyperCR0 = ASMGetCR0();
564 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
565 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
566 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
567 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
568 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
569 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
570 ASMSetCR0(HyperCR0);
571 }
572 }
573#endif /* IN_RC */
574
575 /*
576 * Check for changes causing TLB flushes (for REM).
577 * The caller is responsible for calling PGM when appropriate.
578 */
579 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
580 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
581 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
582 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
583
584 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
585 return VINF_SUCCESS;
586}
587
588
589VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
590{
591 pVCpu->cpum.s.Guest.cr2 = cr2;
592 return VINF_SUCCESS;
593}
594
595
596VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
597{
598 pVCpu->cpum.s.Guest.cr3 = cr3;
599 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
600 return VINF_SUCCESS;
601}
602
603
604VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
605{
606 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
607 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
608 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
609 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
610 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
611 cr4 &= ~X86_CR4_OSFSXR;
612 pVCpu->cpum.s.Guest.cr4 = cr4;
613 return VINF_SUCCESS;
614}
615
616
617VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
618{
619 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
620 return VINF_SUCCESS;
621}
622
623
624VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
625{
626 pVCpu->cpum.s.Guest.eip = eip;
627 return VINF_SUCCESS;
628}
629
630
631VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
632{
633 pVCpu->cpum.s.Guest.eax = eax;
634 return VINF_SUCCESS;
635}
636
637
638VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
639{
640 pVCpu->cpum.s.Guest.ebx = ebx;
641 return VINF_SUCCESS;
642}
643
644
645VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
646{
647 pVCpu->cpum.s.Guest.ecx = ecx;
648 return VINF_SUCCESS;
649}
650
651
652VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
653{
654 pVCpu->cpum.s.Guest.edx = edx;
655 return VINF_SUCCESS;
656}
657
658
659VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
660{
661 pVCpu->cpum.s.Guest.esp = esp;
662 return VINF_SUCCESS;
663}
664
665
666VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
667{
668 pVCpu->cpum.s.Guest.ebp = ebp;
669 return VINF_SUCCESS;
670}
671
672
673VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
674{
675 pVCpu->cpum.s.Guest.esi = esi;
676 return VINF_SUCCESS;
677}
678
679
680VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
681{
682 pVCpu->cpum.s.Guest.edi = edi;
683 return VINF_SUCCESS;
684}
685
686
687VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
688{
689 pVCpu->cpum.s.Guest.ss = ss;
690 return VINF_SUCCESS;
691}
692
693
694VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
695{
696 pVCpu->cpum.s.Guest.cs = cs;
697 return VINF_SUCCESS;
698}
699
700
701VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
702{
703 pVCpu->cpum.s.Guest.ds = ds;
704 return VINF_SUCCESS;
705}
706
707
708VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
709{
710 pVCpu->cpum.s.Guest.es = es;
711 return VINF_SUCCESS;
712}
713
714
715VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
716{
717 pVCpu->cpum.s.Guest.fs = fs;
718 return VINF_SUCCESS;
719}
720
721
722VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
723{
724 pVCpu->cpum.s.Guest.gs = gs;
725 return VINF_SUCCESS;
726}
727
728
729VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
730{
731 pVCpu->cpum.s.Guest.msrEFER = val;
732}
733
734
735VMMDECL(uint64_t) CPUMGetGuestMsr(PVMCPU pVCpu, unsigned idMsr)
736{
737 uint64_t u64 = 0;
738
739 switch (idMsr)
740 {
741 case MSR_IA32_TSC:
742 u64 = TMCpuTickGet(pVCpu);
743 break;
744
745 case MSR_IA32_CR_PAT:
746 u64 = pVCpu->cpum.s.Guest.msrPAT;
747 break;
748
749 case MSR_IA32_SYSENTER_CS:
750 u64 = pVCpu->cpum.s.Guest.SysEnter.cs;
751 break;
752
753 case MSR_IA32_SYSENTER_EIP:
754 u64 = pVCpu->cpum.s.Guest.SysEnter.eip;
755 break;
756
757 case MSR_IA32_SYSENTER_ESP:
758 u64 = pVCpu->cpum.s.Guest.SysEnter.esp;
759 break;
760
761 case MSR_K6_EFER:
762 u64 = pVCpu->cpum.s.Guest.msrEFER;
763 break;
764
765 case MSR_K8_SF_MASK:
766 u64 = pVCpu->cpum.s.Guest.msrSFMASK;
767 break;
768
769 case MSR_K6_STAR:
770 u64 = pVCpu->cpum.s.Guest.msrSTAR;
771 break;
772
773 case MSR_K8_LSTAR:
774 u64 = pVCpu->cpum.s.Guest.msrLSTAR;
775 break;
776
777 case MSR_K8_CSTAR:
778 u64 = pVCpu->cpum.s.Guest.msrCSTAR;
779 break;
780
781 case MSR_K8_KERNEL_GS_BASE:
782 u64 = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
783 break;
784
785 case MSR_K8_TSC_AUX:
786 u64 = pVCpu->cpum.s.GuestMsr.msr.tscAux;
787 break;
788
789 case MSR_IA32_PERF_STATUS:
790 /** @todo: could really be not exactly correct, maybe use host's values */
791 /* Keep consistent with helper_rdmsr() in REM */
792 u64 = (1000ULL /* TSC increment by tick */)
793 | (((uint64_t)4ULL) << 40 /* CPU multiplier */ );
794 break;
795
796 /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
797 default:
798 AssertFailed();
799 break;
800 }
801 return u64;
802}
803
804VMMDECL(void) CPUMSetGuestMsr(PVMCPU pVCpu, unsigned idMsr, uint64_t valMsr)
805{
806 /* On purpose only a limited number of MSRs; use the emulation function to update the others. */
807 switch (idMsr)
808 {
809 case MSR_K8_TSC_AUX:
810 pVCpu->cpum.s.GuestMsr.msr.tscAux = valMsr;
811 break;
812
813 default:
814 AssertFailed();
815 break;
816 }
817}
818
819VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
820{
821 if (pcbLimit)
822 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
823 return pVCpu->cpum.s.Guest.idtr.pIdt;
824}
825
826
827VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
828{
829 if (pHidden)
830 *pHidden = pVCpu->cpum.s.Guest.trHid;
831 return pVCpu->cpum.s.Guest.tr;
832}
833
834
835VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
836{
837 return pVCpu->cpum.s.Guest.cs;
838}
839
840
841VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
842{
843 return pVCpu->cpum.s.Guest.ds;
844}
845
846
847VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
848{
849 return pVCpu->cpum.s.Guest.es;
850}
851
852
853VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
854{
855 return pVCpu->cpum.s.Guest.fs;
856}
857
858
859VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
860{
861 return pVCpu->cpum.s.Guest.gs;
862}
863
864
865VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
866{
867 return pVCpu->cpum.s.Guest.ss;
868}
869
870
871VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
872{
873 return pVCpu->cpum.s.Guest.ldtr;
874}
875
876
877VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
878{
879 return pVCpu->cpum.s.Guest.cr0;
880}
881
882
883VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
884{
885 return pVCpu->cpum.s.Guest.cr2;
886}
887
888
889VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
890{
891 return pVCpu->cpum.s.Guest.cr3;
892}
893
894
895VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
896{
897 return pVCpu->cpum.s.Guest.cr4;
898}
899
900
901VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
902{
903 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
904}
905
906
907VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
908{
909 return pVCpu->cpum.s.Guest.eip;
910}
911
912
913VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
914{
915 return pVCpu->cpum.s.Guest.rip;
916}
917
918
919VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
920{
921 return pVCpu->cpum.s.Guest.eax;
922}
923
924
925VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
926{
927 return pVCpu->cpum.s.Guest.ebx;
928}
929
930
931VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
932{
933 return pVCpu->cpum.s.Guest.ecx;
934}
935
936
937VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
938{
939 return pVCpu->cpum.s.Guest.edx;
940}
941
942
943VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
944{
945 return pVCpu->cpum.s.Guest.esi;
946}
947
948
949VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
950{
951 return pVCpu->cpum.s.Guest.edi;
952}
953
954
955VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
956{
957 return pVCpu->cpum.s.Guest.esp;
958}
959
960
961VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
962{
963 return pVCpu->cpum.s.Guest.ebp;
964}
965
966
967VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
968{
969 return pVCpu->cpum.s.Guest.eflags.u32;
970}
971
972
973///@todo: crx should be an array
974VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
975{
976 switch (iReg)
977 {
978 case USE_REG_CR0:
979 *pValue = pVCpu->cpum.s.Guest.cr0;
980 break;
981 case USE_REG_CR2:
982 *pValue = pVCpu->cpum.s.Guest.cr2;
983 break;
984 case USE_REG_CR3:
985 *pValue = pVCpu->cpum.s.Guest.cr3;
986 break;
987 case USE_REG_CR4:
988 *pValue = pVCpu->cpum.s.Guest.cr4;
989 break;
990 default:
991 return VERR_INVALID_PARAMETER;
992 }
993 return VINF_SUCCESS;
994}
995
996
997VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
998{
999 return pVCpu->cpum.s.Guest.dr[0];
1000}
1001
1002
1003VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1004{
1005 return pVCpu->cpum.s.Guest.dr[1];
1006}
1007
1008
1009VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1010{
1011 return pVCpu->cpum.s.Guest.dr[2];
1012}
1013
1014
1015VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1016{
1017 return pVCpu->cpum.s.Guest.dr[3];
1018}
1019
1020
1021VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1022{
1023 return pVCpu->cpum.s.Guest.dr[6];
1024}
1025
1026
1027VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1028{
1029 return pVCpu->cpum.s.Guest.dr[7];
1030}
1031
1032
1033VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1034{
1035 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1036 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1037 if (iReg == 4 || iReg == 5)
1038 iReg += 2;
1039 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1040 return VINF_SUCCESS;
1041}
1042
1043
1044VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1045{
1046 return pVCpu->cpum.s.Guest.msrEFER;
1047}
1048
1049
1050/**
1051 * Gets a CpuId leaf.
1052 *
1053 * @param pVCpu The VMCPU handle.
1054 * @param iLeaf The CPUID leaf to get.
1055 * @param pEax Where to store the EAX value.
1056 * @param pEbx Where to store the EBX value.
1057 * @param pEcx Where to store the ECX value.
1058 * @param pEdx Where to store the EDX value.
1059 */
1060VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1061{
1062 PVM pVM = pVCpu->CTX_SUFF(pVM);
1063
1064 PCCPUMCPUID pCpuId;
1065 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1066 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1067 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1068 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1069 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1070 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1071 else
1072 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1073
1074 bool fHasMoreCaches = (*pEcx == 0);
1075
1076 *pEax = pCpuId->eax;
1077 *pEbx = pCpuId->ebx;
1078 *pEcx = pCpuId->ecx;
1079 *pEdx = pCpuId->edx;
1080
1081 if ( iLeaf == 1
1082 && pVM->cCpus > 1)
1083 {
1084 /* Bits 31-24: Initial APIC ID */
1085 Assert(pVCpu->idCpu <= 255);
1086 *pEbx |= (pVCpu->idCpu << 24);
1087 }
1088
1089 if ( iLeaf == 4
1090 && fHasMoreCaches
1091 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1092 {
1093 /* Report L0 data cache, Linux'es num_cpu_cores() requires
1094 * that to be non-0 to detect core count correctly. */
1095 *pEax |= (1 << 5) /* level 1 */ | 1 /* 1 - data cache, 2 - i-cache, 3 - unified */ ;
1096 *pEbx = 63 /* linesize 64 */ ;
1097 }
1098
1099 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1100}
1101
1102/**
1103 * Gets a number of standard CPUID leafs.
1104 *
1105 * @returns Number of leafs.
1106 * @param pVM The VM handle.
1107 * @remark Intended for PATM.
1108 */
1109VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1110{
1111 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1112}
1113
1114
1115/**
1116 * Gets a number of extended CPUID leafs.
1117 *
1118 * @returns Number of leafs.
1119 * @param pVM The VM handle.
1120 * @remark Intended for PATM.
1121 */
1122VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1123{
1124 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1125}
1126
1127
1128/**
1129 * Gets a number of centaur CPUID leafs.
1130 *
1131 * @returns Number of leafs.
1132 * @param pVM The VM handle.
1133 * @remark Intended for PATM.
1134 */
1135VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1136{
1137 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1138}
1139
1140
1141/**
1142 * Sets a CPUID feature bit.
1143 *
1144 * @param pVM The VM Handle.
1145 * @param enmFeature The feature to set.
1146 */
1147VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1148{
1149 switch (enmFeature)
1150 {
1151 /*
1152 * Set the APIC bit in both feature masks.
1153 */
1154 case CPUMCPUIDFEATURE_APIC:
1155 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1156 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1157 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1158 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1159 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1160 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1161 break;
1162
1163 /*
1164 * Set the x2APIC bit in the standard feature mask.
1165 */
1166 case CPUMCPUIDFEATURE_X2APIC:
1167 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1168 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1169 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1170 break;
1171
1172 /*
1173 * Set the sysenter/sysexit bit in the standard feature mask.
1174 * Assumes the caller knows what it's doing! (host must support these)
1175 */
1176 case CPUMCPUIDFEATURE_SEP:
1177 {
1178 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1179 {
1180 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1181 return;
1182 }
1183
1184 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1185 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1186 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1187 break;
1188 }
1189
1190 /*
1191 * Set the syscall/sysret bit in the extended feature mask.
1192 * Assumes the caller knows what it's doing! (host must support these)
1193 */
1194 case CPUMCPUIDFEATURE_SYSCALL:
1195 {
1196 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1197 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1198 {
1199#if HC_ARCH_BITS == 32
1200 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1201 * Even when the cpu is capable of doing so in 64 bits mode.
1202 */
1203 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1204 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1205 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1206#endif
1207 {
1208 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1209 return;
1210 }
1211 }
1212 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1213 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1214 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1215 break;
1216 }
1217
1218 /*
1219 * Set the PAE bit in both feature masks.
1220 * Assumes the caller knows what it's doing! (host must support these)
1221 */
1222 case CPUMCPUIDFEATURE_PAE:
1223 {
1224 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1225 {
1226 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1227 return;
1228 }
1229
1230 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1231 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1232 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1233 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1234 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1235 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1236 break;
1237 }
1238
1239 /*
1240 * Set the LONG MODE bit in the extended feature mask.
1241 * Assumes the caller knows what it's doing! (host must support these)
1242 */
1243 case CPUMCPUIDFEATURE_LONG_MODE:
1244 {
1245 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1246 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1247 {
1248 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1249 return;
1250 }
1251
1252 /* Valid for both Intel and AMD. */
1253 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1254 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1255 break;
1256 }
1257
1258 /*
1259 * Set the NXE bit in the extended feature mask.
1260 * Assumes the caller knows what it's doing! (host must support these)
1261 */
1262 case CPUMCPUIDFEATURE_NXE:
1263 {
1264 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1265 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1266 {
1267 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1268 return;
1269 }
1270
1271 /* Valid for both Intel and AMD. */
1272 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1273 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1274 break;
1275 }
1276
1277 case CPUMCPUIDFEATURE_LAHF:
1278 {
1279 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1280 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1281 {
1282 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1283 return;
1284 }
1285
1286 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1287 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1288 break;
1289 }
1290
1291 case CPUMCPUIDFEATURE_PAT:
1292 {
1293 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1294 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1295 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1296 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1297 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1298 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1299 break;
1300 }
1301
1302 case CPUMCPUIDFEATURE_RDTSCP:
1303 {
1304 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1305 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP))
1306 {
1307 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1308 return;
1309 }
1310
1311 /* Valid for AMD only (for now). */
1312 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1313 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1314 break;
1315 }
1316
1317 default:
1318 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1319 break;
1320 }
1321 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1322 {
1323 PVMCPU pVCpu = &pVM->aCpus[i];
1324 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1325 }
1326}
1327
1328
1329/**
1330 * Queries a CPUID feature bit.
1331 *
1332 * @returns boolean for feature presence
1333 * @param pVM The VM Handle.
1334 * @param enmFeature The feature to query.
1335 */
1336VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1337{
1338 switch (enmFeature)
1339 {
1340 case CPUMCPUIDFEATURE_PAE:
1341 {
1342 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1343 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1344 break;
1345 }
1346
1347 case CPUMCPUIDFEATURE_RDTSCP:
1348 {
1349 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1350 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1351 break;
1352 }
1353
1354 case CPUMCPUIDFEATURE_LONG_MODE:
1355 {
1356 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1357 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1358 break;
1359 }
1360
1361 default:
1362 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1363 break;
1364 }
1365 return false;
1366}
1367
1368
1369/**
1370 * Clears a CPUID feature bit.
1371 *
1372 * @param pVM The VM Handle.
1373 * @param enmFeature The feature to clear.
1374 */
1375VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1376{
1377 switch (enmFeature)
1378 {
1379 /*
1380 * Set the APIC bit in both feature masks.
1381 */
1382 case CPUMCPUIDFEATURE_APIC:
1383 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1384 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1385 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1386 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1387 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1388 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1389 break;
1390
1391 /*
1392 * Clear the x2APIC bit in the standard feature mask.
1393 */
1394 case CPUMCPUIDFEATURE_X2APIC:
1395 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1396 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1397 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1398 break;
1399
1400 case CPUMCPUIDFEATURE_PAE:
1401 {
1402 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1403 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1404 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1405 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1406 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1407 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1408 break;
1409 }
1410
1411 case CPUMCPUIDFEATURE_PAT:
1412 {
1413 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1414 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1415 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1416 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1417 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1418 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1419 break;
1420 }
1421
1422 case CPUMCPUIDFEATURE_LONG_MODE:
1423 {
1424 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1425 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1426 break;
1427 }
1428
1429 case CPUMCPUIDFEATURE_LAHF:
1430 {
1431 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1432 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1433 break;
1434 }
1435
1436 default:
1437 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1438 break;
1439 }
1440 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1441 {
1442 PVMCPU pVCpu = &pVM->aCpus[i];
1443 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1444 }
1445}
1446
1447
1448/**
1449 * Gets the host CPU vendor
1450 *
1451 * @returns CPU vendor
1452 * @param pVM The VM handle.
1453 */
1454VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1455{
1456 return pVM->cpum.s.enmHostCpuVendor;
1457}
1458
1459/**
1460 * Gets the CPU vendor
1461 *
1462 * @returns CPU vendor
1463 * @param pVM The VM handle.
1464 */
1465VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1466{
1467 return pVM->cpum.s.enmGuestCpuVendor;
1468}
1469
1470
1471VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1472{
1473 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1474 return CPUMRecalcHyperDRx(pVCpu);
1475}
1476
1477
1478VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1479{
1480 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1481 return CPUMRecalcHyperDRx(pVCpu);
1482}
1483
1484
1485VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1486{
1487 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1488 return CPUMRecalcHyperDRx(pVCpu);
1489}
1490
1491
1492VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1493{
1494 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1495 return CPUMRecalcHyperDRx(pVCpu);
1496}
1497
1498
1499VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1500{
1501 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1502 return CPUMRecalcHyperDRx(pVCpu);
1503}
1504
1505
1506VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1507{
1508 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1509 return CPUMRecalcHyperDRx(pVCpu);
1510}
1511
1512
1513VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1514{
1515 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1516 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1517 if (iReg == 4 || iReg == 5)
1518 iReg += 2;
1519 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1520 return CPUMRecalcHyperDRx(pVCpu);
1521}
1522
1523
1524/**
1525 * Recalculates the hypvervisor DRx register values based on
1526 * current guest registers and DBGF breakpoints.
1527 *
1528 * This is called whenever a guest DRx register is modified and when DBGF
1529 * sets a hardware breakpoint. In guest context this function will reload
1530 * any (hyper) DRx registers which comes out with a different value.
1531 *
1532 * @returns VINF_SUCCESS.
1533 * @param pVCpu The VMCPU handle.
1534 */
1535VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1536{
1537 PVM pVM = pVCpu->CTX_SUFF(pVM);
1538
1539 /*
1540 * Compare the DR7s first.
1541 *
1542 * We only care about the enabled flags. The GE and LE flags are always
1543 * set and we don't care if the guest doesn't set them. GD is virtualized
1544 * when we dispatch #DB, we never enable it.
1545 */
1546 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1547#ifdef CPUM_VIRTUALIZE_DRX
1548 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1549#else
1550 const RTGCUINTREG uGstDr7 = 0;
1551#endif
1552 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1553 {
1554 /*
1555 * Ok, something is enabled. Recalc each of the breakpoints.
1556 * Straight forward code, not optimized/minimized in any way.
1557 */
1558 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1559
1560 /* bp 0 */
1561 RTGCUINTREG uNewDr0;
1562 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1563 {
1564 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1565 uNewDr0 = DBGFBpGetDR0(pVM);
1566 }
1567 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1568 {
1569 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1570 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1571 }
1572 else
1573 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
1574
1575 /* bp 1 */
1576 RTGCUINTREG uNewDr1;
1577 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1578 {
1579 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1580 uNewDr1 = DBGFBpGetDR1(pVM);
1581 }
1582 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1583 {
1584 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1585 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1586 }
1587 else
1588 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
1589
1590 /* bp 2 */
1591 RTGCUINTREG uNewDr2;
1592 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1593 {
1594 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1595 uNewDr2 = DBGFBpGetDR2(pVM);
1596 }
1597 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1598 {
1599 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1600 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1601 }
1602 else
1603 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
1604
1605 /* bp 3 */
1606 RTGCUINTREG uNewDr3;
1607 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1608 {
1609 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1610 uNewDr3 = DBGFBpGetDR3(pVM);
1611 }
1612 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1613 {
1614 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1615 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1616 }
1617 else
1618 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
1619
1620 /*
1621 * Apply the updates.
1622 */
1623#ifdef IN_RC
1624 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1625 {
1626 /** @todo save host DBx registers. */
1627 }
1628#endif
1629 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1630 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1631 CPUMSetHyperDR3(pVCpu, uNewDr3);
1632 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1633 CPUMSetHyperDR2(pVCpu, uNewDr2);
1634 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1635 CPUMSetHyperDR1(pVCpu, uNewDr1);
1636 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1637 CPUMSetHyperDR0(pVCpu, uNewDr0);
1638 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1639 CPUMSetHyperDR7(pVCpu, uNewDr7);
1640 }
1641 else
1642 {
1643#ifdef IN_RC
1644 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1645 {
1646 /** @todo restore host DBx registers. */
1647 }
1648#endif
1649 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1650 }
1651 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1652 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1653 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1654 pVCpu->cpum.s.Hyper.dr[7]));
1655
1656 return VINF_SUCCESS;
1657}
1658
1659#ifndef IN_RING0 /** @todo I don't think we need this in R0, so move it to CPUMAll.cpp? */
1660
1661/**
1662 * Transforms the guest CPU state to raw-ring mode.
1663 *
1664 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
1665 *
1666 * @returns VBox status. (recompiler failure)
1667 * @param pVCpu The VMCPU handle.
1668 * @param pCtxCore The context core (for trap usage).
1669 * @see @ref pg_raw
1670 */
1671VMMDECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
1672{
1673 PVM pVM = pVCpu->CTX_SUFF(pVM);
1674
1675 Assert(!pVM->cpum.s.fRawEntered);
1676 if (!pCtxCore)
1677 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
1678
1679 /*
1680 * Are we in Ring-0?
1681 */
1682 if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
1683 && !pCtxCore->eflags.Bits.u1VM)
1684 {
1685 /*
1686 * Enter execution mode.
1687 */
1688 PATMRawEnter(pVM, pCtxCore);
1689
1690 /*
1691 * Set CPL to Ring-1.
1692 */
1693 pCtxCore->ss |= 1;
1694 if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
1695 pCtxCore->cs |= 1;
1696 }
1697 else
1698 {
1699 AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
1700 ("ring-1 code not supported\n"));
1701 /*
1702 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
1703 */
1704 PATMRawEnter(pVM, pCtxCore);
1705 }
1706
1707 /*
1708 * Assert sanity.
1709 */
1710 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
1711 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
1712 || pCtxCore->eflags.Bits.u1VM,
1713 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1714 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
1715 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
1716
1717 pVM->cpum.s.fRawEntered = true;
1718 return VINF_SUCCESS;
1719}
1720
1721
1722/**
1723 * Transforms the guest CPU state from raw-ring mode to correct values.
1724 *
1725 * This function will change any selector registers with DPL=1 to DPL=0.
1726 *
1727 * @returns Adjusted rc.
1728 * @param pVCpu The VMCPU handle.
1729 * @param rc Raw mode return code
1730 * @param pCtxCore The context core (for trap usage).
1731 * @see @ref pg_raw
1732 */
1733VMMDECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
1734{
1735 PVM pVM = pVCpu->CTX_SUFF(pVM);
1736
1737 /*
1738 * Don't leave if we've already left (in GC).
1739 */
1740 Assert(pVM->cpum.s.fRawEntered);
1741 if (!pVM->cpum.s.fRawEntered)
1742 return rc;
1743 pVM->cpum.s.fRawEntered = false;
1744
1745 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1746 if (!pCtxCore)
1747 pCtxCore = CPUMCTX2CORE(pCtx);
1748 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss & X86_SEL_RPL));
1749 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
1750 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1751
1752 /*
1753 * Are we executing in raw ring-1?
1754 */
1755 if ( (pCtxCore->ss & X86_SEL_RPL) == 1
1756 && !pCtxCore->eflags.Bits.u1VM)
1757 {
1758 /*
1759 * Leave execution mode.
1760 */
1761 PATMRawLeave(pVM, pCtxCore, rc);
1762 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
1763 /** @todo See what happens if we remove this. */
1764 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1765 pCtxCore->ds &= ~X86_SEL_RPL;
1766 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1767 pCtxCore->es &= ~X86_SEL_RPL;
1768 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1769 pCtxCore->fs &= ~X86_SEL_RPL;
1770 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1771 pCtxCore->gs &= ~X86_SEL_RPL;
1772
1773 /*
1774 * Ring-1 selector => Ring-0.
1775 */
1776 pCtxCore->ss &= ~X86_SEL_RPL;
1777 if ((pCtxCore->cs & X86_SEL_RPL) == 1)
1778 pCtxCore->cs &= ~X86_SEL_RPL;
1779 }
1780 else
1781 {
1782 /*
1783 * PATM is taking care of the IOPL and IF flags for us.
1784 */
1785 PATMRawLeave(pVM, pCtxCore, rc);
1786 if (!pCtxCore->eflags.Bits.u1VM)
1787 {
1788 /** @todo See what happens if we remove this. */
1789 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1790 pCtxCore->ds &= ~X86_SEL_RPL;
1791 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1792 pCtxCore->es &= ~X86_SEL_RPL;
1793 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1794 pCtxCore->fs &= ~X86_SEL_RPL;
1795 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1796 pCtxCore->gs &= ~X86_SEL_RPL;
1797 }
1798 }
1799
1800 return rc;
1801}
1802
1803/**
1804 * Updates the EFLAGS while we're in raw-mode.
1805 *
1806 * @param pVCpu The VMCPU handle.
1807 * @param pCtxCore The context core.
1808 * @param eflags The new EFLAGS value.
1809 */
1810VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags)
1811{
1812 PVM pVM = pVCpu->CTX_SUFF(pVM);
1813
1814 if (!pVM->cpum.s.fRawEntered)
1815 {
1816 pCtxCore->eflags.u32 = eflags;
1817 return;
1818 }
1819 PATMRawSetEFlags(pVM, pCtxCore, eflags);
1820}
1821
1822#endif /* !IN_RING0 */
1823
1824/**
1825 * Gets the EFLAGS while we're in raw-mode.
1826 *
1827 * @returns The eflags.
1828 * @param pVCpu The VMCPU handle.
1829 * @param pCtxCore The context core.
1830 */
1831VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
1832{
1833#ifdef IN_RING0
1834 return pCtxCore->eflags.u32;
1835#else
1836 PVM pVM = pVCpu->CTX_SUFF(pVM);
1837
1838 if (!pVM->cpum.s.fRawEntered)
1839 return pCtxCore->eflags.u32;
1840 return PATMRawGetEFlags(pVM, pCtxCore);
1841#endif
1842}
1843
1844
1845/**
1846 * Gets and resets the changed flags (CPUM_CHANGED_*).
1847 * Only REM should call this function.
1848 *
1849 * @returns The changed flags.
1850 * @param pVCpu The VMCPU handle.
1851 */
1852VMMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVMCPU pVCpu)
1853{
1854 unsigned fFlags = pVCpu->cpum.s.fChanged;
1855 pVCpu->cpum.s.fChanged = 0;
1856 /** @todo change the switcher to use the fChanged flags. */
1857 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
1858 {
1859 fFlags |= CPUM_CHANGED_FPU_REM;
1860 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
1861 }
1862 return fFlags;
1863}
1864
1865
1866/**
1867 * Sets the specified changed flags (CPUM_CHANGED_*).
1868 *
1869 * @param pVCpu The VMCPU handle.
1870 */
1871VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
1872{
1873 pVCpu->cpum.s.fChanged |= fChangedFlags;
1874}
1875
1876
1877/**
1878 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
1879 * @returns true if supported.
1880 * @returns false if not supported.
1881 * @param pVM The VM handle.
1882 */
1883VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
1884{
1885 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
1886}
1887
1888
1889/**
1890 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1891 * @returns true if used.
1892 * @returns false if not used.
1893 * @param pVM The VM handle.
1894 */
1895VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1896{
1897 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
1898}
1899
1900
1901/**
1902 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1903 * @returns true if used.
1904 * @returns false if not used.
1905 * @param pVM The VM handle.
1906 */
1907VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1908{
1909 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
1910}
1911
1912#ifndef IN_RING3
1913
1914/**
1915 * Lazily sync in the FPU/XMM state
1916 *
1917 * @returns VBox status code.
1918 * @param pVCpu VMCPU handle
1919 */
1920VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
1921{
1922 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
1923}
1924
1925#endif /* !IN_RING3 */
1926
1927/**
1928 * Checks if we activated the FPU/XMM state of the guest OS
1929 * @returns true if we did.
1930 * @returns false if not.
1931 * @param pVCpu The VMCPU handle.
1932 */
1933VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
1934{
1935 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
1936}
1937
1938
1939/**
1940 * Deactivate the FPU/XMM state of the guest OS
1941 * @param pVCpu The VMCPU handle.
1942 */
1943VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
1944{
1945 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
1946}
1947
1948
1949/**
1950 * Checks if the guest debug state is active
1951 *
1952 * @returns boolean
1953 * @param pVM VM handle.
1954 */
1955VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
1956{
1957 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
1958}
1959
1960/**
1961 * Checks if the hyper debug state is active
1962 *
1963 * @returns boolean
1964 * @param pVM VM handle.
1965 */
1966VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
1967{
1968 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
1969}
1970
1971
1972/**
1973 * Mark the guest's debug state as inactive
1974 *
1975 * @returns boolean
1976 * @param pVM VM handle.
1977 */
1978VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
1979{
1980 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1981}
1982
1983
1984/**
1985 * Mark the hypervisor's debug state as inactive
1986 *
1987 * @returns boolean
1988 * @param pVM VM handle.
1989 */
1990VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
1991{
1992 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
1993}
1994
1995/**
1996 * Checks if the hidden selector registers are valid
1997 * @returns true if they are.
1998 * @returns false if not.
1999 * @param pVM The VM handle.
2000 */
2001VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM)
2002{
2003 return HWACCMIsEnabled(pVM);
2004}
2005
2006
2007
2008/**
2009 * Get the current privilege level of the guest.
2010 *
2011 * @returns cpl
2012 * @param pVM VM Handle.
2013 * @param pRegFrame Trap register frame.
2014 */
2015VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2016{
2017 uint32_t cpl;
2018
2019 if (CPUMAreHiddenSelRegsValid(pVCpu->CTX_SUFF(pVM)))
2020 {
2021 /*
2022 * The hidden CS.DPL register is always equal to the CPL, it is
2023 * not affected by loading a conforming coding segment.
2024 *
2025 * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
2026 * at SS. (ACP2 regression during install after a far call to ring 2)
2027 */
2028 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2029 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
2030 else
2031 cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2032 }
2033 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2034 {
2035 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
2036 {
2037 /*
2038 * The SS RPL is always equal to the CPL, while the CS RPL
2039 * isn't necessarily equal if the segment is conforming.
2040 * See section 4.11.1 in the AMD manual.
2041 */
2042 cpl = (pCtxCore->ss & X86_SEL_RPL);
2043#ifndef IN_RING0
2044 if (cpl == 1)
2045 cpl = 0;
2046#endif
2047 }
2048 else
2049 cpl = 3;
2050 }
2051 else
2052 cpl = 0; /* real mode; cpl is zero */
2053
2054 return cpl;
2055}
2056
2057
2058/**
2059 * Gets the current guest CPU mode.
2060 *
2061 * If paging mode is what you need, check out PGMGetGuestMode().
2062 *
2063 * @returns The CPU mode.
2064 * @param pVCpu The VMCPU handle.
2065 */
2066VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2067{
2068 CPUMMODE enmMode;
2069 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2070 enmMode = CPUMMODE_REAL;
2071 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2072 enmMode = CPUMMODE_PROTECTED;
2073 else
2074 enmMode = CPUMMODE_LONG;
2075
2076 return enmMode;
2077}
2078
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