VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 84823

Last change on this file since 84823 was 82968, checked in by vboxsync, 5 years ago

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1/* $Id: CPUMAllMsrs.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/apic.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/hm_vmx.h>
27#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
28# include <VBox/vmm/iem.h>
29#endif
30#include <VBox/vmm/tm.h>
31#include <VBox/vmm/gim.h>
32#include "CPUMInternal.h"
33#include <VBox/vmm/vmcc.h>
34#include <VBox/err.h>
35
36
37/*********************************************************************************************************************************
38* Defined Constants And Macros *
39*********************************************************************************************************************************/
40/**
41 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
42 * pointing to it.
43 *
44 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
45 * correctly.
46 */
47#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
48 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
49 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
50 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
51 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
52 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
53 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
54
55
56/*********************************************************************************************************************************
57* Structures and Typedefs *
58*********************************************************************************************************************************/
59
60/**
61 * Implements reading one or more MSRs.
62 *
63 * @returns VBox status code.
64 * @retval VINF_SUCCESS on success.
65 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
66 * current context (raw-mode or ring-0).
67 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
68 *
69 * @param pVCpu The cross context virtual CPU structure.
70 * @param idMsr The MSR we're reading.
71 * @param pRange The MSR range descriptor.
72 * @param puValue Where to return the value.
73 */
74typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
75/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
76typedef FNCPUMRDMSR *PFNCPUMRDMSR;
77
78
79/**
80 * Implements writing one or more MSRs.
81 *
82 * @retval VINF_SUCCESS on success.
83 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
84 * current context (raw-mode or ring-0).
85 * @retval VERR_CPUM_RAISE_GP_0 on failure.
86 *
87 * @param pVCpu The cross context virtual CPU structure.
88 * @param idMsr The MSR we're writing.
89 * @param pRange The MSR range descriptor.
90 * @param uValue The value to set, ignored bits masked.
91 * @param uRawValue The raw value with the ignored bits not masked.
92 */
93typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
94/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
95typedef FNCPUMWRMSR *PFNCPUMWRMSR;
96
97
98
99/*
100 * Generic functions.
101 * Generic functions.
102 * Generic functions.
103 */
104
105
106/** @callback_method_impl{FNCPUMRDMSR} */
107static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
108{
109 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
110 *puValue = pRange->uValue;
111 return VINF_SUCCESS;
112}
113
114
115/** @callback_method_impl{FNCPUMWRMSR} */
116static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
117{
118 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
119 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
120 return VINF_SUCCESS;
121}
122
123
124/** @callback_method_impl{FNCPUMRDMSR} */
125static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
126{
127 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
128 return VERR_CPUM_RAISE_GP_0;
129}
130
131
132/** @callback_method_impl{FNCPUMWRMSR} */
133static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
134{
135 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
136 Assert(pRange->fWrGpMask == UINT64_MAX);
137 return VERR_CPUM_RAISE_GP_0;
138}
139
140
141
142
143/*
144 * IA32
145 * IA32
146 * IA32
147 */
148
149/** @callback_method_impl{FNCPUMRDMSR} */
150static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
151{
152 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
153 *puValue = 0; /** @todo implement machine check injection. */
154 return VINF_SUCCESS;
155}
156
157
158/** @callback_method_impl{FNCPUMWRMSR} */
159static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
160{
161 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
162 /** @todo implement machine check injection. */
163 return VINF_SUCCESS;
164}
165
166
167/** @callback_method_impl{FNCPUMRDMSR} */
168static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
169{
170 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
171 *puValue = 0; /** @todo implement machine check injection. */
172 return VINF_SUCCESS;
173}
174
175
176/** @callback_method_impl{FNCPUMWRMSR} */
177static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
178{
179 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
180 /** @todo implement machine check injection. */
181 return VINF_SUCCESS;
182}
183
184
185/** @callback_method_impl{FNCPUMRDMSR} */
186static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
187{
188 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
189 *puValue = TMCpuTickGet(pVCpu);
190#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
191 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
192#endif
193 return VINF_SUCCESS;
194}
195
196
197/** @callback_method_impl{FNCPUMWRMSR} */
198static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
199{
200 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
201 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
202 return VINF_SUCCESS;
203}
204
205
206/** @callback_method_impl{FNCPUMRDMSR} */
207static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
208{
209 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
210 uint64_t uValue = pRange->uValue;
211 if (uValue & 0x1f00)
212 {
213 /* Max allowed bus ratio present. */
214 /** @todo Implement scaled BUS frequency. */
215 }
216
217 *puValue = uValue;
218 return VINF_SUCCESS;
219}
220
221
222/** @callback_method_impl{FNCPUMRDMSR} */
223static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
224{
225 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
226 return APICGetBaseMsr(pVCpu, puValue);
227}
228
229
230/** @callback_method_impl{FNCPUMWRMSR} */
231static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
232{
233 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
234 return APICSetBaseMsr(pVCpu, uValue);
235}
236
237
238/** @callback_method_impl{FNCPUMRDMSR} */
239static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
240{
241 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
242 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64FeatCtrl;
243 return VINF_SUCCESS;
244}
245
246
247/** @callback_method_impl{FNCPUMWRMSR} */
248static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
249{
250 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
251 return VERR_CPUM_RAISE_GP_0;
252}
253
254
255/** @callback_method_impl{FNCPUMRDMSR} */
256static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
257{
258 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
259 /** @todo fake microcode update. */
260 *puValue = pRange->uValue;
261 return VINF_SUCCESS;
262}
263
264
265/** @callback_method_impl{FNCPUMWRMSR} */
266static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
267{
268 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
269 /* Normally, zero is written to Ia32BiosSignId before reading it in order
270 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
271 of the database entry should take care of most illegal writes for now, so
272 just ignore all writes atm. */
273 return VINF_SUCCESS;
274}
275
276
277/** @callback_method_impl{FNCPUMWRMSR} */
278static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
279{
280 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
281
282 /* Microcode updates cannot be loaded in VMX non-root mode. */
283 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
284 return VINF_SUCCESS;
285
286 /** @todo Fake bios update trigger better. The value is the address to an
287 * update package, I think. We should probably GP if it's invalid. */
288 return VINF_SUCCESS;
289}
290
291
292/**
293 * Get MSR_IA32_SMM_MONITOR_CTL value for IEM and cpumMsrRd_Ia32SmmMonitorCtl.
294 *
295 * @returns The MSR_IA32_SMM_MONITOR_CTL value.
296 * @param pVCpu The cross context per CPU structure.
297 */
298VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPU pVCpu)
299{
300 /* We do not support dual-monitor treatment for SMI and SMM. */
301 /** @todo SMM. */
302 RT_NOREF(pVCpu);
303 return 0;
304}
305
306
307/** @callback_method_impl{FNCPUMRDMSR} */
308static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
309{
310 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
311 *puValue = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
312 return VINF_SUCCESS;
313}
314
315
316/** @callback_method_impl{FNCPUMWRMSR} */
317static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
318{
319 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
320 /** @todo SMM. */
321 return VINF_SUCCESS;
322}
323
324
325/** @callback_method_impl{FNCPUMRDMSR} */
326static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
327{
328 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
329 /** @todo check CPUID leaf 0ah. */
330 *puValue = 0;
331 return VINF_SUCCESS;
332}
333
334
335/** @callback_method_impl{FNCPUMWRMSR} */
336static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
337{
338 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
339 /** @todo check CPUID leaf 0ah. */
340 return VINF_SUCCESS;
341}
342
343
344/** @callback_method_impl{FNCPUMRDMSR} */
345static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
346{
347 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
348 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
349 *puValue = 0x40; /** @todo Change to CPU cache line size. */
350 return VINF_SUCCESS;
351}
352
353
354/** @callback_method_impl{FNCPUMWRMSR} */
355static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
356{
357 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
358 /** @todo should remember writes, though it's supposedly something only a BIOS
359 * would write so, it's not extremely important. */
360 return VINF_SUCCESS;
361}
362
363/** @callback_method_impl{FNCPUMRDMSR} */
364static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
365{
366 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
367 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
368 * what we want? */
369 *puValue = TMCpuTickGet(pVCpu);
370#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
371 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
372#endif
373 return VINF_SUCCESS;
374}
375
376
377/** @callback_method_impl{FNCPUMWRMSR} */
378static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
379{
380 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
381 /** @todo Write MPERF: Calc adjustment. */
382 return VINF_SUCCESS;
383}
384
385
386/** @callback_method_impl{FNCPUMRDMSR} */
387static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
388{
389 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
390 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
391 * what we want? */
392 *puValue = TMCpuTickGet(pVCpu);
393#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
394 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
395#endif
396 return VINF_SUCCESS;
397}
398
399
400/** @callback_method_impl{FNCPUMWRMSR} */
401static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
402{
403 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
404 /** @todo Write APERF: Calc adjustment. */
405 return VINF_SUCCESS;
406}
407
408
409/**
410 * Get fixed IA32_MTRR_CAP value for NEM and cpumMsrRd_Ia32MtrrCap.
411 *
412 * @returns Fixed IA32_MTRR_CAP value.
413 * @param pVCpu The cross context per CPU structure.
414 */
415VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu)
416{
417 RT_NOREF_PV(pVCpu);
418
419 /* This is currently a bit weird. :-) */
420 uint8_t const cVariableRangeRegs = 0;
421 bool const fSystemManagementRangeRegisters = false;
422 bool const fFixedRangeRegisters = false;
423 bool const fWriteCombiningType = false;
424 return cVariableRangeRegs
425 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
426 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
427 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
428}
429
430/** @callback_method_impl{FNCPUMRDMSR} */
431static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
432{
433 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
434 *puValue = CPUMGetGuestIa32MtrrCap(pVCpu);
435 return VINF_SUCCESS;
436}
437
438
439/** @callback_method_impl{FNCPUMRDMSR} */
440static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
441{
442 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
443 /** @todo Implement variable MTRR storage. */
444 Assert(pRange->uValue == (idMsr - 0x200) / 2);
445 *puValue = 0;
446 return VINF_SUCCESS;
447}
448
449
450/** @callback_method_impl{FNCPUMWRMSR} */
451static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
452{
453 /*
454 * Validate the value.
455 */
456 Assert(pRange->uValue == (idMsr - 0x200) / 2);
457 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
458
459 uint8_t uType = uValue & 0xff;
460 if ((uType >= 7) || (uType == 2) || (uType == 3))
461 {
462 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uType));
463 return VERR_CPUM_RAISE_GP_0;
464 }
465
466 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
467 if (fInvPhysMask & uValue)
468 {
469 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
470 idMsr, uValue, uValue & fInvPhysMask));
471 return VERR_CPUM_RAISE_GP_0;
472 }
473
474 /*
475 * Store it.
476 */
477 /** @todo Implement variable MTRR storage. */
478 return VINF_SUCCESS;
479}
480
481
482/** @callback_method_impl{FNCPUMRDMSR} */
483static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
484{
485 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
486 /** @todo Implement variable MTRR storage. */
487 Assert(pRange->uValue == (idMsr - 0x200) / 2);
488 *puValue = 0;
489 return VINF_SUCCESS;
490}
491
492
493/** @callback_method_impl{FNCPUMWRMSR} */
494static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
495{
496 /*
497 * Validate the value.
498 */
499 Assert(pRange->uValue == (idMsr - 0x200) / 2);
500 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
501
502 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
503 if (fInvPhysMask & uValue)
504 {
505 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
506 idMsr, uValue, uValue & fInvPhysMask));
507 return VERR_CPUM_RAISE_GP_0;
508 }
509
510 /*
511 * Store it.
512 */
513 /** @todo Implement variable MTRR storage. */
514 return VINF_SUCCESS;
515}
516
517
518/** @callback_method_impl{FNCPUMRDMSR} */
519static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
520{
521 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
522 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
523 *puValue = *puFixedMtrr;
524 return VINF_SUCCESS;
525}
526
527
528/** @callback_method_impl{FNCPUMWRMSR} */
529static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
530{
531 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
532 RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue);
533
534 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
535 {
536 uint8_t uType = (uint8_t)(uValue >> cShift);
537 if ((uType >= 7) || (uType == 2) || (uType == 3))
538 {
539 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
540 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
541 return VERR_CPUM_RAISE_GP_0;
542 }
543 }
544 *puFixedMtrr = uValue;
545 return VINF_SUCCESS;
546}
547
548
549/** @callback_method_impl{FNCPUMRDMSR} */
550static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
551{
552 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
553 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
554 return VINF_SUCCESS;
555}
556
557
558/** @callback_method_impl{FNCPUMWRMSR} */
559static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
560{
561 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
562
563 uint8_t uType = uValue & 0xff;
564 if ((uType >= 7) || (uType == 2) || (uType == 3))
565 {
566 Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uType));
567 return VERR_CPUM_RAISE_GP_0;
568 }
569
570 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
571 return VINF_SUCCESS;
572}
573
574
575/** @callback_method_impl{FNCPUMRDMSR} */
576static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
577{
578 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
579 *puValue = pVCpu->cpum.s.Guest.msrPAT;
580 return VINF_SUCCESS;
581}
582
583
584/** @callback_method_impl{FNCPUMWRMSR} */
585static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
586{
587 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
588 if (CPUMIsPatMsrValid(uValue))
589 {
590 pVCpu->cpum.s.Guest.msrPAT = uValue;
591 return VINF_SUCCESS;
592 }
593 return VERR_CPUM_RAISE_GP_0;
594}
595
596
597/** @callback_method_impl{FNCPUMRDMSR} */
598static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
599{
600 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
601 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
602 return VINF_SUCCESS;
603}
604
605
606/** @callback_method_impl{FNCPUMWRMSR} */
607static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
608{
609 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
610
611 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
612 there are generally 32-bit working bits backing this register. */
613 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
614 return VINF_SUCCESS;
615}
616
617
618/** @callback_method_impl{FNCPUMRDMSR} */
619static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
620{
621 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
622 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
623 return VINF_SUCCESS;
624}
625
626
627/** @callback_method_impl{FNCPUMWRMSR} */
628static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
629{
630 if (X86_IS_CANONICAL(uValue))
631 {
632 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
633 return VINF_SUCCESS;
634 }
635 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
636 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
637 return VERR_CPUM_RAISE_GP_0;
638}
639
640
641/** @callback_method_impl{FNCPUMRDMSR} */
642static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
643{
644 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
645 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
646 return VINF_SUCCESS;
647}
648
649
650/** @callback_method_impl{FNCPUMWRMSR} */
651static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
652{
653 if (X86_IS_CANONICAL(uValue))
654 {
655 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
656 return VINF_SUCCESS;
657 }
658 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
659 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
660 return VERR_CPUM_RAISE_GP_0;
661}
662
663
664/** @callback_method_impl{FNCPUMRDMSR} */
665static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
666{
667#if 0 /** @todo implement machine checks. */
668 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
669#else
670 *puValue = 0;
671#endif
672 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
673 return VINF_SUCCESS;
674}
675
676
677/** @callback_method_impl{FNCPUMRDMSR} */
678static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
679{
680 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
681 /** @todo implement machine checks. */
682 *puValue = 0;
683 return VINF_SUCCESS;
684}
685
686
687/** @callback_method_impl{FNCPUMWRMSR} */
688static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
689{
690 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
691 /** @todo implement machine checks. */
692 return VINF_SUCCESS;
693}
694
695
696/** @callback_method_impl{FNCPUMRDMSR} */
697static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
698{
699 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
700 /** @todo implement machine checks. */
701 *puValue = 0;
702 return VINF_SUCCESS;
703}
704
705
706/** @callback_method_impl{FNCPUMWRMSR} */
707static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
708{
709 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
710 /** @todo implement machine checks. */
711 return VINF_SUCCESS;
712}
713
714
715/** @callback_method_impl{FNCPUMRDMSR} */
716static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
717{
718 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
719 /** @todo implement IA32_DEBUGCTL. */
720 *puValue = 0;
721 return VINF_SUCCESS;
722}
723
724
725/** @callback_method_impl{FNCPUMWRMSR} */
726static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
727{
728 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
729 /** @todo implement IA32_DEBUGCTL. */
730 return VINF_SUCCESS;
731}
732
733
734/** @callback_method_impl{FNCPUMRDMSR} */
735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
736{
737 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
738 /** @todo implement intel SMM. */
739 *puValue = 0;
740 return VINF_SUCCESS;
741}
742
743
744/** @callback_method_impl{FNCPUMWRMSR} */
745static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
746{
747 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
748 /** @todo implement intel SMM. */
749 return VERR_CPUM_RAISE_GP_0;
750}
751
752
753/** @callback_method_impl{FNCPUMRDMSR} */
754static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
755{
756 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
757 /** @todo implement intel SMM. */
758 *puValue = 0;
759 return VINF_SUCCESS;
760}
761
762
763/** @callback_method_impl{FNCPUMWRMSR} */
764static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
765{
766 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
767 /** @todo implement intel SMM. */
768 return VERR_CPUM_RAISE_GP_0;
769}
770
771
772/** @callback_method_impl{FNCPUMRDMSR} */
773static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
774{
775 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
776 /** @todo implement intel direct cache access (DCA)?? */
777 *puValue = 0;
778 return VINF_SUCCESS;
779}
780
781
782/** @callback_method_impl{FNCPUMWRMSR} */
783static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
784{
785 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
786 /** @todo implement intel direct cache access (DCA)?? */
787 return VINF_SUCCESS;
788}
789
790
791/** @callback_method_impl{FNCPUMRDMSR} */
792static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
793{
794 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
795 /** @todo implement intel direct cache access (DCA)?? */
796 *puValue = 0;
797 return VINF_SUCCESS;
798}
799
800
801/** @callback_method_impl{FNCPUMRDMSR} */
802static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
803{
804 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
805 /** @todo implement intel direct cache access (DCA)?? */
806 *puValue = 0;
807 return VINF_SUCCESS;
808}
809
810
811/** @callback_method_impl{FNCPUMWRMSR} */
812static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
813{
814 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
815 /** @todo implement intel direct cache access (DCA)?? */
816 return VINF_SUCCESS;
817}
818
819
820/** @callback_method_impl{FNCPUMRDMSR} */
821static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
822{
823 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
824 /** @todo implement IA32_PERFEVTSEL0+. */
825 *puValue = 0;
826 return VINF_SUCCESS;
827}
828
829
830/** @callback_method_impl{FNCPUMWRMSR} */
831static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
832{
833 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
834 /** @todo implement IA32_PERFEVTSEL0+. */
835 return VINF_SUCCESS;
836}
837
838
839/** @callback_method_impl{FNCPUMRDMSR} */
840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
841{
842 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
843 uint64_t uValue = pRange->uValue;
844
845 /* Always provide the max bus ratio for now. XNU expects it. */
846 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
847
848 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
849 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
850 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
851 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
852 if (uTscRatio > 0x1f)
853 uTscRatio = 0x1f;
854 uValue |= (uint64_t)uTscRatio << 40;
855
856 *puValue = uValue;
857 return VINF_SUCCESS;
858}
859
860
861/** @callback_method_impl{FNCPUMWRMSR} */
862static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
863{
864 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
865 /* Pentium4 allows writing, but all bits are ignored. */
866 return VINF_SUCCESS;
867}
868
869
870/** @callback_method_impl{FNCPUMRDMSR} */
871static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
872{
873 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
874 /** @todo implement IA32_PERFCTL. */
875 *puValue = 0;
876 return VINF_SUCCESS;
877}
878
879
880/** @callback_method_impl{FNCPUMWRMSR} */
881static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
882{
883 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
884 /** @todo implement IA32_PERFCTL. */
885 return VINF_SUCCESS;
886}
887
888
889/** @callback_method_impl{FNCPUMRDMSR} */
890static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
891{
892 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
893 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
894 *puValue = 0;
895 return VINF_SUCCESS;
896}
897
898
899/** @callback_method_impl{FNCPUMWRMSR} */
900static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
901{
902 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
903 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
904 return VINF_SUCCESS;
905}
906
907
908/** @callback_method_impl{FNCPUMRDMSR} */
909static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
910{
911 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
912 /** @todo implement performance counters. */
913 *puValue = 0;
914 return VINF_SUCCESS;
915}
916
917
918/** @callback_method_impl{FNCPUMWRMSR} */
919static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
920{
921 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
922 /** @todo implement performance counters. */
923 return VINF_SUCCESS;
924}
925
926
927/** @callback_method_impl{FNCPUMRDMSR} */
928static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
929{
930 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
931 /** @todo implement performance counters. */
932 *puValue = 0;
933 return VINF_SUCCESS;
934}
935
936
937/** @callback_method_impl{FNCPUMWRMSR} */
938static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
939{
940 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
941 /** @todo implement performance counters. */
942 return VINF_SUCCESS;
943}
944
945
946/** @callback_method_impl{FNCPUMRDMSR} */
947static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
948{
949 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
950 /** @todo implement performance counters. */
951 *puValue = 0;
952 return VINF_SUCCESS;
953}
954
955
956/** @callback_method_impl{FNCPUMWRMSR} */
957static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
958{
959 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
960 /** @todo implement performance counters. */
961 return VINF_SUCCESS;
962}
963
964
965/** @callback_method_impl{FNCPUMRDMSR} */
966static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
967{
968 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
969 /** @todo implement performance counters. */
970 *puValue = 0;
971 return VINF_SUCCESS;
972}
973
974
975/** @callback_method_impl{FNCPUMWRMSR} */
976static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
977{
978 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
979 /** @todo implement performance counters. */
980 return VINF_SUCCESS;
981}
982
983
984/** @callback_method_impl{FNCPUMRDMSR} */
985static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
986{
987 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
988 /** @todo implement performance counters. */
989 *puValue = 0;
990 return VINF_SUCCESS;
991}
992
993
994/** @callback_method_impl{FNCPUMWRMSR} */
995static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
996{
997 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
998 /** @todo implement performance counters. */
999 return VINF_SUCCESS;
1000}
1001
1002
1003/** @callback_method_impl{FNCPUMRDMSR} */
1004static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1005{
1006 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1007 /** @todo implement performance counters. */
1008 *puValue = 0;
1009 return VINF_SUCCESS;
1010}
1011
1012
1013/** @callback_method_impl{FNCPUMWRMSR} */
1014static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1015{
1016 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1017 /** @todo implement performance counters. */
1018 return VINF_SUCCESS;
1019}
1020
1021
1022/** @callback_method_impl{FNCPUMRDMSR} */
1023static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1024{
1025 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1026 /** @todo implement IA32_CLOCK_MODULATION. */
1027 *puValue = 0;
1028 return VINF_SUCCESS;
1029}
1030
1031
1032/** @callback_method_impl{FNCPUMWRMSR} */
1033static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1034{
1035 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1036 /** @todo implement IA32_CLOCK_MODULATION. */
1037 return VINF_SUCCESS;
1038}
1039
1040
1041/** @callback_method_impl{FNCPUMRDMSR} */
1042static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1043{
1044 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1045 /** @todo implement IA32_THERM_INTERRUPT. */
1046 *puValue = 0;
1047 return VINF_SUCCESS;
1048}
1049
1050
1051/** @callback_method_impl{FNCPUMWRMSR} */
1052static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1053{
1054 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1055 /** @todo implement IA32_THERM_STATUS. */
1056 return VINF_SUCCESS;
1057}
1058
1059
1060/** @callback_method_impl{FNCPUMRDMSR} */
1061static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1062{
1063 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1064 /** @todo implement IA32_THERM_STATUS. */
1065 *puValue = 0;
1066 return VINF_SUCCESS;
1067}
1068
1069
1070/** @callback_method_impl{FNCPUMWRMSR} */
1071static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1072{
1073 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1074 /** @todo implement IA32_THERM_INTERRUPT. */
1075 return VINF_SUCCESS;
1076}
1077
1078
1079/** @callback_method_impl{FNCPUMRDMSR} */
1080static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1081{
1082 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1083 /** @todo implement IA32_THERM2_CTL. */
1084 *puValue = 0;
1085 return VINF_SUCCESS;
1086}
1087
1088
1089/** @callback_method_impl{FNCPUMWRMSR} */
1090static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1091{
1092 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1093 /** @todo implement IA32_THERM2_CTL. */
1094 return VINF_SUCCESS;
1095}
1096
1097
1098/** @callback_method_impl{FNCPUMRDMSR} */
1099static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1100{
1101 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1102 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1103 return VINF_SUCCESS;
1104}
1105
1106
1107/** @callback_method_impl{FNCPUMWRMSR} */
1108static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1109{
1110 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1111#ifdef LOG_ENABLED
1112 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1113#endif
1114
1115 /* Unsupported bits are generally ignored and stripped by the MSR range
1116 entry that got us here. So, we just need to preserve fixed bits. */
1117 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
1118 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1119 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
1120
1121 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
1122 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
1123
1124 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1125 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1126 return VINF_SUCCESS;
1127}
1128
1129
1130/** @callback_method_impl{FNCPUMRDMSR} */
1131static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1132{
1133 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange);
1134
1135 /** @todo Implement machine check exception injection. */
1136 switch (idMsr & 3)
1137 {
1138 case 0:
1139 case 1:
1140 *puValue = 0;
1141 break;
1142
1143 /* The ADDR and MISC registers aren't accessible since the
1144 corresponding STATUS bits are zero. */
1145 case 2:
1146 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1147 return VERR_CPUM_RAISE_GP_0;
1148 case 3:
1149 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1150 return VERR_CPUM_RAISE_GP_0;
1151 }
1152 return VINF_SUCCESS;
1153}
1154
1155
1156/** @callback_method_impl{FNCPUMWRMSR} */
1157static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1158{
1159 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1160 switch (idMsr & 3)
1161 {
1162 case 0:
1163 /* Ignore writes to the CTL register. */
1164 break;
1165
1166 case 1:
1167 /* According to specs, the STATUS register can only be written to
1168 with the value 0. VBoxCpuReport thinks different for a
1169 Pentium M Dothan, but implementing according to specs now. */
1170 if (uValue != 0)
1171 {
1172 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1173 return VERR_CPUM_RAISE_GP_0;
1174 }
1175 break;
1176
1177 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1178 Writing 1s will GP. Need to figure out how this relates to the
1179 ADDRV and MISCV status flags. If writing is independent of those
1180 bits, we need to know whether the CPU really implements them since
1181 that is exposed by writing 0 to them.
1182 Implementing the solution with the fewer GPs for now. */
1183 case 2:
1184 if (uValue != 0)
1185 {
1186 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1187 return VERR_CPUM_RAISE_GP_0;
1188 }
1189 break;
1190 case 3:
1191 if (uValue != 0)
1192 {
1193 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1194 return VERR_CPUM_RAISE_GP_0;
1195 }
1196 break;
1197 }
1198 return VINF_SUCCESS;
1199}
1200
1201
1202/** @callback_method_impl{FNCPUMRDMSR} */
1203static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1204{
1205 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1206 /** @todo Implement machine check exception injection. */
1207 *puValue = 0;
1208 return VINF_SUCCESS;
1209}
1210
1211
1212/** @callback_method_impl{FNCPUMWRMSR} */
1213static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1214{
1215 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1216 /** @todo Implement machine check exception injection. */
1217 return VINF_SUCCESS;
1218}
1219
1220
1221/** @callback_method_impl{FNCPUMRDMSR} */
1222static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1223{
1224 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1225 /** @todo implement IA32_DS_AREA. */
1226 *puValue = 0;
1227 return VINF_SUCCESS;
1228}
1229
1230
1231/** @callback_method_impl{FNCPUMWRMSR} */
1232static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1233{
1234 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1235 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1236 return VINF_SUCCESS;
1237}
1238
1239
1240/** @callback_method_impl{FNCPUMRDMSR} */
1241static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1242{
1243 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1244 /** @todo implement TSC deadline timer. */
1245 *puValue = 0;
1246 return VINF_SUCCESS;
1247}
1248
1249
1250/** @callback_method_impl{FNCPUMWRMSR} */
1251static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1252{
1253 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1254 /** @todo implement TSC deadline timer. */
1255 return VINF_SUCCESS;
1256}
1257
1258
1259/** @callback_method_impl{FNCPUMRDMSR} */
1260static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1261{
1262 RT_NOREF_PV(pRange);
1263#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1264 if ( CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest)
1265 && CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
1266 {
1267 VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMsr(pVCpu, idMsr, puValue, false /* fWrite */);
1268 if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
1269 return VINF_SUCCESS;
1270 if (rcStrict == VERR_OUT_OF_RANGE)
1271 return VERR_CPUM_RAISE_GP_0;
1272 Assert(rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
1273 }
1274#endif
1275 return APICReadMsr(pVCpu, idMsr, puValue);
1276}
1277
1278
1279/** @callback_method_impl{FNCPUMWRMSR} */
1280static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1281{
1282 RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1283#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1284 if ( CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest)
1285 && CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
1286 {
1287 VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMsr(pVCpu, idMsr, &uValue, true /* fWrite */);
1288 if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
1289 return VINF_SUCCESS;
1290 if (rcStrict == VERR_OUT_OF_RANGE)
1291 return VERR_CPUM_RAISE_GP_0;
1292 Assert(rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
1293 }
1294#endif
1295 return APICWriteMsr(pVCpu, idMsr, uValue);
1296}
1297
1298
1299/** @callback_method_impl{FNCPUMRDMSR} */
1300static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1301{
1302 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1303 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1304 *puValue = 0;
1305 return VINF_SUCCESS;
1306}
1307
1308
1309/** @callback_method_impl{FNCPUMWRMSR} */
1310static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1311{
1312 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1313 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1314 return VINF_SUCCESS;
1315}
1316
1317
1318/** @callback_method_impl{FNCPUMRDMSR} */
1319static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBasic(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1320{
1321 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1322 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic;
1323 return VINF_SUCCESS;
1324}
1325
1326
1327/** @callback_method_impl{FNCPUMRDMSR} */
1328static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1329{
1330 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1331 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.PinCtls.u;
1332 return VINF_SUCCESS;
1333}
1334
1335/** @callback_method_impl{FNCPUMRDMSR} */
1336static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1337{
1338 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1339 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls.u;
1340 return VINF_SUCCESS;
1341}
1342
1343
1344/** @callback_method_impl{FNCPUMRDMSR} */
1345static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1346{
1347 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1348 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ExitCtls.u;
1349 return VINF_SUCCESS;
1350}
1351
1352
1353/** @callback_method_impl{FNCPUMRDMSR} */
1354static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1355{
1356 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1357 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.EntryCtls.u;
1358 return VINF_SUCCESS;
1359}
1360
1361
1362
1363/** @callback_method_impl{FNCPUMRDMSR} */
1364static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1365{
1366 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1367 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Misc;
1368 return VINF_SUCCESS;
1369}
1370
1371
1372/** @callback_method_impl{FNCPUMRDMSR} */
1373static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1374{
1375 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1376 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1377 return VINF_SUCCESS;
1378}
1379
1380
1381/** @callback_method_impl{FNCPUMRDMSR} */
1382static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1383{
1384 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1385 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1386 return VINF_SUCCESS;
1387}
1388
1389
1390/** @callback_method_impl{FNCPUMRDMSR} */
1391static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1392{
1393 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1394 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1395 return VINF_SUCCESS;
1396}
1397
1398
1399/** @callback_method_impl{FNCPUMRDMSR} */
1400static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1401{
1402 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1403 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1404 return VINF_SUCCESS;
1405}
1406
1407
1408/** @callback_method_impl{FNCPUMRDMSR} */
1409static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1410{
1411 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1412 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmcsEnum;
1413 return VINF_SUCCESS;
1414}
1415
1416
1417/** @callback_method_impl{FNCPUMRDMSR} */
1418static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1419{
1420 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1421 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls2.u;
1422 return VINF_SUCCESS;
1423}
1424
1425
1426/** @callback_method_impl{FNCPUMRDMSR} */
1427static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1428{
1429 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1430 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64EptVpidCaps;
1431 return VINF_SUCCESS;
1432}
1433
1434
1435/** @callback_method_impl{FNCPUMRDMSR} */
1436static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1437{
1438 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1439 *puValue = 0;
1440 return VINF_SUCCESS;
1441}
1442
1443
1444/** @callback_method_impl{FNCPUMRDMSR} */
1445static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1446{
1447 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1448 *puValue = 0;
1449 return VINF_SUCCESS;
1450}
1451
1452
1453/** @callback_method_impl{FNCPUMRDMSR} */
1454static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1455{
1456 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1457 *puValue = 0;
1458 return VINF_SUCCESS;
1459}
1460
1461
1462/** @callback_method_impl{FNCPUMRDMSR} */
1463static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1464{
1465 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1466 *puValue = 0;
1467 return VINF_SUCCESS;
1468}
1469
1470
1471/** @callback_method_impl{FNCPUMRDMSR} */
1472static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1473{
1474 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1475 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
1476 return VINF_SUCCESS;
1477}
1478
1479
1480/** @callback_method_impl{FNCPUMRDMSR} */
1481static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SpecCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1482{
1483 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1484 *puValue = pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
1485 return VINF_SUCCESS;
1486}
1487
1488
1489/** @callback_method_impl{FNCPUMWRMSR} */
1490static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SpecCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1491{
1492 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1493
1494 /* NB: The STIBP bit can be set even when IBRS is present, regardless of whether STIBP is actually implemented. */
1495 if (uValue & ~(MSR_IA32_SPEC_CTRL_F_IBRS | MSR_IA32_SPEC_CTRL_F_STIBP))
1496 {
1497 Log(("CPUM: Invalid IA32_SPEC_CTRL bits (trying to write %#llx)\n", uValue));
1498 return VERR_CPUM_RAISE_GP_0;
1499 }
1500
1501 pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
1502 return VINF_SUCCESS;
1503}
1504
1505
1506/** @callback_method_impl{FNCPUMWRMSR} */
1507static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PredCmd(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1508{
1509 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1510 return VINF_SUCCESS;
1511}
1512
1513
1514/** @callback_method_impl{FNCPUMRDMSR} */
1515static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ArchCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1516{
1517 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1518 *puValue = pVCpu->cpum.s.GuestMsrs.msr.ArchCaps;
1519 return VINF_SUCCESS;
1520}
1521
1522
1523/** @callback_method_impl{FNCPUMWRMSR} */
1524static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FlushCmd(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1525{
1526 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1527 if ((uValue & ~MSR_IA32_FLUSH_CMD_F_L1D) == 0)
1528 return VINF_SUCCESS;
1529 Log(("CPUM: Invalid MSR_IA32_FLUSH_CMD_ bits (trying to write %#llx)\n", uValue));
1530 return VERR_CPUM_RAISE_GP_0;
1531}
1532
1533
1534
1535/*
1536 * AMD64
1537 * AMD64
1538 * AMD64
1539 */
1540
1541
1542/** @callback_method_impl{FNCPUMRDMSR} */
1543static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1544{
1545 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1546 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1547 return VINF_SUCCESS;
1548}
1549
1550
1551/** @callback_method_impl{FNCPUMWRMSR} */
1552static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1553{
1554 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1555 uint64_t uValidatedEfer;
1556 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1557 int rc = CPUMIsGuestEferMsrWriteValid(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.Guest.cr0, uOldEfer, uValue, &uValidatedEfer);
1558 if (RT_FAILURE(rc))
1559 return VERR_CPUM_RAISE_GP_0;
1560
1561 CPUMSetGuestEferMsrNoChecks(pVCpu, uOldEfer, uValidatedEfer);
1562 return VINF_SUCCESS;
1563}
1564
1565
1566/** @callback_method_impl{FNCPUMRDMSR} */
1567static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1568{
1569 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1570 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1571 return VINF_SUCCESS;
1572}
1573
1574
1575/** @callback_method_impl{FNCPUMWRMSR} */
1576static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1577{
1578 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1579 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1580 return VINF_SUCCESS;
1581}
1582
1583
1584/** @callback_method_impl{FNCPUMRDMSR} */
1585static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1586{
1587 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1588 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1589 return VINF_SUCCESS;
1590}
1591
1592
1593/** @callback_method_impl{FNCPUMWRMSR} */
1594static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1595{
1596 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1597 if (!X86_IS_CANONICAL(uValue))
1598 {
1599 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1600 return VERR_CPUM_RAISE_GP_0;
1601 }
1602 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1603 return VINF_SUCCESS;
1604}
1605
1606
1607/** @callback_method_impl{FNCPUMRDMSR} */
1608static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1609{
1610 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1611 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1612 return VINF_SUCCESS;
1613}
1614
1615
1616/** @callback_method_impl{FNCPUMWRMSR} */
1617static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1618{
1619 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1620 if (!X86_IS_CANONICAL(uValue))
1621 {
1622 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1623 return VERR_CPUM_RAISE_GP_0;
1624 }
1625 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1626 return VINF_SUCCESS;
1627}
1628
1629
1630/** @callback_method_impl{FNCPUMRDMSR} */
1631static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1632{
1633 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1634 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1635 return VINF_SUCCESS;
1636}
1637
1638
1639/** @callback_method_impl{FNCPUMWRMSR} */
1640static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1641{
1642 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1643 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1644 return VINF_SUCCESS;
1645}
1646
1647
1648/** @callback_method_impl{FNCPUMRDMSR} */
1649static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1650{
1651 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1652 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1653 return VINF_SUCCESS;
1654}
1655
1656
1657/** @callback_method_impl{FNCPUMWRMSR} */
1658static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1659{
1660 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1661 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1662 return VINF_SUCCESS;
1663}
1664
1665
1666/** @callback_method_impl{FNCPUMRDMSR} */
1667static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1668{
1669 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1670 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1671 return VINF_SUCCESS;
1672}
1673
1674/** @callback_method_impl{FNCPUMWRMSR} */
1675static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1676{
1677 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1678 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1679 return VINF_SUCCESS;
1680}
1681
1682
1683
1684/** @callback_method_impl{FNCPUMRDMSR} */
1685static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1686{
1687 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1688 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1689 return VINF_SUCCESS;
1690}
1691
1692/** @callback_method_impl{FNCPUMWRMSR} */
1693static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1694{
1695 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1696 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1697 return VINF_SUCCESS;
1698}
1699
1700
1701/** @callback_method_impl{FNCPUMRDMSR} */
1702static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1703{
1704 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1705 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1706 return VINF_SUCCESS;
1707}
1708
1709/** @callback_method_impl{FNCPUMWRMSR} */
1710static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1711{
1712 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1713 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1714 return VINF_SUCCESS;
1715}
1716
1717
1718/*
1719 * Intel specific
1720 * Intel specific
1721 * Intel specific
1722 */
1723
1724/** @callback_method_impl{FNCPUMRDMSR} */
1725static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1726{
1727 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1728 /** @todo recalc clock frequency ratio? */
1729 *puValue = pRange->uValue;
1730 return VINF_SUCCESS;
1731}
1732
1733
1734/** @callback_method_impl{FNCPUMWRMSR} */
1735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1736{
1737 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1738 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1739 return VINF_SUCCESS;
1740}
1741
1742
1743/** @callback_method_impl{FNCPUMRDMSR} */
1744static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1745{
1746 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1747
1748 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1749 have a 4-bit core count. */
1750 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1751 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1752 *puValue = RT_MAKE_U32(cThreads, cCores);
1753 return VINF_SUCCESS;
1754}
1755
1756
1757/** @callback_method_impl{FNCPUMRDMSR} */
1758static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1759{
1760 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1761 /** @todo P4 hard power on config */
1762 *puValue = pRange->uValue;
1763 return VINF_SUCCESS;
1764}
1765
1766
1767/** @callback_method_impl{FNCPUMWRMSR} */
1768static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1769{
1770 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1771 /** @todo P4 hard power on config */
1772 return VINF_SUCCESS;
1773}
1774
1775
1776/** @callback_method_impl{FNCPUMRDMSR} */
1777static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1778{
1779 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1780 /** @todo P4 soft power on config */
1781 *puValue = pRange->uValue;
1782 return VINF_SUCCESS;
1783}
1784
1785
1786/** @callback_method_impl{FNCPUMWRMSR} */
1787static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1788{
1789 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1790 /** @todo P4 soft power on config */
1791 return VINF_SUCCESS;
1792}
1793
1794
1795/** @callback_method_impl{FNCPUMRDMSR} */
1796static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1797{
1798 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1799
1800 uint64_t uValue;
1801 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1802 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1803 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1804 {
1805 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1806 {
1807 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1808 uValue = 0;
1809 }
1810 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1811 {
1812 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1813 uValue = 1;
1814 }
1815 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1816 {
1817 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1818 uValue = 3;
1819 }
1820 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1821 {
1822 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1823 uValue = 2;
1824 }
1825 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1826 {
1827 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1828 uValue = 0;
1829 }
1830 else
1831 {
1832 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1833 uValue = 6;
1834 }
1835 uValue <<= 16;
1836
1837 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1838 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1839 uValue |= (uint32_t)uTscRatio << 24;
1840
1841 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1842 }
1843 else
1844 {
1845 /* Probably more stuff here, but intel doesn't want to tell us. */
1846 uValue = pRange->uValue;
1847 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1848 }
1849
1850 *puValue = uValue;
1851 return VINF_SUCCESS;
1852}
1853
1854
1855/** @callback_method_impl{FNCPUMWRMSR} */
1856static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1857{
1858 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1859 /** @todo P4 bus frequency config */
1860 return VINF_SUCCESS;
1861}
1862
1863
1864/** @callback_method_impl{FNCPUMRDMSR} */
1865static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1866{
1867 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1868
1869 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1870 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1871 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1872 *puValue = 5;
1873 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1874 *puValue = 1;
1875 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1876 *puValue = 3;
1877 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1878 *puValue = 2;
1879 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1880 *puValue = 0;
1881 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1882 *puValue = 4;
1883 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1884 *puValue = 6;
1885
1886 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1887
1888 return VINF_SUCCESS;
1889}
1890
1891
1892/** @callback_method_impl{FNCPUMRDMSR} */
1893static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1894{
1895 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1896
1897 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1898 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1899 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1900 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1901 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1902 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1903 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1904
1905 /* Ivy bridge has a minimum operating ratio as well. */
1906 if (true) /** @todo detect sandy bridge. */
1907 uValue |= (uint64_t)uTscRatio << 48;
1908
1909 *puValue = uValue;
1910 return VINF_SUCCESS;
1911}
1912
1913
1914/** @callback_method_impl{FNCPUMRDMSR} */
1915static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1916{
1917 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1918
1919 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1920
1921 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1922 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1923 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1924 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1925 uValue |= (uint32_t)uTscRatio << 8;
1926
1927 *puValue = uValue;
1928 return VINF_SUCCESS;
1929}
1930
1931
1932/** @callback_method_impl{FNCPUMWRMSR} */
1933static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1934{
1935 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1936 /** @todo implement writing MSR_FLEX_RATIO. */
1937 return VINF_SUCCESS;
1938}
1939
1940
1941/** @callback_method_impl{FNCPUMRDMSR} */
1942static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1943{
1944 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1945 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1946 return VINF_SUCCESS;
1947}
1948
1949
1950/** @callback_method_impl{FNCPUMWRMSR} */
1951static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1952{
1953 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1954
1955 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1956 {
1957 Log(("CPUM: WRMSR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1958 return VERR_CPUM_RAISE_GP_0;
1959 }
1960#if 0 /** @todo check what real (old) hardware does. */
1961 if ((uValue & 7) >= 5)
1962 {
1963 Log(("CPUM: WRMSR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1964 return VERR_CPUM_RAISE_GP_0;
1965 }
1966#endif
1967 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1968 return VINF_SUCCESS;
1969}
1970
1971
1972/** @callback_method_impl{FNCPUMRDMSR} */
1973static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1974{
1975 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1976 /** @todo implement I/O mwait wakeup. */
1977 *puValue = 0;
1978 return VINF_SUCCESS;
1979}
1980
1981
1982/** @callback_method_impl{FNCPUMWRMSR} */
1983static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1984{
1985 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1986 /** @todo implement I/O mwait wakeup. */
1987 return VINF_SUCCESS;
1988}
1989
1990
1991/** @callback_method_impl{FNCPUMRDMSR} */
1992static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1993{
1994 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1995 /** @todo implement last branch records. */
1996 *puValue = 0;
1997 return VINF_SUCCESS;
1998}
1999
2000
2001/** @callback_method_impl{FNCPUMWRMSR} */
2002static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2003{
2004 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2005 /** @todo implement last branch records. */
2006 return VINF_SUCCESS;
2007}
2008
2009
2010/** @callback_method_impl{FNCPUMRDMSR} */
2011static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2012{
2013 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2014 /** @todo implement last branch records. */
2015 *puValue = 0;
2016 return VINF_SUCCESS;
2017}
2018
2019
2020/** @callback_method_impl{FNCPUMWRMSR} */
2021static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2022{
2023 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
2024 /** @todo implement last branch records. */
2025 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2026 * if the rest of the bits are zero. Automatic sign extending?
2027 * Investigate! */
2028 if (!X86_IS_CANONICAL(uValue))
2029 {
2030 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2031 return VERR_CPUM_RAISE_GP_0;
2032 }
2033 return VINF_SUCCESS;
2034}
2035
2036
2037/** @callback_method_impl{FNCPUMRDMSR} */
2038static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2039{
2040 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2041 /** @todo implement last branch records. */
2042 *puValue = 0;
2043 return VINF_SUCCESS;
2044}
2045
2046
2047/** @callback_method_impl{FNCPUMWRMSR} */
2048static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2049{
2050 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2051 /** @todo implement last branch records. */
2052 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2053 * if the rest of the bits are zero. Automatic sign extending?
2054 * Investigate! */
2055 if (!X86_IS_CANONICAL(uValue))
2056 {
2057 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2058 return VERR_CPUM_RAISE_GP_0;
2059 }
2060 return VINF_SUCCESS;
2061}
2062
2063
2064/** @callback_method_impl{FNCPUMRDMSR} */
2065static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2066{
2067 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2068 /** @todo implement last branch records. */
2069 *puValue = 0;
2070 return VINF_SUCCESS;
2071}
2072
2073
2074/** @callback_method_impl{FNCPUMWRMSR} */
2075static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2076{
2077 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2078 /** @todo implement last branch records. */
2079 return VINF_SUCCESS;
2080}
2081
2082
2083/** @callback_method_impl{FNCPUMRDMSR} */
2084static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2085{
2086 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2087 *puValue = pRange->uValue;
2088 return VINF_SUCCESS;
2089}
2090
2091
2092/** @callback_method_impl{FNCPUMWRMSR} */
2093static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2094{
2095 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2096 return VINF_SUCCESS;
2097}
2098
2099
2100/** @callback_method_impl{FNCPUMRDMSR} */
2101static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2102{
2103 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2104 *puValue = pRange->uValue;
2105 return VINF_SUCCESS;
2106}
2107
2108
2109/** @callback_method_impl{FNCPUMWRMSR} */
2110static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2111{
2112 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2113 return VINF_SUCCESS;
2114}
2115
2116
2117/** @callback_method_impl{FNCPUMRDMSR} */
2118static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2119{
2120 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2121 *puValue = pRange->uValue;
2122 return VINF_SUCCESS;
2123}
2124
2125
2126/** @callback_method_impl{FNCPUMWRMSR} */
2127static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2128{
2129 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2130 return VINF_SUCCESS;
2131}
2132
2133
2134/** @callback_method_impl{FNCPUMRDMSR} */
2135static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2136{
2137 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2138 /** @todo machine check. */
2139 *puValue = pRange->uValue;
2140 return VINF_SUCCESS;
2141}
2142
2143
2144/** @callback_method_impl{FNCPUMWRMSR} */
2145static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2146{
2147 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2148 /** @todo machine check. */
2149 return VINF_SUCCESS;
2150}
2151
2152
2153/** @callback_method_impl{FNCPUMRDMSR} */
2154static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2155{
2156 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2157 *puValue = 0;
2158 return VINF_SUCCESS;
2159}
2160
2161
2162/** @callback_method_impl{FNCPUMWRMSR} */
2163static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2164{
2165 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2166 return VINF_SUCCESS;
2167}
2168
2169
2170/** @callback_method_impl{FNCPUMRDMSR} */
2171static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2172{
2173 RT_NOREF_PV(idMsr);
2174 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
2175 AssertRC(rc);
2176 return VINF_SUCCESS;
2177}
2178
2179
2180/** @callback_method_impl{FNCPUMWRMSR} */
2181static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2182{
2183 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2184 /* This CRx interface differs from the MOV CRx, GReg interface in that
2185 #GP(0) isn't raised if unsupported bits are written to. Instead they
2186 are simply ignored and masked off. (Pentium M Dothan) */
2187 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
2188 * any, gain. */
2189 return VINF_SUCCESS;
2190}
2191
2192
2193/** @callback_method_impl{FNCPUMRDMSR} */
2194static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2195{
2196 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2197 /** @todo implement CPUID masking. */
2198 *puValue = UINT64_MAX;
2199 return VINF_SUCCESS;
2200}
2201
2202
2203/** @callback_method_impl{FNCPUMWRMSR} */
2204static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2205{
2206 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2207 /** @todo implement CPUID masking. */
2208 return VINF_SUCCESS;
2209}
2210
2211
2212/** @callback_method_impl{FNCPUMRDMSR} */
2213static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2214{
2215 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2216 /** @todo implement CPUID masking. */
2217 *puValue = 0;
2218 return VINF_SUCCESS;
2219}
2220
2221
2222/** @callback_method_impl{FNCPUMWRMSR} */
2223static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2224{
2225 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2226 /** @todo implement CPUID masking. */
2227 return VINF_SUCCESS;
2228}
2229
2230
2231
2232/** @callback_method_impl{FNCPUMRDMSR} */
2233static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2234{
2235 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2236 /** @todo implement CPUID masking. */
2237 *puValue = UINT64_MAX;
2238 return VINF_SUCCESS;
2239}
2240
2241
2242/** @callback_method_impl{FNCPUMWRMSR} */
2243static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2244{
2245 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2246 /** @todo implement CPUID masking. */
2247 return VINF_SUCCESS;
2248}
2249
2250
2251
2252/** @callback_method_impl{FNCPUMRDMSR} */
2253static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2254{
2255 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2256 /** @todo implement AES-NI. */
2257 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2258 return VINF_SUCCESS;
2259}
2260
2261
2262/** @callback_method_impl{FNCPUMWRMSR} */
2263static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2264{
2265 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2266 /** @todo implement AES-NI. */
2267 return VERR_CPUM_RAISE_GP_0;
2268}
2269
2270
2271/** @callback_method_impl{FNCPUMRDMSR} */
2272static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2273{
2274 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2275 /** @todo implement intel C states. */
2276 *puValue = pRange->uValue;
2277 return VINF_SUCCESS;
2278}
2279
2280
2281/** @callback_method_impl{FNCPUMWRMSR} */
2282static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2283{
2284 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2285 /** @todo implement intel C states. */
2286 return VINF_SUCCESS;
2287}
2288
2289
2290/** @callback_method_impl{FNCPUMRDMSR} */
2291static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2292{
2293 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2294 /** @todo implement last-branch-records. */
2295 *puValue = 0;
2296 return VINF_SUCCESS;
2297}
2298
2299
2300/** @callback_method_impl{FNCPUMWRMSR} */
2301static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2302{
2303 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2304 /** @todo implement last-branch-records. */
2305 return VINF_SUCCESS;
2306}
2307
2308
2309/** @callback_method_impl{FNCPUMRDMSR} */
2310static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2311{
2312 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2313 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2314 *puValue = 0;
2315 return VINF_SUCCESS;
2316}
2317
2318
2319/** @callback_method_impl{FNCPUMWRMSR} */
2320static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2321{
2322 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2323 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2324 return VINF_SUCCESS;
2325}
2326
2327
2328/** @callback_method_impl{FNCPUMRDMSR} */
2329static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2330{
2331 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2332 /** @todo implement memory VLW? */
2333 *puValue = pRange->uValue;
2334 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2335 AAJ49/AAK51/????, which documents the inversion of this bit. The
2336 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2337 that correct things. Some guesses at the other bits:
2338 bit 2 = INTR
2339 bit 4 = SMI
2340 bit 5 = INIT
2341 bit 6 = NMI */
2342 return VINF_SUCCESS;
2343}
2344
2345
2346/** @callback_method_impl{FNCPUMRDMSR} */
2347static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2348{
2349 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2350 /** @todo intel power management */
2351 *puValue = 0;
2352 return VINF_SUCCESS;
2353}
2354
2355
2356/** @callback_method_impl{FNCPUMWRMSR} */
2357static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2358{
2359 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2360 /** @todo intel power management */
2361 return VINF_SUCCESS;
2362}
2363
2364
2365/** @callback_method_impl{FNCPUMRDMSR} */
2366static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2367{
2368 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2369 /** @todo intel performance counters. */
2370 *puValue = 0;
2371 return VINF_SUCCESS;
2372}
2373
2374
2375/** @callback_method_impl{FNCPUMWRMSR} */
2376static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2377{
2378 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2379 /** @todo intel performance counters. */
2380 return VINF_SUCCESS;
2381}
2382
2383
2384/** @callback_method_impl{FNCPUMRDMSR} */
2385static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2386{
2387 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2388 /** @todo intel performance counters. */
2389 *puValue = 0;
2390 return VINF_SUCCESS;
2391}
2392
2393
2394/** @callback_method_impl{FNCPUMWRMSR} */
2395static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2396{
2397 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2398 /** @todo intel performance counters. */
2399 return VINF_SUCCESS;
2400}
2401
2402
2403/** @callback_method_impl{FNCPUMRDMSR} */
2404static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2405{
2406 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2407 /** @todo intel power management. */
2408 *puValue = 0;
2409 return VINF_SUCCESS;
2410}
2411
2412
2413/** @callback_method_impl{FNCPUMRDMSR} */
2414static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2415{
2416 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2417 /** @todo intel power management. */
2418 *puValue = 0;
2419 return VINF_SUCCESS;
2420}
2421
2422
2423/** @callback_method_impl{FNCPUMRDMSR} */
2424static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2425{
2426 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2427 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2428 *puValue = 0;
2429 return VINF_SUCCESS;
2430}
2431
2432
2433/** @callback_method_impl{FNCPUMWRMSR} */
2434static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2435{
2436 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2437 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2438 return VINF_SUCCESS;
2439}
2440
2441
2442/** @callback_method_impl{FNCPUMRDMSR} */
2443static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2444{
2445 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2446 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2447 *puValue = 0;
2448 return VINF_SUCCESS;
2449}
2450
2451
2452/** @callback_method_impl{FNCPUMWRMSR} */
2453static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2454{
2455 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2456 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2457 return VINF_SUCCESS;
2458}
2459
2460
2461/** @callback_method_impl{FNCPUMRDMSR} */
2462static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2463{
2464 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2465 /** @todo intel RAPL. */
2466 *puValue = pRange->uValue;
2467 return VINF_SUCCESS;
2468}
2469
2470
2471/** @callback_method_impl{FNCPUMWRMSR} */
2472static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2473{
2474 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2475 /* Note! This is documented as read only and except for a Silvermont sample has
2476 always been classified as read only. This is just here to make it compile. */
2477 return VINF_SUCCESS;
2478}
2479
2480
2481/** @callback_method_impl{FNCPUMRDMSR} */
2482static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2483{
2484 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2485 /** @todo intel power management. */
2486 *puValue = 0;
2487 return VINF_SUCCESS;
2488}
2489
2490
2491/** @callback_method_impl{FNCPUMWRMSR} */
2492static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2493{
2494 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2495 /** @todo intel power management. */
2496 return VINF_SUCCESS;
2497}
2498
2499
2500/** @callback_method_impl{FNCPUMRDMSR} */
2501static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2502{
2503 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2504 /** @todo intel power management. */
2505 *puValue = 0;
2506 return VINF_SUCCESS;
2507}
2508
2509
2510/** @callback_method_impl{FNCPUMWRMSR} */
2511static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2512{
2513 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2514 /* Note! This is documented as read only and except for a Silvermont sample has
2515 always been classified as read only. This is just here to make it compile. */
2516 return VINF_SUCCESS;
2517}
2518
2519
2520/** @callback_method_impl{FNCPUMRDMSR} */
2521static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2522{
2523 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2524 /** @todo intel RAPL. */
2525 *puValue = 0;
2526 return VINF_SUCCESS;
2527}
2528
2529
2530/** @callback_method_impl{FNCPUMWRMSR} */
2531static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2532{
2533 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2534 /** @todo intel RAPL. */
2535 return VINF_SUCCESS;
2536}
2537
2538
2539/** @callback_method_impl{FNCPUMRDMSR} */
2540static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2541{
2542 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2543 /** @todo intel power management. */
2544 *puValue = 0;
2545 return VINF_SUCCESS;
2546}
2547
2548
2549/** @callback_method_impl{FNCPUMRDMSR} */
2550static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2551{
2552 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2553 /** @todo intel power management. */
2554 *puValue = 0;
2555 return VINF_SUCCESS;
2556}
2557
2558
2559/** @callback_method_impl{FNCPUMRDMSR} */
2560static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2561{
2562 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2563 /** @todo intel power management. */
2564 *puValue = 0;
2565 return VINF_SUCCESS;
2566}
2567
2568
2569/** @callback_method_impl{FNCPUMRDMSR} */
2570static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2571{
2572 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2573 /** @todo intel RAPL. */
2574 *puValue = 0;
2575 return VINF_SUCCESS;
2576}
2577
2578
2579/** @callback_method_impl{FNCPUMWRMSR} */
2580static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2581{
2582 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2583 /** @todo intel RAPL. */
2584 return VINF_SUCCESS;
2585}
2586
2587
2588/** @callback_method_impl{FNCPUMRDMSR} */
2589static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2590{
2591 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2592 /** @todo intel power management. */
2593 *puValue = 0;
2594 return VINF_SUCCESS;
2595}
2596
2597
2598/** @callback_method_impl{FNCPUMRDMSR} */
2599static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2600{
2601 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2602 /** @todo intel power management. */
2603 *puValue = 0;
2604 return VINF_SUCCESS;
2605}
2606
2607
2608/** @callback_method_impl{FNCPUMRDMSR} */
2609static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2610{
2611 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2612 /** @todo intel power management. */
2613 *puValue = 0;
2614 return VINF_SUCCESS;
2615}
2616
2617
2618/** @callback_method_impl{FNCPUMRDMSR} */
2619static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2620{
2621 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2622 /** @todo intel RAPL. */
2623 *puValue = 0;
2624 return VINF_SUCCESS;
2625}
2626
2627
2628/** @callback_method_impl{FNCPUMWRMSR} */
2629static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2630{
2631 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2632 /** @todo intel RAPL. */
2633 return VINF_SUCCESS;
2634}
2635
2636
2637/** @callback_method_impl{FNCPUMRDMSR} */
2638static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2639{
2640 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2641 /** @todo intel power management. */
2642 *puValue = 0;
2643 return VINF_SUCCESS;
2644}
2645
2646
2647/** @callback_method_impl{FNCPUMRDMSR} */
2648static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2649{
2650 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2651 /** @todo intel RAPL. */
2652 *puValue = 0;
2653 return VINF_SUCCESS;
2654}
2655
2656
2657/** @callback_method_impl{FNCPUMWRMSR} */
2658static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2659{
2660 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2661 /** @todo intel RAPL. */
2662 return VINF_SUCCESS;
2663}
2664
2665
2666/** @callback_method_impl{FNCPUMRDMSR} */
2667static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2668{
2669 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2670 /** @todo intel power management. */
2671 *puValue = 0;
2672 return VINF_SUCCESS;
2673}
2674
2675
2676/** @callback_method_impl{FNCPUMRDMSR} */
2677static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2678{
2679 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2680 /** @todo intel RAPL. */
2681 *puValue = 0;
2682 return VINF_SUCCESS;
2683}
2684
2685
2686/** @callback_method_impl{FNCPUMWRMSR} */
2687static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2688{
2689 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2690 /** @todo intel RAPL. */
2691 return VINF_SUCCESS;
2692}
2693
2694
2695/** @callback_method_impl{FNCPUMRDMSR} */
2696static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2697{
2698 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2699 /** @todo intel power management. */
2700 *puValue = 0;
2701 return VINF_SUCCESS;
2702}
2703
2704
2705/** @callback_method_impl{FNCPUMRDMSR} */
2706static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2707{
2708 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2709 /** @todo intel RAPL. */
2710 *puValue = 0;
2711 return VINF_SUCCESS;
2712}
2713
2714
2715/** @callback_method_impl{FNCPUMWRMSR} */
2716static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2717{
2718 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2719 /** @todo intel RAPL. */
2720 return VINF_SUCCESS;
2721}
2722
2723
2724/** @callback_method_impl{FNCPUMRDMSR} */
2725static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2726{
2727 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2728 /** @todo intel power management. */
2729 *puValue = pRange->uValue;
2730 return VINF_SUCCESS;
2731}
2732
2733
2734/** @callback_method_impl{FNCPUMRDMSR} */
2735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2736{
2737 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2738 /** @todo intel power management. */
2739 *puValue = pRange->uValue;
2740 return VINF_SUCCESS;
2741}
2742
2743
2744/** @callback_method_impl{FNCPUMRDMSR} */
2745static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2746{
2747 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2748 /** @todo intel power management. */
2749 *puValue = pRange->uValue;
2750 return VINF_SUCCESS;
2751}
2752
2753
2754/** @callback_method_impl{FNCPUMRDMSR} */
2755static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2756{
2757 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2758 /** @todo intel power management. */
2759 *puValue = 0;
2760 return VINF_SUCCESS;
2761}
2762
2763
2764/** @callback_method_impl{FNCPUMWRMSR} */
2765static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2766{
2767 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2768 /** @todo intel power management. */
2769 return VINF_SUCCESS;
2770}
2771
2772
2773/** @callback_method_impl{FNCPUMRDMSR} */
2774static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2775{
2776 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2777 /** @todo intel power management. */
2778 *puValue = 0;
2779 return VINF_SUCCESS;
2780}
2781
2782
2783/** @callback_method_impl{FNCPUMWRMSR} */
2784static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2785{
2786 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2787 /** @todo intel power management. */
2788 return VINF_SUCCESS;
2789}
2790
2791
2792/** @callback_method_impl{FNCPUMRDMSR} */
2793static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2794{
2795 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2796 /** @todo uncore msrs. */
2797 *puValue = 0;
2798 return VINF_SUCCESS;
2799}
2800
2801
2802/** @callback_method_impl{FNCPUMWRMSR} */
2803static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2804{
2805 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2806 /** @todo uncore msrs. */
2807 return VINF_SUCCESS;
2808}
2809
2810
2811/** @callback_method_impl{FNCPUMRDMSR} */
2812static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2813{
2814 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2815 /** @todo uncore msrs. */
2816 *puValue = 0;
2817 return VINF_SUCCESS;
2818}
2819
2820
2821/** @callback_method_impl{FNCPUMWRMSR} */
2822static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2823{
2824 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2825 /** @todo uncore msrs. */
2826 return VINF_SUCCESS;
2827}
2828
2829
2830/** @callback_method_impl{FNCPUMRDMSR} */
2831static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2832{
2833 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2834 /** @todo uncore msrs. */
2835 *puValue = 0;
2836 return VINF_SUCCESS;
2837}
2838
2839
2840/** @callback_method_impl{FNCPUMWRMSR} */
2841static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2842{
2843 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2844 /** @todo uncore msrs. */
2845 return VINF_SUCCESS;
2846}
2847
2848
2849/** @callback_method_impl{FNCPUMRDMSR} */
2850static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2851{
2852 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2853 /** @todo uncore msrs. */
2854 *puValue = 0;
2855 return VINF_SUCCESS;
2856}
2857
2858
2859/** @callback_method_impl{FNCPUMWRMSR} */
2860static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2861{
2862 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2863 /** @todo uncore msrs. */
2864 return VINF_SUCCESS;
2865}
2866
2867
2868/** @callback_method_impl{FNCPUMRDMSR} */
2869static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2870{
2871 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2872 /** @todo uncore msrs. */
2873 *puValue = 0;
2874 return VINF_SUCCESS;
2875}
2876
2877
2878/** @callback_method_impl{FNCPUMWRMSR} */
2879static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2880{
2881 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2882 /** @todo uncore msrs. */
2883 return VINF_SUCCESS;
2884}
2885
2886
2887/** @callback_method_impl{FNCPUMRDMSR} */
2888static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2889{
2890 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2891 /** @todo uncore msrs. */
2892 *puValue = 0;
2893 return VINF_SUCCESS;
2894}
2895
2896
2897/** @callback_method_impl{FNCPUMRDMSR} */
2898static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2899{
2900 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2901 /** @todo uncore msrs. */
2902 *puValue = 0;
2903 return VINF_SUCCESS;
2904}
2905
2906
2907/** @callback_method_impl{FNCPUMWRMSR} */
2908static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2909{
2910 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2911 /** @todo uncore msrs. */
2912 return VINF_SUCCESS;
2913}
2914
2915
2916/** @callback_method_impl{FNCPUMRDMSR} */
2917static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2918{
2919 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2920 /** @todo uncore msrs. */
2921 *puValue = 0;
2922 return VINF_SUCCESS;
2923}
2924
2925
2926/** @callback_method_impl{FNCPUMWRMSR} */
2927static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2928{
2929 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2930 /** @todo uncore msrs. */
2931 return VINF_SUCCESS;
2932}
2933
2934
2935/** @callback_method_impl{FNCPUMRDMSR} */
2936static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2937{
2938 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2939
2940 /*
2941 * 31:0 is SMI count (read only), 63:32 reserved.
2942 * Since we don't do SMI, the count is always zero.
2943 */
2944 *puValue = 0;
2945 return VINF_SUCCESS;
2946}
2947
2948
2949/** @callback_method_impl{FNCPUMRDMSR} */
2950static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2951{
2952 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2953 /** @todo implement enhanced multi thread termal monitoring? */
2954 *puValue = pRange->uValue;
2955 return VINF_SUCCESS;
2956}
2957
2958
2959/** @callback_method_impl{FNCPUMWRMSR} */
2960static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2961{
2962 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2963 /** @todo implement enhanced multi thread termal monitoring? */
2964 return VINF_SUCCESS;
2965}
2966
2967
2968/** @callback_method_impl{FNCPUMRDMSR} */
2969static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2970{
2971 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2972 /** @todo SMM & C-states? */
2973 *puValue = 0;
2974 return VINF_SUCCESS;
2975}
2976
2977
2978/** @callback_method_impl{FNCPUMWRMSR} */
2979static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2980{
2981 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2982 /** @todo SMM & C-states? */
2983 return VINF_SUCCESS;
2984}
2985
2986
2987/** @callback_method_impl{FNCPUMRDMSR} */
2988static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2989{
2990 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2991 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2992 *puValue = 0;
2993 return VINF_SUCCESS;
2994}
2995
2996
2997/** @callback_method_impl{FNCPUMWRMSR} */
2998static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2999{
3000 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3001 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
3002 return VINF_SUCCESS;
3003}
3004
3005
3006/** @callback_method_impl{FNCPUMRDMSR} */
3007static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3008{
3009 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3010 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3011 *puValue = 0;
3012 return VINF_SUCCESS;
3013}
3014
3015
3016/** @callback_method_impl{FNCPUMWRMSR} */
3017static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3018{
3019 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3020 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3021 return VINF_SUCCESS;
3022}
3023
3024
3025/** @callback_method_impl{FNCPUMRDMSR} */
3026static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3027{
3028 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3029 /** @todo Core2+ platform environment control interface control register? */
3030 *puValue = 0;
3031 return VINF_SUCCESS;
3032}
3033
3034
3035/** @callback_method_impl{FNCPUMWRMSR} */
3036static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3037{
3038 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3039 /** @todo Core2+ platform environment control interface control register? */
3040 return VINF_SUCCESS;
3041}
3042
3043
3044/** @callback_method_impl{FNCPUMRDMSR} */
3045static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3046{
3047 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3048 *puValue = 0;
3049 return VINF_SUCCESS;
3050}
3051
3052
3053/*
3054 * Multiple vendor P6 MSRs.
3055 * Multiple vendor P6 MSRs.
3056 * Multiple vendor P6 MSRs.
3057 *
3058 * These MSRs were introduced with the P6 but not elevated to architectural
3059 * MSRs, despite other vendors implementing them.
3060 */
3061
3062
3063/** @callback_method_impl{FNCPUMRDMSR} */
3064static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3065{
3066 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3067 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
3068 if I read the docs correctly, thus the need for separate functions. */
3069 /** @todo implement last branch records. */
3070 *puValue = 0;
3071 return VINF_SUCCESS;
3072}
3073
3074
3075/** @callback_method_impl{FNCPUMRDMSR} */
3076static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3077{
3078 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3079 /** @todo implement last branch records. */
3080 *puValue = 0;
3081 return VINF_SUCCESS;
3082}
3083
3084
3085/** @callback_method_impl{FNCPUMRDMSR} */
3086static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3087{
3088 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3089 /** @todo implement last exception records. */
3090 *puValue = 0;
3091 return VINF_SUCCESS;
3092}
3093
3094
3095/** @callback_method_impl{FNCPUMWRMSR} */
3096static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3097{
3098 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3099 /** @todo implement last exception records. */
3100 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
3101 a non-cannonical address. */
3102 return VINF_SUCCESS;
3103}
3104
3105
3106/** @callback_method_impl{FNCPUMRDMSR} */
3107static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3108{
3109 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3110 /** @todo implement last exception records. */
3111 *puValue = 0;
3112 return VINF_SUCCESS;
3113}
3114
3115
3116/** @callback_method_impl{FNCPUMWRMSR} */
3117static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3118{
3119 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3120 /** @todo implement last exception records. */
3121 return VINF_SUCCESS;
3122}
3123
3124
3125
3126/*
3127 * AMD specific
3128 * AMD specific
3129 * AMD specific
3130 */
3131
3132
3133/** @callback_method_impl{FNCPUMRDMSR} */
3134static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3135{
3136 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3137 /** @todo Implement TscRateMsr */
3138 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
3139 return VINF_SUCCESS;
3140}
3141
3142
3143/** @callback_method_impl{FNCPUMWRMSR} */
3144static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3145{
3146 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3147 /** @todo Implement TscRateMsr */
3148 return VINF_SUCCESS;
3149}
3150
3151
3152/** @callback_method_impl{FNCPUMRDMSR} */
3153static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3154{
3155 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3156 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3157 /* Note: Only listes in BKDG for Family 15H. */
3158 *puValue = 0;
3159 return VINF_SUCCESS;
3160}
3161
3162
3163/** @callback_method_impl{FNCPUMWRMSR} */
3164static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3165{
3166 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3167 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3168 return VINF_SUCCESS;
3169}
3170
3171
3172/** @callback_method_impl{FNCPUMRDMSR} */
3173static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3174{
3175 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3176 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3177 /* Note: Only listes in BKDG for Family 15H. */
3178 *puValue = 0;
3179 return VINF_SUCCESS;
3180}
3181
3182
3183/** @callback_method_impl{FNCPUMWRMSR} */
3184static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3185{
3186 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3187 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3188 return VINF_SUCCESS;
3189}
3190
3191
3192/** @callback_method_impl{FNCPUMRDMSR} */
3193static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3194{
3195 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3196 /** @todo machine check. */
3197 *puValue = 0;
3198 return VINF_SUCCESS;
3199}
3200
3201
3202/** @callback_method_impl{FNCPUMWRMSR} */
3203static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3204{
3205 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3206 /** @todo machine check. */
3207 return VINF_SUCCESS;
3208}
3209
3210
3211/** @callback_method_impl{FNCPUMRDMSR} */
3212static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3213{
3214 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3215 /** @todo AMD performance events. */
3216 *puValue = 0;
3217 return VINF_SUCCESS;
3218}
3219
3220
3221/** @callback_method_impl{FNCPUMWRMSR} */
3222static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3223{
3224 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3225 /** @todo AMD performance events. */
3226 return VINF_SUCCESS;
3227}
3228
3229
3230/** @callback_method_impl{FNCPUMRDMSR} */
3231static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3232{
3233 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3234 /** @todo AMD performance events. */
3235 *puValue = 0;
3236 return VINF_SUCCESS;
3237}
3238
3239
3240/** @callback_method_impl{FNCPUMWRMSR} */
3241static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3242{
3243 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3244 /** @todo AMD performance events. */
3245 return VINF_SUCCESS;
3246}
3247
3248
3249/** @callback_method_impl{FNCPUMRDMSR} */
3250static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3251{
3252 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3253 /** @todo AMD SYS_CFG */
3254 *puValue = pRange->uValue;
3255 return VINF_SUCCESS;
3256}
3257
3258
3259/** @callback_method_impl{FNCPUMWRMSR} */
3260static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3261{
3262 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3263 /** @todo AMD SYS_CFG */
3264 return VINF_SUCCESS;
3265}
3266
3267
3268/** @callback_method_impl{FNCPUMRDMSR} */
3269static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3270{
3271 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3272 /** @todo AMD HW_CFG */
3273 *puValue = 0;
3274 return VINF_SUCCESS;
3275}
3276
3277
3278/** @callback_method_impl{FNCPUMWRMSR} */
3279static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3280{
3281 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3282 /** @todo AMD HW_CFG */
3283 return VINF_SUCCESS;
3284}
3285
3286
3287/** @callback_method_impl{FNCPUMRDMSR} */
3288static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3289{
3290 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3291 /** @todo AMD IorrMask/IorrBase */
3292 *puValue = 0;
3293 return VINF_SUCCESS;
3294}
3295
3296
3297/** @callback_method_impl{FNCPUMWRMSR} */
3298static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3299{
3300 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3301 /** @todo AMD IorrMask/IorrBase */
3302 return VINF_SUCCESS;
3303}
3304
3305
3306/** @callback_method_impl{FNCPUMRDMSR} */
3307static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3308{
3309 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3310 /** @todo AMD IorrMask/IorrBase */
3311 *puValue = 0;
3312 return VINF_SUCCESS;
3313}
3314
3315
3316/** @callback_method_impl{FNCPUMWRMSR} */
3317static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3318{
3319 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3320 /** @todo AMD IorrMask/IorrBase */
3321 return VINF_SUCCESS;
3322}
3323
3324
3325/** @callback_method_impl{FNCPUMRDMSR} */
3326static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3327{
3328 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3329 *puValue = 0;
3330 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
3331 * for TOPMEM2. */
3332 //if (pRange->uValue == 0)
3333 // *puValue = _4G - RamHoleSize;
3334 return VINF_SUCCESS;
3335}
3336
3337
3338/** @callback_method_impl{FNCPUMWRMSR} */
3339static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3340{
3341 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3342 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
3343 return VINF_SUCCESS;
3344}
3345
3346
3347/** @callback_method_impl{FNCPUMRDMSR} */
3348static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3349{
3350 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3351 /** @todo AMD NB_CFG1 */
3352 *puValue = 0;
3353 return VINF_SUCCESS;
3354}
3355
3356
3357/** @callback_method_impl{FNCPUMWRMSR} */
3358static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3359{
3360 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3361 /** @todo AMD NB_CFG1 */
3362 return VINF_SUCCESS;
3363}
3364
3365
3366/** @callback_method_impl{FNCPUMRDMSR} */
3367static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3368{
3369 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3370 /** @todo machine check. */
3371 *puValue = 0;
3372 return VINF_SUCCESS;
3373}
3374
3375
3376/** @callback_method_impl{FNCPUMWRMSR} */
3377static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3378{
3379 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3380 /** @todo machine check. */
3381 return VINF_SUCCESS;
3382}
3383
3384
3385/** @callback_method_impl{FNCPUMRDMSR} */
3386static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3387{
3388 RT_NOREF_PV(idMsr);
3389 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
3390 if (pLeaf)
3391 {
3392 if (!(pRange->uValue & 1))
3393 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
3394 else
3395 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
3396 }
3397 else
3398 *puValue = 0;
3399 return VINF_SUCCESS;
3400}
3401
3402
3403/** @callback_method_impl{FNCPUMWRMSR} */
3404static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3405{
3406 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3407 /** @todo Remember guest programmed CPU name. */
3408 return VINF_SUCCESS;
3409}
3410
3411
3412/** @callback_method_impl{FNCPUMRDMSR} */
3413static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3414{
3415 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3416 /** @todo AMD HTC. */
3417 *puValue = pRange->uValue;
3418 return VINF_SUCCESS;
3419}
3420
3421
3422/** @callback_method_impl{FNCPUMWRMSR} */
3423static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3424{
3425 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3426 /** @todo AMD HTC. */
3427 return VINF_SUCCESS;
3428}
3429
3430
3431/** @callback_method_impl{FNCPUMRDMSR} */
3432static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3433{
3434 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3435 /** @todo AMD STC. */
3436 *puValue = 0;
3437 return VINF_SUCCESS;
3438}
3439
3440
3441/** @callback_method_impl{FNCPUMWRMSR} */
3442static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3443{
3444 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3445 /** @todo AMD STC. */
3446 return VINF_SUCCESS;
3447}
3448
3449
3450/** @callback_method_impl{FNCPUMRDMSR} */
3451static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3452{
3453 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3454 /** @todo AMD FIDVID_CTL. */
3455 *puValue = pRange->uValue;
3456 return VINF_SUCCESS;
3457}
3458
3459
3460/** @callback_method_impl{FNCPUMWRMSR} */
3461static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3462{
3463 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3464 /** @todo AMD FIDVID_CTL. */
3465 return VINF_SUCCESS;
3466}
3467
3468
3469/** @callback_method_impl{FNCPUMRDMSR} */
3470static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3471{
3472 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3473 /** @todo AMD FIDVID_STATUS. */
3474 *puValue = pRange->uValue;
3475 return VINF_SUCCESS;
3476}
3477
3478
3479/** @callback_method_impl{FNCPUMRDMSR} */
3480static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3481{
3482 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3483 /** @todo AMD MC. */
3484 *puValue = 0;
3485 return VINF_SUCCESS;
3486}
3487
3488
3489/** @callback_method_impl{FNCPUMWRMSR} */
3490static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3491{
3492 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3493 /** @todo AMD MC. */
3494 return VINF_SUCCESS;
3495}
3496
3497
3498/** @callback_method_impl{FNCPUMRDMSR} */
3499static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3500{
3501 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3502 /** @todo AMD SMM/SMI and I/O trap. */
3503 *puValue = 0;
3504 return VINF_SUCCESS;
3505}
3506
3507
3508/** @callback_method_impl{FNCPUMWRMSR} */
3509static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3510{
3511 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3512 /** @todo AMD SMM/SMI and I/O trap. */
3513 return VINF_SUCCESS;
3514}
3515
3516
3517/** @callback_method_impl{FNCPUMRDMSR} */
3518static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3519{
3520 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3521 /** @todo AMD SMM/SMI and I/O trap. */
3522 *puValue = 0;
3523 return VINF_SUCCESS;
3524}
3525
3526
3527/** @callback_method_impl{FNCPUMWRMSR} */
3528static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3529{
3530 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3531 /** @todo AMD SMM/SMI and I/O trap. */
3532 return VINF_SUCCESS;
3533}
3534
3535
3536/** @callback_method_impl{FNCPUMRDMSR} */
3537static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3538{
3539 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3540 /** @todo Interrupt pending message. */
3541 *puValue = 0;
3542 return VINF_SUCCESS;
3543}
3544
3545
3546/** @callback_method_impl{FNCPUMWRMSR} */
3547static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3548{
3549 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3550 /** @todo Interrupt pending message. */
3551 return VINF_SUCCESS;
3552}
3553
3554
3555/** @callback_method_impl{FNCPUMRDMSR} */
3556static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3557{
3558 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3559 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3560 *puValue = 0;
3561 return VINF_SUCCESS;
3562}
3563
3564
3565/** @callback_method_impl{FNCPUMWRMSR} */
3566static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3567{
3568 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3569 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3570 return VINF_SUCCESS;
3571}
3572
3573
3574/** @callback_method_impl{FNCPUMRDMSR} */
3575static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3576{
3577 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3578 /** @todo AMD MMIO Configuration base address. */
3579 *puValue = 0;
3580 return VINF_SUCCESS;
3581}
3582
3583
3584/** @callback_method_impl{FNCPUMWRMSR} */
3585static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3586{
3587 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3588 /** @todo AMD MMIO Configuration base address. */
3589 return VINF_SUCCESS;
3590}
3591
3592
3593/** @callback_method_impl{FNCPUMRDMSR} */
3594static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3595{
3596 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3597 /** @todo AMD 0xc0010059. */
3598 *puValue = 0;
3599 return VINF_SUCCESS;
3600}
3601
3602
3603/** @callback_method_impl{FNCPUMWRMSR} */
3604static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3605{
3606 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3607 /** @todo AMD 0xc0010059. */
3608 return VINF_SUCCESS;
3609}
3610
3611
3612/** @callback_method_impl{FNCPUMRDMSR} */
3613static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3614{
3615 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3616 /** @todo AMD P-states. */
3617 *puValue = pRange->uValue;
3618 return VINF_SUCCESS;
3619}
3620
3621
3622/** @callback_method_impl{FNCPUMRDMSR} */
3623static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3624{
3625 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3626 /** @todo AMD P-states. */
3627 *puValue = pRange->uValue;
3628 return VINF_SUCCESS;
3629}
3630
3631
3632/** @callback_method_impl{FNCPUMWRMSR} */
3633static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3634{
3635 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3636 /** @todo AMD P-states. */
3637 return VINF_SUCCESS;
3638}
3639
3640
3641/** @callback_method_impl{FNCPUMRDMSR} */
3642static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3643{
3644 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3645 /** @todo AMD P-states. */
3646 *puValue = pRange->uValue;
3647 return VINF_SUCCESS;
3648}
3649
3650
3651/** @callback_method_impl{FNCPUMWRMSR} */
3652static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3653{
3654 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3655 /** @todo AMD P-states. */
3656 return VINF_SUCCESS;
3657}
3658
3659
3660/** @callback_method_impl{FNCPUMRDMSR} */
3661static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3662{
3663 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3664 /** @todo AMD P-states. */
3665 *puValue = pRange->uValue;
3666 return VINF_SUCCESS;
3667}
3668
3669
3670/** @callback_method_impl{FNCPUMWRMSR} */
3671static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3672{
3673 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3674 /** @todo AMD P-states. */
3675 return VINF_SUCCESS;
3676}
3677
3678
3679/** @callback_method_impl{FNCPUMRDMSR} */
3680static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3681{
3682 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3683 /** @todo AMD P-states. */
3684 *puValue = pRange->uValue;
3685 return VINF_SUCCESS;
3686}
3687
3688
3689/** @callback_method_impl{FNCPUMWRMSR} */
3690static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3691{
3692 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3693 /** @todo AMD P-states. */
3694 return VINF_SUCCESS;
3695}
3696
3697
3698/** @callback_method_impl{FNCPUMRDMSR} */
3699static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3700{
3701 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3702 /** @todo AMD P-states. */
3703 *puValue = pRange->uValue;
3704 return VINF_SUCCESS;
3705}
3706
3707
3708/** @callback_method_impl{FNCPUMWRMSR} */
3709static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3710{
3711 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3712 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3713 /** @todo AMD P-states. */
3714 return VINF_SUCCESS;
3715}
3716
3717
3718/** @callback_method_impl{FNCPUMRDMSR} */
3719static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3720{
3721 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3722 /** @todo AMD C-states. */
3723 *puValue = 0;
3724 return VINF_SUCCESS;
3725}
3726
3727
3728/** @callback_method_impl{FNCPUMWRMSR} */
3729static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3730{
3731 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3732 /** @todo AMD C-states. */
3733 return VINF_SUCCESS;
3734}
3735
3736
3737/** @callback_method_impl{FNCPUMRDMSR} */
3738static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3739{
3740 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3741 /** @todo AMD machine checks. */
3742 *puValue = 0;
3743 return VINF_SUCCESS;
3744}
3745
3746
3747/** @callback_method_impl{FNCPUMWRMSR} */
3748static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3749{
3750 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3751 /** @todo AMD machine checks. */
3752 return VINF_SUCCESS;
3753}
3754
3755
3756/** @callback_method_impl{FNCPUMRDMSR} */
3757static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3758{
3759 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3760 /** @todo AMD SMM. */
3761 *puValue = 0;
3762 return VINF_SUCCESS;
3763}
3764
3765
3766/** @callback_method_impl{FNCPUMWRMSR} */
3767static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3768{
3769 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3770 /** @todo AMD SMM. */
3771 return VINF_SUCCESS;
3772}
3773
3774
3775/** @callback_method_impl{FNCPUMRDMSR} */
3776static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3777{
3778 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3779 /** @todo AMD SMM. */
3780 *puValue = 0;
3781 return VINF_SUCCESS;
3782}
3783
3784
3785/** @callback_method_impl{FNCPUMWRMSR} */
3786static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3787{
3788 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3789 /** @todo AMD SMM. */
3790 return VINF_SUCCESS;
3791}
3792
3793
3794
3795/** @callback_method_impl{FNCPUMRDMSR} */
3796static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3797{
3798 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3799 /** @todo AMD SMM. */
3800 *puValue = 0;
3801 return VINF_SUCCESS;
3802}
3803
3804
3805/** @callback_method_impl{FNCPUMWRMSR} */
3806static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3807{
3808 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3809 /** @todo AMD SMM. */
3810 return VINF_SUCCESS;
3811}
3812
3813
3814/** @callback_method_impl{FNCPUMRDMSR} */
3815static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3816{
3817 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3818 PVM pVM = pVCpu->CTX_SUFF(pVM);
3819 if (pVM->cpum.s.GuestFeatures.fSvm)
3820 *puValue = MSR_K8_VM_CR_LOCK;
3821 else
3822 *puValue = 0;
3823 return VINF_SUCCESS;
3824}
3825
3826
3827/** @callback_method_impl{FNCPUMWRMSR} */
3828static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3829{
3830 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3831 PVM pVM = pVCpu->CTX_SUFF(pVM);
3832 if (pVM->cpum.s.GuestFeatures.fSvm)
3833 {
3834 /* Silently ignore writes to LOCK and SVM_DISABLE bit when the LOCK bit is set (see cpumMsrRd_AmdK8VmCr). */
3835 if (uValue & (MSR_K8_VM_CR_DPD | MSR_K8_VM_CR_R_INIT | MSR_K8_VM_CR_DIS_A20M))
3836 return VERR_CPUM_RAISE_GP_0;
3837 return VINF_SUCCESS;
3838 }
3839 return VERR_CPUM_RAISE_GP_0;
3840}
3841
3842
3843/** @callback_method_impl{FNCPUMRDMSR} */
3844static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3845{
3846 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3847 /** @todo AMD IGNNE\# control. */
3848 *puValue = 0;
3849 return VINF_SUCCESS;
3850}
3851
3852
3853/** @callback_method_impl{FNCPUMWRMSR} */
3854static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3855{
3856 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3857 /** @todo AMD IGNNE\# control. */
3858 return VINF_SUCCESS;
3859}
3860
3861
3862/** @callback_method_impl{FNCPUMRDMSR} */
3863static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3864{
3865 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3866 /** @todo AMD SMM. */
3867 *puValue = 0;
3868 return VINF_SUCCESS;
3869}
3870
3871
3872/** @callback_method_impl{FNCPUMWRMSR} */
3873static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3874{
3875 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3876 /** @todo AMD SMM. */
3877 return VINF_SUCCESS;
3878}
3879
3880
3881/** @callback_method_impl{FNCPUMRDMSR} */
3882static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3883{
3884 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3885 *puValue = pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa;
3886 return VINF_SUCCESS;
3887}
3888
3889
3890/** @callback_method_impl{FNCPUMWRMSR} */
3891static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3892{
3893 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3894 if (uValue & UINT64_C(0xfff))
3895 {
3896 Log(("CPUM: Invalid setting of low 12 bits set writing host-state save area MSR %#x: %#llx\n", idMsr, uValue));
3897 return VERR_CPUM_RAISE_GP_0;
3898 }
3899
3900 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3901 if (fInvPhysMask & uValue)
3902 {
3903 Log(("CPUM: Invalid physical address bits set writing host-state save area MSR %#x: %#llx (%#llx)\n",
3904 idMsr, uValue, uValue & fInvPhysMask));
3905 return VERR_CPUM_RAISE_GP_0;
3906 }
3907
3908 pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa = uValue;
3909 return VINF_SUCCESS;
3910}
3911
3912
3913/** @callback_method_impl{FNCPUMRDMSR} */
3914static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3915{
3916 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3917 /** @todo AMD SVM. */
3918 *puValue = 0; /* RAZ */
3919 return VINF_SUCCESS;
3920}
3921
3922
3923/** @callback_method_impl{FNCPUMWRMSR} */
3924static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3925{
3926 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3927 /** @todo AMD SVM. */
3928 return VINF_SUCCESS;
3929}
3930
3931
3932/** @callback_method_impl{FNCPUMRDMSR} */
3933static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3934{
3935 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3936 /** @todo AMD SMM. */
3937 *puValue = 0; /* RAZ */
3938 return VINF_SUCCESS;
3939}
3940
3941
3942/** @callback_method_impl{FNCPUMWRMSR} */
3943static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3944{
3945 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3946 /** @todo AMD SMM. */
3947 return VINF_SUCCESS;
3948}
3949
3950
3951/** @callback_method_impl{FNCPUMRDMSR} */
3952static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3953{
3954 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3955 /** @todo AMD SMM/SMI. */
3956 *puValue = 0;
3957 return VINF_SUCCESS;
3958}
3959
3960
3961/** @callback_method_impl{FNCPUMWRMSR} */
3962static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3963{
3964 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3965 /** @todo AMD SMM/SMI. */
3966 return VINF_SUCCESS;
3967}
3968
3969
3970/** @callback_method_impl{FNCPUMRDMSR} */
3971static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3972{
3973 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3974 /** @todo AMD OS visible workaround. */
3975 *puValue = pRange->uValue;
3976 return VINF_SUCCESS;
3977}
3978
3979
3980/** @callback_method_impl{FNCPUMWRMSR} */
3981static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3982{
3983 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3984 /** @todo AMD OS visible workaround. */
3985 return VINF_SUCCESS;
3986}
3987
3988
3989/** @callback_method_impl{FNCPUMRDMSR} */
3990static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3991{
3992 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3993 /** @todo AMD OS visible workaround. */
3994 *puValue = 0;
3995 return VINF_SUCCESS;
3996}
3997
3998
3999/** @callback_method_impl{FNCPUMWRMSR} */
4000static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4001{
4002 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4003 /** @todo AMD OS visible workaround. */
4004 return VINF_SUCCESS;
4005}
4006
4007
4008/** @callback_method_impl{FNCPUMRDMSR} */
4009static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4010{
4011 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4012 /** @todo AMD L2I performance counters. */
4013 *puValue = 0;
4014 return VINF_SUCCESS;
4015}
4016
4017
4018/** @callback_method_impl{FNCPUMWRMSR} */
4019static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4020{
4021 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4022 /** @todo AMD L2I performance counters. */
4023 return VINF_SUCCESS;
4024}
4025
4026
4027/** @callback_method_impl{FNCPUMRDMSR} */
4028static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4029{
4030 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4031 /** @todo AMD L2I performance counters. */
4032 *puValue = 0;
4033 return VINF_SUCCESS;
4034}
4035
4036
4037/** @callback_method_impl{FNCPUMWRMSR} */
4038static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4039{
4040 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4041 /** @todo AMD L2I performance counters. */
4042 return VINF_SUCCESS;
4043}
4044
4045
4046/** @callback_method_impl{FNCPUMRDMSR} */
4047static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4048{
4049 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4050 /** @todo AMD Northbridge performance counters. */
4051 *puValue = 0;
4052 return VINF_SUCCESS;
4053}
4054
4055
4056/** @callback_method_impl{FNCPUMWRMSR} */
4057static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4058{
4059 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4060 /** @todo AMD Northbridge performance counters. */
4061 return VINF_SUCCESS;
4062}
4063
4064
4065/** @callback_method_impl{FNCPUMRDMSR} */
4066static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4067{
4068 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4069 /** @todo AMD Northbridge performance counters. */
4070 *puValue = 0;
4071 return VINF_SUCCESS;
4072}
4073
4074
4075/** @callback_method_impl{FNCPUMWRMSR} */
4076static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4077{
4078 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4079 /** @todo AMD Northbridge performance counters. */
4080 return VINF_SUCCESS;
4081}
4082
4083
4084/** @callback_method_impl{FNCPUMRDMSR} */
4085static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4086{
4087 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4088 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4089 * cpus. Need to be explored and verify K7 presence. */
4090 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4091 *puValue = pRange->uValue;
4092 return VINF_SUCCESS;
4093}
4094
4095
4096/** @callback_method_impl{FNCPUMWRMSR} */
4097static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4098{
4099 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4100 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4101 * cpus. Need to be explored and verify K7 presence. */
4102 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4103 return VINF_SUCCESS;
4104}
4105
4106
4107/** @callback_method_impl{FNCPUMRDMSR} */
4108static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4109{
4110 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4111 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4112 * cpus. Need to be explored and verify K7 presence. */
4113 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4114 * describing EBL_CR_POWERON. */
4115 *puValue = pRange->uValue;
4116 return VINF_SUCCESS;
4117}
4118
4119
4120/** @callback_method_impl{FNCPUMWRMSR} */
4121static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4122{
4123 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4124 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4125 * cpus. Need to be explored and verify K7 presence. */
4126 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4127 * describing EBL_CR_POWERON. */
4128 return VINF_SUCCESS;
4129}
4130
4131
4132/** @callback_method_impl{FNCPUMRDMSR} */
4133static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4134{
4135 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4136 bool fIgnored;
4137 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
4138 if (pLeaf)
4139 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
4140 else
4141 *puValue = 0;
4142 return VINF_SUCCESS;
4143}
4144
4145
4146/** @callback_method_impl{FNCPUMWRMSR} */
4147static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4148{
4149 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4150 /** @todo Changing CPUID leaf 7/0. */
4151 return VINF_SUCCESS;
4152}
4153
4154
4155/** @callback_method_impl{FNCPUMRDMSR} */
4156static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4157{
4158 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4159 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
4160 if (pLeaf)
4161 *puValue = pLeaf->uEcx;
4162 else
4163 *puValue = 0;
4164 return VINF_SUCCESS;
4165}
4166
4167
4168/** @callback_method_impl{FNCPUMWRMSR} */
4169static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4170{
4171 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4172 /** @todo Changing CPUID leaf 6. */
4173 return VINF_SUCCESS;
4174}
4175
4176
4177/** @callback_method_impl{FNCPUMRDMSR} */
4178static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4179{
4180 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4181 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
4182 if (pLeaf)
4183 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4184 else
4185 *puValue = 0;
4186 return VINF_SUCCESS;
4187}
4188
4189
4190/** @callback_method_impl{FNCPUMWRMSR} */
4191static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4192{
4193 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4194 /** @todo Changing CPUID leaf 0x80000001. */
4195 return VINF_SUCCESS;
4196}
4197
4198
4199/** @callback_method_impl{FNCPUMRDMSR} */
4200static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4201{
4202 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4203 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
4204 if (pLeaf)
4205 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4206 else
4207 *puValue = 0;
4208 return VINF_SUCCESS;
4209}
4210
4211
4212/** @callback_method_impl{FNCPUMWRMSR} */
4213static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4214{
4215 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4216 /** @todo Changing CPUID leaf 0x80000001. */
4217 return VINF_SUCCESS;
4218}
4219
4220
4221/** @callback_method_impl{FNCPUMRDMSR} */
4222static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4223{
4224 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4225 /** @todo Fake AMD microcode patching. */
4226 *puValue = pRange->uValue;
4227 return VINF_SUCCESS;
4228}
4229
4230
4231/** @callback_method_impl{FNCPUMWRMSR} */
4232static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4233{
4234 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4235 /** @todo Fake AMD microcode patching. */
4236 return VINF_SUCCESS;
4237}
4238
4239
4240/** @callback_method_impl{FNCPUMRDMSR} */
4241static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4242{
4243 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4244 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4245 * cpus. Need to be explored and verify K7 presence. */
4246 /** @todo undocumented */
4247 *puValue = 0;
4248 return VINF_SUCCESS;
4249}
4250
4251
4252/** @callback_method_impl{FNCPUMWRMSR} */
4253static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4254{
4255 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4256 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4257 * cpus. Need to be explored and verify K7 presence. */
4258 /** @todo undocumented */
4259 return VINF_SUCCESS;
4260}
4261
4262
4263/** @callback_method_impl{FNCPUMRDMSR} */
4264static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4265{
4266 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4267 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4268 * cpus. Need to be explored and verify K7 presence. */
4269 /** @todo undocumented */
4270 *puValue = 0;
4271 return VINF_SUCCESS;
4272}
4273
4274
4275/** @callback_method_impl{FNCPUMWRMSR} */
4276static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4277{
4278 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4279 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4280 * cpus. Need to be explored and verify K7 presence. */
4281 /** @todo undocumented */
4282 return VINF_SUCCESS;
4283}
4284
4285
4286/** @callback_method_impl{FNCPUMRDMSR} */
4287static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4288{
4289 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4290 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4291 * cpus. Need to be explored and verify K7 presence. */
4292 /** @todo undocumented */
4293 *puValue = 0;
4294 return VINF_SUCCESS;
4295}
4296
4297
4298/** @callback_method_impl{FNCPUMWRMSR} */
4299static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4300{
4301 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4302 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4303 * cpus. Need to be explored and verify K7 presence. */
4304 /** @todo undocumented */
4305 return VINF_SUCCESS;
4306}
4307
4308
4309/** @callback_method_impl{FNCPUMRDMSR} */
4310static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4311{
4312 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4313 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4314 * cpus. Need to be explored and verify K7 presence. */
4315 /** @todo undocumented */
4316 *puValue = 0;
4317 return VINF_SUCCESS;
4318}
4319
4320
4321/** @callback_method_impl{FNCPUMWRMSR} */
4322static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4323{
4324 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4325 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4326 * cpus. Need to be explored and verify K7 presence. */
4327 /** @todo undocumented */
4328 return VINF_SUCCESS;
4329}
4330
4331
4332/** @callback_method_impl{FNCPUMRDMSR} */
4333static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4334{
4335 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4336 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4337 * cpus. Need to be explored and verify K7 presence. */
4338 /** @todo undocumented */
4339 *puValue = 0;
4340 return VINF_SUCCESS;
4341}
4342
4343
4344/** @callback_method_impl{FNCPUMWRMSR} */
4345static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4346{
4347 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4348 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4349 * cpus. Need to be explored and verify K7 presence. */
4350 /** @todo undocumented */
4351 return VINF_SUCCESS;
4352}
4353
4354
4355/** @callback_method_impl{FNCPUMRDMSR} */
4356static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4357{
4358 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4359 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4360 * cpus. Need to be explored and verify K7 presence. */
4361 /** @todo undocumented */
4362 *puValue = 0;
4363 return VINF_SUCCESS;
4364}
4365
4366
4367/** @callback_method_impl{FNCPUMWRMSR} */
4368static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4369{
4370 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4371 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4372 * cpus. Need to be explored and verify K7 presence. */
4373 /** @todo undocumented */
4374 return VINF_SUCCESS;
4375}
4376
4377
4378/** @callback_method_impl{FNCPUMRDMSR} */
4379static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4380{
4381 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4382 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4383 * cpus. Need to be explored and verify K7 presence. */
4384 /** @todo AMD node ID and bios scratch. */
4385 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
4386 return VINF_SUCCESS;
4387}
4388
4389
4390/** @callback_method_impl{FNCPUMWRMSR} */
4391static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4392{
4393 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4394 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4395 * cpus. Need to be explored and verify K7 presence. */
4396 /** @todo AMD node ID and bios scratch. */
4397 return VINF_SUCCESS;
4398}
4399
4400
4401/** @callback_method_impl{FNCPUMRDMSR} */
4402static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4403{
4404 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4405 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4406 * cpus. Need to be explored and verify K7 presence. */
4407 /** @todo AMD DRx address masking (range breakpoints). */
4408 *puValue = 0;
4409 return VINF_SUCCESS;
4410}
4411
4412
4413/** @callback_method_impl{FNCPUMWRMSR} */
4414static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4415{
4416 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4417 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4418 * cpus. Need to be explored and verify K7 presence. */
4419 /** @todo AMD DRx address masking (range breakpoints). */
4420 return VINF_SUCCESS;
4421}
4422
4423
4424/** @callback_method_impl{FNCPUMRDMSR} */
4425static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4426{
4427 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4428 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4429 * cpus. Need to be explored and verify K7 presence. */
4430 /** @todo AMD undocument debugging features. */
4431 *puValue = 0;
4432 return VINF_SUCCESS;
4433}
4434
4435
4436/** @callback_method_impl{FNCPUMWRMSR} */
4437static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4438{
4439 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4440 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4441 * cpus. Need to be explored and verify K7 presence. */
4442 /** @todo AMD undocument debugging features. */
4443 return VINF_SUCCESS;
4444}
4445
4446
4447/** @callback_method_impl{FNCPUMRDMSR} */
4448static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4449{
4450 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4451 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4452 * cpus. Need to be explored and verify K7 presence. */
4453 /** @todo AMD undocument debugging features. */
4454 *puValue = 0;
4455 return VINF_SUCCESS;
4456}
4457
4458
4459/** @callback_method_impl{FNCPUMWRMSR} */
4460static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4461{
4462 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4463 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4464 * cpus. Need to be explored and verify K7 presence. */
4465 /** @todo AMD undocument debugging features. */
4466 return VINF_SUCCESS;
4467}
4468
4469
4470/** @callback_method_impl{FNCPUMRDMSR} */
4471static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4472{
4473 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4474 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4475 * cpus. Need to be explored and verify K7 presence. */
4476 /** @todo AMD load-store config. */
4477 *puValue = 0;
4478 return VINF_SUCCESS;
4479}
4480
4481
4482/** @callback_method_impl{FNCPUMWRMSR} */
4483static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4484{
4485 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4486 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4487 * cpus. Need to be explored and verify K7 presence. */
4488 /** @todo AMD load-store config. */
4489 return VINF_SUCCESS;
4490}
4491
4492
4493/** @callback_method_impl{FNCPUMRDMSR} */
4494static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4495{
4496 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4497 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4498 * cpus. Need to be explored and verify K7 presence. */
4499 /** @todo AMD instruction cache config. */
4500 *puValue = 0;
4501 return VINF_SUCCESS;
4502}
4503
4504
4505/** @callback_method_impl{FNCPUMWRMSR} */
4506static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4507{
4508 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4509 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4510 * cpus. Need to be explored and verify K7 presence. */
4511 /** @todo AMD instruction cache config. */
4512 return VINF_SUCCESS;
4513}
4514
4515
4516/** @callback_method_impl{FNCPUMRDMSR} */
4517static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4518{
4519 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4520 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4521 * cpus. Need to be explored and verify K7 presence. */
4522 /** @todo AMD data cache config. */
4523 *puValue = 0;
4524 return VINF_SUCCESS;
4525}
4526
4527
4528/** @callback_method_impl{FNCPUMWRMSR} */
4529static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4530{
4531 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4532 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4533 * cpus. Need to be explored and verify K7 presence. */
4534 /** @todo AMD data cache config. */
4535 return VINF_SUCCESS;
4536}
4537
4538
4539/** @callback_method_impl{FNCPUMRDMSR} */
4540static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4541{
4542 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4543 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4544 * cpus. Need to be explored and verify K7 presence. */
4545 /** @todo AMD bus unit config. */
4546 *puValue = 0;
4547 return VINF_SUCCESS;
4548}
4549
4550
4551/** @callback_method_impl{FNCPUMWRMSR} */
4552static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4553{
4554 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4555 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4556 * cpus. Need to be explored and verify K7 presence. */
4557 /** @todo AMD bus unit config. */
4558 return VINF_SUCCESS;
4559}
4560
4561
4562/** @callback_method_impl{FNCPUMRDMSR} */
4563static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4564{
4565 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4566 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4567 * cpus. Need to be explored and verify K7 presence. */
4568 /** @todo Undocument AMD debug control register \#2. */
4569 *puValue = 0;
4570 return VINF_SUCCESS;
4571}
4572
4573
4574/** @callback_method_impl{FNCPUMWRMSR} */
4575static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4576{
4577 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4578 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4579 * cpus. Need to be explored and verify K7 presence. */
4580 /** @todo Undocument AMD debug control register \#2. */
4581 return VINF_SUCCESS;
4582}
4583
4584
4585/** @callback_method_impl{FNCPUMRDMSR} */
4586static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4587{
4588 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4589 /** @todo AMD FPU config. */
4590 *puValue = 0;
4591 return VINF_SUCCESS;
4592}
4593
4594
4595/** @callback_method_impl{FNCPUMWRMSR} */
4596static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4597{
4598 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4599 /** @todo AMD FPU config. */
4600 return VINF_SUCCESS;
4601}
4602
4603
4604/** @callback_method_impl{FNCPUMRDMSR} */
4605static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4606{
4607 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4608 /** @todo AMD decoder config. */
4609 *puValue = 0;
4610 return VINF_SUCCESS;
4611}
4612
4613
4614/** @callback_method_impl{FNCPUMWRMSR} */
4615static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4616{
4617 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4618 /** @todo AMD decoder config. */
4619 return VINF_SUCCESS;
4620}
4621
4622
4623/** @callback_method_impl{FNCPUMRDMSR} */
4624static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4625{
4626 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4627 /* Note! 10h and 16h */
4628 /** @todo AMD bus unit config. */
4629 *puValue = 0;
4630 return VINF_SUCCESS;
4631}
4632
4633
4634/** @callback_method_impl{FNCPUMWRMSR} */
4635static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4636{
4637 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4638 /* Note! 10h and 16h */
4639 /** @todo AMD bus unit config. */
4640 return VINF_SUCCESS;
4641}
4642
4643
4644/** @callback_method_impl{FNCPUMRDMSR} */
4645static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4646{
4647 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4648 /** @todo AMD unit config. */
4649 *puValue = 0;
4650 return VINF_SUCCESS;
4651}
4652
4653
4654/** @callback_method_impl{FNCPUMWRMSR} */
4655static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4656{
4657 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4658 /** @todo AMD unit config. */
4659 return VINF_SUCCESS;
4660}
4661
4662
4663/** @callback_method_impl{FNCPUMRDMSR} */
4664static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4665{
4666 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4667 /** @todo AMD unit config 2. */
4668 *puValue = 0;
4669 return VINF_SUCCESS;
4670}
4671
4672
4673/** @callback_method_impl{FNCPUMWRMSR} */
4674static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4675{
4676 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4677 /** @todo AMD unit config 2. */
4678 return VINF_SUCCESS;
4679}
4680
4681
4682/** @callback_method_impl{FNCPUMRDMSR} */
4683static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4684{
4685 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4686 /** @todo AMD combined unit config 3. */
4687 *puValue = 0;
4688 return VINF_SUCCESS;
4689}
4690
4691
4692/** @callback_method_impl{FNCPUMWRMSR} */
4693static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4694{
4695 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4696 /** @todo AMD combined unit config 3. */
4697 return VINF_SUCCESS;
4698}
4699
4700
4701/** @callback_method_impl{FNCPUMRDMSR} */
4702static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4703{
4704 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4705 /** @todo AMD execution unit config. */
4706 *puValue = 0;
4707 return VINF_SUCCESS;
4708}
4709
4710
4711/** @callback_method_impl{FNCPUMWRMSR} */
4712static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4713{
4714 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4715 /** @todo AMD execution unit config. */
4716 return VINF_SUCCESS;
4717}
4718
4719
4720/** @callback_method_impl{FNCPUMRDMSR} */
4721static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4722{
4723 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4724 /** @todo AMD load-store config 2. */
4725 *puValue = 0;
4726 return VINF_SUCCESS;
4727}
4728
4729
4730/** @callback_method_impl{FNCPUMWRMSR} */
4731static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4732{
4733 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4734 /** @todo AMD load-store config 2. */
4735 return VINF_SUCCESS;
4736}
4737
4738
4739/** @callback_method_impl{FNCPUMRDMSR} */
4740static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4741{
4742 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4743 /** @todo AMD IBS. */
4744 *puValue = 0;
4745 return VINF_SUCCESS;
4746}
4747
4748
4749/** @callback_method_impl{FNCPUMWRMSR} */
4750static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4751{
4752 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4753 /** @todo AMD IBS. */
4754 return VINF_SUCCESS;
4755}
4756
4757
4758/** @callback_method_impl{FNCPUMRDMSR} */
4759static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4760{
4761 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4762 /** @todo AMD IBS. */
4763 *puValue = 0;
4764 return VINF_SUCCESS;
4765}
4766
4767
4768/** @callback_method_impl{FNCPUMWRMSR} */
4769static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4770{
4771 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4772 /** @todo AMD IBS. */
4773 return VINF_SUCCESS;
4774}
4775
4776
4777/** @callback_method_impl{FNCPUMRDMSR} */
4778static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4779{
4780 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4781 /** @todo AMD IBS. */
4782 *puValue = 0;
4783 return VINF_SUCCESS;
4784}
4785
4786
4787/** @callback_method_impl{FNCPUMWRMSR} */
4788static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4789{
4790 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4791 /** @todo AMD IBS. */
4792 return VINF_SUCCESS;
4793}
4794
4795
4796/** @callback_method_impl{FNCPUMRDMSR} */
4797static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4798{
4799 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4800 /** @todo AMD IBS. */
4801 *puValue = 0;
4802 return VINF_SUCCESS;
4803}
4804
4805
4806/** @callback_method_impl{FNCPUMWRMSR} */
4807static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4808{
4809 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4810 /** @todo AMD IBS. */
4811 return VINF_SUCCESS;
4812}
4813
4814
4815/** @callback_method_impl{FNCPUMRDMSR} */
4816static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4817{
4818 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4819 /** @todo AMD IBS. */
4820 *puValue = 0;
4821 return VINF_SUCCESS;
4822}
4823
4824
4825/** @callback_method_impl{FNCPUMWRMSR} */
4826static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4827{
4828 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4829 /** @todo AMD IBS. */
4830 if (!X86_IS_CANONICAL(uValue))
4831 {
4832 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4833 return VERR_CPUM_RAISE_GP_0;
4834 }
4835 return VINF_SUCCESS;
4836}
4837
4838
4839/** @callback_method_impl{FNCPUMRDMSR} */
4840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4841{
4842 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4843 /** @todo AMD IBS. */
4844 *puValue = 0;
4845 return VINF_SUCCESS;
4846}
4847
4848
4849/** @callback_method_impl{FNCPUMWRMSR} */
4850static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4851{
4852 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4853 /** @todo AMD IBS. */
4854 return VINF_SUCCESS;
4855}
4856
4857
4858/** @callback_method_impl{FNCPUMRDMSR} */
4859static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4860{
4861 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4862 /** @todo AMD IBS. */
4863 *puValue = 0;
4864 return VINF_SUCCESS;
4865}
4866
4867
4868/** @callback_method_impl{FNCPUMWRMSR} */
4869static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4870{
4871 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4872 /** @todo AMD IBS. */
4873 return VINF_SUCCESS;
4874}
4875
4876
4877/** @callback_method_impl{FNCPUMRDMSR} */
4878static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4879{
4880 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4881 /** @todo AMD IBS. */
4882 *puValue = 0;
4883 return VINF_SUCCESS;
4884}
4885
4886
4887/** @callback_method_impl{FNCPUMWRMSR} */
4888static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4889{
4890 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4891 /** @todo AMD IBS. */
4892 return VINF_SUCCESS;
4893}
4894
4895
4896/** @callback_method_impl{FNCPUMRDMSR} */
4897static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4898{
4899 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4900 /** @todo AMD IBS. */
4901 *puValue = 0;
4902 return VINF_SUCCESS;
4903}
4904
4905
4906/** @callback_method_impl{FNCPUMWRMSR} */
4907static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4908{
4909 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4910 /** @todo AMD IBS. */
4911 if (!X86_IS_CANONICAL(uValue))
4912 {
4913 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4914 return VERR_CPUM_RAISE_GP_0;
4915 }
4916 return VINF_SUCCESS;
4917}
4918
4919
4920/** @callback_method_impl{FNCPUMRDMSR} */
4921static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4922{
4923 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4924 /** @todo AMD IBS. */
4925 *puValue = 0;
4926 return VINF_SUCCESS;
4927}
4928
4929
4930/** @callback_method_impl{FNCPUMWRMSR} */
4931static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4932{
4933 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4934 /** @todo AMD IBS. */
4935 return VINF_SUCCESS;
4936}
4937
4938
4939/** @callback_method_impl{FNCPUMRDMSR} */
4940static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4941{
4942 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4943 /** @todo AMD IBS. */
4944 *puValue = 0;
4945 return VINF_SUCCESS;
4946}
4947
4948
4949/** @callback_method_impl{FNCPUMWRMSR} */
4950static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4951{
4952 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4953 /** @todo AMD IBS. */
4954 return VINF_SUCCESS;
4955}
4956
4957
4958/** @callback_method_impl{FNCPUMRDMSR} */
4959static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4960{
4961 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4962 /** @todo AMD IBS. */
4963 *puValue = 0;
4964 return VINF_SUCCESS;
4965}
4966
4967
4968/** @callback_method_impl{FNCPUMWRMSR} */
4969static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4970{
4971 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4972 /** @todo AMD IBS. */
4973 if (!X86_IS_CANONICAL(uValue))
4974 {
4975 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4976 return VERR_CPUM_RAISE_GP_0;
4977 }
4978 return VINF_SUCCESS;
4979}
4980
4981
4982
4983/*
4984 * GIM MSRs.
4985 * GIM MSRs.
4986 * GIM MSRs.
4987 */
4988
4989
4990/** @callback_method_impl{FNCPUMRDMSR} */
4991static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4992{
4993#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
4994 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
4995 if ( CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest)
4996 || CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
4997 return VERR_CPUM_RAISE_GP_0;
4998#endif
4999 return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
5000}
5001
5002
5003/** @callback_method_impl{FNCPUMWRMSR} */
5004static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5005{
5006#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
5007 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
5008 if ( CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest)
5009 || CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
5010 return VERR_CPUM_RAISE_GP_0;
5011#endif
5012 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
5013}
5014
5015
5016/**
5017 * MSR read function table.
5018 */
5019static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
5020{
5021 NULL, /* Invalid */
5022 cpumMsrRd_FixedValue,
5023 NULL, /* Alias */
5024 cpumMsrRd_WriteOnly,
5025 cpumMsrRd_Ia32P5McAddr,
5026 cpumMsrRd_Ia32P5McType,
5027 cpumMsrRd_Ia32TimestampCounter,
5028 cpumMsrRd_Ia32PlatformId,
5029 cpumMsrRd_Ia32ApicBase,
5030 cpumMsrRd_Ia32FeatureControl,
5031 cpumMsrRd_Ia32BiosSignId,
5032 cpumMsrRd_Ia32SmmMonitorCtl,
5033 cpumMsrRd_Ia32PmcN,
5034 cpumMsrRd_Ia32MonitorFilterLineSize,
5035 cpumMsrRd_Ia32MPerf,
5036 cpumMsrRd_Ia32APerf,
5037 cpumMsrRd_Ia32MtrrCap,
5038 cpumMsrRd_Ia32MtrrPhysBaseN,
5039 cpumMsrRd_Ia32MtrrPhysMaskN,
5040 cpumMsrRd_Ia32MtrrFixed,
5041 cpumMsrRd_Ia32MtrrDefType,
5042 cpumMsrRd_Ia32Pat,
5043 cpumMsrRd_Ia32SysEnterCs,
5044 cpumMsrRd_Ia32SysEnterEsp,
5045 cpumMsrRd_Ia32SysEnterEip,
5046 cpumMsrRd_Ia32McgCap,
5047 cpumMsrRd_Ia32McgStatus,
5048 cpumMsrRd_Ia32McgCtl,
5049 cpumMsrRd_Ia32DebugCtl,
5050 cpumMsrRd_Ia32SmrrPhysBase,
5051 cpumMsrRd_Ia32SmrrPhysMask,
5052 cpumMsrRd_Ia32PlatformDcaCap,
5053 cpumMsrRd_Ia32CpuDcaCap,
5054 cpumMsrRd_Ia32Dca0Cap,
5055 cpumMsrRd_Ia32PerfEvtSelN,
5056 cpumMsrRd_Ia32PerfStatus,
5057 cpumMsrRd_Ia32PerfCtl,
5058 cpumMsrRd_Ia32FixedCtrN,
5059 cpumMsrRd_Ia32PerfCapabilities,
5060 cpumMsrRd_Ia32FixedCtrCtrl,
5061 cpumMsrRd_Ia32PerfGlobalStatus,
5062 cpumMsrRd_Ia32PerfGlobalCtrl,
5063 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
5064 cpumMsrRd_Ia32PebsEnable,
5065 cpumMsrRd_Ia32ClockModulation,
5066 cpumMsrRd_Ia32ThermInterrupt,
5067 cpumMsrRd_Ia32ThermStatus,
5068 cpumMsrRd_Ia32Therm2Ctl,
5069 cpumMsrRd_Ia32MiscEnable,
5070 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
5071 cpumMsrRd_Ia32McNCtl2,
5072 cpumMsrRd_Ia32DsArea,
5073 cpumMsrRd_Ia32TscDeadline,
5074 cpumMsrRd_Ia32X2ApicN,
5075 cpumMsrRd_Ia32DebugInterface,
5076 cpumMsrRd_Ia32VmxBasic,
5077 cpumMsrRd_Ia32VmxPinbasedCtls,
5078 cpumMsrRd_Ia32VmxProcbasedCtls,
5079 cpumMsrRd_Ia32VmxExitCtls,
5080 cpumMsrRd_Ia32VmxEntryCtls,
5081 cpumMsrRd_Ia32VmxMisc,
5082 cpumMsrRd_Ia32VmxCr0Fixed0,
5083 cpumMsrRd_Ia32VmxCr0Fixed1,
5084 cpumMsrRd_Ia32VmxCr4Fixed0,
5085 cpumMsrRd_Ia32VmxCr4Fixed1,
5086 cpumMsrRd_Ia32VmxVmcsEnum,
5087 cpumMsrRd_Ia32VmxProcBasedCtls2,
5088 cpumMsrRd_Ia32VmxEptVpidCap,
5089 cpumMsrRd_Ia32VmxTruePinbasedCtls,
5090 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
5091 cpumMsrRd_Ia32VmxTrueExitCtls,
5092 cpumMsrRd_Ia32VmxTrueEntryCtls,
5093 cpumMsrRd_Ia32VmxVmFunc,
5094 cpumMsrRd_Ia32SpecCtrl,
5095 cpumMsrRd_Ia32ArchCapabilities,
5096
5097 cpumMsrRd_Amd64Efer,
5098 cpumMsrRd_Amd64SyscallTarget,
5099 cpumMsrRd_Amd64LongSyscallTarget,
5100 cpumMsrRd_Amd64CompSyscallTarget,
5101 cpumMsrRd_Amd64SyscallFlagMask,
5102 cpumMsrRd_Amd64FsBase,
5103 cpumMsrRd_Amd64GsBase,
5104 cpumMsrRd_Amd64KernelGsBase,
5105 cpumMsrRd_Amd64TscAux,
5106
5107 cpumMsrRd_IntelEblCrPowerOn,
5108 cpumMsrRd_IntelI7CoreThreadCount,
5109 cpumMsrRd_IntelP4EbcHardPowerOn,
5110 cpumMsrRd_IntelP4EbcSoftPowerOn,
5111 cpumMsrRd_IntelP4EbcFrequencyId,
5112 cpumMsrRd_IntelP6FsbFrequency,
5113 cpumMsrRd_IntelPlatformInfo,
5114 cpumMsrRd_IntelFlexRatio,
5115 cpumMsrRd_IntelPkgCStConfigControl,
5116 cpumMsrRd_IntelPmgIoCaptureBase,
5117 cpumMsrRd_IntelLastBranchFromToN,
5118 cpumMsrRd_IntelLastBranchFromN,
5119 cpumMsrRd_IntelLastBranchToN,
5120 cpumMsrRd_IntelLastBranchTos,
5121 cpumMsrRd_IntelBblCrCtl,
5122 cpumMsrRd_IntelBblCrCtl3,
5123 cpumMsrRd_IntelI7TemperatureTarget,
5124 cpumMsrRd_IntelI7MsrOffCoreResponseN,
5125 cpumMsrRd_IntelI7MiscPwrMgmt,
5126 cpumMsrRd_IntelP6CrN,
5127 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
5128 cpumMsrRd_IntelCpuId1FeatureMaskEax,
5129 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
5130 cpumMsrRd_IntelI7SandyAesNiCtl,
5131 cpumMsrRd_IntelI7TurboRatioLimit,
5132 cpumMsrRd_IntelI7LbrSelect,
5133 cpumMsrRd_IntelI7SandyErrorControl,
5134 cpumMsrRd_IntelI7VirtualLegacyWireCap,
5135 cpumMsrRd_IntelI7PowerCtl,
5136 cpumMsrRd_IntelI7SandyPebsNumAlt,
5137 cpumMsrRd_IntelI7PebsLdLat,
5138 cpumMsrRd_IntelI7PkgCnResidencyN,
5139 cpumMsrRd_IntelI7CoreCnResidencyN,
5140 cpumMsrRd_IntelI7SandyVrCurrentConfig,
5141 cpumMsrRd_IntelI7SandyVrMiscConfig,
5142 cpumMsrRd_IntelI7SandyRaplPowerUnit,
5143 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
5144 cpumMsrRd_IntelI7SandyPkgC2Residency,
5145 cpumMsrRd_IntelI7RaplPkgPowerLimit,
5146 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
5147 cpumMsrRd_IntelI7RaplPkgPerfStatus,
5148 cpumMsrRd_IntelI7RaplPkgPowerInfo,
5149 cpumMsrRd_IntelI7RaplDramPowerLimit,
5150 cpumMsrRd_IntelI7RaplDramEnergyStatus,
5151 cpumMsrRd_IntelI7RaplDramPerfStatus,
5152 cpumMsrRd_IntelI7RaplDramPowerInfo,
5153 cpumMsrRd_IntelI7RaplPp0PowerLimit,
5154 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
5155 cpumMsrRd_IntelI7RaplPp0Policy,
5156 cpumMsrRd_IntelI7RaplPp0PerfStatus,
5157 cpumMsrRd_IntelI7RaplPp1PowerLimit,
5158 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
5159 cpumMsrRd_IntelI7RaplPp1Policy,
5160 cpumMsrRd_IntelI7IvyConfigTdpNominal,
5161 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
5162 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
5163 cpumMsrRd_IntelI7IvyConfigTdpControl,
5164 cpumMsrRd_IntelI7IvyTurboActivationRatio,
5165 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
5166 cpumMsrRd_IntelI7UncPerfGlobalStatus,
5167 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
5168 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
5169 cpumMsrRd_IntelI7UncPerfFixedCtr,
5170 cpumMsrRd_IntelI7UncCBoxConfig,
5171 cpumMsrRd_IntelI7UncArbPerfCtrN,
5172 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
5173 cpumMsrRd_IntelI7SmiCount,
5174 cpumMsrRd_IntelCore2EmttmCrTablesN,
5175 cpumMsrRd_IntelCore2SmmCStMiscInfo,
5176 cpumMsrRd_IntelCore1ExtConfig,
5177 cpumMsrRd_IntelCore1DtsCalControl,
5178 cpumMsrRd_IntelCore2PeciControl,
5179 cpumMsrRd_IntelAtSilvCoreC1Recidency,
5180
5181 cpumMsrRd_P6LastBranchFromIp,
5182 cpumMsrRd_P6LastBranchToIp,
5183 cpumMsrRd_P6LastIntFromIp,
5184 cpumMsrRd_P6LastIntToIp,
5185
5186 cpumMsrRd_AmdFam15hTscRate,
5187 cpumMsrRd_AmdFam15hLwpCfg,
5188 cpumMsrRd_AmdFam15hLwpCbAddr,
5189 cpumMsrRd_AmdFam10hMc4MiscN,
5190 cpumMsrRd_AmdK8PerfCtlN,
5191 cpumMsrRd_AmdK8PerfCtrN,
5192 cpumMsrRd_AmdK8SysCfg,
5193 cpumMsrRd_AmdK8HwCr,
5194 cpumMsrRd_AmdK8IorrBaseN,
5195 cpumMsrRd_AmdK8IorrMaskN,
5196 cpumMsrRd_AmdK8TopOfMemN,
5197 cpumMsrRd_AmdK8NbCfg1,
5198 cpumMsrRd_AmdK8McXcptRedir,
5199 cpumMsrRd_AmdK8CpuNameN,
5200 cpumMsrRd_AmdK8HwThermalCtrl,
5201 cpumMsrRd_AmdK8SwThermalCtrl,
5202 cpumMsrRd_AmdK8FidVidControl,
5203 cpumMsrRd_AmdK8FidVidStatus,
5204 cpumMsrRd_AmdK8McCtlMaskN,
5205 cpumMsrRd_AmdK8SmiOnIoTrapN,
5206 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
5207 cpumMsrRd_AmdK8IntPendingMessage,
5208 cpumMsrRd_AmdK8SmiTriggerIoCycle,
5209 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
5210 cpumMsrRd_AmdFam10hTrapCtlMaybe,
5211 cpumMsrRd_AmdFam10hPStateCurLimit,
5212 cpumMsrRd_AmdFam10hPStateControl,
5213 cpumMsrRd_AmdFam10hPStateStatus,
5214 cpumMsrRd_AmdFam10hPStateN,
5215 cpumMsrRd_AmdFam10hCofVidControl,
5216 cpumMsrRd_AmdFam10hCofVidStatus,
5217 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
5218 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
5219 cpumMsrRd_AmdK8SmmBase,
5220 cpumMsrRd_AmdK8SmmAddr,
5221 cpumMsrRd_AmdK8SmmMask,
5222 cpumMsrRd_AmdK8VmCr,
5223 cpumMsrRd_AmdK8IgnNe,
5224 cpumMsrRd_AmdK8SmmCtl,
5225 cpumMsrRd_AmdK8VmHSavePa,
5226 cpumMsrRd_AmdFam10hVmLockKey,
5227 cpumMsrRd_AmdFam10hSmmLockKey,
5228 cpumMsrRd_AmdFam10hLocalSmiStatus,
5229 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
5230 cpumMsrRd_AmdFam10hOsVisWrkStatus,
5231 cpumMsrRd_AmdFam16hL2IPerfCtlN,
5232 cpumMsrRd_AmdFam16hL2IPerfCtrN,
5233 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
5234 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
5235 cpumMsrRd_AmdK7MicrocodeCtl,
5236 cpumMsrRd_AmdK7ClusterIdMaybe,
5237 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
5238 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
5239 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
5240 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
5241 cpumMsrRd_AmdK8PatchLevel,
5242 cpumMsrRd_AmdK7DebugStatusMaybe,
5243 cpumMsrRd_AmdK7BHTraceBaseMaybe,
5244 cpumMsrRd_AmdK7BHTracePtrMaybe,
5245 cpumMsrRd_AmdK7BHTraceLimitMaybe,
5246 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
5247 cpumMsrRd_AmdK7FastFlushCountMaybe,
5248 cpumMsrRd_AmdK7NodeId,
5249 cpumMsrRd_AmdK7DrXAddrMaskN,
5250 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
5251 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
5252 cpumMsrRd_AmdK7LoadStoreCfg,
5253 cpumMsrRd_AmdK7InstrCacheCfg,
5254 cpumMsrRd_AmdK7DataCacheCfg,
5255 cpumMsrRd_AmdK7BusUnitCfg,
5256 cpumMsrRd_AmdK7DebugCtl2Maybe,
5257 cpumMsrRd_AmdFam15hFpuCfg,
5258 cpumMsrRd_AmdFam15hDecoderCfg,
5259 cpumMsrRd_AmdFam10hBusUnitCfg2,
5260 cpumMsrRd_AmdFam15hCombUnitCfg,
5261 cpumMsrRd_AmdFam15hCombUnitCfg2,
5262 cpumMsrRd_AmdFam15hCombUnitCfg3,
5263 cpumMsrRd_AmdFam15hExecUnitCfg,
5264 cpumMsrRd_AmdFam15hLoadStoreCfg2,
5265 cpumMsrRd_AmdFam10hIbsFetchCtl,
5266 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
5267 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
5268 cpumMsrRd_AmdFam10hIbsOpExecCtl,
5269 cpumMsrRd_AmdFam10hIbsOpRip,
5270 cpumMsrRd_AmdFam10hIbsOpData,
5271 cpumMsrRd_AmdFam10hIbsOpData2,
5272 cpumMsrRd_AmdFam10hIbsOpData3,
5273 cpumMsrRd_AmdFam10hIbsDcLinAddr,
5274 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
5275 cpumMsrRd_AmdFam10hIbsCtl,
5276 cpumMsrRd_AmdFam14hIbsBrTarget,
5277
5278 cpumMsrRd_Gim
5279};
5280
5281
5282/**
5283 * MSR write function table.
5284 */
5285static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
5286{
5287 NULL, /* Invalid */
5288 cpumMsrWr_IgnoreWrite,
5289 cpumMsrWr_ReadOnly,
5290 NULL, /* Alias */
5291 cpumMsrWr_Ia32P5McAddr,
5292 cpumMsrWr_Ia32P5McType,
5293 cpumMsrWr_Ia32TimestampCounter,
5294 cpumMsrWr_Ia32ApicBase,
5295 cpumMsrWr_Ia32FeatureControl,
5296 cpumMsrWr_Ia32BiosSignId,
5297 cpumMsrWr_Ia32BiosUpdateTrigger,
5298 cpumMsrWr_Ia32SmmMonitorCtl,
5299 cpumMsrWr_Ia32PmcN,
5300 cpumMsrWr_Ia32MonitorFilterLineSize,
5301 cpumMsrWr_Ia32MPerf,
5302 cpumMsrWr_Ia32APerf,
5303 cpumMsrWr_Ia32MtrrPhysBaseN,
5304 cpumMsrWr_Ia32MtrrPhysMaskN,
5305 cpumMsrWr_Ia32MtrrFixed,
5306 cpumMsrWr_Ia32MtrrDefType,
5307 cpumMsrWr_Ia32Pat,
5308 cpumMsrWr_Ia32SysEnterCs,
5309 cpumMsrWr_Ia32SysEnterEsp,
5310 cpumMsrWr_Ia32SysEnterEip,
5311 cpumMsrWr_Ia32McgStatus,
5312 cpumMsrWr_Ia32McgCtl,
5313 cpumMsrWr_Ia32DebugCtl,
5314 cpumMsrWr_Ia32SmrrPhysBase,
5315 cpumMsrWr_Ia32SmrrPhysMask,
5316 cpumMsrWr_Ia32PlatformDcaCap,
5317 cpumMsrWr_Ia32Dca0Cap,
5318 cpumMsrWr_Ia32PerfEvtSelN,
5319 cpumMsrWr_Ia32PerfStatus,
5320 cpumMsrWr_Ia32PerfCtl,
5321 cpumMsrWr_Ia32FixedCtrN,
5322 cpumMsrWr_Ia32PerfCapabilities,
5323 cpumMsrWr_Ia32FixedCtrCtrl,
5324 cpumMsrWr_Ia32PerfGlobalStatus,
5325 cpumMsrWr_Ia32PerfGlobalCtrl,
5326 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
5327 cpumMsrWr_Ia32PebsEnable,
5328 cpumMsrWr_Ia32ClockModulation,
5329 cpumMsrWr_Ia32ThermInterrupt,
5330 cpumMsrWr_Ia32ThermStatus,
5331 cpumMsrWr_Ia32Therm2Ctl,
5332 cpumMsrWr_Ia32MiscEnable,
5333 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
5334 cpumMsrWr_Ia32McNCtl2,
5335 cpumMsrWr_Ia32DsArea,
5336 cpumMsrWr_Ia32TscDeadline,
5337 cpumMsrWr_Ia32X2ApicN,
5338 cpumMsrWr_Ia32DebugInterface,
5339 cpumMsrWr_Ia32SpecCtrl,
5340 cpumMsrWr_Ia32PredCmd,
5341 cpumMsrWr_Ia32FlushCmd,
5342
5343 cpumMsrWr_Amd64Efer,
5344 cpumMsrWr_Amd64SyscallTarget,
5345 cpumMsrWr_Amd64LongSyscallTarget,
5346 cpumMsrWr_Amd64CompSyscallTarget,
5347 cpumMsrWr_Amd64SyscallFlagMask,
5348 cpumMsrWr_Amd64FsBase,
5349 cpumMsrWr_Amd64GsBase,
5350 cpumMsrWr_Amd64KernelGsBase,
5351 cpumMsrWr_Amd64TscAux,
5352
5353 cpumMsrWr_IntelEblCrPowerOn,
5354 cpumMsrWr_IntelP4EbcHardPowerOn,
5355 cpumMsrWr_IntelP4EbcSoftPowerOn,
5356 cpumMsrWr_IntelP4EbcFrequencyId,
5357 cpumMsrWr_IntelFlexRatio,
5358 cpumMsrWr_IntelPkgCStConfigControl,
5359 cpumMsrWr_IntelPmgIoCaptureBase,
5360 cpumMsrWr_IntelLastBranchFromToN,
5361 cpumMsrWr_IntelLastBranchFromN,
5362 cpumMsrWr_IntelLastBranchToN,
5363 cpumMsrWr_IntelLastBranchTos,
5364 cpumMsrWr_IntelBblCrCtl,
5365 cpumMsrWr_IntelBblCrCtl3,
5366 cpumMsrWr_IntelI7TemperatureTarget,
5367 cpumMsrWr_IntelI7MsrOffCoreResponseN,
5368 cpumMsrWr_IntelI7MiscPwrMgmt,
5369 cpumMsrWr_IntelP6CrN,
5370 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
5371 cpumMsrWr_IntelCpuId1FeatureMaskEax,
5372 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
5373 cpumMsrWr_IntelI7SandyAesNiCtl,
5374 cpumMsrWr_IntelI7TurboRatioLimit,
5375 cpumMsrWr_IntelI7LbrSelect,
5376 cpumMsrWr_IntelI7SandyErrorControl,
5377 cpumMsrWr_IntelI7PowerCtl,
5378 cpumMsrWr_IntelI7SandyPebsNumAlt,
5379 cpumMsrWr_IntelI7PebsLdLat,
5380 cpumMsrWr_IntelI7SandyVrCurrentConfig,
5381 cpumMsrWr_IntelI7SandyVrMiscConfig,
5382 cpumMsrWr_IntelI7SandyRaplPowerUnit,
5383 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
5384 cpumMsrWr_IntelI7SandyPkgC2Residency,
5385 cpumMsrWr_IntelI7RaplPkgPowerLimit,
5386 cpumMsrWr_IntelI7RaplDramPowerLimit,
5387 cpumMsrWr_IntelI7RaplPp0PowerLimit,
5388 cpumMsrWr_IntelI7RaplPp0Policy,
5389 cpumMsrWr_IntelI7RaplPp1PowerLimit,
5390 cpumMsrWr_IntelI7RaplPp1Policy,
5391 cpumMsrWr_IntelI7IvyConfigTdpControl,
5392 cpumMsrWr_IntelI7IvyTurboActivationRatio,
5393 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
5394 cpumMsrWr_IntelI7UncPerfGlobalStatus,
5395 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
5396 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
5397 cpumMsrWr_IntelI7UncPerfFixedCtr,
5398 cpumMsrWr_IntelI7UncArbPerfCtrN,
5399 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
5400 cpumMsrWr_IntelCore2EmttmCrTablesN,
5401 cpumMsrWr_IntelCore2SmmCStMiscInfo,
5402 cpumMsrWr_IntelCore1ExtConfig,
5403 cpumMsrWr_IntelCore1DtsCalControl,
5404 cpumMsrWr_IntelCore2PeciControl,
5405
5406 cpumMsrWr_P6LastIntFromIp,
5407 cpumMsrWr_P6LastIntToIp,
5408
5409 cpumMsrWr_AmdFam15hTscRate,
5410 cpumMsrWr_AmdFam15hLwpCfg,
5411 cpumMsrWr_AmdFam15hLwpCbAddr,
5412 cpumMsrWr_AmdFam10hMc4MiscN,
5413 cpumMsrWr_AmdK8PerfCtlN,
5414 cpumMsrWr_AmdK8PerfCtrN,
5415 cpumMsrWr_AmdK8SysCfg,
5416 cpumMsrWr_AmdK8HwCr,
5417 cpumMsrWr_AmdK8IorrBaseN,
5418 cpumMsrWr_AmdK8IorrMaskN,
5419 cpumMsrWr_AmdK8TopOfMemN,
5420 cpumMsrWr_AmdK8NbCfg1,
5421 cpumMsrWr_AmdK8McXcptRedir,
5422 cpumMsrWr_AmdK8CpuNameN,
5423 cpumMsrWr_AmdK8HwThermalCtrl,
5424 cpumMsrWr_AmdK8SwThermalCtrl,
5425 cpumMsrWr_AmdK8FidVidControl,
5426 cpumMsrWr_AmdK8McCtlMaskN,
5427 cpumMsrWr_AmdK8SmiOnIoTrapN,
5428 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
5429 cpumMsrWr_AmdK8IntPendingMessage,
5430 cpumMsrWr_AmdK8SmiTriggerIoCycle,
5431 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
5432 cpumMsrWr_AmdFam10hTrapCtlMaybe,
5433 cpumMsrWr_AmdFam10hPStateControl,
5434 cpumMsrWr_AmdFam10hPStateStatus,
5435 cpumMsrWr_AmdFam10hPStateN,
5436 cpumMsrWr_AmdFam10hCofVidControl,
5437 cpumMsrWr_AmdFam10hCofVidStatus,
5438 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
5439 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
5440 cpumMsrWr_AmdK8SmmBase,
5441 cpumMsrWr_AmdK8SmmAddr,
5442 cpumMsrWr_AmdK8SmmMask,
5443 cpumMsrWr_AmdK8VmCr,
5444 cpumMsrWr_AmdK8IgnNe,
5445 cpumMsrWr_AmdK8SmmCtl,
5446 cpumMsrWr_AmdK8VmHSavePa,
5447 cpumMsrWr_AmdFam10hVmLockKey,
5448 cpumMsrWr_AmdFam10hSmmLockKey,
5449 cpumMsrWr_AmdFam10hLocalSmiStatus,
5450 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
5451 cpumMsrWr_AmdFam10hOsVisWrkStatus,
5452 cpumMsrWr_AmdFam16hL2IPerfCtlN,
5453 cpumMsrWr_AmdFam16hL2IPerfCtrN,
5454 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
5455 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
5456 cpumMsrWr_AmdK7MicrocodeCtl,
5457 cpumMsrWr_AmdK7ClusterIdMaybe,
5458 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
5459 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
5460 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
5461 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
5462 cpumMsrWr_AmdK8PatchLoader,
5463 cpumMsrWr_AmdK7DebugStatusMaybe,
5464 cpumMsrWr_AmdK7BHTraceBaseMaybe,
5465 cpumMsrWr_AmdK7BHTracePtrMaybe,
5466 cpumMsrWr_AmdK7BHTraceLimitMaybe,
5467 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
5468 cpumMsrWr_AmdK7FastFlushCountMaybe,
5469 cpumMsrWr_AmdK7NodeId,
5470 cpumMsrWr_AmdK7DrXAddrMaskN,
5471 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
5472 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
5473 cpumMsrWr_AmdK7LoadStoreCfg,
5474 cpumMsrWr_AmdK7InstrCacheCfg,
5475 cpumMsrWr_AmdK7DataCacheCfg,
5476 cpumMsrWr_AmdK7BusUnitCfg,
5477 cpumMsrWr_AmdK7DebugCtl2Maybe,
5478 cpumMsrWr_AmdFam15hFpuCfg,
5479 cpumMsrWr_AmdFam15hDecoderCfg,
5480 cpumMsrWr_AmdFam10hBusUnitCfg2,
5481 cpumMsrWr_AmdFam15hCombUnitCfg,
5482 cpumMsrWr_AmdFam15hCombUnitCfg2,
5483 cpumMsrWr_AmdFam15hCombUnitCfg3,
5484 cpumMsrWr_AmdFam15hExecUnitCfg,
5485 cpumMsrWr_AmdFam15hLoadStoreCfg2,
5486 cpumMsrWr_AmdFam10hIbsFetchCtl,
5487 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
5488 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
5489 cpumMsrWr_AmdFam10hIbsOpExecCtl,
5490 cpumMsrWr_AmdFam10hIbsOpRip,
5491 cpumMsrWr_AmdFam10hIbsOpData,
5492 cpumMsrWr_AmdFam10hIbsOpData2,
5493 cpumMsrWr_AmdFam10hIbsOpData3,
5494 cpumMsrWr_AmdFam10hIbsDcLinAddr,
5495 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
5496 cpumMsrWr_AmdFam10hIbsCtl,
5497 cpumMsrWr_AmdFam14hIbsBrTarget,
5498
5499 cpumMsrWr_Gim
5500};
5501
5502
5503/**
5504 * Looks up the range for the given MSR.
5505 *
5506 * @returns Pointer to the range if found, NULL if not.
5507 * @param pVM The cross context VM structure.
5508 * @param idMsr The MSR to look up.
5509 */
5510# ifndef IN_RING3
5511static
5512# endif
5513PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
5514{
5515 /*
5516 * Binary lookup.
5517 */
5518 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
5519 if (!cRanges)
5520 return NULL;
5521 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5522 for (;;)
5523 {
5524 uint32_t i = cRanges / 2;
5525 if (idMsr < paRanges[i].uFirst)
5526 {
5527 if (i == 0)
5528 break;
5529 cRanges = i;
5530 }
5531 else if (idMsr > paRanges[i].uLast)
5532 {
5533 i++;
5534 if (i >= cRanges)
5535 break;
5536 cRanges -= i;
5537 paRanges = &paRanges[i];
5538 }
5539 else
5540 {
5541 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
5542 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
5543 return &paRanges[i];
5544 }
5545 }
5546
5547# ifdef VBOX_STRICT
5548 /*
5549 * Linear lookup to verify the above binary search.
5550 */
5551 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
5552 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5553 while (cLeft-- > 0)
5554 {
5555 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
5556 {
5557 AssertFailed();
5558 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
5559 return cpumLookupMsrRange(pVM, pCur->uValue);
5560 return pCur;
5561 }
5562 pCur++;
5563 }
5564# endif
5565 return NULL;
5566}
5567
5568
5569/**
5570 * Query a guest MSR.
5571 *
5572 * The caller is responsible for checking privilege if the call is the result of
5573 * a RDMSR instruction. We'll do the rest.
5574 *
5575 * @retval VINF_SUCCESS on success.
5576 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
5577 * current context (raw-mode or ring-0).
5578 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
5579 * expected to take the appropriate actions. @a *puValue is set to 0.
5580 * @param pVCpu The cross context virtual CPU structure.
5581 * @param idMsr The MSR.
5582 * @param puValue Where to return the value.
5583 *
5584 * @remarks This will always return the right values, even when we're in the
5585 * recompiler.
5586 */
5587VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue)
5588{
5589 *puValue = 0;
5590
5591 VBOXSTRICTRC rcStrict;
5592 PVM pVM = pVCpu->CTX_SUFF(pVM);
5593 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5594 if (pRange)
5595 {
5596 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
5597 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5598
5599 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
5600 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5601
5602 STAM_COUNTER_INC(&pRange->cReads);
5603 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5604
5605 rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5606 if (rcStrict == VINF_SUCCESS)
5607 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5608 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5609 {
5610 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5611 STAM_COUNTER_INC(&pRange->cGps);
5612 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5613 }
5614#ifndef IN_RING3
5615 else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5616 Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5617#endif
5618 else
5619 {
5620 Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5621 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5622 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5623 Assert(rcStrict != VERR_EM_INTERPRETER);
5624 }
5625 }
5626 else
5627 {
5628 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5629 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5630 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5631 rcStrict = VERR_CPUM_RAISE_GP_0;
5632 }
5633 return rcStrict;
5634}
5635
5636
5637/**
5638 * Writes to a guest MSR.
5639 *
5640 * The caller is responsible for checking privilege if the call is the result of
5641 * a WRMSR instruction. We'll do the rest.
5642 *
5643 * @retval VINF_SUCCESS on success.
5644 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5645 * current context (raw-mode or ring-0).
5646 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5647 * appropriate actions.
5648 *
5649 * @param pVCpu The cross context virtual CPU structure.
5650 * @param idMsr The MSR id.
5651 * @param uValue The value to set.
5652 *
5653 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5654 * by calling this method. This makes sure we have current values and
5655 * that we trigger all the right actions when something changes.
5656 *
5657 * For performance reasons, this actually isn't entirely true for some
5658 * MSRs when in HM mode. The code here and in HM must be aware of
5659 * this.
5660 */
5661VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue)
5662{
5663 VBOXSTRICTRC rcStrict;
5664 PVM pVM = pVCpu->CTX_SUFF(pVM);
5665 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5666 if (pRange)
5667 {
5668 STAM_COUNTER_INC(&pRange->cWrites);
5669 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5670
5671 if (!(uValue & pRange->fWrGpMask))
5672 {
5673 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5674 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5675
5676 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5677 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5678
5679 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5680 if (uValueAdjusted != uValue)
5681 {
5682 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5683 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5684 }
5685
5686 rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5687 if (rcStrict == VINF_SUCCESS)
5688 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5689 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5690 {
5691 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5692 STAM_COUNTER_INC(&pRange->cGps);
5693 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5694 }
5695#ifndef IN_RING3
5696 else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5697 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5698#endif
5699 else
5700 {
5701 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5702 idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5703 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5704 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5705 Assert(rcStrict != VERR_EM_INTERPRETER);
5706 }
5707 }
5708 else
5709 {
5710 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5711 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5712 STAM_COUNTER_INC(&pRange->cGps);
5713 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5714 rcStrict = VERR_CPUM_RAISE_GP_0;
5715 }
5716 }
5717 else
5718 {
5719 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5720 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5721 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5722 rcStrict = VERR_CPUM_RAISE_GP_0;
5723 }
5724 return rcStrict;
5725}
5726
5727
5728#if defined(VBOX_STRICT) && defined(IN_RING3)
5729/**
5730 * Performs some checks on the static data related to MSRs.
5731 *
5732 * @returns VINF_SUCCESS on success, error on failure.
5733 */
5734int cpumR3MsrStrictInitChecks(void)
5735{
5736#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5737 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5738#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5739 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5740
5741 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5742 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5743 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5744 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5745 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5746 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5747 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5748 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5749 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5750 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5751 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5752 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5753 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5754 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5755 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5756 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5757 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5758 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5759 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5760 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5761 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5762 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5763 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5764 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5765 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5766 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5767 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5768 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5769 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5770 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5771 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5772 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5773 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5774 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5775 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5776 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5777 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5778 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5779 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5780 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5781 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5782 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5783 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5784 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5785 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5786 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5787 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5788 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5789 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5790 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5791 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5792 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5793 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5794 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBasic);
5795 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5796 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5797 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5798 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5799 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5800 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5801 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5802 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5803 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5804 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5805 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5806 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5807 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5808 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5809 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5810 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5811 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc);
5812 CPUM_ASSERT_RD_MSR_FN(Ia32SpecCtrl);
5813 CPUM_ASSERT_RD_MSR_FN(Ia32ArchCapabilities);
5814
5815 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5816 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5817 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5818 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5819 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5820 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5821 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5822 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5823 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5824
5825 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5826 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5827 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5828 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5829 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5830 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5831 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5832 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5833 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5834 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5835 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5836 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5837 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5838 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5839 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5840 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5841 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5842 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5843 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5844 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5845 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5846 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5847 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5848 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5849 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5850 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5851 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5852 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5853 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5854 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5855 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5856 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5857 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5858 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5859 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5860 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5861 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5862 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5863 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5864 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5865 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5866 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5867 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5868 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5869 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5870 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5871 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5872 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5873 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5874 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5875 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5876 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5877 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5878 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5879 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5880 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5881 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5882 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5883 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5884 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5885 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5886 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5887 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5888 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5889 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5890 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5891 CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount);
5892 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5893 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5894 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5895 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5896 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5897 CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency);
5898
5899 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5900 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5901 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5902 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5903
5904 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5905 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5906 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5907 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5908 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5909 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5910 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5911 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5912 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5913 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5914 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5915 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5916 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5917 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5918 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5919 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5920 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5921 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5922 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5923 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5924 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5925 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5926 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5927 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5928 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5929 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5930 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5931 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5932 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5933 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5934 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5935 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5936 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5937 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5938 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5939 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5940 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5941 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5942 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5943 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5944 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5945 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5946 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5947 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5948 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5949 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5950 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5951 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5952 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5953 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5954 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5955 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5956 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5957 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5958 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5959 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5960 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5961 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5962 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5963 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5964 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5965 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5966 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5967 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5968 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5969 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5970 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5971 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5972 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5973 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5974 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5975 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5976 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5977 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5978 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5979 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5980 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5981 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5982 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5983 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5984 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5985 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5986 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5987 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5988 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5989 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5990 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5991 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5992 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5993 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5994 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5995
5996 CPUM_ASSERT_RD_MSR_FN(Gim)
5997
5998 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5999 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
6000 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
6001 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
6002 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
6003 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
6004 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
6005 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
6006 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
6007 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
6008 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
6009 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
6010 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
6011 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
6012 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
6013 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
6014 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
6015 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
6016 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
6017 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
6018 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
6019 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
6020 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
6021 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
6022 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
6023 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
6024 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
6025 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
6026 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
6027 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
6028 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
6029 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
6030 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
6031 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
6032 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
6033 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
6034 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
6035 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
6036 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
6037 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
6038 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
6039 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
6040 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
6041 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
6042 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
6043 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
6044 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
6045 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
6046 CPUM_ASSERT_WR_MSR_FN(Ia32SpecCtrl);
6047 CPUM_ASSERT_WR_MSR_FN(Ia32PredCmd);
6048 CPUM_ASSERT_WR_MSR_FN(Ia32FlushCmd);
6049
6050 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
6051 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
6052 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
6053 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
6054 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
6055 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
6056 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
6057 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
6058 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
6059
6060 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
6061 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
6062 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
6063 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
6064 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
6065 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
6066 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
6067 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
6068 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
6069 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
6070 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
6071 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
6072 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
6073 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
6074 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
6075 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
6076 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
6077 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6078 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
6079 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6080 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
6081 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
6082 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
6083 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
6084 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
6085 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
6086 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
6087 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
6088 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
6089 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
6090 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency);
6091 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
6092 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
6093 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
6094 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
6095 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
6096 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
6097 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
6098 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
6099 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
6100 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
6101 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6102 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6103 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
6104 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
6105 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
6106 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
6107 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
6108 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
6109 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
6110 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
6111
6112 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
6113 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
6114
6115 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
6116 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
6117 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
6118 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
6119 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
6120 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
6121 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
6122 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
6123 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
6124 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
6125 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
6126 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
6127 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
6128 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
6129 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
6130 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
6131 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
6132 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
6133 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
6134 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6135 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
6136 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
6137 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6138 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
6139 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
6140 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
6141 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
6142 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
6143 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
6144 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
6145 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
6146 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
6147 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
6148 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
6149 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
6150 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
6151 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
6152 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
6153 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
6154 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
6155 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
6156 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
6157 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
6158 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
6159 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
6160 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6161 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6162 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
6163 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
6164 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6165 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6166 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6167 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6168 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
6169 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
6170 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
6171 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
6172 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
6173 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6174 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
6175 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
6176 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
6177 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
6178 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
6179 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
6180 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
6181 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
6182 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
6183 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
6184 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
6185 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
6186 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
6187 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
6188 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
6189 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
6190 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
6191 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
6192 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
6193 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
6194 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6195 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
6196 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
6197 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
6198 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
6199 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
6200 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
6201 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
6202 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
6203 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
6204
6205 CPUM_ASSERT_WR_MSR_FN(Gim);
6206
6207 return VINF_SUCCESS;
6208}
6209#endif /* VBOX_STRICT && IN_RING3 */
6210
6211
6212/**
6213 * Gets the scalable bus frequency.
6214 *
6215 * The bus frequency is used as a base in several MSRs that gives the CPU and
6216 * other frequency ratios.
6217 *
6218 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
6219 * @param pVM The cross context VM structure.
6220 */
6221VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
6222{
6223 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
6224 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
6225 uFreq = CPUM_SBUSFREQ_100MHZ;
6226 return uFreq;
6227}
6228
6229
6230/**
6231 * Sets the guest EFER MSR without performing any additional checks.
6232 *
6233 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6234 * @param uOldEfer The previous EFER MSR value.
6235 * @param uValidEfer The new, validated EFER MSR value.
6236 *
6237 * @remarks One would normally call CPUMIsGuestEferMsrWriteValid() before calling
6238 * this function to change the EFER in order to perform an EFER transition.
6239 */
6240VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer)
6241{
6242 pVCpu->cpum.s.Guest.msrEFER = uValidEfer;
6243
6244 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
6245 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
6246 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
6247 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
6248 {
6249 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
6250 HMFlushTlb(pVCpu);
6251
6252 /* Notify PGM about NXE changes. */
6253 if ( (uOldEfer & MSR_K6_EFER_NXE)
6254 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
6255 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
6256 }
6257}
6258
6259
6260/**
6261 * Checks if a guest PAT MSR write is valid.
6262 *
6263 * @returns @c true if the PAT bit combination is valid, @c false otherwise.
6264 * @param uValue The PAT MSR value.
6265 */
6266VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue)
6267{
6268 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
6269 {
6270 /* Check all eight bits because the top 5 bits of each byte are reserved. */
6271 uint8_t uType = (uint8_t)(uValue >> cShift);
6272 if ((uType >= 8) || (uType == 2) || (uType == 3))
6273 {
6274 Log(("CPUM: Invalid PAT type at %u:%u in IA32_PAT: %#llx (%#llx)\n", cShift + 7, cShift, uValue, uType));
6275 return false;
6276 }
6277 }
6278 return true;
6279}
6280
6281
6282/**
6283 * Validates an EFER MSR write and provides the new, validated EFER MSR.
6284 *
6285 * @returns VBox status code.
6286 * @param pVM The cross context VM structure.
6287 * @param uCr0 The CR0 of the CPU corresponding to the EFER MSR.
6288 * @param uOldEfer Value of the previous EFER MSR on the CPU if any.
6289 * @param uNewEfer The new EFER MSR value being written.
6290 * @param puValidEfer Where to store the validated EFER (only updated if
6291 * this function returns VINF_SUCCESS).
6292 */
6293VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer, uint64_t *puValidEfer)
6294{
6295 /* #GP(0) If anything outside the allowed bits is set. */
6296 uint64_t fMask = CPUMGetGuestEferMsrValidMask(pVM);
6297 if (uNewEfer & ~fMask)
6298 {
6299 Log(("CPUM: Settings disallowed EFER bit. uNewEfer=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uNewEfer, fMask));
6300 return VERR_CPUM_RAISE_GP_0;
6301 }
6302
6303 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
6304 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6305 if ( (uOldEfer & MSR_K6_EFER_LME) != (uNewEfer & MSR_K6_EFER_LME)
6306 && (uCr0 & X86_CR0_PG))
6307 {
6308 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
6309 return VERR_CPUM_RAISE_GP_0;
6310 }
6311
6312 /* There are a few more: e.g. MSR_K6_EFER_LMSLE. */
6313 AssertMsg(!(uNewEfer & ~( MSR_K6_EFER_NXE
6314 | MSR_K6_EFER_LME
6315 | MSR_K6_EFER_LMA /* ignored anyway */
6316 | MSR_K6_EFER_SCE
6317 | MSR_K6_EFER_FFXSR
6318 | MSR_K6_EFER_SVME)),
6319 ("Unexpected value %#RX64\n", uNewEfer));
6320
6321 /* Ignore EFER.LMA, it's updated when setting CR0. */
6322 fMask &= ~MSR_K6_EFER_LMA;
6323
6324 *puValidEfer = (uOldEfer & ~fMask) | (uNewEfer & fMask);
6325 return VINF_SUCCESS;
6326}
6327
6328
6329/**
6330 * Gets the mask of valid EFER bits depending on supported guest-CPU features.
6331 *
6332 * @returns Mask of valid EFER bits.
6333 * @param pVM The cross context VM structure.
6334 *
6335 * @remarks EFER.LMA is included as part of the valid mask. It's not invalid but
6336 * rather a read-only bit.
6337 */
6338VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM)
6339{
6340 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
6341 ? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
6342 : 0;
6343 uint64_t fMask = 0;
6344 uint64_t const fIgnoreMask = MSR_K6_EFER_LMA;
6345
6346 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
6347 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
6348 fMask |= MSR_K6_EFER_NXE;
6349 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
6350 fMask |= MSR_K6_EFER_LME;
6351 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
6352 fMask |= MSR_K6_EFER_SCE;
6353 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
6354 fMask |= MSR_K6_EFER_FFXSR;
6355 if (pVM->cpum.s.GuestFeatures.fSvm)
6356 fMask |= MSR_K6_EFER_SVME;
6357
6358 return (fIgnoreMask | fMask);
6359}
6360
6361
6362/**
6363 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6364 *
6365 * @returns The register value.
6366 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6367 * @thread EMT(pVCpu)
6368 */
6369VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu)
6370{
6371 Assert(!(pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_TSC_AUX));
6372 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
6373}
6374
6375
6376/**
6377 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6378 *
6379 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6380 * @param uValue The new value.
6381 * @thread EMT(pVCpu)
6382 */
6383VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue)
6384{
6385 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_TSC_AUX;
6386 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
6387}
6388
6389
6390/**
6391 * Fast way for HM to access the IA32_SPEC_CTRL register.
6392 *
6393 * @returns The register value.
6394 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6395 * @thread EMT(pVCpu)
6396 */
6397VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu)
6398{
6399 return pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
6400}
6401
6402
6403/**
6404 * Fast way for HM to access the IA32_SPEC_CTRL register.
6405 *
6406 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6407 * @param uValue The new value.
6408 * @thread EMT(pVCpu)
6409 */
6410VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue)
6411{
6412 pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
6413}
6414
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