VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 73257

Last change on this file since 73257 was 73257, checked in by vboxsync, 7 years ago

VMM: Nested VMX: bugref:9180 Renamed Ia32VmxBase to Ia32VmxBasic to match the Intel MSR name.
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File size: 234.6 KB
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1/* $Id: CPUMAllMsrs.cpp 73257 2018-07-20 08:33:28Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/apic.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/tm.h>
27#include <VBox/vmm/gim.h>
28#include "CPUMInternal.h"
29#include <VBox/vmm/vm.h>
30#include <VBox/err.h>
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36/**
37 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
38 * pointing to it.
39 *
40 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
41 * correctly.
42 */
43#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
44 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
45 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
46 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
47 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
48 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
49 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
50
51
52/*********************************************************************************************************************************
53* Structures and Typedefs *
54*********************************************************************************************************************************/
55
56/**
57 * Implements reading one or more MSRs.
58 *
59 * @returns VBox status code.
60 * @retval VINF_SUCCESS on success.
61 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
62 * current context (raw-mode or ring-0).
63 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
64 *
65 * @param pVCpu The cross context virtual CPU structure.
66 * @param idMsr The MSR we're reading.
67 * @param pRange The MSR range descriptor.
68 * @param puValue Where to return the value.
69 */
70typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
71/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
72typedef FNCPUMRDMSR *PFNCPUMRDMSR;
73
74
75/**
76 * Implements writing one or more MSRs.
77 *
78 * @retval VINF_SUCCESS on success.
79 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
80 * current context (raw-mode or ring-0).
81 * @retval VERR_CPUM_RAISE_GP_0 on failure.
82 *
83 * @param pVCpu The cross context virtual CPU structure.
84 * @param idMsr The MSR we're writing.
85 * @param pRange The MSR range descriptor.
86 * @param uValue The value to set, ignored bits masked.
87 * @param uRawValue The raw value with the ignored bits not masked.
88 */
89typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
90/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
91typedef FNCPUMWRMSR *PFNCPUMWRMSR;
92
93
94
95/*
96 * Generic functions.
97 * Generic functions.
98 * Generic functions.
99 */
100
101
102/** @callback_method_impl{FNCPUMRDMSR} */
103static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
104{
105 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
106 *puValue = pRange->uValue;
107 return VINF_SUCCESS;
108}
109
110
111/** @callback_method_impl{FNCPUMWRMSR} */
112static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
113{
114 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
115 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
116 return VINF_SUCCESS;
117}
118
119
120/** @callback_method_impl{FNCPUMRDMSR} */
121static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
122{
123 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
124 return VERR_CPUM_RAISE_GP_0;
125}
126
127
128/** @callback_method_impl{FNCPUMWRMSR} */
129static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
130{
131 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
132 Assert(pRange->fWrGpMask == UINT64_MAX);
133 return VERR_CPUM_RAISE_GP_0;
134}
135
136
137
138
139/*
140 * IA32
141 * IA32
142 * IA32
143 */
144
145/** @callback_method_impl{FNCPUMRDMSR} */
146static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
147{
148 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
149 *puValue = 0; /** @todo implement machine check injection. */
150 return VINF_SUCCESS;
151}
152
153
154/** @callback_method_impl{FNCPUMWRMSR} */
155static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
156{
157 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
158 /** @todo implement machine check injection. */
159 return VINF_SUCCESS;
160}
161
162
163/** @callback_method_impl{FNCPUMRDMSR} */
164static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
165{
166 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
167 *puValue = 0; /** @todo implement machine check injection. */
168 return VINF_SUCCESS;
169}
170
171
172/** @callback_method_impl{FNCPUMWRMSR} */
173static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
174{
175 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
176 /** @todo implement machine check injection. */
177 return VINF_SUCCESS;
178}
179
180
181/** @callback_method_impl{FNCPUMRDMSR} */
182static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
183{
184 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
185 *puValue = TMCpuTickGet(pVCpu);
186#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
187 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
188#endif
189 return VINF_SUCCESS;
190}
191
192
193/** @callback_method_impl{FNCPUMWRMSR} */
194static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
195{
196 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
197 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
198 return VINF_SUCCESS;
199}
200
201
202/** @callback_method_impl{FNCPUMRDMSR} */
203static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
204{
205 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
206 uint64_t uValue = pRange->uValue;
207 if (uValue & 0x1f00)
208 {
209 /* Max allowed bus ratio present. */
210 /** @todo Implement scaled BUS frequency. */
211 }
212
213 *puValue = uValue;
214 return VINF_SUCCESS;
215}
216
217
218/** @callback_method_impl{FNCPUMRDMSR} */
219static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
220{
221 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
222 return APICGetBaseMsr(pVCpu, puValue);
223}
224
225
226/** @callback_method_impl{FNCPUMWRMSR} */
227static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
228{
229 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
230 return APICSetBaseMsr(pVCpu, uValue);
231}
232
233
234/**
235 * Get fixed IA32_FEATURE_CONTROL value for NEM and cpumMsrRd_Ia32FeatureControl.
236 *
237 * @returns Fixed IA32_FEATURE_CONTROL value.
238 * @param pVCpu The cross context per CPU structure.
239 */
240VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatureControl(PVMCPU pVCpu)
241{
242 /* Always report the MSR lock bit as set, in order to prevent guests from modifiying this MSR. */
243 uint64_t fFeatCtl = MSR_IA32_FEATURE_CONTROL_LOCK;
244
245 /* Report VMX features. */
246 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
247 fFeatCtl |= MSR_IA32_FEATURE_CONTROL_VMXON;
248
249 return fFeatCtl;
250}
251
252/** @callback_method_impl{FNCPUMRDMSR} */
253static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
254{
255 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
256 *puValue = CPUMGetGuestIa32FeatureControl(pVCpu);
257 return VINF_SUCCESS;
258}
259
260
261/** @callback_method_impl{FNCPUMWRMSR} */
262static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
263{
264 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
265 return VERR_CPUM_RAISE_GP_0;
266}
267
268
269/** @callback_method_impl{FNCPUMRDMSR} */
270static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
271{
272 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
273 /** @todo fake microcode update. */
274 *puValue = pRange->uValue;
275 return VINF_SUCCESS;
276}
277
278
279/** @callback_method_impl{FNCPUMWRMSR} */
280static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
281{
282 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
283 /* Normally, zero is written to Ia32BiosSignId before reading it in order
284 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
285 of the database entry should take care of most illegal writes for now, so
286 just ignore all writes atm. */
287 return VINF_SUCCESS;
288}
289
290
291/** @callback_method_impl{FNCPUMWRMSR} */
292static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
293{
294 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
295 /** @todo Fake bios update trigger better. The value is the address to an
296 * update package, I think. We should probably GP if it's invalid. */
297 return VINF_SUCCESS;
298}
299
300
301/** @callback_method_impl{FNCPUMRDMSR} */
302static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
303{
304 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
305 /** @todo SMM. */
306 *puValue = 0;
307 return VINF_SUCCESS;
308}
309
310
311/** @callback_method_impl{FNCPUMWRMSR} */
312static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
313{
314 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
315 /** @todo SMM. */
316 return VINF_SUCCESS;
317}
318
319
320/** @callback_method_impl{FNCPUMRDMSR} */
321static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
322{
323 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
324 /** @todo check CPUID leaf 0ah. */
325 *puValue = 0;
326 return VINF_SUCCESS;
327}
328
329
330/** @callback_method_impl{FNCPUMWRMSR} */
331static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
332{
333 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
334 /** @todo check CPUID leaf 0ah. */
335 return VINF_SUCCESS;
336}
337
338
339/** @callback_method_impl{FNCPUMRDMSR} */
340static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
341{
342 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
343 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
344 *puValue = 0x40; /** @todo Change to CPU cache line size. */
345 return VINF_SUCCESS;
346}
347
348
349/** @callback_method_impl{FNCPUMWRMSR} */
350static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
351{
352 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
353 /** @todo should remember writes, though it's supposedly something only a BIOS
354 * would write so, it's not extremely important. */
355 return VINF_SUCCESS;
356}
357
358/** @callback_method_impl{FNCPUMRDMSR} */
359static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
360{
361 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
362 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
363 * what we want? */
364 *puValue = TMCpuTickGet(pVCpu);
365#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
366 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
367#endif
368 return VINF_SUCCESS;
369}
370
371
372/** @callback_method_impl{FNCPUMWRMSR} */
373static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
374{
375 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
376 /** @todo Write MPERF: Calc adjustment. */
377 return VINF_SUCCESS;
378}
379
380
381/** @callback_method_impl{FNCPUMRDMSR} */
382static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
383{
384 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
385 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
386 * what we want? */
387 *puValue = TMCpuTickGet(pVCpu);
388#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
389 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
390#endif
391 return VINF_SUCCESS;
392}
393
394
395/** @callback_method_impl{FNCPUMWRMSR} */
396static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
397{
398 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
399 /** @todo Write APERF: Calc adjustment. */
400 return VINF_SUCCESS;
401}
402
403
404/**
405 * Get fixed IA32_MTRR_CAP value for NEM and cpumMsrRd_Ia32MtrrCap.
406 *
407 * @returns Fixed IA32_MTRR_CAP value.
408 * @param pVCpu The cross context per CPU structure.
409 */
410VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PVMCPU pVCpu)
411{
412 RT_NOREF_PV(pVCpu);
413
414 /* This is currently a bit weird. :-) */
415 uint8_t const cVariableRangeRegs = 0;
416 bool const fSystemManagementRangeRegisters = false;
417 bool const fFixedRangeRegisters = false;
418 bool const fWriteCombiningType = false;
419 return cVariableRangeRegs
420 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
421 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
422 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
423}
424
425/** @callback_method_impl{FNCPUMRDMSR} */
426static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
427{
428 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
429 *puValue = CPUMGetGuestIa32MtrrCap(pVCpu);
430 return VINF_SUCCESS;
431}
432
433
434/** @callback_method_impl{FNCPUMRDMSR} */
435static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
436{
437 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
438 /** @todo Implement variable MTRR storage. */
439 Assert(pRange->uValue == (idMsr - 0x200) / 2);
440 *puValue = 0;
441 return VINF_SUCCESS;
442}
443
444
445/** @callback_method_impl{FNCPUMWRMSR} */
446static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
447{
448 /*
449 * Validate the value.
450 */
451 Assert(pRange->uValue == (idMsr - 0x200) / 2);
452 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
453
454 uint8_t uType = uValue & 0xff;
455 if ((uType >= 7) || (uType == 2) || (uType == 3))
456 {
457 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uType));
458 return VERR_CPUM_RAISE_GP_0;
459 }
460
461 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
462 if (fInvPhysMask & uValue)
463 {
464 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
465 idMsr, uValue, uValue & fInvPhysMask));
466 return VERR_CPUM_RAISE_GP_0;
467 }
468
469 /*
470 * Store it.
471 */
472 /** @todo Implement variable MTRR storage. */
473 return VINF_SUCCESS;
474}
475
476
477/** @callback_method_impl{FNCPUMRDMSR} */
478static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
479{
480 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
481 /** @todo Implement variable MTRR storage. */
482 Assert(pRange->uValue == (idMsr - 0x200) / 2);
483 *puValue = 0;
484 return VINF_SUCCESS;
485}
486
487
488/** @callback_method_impl{FNCPUMWRMSR} */
489static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
490{
491 /*
492 * Validate the value.
493 */
494 Assert(pRange->uValue == (idMsr - 0x200) / 2);
495 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
496
497 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
498 if (fInvPhysMask & uValue)
499 {
500 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
501 idMsr, uValue, uValue & fInvPhysMask));
502 return VERR_CPUM_RAISE_GP_0;
503 }
504
505 /*
506 * Store it.
507 */
508 /** @todo Implement variable MTRR storage. */
509 return VINF_SUCCESS;
510}
511
512
513/** @callback_method_impl{FNCPUMRDMSR} */
514static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
515{
516 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
517 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
518 *puValue = *puFixedMtrr;
519 return VINF_SUCCESS;
520}
521
522
523/** @callback_method_impl{FNCPUMWRMSR} */
524static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
525{
526 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
527 RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue);
528
529 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
530 {
531 uint8_t uType = (uint8_t)(uValue >> cShift);
532 if ((uType >= 7) || (uType == 2) || (uType == 3))
533 {
534 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
535 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
536 return VERR_CPUM_RAISE_GP_0;
537 }
538 }
539 *puFixedMtrr = uValue;
540 return VINF_SUCCESS;
541}
542
543
544/** @callback_method_impl{FNCPUMRDMSR} */
545static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
546{
547 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
548 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
549 return VINF_SUCCESS;
550}
551
552
553/** @callback_method_impl{FNCPUMWRMSR} */
554static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
555{
556 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
557
558 uint8_t uType = uValue & 0xff;
559 if ((uType >= 7) || (uType == 2) || (uType == 3))
560 {
561 Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uType));
562 return VERR_CPUM_RAISE_GP_0;
563 }
564
565 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
566 return VINF_SUCCESS;
567}
568
569
570/** @callback_method_impl{FNCPUMRDMSR} */
571static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
572{
573 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
574 *puValue = pVCpu->cpum.s.Guest.msrPAT;
575 return VINF_SUCCESS;
576}
577
578
579/** @callback_method_impl{FNCPUMWRMSR} */
580static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
581{
582 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
583 if (CPUMIsPatMsrValid(uValue))
584 {
585 pVCpu->cpum.s.Guest.msrPAT = uValue;
586 return VINF_SUCCESS;
587 }
588 return VERR_CPUM_RAISE_GP_0;
589}
590
591
592/** @callback_method_impl{FNCPUMRDMSR} */
593static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
594{
595 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
596 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
597 return VINF_SUCCESS;
598}
599
600
601/** @callback_method_impl{FNCPUMWRMSR} */
602static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
603{
604 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
605
606 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
607 there are generally 32-bit working bits backing this register. */
608 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
609 return VINF_SUCCESS;
610}
611
612
613/** @callback_method_impl{FNCPUMRDMSR} */
614static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
615{
616 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
617 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
618 return VINF_SUCCESS;
619}
620
621
622/** @callback_method_impl{FNCPUMWRMSR} */
623static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
624{
625 if (X86_IS_CANONICAL(uValue))
626 {
627 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
628 return VINF_SUCCESS;
629 }
630 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
631 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
632 return VERR_CPUM_RAISE_GP_0;
633}
634
635
636/** @callback_method_impl{FNCPUMRDMSR} */
637static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
638{
639 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
640 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
641 return VINF_SUCCESS;
642}
643
644
645/** @callback_method_impl{FNCPUMWRMSR} */
646static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
647{
648 if (X86_IS_CANONICAL(uValue))
649 {
650 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
651 return VINF_SUCCESS;
652 }
653 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
654 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
655 return VERR_CPUM_RAISE_GP_0;
656}
657
658
659/** @callback_method_impl{FNCPUMRDMSR} */
660static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
661{
662#if 0 /** @todo implement machine checks. */
663 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
664#else
665 *puValue = 0;
666#endif
667 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
668 return VINF_SUCCESS;
669}
670
671
672/** @callback_method_impl{FNCPUMRDMSR} */
673static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
674{
675 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
676 /** @todo implement machine checks. */
677 *puValue = 0;
678 return VINF_SUCCESS;
679}
680
681
682/** @callback_method_impl{FNCPUMWRMSR} */
683static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
684{
685 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
686 /** @todo implement machine checks. */
687 return VINF_SUCCESS;
688}
689
690
691/** @callback_method_impl{FNCPUMRDMSR} */
692static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
693{
694 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
695 /** @todo implement machine checks. */
696 *puValue = 0;
697 return VINF_SUCCESS;
698}
699
700
701/** @callback_method_impl{FNCPUMWRMSR} */
702static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
703{
704 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
705 /** @todo implement machine checks. */
706 return VINF_SUCCESS;
707}
708
709
710/** @callback_method_impl{FNCPUMRDMSR} */
711static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
712{
713 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
714 /** @todo implement IA32_DEBUGCTL. */
715 *puValue = 0;
716 return VINF_SUCCESS;
717}
718
719
720/** @callback_method_impl{FNCPUMWRMSR} */
721static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
722{
723 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
724 /** @todo implement IA32_DEBUGCTL. */
725 return VINF_SUCCESS;
726}
727
728
729/** @callback_method_impl{FNCPUMRDMSR} */
730static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
731{
732 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
733 /** @todo implement intel SMM. */
734 *puValue = 0;
735 return VINF_SUCCESS;
736}
737
738
739/** @callback_method_impl{FNCPUMWRMSR} */
740static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
741{
742 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
743 /** @todo implement intel SMM. */
744 return VERR_CPUM_RAISE_GP_0;
745}
746
747
748/** @callback_method_impl{FNCPUMRDMSR} */
749static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
750{
751 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
752 /** @todo implement intel SMM. */
753 *puValue = 0;
754 return VINF_SUCCESS;
755}
756
757
758/** @callback_method_impl{FNCPUMWRMSR} */
759static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
760{
761 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
762 /** @todo implement intel SMM. */
763 return VERR_CPUM_RAISE_GP_0;
764}
765
766
767/** @callback_method_impl{FNCPUMRDMSR} */
768static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
769{
770 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
771 /** @todo implement intel direct cache access (DCA)?? */
772 *puValue = 0;
773 return VINF_SUCCESS;
774}
775
776
777/** @callback_method_impl{FNCPUMWRMSR} */
778static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
779{
780 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
781 /** @todo implement intel direct cache access (DCA)?? */
782 return VINF_SUCCESS;
783}
784
785
786/** @callback_method_impl{FNCPUMRDMSR} */
787static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
788{
789 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
790 /** @todo implement intel direct cache access (DCA)?? */
791 *puValue = 0;
792 return VINF_SUCCESS;
793}
794
795
796/** @callback_method_impl{FNCPUMRDMSR} */
797static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
798{
799 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
800 /** @todo implement intel direct cache access (DCA)?? */
801 *puValue = 0;
802 return VINF_SUCCESS;
803}
804
805
806/** @callback_method_impl{FNCPUMWRMSR} */
807static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
808{
809 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
810 /** @todo implement intel direct cache access (DCA)?? */
811 return VINF_SUCCESS;
812}
813
814
815/** @callback_method_impl{FNCPUMRDMSR} */
816static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
817{
818 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
819 /** @todo implement IA32_PERFEVTSEL0+. */
820 *puValue = 0;
821 return VINF_SUCCESS;
822}
823
824
825/** @callback_method_impl{FNCPUMWRMSR} */
826static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
827{
828 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
829 /** @todo implement IA32_PERFEVTSEL0+. */
830 return VINF_SUCCESS;
831}
832
833
834/** @callback_method_impl{FNCPUMRDMSR} */
835static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
836{
837 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
838 uint64_t uValue = pRange->uValue;
839
840 /* Always provide the max bus ratio for now. XNU expects it. */
841 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
842
843 PVM pVM = pVCpu->CTX_SUFF(pVM);
844 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
845 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
846 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
847 if (uTscRatio > 0x1f)
848 uTscRatio = 0x1f;
849 uValue |= (uint64_t)uTscRatio << 40;
850
851 *puValue = uValue;
852 return VINF_SUCCESS;
853}
854
855
856/** @callback_method_impl{FNCPUMWRMSR} */
857static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
858{
859 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
860 /* Pentium4 allows writing, but all bits are ignored. */
861 return VINF_SUCCESS;
862}
863
864
865/** @callback_method_impl{FNCPUMRDMSR} */
866static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
867{
868 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
869 /** @todo implement IA32_PERFCTL. */
870 *puValue = 0;
871 return VINF_SUCCESS;
872}
873
874
875/** @callback_method_impl{FNCPUMWRMSR} */
876static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
877{
878 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
879 /** @todo implement IA32_PERFCTL. */
880 return VINF_SUCCESS;
881}
882
883
884/** @callback_method_impl{FNCPUMRDMSR} */
885static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
886{
887 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
888 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
889 *puValue = 0;
890 return VINF_SUCCESS;
891}
892
893
894/** @callback_method_impl{FNCPUMWRMSR} */
895static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
896{
897 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
898 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
899 return VINF_SUCCESS;
900}
901
902
903/** @callback_method_impl{FNCPUMRDMSR} */
904static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
905{
906 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
907 /** @todo implement performance counters. */
908 *puValue = 0;
909 return VINF_SUCCESS;
910}
911
912
913/** @callback_method_impl{FNCPUMWRMSR} */
914static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
915{
916 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
917 /** @todo implement performance counters. */
918 return VINF_SUCCESS;
919}
920
921
922/** @callback_method_impl{FNCPUMRDMSR} */
923static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
924{
925 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
926 /** @todo implement performance counters. */
927 *puValue = 0;
928 return VINF_SUCCESS;
929}
930
931
932/** @callback_method_impl{FNCPUMWRMSR} */
933static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
934{
935 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
936 /** @todo implement performance counters. */
937 return VINF_SUCCESS;
938}
939
940
941/** @callback_method_impl{FNCPUMRDMSR} */
942static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
943{
944 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
945 /** @todo implement performance counters. */
946 *puValue = 0;
947 return VINF_SUCCESS;
948}
949
950
951/** @callback_method_impl{FNCPUMWRMSR} */
952static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
953{
954 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
955 /** @todo implement performance counters. */
956 return VINF_SUCCESS;
957}
958
959
960/** @callback_method_impl{FNCPUMRDMSR} */
961static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
962{
963 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
964 /** @todo implement performance counters. */
965 *puValue = 0;
966 return VINF_SUCCESS;
967}
968
969
970/** @callback_method_impl{FNCPUMWRMSR} */
971static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
972{
973 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
974 /** @todo implement performance counters. */
975 return VINF_SUCCESS;
976}
977
978
979/** @callback_method_impl{FNCPUMRDMSR} */
980static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
981{
982 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
983 /** @todo implement performance counters. */
984 *puValue = 0;
985 return VINF_SUCCESS;
986}
987
988
989/** @callback_method_impl{FNCPUMWRMSR} */
990static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
991{
992 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
993 /** @todo implement performance counters. */
994 return VINF_SUCCESS;
995}
996
997
998/** @callback_method_impl{FNCPUMRDMSR} */
999static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1000{
1001 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1002 /** @todo implement performance counters. */
1003 *puValue = 0;
1004 return VINF_SUCCESS;
1005}
1006
1007
1008/** @callback_method_impl{FNCPUMWRMSR} */
1009static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1010{
1011 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1012 /** @todo implement performance counters. */
1013 return VINF_SUCCESS;
1014}
1015
1016
1017/** @callback_method_impl{FNCPUMRDMSR} */
1018static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1019{
1020 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1021 /** @todo implement IA32_CLOCK_MODULATION. */
1022 *puValue = 0;
1023 return VINF_SUCCESS;
1024}
1025
1026
1027/** @callback_method_impl{FNCPUMWRMSR} */
1028static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1029{
1030 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1031 /** @todo implement IA32_CLOCK_MODULATION. */
1032 return VINF_SUCCESS;
1033}
1034
1035
1036/** @callback_method_impl{FNCPUMRDMSR} */
1037static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1038{
1039 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1040 /** @todo implement IA32_THERM_INTERRUPT. */
1041 *puValue = 0;
1042 return VINF_SUCCESS;
1043}
1044
1045
1046/** @callback_method_impl{FNCPUMWRMSR} */
1047static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1048{
1049 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1050 /** @todo implement IA32_THERM_STATUS. */
1051 return VINF_SUCCESS;
1052}
1053
1054
1055/** @callback_method_impl{FNCPUMRDMSR} */
1056static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1057{
1058 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1059 /** @todo implement IA32_THERM_STATUS. */
1060 *puValue = 0;
1061 return VINF_SUCCESS;
1062}
1063
1064
1065/** @callback_method_impl{FNCPUMWRMSR} */
1066static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1067{
1068 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1069 /** @todo implement IA32_THERM_INTERRUPT. */
1070 return VINF_SUCCESS;
1071}
1072
1073
1074/** @callback_method_impl{FNCPUMRDMSR} */
1075static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1076{
1077 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1078 /** @todo implement IA32_THERM2_CTL. */
1079 *puValue = 0;
1080 return VINF_SUCCESS;
1081}
1082
1083
1084/** @callback_method_impl{FNCPUMWRMSR} */
1085static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1086{
1087 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1088 /** @todo implement IA32_THERM2_CTL. */
1089 return VINF_SUCCESS;
1090}
1091
1092
1093/** @callback_method_impl{FNCPUMRDMSR} */
1094static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1095{
1096 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1097 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1098 return VINF_SUCCESS;
1099}
1100
1101
1102/** @callback_method_impl{FNCPUMWRMSR} */
1103static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1104{
1105 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1106#ifdef LOG_ENABLED
1107 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1108#endif
1109
1110 /* Unsupported bits are generally ignored and stripped by the MSR range
1111 entry that got us here. So, we just need to preserve fixed bits. */
1112 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
1113 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1114 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
1115
1116 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
1117 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
1118
1119 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1120 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1121 return VINF_SUCCESS;
1122}
1123
1124
1125/** @callback_method_impl{FNCPUMRDMSR} */
1126static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1127{
1128 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange);
1129
1130 /** @todo Implement machine check exception injection. */
1131 switch (idMsr & 3)
1132 {
1133 case 0:
1134 case 1:
1135 *puValue = 0;
1136 break;
1137
1138 /* The ADDR and MISC registers aren't accessible since the
1139 corresponding STATUS bits are zero. */
1140 case 2:
1141 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1142 return VERR_CPUM_RAISE_GP_0;
1143 case 3:
1144 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1145 return VERR_CPUM_RAISE_GP_0;
1146 }
1147 return VINF_SUCCESS;
1148}
1149
1150
1151/** @callback_method_impl{FNCPUMWRMSR} */
1152static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1153{
1154 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1155 switch (idMsr & 3)
1156 {
1157 case 0:
1158 /* Ignore writes to the CTL register. */
1159 break;
1160
1161 case 1:
1162 /* According to specs, the STATUS register can only be written to
1163 with the value 0. VBoxCpuReport thinks different for a
1164 Pentium M Dothan, but implementing according to specs now. */
1165 if (uValue != 0)
1166 {
1167 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1168 return VERR_CPUM_RAISE_GP_0;
1169 }
1170 break;
1171
1172 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1173 Writing 1s will GP. Need to figure out how this relates to the
1174 ADDRV and MISCV status flags. If writing is independent of those
1175 bits, we need to know whether the CPU really implements them since
1176 that is exposed by writing 0 to them.
1177 Implementing the solution with the fewer GPs for now. */
1178 case 2:
1179 if (uValue != 0)
1180 {
1181 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1182 return VERR_CPUM_RAISE_GP_0;
1183 }
1184 break;
1185 case 3:
1186 if (uValue != 0)
1187 {
1188 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1189 return VERR_CPUM_RAISE_GP_0;
1190 }
1191 break;
1192 }
1193 return VINF_SUCCESS;
1194}
1195
1196
1197/** @callback_method_impl{FNCPUMRDMSR} */
1198static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1199{
1200 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1201 /** @todo Implement machine check exception injection. */
1202 *puValue = 0;
1203 return VINF_SUCCESS;
1204}
1205
1206
1207/** @callback_method_impl{FNCPUMWRMSR} */
1208static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1209{
1210 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1211 /** @todo Implement machine check exception injection. */
1212 return VINF_SUCCESS;
1213}
1214
1215
1216/** @callback_method_impl{FNCPUMRDMSR} */
1217static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1218{
1219 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1220 /** @todo implement IA32_DS_AREA. */
1221 *puValue = 0;
1222 return VINF_SUCCESS;
1223}
1224
1225
1226/** @callback_method_impl{FNCPUMWRMSR} */
1227static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1228{
1229 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1230 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1231 return VINF_SUCCESS;
1232}
1233
1234
1235/** @callback_method_impl{FNCPUMRDMSR} */
1236static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1237{
1238 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1239 /** @todo implement TSC deadline timer. */
1240 *puValue = 0;
1241 return VINF_SUCCESS;
1242}
1243
1244
1245/** @callback_method_impl{FNCPUMWRMSR} */
1246static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1247{
1248 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1249 /** @todo implement TSC deadline timer. */
1250 return VINF_SUCCESS;
1251}
1252
1253
1254/** @callback_method_impl{FNCPUMRDMSR} */
1255static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1256{
1257 RT_NOREF_PV(pRange);
1258 return APICReadMsr(pVCpu, idMsr, puValue);
1259}
1260
1261
1262/** @callback_method_impl{FNCPUMWRMSR} */
1263static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1264{
1265 RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1266 return APICWriteMsr(pVCpu, idMsr, uValue);
1267}
1268
1269
1270/** @callback_method_impl{FNCPUMRDMSR} */
1271static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1272{
1273 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1274 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1275 *puValue = 0;
1276 return VINF_SUCCESS;
1277}
1278
1279
1280/** @callback_method_impl{FNCPUMWRMSR} */
1281static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1282{
1283 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1284 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1285 return VINF_SUCCESS;
1286}
1287
1288
1289/** @callback_method_impl{FNCPUMRDMSR} */
1290static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBasic(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1291{
1292 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1293 *puValue = 0;
1294 return VINF_SUCCESS;
1295}
1296
1297
1298/** @callback_method_impl{FNCPUMRDMSR} */
1299static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1300{
1301 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1302 *puValue = 0;
1303 return VINF_SUCCESS;
1304}
1305
1306
1307/** @callback_method_impl{FNCPUMRDMSR} */
1308static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1309{
1310 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1311 *puValue = 0;
1312 return VINF_SUCCESS;
1313}
1314
1315
1316/** @callback_method_impl{FNCPUMRDMSR} */
1317static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1318{
1319 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1320 *puValue = 0;
1321 return VINF_SUCCESS;
1322}
1323
1324
1325/** @callback_method_impl{FNCPUMRDMSR} */
1326static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1327{
1328 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1329 *puValue = 0;
1330 return VINF_SUCCESS;
1331}
1332
1333
1334/** @callback_method_impl{FNCPUMRDMSR} */
1335static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1336{
1337 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1338 *puValue = 0;
1339 return VINF_SUCCESS;
1340}
1341
1342
1343/** @callback_method_impl{FNCPUMRDMSR} */
1344static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1345{
1346 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1347 *puValue = 0;
1348 return VINF_SUCCESS;
1349}
1350
1351
1352/** @callback_method_impl{FNCPUMRDMSR} */
1353static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1354{
1355 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1356 *puValue = 0;
1357 return VINF_SUCCESS;
1358}
1359
1360
1361/** @callback_method_impl{FNCPUMRDMSR} */
1362static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1363{
1364 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1365 *puValue = 0;
1366 return VINF_SUCCESS;
1367}
1368
1369
1370/** @callback_method_impl{FNCPUMRDMSR} */
1371static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1372{
1373 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1374 *puValue = 0;
1375 return VINF_SUCCESS;
1376}
1377
1378
1379/** @callback_method_impl{FNCPUMRDMSR} */
1380static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1381{
1382 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1383 *puValue = 0;
1384 return VINF_SUCCESS;
1385}
1386
1387
1388/** @callback_method_impl{FNCPUMRDMSR} */
1389static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1390{
1391 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1392 *puValue = 0;
1393 return VINF_SUCCESS;
1394}
1395
1396
1397/** @callback_method_impl{FNCPUMRDMSR} */
1398static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1399{
1400 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1401 *puValue = 0;
1402 return VINF_SUCCESS;
1403}
1404
1405
1406/** @callback_method_impl{FNCPUMRDMSR} */
1407static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1408{
1409 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1410 *puValue = 0;
1411 return VINF_SUCCESS;
1412}
1413
1414
1415/** @callback_method_impl{FNCPUMRDMSR} */
1416static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1417{
1418 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1419 *puValue = 0;
1420 return VINF_SUCCESS;
1421}
1422
1423
1424/** @callback_method_impl{FNCPUMRDMSR} */
1425static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1426{
1427 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1428 *puValue = 0;
1429 return VINF_SUCCESS;
1430}
1431
1432
1433/** @callback_method_impl{FNCPUMRDMSR} */
1434static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1435{
1436 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1437 *puValue = 0;
1438 return VINF_SUCCESS;
1439}
1440
1441
1442/** @callback_method_impl{FNCPUMRDMSR} */
1443static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1444{
1445 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1446 *puValue = 0;
1447 return VINF_SUCCESS;
1448}
1449
1450
1451/** @callback_method_impl{FNCPUMRDMSR} */
1452static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SpecCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1453{
1454 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1455 *puValue = pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
1456 return VINF_SUCCESS;
1457}
1458
1459
1460/** @callback_method_impl{FNCPUMWRMSR} */
1461static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SpecCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1462{
1463 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1464
1465 /* NB: The STIBP bit can be set even when IBRS is present, regardless of whether STIBP is actually implemented. */
1466 if (uValue & ~(MSR_IA32_SPEC_CTRL_F_IBRS | MSR_IA32_SPEC_CTRL_F_STIBP))
1467 {
1468 Log(("CPUM: Invalid IA32_SPEC_CTRL bits (trying to write %#llx)\n", uValue));
1469 return VERR_CPUM_RAISE_GP_0;
1470 }
1471
1472 pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
1473 return VINF_SUCCESS;
1474}
1475
1476
1477/** @callback_method_impl{FNCPUMWRMSR} */
1478static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PredCmd(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1479{
1480 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1481 return VINF_SUCCESS;
1482}
1483
1484
1485/** @callback_method_impl{FNCPUMRDMSR} */
1486static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ArchCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1487{
1488 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1489 *puValue = pVCpu->cpum.s.GuestMsrs.msr.ArchCaps;
1490 return VINF_SUCCESS;
1491}
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504/*
1505 * AMD64
1506 * AMD64
1507 * AMD64
1508 */
1509
1510
1511/** @callback_method_impl{FNCPUMRDMSR} */
1512static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1513{
1514 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1515 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1516 return VINF_SUCCESS;
1517}
1518
1519
1520/** @callback_method_impl{FNCPUMWRMSR} */
1521static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1522{
1523 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1524 uint64_t uValidatedEfer;
1525 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1526 int rc = CPUMQueryValidatedGuestEfer(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.Guest.cr0, uOldEfer, uValue, &uValidatedEfer);
1527 if (RT_FAILURE(rc))
1528 return VERR_CPUM_RAISE_GP_0;
1529
1530 CPUMSetGuestMsrEferNoCheck(pVCpu, uOldEfer, uValidatedEfer);
1531 return VINF_SUCCESS;
1532}
1533
1534
1535/** @callback_method_impl{FNCPUMRDMSR} */
1536static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1537{
1538 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1539 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1540 return VINF_SUCCESS;
1541}
1542
1543
1544/** @callback_method_impl{FNCPUMWRMSR} */
1545static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1546{
1547 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1548 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1549 return VINF_SUCCESS;
1550}
1551
1552
1553/** @callback_method_impl{FNCPUMRDMSR} */
1554static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1555{
1556 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1557 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1558 return VINF_SUCCESS;
1559}
1560
1561
1562/** @callback_method_impl{FNCPUMWRMSR} */
1563static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1564{
1565 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1566 if (!X86_IS_CANONICAL(uValue))
1567 {
1568 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1569 return VERR_CPUM_RAISE_GP_0;
1570 }
1571 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1572 return VINF_SUCCESS;
1573}
1574
1575
1576/** @callback_method_impl{FNCPUMRDMSR} */
1577static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1578{
1579 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1580 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1581 return VINF_SUCCESS;
1582}
1583
1584
1585/** @callback_method_impl{FNCPUMWRMSR} */
1586static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1587{
1588 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1589 if (!X86_IS_CANONICAL(uValue))
1590 {
1591 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1592 return VERR_CPUM_RAISE_GP_0;
1593 }
1594 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1595 return VINF_SUCCESS;
1596}
1597
1598
1599/** @callback_method_impl{FNCPUMRDMSR} */
1600static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1601{
1602 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1603 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1604 return VINF_SUCCESS;
1605}
1606
1607
1608/** @callback_method_impl{FNCPUMWRMSR} */
1609static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1610{
1611 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1612 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1613 return VINF_SUCCESS;
1614}
1615
1616
1617/** @callback_method_impl{FNCPUMRDMSR} */
1618static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1619{
1620 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1621 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1622 return VINF_SUCCESS;
1623}
1624
1625
1626/** @callback_method_impl{FNCPUMWRMSR} */
1627static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1628{
1629 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1630 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1631 return VINF_SUCCESS;
1632}
1633
1634
1635/** @callback_method_impl{FNCPUMRDMSR} */
1636static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1637{
1638 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1639 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1640 return VINF_SUCCESS;
1641}
1642
1643/** @callback_method_impl{FNCPUMWRMSR} */
1644static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1645{
1646 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1647 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1648 return VINF_SUCCESS;
1649}
1650
1651
1652
1653/** @callback_method_impl{FNCPUMRDMSR} */
1654static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1655{
1656 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1657 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1658 return VINF_SUCCESS;
1659}
1660
1661/** @callback_method_impl{FNCPUMWRMSR} */
1662static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1663{
1664 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1665 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1666 return VINF_SUCCESS;
1667}
1668
1669
1670/** @callback_method_impl{FNCPUMRDMSR} */
1671static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1672{
1673 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1674 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1675 return VINF_SUCCESS;
1676}
1677
1678/** @callback_method_impl{FNCPUMWRMSR} */
1679static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1680{
1681 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1682 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1683 return VINF_SUCCESS;
1684}
1685
1686
1687/*
1688 * Intel specific
1689 * Intel specific
1690 * Intel specific
1691 */
1692
1693/** @callback_method_impl{FNCPUMRDMSR} */
1694static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1695{
1696 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1697 /** @todo recalc clock frequency ratio? */
1698 *puValue = pRange->uValue;
1699 return VINF_SUCCESS;
1700}
1701
1702
1703/** @callback_method_impl{FNCPUMWRMSR} */
1704static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1705{
1706 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1707 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1708 return VINF_SUCCESS;
1709}
1710
1711
1712/** @callback_method_impl{FNCPUMRDMSR} */
1713static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1714{
1715 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1716
1717 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1718 have a 4-bit core count. */
1719 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1720 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1721 *puValue = RT_MAKE_U32(cThreads, cCores);
1722 return VINF_SUCCESS;
1723}
1724
1725
1726/** @callback_method_impl{FNCPUMRDMSR} */
1727static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1728{
1729 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1730 /** @todo P4 hard power on config */
1731 *puValue = pRange->uValue;
1732 return VINF_SUCCESS;
1733}
1734
1735
1736/** @callback_method_impl{FNCPUMWRMSR} */
1737static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1738{
1739 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1740 /** @todo P4 hard power on config */
1741 return VINF_SUCCESS;
1742}
1743
1744
1745/** @callback_method_impl{FNCPUMRDMSR} */
1746static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1747{
1748 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1749 /** @todo P4 soft power on config */
1750 *puValue = pRange->uValue;
1751 return VINF_SUCCESS;
1752}
1753
1754
1755/** @callback_method_impl{FNCPUMWRMSR} */
1756static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1757{
1758 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1759 /** @todo P4 soft power on config */
1760 return VINF_SUCCESS;
1761}
1762
1763
1764/** @callback_method_impl{FNCPUMRDMSR} */
1765static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1766{
1767 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1768
1769 uint64_t uValue;
1770 PVM pVM = pVCpu->CTX_SUFF(pVM);
1771 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1772 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1773 {
1774 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1775 {
1776 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1777 uValue = 0;
1778 }
1779 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1780 {
1781 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1782 uValue = 1;
1783 }
1784 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1785 {
1786 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1787 uValue = 3;
1788 }
1789 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1790 {
1791 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1792 uValue = 2;
1793 }
1794 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1795 {
1796 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1797 uValue = 0;
1798 }
1799 else
1800 {
1801 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1802 uValue = 6;
1803 }
1804 uValue <<= 16;
1805
1806 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1807 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1808 uValue |= (uint32_t)uTscRatio << 24;
1809
1810 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1811 }
1812 else
1813 {
1814 /* Probably more stuff here, but intel doesn't want to tell us. */
1815 uValue = pRange->uValue;
1816 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1817 }
1818
1819 *puValue = uValue;
1820 return VINF_SUCCESS;
1821}
1822
1823
1824/** @callback_method_impl{FNCPUMWRMSR} */
1825static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1826{
1827 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1828 /** @todo P4 bus frequency config */
1829 return VINF_SUCCESS;
1830}
1831
1832
1833/** @callback_method_impl{FNCPUMRDMSR} */
1834static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1835{
1836 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1837
1838 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1839 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1840 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1841 *puValue = 5;
1842 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1843 *puValue = 1;
1844 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1845 *puValue = 3;
1846 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1847 *puValue = 2;
1848 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1849 *puValue = 0;
1850 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1851 *puValue = 4;
1852 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1853 *puValue = 6;
1854
1855 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1856
1857 return VINF_SUCCESS;
1858}
1859
1860
1861/** @callback_method_impl{FNCPUMRDMSR} */
1862static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1863{
1864 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1865
1866 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1867 PVM pVM = pVCpu->CTX_SUFF(pVM);
1868 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1869 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1870 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1871 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1872 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1873
1874 /* Ivy bridge has a minimum operating ratio as well. */
1875 if (true) /** @todo detect sandy bridge. */
1876 uValue |= (uint64_t)uTscRatio << 48;
1877
1878 *puValue = uValue;
1879 return VINF_SUCCESS;
1880}
1881
1882
1883/** @callback_method_impl{FNCPUMRDMSR} */
1884static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1885{
1886 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1887
1888 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1889
1890 PVM pVM = pVCpu->CTX_SUFF(pVM);
1891 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1892 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1893 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1894 uValue |= (uint32_t)uTscRatio << 8;
1895
1896 *puValue = uValue;
1897 return VINF_SUCCESS;
1898}
1899
1900
1901/** @callback_method_impl{FNCPUMWRMSR} */
1902static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1903{
1904 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1905 /** @todo implement writing MSR_FLEX_RATIO. */
1906 return VINF_SUCCESS;
1907}
1908
1909
1910/** @callback_method_impl{FNCPUMRDMSR} */
1911static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1912{
1913 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1914 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1915 return VINF_SUCCESS;
1916}
1917
1918
1919/** @callback_method_impl{FNCPUMWRMSR} */
1920static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1921{
1922 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1923
1924 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1925 {
1926 Log(("CPUM: WRMSR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1927 return VERR_CPUM_RAISE_GP_0;
1928 }
1929#if 0 /** @todo check what real (old) hardware does. */
1930 if ((uValue & 7) >= 5)
1931 {
1932 Log(("CPUM: WRMSR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1933 return VERR_CPUM_RAISE_GP_0;
1934 }
1935#endif
1936 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1937 return VINF_SUCCESS;
1938}
1939
1940
1941/** @callback_method_impl{FNCPUMRDMSR} */
1942static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1943{
1944 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1945 /** @todo implement I/O mwait wakeup. */
1946 *puValue = 0;
1947 return VINF_SUCCESS;
1948}
1949
1950
1951/** @callback_method_impl{FNCPUMWRMSR} */
1952static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1953{
1954 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1955 /** @todo implement I/O mwait wakeup. */
1956 return VINF_SUCCESS;
1957}
1958
1959
1960/** @callback_method_impl{FNCPUMRDMSR} */
1961static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1962{
1963 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1964 /** @todo implement last branch records. */
1965 *puValue = 0;
1966 return VINF_SUCCESS;
1967}
1968
1969
1970/** @callback_method_impl{FNCPUMWRMSR} */
1971static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1972{
1973 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1974 /** @todo implement last branch records. */
1975 return VINF_SUCCESS;
1976}
1977
1978
1979/** @callback_method_impl{FNCPUMRDMSR} */
1980static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1981{
1982 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1983 /** @todo implement last branch records. */
1984 *puValue = 0;
1985 return VINF_SUCCESS;
1986}
1987
1988
1989/** @callback_method_impl{FNCPUMWRMSR} */
1990static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1991{
1992 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1993 /** @todo implement last branch records. */
1994 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1995 * if the rest of the bits are zero. Automatic sign extending?
1996 * Investigate! */
1997 if (!X86_IS_CANONICAL(uValue))
1998 {
1999 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2000 return VERR_CPUM_RAISE_GP_0;
2001 }
2002 return VINF_SUCCESS;
2003}
2004
2005
2006/** @callback_method_impl{FNCPUMRDMSR} */
2007static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2008{
2009 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2010 /** @todo implement last branch records. */
2011 *puValue = 0;
2012 return VINF_SUCCESS;
2013}
2014
2015
2016/** @callback_method_impl{FNCPUMWRMSR} */
2017static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2018{
2019 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2020 /** @todo implement last branch records. */
2021 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2022 * if the rest of the bits are zero. Automatic sign extending?
2023 * Investigate! */
2024 if (!X86_IS_CANONICAL(uValue))
2025 {
2026 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2027 return VERR_CPUM_RAISE_GP_0;
2028 }
2029 return VINF_SUCCESS;
2030}
2031
2032
2033/** @callback_method_impl{FNCPUMRDMSR} */
2034static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2035{
2036 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2037 /** @todo implement last branch records. */
2038 *puValue = 0;
2039 return VINF_SUCCESS;
2040}
2041
2042
2043/** @callback_method_impl{FNCPUMWRMSR} */
2044static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2045{
2046 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2047 /** @todo implement last branch records. */
2048 return VINF_SUCCESS;
2049}
2050
2051
2052/** @callback_method_impl{FNCPUMRDMSR} */
2053static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2054{
2055 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2056 *puValue = pRange->uValue;
2057 return VINF_SUCCESS;
2058}
2059
2060
2061/** @callback_method_impl{FNCPUMWRMSR} */
2062static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2063{
2064 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2065 return VINF_SUCCESS;
2066}
2067
2068
2069/** @callback_method_impl{FNCPUMRDMSR} */
2070static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2071{
2072 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2073 *puValue = pRange->uValue;
2074 return VINF_SUCCESS;
2075}
2076
2077
2078/** @callback_method_impl{FNCPUMWRMSR} */
2079static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2080{
2081 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2082 return VINF_SUCCESS;
2083}
2084
2085
2086/** @callback_method_impl{FNCPUMRDMSR} */
2087static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2088{
2089 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2090 *puValue = pRange->uValue;
2091 return VINF_SUCCESS;
2092}
2093
2094
2095/** @callback_method_impl{FNCPUMWRMSR} */
2096static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2097{
2098 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2099 return VINF_SUCCESS;
2100}
2101
2102
2103/** @callback_method_impl{FNCPUMRDMSR} */
2104static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2105{
2106 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2107 /** @todo machine check. */
2108 *puValue = pRange->uValue;
2109 return VINF_SUCCESS;
2110}
2111
2112
2113/** @callback_method_impl{FNCPUMWRMSR} */
2114static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2115{
2116 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2117 /** @todo machine check. */
2118 return VINF_SUCCESS;
2119}
2120
2121
2122/** @callback_method_impl{FNCPUMRDMSR} */
2123static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2124{
2125 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2126 *puValue = 0;
2127 return VINF_SUCCESS;
2128}
2129
2130
2131/** @callback_method_impl{FNCPUMWRMSR} */
2132static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2133{
2134 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2135 return VINF_SUCCESS;
2136}
2137
2138
2139/** @callback_method_impl{FNCPUMRDMSR} */
2140static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2141{
2142 RT_NOREF_PV(idMsr);
2143 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
2144 AssertRC(rc);
2145 return VINF_SUCCESS;
2146}
2147
2148
2149/** @callback_method_impl{FNCPUMWRMSR} */
2150static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2151{
2152 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2153 /* This CRx interface differs from the MOV CRx, GReg interface in that
2154 #GP(0) isn't raised if unsupported bits are written to. Instead they
2155 are simply ignored and masked off. (Pentium M Dothan) */
2156 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
2157 * any, gain. */
2158 return VINF_SUCCESS;
2159}
2160
2161
2162/** @callback_method_impl{FNCPUMRDMSR} */
2163static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2164{
2165 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2166 /** @todo implement CPUID masking. */
2167 *puValue = UINT64_MAX;
2168 return VINF_SUCCESS;
2169}
2170
2171
2172/** @callback_method_impl{FNCPUMWRMSR} */
2173static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2174{
2175 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2176 /** @todo implement CPUID masking. */
2177 return VINF_SUCCESS;
2178}
2179
2180
2181/** @callback_method_impl{FNCPUMRDMSR} */
2182static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2183{
2184 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2185 /** @todo implement CPUID masking. */
2186 *puValue = 0;
2187 return VINF_SUCCESS;
2188}
2189
2190
2191/** @callback_method_impl{FNCPUMWRMSR} */
2192static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2193{
2194 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2195 /** @todo implement CPUID masking. */
2196 return VINF_SUCCESS;
2197}
2198
2199
2200
2201/** @callback_method_impl{FNCPUMRDMSR} */
2202static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2203{
2204 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2205 /** @todo implement CPUID masking. */
2206 *puValue = UINT64_MAX;
2207 return VINF_SUCCESS;
2208}
2209
2210
2211/** @callback_method_impl{FNCPUMWRMSR} */
2212static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2213{
2214 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2215 /** @todo implement CPUID masking. */
2216 return VINF_SUCCESS;
2217}
2218
2219
2220
2221/** @callback_method_impl{FNCPUMRDMSR} */
2222static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2223{
2224 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2225 /** @todo implement AES-NI. */
2226 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2227 return VINF_SUCCESS;
2228}
2229
2230
2231/** @callback_method_impl{FNCPUMWRMSR} */
2232static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2233{
2234 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2235 /** @todo implement AES-NI. */
2236 return VERR_CPUM_RAISE_GP_0;
2237}
2238
2239
2240/** @callback_method_impl{FNCPUMRDMSR} */
2241static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2242{
2243 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2244 /** @todo implement intel C states. */
2245 *puValue = pRange->uValue;
2246 return VINF_SUCCESS;
2247}
2248
2249
2250/** @callback_method_impl{FNCPUMWRMSR} */
2251static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2252{
2253 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2254 /** @todo implement intel C states. */
2255 return VINF_SUCCESS;
2256}
2257
2258
2259/** @callback_method_impl{FNCPUMRDMSR} */
2260static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2261{
2262 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2263 /** @todo implement last-branch-records. */
2264 *puValue = 0;
2265 return VINF_SUCCESS;
2266}
2267
2268
2269/** @callback_method_impl{FNCPUMWRMSR} */
2270static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2271{
2272 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2273 /** @todo implement last-branch-records. */
2274 return VINF_SUCCESS;
2275}
2276
2277
2278/** @callback_method_impl{FNCPUMRDMSR} */
2279static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2280{
2281 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2282 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2283 *puValue = 0;
2284 return VINF_SUCCESS;
2285}
2286
2287
2288/** @callback_method_impl{FNCPUMWRMSR} */
2289static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2290{
2291 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2292 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2293 return VINF_SUCCESS;
2294}
2295
2296
2297/** @callback_method_impl{FNCPUMRDMSR} */
2298static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2299{
2300 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2301 /** @todo implement memory VLW? */
2302 *puValue = pRange->uValue;
2303 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2304 AAJ49/AAK51/????, which documents the inversion of this bit. The
2305 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2306 that correct things. Some guesses at the other bits:
2307 bit 2 = INTR
2308 bit 4 = SMI
2309 bit 5 = INIT
2310 bit 6 = NMI */
2311 return VINF_SUCCESS;
2312}
2313
2314
2315/** @callback_method_impl{FNCPUMRDMSR} */
2316static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2317{
2318 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2319 /** @todo intel power management */
2320 *puValue = 0;
2321 return VINF_SUCCESS;
2322}
2323
2324
2325/** @callback_method_impl{FNCPUMWRMSR} */
2326static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2327{
2328 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2329 /** @todo intel power management */
2330 return VINF_SUCCESS;
2331}
2332
2333
2334/** @callback_method_impl{FNCPUMRDMSR} */
2335static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2336{
2337 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2338 /** @todo intel performance counters. */
2339 *puValue = 0;
2340 return VINF_SUCCESS;
2341}
2342
2343
2344/** @callback_method_impl{FNCPUMWRMSR} */
2345static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2346{
2347 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2348 /** @todo intel performance counters. */
2349 return VINF_SUCCESS;
2350}
2351
2352
2353/** @callback_method_impl{FNCPUMRDMSR} */
2354static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2355{
2356 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2357 /** @todo intel performance counters. */
2358 *puValue = 0;
2359 return VINF_SUCCESS;
2360}
2361
2362
2363/** @callback_method_impl{FNCPUMWRMSR} */
2364static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2365{
2366 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2367 /** @todo intel performance counters. */
2368 return VINF_SUCCESS;
2369}
2370
2371
2372/** @callback_method_impl{FNCPUMRDMSR} */
2373static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2374{
2375 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2376 /** @todo intel power management. */
2377 *puValue = 0;
2378 return VINF_SUCCESS;
2379}
2380
2381
2382/** @callback_method_impl{FNCPUMRDMSR} */
2383static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2384{
2385 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2386 /** @todo intel power management. */
2387 *puValue = 0;
2388 return VINF_SUCCESS;
2389}
2390
2391
2392/** @callback_method_impl{FNCPUMRDMSR} */
2393static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2394{
2395 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2396 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2397 *puValue = 0;
2398 return VINF_SUCCESS;
2399}
2400
2401
2402/** @callback_method_impl{FNCPUMWRMSR} */
2403static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2404{
2405 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2406 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2407 return VINF_SUCCESS;
2408}
2409
2410
2411/** @callback_method_impl{FNCPUMRDMSR} */
2412static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2413{
2414 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2415 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2416 *puValue = 0;
2417 return VINF_SUCCESS;
2418}
2419
2420
2421/** @callback_method_impl{FNCPUMWRMSR} */
2422static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2423{
2424 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2425 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2426 return VINF_SUCCESS;
2427}
2428
2429
2430/** @callback_method_impl{FNCPUMRDMSR} */
2431static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2432{
2433 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2434 /** @todo intel RAPL. */
2435 *puValue = pRange->uValue;
2436 return VINF_SUCCESS;
2437}
2438
2439
2440/** @callback_method_impl{FNCPUMWRMSR} */
2441static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2442{
2443 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2444 /* Note! This is documented as read only and except for a Silvermont sample has
2445 always been classified as read only. This is just here to make it compile. */
2446 return VINF_SUCCESS;
2447}
2448
2449
2450/** @callback_method_impl{FNCPUMRDMSR} */
2451static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2452{
2453 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2454 /** @todo intel power management. */
2455 *puValue = 0;
2456 return VINF_SUCCESS;
2457}
2458
2459
2460/** @callback_method_impl{FNCPUMWRMSR} */
2461static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2462{
2463 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2464 /** @todo intel power management. */
2465 return VINF_SUCCESS;
2466}
2467
2468
2469/** @callback_method_impl{FNCPUMRDMSR} */
2470static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2471{
2472 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2473 /** @todo intel power management. */
2474 *puValue = 0;
2475 return VINF_SUCCESS;
2476}
2477
2478
2479/** @callback_method_impl{FNCPUMWRMSR} */
2480static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2481{
2482 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2483 /* Note! This is documented as read only and except for a Silvermont sample has
2484 always been classified as read only. This is just here to make it compile. */
2485 return VINF_SUCCESS;
2486}
2487
2488
2489/** @callback_method_impl{FNCPUMRDMSR} */
2490static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2491{
2492 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2493 /** @todo intel RAPL. */
2494 *puValue = 0;
2495 return VINF_SUCCESS;
2496}
2497
2498
2499/** @callback_method_impl{FNCPUMWRMSR} */
2500static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2501{
2502 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2503 /** @todo intel RAPL. */
2504 return VINF_SUCCESS;
2505}
2506
2507
2508/** @callback_method_impl{FNCPUMRDMSR} */
2509static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2510{
2511 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2512 /** @todo intel power management. */
2513 *puValue = 0;
2514 return VINF_SUCCESS;
2515}
2516
2517
2518/** @callback_method_impl{FNCPUMRDMSR} */
2519static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2520{
2521 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2522 /** @todo intel power management. */
2523 *puValue = 0;
2524 return VINF_SUCCESS;
2525}
2526
2527
2528/** @callback_method_impl{FNCPUMRDMSR} */
2529static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2530{
2531 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2532 /** @todo intel power management. */
2533 *puValue = 0;
2534 return VINF_SUCCESS;
2535}
2536
2537
2538/** @callback_method_impl{FNCPUMRDMSR} */
2539static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2540{
2541 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2542 /** @todo intel RAPL. */
2543 *puValue = 0;
2544 return VINF_SUCCESS;
2545}
2546
2547
2548/** @callback_method_impl{FNCPUMWRMSR} */
2549static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2550{
2551 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2552 /** @todo intel RAPL. */
2553 return VINF_SUCCESS;
2554}
2555
2556
2557/** @callback_method_impl{FNCPUMRDMSR} */
2558static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2559{
2560 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2561 /** @todo intel power management. */
2562 *puValue = 0;
2563 return VINF_SUCCESS;
2564}
2565
2566
2567/** @callback_method_impl{FNCPUMRDMSR} */
2568static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2569{
2570 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2571 /** @todo intel power management. */
2572 *puValue = 0;
2573 return VINF_SUCCESS;
2574}
2575
2576
2577/** @callback_method_impl{FNCPUMRDMSR} */
2578static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2579{
2580 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2581 /** @todo intel power management. */
2582 *puValue = 0;
2583 return VINF_SUCCESS;
2584}
2585
2586
2587/** @callback_method_impl{FNCPUMRDMSR} */
2588static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2589{
2590 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2591 /** @todo intel RAPL. */
2592 *puValue = 0;
2593 return VINF_SUCCESS;
2594}
2595
2596
2597/** @callback_method_impl{FNCPUMWRMSR} */
2598static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2599{
2600 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2601 /** @todo intel RAPL. */
2602 return VINF_SUCCESS;
2603}
2604
2605
2606/** @callback_method_impl{FNCPUMRDMSR} */
2607static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2608{
2609 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2610 /** @todo intel power management. */
2611 *puValue = 0;
2612 return VINF_SUCCESS;
2613}
2614
2615
2616/** @callback_method_impl{FNCPUMRDMSR} */
2617static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2618{
2619 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2620 /** @todo intel RAPL. */
2621 *puValue = 0;
2622 return VINF_SUCCESS;
2623}
2624
2625
2626/** @callback_method_impl{FNCPUMWRMSR} */
2627static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2628{
2629 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2630 /** @todo intel RAPL. */
2631 return VINF_SUCCESS;
2632}
2633
2634
2635/** @callback_method_impl{FNCPUMRDMSR} */
2636static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2637{
2638 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2639 /** @todo intel power management. */
2640 *puValue = 0;
2641 return VINF_SUCCESS;
2642}
2643
2644
2645/** @callback_method_impl{FNCPUMRDMSR} */
2646static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2647{
2648 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2649 /** @todo intel RAPL. */
2650 *puValue = 0;
2651 return VINF_SUCCESS;
2652}
2653
2654
2655/** @callback_method_impl{FNCPUMWRMSR} */
2656static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2657{
2658 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2659 /** @todo intel RAPL. */
2660 return VINF_SUCCESS;
2661}
2662
2663
2664/** @callback_method_impl{FNCPUMRDMSR} */
2665static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2666{
2667 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2668 /** @todo intel power management. */
2669 *puValue = 0;
2670 return VINF_SUCCESS;
2671}
2672
2673
2674/** @callback_method_impl{FNCPUMRDMSR} */
2675static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2676{
2677 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2678 /** @todo intel RAPL. */
2679 *puValue = 0;
2680 return VINF_SUCCESS;
2681}
2682
2683
2684/** @callback_method_impl{FNCPUMWRMSR} */
2685static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2686{
2687 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2688 /** @todo intel RAPL. */
2689 return VINF_SUCCESS;
2690}
2691
2692
2693/** @callback_method_impl{FNCPUMRDMSR} */
2694static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2695{
2696 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2697 /** @todo intel power management. */
2698 *puValue = pRange->uValue;
2699 return VINF_SUCCESS;
2700}
2701
2702
2703/** @callback_method_impl{FNCPUMRDMSR} */
2704static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2705{
2706 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2707 /** @todo intel power management. */
2708 *puValue = pRange->uValue;
2709 return VINF_SUCCESS;
2710}
2711
2712
2713/** @callback_method_impl{FNCPUMRDMSR} */
2714static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2715{
2716 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2717 /** @todo intel power management. */
2718 *puValue = pRange->uValue;
2719 return VINF_SUCCESS;
2720}
2721
2722
2723/** @callback_method_impl{FNCPUMRDMSR} */
2724static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2725{
2726 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2727 /** @todo intel power management. */
2728 *puValue = 0;
2729 return VINF_SUCCESS;
2730}
2731
2732
2733/** @callback_method_impl{FNCPUMWRMSR} */
2734static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2735{
2736 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2737 /** @todo intel power management. */
2738 return VINF_SUCCESS;
2739}
2740
2741
2742/** @callback_method_impl{FNCPUMRDMSR} */
2743static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2744{
2745 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2746 /** @todo intel power management. */
2747 *puValue = 0;
2748 return VINF_SUCCESS;
2749}
2750
2751
2752/** @callback_method_impl{FNCPUMWRMSR} */
2753static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2754{
2755 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2756 /** @todo intel power management. */
2757 return VINF_SUCCESS;
2758}
2759
2760
2761/** @callback_method_impl{FNCPUMRDMSR} */
2762static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2763{
2764 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2765 /** @todo uncore msrs. */
2766 *puValue = 0;
2767 return VINF_SUCCESS;
2768}
2769
2770
2771/** @callback_method_impl{FNCPUMWRMSR} */
2772static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2773{
2774 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2775 /** @todo uncore msrs. */
2776 return VINF_SUCCESS;
2777}
2778
2779
2780/** @callback_method_impl{FNCPUMRDMSR} */
2781static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2782{
2783 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2784 /** @todo uncore msrs. */
2785 *puValue = 0;
2786 return VINF_SUCCESS;
2787}
2788
2789
2790/** @callback_method_impl{FNCPUMWRMSR} */
2791static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2792{
2793 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2794 /** @todo uncore msrs. */
2795 return VINF_SUCCESS;
2796}
2797
2798
2799/** @callback_method_impl{FNCPUMRDMSR} */
2800static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2801{
2802 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2803 /** @todo uncore msrs. */
2804 *puValue = 0;
2805 return VINF_SUCCESS;
2806}
2807
2808
2809/** @callback_method_impl{FNCPUMWRMSR} */
2810static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2811{
2812 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2813 /** @todo uncore msrs. */
2814 return VINF_SUCCESS;
2815}
2816
2817
2818/** @callback_method_impl{FNCPUMRDMSR} */
2819static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2820{
2821 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2822 /** @todo uncore msrs. */
2823 *puValue = 0;
2824 return VINF_SUCCESS;
2825}
2826
2827
2828/** @callback_method_impl{FNCPUMWRMSR} */
2829static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2830{
2831 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2832 /** @todo uncore msrs. */
2833 return VINF_SUCCESS;
2834}
2835
2836
2837/** @callback_method_impl{FNCPUMRDMSR} */
2838static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2839{
2840 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2841 /** @todo uncore msrs. */
2842 *puValue = 0;
2843 return VINF_SUCCESS;
2844}
2845
2846
2847/** @callback_method_impl{FNCPUMWRMSR} */
2848static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2849{
2850 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2851 /** @todo uncore msrs. */
2852 return VINF_SUCCESS;
2853}
2854
2855
2856/** @callback_method_impl{FNCPUMRDMSR} */
2857static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2858{
2859 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2860 /** @todo uncore msrs. */
2861 *puValue = 0;
2862 return VINF_SUCCESS;
2863}
2864
2865
2866/** @callback_method_impl{FNCPUMRDMSR} */
2867static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2868{
2869 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2870 /** @todo uncore msrs. */
2871 *puValue = 0;
2872 return VINF_SUCCESS;
2873}
2874
2875
2876/** @callback_method_impl{FNCPUMWRMSR} */
2877static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2878{
2879 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2880 /** @todo uncore msrs. */
2881 return VINF_SUCCESS;
2882}
2883
2884
2885/** @callback_method_impl{FNCPUMRDMSR} */
2886static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2887{
2888 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2889 /** @todo uncore msrs. */
2890 *puValue = 0;
2891 return VINF_SUCCESS;
2892}
2893
2894
2895/** @callback_method_impl{FNCPUMWRMSR} */
2896static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2897{
2898 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2899 /** @todo uncore msrs. */
2900 return VINF_SUCCESS;
2901}
2902
2903
2904/** @callback_method_impl{FNCPUMRDMSR} */
2905static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2906{
2907 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2908
2909 /*
2910 * 31:0 is SMI count (read only), 63:32 reserved.
2911 * Since we don't do SMI, the count is always zero.
2912 */
2913 *puValue = 0;
2914 return VINF_SUCCESS;
2915}
2916
2917
2918/** @callback_method_impl{FNCPUMRDMSR} */
2919static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2920{
2921 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2922 /** @todo implement enhanced multi thread termal monitoring? */
2923 *puValue = pRange->uValue;
2924 return VINF_SUCCESS;
2925}
2926
2927
2928/** @callback_method_impl{FNCPUMWRMSR} */
2929static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2930{
2931 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2932 /** @todo implement enhanced multi thread termal monitoring? */
2933 return VINF_SUCCESS;
2934}
2935
2936
2937/** @callback_method_impl{FNCPUMRDMSR} */
2938static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2939{
2940 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2941 /** @todo SMM & C-states? */
2942 *puValue = 0;
2943 return VINF_SUCCESS;
2944}
2945
2946
2947/** @callback_method_impl{FNCPUMWRMSR} */
2948static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2949{
2950 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2951 /** @todo SMM & C-states? */
2952 return VINF_SUCCESS;
2953}
2954
2955
2956/** @callback_method_impl{FNCPUMRDMSR} */
2957static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2958{
2959 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2960 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2961 *puValue = 0;
2962 return VINF_SUCCESS;
2963}
2964
2965
2966/** @callback_method_impl{FNCPUMWRMSR} */
2967static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2968{
2969 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2970 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2971 return VINF_SUCCESS;
2972}
2973
2974
2975/** @callback_method_impl{FNCPUMRDMSR} */
2976static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2977{
2978 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2979 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2980 *puValue = 0;
2981 return VINF_SUCCESS;
2982}
2983
2984
2985/** @callback_method_impl{FNCPUMWRMSR} */
2986static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2987{
2988 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2989 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2990 return VINF_SUCCESS;
2991}
2992
2993
2994/** @callback_method_impl{FNCPUMRDMSR} */
2995static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2996{
2997 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2998 /** @todo Core2+ platform environment control interface control register? */
2999 *puValue = 0;
3000 return VINF_SUCCESS;
3001}
3002
3003
3004/** @callback_method_impl{FNCPUMWRMSR} */
3005static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3006{
3007 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3008 /** @todo Core2+ platform environment control interface control register? */
3009 return VINF_SUCCESS;
3010}
3011
3012
3013/** @callback_method_impl{FNCPUMRDMSR} */
3014static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3015{
3016 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3017 *puValue = 0;
3018 return VINF_SUCCESS;
3019}
3020
3021
3022/*
3023 * Multiple vendor P6 MSRs.
3024 * Multiple vendor P6 MSRs.
3025 * Multiple vendor P6 MSRs.
3026 *
3027 * These MSRs were introduced with the P6 but not elevated to architectural
3028 * MSRs, despite other vendors implementing them.
3029 */
3030
3031
3032/** @callback_method_impl{FNCPUMRDMSR} */
3033static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3034{
3035 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3036 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
3037 if I read the docs correctly, thus the need for separate functions. */
3038 /** @todo implement last branch records. */
3039 *puValue = 0;
3040 return VINF_SUCCESS;
3041}
3042
3043
3044/** @callback_method_impl{FNCPUMRDMSR} */
3045static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3046{
3047 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3048 /** @todo implement last branch records. */
3049 *puValue = 0;
3050 return VINF_SUCCESS;
3051}
3052
3053
3054/** @callback_method_impl{FNCPUMRDMSR} */
3055static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3056{
3057 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3058 /** @todo implement last exception records. */
3059 *puValue = 0;
3060 return VINF_SUCCESS;
3061}
3062
3063
3064/** @callback_method_impl{FNCPUMWRMSR} */
3065static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3066{
3067 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3068 /** @todo implement last exception records. */
3069 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
3070 a non-cannonical address. */
3071 return VINF_SUCCESS;
3072}
3073
3074
3075/** @callback_method_impl{FNCPUMRDMSR} */
3076static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3077{
3078 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3079 /** @todo implement last exception records. */
3080 *puValue = 0;
3081 return VINF_SUCCESS;
3082}
3083
3084
3085/** @callback_method_impl{FNCPUMWRMSR} */
3086static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3087{
3088 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3089 /** @todo implement last exception records. */
3090 return VINF_SUCCESS;
3091}
3092
3093
3094
3095/*
3096 * AMD specific
3097 * AMD specific
3098 * AMD specific
3099 */
3100
3101
3102/** @callback_method_impl{FNCPUMRDMSR} */
3103static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3104{
3105 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3106 /** @todo Implement TscRateMsr */
3107 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
3108 return VINF_SUCCESS;
3109}
3110
3111
3112/** @callback_method_impl{FNCPUMWRMSR} */
3113static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3114{
3115 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3116 /** @todo Implement TscRateMsr */
3117 return VINF_SUCCESS;
3118}
3119
3120
3121/** @callback_method_impl{FNCPUMRDMSR} */
3122static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3123{
3124 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3125 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3126 /* Note: Only listes in BKDG for Family 15H. */
3127 *puValue = 0;
3128 return VINF_SUCCESS;
3129}
3130
3131
3132/** @callback_method_impl{FNCPUMWRMSR} */
3133static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3134{
3135 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3136 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3137 return VINF_SUCCESS;
3138}
3139
3140
3141/** @callback_method_impl{FNCPUMRDMSR} */
3142static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3143{
3144 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3145 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3146 /* Note: Only listes in BKDG for Family 15H. */
3147 *puValue = 0;
3148 return VINF_SUCCESS;
3149}
3150
3151
3152/** @callback_method_impl{FNCPUMWRMSR} */
3153static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3154{
3155 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3156 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3157 return VINF_SUCCESS;
3158}
3159
3160
3161/** @callback_method_impl{FNCPUMRDMSR} */
3162static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3163{
3164 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3165 /** @todo machine check. */
3166 *puValue = 0;
3167 return VINF_SUCCESS;
3168}
3169
3170
3171/** @callback_method_impl{FNCPUMWRMSR} */
3172static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3173{
3174 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3175 /** @todo machine check. */
3176 return VINF_SUCCESS;
3177}
3178
3179
3180/** @callback_method_impl{FNCPUMRDMSR} */
3181static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3182{
3183 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3184 /** @todo AMD performance events. */
3185 *puValue = 0;
3186 return VINF_SUCCESS;
3187}
3188
3189
3190/** @callback_method_impl{FNCPUMWRMSR} */
3191static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3192{
3193 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3194 /** @todo AMD performance events. */
3195 return VINF_SUCCESS;
3196}
3197
3198
3199/** @callback_method_impl{FNCPUMRDMSR} */
3200static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3201{
3202 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3203 /** @todo AMD performance events. */
3204 *puValue = 0;
3205 return VINF_SUCCESS;
3206}
3207
3208
3209/** @callback_method_impl{FNCPUMWRMSR} */
3210static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3211{
3212 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3213 /** @todo AMD performance events. */
3214 return VINF_SUCCESS;
3215}
3216
3217
3218/** @callback_method_impl{FNCPUMRDMSR} */
3219static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3220{
3221 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3222 /** @todo AMD SYS_CFG */
3223 *puValue = pRange->uValue;
3224 return VINF_SUCCESS;
3225}
3226
3227
3228/** @callback_method_impl{FNCPUMWRMSR} */
3229static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3230{
3231 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3232 /** @todo AMD SYS_CFG */
3233 return VINF_SUCCESS;
3234}
3235
3236
3237/** @callback_method_impl{FNCPUMRDMSR} */
3238static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3239{
3240 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3241 /** @todo AMD HW_CFG */
3242 *puValue = 0;
3243 return VINF_SUCCESS;
3244}
3245
3246
3247/** @callback_method_impl{FNCPUMWRMSR} */
3248static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3249{
3250 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3251 /** @todo AMD HW_CFG */
3252 return VINF_SUCCESS;
3253}
3254
3255
3256/** @callback_method_impl{FNCPUMRDMSR} */
3257static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3258{
3259 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3260 /** @todo AMD IorrMask/IorrBase */
3261 *puValue = 0;
3262 return VINF_SUCCESS;
3263}
3264
3265
3266/** @callback_method_impl{FNCPUMWRMSR} */
3267static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3268{
3269 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3270 /** @todo AMD IorrMask/IorrBase */
3271 return VINF_SUCCESS;
3272}
3273
3274
3275/** @callback_method_impl{FNCPUMRDMSR} */
3276static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3277{
3278 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3279 /** @todo AMD IorrMask/IorrBase */
3280 *puValue = 0;
3281 return VINF_SUCCESS;
3282}
3283
3284
3285/** @callback_method_impl{FNCPUMWRMSR} */
3286static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3287{
3288 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3289 /** @todo AMD IorrMask/IorrBase */
3290 return VINF_SUCCESS;
3291}
3292
3293
3294/** @callback_method_impl{FNCPUMRDMSR} */
3295static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3296{
3297 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3298 *puValue = 0;
3299 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
3300 * for TOPMEM2. */
3301 //if (pRange->uValue == 0)
3302 // *puValue = _4G - RamHoleSize;
3303 return VINF_SUCCESS;
3304}
3305
3306
3307/** @callback_method_impl{FNCPUMWRMSR} */
3308static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3309{
3310 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3311 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
3312 return VINF_SUCCESS;
3313}
3314
3315
3316/** @callback_method_impl{FNCPUMRDMSR} */
3317static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3318{
3319 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3320 /** @todo AMD NB_CFG1 */
3321 *puValue = 0;
3322 return VINF_SUCCESS;
3323}
3324
3325
3326/** @callback_method_impl{FNCPUMWRMSR} */
3327static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3328{
3329 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3330 /** @todo AMD NB_CFG1 */
3331 return VINF_SUCCESS;
3332}
3333
3334
3335/** @callback_method_impl{FNCPUMRDMSR} */
3336static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3337{
3338 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3339 /** @todo machine check. */
3340 *puValue = 0;
3341 return VINF_SUCCESS;
3342}
3343
3344
3345/** @callback_method_impl{FNCPUMWRMSR} */
3346static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3347{
3348 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3349 /** @todo machine check. */
3350 return VINF_SUCCESS;
3351}
3352
3353
3354/** @callback_method_impl{FNCPUMRDMSR} */
3355static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3356{
3357 RT_NOREF_PV(idMsr);
3358 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
3359 if (pLeaf)
3360 {
3361 if (!(pRange->uValue & 1))
3362 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
3363 else
3364 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
3365 }
3366 else
3367 *puValue = 0;
3368 return VINF_SUCCESS;
3369}
3370
3371
3372/** @callback_method_impl{FNCPUMWRMSR} */
3373static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3374{
3375 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3376 /** @todo Remember guest programmed CPU name. */
3377 return VINF_SUCCESS;
3378}
3379
3380
3381/** @callback_method_impl{FNCPUMRDMSR} */
3382static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3383{
3384 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3385 /** @todo AMD HTC. */
3386 *puValue = pRange->uValue;
3387 return VINF_SUCCESS;
3388}
3389
3390
3391/** @callback_method_impl{FNCPUMWRMSR} */
3392static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3393{
3394 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3395 /** @todo AMD HTC. */
3396 return VINF_SUCCESS;
3397}
3398
3399
3400/** @callback_method_impl{FNCPUMRDMSR} */
3401static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3402{
3403 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3404 /** @todo AMD STC. */
3405 *puValue = 0;
3406 return VINF_SUCCESS;
3407}
3408
3409
3410/** @callback_method_impl{FNCPUMWRMSR} */
3411static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3412{
3413 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3414 /** @todo AMD STC. */
3415 return VINF_SUCCESS;
3416}
3417
3418
3419/** @callback_method_impl{FNCPUMRDMSR} */
3420static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3421{
3422 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3423 /** @todo AMD FIDVID_CTL. */
3424 *puValue = pRange->uValue;
3425 return VINF_SUCCESS;
3426}
3427
3428
3429/** @callback_method_impl{FNCPUMWRMSR} */
3430static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3431{
3432 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3433 /** @todo AMD FIDVID_CTL. */
3434 return VINF_SUCCESS;
3435}
3436
3437
3438/** @callback_method_impl{FNCPUMRDMSR} */
3439static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3440{
3441 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3442 /** @todo AMD FIDVID_STATUS. */
3443 *puValue = pRange->uValue;
3444 return VINF_SUCCESS;
3445}
3446
3447
3448/** @callback_method_impl{FNCPUMRDMSR} */
3449static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3450{
3451 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3452 /** @todo AMD MC. */
3453 *puValue = 0;
3454 return VINF_SUCCESS;
3455}
3456
3457
3458/** @callback_method_impl{FNCPUMWRMSR} */
3459static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3460{
3461 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3462 /** @todo AMD MC. */
3463 return VINF_SUCCESS;
3464}
3465
3466
3467/** @callback_method_impl{FNCPUMRDMSR} */
3468static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3469{
3470 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3471 /** @todo AMD SMM/SMI and I/O trap. */
3472 *puValue = 0;
3473 return VINF_SUCCESS;
3474}
3475
3476
3477/** @callback_method_impl{FNCPUMWRMSR} */
3478static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3479{
3480 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3481 /** @todo AMD SMM/SMI and I/O trap. */
3482 return VINF_SUCCESS;
3483}
3484
3485
3486/** @callback_method_impl{FNCPUMRDMSR} */
3487static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3488{
3489 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3490 /** @todo AMD SMM/SMI and I/O trap. */
3491 *puValue = 0;
3492 return VINF_SUCCESS;
3493}
3494
3495
3496/** @callback_method_impl{FNCPUMWRMSR} */
3497static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3498{
3499 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3500 /** @todo AMD SMM/SMI and I/O trap. */
3501 return VINF_SUCCESS;
3502}
3503
3504
3505/** @callback_method_impl{FNCPUMRDMSR} */
3506static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3507{
3508 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3509 /** @todo Interrupt pending message. */
3510 *puValue = 0;
3511 return VINF_SUCCESS;
3512}
3513
3514
3515/** @callback_method_impl{FNCPUMWRMSR} */
3516static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3517{
3518 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3519 /** @todo Interrupt pending message. */
3520 return VINF_SUCCESS;
3521}
3522
3523
3524/** @callback_method_impl{FNCPUMRDMSR} */
3525static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3526{
3527 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3528 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3529 *puValue = 0;
3530 return VINF_SUCCESS;
3531}
3532
3533
3534/** @callback_method_impl{FNCPUMWRMSR} */
3535static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3536{
3537 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3538 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3539 return VINF_SUCCESS;
3540}
3541
3542
3543/** @callback_method_impl{FNCPUMRDMSR} */
3544static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3545{
3546 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3547 /** @todo AMD MMIO Configuration base address. */
3548 *puValue = 0;
3549 return VINF_SUCCESS;
3550}
3551
3552
3553/** @callback_method_impl{FNCPUMWRMSR} */
3554static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3555{
3556 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3557 /** @todo AMD MMIO Configuration base address. */
3558 return VINF_SUCCESS;
3559}
3560
3561
3562/** @callback_method_impl{FNCPUMRDMSR} */
3563static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3564{
3565 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3566 /** @todo AMD 0xc0010059. */
3567 *puValue = 0;
3568 return VINF_SUCCESS;
3569}
3570
3571
3572/** @callback_method_impl{FNCPUMWRMSR} */
3573static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3574{
3575 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3576 /** @todo AMD 0xc0010059. */
3577 return VINF_SUCCESS;
3578}
3579
3580
3581/** @callback_method_impl{FNCPUMRDMSR} */
3582static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3583{
3584 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3585 /** @todo AMD P-states. */
3586 *puValue = pRange->uValue;
3587 return VINF_SUCCESS;
3588}
3589
3590
3591/** @callback_method_impl{FNCPUMRDMSR} */
3592static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3593{
3594 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3595 /** @todo AMD P-states. */
3596 *puValue = pRange->uValue;
3597 return VINF_SUCCESS;
3598}
3599
3600
3601/** @callback_method_impl{FNCPUMWRMSR} */
3602static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3603{
3604 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3605 /** @todo AMD P-states. */
3606 return VINF_SUCCESS;
3607}
3608
3609
3610/** @callback_method_impl{FNCPUMRDMSR} */
3611static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3612{
3613 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3614 /** @todo AMD P-states. */
3615 *puValue = pRange->uValue;
3616 return VINF_SUCCESS;
3617}
3618
3619
3620/** @callback_method_impl{FNCPUMWRMSR} */
3621static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3622{
3623 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3624 /** @todo AMD P-states. */
3625 return VINF_SUCCESS;
3626}
3627
3628
3629/** @callback_method_impl{FNCPUMRDMSR} */
3630static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3631{
3632 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3633 /** @todo AMD P-states. */
3634 *puValue = pRange->uValue;
3635 return VINF_SUCCESS;
3636}
3637
3638
3639/** @callback_method_impl{FNCPUMWRMSR} */
3640static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3641{
3642 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3643 /** @todo AMD P-states. */
3644 return VINF_SUCCESS;
3645}
3646
3647
3648/** @callback_method_impl{FNCPUMRDMSR} */
3649static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3650{
3651 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3652 /** @todo AMD P-states. */
3653 *puValue = pRange->uValue;
3654 return VINF_SUCCESS;
3655}
3656
3657
3658/** @callback_method_impl{FNCPUMWRMSR} */
3659static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3660{
3661 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3662 /** @todo AMD P-states. */
3663 return VINF_SUCCESS;
3664}
3665
3666
3667/** @callback_method_impl{FNCPUMRDMSR} */
3668static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3669{
3670 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3671 /** @todo AMD P-states. */
3672 *puValue = pRange->uValue;
3673 return VINF_SUCCESS;
3674}
3675
3676
3677/** @callback_method_impl{FNCPUMWRMSR} */
3678static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3679{
3680 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3681 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3682 /** @todo AMD P-states. */
3683 return VINF_SUCCESS;
3684}
3685
3686
3687/** @callback_method_impl{FNCPUMRDMSR} */
3688static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3689{
3690 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3691 /** @todo AMD C-states. */
3692 *puValue = 0;
3693 return VINF_SUCCESS;
3694}
3695
3696
3697/** @callback_method_impl{FNCPUMWRMSR} */
3698static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3699{
3700 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3701 /** @todo AMD C-states. */
3702 return VINF_SUCCESS;
3703}
3704
3705
3706/** @callback_method_impl{FNCPUMRDMSR} */
3707static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3708{
3709 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3710 /** @todo AMD machine checks. */
3711 *puValue = 0;
3712 return VINF_SUCCESS;
3713}
3714
3715
3716/** @callback_method_impl{FNCPUMWRMSR} */
3717static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3718{
3719 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3720 /** @todo AMD machine checks. */
3721 return VINF_SUCCESS;
3722}
3723
3724
3725/** @callback_method_impl{FNCPUMRDMSR} */
3726static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3727{
3728 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3729 /** @todo AMD SMM. */
3730 *puValue = 0;
3731 return VINF_SUCCESS;
3732}
3733
3734
3735/** @callback_method_impl{FNCPUMWRMSR} */
3736static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3737{
3738 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3739 /** @todo AMD SMM. */
3740 return VINF_SUCCESS;
3741}
3742
3743
3744/** @callback_method_impl{FNCPUMRDMSR} */
3745static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3746{
3747 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3748 /** @todo AMD SMM. */
3749 *puValue = 0;
3750 return VINF_SUCCESS;
3751}
3752
3753
3754/** @callback_method_impl{FNCPUMWRMSR} */
3755static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3756{
3757 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3758 /** @todo AMD SMM. */
3759 return VINF_SUCCESS;
3760}
3761
3762
3763
3764/** @callback_method_impl{FNCPUMRDMSR} */
3765static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3766{
3767 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3768 /** @todo AMD SMM. */
3769 *puValue = 0;
3770 return VINF_SUCCESS;
3771}
3772
3773
3774/** @callback_method_impl{FNCPUMWRMSR} */
3775static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3776{
3777 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3778 /** @todo AMD SMM. */
3779 return VINF_SUCCESS;
3780}
3781
3782
3783/** @callback_method_impl{FNCPUMRDMSR} */
3784static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3785{
3786 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3787 PVM pVM = pVCpu->CTX_SUFF(pVM);
3788 if (pVM->cpum.s.GuestFeatures.fSvm)
3789 *puValue = MSR_K8_VM_CR_LOCK;
3790 else
3791 *puValue = 0;
3792 return VINF_SUCCESS;
3793}
3794
3795
3796/** @callback_method_impl{FNCPUMWRMSR} */
3797static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3798{
3799 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3800 PVM pVM = pVCpu->CTX_SUFF(pVM);
3801 if (pVM->cpum.s.GuestFeatures.fSvm)
3802 {
3803 /* Silently ignore writes to LOCK and SVM_DISABLE bit when the LOCK bit is set (see cpumMsrRd_AmdK8VmCr). */
3804 if (uValue & (MSR_K8_VM_CR_DPD | MSR_K8_VM_CR_R_INIT | MSR_K8_VM_CR_DIS_A20M))
3805 return VERR_CPUM_RAISE_GP_0;
3806 return VINF_SUCCESS;
3807 }
3808 return VERR_CPUM_RAISE_GP_0;
3809}
3810
3811
3812/** @callback_method_impl{FNCPUMRDMSR} */
3813static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3814{
3815 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3816 /** @todo AMD IGNNE\# control. */
3817 *puValue = 0;
3818 return VINF_SUCCESS;
3819}
3820
3821
3822/** @callback_method_impl{FNCPUMWRMSR} */
3823static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3824{
3825 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3826 /** @todo AMD IGNNE\# control. */
3827 return VINF_SUCCESS;
3828}
3829
3830
3831/** @callback_method_impl{FNCPUMRDMSR} */
3832static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3833{
3834 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3835 /** @todo AMD SMM. */
3836 *puValue = 0;
3837 return VINF_SUCCESS;
3838}
3839
3840
3841/** @callback_method_impl{FNCPUMWRMSR} */
3842static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3843{
3844 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3845 /** @todo AMD SMM. */
3846 return VINF_SUCCESS;
3847}
3848
3849
3850/** @callback_method_impl{FNCPUMRDMSR} */
3851static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3852{
3853 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3854 *puValue = pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa;
3855 return VINF_SUCCESS;
3856}
3857
3858
3859/** @callback_method_impl{FNCPUMWRMSR} */
3860static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3861{
3862 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3863 if (uValue & UINT64_C(0xfff))
3864 {
3865 Log(("CPUM: Invalid setting of low 12 bits set writing host-state save area MSR %#x: %#llx\n", idMsr, uValue));
3866 return VERR_CPUM_RAISE_GP_0;
3867 }
3868
3869 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3870 if (fInvPhysMask & uValue)
3871 {
3872 Log(("CPUM: Invalid physical address bits set writing host-state save area MSR %#x: %#llx (%#llx)\n",
3873 idMsr, uValue, uValue & fInvPhysMask));
3874 return VERR_CPUM_RAISE_GP_0;
3875 }
3876
3877 pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa = uValue;
3878 return VINF_SUCCESS;
3879}
3880
3881
3882/** @callback_method_impl{FNCPUMRDMSR} */
3883static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3884{
3885 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3886 /** @todo AMD SVM. */
3887 *puValue = 0; /* RAZ */
3888 return VINF_SUCCESS;
3889}
3890
3891
3892/** @callback_method_impl{FNCPUMWRMSR} */
3893static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3894{
3895 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3896 /** @todo AMD SVM. */
3897 return VINF_SUCCESS;
3898}
3899
3900
3901/** @callback_method_impl{FNCPUMRDMSR} */
3902static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3903{
3904 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3905 /** @todo AMD SMM. */
3906 *puValue = 0; /* RAZ */
3907 return VINF_SUCCESS;
3908}
3909
3910
3911/** @callback_method_impl{FNCPUMWRMSR} */
3912static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3913{
3914 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3915 /** @todo AMD SMM. */
3916 return VINF_SUCCESS;
3917}
3918
3919
3920/** @callback_method_impl{FNCPUMRDMSR} */
3921static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3922{
3923 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3924 /** @todo AMD SMM/SMI. */
3925 *puValue = 0;
3926 return VINF_SUCCESS;
3927}
3928
3929
3930/** @callback_method_impl{FNCPUMWRMSR} */
3931static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3932{
3933 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3934 /** @todo AMD SMM/SMI. */
3935 return VINF_SUCCESS;
3936}
3937
3938
3939/** @callback_method_impl{FNCPUMRDMSR} */
3940static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3941{
3942 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3943 /** @todo AMD OS visible workaround. */
3944 *puValue = pRange->uValue;
3945 return VINF_SUCCESS;
3946}
3947
3948
3949/** @callback_method_impl{FNCPUMWRMSR} */
3950static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3951{
3952 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3953 /** @todo AMD OS visible workaround. */
3954 return VINF_SUCCESS;
3955}
3956
3957
3958/** @callback_method_impl{FNCPUMRDMSR} */
3959static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3960{
3961 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3962 /** @todo AMD OS visible workaround. */
3963 *puValue = 0;
3964 return VINF_SUCCESS;
3965}
3966
3967
3968/** @callback_method_impl{FNCPUMWRMSR} */
3969static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3970{
3971 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3972 /** @todo AMD OS visible workaround. */
3973 return VINF_SUCCESS;
3974}
3975
3976
3977/** @callback_method_impl{FNCPUMRDMSR} */
3978static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3979{
3980 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3981 /** @todo AMD L2I performance counters. */
3982 *puValue = 0;
3983 return VINF_SUCCESS;
3984}
3985
3986
3987/** @callback_method_impl{FNCPUMWRMSR} */
3988static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3989{
3990 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3991 /** @todo AMD L2I performance counters. */
3992 return VINF_SUCCESS;
3993}
3994
3995
3996/** @callback_method_impl{FNCPUMRDMSR} */
3997static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3998{
3999 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4000 /** @todo AMD L2I performance counters. */
4001 *puValue = 0;
4002 return VINF_SUCCESS;
4003}
4004
4005
4006/** @callback_method_impl{FNCPUMWRMSR} */
4007static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4008{
4009 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4010 /** @todo AMD L2I performance counters. */
4011 return VINF_SUCCESS;
4012}
4013
4014
4015/** @callback_method_impl{FNCPUMRDMSR} */
4016static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4017{
4018 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4019 /** @todo AMD Northbridge performance counters. */
4020 *puValue = 0;
4021 return VINF_SUCCESS;
4022}
4023
4024
4025/** @callback_method_impl{FNCPUMWRMSR} */
4026static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4027{
4028 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4029 /** @todo AMD Northbridge performance counters. */
4030 return VINF_SUCCESS;
4031}
4032
4033
4034/** @callback_method_impl{FNCPUMRDMSR} */
4035static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4036{
4037 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4038 /** @todo AMD Northbridge performance counters. */
4039 *puValue = 0;
4040 return VINF_SUCCESS;
4041}
4042
4043
4044/** @callback_method_impl{FNCPUMWRMSR} */
4045static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4046{
4047 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4048 /** @todo AMD Northbridge performance counters. */
4049 return VINF_SUCCESS;
4050}
4051
4052
4053/** @callback_method_impl{FNCPUMRDMSR} */
4054static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4055{
4056 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4057 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4058 * cpus. Need to be explored and verify K7 presence. */
4059 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4060 *puValue = pRange->uValue;
4061 return VINF_SUCCESS;
4062}
4063
4064
4065/** @callback_method_impl{FNCPUMWRMSR} */
4066static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4067{
4068 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4069 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4070 * cpus. Need to be explored and verify K7 presence. */
4071 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4072 return VINF_SUCCESS;
4073}
4074
4075
4076/** @callback_method_impl{FNCPUMRDMSR} */
4077static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4078{
4079 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4080 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4081 * cpus. Need to be explored and verify K7 presence. */
4082 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4083 * describing EBL_CR_POWERON. */
4084 *puValue = pRange->uValue;
4085 return VINF_SUCCESS;
4086}
4087
4088
4089/** @callback_method_impl{FNCPUMWRMSR} */
4090static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4091{
4092 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4093 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4094 * cpus. Need to be explored and verify K7 presence. */
4095 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4096 * describing EBL_CR_POWERON. */
4097 return VINF_SUCCESS;
4098}
4099
4100
4101/** @callback_method_impl{FNCPUMRDMSR} */
4102static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4103{
4104 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4105 bool fIgnored;
4106 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
4107 if (pLeaf)
4108 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
4109 else
4110 *puValue = 0;
4111 return VINF_SUCCESS;
4112}
4113
4114
4115/** @callback_method_impl{FNCPUMWRMSR} */
4116static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4117{
4118 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4119 /** @todo Changing CPUID leaf 7/0. */
4120 return VINF_SUCCESS;
4121}
4122
4123
4124/** @callback_method_impl{FNCPUMRDMSR} */
4125static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4126{
4127 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4128 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
4129 if (pLeaf)
4130 *puValue = pLeaf->uEcx;
4131 else
4132 *puValue = 0;
4133 return VINF_SUCCESS;
4134}
4135
4136
4137/** @callback_method_impl{FNCPUMWRMSR} */
4138static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4139{
4140 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4141 /** @todo Changing CPUID leaf 6. */
4142 return VINF_SUCCESS;
4143}
4144
4145
4146/** @callback_method_impl{FNCPUMRDMSR} */
4147static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4148{
4149 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4150 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
4151 if (pLeaf)
4152 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4153 else
4154 *puValue = 0;
4155 return VINF_SUCCESS;
4156}
4157
4158
4159/** @callback_method_impl{FNCPUMWRMSR} */
4160static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4161{
4162 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4163 /** @todo Changing CPUID leaf 0x80000001. */
4164 return VINF_SUCCESS;
4165}
4166
4167
4168/** @callback_method_impl{FNCPUMRDMSR} */
4169static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4170{
4171 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4172 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
4173 if (pLeaf)
4174 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4175 else
4176 *puValue = 0;
4177 return VINF_SUCCESS;
4178}
4179
4180
4181/** @callback_method_impl{FNCPUMWRMSR} */
4182static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4183{
4184 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4185 /** @todo Changing CPUID leaf 0x80000001. */
4186 return VINF_SUCCESS;
4187}
4188
4189
4190/** @callback_method_impl{FNCPUMRDMSR} */
4191static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4192{
4193 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4194 /** @todo Fake AMD microcode patching. */
4195 *puValue = pRange->uValue;
4196 return VINF_SUCCESS;
4197}
4198
4199
4200/** @callback_method_impl{FNCPUMWRMSR} */
4201static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4202{
4203 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4204 /** @todo Fake AMD microcode patching. */
4205 return VINF_SUCCESS;
4206}
4207
4208
4209/** @callback_method_impl{FNCPUMRDMSR} */
4210static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4211{
4212 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4213 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4214 * cpus. Need to be explored and verify K7 presence. */
4215 /** @todo undocumented */
4216 *puValue = 0;
4217 return VINF_SUCCESS;
4218}
4219
4220
4221/** @callback_method_impl{FNCPUMWRMSR} */
4222static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4223{
4224 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4225 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4226 * cpus. Need to be explored and verify K7 presence. */
4227 /** @todo undocumented */
4228 return VINF_SUCCESS;
4229}
4230
4231
4232/** @callback_method_impl{FNCPUMRDMSR} */
4233static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4234{
4235 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4236 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4237 * cpus. Need to be explored and verify K7 presence. */
4238 /** @todo undocumented */
4239 *puValue = 0;
4240 return VINF_SUCCESS;
4241}
4242
4243
4244/** @callback_method_impl{FNCPUMWRMSR} */
4245static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4246{
4247 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4248 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4249 * cpus. Need to be explored and verify K7 presence. */
4250 /** @todo undocumented */
4251 return VINF_SUCCESS;
4252}
4253
4254
4255/** @callback_method_impl{FNCPUMRDMSR} */
4256static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4257{
4258 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4259 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4260 * cpus. Need to be explored and verify K7 presence. */
4261 /** @todo undocumented */
4262 *puValue = 0;
4263 return VINF_SUCCESS;
4264}
4265
4266
4267/** @callback_method_impl{FNCPUMWRMSR} */
4268static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4269{
4270 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4271 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4272 * cpus. Need to be explored and verify K7 presence. */
4273 /** @todo undocumented */
4274 return VINF_SUCCESS;
4275}
4276
4277
4278/** @callback_method_impl{FNCPUMRDMSR} */
4279static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4280{
4281 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4282 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4283 * cpus. Need to be explored and verify K7 presence. */
4284 /** @todo undocumented */
4285 *puValue = 0;
4286 return VINF_SUCCESS;
4287}
4288
4289
4290/** @callback_method_impl{FNCPUMWRMSR} */
4291static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4292{
4293 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4294 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4295 * cpus. Need to be explored and verify K7 presence. */
4296 /** @todo undocumented */
4297 return VINF_SUCCESS;
4298}
4299
4300
4301/** @callback_method_impl{FNCPUMRDMSR} */
4302static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4303{
4304 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4305 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4306 * cpus. Need to be explored and verify K7 presence. */
4307 /** @todo undocumented */
4308 *puValue = 0;
4309 return VINF_SUCCESS;
4310}
4311
4312
4313/** @callback_method_impl{FNCPUMWRMSR} */
4314static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4315{
4316 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4317 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4318 * cpus. Need to be explored and verify K7 presence. */
4319 /** @todo undocumented */
4320 return VINF_SUCCESS;
4321}
4322
4323
4324/** @callback_method_impl{FNCPUMRDMSR} */
4325static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4326{
4327 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4328 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4329 * cpus. Need to be explored and verify K7 presence. */
4330 /** @todo undocumented */
4331 *puValue = 0;
4332 return VINF_SUCCESS;
4333}
4334
4335
4336/** @callback_method_impl{FNCPUMWRMSR} */
4337static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4338{
4339 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4340 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4341 * cpus. Need to be explored and verify K7 presence. */
4342 /** @todo undocumented */
4343 return VINF_SUCCESS;
4344}
4345
4346
4347/** @callback_method_impl{FNCPUMRDMSR} */
4348static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4349{
4350 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4351 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4352 * cpus. Need to be explored and verify K7 presence. */
4353 /** @todo AMD node ID and bios scratch. */
4354 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
4355 return VINF_SUCCESS;
4356}
4357
4358
4359/** @callback_method_impl{FNCPUMWRMSR} */
4360static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4361{
4362 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4363 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4364 * cpus. Need to be explored and verify K7 presence. */
4365 /** @todo AMD node ID and bios scratch. */
4366 return VINF_SUCCESS;
4367}
4368
4369
4370/** @callback_method_impl{FNCPUMRDMSR} */
4371static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4372{
4373 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4374 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4375 * cpus. Need to be explored and verify K7 presence. */
4376 /** @todo AMD DRx address masking (range breakpoints). */
4377 *puValue = 0;
4378 return VINF_SUCCESS;
4379}
4380
4381
4382/** @callback_method_impl{FNCPUMWRMSR} */
4383static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4384{
4385 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4386 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4387 * cpus. Need to be explored and verify K7 presence. */
4388 /** @todo AMD DRx address masking (range breakpoints). */
4389 return VINF_SUCCESS;
4390}
4391
4392
4393/** @callback_method_impl{FNCPUMRDMSR} */
4394static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4395{
4396 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4397 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4398 * cpus. Need to be explored and verify K7 presence. */
4399 /** @todo AMD undocument debugging features. */
4400 *puValue = 0;
4401 return VINF_SUCCESS;
4402}
4403
4404
4405/** @callback_method_impl{FNCPUMWRMSR} */
4406static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4407{
4408 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4409 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4410 * cpus. Need to be explored and verify K7 presence. */
4411 /** @todo AMD undocument debugging features. */
4412 return VINF_SUCCESS;
4413}
4414
4415
4416/** @callback_method_impl{FNCPUMRDMSR} */
4417static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4418{
4419 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4420 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4421 * cpus. Need to be explored and verify K7 presence. */
4422 /** @todo AMD undocument debugging features. */
4423 *puValue = 0;
4424 return VINF_SUCCESS;
4425}
4426
4427
4428/** @callback_method_impl{FNCPUMWRMSR} */
4429static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4430{
4431 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4432 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4433 * cpus. Need to be explored and verify K7 presence. */
4434 /** @todo AMD undocument debugging features. */
4435 return VINF_SUCCESS;
4436}
4437
4438
4439/** @callback_method_impl{FNCPUMRDMSR} */
4440static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4441{
4442 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4443 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4444 * cpus. Need to be explored and verify K7 presence. */
4445 /** @todo AMD load-store config. */
4446 *puValue = 0;
4447 return VINF_SUCCESS;
4448}
4449
4450
4451/** @callback_method_impl{FNCPUMWRMSR} */
4452static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4453{
4454 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4455 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4456 * cpus. Need to be explored and verify K7 presence. */
4457 /** @todo AMD load-store config. */
4458 return VINF_SUCCESS;
4459}
4460
4461
4462/** @callback_method_impl{FNCPUMRDMSR} */
4463static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4464{
4465 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4466 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4467 * cpus. Need to be explored and verify K7 presence. */
4468 /** @todo AMD instruction cache config. */
4469 *puValue = 0;
4470 return VINF_SUCCESS;
4471}
4472
4473
4474/** @callback_method_impl{FNCPUMWRMSR} */
4475static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4476{
4477 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4478 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4479 * cpus. Need to be explored and verify K7 presence. */
4480 /** @todo AMD instruction cache config. */
4481 return VINF_SUCCESS;
4482}
4483
4484
4485/** @callback_method_impl{FNCPUMRDMSR} */
4486static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4487{
4488 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4489 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4490 * cpus. Need to be explored and verify K7 presence. */
4491 /** @todo AMD data cache config. */
4492 *puValue = 0;
4493 return VINF_SUCCESS;
4494}
4495
4496
4497/** @callback_method_impl{FNCPUMWRMSR} */
4498static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4499{
4500 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4501 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4502 * cpus. Need to be explored and verify K7 presence. */
4503 /** @todo AMD data cache config. */
4504 return VINF_SUCCESS;
4505}
4506
4507
4508/** @callback_method_impl{FNCPUMRDMSR} */
4509static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4510{
4511 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4512 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4513 * cpus. Need to be explored and verify K7 presence. */
4514 /** @todo AMD bus unit config. */
4515 *puValue = 0;
4516 return VINF_SUCCESS;
4517}
4518
4519
4520/** @callback_method_impl{FNCPUMWRMSR} */
4521static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4522{
4523 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4524 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4525 * cpus. Need to be explored and verify K7 presence. */
4526 /** @todo AMD bus unit config. */
4527 return VINF_SUCCESS;
4528}
4529
4530
4531/** @callback_method_impl{FNCPUMRDMSR} */
4532static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4533{
4534 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4535 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4536 * cpus. Need to be explored and verify K7 presence. */
4537 /** @todo Undocument AMD debug control register \#2. */
4538 *puValue = 0;
4539 return VINF_SUCCESS;
4540}
4541
4542
4543/** @callback_method_impl{FNCPUMWRMSR} */
4544static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4545{
4546 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4547 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4548 * cpus. Need to be explored and verify K7 presence. */
4549 /** @todo Undocument AMD debug control register \#2. */
4550 return VINF_SUCCESS;
4551}
4552
4553
4554/** @callback_method_impl{FNCPUMRDMSR} */
4555static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4556{
4557 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4558 /** @todo AMD FPU config. */
4559 *puValue = 0;
4560 return VINF_SUCCESS;
4561}
4562
4563
4564/** @callback_method_impl{FNCPUMWRMSR} */
4565static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4566{
4567 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4568 /** @todo AMD FPU config. */
4569 return VINF_SUCCESS;
4570}
4571
4572
4573/** @callback_method_impl{FNCPUMRDMSR} */
4574static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4575{
4576 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4577 /** @todo AMD decoder config. */
4578 *puValue = 0;
4579 return VINF_SUCCESS;
4580}
4581
4582
4583/** @callback_method_impl{FNCPUMWRMSR} */
4584static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4585{
4586 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4587 /** @todo AMD decoder config. */
4588 return VINF_SUCCESS;
4589}
4590
4591
4592/** @callback_method_impl{FNCPUMRDMSR} */
4593static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4594{
4595 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4596 /* Note! 10h and 16h */
4597 /** @todo AMD bus unit config. */
4598 *puValue = 0;
4599 return VINF_SUCCESS;
4600}
4601
4602
4603/** @callback_method_impl{FNCPUMWRMSR} */
4604static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4605{
4606 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4607 /* Note! 10h and 16h */
4608 /** @todo AMD bus unit config. */
4609 return VINF_SUCCESS;
4610}
4611
4612
4613/** @callback_method_impl{FNCPUMRDMSR} */
4614static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4615{
4616 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4617 /** @todo AMD unit config. */
4618 *puValue = 0;
4619 return VINF_SUCCESS;
4620}
4621
4622
4623/** @callback_method_impl{FNCPUMWRMSR} */
4624static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4625{
4626 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4627 /** @todo AMD unit config. */
4628 return VINF_SUCCESS;
4629}
4630
4631
4632/** @callback_method_impl{FNCPUMRDMSR} */
4633static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4634{
4635 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4636 /** @todo AMD unit config 2. */
4637 *puValue = 0;
4638 return VINF_SUCCESS;
4639}
4640
4641
4642/** @callback_method_impl{FNCPUMWRMSR} */
4643static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4644{
4645 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4646 /** @todo AMD unit config 2. */
4647 return VINF_SUCCESS;
4648}
4649
4650
4651/** @callback_method_impl{FNCPUMRDMSR} */
4652static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4653{
4654 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4655 /** @todo AMD combined unit config 3. */
4656 *puValue = 0;
4657 return VINF_SUCCESS;
4658}
4659
4660
4661/** @callback_method_impl{FNCPUMWRMSR} */
4662static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4663{
4664 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4665 /** @todo AMD combined unit config 3. */
4666 return VINF_SUCCESS;
4667}
4668
4669
4670/** @callback_method_impl{FNCPUMRDMSR} */
4671static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4672{
4673 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4674 /** @todo AMD execution unit config. */
4675 *puValue = 0;
4676 return VINF_SUCCESS;
4677}
4678
4679
4680/** @callback_method_impl{FNCPUMWRMSR} */
4681static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4682{
4683 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4684 /** @todo AMD execution unit config. */
4685 return VINF_SUCCESS;
4686}
4687
4688
4689/** @callback_method_impl{FNCPUMRDMSR} */
4690static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4691{
4692 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4693 /** @todo AMD load-store config 2. */
4694 *puValue = 0;
4695 return VINF_SUCCESS;
4696}
4697
4698
4699/** @callback_method_impl{FNCPUMWRMSR} */
4700static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4701{
4702 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4703 /** @todo AMD load-store config 2. */
4704 return VINF_SUCCESS;
4705}
4706
4707
4708/** @callback_method_impl{FNCPUMRDMSR} */
4709static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4710{
4711 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4712 /** @todo AMD IBS. */
4713 *puValue = 0;
4714 return VINF_SUCCESS;
4715}
4716
4717
4718/** @callback_method_impl{FNCPUMWRMSR} */
4719static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4720{
4721 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4722 /** @todo AMD IBS. */
4723 return VINF_SUCCESS;
4724}
4725
4726
4727/** @callback_method_impl{FNCPUMRDMSR} */
4728static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4729{
4730 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4731 /** @todo AMD IBS. */
4732 *puValue = 0;
4733 return VINF_SUCCESS;
4734}
4735
4736
4737/** @callback_method_impl{FNCPUMWRMSR} */
4738static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4739{
4740 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4741 /** @todo AMD IBS. */
4742 return VINF_SUCCESS;
4743}
4744
4745
4746/** @callback_method_impl{FNCPUMRDMSR} */
4747static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4748{
4749 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4750 /** @todo AMD IBS. */
4751 *puValue = 0;
4752 return VINF_SUCCESS;
4753}
4754
4755
4756/** @callback_method_impl{FNCPUMWRMSR} */
4757static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4758{
4759 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4760 /** @todo AMD IBS. */
4761 return VINF_SUCCESS;
4762}
4763
4764
4765/** @callback_method_impl{FNCPUMRDMSR} */
4766static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4767{
4768 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4769 /** @todo AMD IBS. */
4770 *puValue = 0;
4771 return VINF_SUCCESS;
4772}
4773
4774
4775/** @callback_method_impl{FNCPUMWRMSR} */
4776static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4777{
4778 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4779 /** @todo AMD IBS. */
4780 return VINF_SUCCESS;
4781}
4782
4783
4784/** @callback_method_impl{FNCPUMRDMSR} */
4785static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4786{
4787 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4788 /** @todo AMD IBS. */
4789 *puValue = 0;
4790 return VINF_SUCCESS;
4791}
4792
4793
4794/** @callback_method_impl{FNCPUMWRMSR} */
4795static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4796{
4797 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4798 /** @todo AMD IBS. */
4799 if (!X86_IS_CANONICAL(uValue))
4800 {
4801 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4802 return VERR_CPUM_RAISE_GP_0;
4803 }
4804 return VINF_SUCCESS;
4805}
4806
4807
4808/** @callback_method_impl{FNCPUMRDMSR} */
4809static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4810{
4811 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4812 /** @todo AMD IBS. */
4813 *puValue = 0;
4814 return VINF_SUCCESS;
4815}
4816
4817
4818/** @callback_method_impl{FNCPUMWRMSR} */
4819static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4820{
4821 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4822 /** @todo AMD IBS. */
4823 return VINF_SUCCESS;
4824}
4825
4826
4827/** @callback_method_impl{FNCPUMRDMSR} */
4828static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4829{
4830 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4831 /** @todo AMD IBS. */
4832 *puValue = 0;
4833 return VINF_SUCCESS;
4834}
4835
4836
4837/** @callback_method_impl{FNCPUMWRMSR} */
4838static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4839{
4840 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4841 /** @todo AMD IBS. */
4842 return VINF_SUCCESS;
4843}
4844
4845
4846/** @callback_method_impl{FNCPUMRDMSR} */
4847static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4848{
4849 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4850 /** @todo AMD IBS. */
4851 *puValue = 0;
4852 return VINF_SUCCESS;
4853}
4854
4855
4856/** @callback_method_impl{FNCPUMWRMSR} */
4857static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4858{
4859 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4860 /** @todo AMD IBS. */
4861 return VINF_SUCCESS;
4862}
4863
4864
4865/** @callback_method_impl{FNCPUMRDMSR} */
4866static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4867{
4868 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4869 /** @todo AMD IBS. */
4870 *puValue = 0;
4871 return VINF_SUCCESS;
4872}
4873
4874
4875/** @callback_method_impl{FNCPUMWRMSR} */
4876static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4877{
4878 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4879 /** @todo AMD IBS. */
4880 if (!X86_IS_CANONICAL(uValue))
4881 {
4882 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4883 return VERR_CPUM_RAISE_GP_0;
4884 }
4885 return VINF_SUCCESS;
4886}
4887
4888
4889/** @callback_method_impl{FNCPUMRDMSR} */
4890static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4891{
4892 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4893 /** @todo AMD IBS. */
4894 *puValue = 0;
4895 return VINF_SUCCESS;
4896}
4897
4898
4899/** @callback_method_impl{FNCPUMWRMSR} */
4900static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4901{
4902 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4903 /** @todo AMD IBS. */
4904 return VINF_SUCCESS;
4905}
4906
4907
4908/** @callback_method_impl{FNCPUMRDMSR} */
4909static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4910{
4911 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4912 /** @todo AMD IBS. */
4913 *puValue = 0;
4914 return VINF_SUCCESS;
4915}
4916
4917
4918/** @callback_method_impl{FNCPUMWRMSR} */
4919static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4920{
4921 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4922 /** @todo AMD IBS. */
4923 return VINF_SUCCESS;
4924}
4925
4926
4927/** @callback_method_impl{FNCPUMRDMSR} */
4928static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4929{
4930 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4931 /** @todo AMD IBS. */
4932 *puValue = 0;
4933 return VINF_SUCCESS;
4934}
4935
4936
4937/** @callback_method_impl{FNCPUMWRMSR} */
4938static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4939{
4940 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4941 /** @todo AMD IBS. */
4942 if (!X86_IS_CANONICAL(uValue))
4943 {
4944 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4945 return VERR_CPUM_RAISE_GP_0;
4946 }
4947 return VINF_SUCCESS;
4948}
4949
4950
4951
4952/*
4953 * GIM MSRs.
4954 * GIM MSRs.
4955 * GIM MSRs.
4956 */
4957
4958
4959/** @callback_method_impl{FNCPUMRDMSR} */
4960static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4961{
4962#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4963 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
4964 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4965 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
4966 return VERR_CPUM_RAISE_GP_0;
4967#endif
4968 return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
4969}
4970
4971
4972/** @callback_method_impl{FNCPUMWRMSR} */
4973static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4974{
4975#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4976 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
4977 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4978 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
4979 return VERR_CPUM_RAISE_GP_0;
4980#endif
4981 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
4982}
4983
4984
4985/**
4986 * MSR read function table.
4987 */
4988static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4989{
4990 NULL, /* Invalid */
4991 cpumMsrRd_FixedValue,
4992 NULL, /* Alias */
4993 cpumMsrRd_WriteOnly,
4994 cpumMsrRd_Ia32P5McAddr,
4995 cpumMsrRd_Ia32P5McType,
4996 cpumMsrRd_Ia32TimestampCounter,
4997 cpumMsrRd_Ia32PlatformId,
4998 cpumMsrRd_Ia32ApicBase,
4999 cpumMsrRd_Ia32FeatureControl,
5000 cpumMsrRd_Ia32BiosSignId,
5001 cpumMsrRd_Ia32SmmMonitorCtl,
5002 cpumMsrRd_Ia32PmcN,
5003 cpumMsrRd_Ia32MonitorFilterLineSize,
5004 cpumMsrRd_Ia32MPerf,
5005 cpumMsrRd_Ia32APerf,
5006 cpumMsrRd_Ia32MtrrCap,
5007 cpumMsrRd_Ia32MtrrPhysBaseN,
5008 cpumMsrRd_Ia32MtrrPhysMaskN,
5009 cpumMsrRd_Ia32MtrrFixed,
5010 cpumMsrRd_Ia32MtrrDefType,
5011 cpumMsrRd_Ia32Pat,
5012 cpumMsrRd_Ia32SysEnterCs,
5013 cpumMsrRd_Ia32SysEnterEsp,
5014 cpumMsrRd_Ia32SysEnterEip,
5015 cpumMsrRd_Ia32McgCap,
5016 cpumMsrRd_Ia32McgStatus,
5017 cpumMsrRd_Ia32McgCtl,
5018 cpumMsrRd_Ia32DebugCtl,
5019 cpumMsrRd_Ia32SmrrPhysBase,
5020 cpumMsrRd_Ia32SmrrPhysMask,
5021 cpumMsrRd_Ia32PlatformDcaCap,
5022 cpumMsrRd_Ia32CpuDcaCap,
5023 cpumMsrRd_Ia32Dca0Cap,
5024 cpumMsrRd_Ia32PerfEvtSelN,
5025 cpumMsrRd_Ia32PerfStatus,
5026 cpumMsrRd_Ia32PerfCtl,
5027 cpumMsrRd_Ia32FixedCtrN,
5028 cpumMsrRd_Ia32PerfCapabilities,
5029 cpumMsrRd_Ia32FixedCtrCtrl,
5030 cpumMsrRd_Ia32PerfGlobalStatus,
5031 cpumMsrRd_Ia32PerfGlobalCtrl,
5032 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
5033 cpumMsrRd_Ia32PebsEnable,
5034 cpumMsrRd_Ia32ClockModulation,
5035 cpumMsrRd_Ia32ThermInterrupt,
5036 cpumMsrRd_Ia32ThermStatus,
5037 cpumMsrRd_Ia32Therm2Ctl,
5038 cpumMsrRd_Ia32MiscEnable,
5039 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
5040 cpumMsrRd_Ia32McNCtl2,
5041 cpumMsrRd_Ia32DsArea,
5042 cpumMsrRd_Ia32TscDeadline,
5043 cpumMsrRd_Ia32X2ApicN,
5044 cpumMsrRd_Ia32DebugInterface,
5045 cpumMsrRd_Ia32VmxBasic,
5046 cpumMsrRd_Ia32VmxPinbasedCtls,
5047 cpumMsrRd_Ia32VmxProcbasedCtls,
5048 cpumMsrRd_Ia32VmxExitCtls,
5049 cpumMsrRd_Ia32VmxEntryCtls,
5050 cpumMsrRd_Ia32VmxMisc,
5051 cpumMsrRd_Ia32VmxCr0Fixed0,
5052 cpumMsrRd_Ia32VmxCr0Fixed1,
5053 cpumMsrRd_Ia32VmxCr4Fixed0,
5054 cpumMsrRd_Ia32VmxCr4Fixed1,
5055 cpumMsrRd_Ia32VmxVmcsEnum,
5056 cpumMsrRd_Ia32VmxProcBasedCtls2,
5057 cpumMsrRd_Ia32VmxEptVpidCap,
5058 cpumMsrRd_Ia32VmxTruePinbasedCtls,
5059 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
5060 cpumMsrRd_Ia32VmxTrueExitCtls,
5061 cpumMsrRd_Ia32VmxTrueEntryCtls,
5062 cpumMsrRd_Ia32VmxVmFunc,
5063 cpumMsrRd_Ia32SpecCtrl,
5064 cpumMsrRd_Ia32ArchCapabilities,
5065
5066 cpumMsrRd_Amd64Efer,
5067 cpumMsrRd_Amd64SyscallTarget,
5068 cpumMsrRd_Amd64LongSyscallTarget,
5069 cpumMsrRd_Amd64CompSyscallTarget,
5070 cpumMsrRd_Amd64SyscallFlagMask,
5071 cpumMsrRd_Amd64FsBase,
5072 cpumMsrRd_Amd64GsBase,
5073 cpumMsrRd_Amd64KernelGsBase,
5074 cpumMsrRd_Amd64TscAux,
5075
5076 cpumMsrRd_IntelEblCrPowerOn,
5077 cpumMsrRd_IntelI7CoreThreadCount,
5078 cpumMsrRd_IntelP4EbcHardPowerOn,
5079 cpumMsrRd_IntelP4EbcSoftPowerOn,
5080 cpumMsrRd_IntelP4EbcFrequencyId,
5081 cpumMsrRd_IntelP6FsbFrequency,
5082 cpumMsrRd_IntelPlatformInfo,
5083 cpumMsrRd_IntelFlexRatio,
5084 cpumMsrRd_IntelPkgCStConfigControl,
5085 cpumMsrRd_IntelPmgIoCaptureBase,
5086 cpumMsrRd_IntelLastBranchFromToN,
5087 cpumMsrRd_IntelLastBranchFromN,
5088 cpumMsrRd_IntelLastBranchToN,
5089 cpumMsrRd_IntelLastBranchTos,
5090 cpumMsrRd_IntelBblCrCtl,
5091 cpumMsrRd_IntelBblCrCtl3,
5092 cpumMsrRd_IntelI7TemperatureTarget,
5093 cpumMsrRd_IntelI7MsrOffCoreResponseN,
5094 cpumMsrRd_IntelI7MiscPwrMgmt,
5095 cpumMsrRd_IntelP6CrN,
5096 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
5097 cpumMsrRd_IntelCpuId1FeatureMaskEax,
5098 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
5099 cpumMsrRd_IntelI7SandyAesNiCtl,
5100 cpumMsrRd_IntelI7TurboRatioLimit,
5101 cpumMsrRd_IntelI7LbrSelect,
5102 cpumMsrRd_IntelI7SandyErrorControl,
5103 cpumMsrRd_IntelI7VirtualLegacyWireCap,
5104 cpumMsrRd_IntelI7PowerCtl,
5105 cpumMsrRd_IntelI7SandyPebsNumAlt,
5106 cpumMsrRd_IntelI7PebsLdLat,
5107 cpumMsrRd_IntelI7PkgCnResidencyN,
5108 cpumMsrRd_IntelI7CoreCnResidencyN,
5109 cpumMsrRd_IntelI7SandyVrCurrentConfig,
5110 cpumMsrRd_IntelI7SandyVrMiscConfig,
5111 cpumMsrRd_IntelI7SandyRaplPowerUnit,
5112 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
5113 cpumMsrRd_IntelI7SandyPkgC2Residency,
5114 cpumMsrRd_IntelI7RaplPkgPowerLimit,
5115 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
5116 cpumMsrRd_IntelI7RaplPkgPerfStatus,
5117 cpumMsrRd_IntelI7RaplPkgPowerInfo,
5118 cpumMsrRd_IntelI7RaplDramPowerLimit,
5119 cpumMsrRd_IntelI7RaplDramEnergyStatus,
5120 cpumMsrRd_IntelI7RaplDramPerfStatus,
5121 cpumMsrRd_IntelI7RaplDramPowerInfo,
5122 cpumMsrRd_IntelI7RaplPp0PowerLimit,
5123 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
5124 cpumMsrRd_IntelI7RaplPp0Policy,
5125 cpumMsrRd_IntelI7RaplPp0PerfStatus,
5126 cpumMsrRd_IntelI7RaplPp1PowerLimit,
5127 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
5128 cpumMsrRd_IntelI7RaplPp1Policy,
5129 cpumMsrRd_IntelI7IvyConfigTdpNominal,
5130 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
5131 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
5132 cpumMsrRd_IntelI7IvyConfigTdpControl,
5133 cpumMsrRd_IntelI7IvyTurboActivationRatio,
5134 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
5135 cpumMsrRd_IntelI7UncPerfGlobalStatus,
5136 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
5137 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
5138 cpumMsrRd_IntelI7UncPerfFixedCtr,
5139 cpumMsrRd_IntelI7UncCBoxConfig,
5140 cpumMsrRd_IntelI7UncArbPerfCtrN,
5141 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
5142 cpumMsrRd_IntelI7SmiCount,
5143 cpumMsrRd_IntelCore2EmttmCrTablesN,
5144 cpumMsrRd_IntelCore2SmmCStMiscInfo,
5145 cpumMsrRd_IntelCore1ExtConfig,
5146 cpumMsrRd_IntelCore1DtsCalControl,
5147 cpumMsrRd_IntelCore2PeciControl,
5148 cpumMsrRd_IntelAtSilvCoreC1Recidency,
5149
5150 cpumMsrRd_P6LastBranchFromIp,
5151 cpumMsrRd_P6LastBranchToIp,
5152 cpumMsrRd_P6LastIntFromIp,
5153 cpumMsrRd_P6LastIntToIp,
5154
5155 cpumMsrRd_AmdFam15hTscRate,
5156 cpumMsrRd_AmdFam15hLwpCfg,
5157 cpumMsrRd_AmdFam15hLwpCbAddr,
5158 cpumMsrRd_AmdFam10hMc4MiscN,
5159 cpumMsrRd_AmdK8PerfCtlN,
5160 cpumMsrRd_AmdK8PerfCtrN,
5161 cpumMsrRd_AmdK8SysCfg,
5162 cpumMsrRd_AmdK8HwCr,
5163 cpumMsrRd_AmdK8IorrBaseN,
5164 cpumMsrRd_AmdK8IorrMaskN,
5165 cpumMsrRd_AmdK8TopOfMemN,
5166 cpumMsrRd_AmdK8NbCfg1,
5167 cpumMsrRd_AmdK8McXcptRedir,
5168 cpumMsrRd_AmdK8CpuNameN,
5169 cpumMsrRd_AmdK8HwThermalCtrl,
5170 cpumMsrRd_AmdK8SwThermalCtrl,
5171 cpumMsrRd_AmdK8FidVidControl,
5172 cpumMsrRd_AmdK8FidVidStatus,
5173 cpumMsrRd_AmdK8McCtlMaskN,
5174 cpumMsrRd_AmdK8SmiOnIoTrapN,
5175 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
5176 cpumMsrRd_AmdK8IntPendingMessage,
5177 cpumMsrRd_AmdK8SmiTriggerIoCycle,
5178 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
5179 cpumMsrRd_AmdFam10hTrapCtlMaybe,
5180 cpumMsrRd_AmdFam10hPStateCurLimit,
5181 cpumMsrRd_AmdFam10hPStateControl,
5182 cpumMsrRd_AmdFam10hPStateStatus,
5183 cpumMsrRd_AmdFam10hPStateN,
5184 cpumMsrRd_AmdFam10hCofVidControl,
5185 cpumMsrRd_AmdFam10hCofVidStatus,
5186 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
5187 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
5188 cpumMsrRd_AmdK8SmmBase,
5189 cpumMsrRd_AmdK8SmmAddr,
5190 cpumMsrRd_AmdK8SmmMask,
5191 cpumMsrRd_AmdK8VmCr,
5192 cpumMsrRd_AmdK8IgnNe,
5193 cpumMsrRd_AmdK8SmmCtl,
5194 cpumMsrRd_AmdK8VmHSavePa,
5195 cpumMsrRd_AmdFam10hVmLockKey,
5196 cpumMsrRd_AmdFam10hSmmLockKey,
5197 cpumMsrRd_AmdFam10hLocalSmiStatus,
5198 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
5199 cpumMsrRd_AmdFam10hOsVisWrkStatus,
5200 cpumMsrRd_AmdFam16hL2IPerfCtlN,
5201 cpumMsrRd_AmdFam16hL2IPerfCtrN,
5202 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
5203 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
5204 cpumMsrRd_AmdK7MicrocodeCtl,
5205 cpumMsrRd_AmdK7ClusterIdMaybe,
5206 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
5207 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
5208 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
5209 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
5210 cpumMsrRd_AmdK8PatchLevel,
5211 cpumMsrRd_AmdK7DebugStatusMaybe,
5212 cpumMsrRd_AmdK7BHTraceBaseMaybe,
5213 cpumMsrRd_AmdK7BHTracePtrMaybe,
5214 cpumMsrRd_AmdK7BHTraceLimitMaybe,
5215 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
5216 cpumMsrRd_AmdK7FastFlushCountMaybe,
5217 cpumMsrRd_AmdK7NodeId,
5218 cpumMsrRd_AmdK7DrXAddrMaskN,
5219 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
5220 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
5221 cpumMsrRd_AmdK7LoadStoreCfg,
5222 cpumMsrRd_AmdK7InstrCacheCfg,
5223 cpumMsrRd_AmdK7DataCacheCfg,
5224 cpumMsrRd_AmdK7BusUnitCfg,
5225 cpumMsrRd_AmdK7DebugCtl2Maybe,
5226 cpumMsrRd_AmdFam15hFpuCfg,
5227 cpumMsrRd_AmdFam15hDecoderCfg,
5228 cpumMsrRd_AmdFam10hBusUnitCfg2,
5229 cpumMsrRd_AmdFam15hCombUnitCfg,
5230 cpumMsrRd_AmdFam15hCombUnitCfg2,
5231 cpumMsrRd_AmdFam15hCombUnitCfg3,
5232 cpumMsrRd_AmdFam15hExecUnitCfg,
5233 cpumMsrRd_AmdFam15hLoadStoreCfg2,
5234 cpumMsrRd_AmdFam10hIbsFetchCtl,
5235 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
5236 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
5237 cpumMsrRd_AmdFam10hIbsOpExecCtl,
5238 cpumMsrRd_AmdFam10hIbsOpRip,
5239 cpumMsrRd_AmdFam10hIbsOpData,
5240 cpumMsrRd_AmdFam10hIbsOpData2,
5241 cpumMsrRd_AmdFam10hIbsOpData3,
5242 cpumMsrRd_AmdFam10hIbsDcLinAddr,
5243 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
5244 cpumMsrRd_AmdFam10hIbsCtl,
5245 cpumMsrRd_AmdFam14hIbsBrTarget,
5246
5247 cpumMsrRd_Gim
5248};
5249
5250
5251/**
5252 * MSR write function table.
5253 */
5254static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
5255{
5256 NULL, /* Invalid */
5257 cpumMsrWr_IgnoreWrite,
5258 cpumMsrWr_ReadOnly,
5259 NULL, /* Alias */
5260 cpumMsrWr_Ia32P5McAddr,
5261 cpumMsrWr_Ia32P5McType,
5262 cpumMsrWr_Ia32TimestampCounter,
5263 cpumMsrWr_Ia32ApicBase,
5264 cpumMsrWr_Ia32FeatureControl,
5265 cpumMsrWr_Ia32BiosSignId,
5266 cpumMsrWr_Ia32BiosUpdateTrigger,
5267 cpumMsrWr_Ia32SmmMonitorCtl,
5268 cpumMsrWr_Ia32PmcN,
5269 cpumMsrWr_Ia32MonitorFilterLineSize,
5270 cpumMsrWr_Ia32MPerf,
5271 cpumMsrWr_Ia32APerf,
5272 cpumMsrWr_Ia32MtrrPhysBaseN,
5273 cpumMsrWr_Ia32MtrrPhysMaskN,
5274 cpumMsrWr_Ia32MtrrFixed,
5275 cpumMsrWr_Ia32MtrrDefType,
5276 cpumMsrWr_Ia32Pat,
5277 cpumMsrWr_Ia32SysEnterCs,
5278 cpumMsrWr_Ia32SysEnterEsp,
5279 cpumMsrWr_Ia32SysEnterEip,
5280 cpumMsrWr_Ia32McgStatus,
5281 cpumMsrWr_Ia32McgCtl,
5282 cpumMsrWr_Ia32DebugCtl,
5283 cpumMsrWr_Ia32SmrrPhysBase,
5284 cpumMsrWr_Ia32SmrrPhysMask,
5285 cpumMsrWr_Ia32PlatformDcaCap,
5286 cpumMsrWr_Ia32Dca0Cap,
5287 cpumMsrWr_Ia32PerfEvtSelN,
5288 cpumMsrWr_Ia32PerfStatus,
5289 cpumMsrWr_Ia32PerfCtl,
5290 cpumMsrWr_Ia32FixedCtrN,
5291 cpumMsrWr_Ia32PerfCapabilities,
5292 cpumMsrWr_Ia32FixedCtrCtrl,
5293 cpumMsrWr_Ia32PerfGlobalStatus,
5294 cpumMsrWr_Ia32PerfGlobalCtrl,
5295 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
5296 cpumMsrWr_Ia32PebsEnable,
5297 cpumMsrWr_Ia32ClockModulation,
5298 cpumMsrWr_Ia32ThermInterrupt,
5299 cpumMsrWr_Ia32ThermStatus,
5300 cpumMsrWr_Ia32Therm2Ctl,
5301 cpumMsrWr_Ia32MiscEnable,
5302 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
5303 cpumMsrWr_Ia32McNCtl2,
5304 cpumMsrWr_Ia32DsArea,
5305 cpumMsrWr_Ia32TscDeadline,
5306 cpumMsrWr_Ia32X2ApicN,
5307 cpumMsrWr_Ia32DebugInterface,
5308 cpumMsrWr_Ia32SpecCtrl,
5309 cpumMsrWr_Ia32PredCmd,
5310
5311 cpumMsrWr_Amd64Efer,
5312 cpumMsrWr_Amd64SyscallTarget,
5313 cpumMsrWr_Amd64LongSyscallTarget,
5314 cpumMsrWr_Amd64CompSyscallTarget,
5315 cpumMsrWr_Amd64SyscallFlagMask,
5316 cpumMsrWr_Amd64FsBase,
5317 cpumMsrWr_Amd64GsBase,
5318 cpumMsrWr_Amd64KernelGsBase,
5319 cpumMsrWr_Amd64TscAux,
5320
5321 cpumMsrWr_IntelEblCrPowerOn,
5322 cpumMsrWr_IntelP4EbcHardPowerOn,
5323 cpumMsrWr_IntelP4EbcSoftPowerOn,
5324 cpumMsrWr_IntelP4EbcFrequencyId,
5325 cpumMsrWr_IntelFlexRatio,
5326 cpumMsrWr_IntelPkgCStConfigControl,
5327 cpumMsrWr_IntelPmgIoCaptureBase,
5328 cpumMsrWr_IntelLastBranchFromToN,
5329 cpumMsrWr_IntelLastBranchFromN,
5330 cpumMsrWr_IntelLastBranchToN,
5331 cpumMsrWr_IntelLastBranchTos,
5332 cpumMsrWr_IntelBblCrCtl,
5333 cpumMsrWr_IntelBblCrCtl3,
5334 cpumMsrWr_IntelI7TemperatureTarget,
5335 cpumMsrWr_IntelI7MsrOffCoreResponseN,
5336 cpumMsrWr_IntelI7MiscPwrMgmt,
5337 cpumMsrWr_IntelP6CrN,
5338 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
5339 cpumMsrWr_IntelCpuId1FeatureMaskEax,
5340 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
5341 cpumMsrWr_IntelI7SandyAesNiCtl,
5342 cpumMsrWr_IntelI7TurboRatioLimit,
5343 cpumMsrWr_IntelI7LbrSelect,
5344 cpumMsrWr_IntelI7SandyErrorControl,
5345 cpumMsrWr_IntelI7PowerCtl,
5346 cpumMsrWr_IntelI7SandyPebsNumAlt,
5347 cpumMsrWr_IntelI7PebsLdLat,
5348 cpumMsrWr_IntelI7SandyVrCurrentConfig,
5349 cpumMsrWr_IntelI7SandyVrMiscConfig,
5350 cpumMsrWr_IntelI7SandyRaplPowerUnit,
5351 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
5352 cpumMsrWr_IntelI7SandyPkgC2Residency,
5353 cpumMsrWr_IntelI7RaplPkgPowerLimit,
5354 cpumMsrWr_IntelI7RaplDramPowerLimit,
5355 cpumMsrWr_IntelI7RaplPp0PowerLimit,
5356 cpumMsrWr_IntelI7RaplPp0Policy,
5357 cpumMsrWr_IntelI7RaplPp1PowerLimit,
5358 cpumMsrWr_IntelI7RaplPp1Policy,
5359 cpumMsrWr_IntelI7IvyConfigTdpControl,
5360 cpumMsrWr_IntelI7IvyTurboActivationRatio,
5361 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
5362 cpumMsrWr_IntelI7UncPerfGlobalStatus,
5363 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
5364 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
5365 cpumMsrWr_IntelI7UncPerfFixedCtr,
5366 cpumMsrWr_IntelI7UncArbPerfCtrN,
5367 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
5368 cpumMsrWr_IntelCore2EmttmCrTablesN,
5369 cpumMsrWr_IntelCore2SmmCStMiscInfo,
5370 cpumMsrWr_IntelCore1ExtConfig,
5371 cpumMsrWr_IntelCore1DtsCalControl,
5372 cpumMsrWr_IntelCore2PeciControl,
5373
5374 cpumMsrWr_P6LastIntFromIp,
5375 cpumMsrWr_P6LastIntToIp,
5376
5377 cpumMsrWr_AmdFam15hTscRate,
5378 cpumMsrWr_AmdFam15hLwpCfg,
5379 cpumMsrWr_AmdFam15hLwpCbAddr,
5380 cpumMsrWr_AmdFam10hMc4MiscN,
5381 cpumMsrWr_AmdK8PerfCtlN,
5382 cpumMsrWr_AmdK8PerfCtrN,
5383 cpumMsrWr_AmdK8SysCfg,
5384 cpumMsrWr_AmdK8HwCr,
5385 cpumMsrWr_AmdK8IorrBaseN,
5386 cpumMsrWr_AmdK8IorrMaskN,
5387 cpumMsrWr_AmdK8TopOfMemN,
5388 cpumMsrWr_AmdK8NbCfg1,
5389 cpumMsrWr_AmdK8McXcptRedir,
5390 cpumMsrWr_AmdK8CpuNameN,
5391 cpumMsrWr_AmdK8HwThermalCtrl,
5392 cpumMsrWr_AmdK8SwThermalCtrl,
5393 cpumMsrWr_AmdK8FidVidControl,
5394 cpumMsrWr_AmdK8McCtlMaskN,
5395 cpumMsrWr_AmdK8SmiOnIoTrapN,
5396 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
5397 cpumMsrWr_AmdK8IntPendingMessage,
5398 cpumMsrWr_AmdK8SmiTriggerIoCycle,
5399 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
5400 cpumMsrWr_AmdFam10hTrapCtlMaybe,
5401 cpumMsrWr_AmdFam10hPStateControl,
5402 cpumMsrWr_AmdFam10hPStateStatus,
5403 cpumMsrWr_AmdFam10hPStateN,
5404 cpumMsrWr_AmdFam10hCofVidControl,
5405 cpumMsrWr_AmdFam10hCofVidStatus,
5406 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
5407 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
5408 cpumMsrWr_AmdK8SmmBase,
5409 cpumMsrWr_AmdK8SmmAddr,
5410 cpumMsrWr_AmdK8SmmMask,
5411 cpumMsrWr_AmdK8VmCr,
5412 cpumMsrWr_AmdK8IgnNe,
5413 cpumMsrWr_AmdK8SmmCtl,
5414 cpumMsrWr_AmdK8VmHSavePa,
5415 cpumMsrWr_AmdFam10hVmLockKey,
5416 cpumMsrWr_AmdFam10hSmmLockKey,
5417 cpumMsrWr_AmdFam10hLocalSmiStatus,
5418 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
5419 cpumMsrWr_AmdFam10hOsVisWrkStatus,
5420 cpumMsrWr_AmdFam16hL2IPerfCtlN,
5421 cpumMsrWr_AmdFam16hL2IPerfCtrN,
5422 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
5423 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
5424 cpumMsrWr_AmdK7MicrocodeCtl,
5425 cpumMsrWr_AmdK7ClusterIdMaybe,
5426 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
5427 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
5428 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
5429 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
5430 cpumMsrWr_AmdK8PatchLoader,
5431 cpumMsrWr_AmdK7DebugStatusMaybe,
5432 cpumMsrWr_AmdK7BHTraceBaseMaybe,
5433 cpumMsrWr_AmdK7BHTracePtrMaybe,
5434 cpumMsrWr_AmdK7BHTraceLimitMaybe,
5435 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
5436 cpumMsrWr_AmdK7FastFlushCountMaybe,
5437 cpumMsrWr_AmdK7NodeId,
5438 cpumMsrWr_AmdK7DrXAddrMaskN,
5439 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
5440 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
5441 cpumMsrWr_AmdK7LoadStoreCfg,
5442 cpumMsrWr_AmdK7InstrCacheCfg,
5443 cpumMsrWr_AmdK7DataCacheCfg,
5444 cpumMsrWr_AmdK7BusUnitCfg,
5445 cpumMsrWr_AmdK7DebugCtl2Maybe,
5446 cpumMsrWr_AmdFam15hFpuCfg,
5447 cpumMsrWr_AmdFam15hDecoderCfg,
5448 cpumMsrWr_AmdFam10hBusUnitCfg2,
5449 cpumMsrWr_AmdFam15hCombUnitCfg,
5450 cpumMsrWr_AmdFam15hCombUnitCfg2,
5451 cpumMsrWr_AmdFam15hCombUnitCfg3,
5452 cpumMsrWr_AmdFam15hExecUnitCfg,
5453 cpumMsrWr_AmdFam15hLoadStoreCfg2,
5454 cpumMsrWr_AmdFam10hIbsFetchCtl,
5455 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
5456 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
5457 cpumMsrWr_AmdFam10hIbsOpExecCtl,
5458 cpumMsrWr_AmdFam10hIbsOpRip,
5459 cpumMsrWr_AmdFam10hIbsOpData,
5460 cpumMsrWr_AmdFam10hIbsOpData2,
5461 cpumMsrWr_AmdFam10hIbsOpData3,
5462 cpumMsrWr_AmdFam10hIbsDcLinAddr,
5463 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
5464 cpumMsrWr_AmdFam10hIbsCtl,
5465 cpumMsrWr_AmdFam14hIbsBrTarget,
5466
5467 cpumMsrWr_Gim
5468};
5469
5470
5471/**
5472 * Looks up the range for the given MSR.
5473 *
5474 * @returns Pointer to the range if found, NULL if not.
5475 * @param pVM The cross context VM structure.
5476 * @param idMsr The MSR to look up.
5477 */
5478# ifndef IN_RING3
5479static
5480# endif
5481PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
5482{
5483 /*
5484 * Binary lookup.
5485 */
5486 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
5487 if (!cRanges)
5488 return NULL;
5489 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5490 for (;;)
5491 {
5492 uint32_t i = cRanges / 2;
5493 if (idMsr < paRanges[i].uFirst)
5494 {
5495 if (i == 0)
5496 break;
5497 cRanges = i;
5498 }
5499 else if (idMsr > paRanges[i].uLast)
5500 {
5501 i++;
5502 if (i >= cRanges)
5503 break;
5504 cRanges -= i;
5505 paRanges = &paRanges[i];
5506 }
5507 else
5508 {
5509 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
5510 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
5511 return &paRanges[i];
5512 }
5513 }
5514
5515# ifdef VBOX_STRICT
5516 /*
5517 * Linear lookup to verify the above binary search.
5518 */
5519 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
5520 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5521 while (cLeft-- > 0)
5522 {
5523 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
5524 {
5525 AssertFailed();
5526 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
5527 return cpumLookupMsrRange(pVM, pCur->uValue);
5528 return pCur;
5529 }
5530 pCur++;
5531 }
5532# endif
5533 return NULL;
5534}
5535
5536
5537/**
5538 * Query a guest MSR.
5539 *
5540 * The caller is responsible for checking privilege if the call is the result of
5541 * a RDMSR instruction. We'll do the rest.
5542 *
5543 * @retval VINF_SUCCESS on success.
5544 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
5545 * current context (raw-mode or ring-0).
5546 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
5547 * expected to take the appropriate actions. @a *puValue is set to 0.
5548 * @param pVCpu The cross context virtual CPU structure.
5549 * @param idMsr The MSR.
5550 * @param puValue Where to return the value.
5551 *
5552 * @remarks This will always return the right values, even when we're in the
5553 * recompiler.
5554 */
5555VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
5556{
5557 *puValue = 0;
5558
5559 VBOXSTRICTRC rcStrict;
5560 PVM pVM = pVCpu->CTX_SUFF(pVM);
5561 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5562 if (pRange)
5563 {
5564 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
5565 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5566
5567 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
5568 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5569
5570 STAM_COUNTER_INC(&pRange->cReads);
5571 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5572
5573 rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5574 if (rcStrict == VINF_SUCCESS)
5575 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5576 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5577 {
5578 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5579 STAM_COUNTER_INC(&pRange->cGps);
5580 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5581 }
5582#ifndef IN_RING3
5583 else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5584 Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5585#endif
5586 else
5587 {
5588 Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5589 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5590 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5591 Assert(rcStrict != VERR_EM_INTERPRETER);
5592 }
5593 }
5594 else
5595 {
5596 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5597 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5598 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5599 rcStrict = VERR_CPUM_RAISE_GP_0;
5600 }
5601 return rcStrict;
5602}
5603
5604
5605/**
5606 * Writes to a guest MSR.
5607 *
5608 * The caller is responsible for checking privilege if the call is the result of
5609 * a WRMSR instruction. We'll do the rest.
5610 *
5611 * @retval VINF_SUCCESS on success.
5612 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5613 * current context (raw-mode or ring-0).
5614 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5615 * appropriate actions.
5616 *
5617 * @param pVCpu The cross context virtual CPU structure.
5618 * @param idMsr The MSR id.
5619 * @param uValue The value to set.
5620 *
5621 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5622 * by calling this method. This makes sure we have current values and
5623 * that we trigger all the right actions when something changes.
5624 *
5625 * For performance reasons, this actually isn't entirely true for some
5626 * MSRs when in HM mode. The code here and in HM must be aware of
5627 * this.
5628 */
5629VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5630{
5631 VBOXSTRICTRC rcStrict;
5632 PVM pVM = pVCpu->CTX_SUFF(pVM);
5633 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5634 if (pRange)
5635 {
5636 STAM_COUNTER_INC(&pRange->cWrites);
5637 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5638
5639 if (!(uValue & pRange->fWrGpMask))
5640 {
5641 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5642 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5643
5644 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5645 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5646
5647 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5648 if (uValueAdjusted != uValue)
5649 {
5650 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5651 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5652 }
5653
5654 rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5655 if (rcStrict == VINF_SUCCESS)
5656 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5657 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5658 {
5659 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5660 STAM_COUNTER_INC(&pRange->cGps);
5661 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5662 }
5663#ifndef IN_RING3
5664 else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5665 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5666#endif
5667 else
5668 {
5669 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5670 idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5671 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5672 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5673 Assert(rcStrict != VERR_EM_INTERPRETER);
5674 }
5675 }
5676 else
5677 {
5678 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5679 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5680 STAM_COUNTER_INC(&pRange->cGps);
5681 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5682 rcStrict = VERR_CPUM_RAISE_GP_0;
5683 }
5684 }
5685 else
5686 {
5687 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5688 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5689 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5690 rcStrict = VERR_CPUM_RAISE_GP_0;
5691 }
5692 return rcStrict;
5693}
5694
5695
5696#if defined(VBOX_STRICT) && defined(IN_RING3)
5697/**
5698 * Performs some checks on the static data related to MSRs.
5699 *
5700 * @returns VINF_SUCCESS on success, error on failure.
5701 */
5702int cpumR3MsrStrictInitChecks(void)
5703{
5704#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5705 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5706#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5707 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5708
5709 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5710 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5711 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5712 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5713 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5714 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5715 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5716 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5717 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5718 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5719 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5720 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5721 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5722 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5723 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5724 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5725 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5726 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5727 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5728 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5729 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5730 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5731 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5732 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5733 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5734 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5735 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5736 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5737 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5738 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5739 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5740 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5741 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5742 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5743 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5744 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5745 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5746 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5747 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5748 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5749 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5750 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5751 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5752 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5753 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5754 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5755 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5756 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5757 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5758 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5759 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5760 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5761 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5762 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBasic);
5763 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5764 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5765 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5766 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5767 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5768 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5769 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5770 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5771 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5772 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5773 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5774 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5775 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5776 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5777 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5778 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5779 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc);
5780 CPUM_ASSERT_RD_MSR_FN(Ia32SpecCtrl);
5781 CPUM_ASSERT_RD_MSR_FN(Ia32ArchCapabilities);
5782
5783 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5784 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5785 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5786 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5787 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5788 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5789 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5790 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5791 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5792
5793 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5794 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5795 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5796 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5797 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5798 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5799 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5800 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5801 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5802 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5803 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5804 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5805 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5806 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5807 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5808 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5809 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5810 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5811 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5812 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5813 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5814 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5815 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5816 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5817 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5818 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5819 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5820 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5821 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5822 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5823 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5824 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5825 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5826 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5827 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5828 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5829 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5830 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5831 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5832 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5833 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5834 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5835 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5836 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5837 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5838 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5839 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5840 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5841 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5842 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5843 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5844 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5845 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5846 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5847 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5848 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5849 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5850 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5851 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5852 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5853 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5854 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5855 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5856 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5857 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5858 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5859 CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount);
5860 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5861 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5862 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5863 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5864 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5865 CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency);
5866
5867 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5868 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5869 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5870 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5871
5872 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5873 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5874 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5875 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5876 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5877 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5878 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5879 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5880 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5881 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5882 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5883 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5884 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5885 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5886 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5887 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5888 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5889 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5890 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5891 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5892 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5893 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5894 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5895 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5896 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5897 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5898 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5899 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5900 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5901 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5902 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5903 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5904 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5905 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5906 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5907 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5908 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5909 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5910 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5911 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5912 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5913 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5914 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5915 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5916 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5917 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5918 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5919 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5920 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5921 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5922 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5923 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5924 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5925 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5926 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5927 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5928 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5929 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5930 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5931 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5932 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5933 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5934 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5935 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5936 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5937 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5938 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5939 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5940 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5941 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5942 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5943 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5944 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5945 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5946 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5947 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5948 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5949 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5950 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5951 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5952 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5953 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5954 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5955 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5956 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5957 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5958 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5959 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5960 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5961 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5962 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5963
5964 CPUM_ASSERT_RD_MSR_FN(Gim)
5965
5966 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5967 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5968 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5969 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5970 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5971 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5972 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5973 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5974 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5975 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5976 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5977 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5978 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5979 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5980 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5981 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5982 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5983 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5984 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5985 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5986 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5987 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5988 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5989 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5990 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5991 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5992 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5993 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5994 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5995 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5996 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5997 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5998 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5999 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
6000 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
6001 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
6002 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
6003 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
6004 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
6005 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
6006 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
6007 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
6008 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
6009 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
6010 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
6011 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
6012 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
6013 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
6014 CPUM_ASSERT_WR_MSR_FN(Ia32SpecCtrl);
6015 CPUM_ASSERT_WR_MSR_FN(Ia32PredCmd);
6016
6017 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
6018 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
6019 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
6020 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
6021 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
6022 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
6023 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
6024 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
6025 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
6026
6027 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
6028 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
6029 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
6030 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
6031 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
6032 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
6033 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
6034 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
6035 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
6036 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
6037 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
6038 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
6039 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
6040 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
6041 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
6042 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
6043 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
6044 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6045 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
6046 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6047 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
6048 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
6049 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
6050 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
6051 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
6052 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
6053 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
6054 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
6055 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
6056 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
6057 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency);
6058 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
6059 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
6060 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
6061 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
6062 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
6063 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
6064 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
6065 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
6066 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
6067 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
6068 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6069 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6070 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
6071 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
6072 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
6073 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
6074 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
6075 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
6076 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
6077 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
6078
6079 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
6080 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
6081
6082 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
6083 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
6084 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
6085 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
6086 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
6087 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
6088 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
6089 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
6090 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
6091 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
6092 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
6093 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
6094 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
6095 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
6096 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
6097 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
6098 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
6099 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
6100 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
6101 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6102 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
6103 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
6104 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6105 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
6106 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
6107 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
6108 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
6109 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
6110 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
6111 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
6112 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
6113 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
6114 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
6115 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
6116 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
6117 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
6118 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
6119 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
6120 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
6121 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
6122 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
6123 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
6124 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
6125 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
6126 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
6127 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6128 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6129 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
6130 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
6131 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6132 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6133 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6134 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6135 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
6136 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
6137 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
6138 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
6139 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
6140 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6141 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
6142 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
6143 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
6144 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
6145 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
6146 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
6147 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
6148 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
6149 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
6150 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
6151 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
6152 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
6153 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
6154 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
6155 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
6156 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
6157 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
6158 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
6159 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
6160 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
6161 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6162 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
6163 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
6164 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
6165 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
6166 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
6167 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
6168 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
6169 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
6170 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
6171
6172 CPUM_ASSERT_WR_MSR_FN(Gim);
6173
6174 return VINF_SUCCESS;
6175}
6176#endif /* VBOX_STRICT && IN_RING3 */
6177
6178
6179/**
6180 * Gets the scalable bus frequency.
6181 *
6182 * The bus frequency is used as a base in several MSRs that gives the CPU and
6183 * other frequency ratios.
6184 *
6185 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
6186 * @param pVM The cross context VM structure.
6187 */
6188VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
6189{
6190 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
6191 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
6192 uFreq = CPUM_SBUSFREQ_100MHZ;
6193 return uFreq;
6194}
6195
6196
6197/**
6198 * Sets the guest EFER MSR without performing any additional checks.
6199 *
6200 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6201 * @param uOldEfer The previous EFER MSR value.
6202 * @param uValidEfer The new, validated EFER MSR value.
6203 *
6204 * @remarks One would normally call CPUMQueryValidatedGuestEfer before calling this
6205 * function to change the EFER in order to perform an EFER transition.
6206 */
6207VMMDECL(void) CPUMSetGuestMsrEferNoCheck(PVMCPU pVCpu, uint64_t uOldEfer, uint64_t uValidEfer)
6208{
6209 pVCpu->cpum.s.Guest.msrEFER = uValidEfer;
6210
6211 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
6212 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
6213 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
6214 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
6215 {
6216 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
6217 HMFlushTLB(pVCpu);
6218
6219 /* Notify PGM about NXE changes. */
6220 if ( (uOldEfer & MSR_K6_EFER_NXE)
6221 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
6222 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
6223 }
6224}
6225
6226
6227/**
6228 * Checks if a guest PAT MSR write is valid.
6229 *
6230 * @returns @c true if the PAT bit combination is valid, @c false otherwise.
6231 * @param uValue The PAT MSR value.
6232 */
6233VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue)
6234{
6235 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
6236 {
6237 /* Check all eight bits because the top 5 bits of each byte are reserved. */
6238 uint8_t uType = (uint8_t)(uValue >> cShift);
6239 if ((uType >= 8) || (uType == 2) || (uType == 3))
6240 {
6241 Log(("CPUM: Invalid PAT type at %u:%u in IA32_PAT: %#llx (%#llx)\n", cShift + 7, cShift, uValue, uType));
6242 return false;
6243 }
6244 }
6245 return true;
6246}
6247
6248
6249/**
6250 * Validates an EFER MSR write.
6251 *
6252 * @returns VBox status code.
6253 * @param pVM The cross context VM structure.
6254 * @param uCr0 The CR0 of the CPU corresponding to the EFER MSR.
6255 * @param uOldEfer Value of the previous EFER MSR on the CPU if any.
6256 * @param uNewEfer The new EFER MSR value being written.
6257 * @param puValidEfer Where to store the validated EFER (only updated if
6258 * this function returns VINF_SUCCESS).
6259 */
6260VMMDECL(int) CPUMQueryValidatedGuestEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer, uint64_t *puValidEfer)
6261{
6262 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
6263 ? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
6264 : 0;
6265 uint64_t fMask = 0;
6266 uint64_t const fIgnoreMask = MSR_K6_EFER_LMA;
6267
6268 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
6269 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
6270 fMask |= MSR_K6_EFER_NXE;
6271 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
6272 fMask |= MSR_K6_EFER_LME;
6273 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
6274 fMask |= MSR_K6_EFER_SCE;
6275 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
6276 fMask |= MSR_K6_EFER_FFXSR;
6277 if (pVM->cpum.s.GuestFeatures.fSvm)
6278 fMask |= MSR_K6_EFER_SVME;
6279
6280 /* #GP(0) If anything outside the allowed bits is set. */
6281 if (uNewEfer & ~(fIgnoreMask | fMask))
6282 {
6283 Log(("CPUM: Settings disallowed EFER bit. uNewEfer=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uNewEfer, fMask));
6284 return VERR_CPUM_RAISE_GP_0;
6285 }
6286
6287 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
6288 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6289 if ( (uOldEfer & MSR_K6_EFER_LME) != (uNewEfer & fMask & MSR_K6_EFER_LME)
6290 && (uCr0 & X86_CR0_PG))
6291 {
6292 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
6293 return VERR_CPUM_RAISE_GP_0;
6294 }
6295
6296 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
6297 AssertMsg(!(uNewEfer & ~( MSR_K6_EFER_NXE
6298 | MSR_K6_EFER_LME
6299 | MSR_K6_EFER_LMA /* ignored anyway */
6300 | MSR_K6_EFER_SCE
6301 | MSR_K6_EFER_FFXSR
6302 | MSR_K6_EFER_SVME)),
6303 ("Unexpected value %#RX64\n", uNewEfer));
6304
6305 *puValidEfer = (uOldEfer & ~fMask) | (uNewEfer & fMask);
6306 return VINF_SUCCESS;
6307}
6308
6309
6310/**
6311 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6312 *
6313 * @returns The register value.
6314 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6315 * @thread EMT(pVCpu)
6316 */
6317VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPU pVCpu)
6318{
6319 Assert(!(pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_TSC_AUX));
6320 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
6321}
6322
6323
6324/**
6325 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6326 *
6327 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6328 * @param uValue The new value.
6329 * @thread EMT(pVCpu)
6330 */
6331VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
6332{
6333 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_TSC_AUX;
6334 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
6335}
6336
6337
6338/**
6339 * Fast way for HM to access the IA32_SPEC_CTRL register.
6340 *
6341 * @returns The register value.
6342 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6343 * @thread EMT(pVCpu)
6344 */
6345VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPU pVCpu)
6346{
6347 return pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
6348}
6349
6350
6351/**
6352 * Fast way for HM to access the IA32_SPEC_CTRL register.
6353 *
6354 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6355 * @param uValue The new value.
6356 * @thread EMT(pVCpu)
6357 */
6358VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPU pVCpu, uint64_t uValue)
6359{
6360 pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
6361}
6362
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