VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 72634

Last change on this file since 72634 was 72634, checked in by vboxsync, 7 years ago

EM[R3]: Use pVCpu->cpum.GstCtx and stop keeping and passing pCtx around.

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1/* $Id: CPUMAllMsrs.cpp 72634 2018-06-20 16:08:42Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/apic.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/tm.h>
27#include <VBox/vmm/gim.h>
28#include "CPUMInternal.h"
29#include <VBox/vmm/vm.h>
30#include <VBox/err.h>
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36/**
37 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
38 * pointing to it.
39 *
40 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
41 * correctly.
42 */
43#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
44 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
45 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
46 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
47 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
48 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
49 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
50
51
52/*********************************************************************************************************************************
53* Structures and Typedefs *
54*********************************************************************************************************************************/
55
56/**
57 * Implements reading one or more MSRs.
58 *
59 * @returns VBox status code.
60 * @retval VINF_SUCCESS on success.
61 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
62 * current context (raw-mode or ring-0).
63 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
64 *
65 * @param pVCpu The cross context virtual CPU structure.
66 * @param idMsr The MSR we're reading.
67 * @param pRange The MSR range descriptor.
68 * @param puValue Where to return the value.
69 */
70typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
71/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
72typedef FNCPUMRDMSR *PFNCPUMRDMSR;
73
74
75/**
76 * Implements writing one or more MSRs.
77 *
78 * @retval VINF_SUCCESS on success.
79 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
80 * current context (raw-mode or ring-0).
81 * @retval VERR_CPUM_RAISE_GP_0 on failure.
82 *
83 * @param pVCpu The cross context virtual CPU structure.
84 * @param idMsr The MSR we're writing.
85 * @param pRange The MSR range descriptor.
86 * @param uValue The value to set, ignored bits masked.
87 * @param uRawValue The raw value with the ignored bits not masked.
88 */
89typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
90/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
91typedef FNCPUMWRMSR *PFNCPUMWRMSR;
92
93
94
95/*
96 * Generic functions.
97 * Generic functions.
98 * Generic functions.
99 */
100
101
102/** @callback_method_impl{FNCPUMRDMSR} */
103static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
104{
105 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
106 *puValue = pRange->uValue;
107 return VINF_SUCCESS;
108}
109
110
111/** @callback_method_impl{FNCPUMWRMSR} */
112static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
113{
114 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
115 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
116 return VINF_SUCCESS;
117}
118
119
120/** @callback_method_impl{FNCPUMRDMSR} */
121static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
122{
123 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
124 return VERR_CPUM_RAISE_GP_0;
125}
126
127
128/** @callback_method_impl{FNCPUMWRMSR} */
129static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
130{
131 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
132 Assert(pRange->fWrGpMask == UINT64_MAX);
133 return VERR_CPUM_RAISE_GP_0;
134}
135
136
137
138
139/*
140 * IA32
141 * IA32
142 * IA32
143 */
144
145/** @callback_method_impl{FNCPUMRDMSR} */
146static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
147{
148 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
149 *puValue = 0; /** @todo implement machine check injection. */
150 return VINF_SUCCESS;
151}
152
153
154/** @callback_method_impl{FNCPUMWRMSR} */
155static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
156{
157 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
158 /** @todo implement machine check injection. */
159 return VINF_SUCCESS;
160}
161
162
163/** @callback_method_impl{FNCPUMRDMSR} */
164static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
165{
166 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
167 *puValue = 0; /** @todo implement machine check injection. */
168 return VINF_SUCCESS;
169}
170
171
172/** @callback_method_impl{FNCPUMWRMSR} */
173static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
174{
175 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
176 /** @todo implement machine check injection. */
177 return VINF_SUCCESS;
178}
179
180
181/** @callback_method_impl{FNCPUMRDMSR} */
182static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
183{
184 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
185 *puValue = TMCpuTickGet(pVCpu);
186#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
187 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
188#endif
189 return VINF_SUCCESS;
190}
191
192
193/** @callback_method_impl{FNCPUMWRMSR} */
194static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
195{
196 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
197 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
198 return VINF_SUCCESS;
199}
200
201
202/** @callback_method_impl{FNCPUMRDMSR} */
203static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
204{
205 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
206 uint64_t uValue = pRange->uValue;
207 if (uValue & 0x1f00)
208 {
209 /* Max allowed bus ratio present. */
210 /** @todo Implement scaled BUS frequency. */
211 }
212
213 *puValue = uValue;
214 return VINF_SUCCESS;
215}
216
217
218/** @callback_method_impl{FNCPUMRDMSR} */
219static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
220{
221 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
222 return APICGetBaseMsr(pVCpu, puValue);
223}
224
225
226/** @callback_method_impl{FNCPUMWRMSR} */
227static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
228{
229 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
230 return APICSetBaseMsr(pVCpu, uValue);
231}
232
233
234/**
235 * Get fixed IA32_FEATURE_CONTROL value for NEM and cpumMsrRd_Ia32FeatureControl.
236 *
237 * @returns Fixed IA32_FEATURE_CONTROL value.
238 * @param pVCpu The cross context per CPU structure.
239 */
240VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatureControl(PVMCPU pVCpu)
241{
242 RT_NOREF_PV(pVCpu);
243 return 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
244}
245
246/** @callback_method_impl{FNCPUMRDMSR} */
247static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
248{
249 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
250 *puValue = CPUMGetGuestIa32FeatureControl(pVCpu);
251 return VINF_SUCCESS;
252}
253
254
255/** @callback_method_impl{FNCPUMWRMSR} */
256static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
257{
258 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
259 return VERR_CPUM_RAISE_GP_0;
260}
261
262
263/** @callback_method_impl{FNCPUMRDMSR} */
264static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
265{
266 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
267 /** @todo fake microcode update. */
268 *puValue = pRange->uValue;
269 return VINF_SUCCESS;
270}
271
272
273/** @callback_method_impl{FNCPUMWRMSR} */
274static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
275{
276 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
277 /* Normally, zero is written to Ia32BiosSignId before reading it in order
278 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
279 of the database entry should take care of most illegal writes for now, so
280 just ignore all writes atm. */
281 return VINF_SUCCESS;
282}
283
284
285/** @callback_method_impl{FNCPUMWRMSR} */
286static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
287{
288 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
289 /** @todo Fake bios update trigger better. The value is the address to an
290 * update package, I think. We should probably GP if it's invalid. */
291 return VINF_SUCCESS;
292}
293
294
295/** @callback_method_impl{FNCPUMRDMSR} */
296static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
297{
298 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
299 /** @todo SMM. */
300 *puValue = 0;
301 return VINF_SUCCESS;
302}
303
304
305/** @callback_method_impl{FNCPUMWRMSR} */
306static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
307{
308 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
309 /** @todo SMM. */
310 return VINF_SUCCESS;
311}
312
313
314/** @callback_method_impl{FNCPUMRDMSR} */
315static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
316{
317 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
318 /** @todo check CPUID leaf 0ah. */
319 *puValue = 0;
320 return VINF_SUCCESS;
321}
322
323
324/** @callback_method_impl{FNCPUMWRMSR} */
325static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
326{
327 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
328 /** @todo check CPUID leaf 0ah. */
329 return VINF_SUCCESS;
330}
331
332
333/** @callback_method_impl{FNCPUMRDMSR} */
334static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
335{
336 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
337 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
338 *puValue = 0x40; /** @todo Change to CPU cache line size. */
339 return VINF_SUCCESS;
340}
341
342
343/** @callback_method_impl{FNCPUMWRMSR} */
344static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
345{
346 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
347 /** @todo should remember writes, though it's supposedly something only a BIOS
348 * would write so, it's not extremely important. */
349 return VINF_SUCCESS;
350}
351
352/** @callback_method_impl{FNCPUMRDMSR} */
353static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
354{
355 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
356 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
357 * what we want? */
358 *puValue = TMCpuTickGet(pVCpu);
359#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
360 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
361#endif
362 return VINF_SUCCESS;
363}
364
365
366/** @callback_method_impl{FNCPUMWRMSR} */
367static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
368{
369 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
370 /** @todo Write MPERF: Calc adjustment. */
371 return VINF_SUCCESS;
372}
373
374
375/** @callback_method_impl{FNCPUMRDMSR} */
376static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
377{
378 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
379 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
380 * what we want? */
381 *puValue = TMCpuTickGet(pVCpu);
382#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
383 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
384#endif
385 return VINF_SUCCESS;
386}
387
388
389/** @callback_method_impl{FNCPUMWRMSR} */
390static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
391{
392 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
393 /** @todo Write APERF: Calc adjustment. */
394 return VINF_SUCCESS;
395}
396
397
398/**
399 * Get fixed IA32_MTRR_CAP value for NEM and cpumMsrRd_Ia32MtrrCap.
400 *
401 * @returns Fixed IA32_MTRR_CAP value.
402 * @param pVCpu The cross context per CPU structure.
403 */
404VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PVMCPU pVCpu)
405{
406 RT_NOREF_PV(pVCpu);
407
408 /* This is currently a bit weird. :-) */
409 uint8_t const cVariableRangeRegs = 0;
410 bool const fSystemManagementRangeRegisters = false;
411 bool const fFixedRangeRegisters = false;
412 bool const fWriteCombiningType = false;
413 return cVariableRangeRegs
414 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
415 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
416 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
417}
418
419/** @callback_method_impl{FNCPUMRDMSR} */
420static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
421{
422 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
423 *puValue = CPUMGetGuestIa32MtrrCap(pVCpu);
424 return VINF_SUCCESS;
425}
426
427
428/** @callback_method_impl{FNCPUMRDMSR} */
429static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
430{
431 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
432 /** @todo Implement variable MTRR storage. */
433 Assert(pRange->uValue == (idMsr - 0x200) / 2);
434 *puValue = 0;
435 return VINF_SUCCESS;
436}
437
438
439/** @callback_method_impl{FNCPUMWRMSR} */
440static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
441{
442 /*
443 * Validate the value.
444 */
445 Assert(pRange->uValue == (idMsr - 0x200) / 2);
446 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
447
448 uint8_t uType = uValue & 0xff;
449 if ((uType >= 7) || (uType == 2) || (uType == 3))
450 {
451 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uType));
452 return VERR_CPUM_RAISE_GP_0;
453 }
454
455 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
456 if (fInvPhysMask & uValue)
457 {
458 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
459 idMsr, uValue, uValue & fInvPhysMask));
460 return VERR_CPUM_RAISE_GP_0;
461 }
462
463 /*
464 * Store it.
465 */
466 /** @todo Implement variable MTRR storage. */
467 return VINF_SUCCESS;
468}
469
470
471/** @callback_method_impl{FNCPUMRDMSR} */
472static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
473{
474 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
475 /** @todo Implement variable MTRR storage. */
476 Assert(pRange->uValue == (idMsr - 0x200) / 2);
477 *puValue = 0;
478 return VINF_SUCCESS;
479}
480
481
482/** @callback_method_impl{FNCPUMWRMSR} */
483static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
484{
485 /*
486 * Validate the value.
487 */
488 Assert(pRange->uValue == (idMsr - 0x200) / 2);
489 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
490
491 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
492 if (fInvPhysMask & uValue)
493 {
494 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
495 idMsr, uValue, uValue & fInvPhysMask));
496 return VERR_CPUM_RAISE_GP_0;
497 }
498
499 /*
500 * Store it.
501 */
502 /** @todo Implement variable MTRR storage. */
503 return VINF_SUCCESS;
504}
505
506
507/** @callback_method_impl{FNCPUMRDMSR} */
508static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
509{
510 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
511 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
512 *puValue = *puFixedMtrr;
513 return VINF_SUCCESS;
514}
515
516
517/** @callback_method_impl{FNCPUMWRMSR} */
518static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
519{
520 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
521 RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue);
522
523 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
524 {
525 uint8_t uType = (uint8_t)(uValue >> cShift);
526 if ((uType >= 7) || (uType == 2) || (uType == 3))
527 {
528 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
529 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
530 return VERR_CPUM_RAISE_GP_0;
531 }
532 }
533 *puFixedMtrr = uValue;
534 return VINF_SUCCESS;
535}
536
537
538/** @callback_method_impl{FNCPUMRDMSR} */
539static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
540{
541 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
542 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
543 return VINF_SUCCESS;
544}
545
546
547/** @callback_method_impl{FNCPUMWRMSR} */
548static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
549{
550 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
551
552 uint8_t uType = uValue & 0xff;
553 if ((uType >= 7) || (uType == 2) || (uType == 3))
554 {
555 Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uType));
556 return VERR_CPUM_RAISE_GP_0;
557 }
558
559 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
560 return VINF_SUCCESS;
561}
562
563
564/** @callback_method_impl{FNCPUMRDMSR} */
565static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
566{
567 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
568 *puValue = pVCpu->cpum.s.Guest.msrPAT;
569 return VINF_SUCCESS;
570}
571
572
573/** @callback_method_impl{FNCPUMWRMSR} */
574static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
575{
576 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
577 if (CPUMIsPatMsrValid(uValue))
578 {
579 pVCpu->cpum.s.Guest.msrPAT = uValue;
580 return VINF_SUCCESS;
581 }
582 return VERR_CPUM_RAISE_GP_0;
583}
584
585
586/** @callback_method_impl{FNCPUMRDMSR} */
587static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
588{
589 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
590 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
591 return VINF_SUCCESS;
592}
593
594
595/** @callback_method_impl{FNCPUMWRMSR} */
596static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
597{
598 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
599
600 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
601 there are generally 32-bit working bits backing this register. */
602 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
603 return VINF_SUCCESS;
604}
605
606
607/** @callback_method_impl{FNCPUMRDMSR} */
608static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
609{
610 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
611 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
612 return VINF_SUCCESS;
613}
614
615
616/** @callback_method_impl{FNCPUMWRMSR} */
617static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
618{
619 if (X86_IS_CANONICAL(uValue))
620 {
621 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
622 return VINF_SUCCESS;
623 }
624 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
625 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
626 return VERR_CPUM_RAISE_GP_0;
627}
628
629
630/** @callback_method_impl{FNCPUMRDMSR} */
631static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
632{
633 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
634 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
635 return VINF_SUCCESS;
636}
637
638
639/** @callback_method_impl{FNCPUMWRMSR} */
640static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
641{
642 if (X86_IS_CANONICAL(uValue))
643 {
644 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
645 return VINF_SUCCESS;
646 }
647#ifdef IN_RING3
648 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
649#else
650 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
651#endif
652 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
653 return VERR_CPUM_RAISE_GP_0;
654}
655
656
657/** @callback_method_impl{FNCPUMRDMSR} */
658static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
659{
660#if 0 /** @todo implement machine checks. */
661 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
662#else
663 *puValue = 0;
664#endif
665 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
666 return VINF_SUCCESS;
667}
668
669
670/** @callback_method_impl{FNCPUMRDMSR} */
671static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
672{
673 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
674 /** @todo implement machine checks. */
675 *puValue = 0;
676 return VINF_SUCCESS;
677}
678
679
680/** @callback_method_impl{FNCPUMWRMSR} */
681static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
682{
683 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
684 /** @todo implement machine checks. */
685 return VINF_SUCCESS;
686}
687
688
689/** @callback_method_impl{FNCPUMRDMSR} */
690static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
691{
692 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
693 /** @todo implement machine checks. */
694 *puValue = 0;
695 return VINF_SUCCESS;
696}
697
698
699/** @callback_method_impl{FNCPUMWRMSR} */
700static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
701{
702 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
703 /** @todo implement machine checks. */
704 return VINF_SUCCESS;
705}
706
707
708/** @callback_method_impl{FNCPUMRDMSR} */
709static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
710{
711 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
712 /** @todo implement IA32_DEBUGCTL. */
713 *puValue = 0;
714 return VINF_SUCCESS;
715}
716
717
718/** @callback_method_impl{FNCPUMWRMSR} */
719static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
720{
721 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
722 /** @todo implement IA32_DEBUGCTL. */
723 return VINF_SUCCESS;
724}
725
726
727/** @callback_method_impl{FNCPUMRDMSR} */
728static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
729{
730 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
731 /** @todo implement intel SMM. */
732 *puValue = 0;
733 return VINF_SUCCESS;
734}
735
736
737/** @callback_method_impl{FNCPUMWRMSR} */
738static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
739{
740 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
741 /** @todo implement intel SMM. */
742 return VERR_CPUM_RAISE_GP_0;
743}
744
745
746/** @callback_method_impl{FNCPUMRDMSR} */
747static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
748{
749 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
750 /** @todo implement intel SMM. */
751 *puValue = 0;
752 return VINF_SUCCESS;
753}
754
755
756/** @callback_method_impl{FNCPUMWRMSR} */
757static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
758{
759 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
760 /** @todo implement intel SMM. */
761 return VERR_CPUM_RAISE_GP_0;
762}
763
764
765/** @callback_method_impl{FNCPUMRDMSR} */
766static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
767{
768 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
769 /** @todo implement intel direct cache access (DCA)?? */
770 *puValue = 0;
771 return VINF_SUCCESS;
772}
773
774
775/** @callback_method_impl{FNCPUMWRMSR} */
776static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
777{
778 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
779 /** @todo implement intel direct cache access (DCA)?? */
780 return VINF_SUCCESS;
781}
782
783
784/** @callback_method_impl{FNCPUMRDMSR} */
785static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
786{
787 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
788 /** @todo implement intel direct cache access (DCA)?? */
789 *puValue = 0;
790 return VINF_SUCCESS;
791}
792
793
794/** @callback_method_impl{FNCPUMRDMSR} */
795static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
796{
797 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
798 /** @todo implement intel direct cache access (DCA)?? */
799 *puValue = 0;
800 return VINF_SUCCESS;
801}
802
803
804/** @callback_method_impl{FNCPUMWRMSR} */
805static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
806{
807 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
808 /** @todo implement intel direct cache access (DCA)?? */
809 return VINF_SUCCESS;
810}
811
812
813/** @callback_method_impl{FNCPUMRDMSR} */
814static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
815{
816 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
817 /** @todo implement IA32_PERFEVTSEL0+. */
818 *puValue = 0;
819 return VINF_SUCCESS;
820}
821
822
823/** @callback_method_impl{FNCPUMWRMSR} */
824static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
825{
826 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
827 /** @todo implement IA32_PERFEVTSEL0+. */
828 return VINF_SUCCESS;
829}
830
831
832/** @callback_method_impl{FNCPUMRDMSR} */
833static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
834{
835 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
836 uint64_t uValue = pRange->uValue;
837
838 /* Always provide the max bus ratio for now. XNU expects it. */
839 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
840
841 PVM pVM = pVCpu->CTX_SUFF(pVM);
842 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
843 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
844 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
845 if (uTscRatio > 0x1f)
846 uTscRatio = 0x1f;
847 uValue |= (uint64_t)uTscRatio << 40;
848
849 *puValue = uValue;
850 return VINF_SUCCESS;
851}
852
853
854/** @callback_method_impl{FNCPUMWRMSR} */
855static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
856{
857 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
858 /* Pentium4 allows writing, but all bits are ignored. */
859 return VINF_SUCCESS;
860}
861
862
863/** @callback_method_impl{FNCPUMRDMSR} */
864static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
865{
866 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
867 /** @todo implement IA32_PERFCTL. */
868 *puValue = 0;
869 return VINF_SUCCESS;
870}
871
872
873/** @callback_method_impl{FNCPUMWRMSR} */
874static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
875{
876 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
877 /** @todo implement IA32_PERFCTL. */
878 return VINF_SUCCESS;
879}
880
881
882/** @callback_method_impl{FNCPUMRDMSR} */
883static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
884{
885 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
886 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
887 *puValue = 0;
888 return VINF_SUCCESS;
889}
890
891
892/** @callback_method_impl{FNCPUMWRMSR} */
893static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
894{
895 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
896 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
897 return VINF_SUCCESS;
898}
899
900
901/** @callback_method_impl{FNCPUMRDMSR} */
902static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
903{
904 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
905 /** @todo implement performance counters. */
906 *puValue = 0;
907 return VINF_SUCCESS;
908}
909
910
911/** @callback_method_impl{FNCPUMWRMSR} */
912static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
913{
914 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
915 /** @todo implement performance counters. */
916 return VINF_SUCCESS;
917}
918
919
920/** @callback_method_impl{FNCPUMRDMSR} */
921static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
922{
923 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
924 /** @todo implement performance counters. */
925 *puValue = 0;
926 return VINF_SUCCESS;
927}
928
929
930/** @callback_method_impl{FNCPUMWRMSR} */
931static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
932{
933 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
934 /** @todo implement performance counters. */
935 return VINF_SUCCESS;
936}
937
938
939/** @callback_method_impl{FNCPUMRDMSR} */
940static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
941{
942 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
943 /** @todo implement performance counters. */
944 *puValue = 0;
945 return VINF_SUCCESS;
946}
947
948
949/** @callback_method_impl{FNCPUMWRMSR} */
950static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
951{
952 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
953 /** @todo implement performance counters. */
954 return VINF_SUCCESS;
955}
956
957
958/** @callback_method_impl{FNCPUMRDMSR} */
959static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
960{
961 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
962 /** @todo implement performance counters. */
963 *puValue = 0;
964 return VINF_SUCCESS;
965}
966
967
968/** @callback_method_impl{FNCPUMWRMSR} */
969static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
970{
971 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
972 /** @todo implement performance counters. */
973 return VINF_SUCCESS;
974}
975
976
977/** @callback_method_impl{FNCPUMRDMSR} */
978static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
979{
980 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
981 /** @todo implement performance counters. */
982 *puValue = 0;
983 return VINF_SUCCESS;
984}
985
986
987/** @callback_method_impl{FNCPUMWRMSR} */
988static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
989{
990 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
991 /** @todo implement performance counters. */
992 return VINF_SUCCESS;
993}
994
995
996/** @callback_method_impl{FNCPUMRDMSR} */
997static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
998{
999 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1000 /** @todo implement performance counters. */
1001 *puValue = 0;
1002 return VINF_SUCCESS;
1003}
1004
1005
1006/** @callback_method_impl{FNCPUMWRMSR} */
1007static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1008{
1009 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1010 /** @todo implement performance counters. */
1011 return VINF_SUCCESS;
1012}
1013
1014
1015/** @callback_method_impl{FNCPUMRDMSR} */
1016static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1017{
1018 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1019 /** @todo implement IA32_CLOCK_MODULATION. */
1020 *puValue = 0;
1021 return VINF_SUCCESS;
1022}
1023
1024
1025/** @callback_method_impl{FNCPUMWRMSR} */
1026static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1027{
1028 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1029 /** @todo implement IA32_CLOCK_MODULATION. */
1030 return VINF_SUCCESS;
1031}
1032
1033
1034/** @callback_method_impl{FNCPUMRDMSR} */
1035static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1036{
1037 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1038 /** @todo implement IA32_THERM_INTERRUPT. */
1039 *puValue = 0;
1040 return VINF_SUCCESS;
1041}
1042
1043
1044/** @callback_method_impl{FNCPUMWRMSR} */
1045static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1046{
1047 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1048 /** @todo implement IA32_THERM_STATUS. */
1049 return VINF_SUCCESS;
1050}
1051
1052
1053/** @callback_method_impl{FNCPUMRDMSR} */
1054static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1055{
1056 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1057 /** @todo implement IA32_THERM_STATUS. */
1058 *puValue = 0;
1059 return VINF_SUCCESS;
1060}
1061
1062
1063/** @callback_method_impl{FNCPUMWRMSR} */
1064static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1065{
1066 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1067 /** @todo implement IA32_THERM_INTERRUPT. */
1068 return VINF_SUCCESS;
1069}
1070
1071
1072/** @callback_method_impl{FNCPUMRDMSR} */
1073static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1074{
1075 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1076 /** @todo implement IA32_THERM2_CTL. */
1077 *puValue = 0;
1078 return VINF_SUCCESS;
1079}
1080
1081
1082/** @callback_method_impl{FNCPUMWRMSR} */
1083static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1084{
1085 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1086 /** @todo implement IA32_THERM2_CTL. */
1087 return VINF_SUCCESS;
1088}
1089
1090
1091/** @callback_method_impl{FNCPUMRDMSR} */
1092static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1093{
1094 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1095 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1096 return VINF_SUCCESS;
1097}
1098
1099
1100/** @callback_method_impl{FNCPUMWRMSR} */
1101static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1102{
1103 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1104#ifdef LOG_ENABLED
1105 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1106#endif
1107
1108 /* Unsupported bits are generally ignored and stripped by the MSR range
1109 entry that got us here. So, we just need to preserve fixed bits. */
1110 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
1111 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1112 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
1113
1114 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
1115 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
1116
1117 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1118 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1119 return VINF_SUCCESS;
1120}
1121
1122
1123/** @callback_method_impl{FNCPUMRDMSR} */
1124static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1125{
1126 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange);
1127
1128 /** @todo Implement machine check exception injection. */
1129 switch (idMsr & 3)
1130 {
1131 case 0:
1132 case 1:
1133 *puValue = 0;
1134 break;
1135
1136 /* The ADDR and MISC registers aren't accessible since the
1137 corresponding STATUS bits are zero. */
1138 case 2:
1139 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1140 return VERR_CPUM_RAISE_GP_0;
1141 case 3:
1142 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1143 return VERR_CPUM_RAISE_GP_0;
1144 }
1145 return VINF_SUCCESS;
1146}
1147
1148
1149/** @callback_method_impl{FNCPUMWRMSR} */
1150static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1151{
1152 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1153 switch (idMsr & 3)
1154 {
1155 case 0:
1156 /* Ignore writes to the CTL register. */
1157 break;
1158
1159 case 1:
1160 /* According to specs, the STATUS register can only be written to
1161 with the value 0. VBoxCpuReport thinks different for a
1162 Pentium M Dothan, but implementing according to specs now. */
1163 if (uValue != 0)
1164 {
1165 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1166 return VERR_CPUM_RAISE_GP_0;
1167 }
1168 break;
1169
1170 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1171 Writing 1s will GP. Need to figure out how this relates to the
1172 ADDRV and MISCV status flags. If writing is independent of those
1173 bits, we need to know whether the CPU really implements them since
1174 that is exposed by writing 0 to them.
1175 Implementing the solution with the fewer GPs for now. */
1176 case 2:
1177 if (uValue != 0)
1178 {
1179 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1180 return VERR_CPUM_RAISE_GP_0;
1181 }
1182 break;
1183 case 3:
1184 if (uValue != 0)
1185 {
1186 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1187 return VERR_CPUM_RAISE_GP_0;
1188 }
1189 break;
1190 }
1191 return VINF_SUCCESS;
1192}
1193
1194
1195/** @callback_method_impl{FNCPUMRDMSR} */
1196static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1197{
1198 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1199 /** @todo Implement machine check exception injection. */
1200 *puValue = 0;
1201 return VINF_SUCCESS;
1202}
1203
1204
1205/** @callback_method_impl{FNCPUMWRMSR} */
1206static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1207{
1208 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1209 /** @todo Implement machine check exception injection. */
1210 return VINF_SUCCESS;
1211}
1212
1213
1214/** @callback_method_impl{FNCPUMRDMSR} */
1215static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1216{
1217 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1218 /** @todo implement IA32_DS_AREA. */
1219 *puValue = 0;
1220 return VINF_SUCCESS;
1221}
1222
1223
1224/** @callback_method_impl{FNCPUMWRMSR} */
1225static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1226{
1227 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1228 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1229 return VINF_SUCCESS;
1230}
1231
1232
1233/** @callback_method_impl{FNCPUMRDMSR} */
1234static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1235{
1236 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1237 /** @todo implement TSC deadline timer. */
1238 *puValue = 0;
1239 return VINF_SUCCESS;
1240}
1241
1242
1243/** @callback_method_impl{FNCPUMWRMSR} */
1244static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1245{
1246 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1247 /** @todo implement TSC deadline timer. */
1248 return VINF_SUCCESS;
1249}
1250
1251
1252/** @callback_method_impl{FNCPUMRDMSR} */
1253static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1254{
1255 RT_NOREF_PV(pRange);
1256 return APICReadMsr(pVCpu, idMsr, puValue);
1257}
1258
1259
1260/** @callback_method_impl{FNCPUMWRMSR} */
1261static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1262{
1263 RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1264 return APICWriteMsr(pVCpu, idMsr, uValue);
1265}
1266
1267
1268/** @callback_method_impl{FNCPUMRDMSR} */
1269static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1270{
1271 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1272 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1273 *puValue = 0;
1274 return VINF_SUCCESS;
1275}
1276
1277
1278/** @callback_method_impl{FNCPUMWRMSR} */
1279static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1280{
1281 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1282 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1283 return VINF_SUCCESS;
1284}
1285
1286
1287/** @callback_method_impl{FNCPUMRDMSR} */
1288static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1289{
1290 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1291 *puValue = 0;
1292 return VINF_SUCCESS;
1293}
1294
1295
1296/** @callback_method_impl{FNCPUMRDMSR} */
1297static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1298{
1299 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1300 *puValue = 0;
1301 return VINF_SUCCESS;
1302}
1303
1304
1305/** @callback_method_impl{FNCPUMRDMSR} */
1306static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1307{
1308 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1309 *puValue = 0;
1310 return VINF_SUCCESS;
1311}
1312
1313
1314/** @callback_method_impl{FNCPUMRDMSR} */
1315static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1316{
1317 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1318 *puValue = 0;
1319 return VINF_SUCCESS;
1320}
1321
1322
1323/** @callback_method_impl{FNCPUMRDMSR} */
1324static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1325{
1326 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1327 *puValue = 0;
1328 return VINF_SUCCESS;
1329}
1330
1331
1332/** @callback_method_impl{FNCPUMRDMSR} */
1333static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1334{
1335 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1336 *puValue = 0;
1337 return VINF_SUCCESS;
1338}
1339
1340
1341/** @callback_method_impl{FNCPUMRDMSR} */
1342static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1343{
1344 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1345 *puValue = 0;
1346 return VINF_SUCCESS;
1347}
1348
1349
1350/** @callback_method_impl{FNCPUMRDMSR} */
1351static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1352{
1353 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1354 *puValue = 0;
1355 return VINF_SUCCESS;
1356}
1357
1358
1359/** @callback_method_impl{FNCPUMRDMSR} */
1360static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1361{
1362 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1363 *puValue = 0;
1364 return VINF_SUCCESS;
1365}
1366
1367
1368/** @callback_method_impl{FNCPUMRDMSR} */
1369static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1370{
1371 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1372 *puValue = 0;
1373 return VINF_SUCCESS;
1374}
1375
1376
1377/** @callback_method_impl{FNCPUMRDMSR} */
1378static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1379{
1380 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1381 *puValue = 0;
1382 return VINF_SUCCESS;
1383}
1384
1385
1386/** @callback_method_impl{FNCPUMRDMSR} */
1387static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1388{
1389 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1390 *puValue = 0;
1391 return VINF_SUCCESS;
1392}
1393
1394
1395/** @callback_method_impl{FNCPUMRDMSR} */
1396static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1397{
1398 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1399 *puValue = 0;
1400 return VINF_SUCCESS;
1401}
1402
1403
1404/** @callback_method_impl{FNCPUMRDMSR} */
1405static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1406{
1407 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1408 *puValue = 0;
1409 return VINF_SUCCESS;
1410}
1411
1412
1413/** @callback_method_impl{FNCPUMRDMSR} */
1414static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1415{
1416 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1417 *puValue = 0;
1418 return VINF_SUCCESS;
1419}
1420
1421
1422/** @callback_method_impl{FNCPUMRDMSR} */
1423static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1424{
1425 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1426 *puValue = 0;
1427 return VINF_SUCCESS;
1428}
1429
1430
1431/** @callback_method_impl{FNCPUMRDMSR} */
1432static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1433{
1434 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1435 *puValue = 0;
1436 return VINF_SUCCESS;
1437}
1438
1439
1440/** @callback_method_impl{FNCPUMRDMSR} */
1441static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1442{
1443 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1444 *puValue = 0;
1445 return VINF_SUCCESS;
1446}
1447
1448
1449/** @callback_method_impl{FNCPUMRDMSR} */
1450static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SpecCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1451{
1452 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1453 *puValue = pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
1454 return VINF_SUCCESS;
1455}
1456
1457
1458/** @callback_method_impl{FNCPUMWRMSR} */
1459static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SpecCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1460{
1461 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1462
1463 /* NB: The STIBP bit can be set even when IBRS is present, regardless of whether STIBP is actually implemented. */
1464 if (uValue & ~(MSR_IA32_SPEC_CTRL_F_IBRS | MSR_IA32_SPEC_CTRL_F_STIBP))
1465 {
1466 Log(("CPUM: Invalid IA32_SPEC_CTRL bits (trying to write %#llx)\n", uValue));
1467 return VERR_CPUM_RAISE_GP_0;
1468 }
1469
1470 pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
1471 return VINF_SUCCESS;
1472}
1473
1474
1475/** @callback_method_impl{FNCPUMWRMSR} */
1476static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PredCmd(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1477{
1478 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1479 return VINF_SUCCESS;
1480}
1481
1482
1483/** @callback_method_impl{FNCPUMRDMSR} */
1484static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ArchCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1485{
1486 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1487 *puValue = pVCpu->cpum.s.GuestMsrs.msr.ArchCaps;
1488 return VINF_SUCCESS;
1489}
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502/*
1503 * AMD64
1504 * AMD64
1505 * AMD64
1506 */
1507
1508
1509/** @callback_method_impl{FNCPUMRDMSR} */
1510static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1511{
1512 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1513 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1514 return VINF_SUCCESS;
1515}
1516
1517
1518/** @callback_method_impl{FNCPUMWRMSR} */
1519static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1520{
1521 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1522 uint64_t uValidatedEfer;
1523 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1524 int rc = CPUMQueryValidatedGuestEfer(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.Guest.cr0, uOldEfer, uValue, &uValidatedEfer);
1525 if (RT_FAILURE(rc))
1526 return VERR_CPUM_RAISE_GP_0;
1527
1528 CPUMSetGuestMsrEferNoCheck(pVCpu, uOldEfer, uValidatedEfer);
1529 return VINF_SUCCESS;
1530}
1531
1532
1533/** @callback_method_impl{FNCPUMRDMSR} */
1534static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1535{
1536 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1537 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1538 return VINF_SUCCESS;
1539}
1540
1541
1542/** @callback_method_impl{FNCPUMWRMSR} */
1543static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1544{
1545 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1546 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1547 return VINF_SUCCESS;
1548}
1549
1550
1551/** @callback_method_impl{FNCPUMRDMSR} */
1552static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1553{
1554 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1555 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1556 return VINF_SUCCESS;
1557}
1558
1559
1560/** @callback_method_impl{FNCPUMWRMSR} */
1561static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1562{
1563 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1564 if (!X86_IS_CANONICAL(uValue))
1565 {
1566 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1567 return VERR_CPUM_RAISE_GP_0;
1568 }
1569 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1570 return VINF_SUCCESS;
1571}
1572
1573
1574/** @callback_method_impl{FNCPUMRDMSR} */
1575static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1576{
1577 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1578 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1579 return VINF_SUCCESS;
1580}
1581
1582
1583/** @callback_method_impl{FNCPUMWRMSR} */
1584static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1585{
1586 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1587 if (!X86_IS_CANONICAL(uValue))
1588 {
1589 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1590 return VERR_CPUM_RAISE_GP_0;
1591 }
1592 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1593 return VINF_SUCCESS;
1594}
1595
1596
1597/** @callback_method_impl{FNCPUMRDMSR} */
1598static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1599{
1600 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1601 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1602 return VINF_SUCCESS;
1603}
1604
1605
1606/** @callback_method_impl{FNCPUMWRMSR} */
1607static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1608{
1609 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1610 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1611 return VINF_SUCCESS;
1612}
1613
1614
1615/** @callback_method_impl{FNCPUMRDMSR} */
1616static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1617{
1618 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1619 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1620 return VINF_SUCCESS;
1621}
1622
1623
1624/** @callback_method_impl{FNCPUMWRMSR} */
1625static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1626{
1627 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1628 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1629 return VINF_SUCCESS;
1630}
1631
1632
1633/** @callback_method_impl{FNCPUMRDMSR} */
1634static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1635{
1636 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1637 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1638 return VINF_SUCCESS;
1639}
1640
1641/** @callback_method_impl{FNCPUMWRMSR} */
1642static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1643{
1644 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1645 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1646 return VINF_SUCCESS;
1647}
1648
1649
1650
1651/** @callback_method_impl{FNCPUMRDMSR} */
1652static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1653{
1654 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1655 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1656 return VINF_SUCCESS;
1657}
1658
1659/** @callback_method_impl{FNCPUMWRMSR} */
1660static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1661{
1662 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1663 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1664 return VINF_SUCCESS;
1665}
1666
1667
1668/** @callback_method_impl{FNCPUMRDMSR} */
1669static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1670{
1671 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1672 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1673 return VINF_SUCCESS;
1674}
1675
1676/** @callback_method_impl{FNCPUMWRMSR} */
1677static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1678{
1679 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1680 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1681 return VINF_SUCCESS;
1682}
1683
1684
1685/*
1686 * Intel specific
1687 * Intel specific
1688 * Intel specific
1689 */
1690
1691/** @callback_method_impl{FNCPUMRDMSR} */
1692static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1693{
1694 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1695 /** @todo recalc clock frequency ratio? */
1696 *puValue = pRange->uValue;
1697 return VINF_SUCCESS;
1698}
1699
1700
1701/** @callback_method_impl{FNCPUMWRMSR} */
1702static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1703{
1704 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1705 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1706 return VINF_SUCCESS;
1707}
1708
1709
1710/** @callback_method_impl{FNCPUMRDMSR} */
1711static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1712{
1713 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1714
1715 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1716 have a 4-bit core count. */
1717 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1718 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1719 *puValue = RT_MAKE_U32(cThreads, cCores);
1720 return VINF_SUCCESS;
1721}
1722
1723
1724/** @callback_method_impl{FNCPUMRDMSR} */
1725static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1726{
1727 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1728 /** @todo P4 hard power on config */
1729 *puValue = pRange->uValue;
1730 return VINF_SUCCESS;
1731}
1732
1733
1734/** @callback_method_impl{FNCPUMWRMSR} */
1735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1736{
1737 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1738 /** @todo P4 hard power on config */
1739 return VINF_SUCCESS;
1740}
1741
1742
1743/** @callback_method_impl{FNCPUMRDMSR} */
1744static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1745{
1746 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1747 /** @todo P4 soft power on config */
1748 *puValue = pRange->uValue;
1749 return VINF_SUCCESS;
1750}
1751
1752
1753/** @callback_method_impl{FNCPUMWRMSR} */
1754static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1755{
1756 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1757 /** @todo P4 soft power on config */
1758 return VINF_SUCCESS;
1759}
1760
1761
1762/** @callback_method_impl{FNCPUMRDMSR} */
1763static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1764{
1765 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1766
1767 uint64_t uValue;
1768 PVM pVM = pVCpu->CTX_SUFF(pVM);
1769 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1770 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1771 {
1772 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1773 {
1774 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1775 uValue = 0;
1776 }
1777 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1778 {
1779 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1780 uValue = 1;
1781 }
1782 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1783 {
1784 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1785 uValue = 3;
1786 }
1787 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1788 {
1789 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1790 uValue = 2;
1791 }
1792 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1793 {
1794 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1795 uValue = 0;
1796 }
1797 else
1798 {
1799 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1800 uValue = 6;
1801 }
1802 uValue <<= 16;
1803
1804 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1805 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1806 uValue |= (uint32_t)uTscRatio << 24;
1807
1808 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1809 }
1810 else
1811 {
1812 /* Probably more stuff here, but intel doesn't want to tell us. */
1813 uValue = pRange->uValue;
1814 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1815 }
1816
1817 *puValue = uValue;
1818 return VINF_SUCCESS;
1819}
1820
1821
1822/** @callback_method_impl{FNCPUMWRMSR} */
1823static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1824{
1825 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1826 /** @todo P4 bus frequency config */
1827 return VINF_SUCCESS;
1828}
1829
1830
1831/** @callback_method_impl{FNCPUMRDMSR} */
1832static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1833{
1834 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1835
1836 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1837 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1838 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1839 *puValue = 5;
1840 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1841 *puValue = 1;
1842 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1843 *puValue = 3;
1844 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1845 *puValue = 2;
1846 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1847 *puValue = 0;
1848 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1849 *puValue = 4;
1850 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1851 *puValue = 6;
1852
1853 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1854
1855 return VINF_SUCCESS;
1856}
1857
1858
1859/** @callback_method_impl{FNCPUMRDMSR} */
1860static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1861{
1862 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1863
1864 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1865 PVM pVM = pVCpu->CTX_SUFF(pVM);
1866 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1867 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1868 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1869 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1870 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1871
1872 /* Ivy bridge has a minimum operating ratio as well. */
1873 if (true) /** @todo detect sandy bridge. */
1874 uValue |= (uint64_t)uTscRatio << 48;
1875
1876 *puValue = uValue;
1877 return VINF_SUCCESS;
1878}
1879
1880
1881/** @callback_method_impl{FNCPUMRDMSR} */
1882static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1883{
1884 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1885
1886 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1887
1888 PVM pVM = pVCpu->CTX_SUFF(pVM);
1889 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1890 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1891 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1892 uValue |= (uint32_t)uTscRatio << 8;
1893
1894 *puValue = uValue;
1895 return VINF_SUCCESS;
1896}
1897
1898
1899/** @callback_method_impl{FNCPUMWRMSR} */
1900static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1901{
1902 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1903 /** @todo implement writing MSR_FLEX_RATIO. */
1904 return VINF_SUCCESS;
1905}
1906
1907
1908/** @callback_method_impl{FNCPUMRDMSR} */
1909static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1910{
1911 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1912 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1913 return VINF_SUCCESS;
1914}
1915
1916
1917/** @callback_method_impl{FNCPUMWRMSR} */
1918static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1919{
1920 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1921
1922 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1923 {
1924 Log(("CPUM: WRMSR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1925 return VERR_CPUM_RAISE_GP_0;
1926 }
1927#if 0 /** @todo check what real (old) hardware does. */
1928 if ((uValue & 7) >= 5)
1929 {
1930 Log(("CPUM: WRMSR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1931 return VERR_CPUM_RAISE_GP_0;
1932 }
1933#endif
1934 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1935 return VINF_SUCCESS;
1936}
1937
1938
1939/** @callback_method_impl{FNCPUMRDMSR} */
1940static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1941{
1942 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1943 /** @todo implement I/O mwait wakeup. */
1944 *puValue = 0;
1945 return VINF_SUCCESS;
1946}
1947
1948
1949/** @callback_method_impl{FNCPUMWRMSR} */
1950static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1951{
1952 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1953 /** @todo implement I/O mwait wakeup. */
1954 return VINF_SUCCESS;
1955}
1956
1957
1958/** @callback_method_impl{FNCPUMRDMSR} */
1959static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1960{
1961 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1962 /** @todo implement last branch records. */
1963 *puValue = 0;
1964 return VINF_SUCCESS;
1965}
1966
1967
1968/** @callback_method_impl{FNCPUMWRMSR} */
1969static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1970{
1971 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1972 /** @todo implement last branch records. */
1973 return VINF_SUCCESS;
1974}
1975
1976
1977/** @callback_method_impl{FNCPUMRDMSR} */
1978static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1979{
1980 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1981 /** @todo implement last branch records. */
1982 *puValue = 0;
1983 return VINF_SUCCESS;
1984}
1985
1986
1987/** @callback_method_impl{FNCPUMWRMSR} */
1988static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1989{
1990 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1991 /** @todo implement last branch records. */
1992 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1993 * if the rest of the bits are zero. Automatic sign extending?
1994 * Investigate! */
1995 if (!X86_IS_CANONICAL(uValue))
1996 {
1997 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1998 return VERR_CPUM_RAISE_GP_0;
1999 }
2000 return VINF_SUCCESS;
2001}
2002
2003
2004/** @callback_method_impl{FNCPUMRDMSR} */
2005static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2006{
2007 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2008 /** @todo implement last branch records. */
2009 *puValue = 0;
2010 return VINF_SUCCESS;
2011}
2012
2013
2014/** @callback_method_impl{FNCPUMWRMSR} */
2015static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2016{
2017 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2018 /** @todo implement last branch records. */
2019 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2020 * if the rest of the bits are zero. Automatic sign extending?
2021 * Investigate! */
2022 if (!X86_IS_CANONICAL(uValue))
2023 {
2024 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2025 return VERR_CPUM_RAISE_GP_0;
2026 }
2027 return VINF_SUCCESS;
2028}
2029
2030
2031/** @callback_method_impl{FNCPUMRDMSR} */
2032static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2033{
2034 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2035 /** @todo implement last branch records. */
2036 *puValue = 0;
2037 return VINF_SUCCESS;
2038}
2039
2040
2041/** @callback_method_impl{FNCPUMWRMSR} */
2042static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2043{
2044 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2045 /** @todo implement last branch records. */
2046 return VINF_SUCCESS;
2047}
2048
2049
2050/** @callback_method_impl{FNCPUMRDMSR} */
2051static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2052{
2053 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2054 *puValue = pRange->uValue;
2055 return VINF_SUCCESS;
2056}
2057
2058
2059/** @callback_method_impl{FNCPUMWRMSR} */
2060static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2061{
2062 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2063 return VINF_SUCCESS;
2064}
2065
2066
2067/** @callback_method_impl{FNCPUMRDMSR} */
2068static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2069{
2070 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2071 *puValue = pRange->uValue;
2072 return VINF_SUCCESS;
2073}
2074
2075
2076/** @callback_method_impl{FNCPUMWRMSR} */
2077static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2078{
2079 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2080 return VINF_SUCCESS;
2081}
2082
2083
2084/** @callback_method_impl{FNCPUMRDMSR} */
2085static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2086{
2087 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2088 *puValue = pRange->uValue;
2089 return VINF_SUCCESS;
2090}
2091
2092
2093/** @callback_method_impl{FNCPUMWRMSR} */
2094static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2095{
2096 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2097 return VINF_SUCCESS;
2098}
2099
2100
2101/** @callback_method_impl{FNCPUMRDMSR} */
2102static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2103{
2104 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2105 /** @todo machine check. */
2106 *puValue = pRange->uValue;
2107 return VINF_SUCCESS;
2108}
2109
2110
2111/** @callback_method_impl{FNCPUMWRMSR} */
2112static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2113{
2114 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2115 /** @todo machine check. */
2116 return VINF_SUCCESS;
2117}
2118
2119
2120/** @callback_method_impl{FNCPUMRDMSR} */
2121static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2122{
2123 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2124 *puValue = 0;
2125 return VINF_SUCCESS;
2126}
2127
2128
2129/** @callback_method_impl{FNCPUMWRMSR} */
2130static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2131{
2132 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2133 return VINF_SUCCESS;
2134}
2135
2136
2137/** @callback_method_impl{FNCPUMRDMSR} */
2138static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2139{
2140 RT_NOREF_PV(idMsr);
2141 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
2142 AssertRC(rc);
2143 return VINF_SUCCESS;
2144}
2145
2146
2147/** @callback_method_impl{FNCPUMWRMSR} */
2148static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2149{
2150 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2151 /* This CRx interface differs from the MOV CRx, GReg interface in that
2152 #GP(0) isn't raised if unsupported bits are written to. Instead they
2153 are simply ignored and masked off. (Pentium M Dothan) */
2154 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
2155 * any, gain. */
2156 return VINF_SUCCESS;
2157}
2158
2159
2160/** @callback_method_impl{FNCPUMRDMSR} */
2161static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2162{
2163 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2164 /** @todo implement CPUID masking. */
2165 *puValue = UINT64_MAX;
2166 return VINF_SUCCESS;
2167}
2168
2169
2170/** @callback_method_impl{FNCPUMWRMSR} */
2171static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2172{
2173 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2174 /** @todo implement CPUID masking. */
2175 return VINF_SUCCESS;
2176}
2177
2178
2179/** @callback_method_impl{FNCPUMRDMSR} */
2180static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2181{
2182 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2183 /** @todo implement CPUID masking. */
2184 *puValue = 0;
2185 return VINF_SUCCESS;
2186}
2187
2188
2189/** @callback_method_impl{FNCPUMWRMSR} */
2190static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2191{
2192 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2193 /** @todo implement CPUID masking. */
2194 return VINF_SUCCESS;
2195}
2196
2197
2198
2199/** @callback_method_impl{FNCPUMRDMSR} */
2200static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2201{
2202 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2203 /** @todo implement CPUID masking. */
2204 *puValue = UINT64_MAX;
2205 return VINF_SUCCESS;
2206}
2207
2208
2209/** @callback_method_impl{FNCPUMWRMSR} */
2210static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2211{
2212 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2213 /** @todo implement CPUID masking. */
2214 return VINF_SUCCESS;
2215}
2216
2217
2218
2219/** @callback_method_impl{FNCPUMRDMSR} */
2220static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2221{
2222 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2223 /** @todo implement AES-NI. */
2224 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2225 return VINF_SUCCESS;
2226}
2227
2228
2229/** @callback_method_impl{FNCPUMWRMSR} */
2230static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2231{
2232 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2233 /** @todo implement AES-NI. */
2234 return VERR_CPUM_RAISE_GP_0;
2235}
2236
2237
2238/** @callback_method_impl{FNCPUMRDMSR} */
2239static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2240{
2241 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2242 /** @todo implement intel C states. */
2243 *puValue = pRange->uValue;
2244 return VINF_SUCCESS;
2245}
2246
2247
2248/** @callback_method_impl{FNCPUMWRMSR} */
2249static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2250{
2251 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2252 /** @todo implement intel C states. */
2253 return VINF_SUCCESS;
2254}
2255
2256
2257/** @callback_method_impl{FNCPUMRDMSR} */
2258static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2259{
2260 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2261 /** @todo implement last-branch-records. */
2262 *puValue = 0;
2263 return VINF_SUCCESS;
2264}
2265
2266
2267/** @callback_method_impl{FNCPUMWRMSR} */
2268static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2269{
2270 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2271 /** @todo implement last-branch-records. */
2272 return VINF_SUCCESS;
2273}
2274
2275
2276/** @callback_method_impl{FNCPUMRDMSR} */
2277static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2278{
2279 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2280 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2281 *puValue = 0;
2282 return VINF_SUCCESS;
2283}
2284
2285
2286/** @callback_method_impl{FNCPUMWRMSR} */
2287static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2288{
2289 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2290 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2291 return VINF_SUCCESS;
2292}
2293
2294
2295/** @callback_method_impl{FNCPUMRDMSR} */
2296static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2297{
2298 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2299 /** @todo implement memory VLW? */
2300 *puValue = pRange->uValue;
2301 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2302 AAJ49/AAK51/????, which documents the inversion of this bit. The
2303 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2304 that correct things. Some guesses at the other bits:
2305 bit 2 = INTR
2306 bit 4 = SMI
2307 bit 5 = INIT
2308 bit 6 = NMI */
2309 return VINF_SUCCESS;
2310}
2311
2312
2313/** @callback_method_impl{FNCPUMRDMSR} */
2314static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2315{
2316 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2317 /** @todo intel power management */
2318 *puValue = 0;
2319 return VINF_SUCCESS;
2320}
2321
2322
2323/** @callback_method_impl{FNCPUMWRMSR} */
2324static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2325{
2326 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2327 /** @todo intel power management */
2328 return VINF_SUCCESS;
2329}
2330
2331
2332/** @callback_method_impl{FNCPUMRDMSR} */
2333static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2334{
2335 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2336 /** @todo intel performance counters. */
2337 *puValue = 0;
2338 return VINF_SUCCESS;
2339}
2340
2341
2342/** @callback_method_impl{FNCPUMWRMSR} */
2343static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2344{
2345 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2346 /** @todo intel performance counters. */
2347 return VINF_SUCCESS;
2348}
2349
2350
2351/** @callback_method_impl{FNCPUMRDMSR} */
2352static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2353{
2354 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2355 /** @todo intel performance counters. */
2356 *puValue = 0;
2357 return VINF_SUCCESS;
2358}
2359
2360
2361/** @callback_method_impl{FNCPUMWRMSR} */
2362static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2363{
2364 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2365 /** @todo intel performance counters. */
2366 return VINF_SUCCESS;
2367}
2368
2369
2370/** @callback_method_impl{FNCPUMRDMSR} */
2371static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2372{
2373 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2374 /** @todo intel power management. */
2375 *puValue = 0;
2376 return VINF_SUCCESS;
2377}
2378
2379
2380/** @callback_method_impl{FNCPUMRDMSR} */
2381static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2382{
2383 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2384 /** @todo intel power management. */
2385 *puValue = 0;
2386 return VINF_SUCCESS;
2387}
2388
2389
2390/** @callback_method_impl{FNCPUMRDMSR} */
2391static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2392{
2393 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2394 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2395 *puValue = 0;
2396 return VINF_SUCCESS;
2397}
2398
2399
2400/** @callback_method_impl{FNCPUMWRMSR} */
2401static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2402{
2403 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2404 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2405 return VINF_SUCCESS;
2406}
2407
2408
2409/** @callback_method_impl{FNCPUMRDMSR} */
2410static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2411{
2412 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2413 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2414 *puValue = 0;
2415 return VINF_SUCCESS;
2416}
2417
2418
2419/** @callback_method_impl{FNCPUMWRMSR} */
2420static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2421{
2422 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2423 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2424 return VINF_SUCCESS;
2425}
2426
2427
2428/** @callback_method_impl{FNCPUMRDMSR} */
2429static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2430{
2431 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2432 /** @todo intel RAPL. */
2433 *puValue = pRange->uValue;
2434 return VINF_SUCCESS;
2435}
2436
2437
2438/** @callback_method_impl{FNCPUMWRMSR} */
2439static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2440{
2441 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2442 /* Note! This is documented as read only and except for a Silvermont sample has
2443 always been classified as read only. This is just here to make it compile. */
2444 return VINF_SUCCESS;
2445}
2446
2447
2448/** @callback_method_impl{FNCPUMRDMSR} */
2449static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2450{
2451 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2452 /** @todo intel power management. */
2453 *puValue = 0;
2454 return VINF_SUCCESS;
2455}
2456
2457
2458/** @callback_method_impl{FNCPUMWRMSR} */
2459static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2460{
2461 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2462 /** @todo intel power management. */
2463 return VINF_SUCCESS;
2464}
2465
2466
2467/** @callback_method_impl{FNCPUMRDMSR} */
2468static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2469{
2470 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2471 /** @todo intel power management. */
2472 *puValue = 0;
2473 return VINF_SUCCESS;
2474}
2475
2476
2477/** @callback_method_impl{FNCPUMWRMSR} */
2478static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2479{
2480 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2481 /* Note! This is documented as read only and except for a Silvermont sample has
2482 always been classified as read only. This is just here to make it compile. */
2483 return VINF_SUCCESS;
2484}
2485
2486
2487/** @callback_method_impl{FNCPUMRDMSR} */
2488static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2489{
2490 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2491 /** @todo intel RAPL. */
2492 *puValue = 0;
2493 return VINF_SUCCESS;
2494}
2495
2496
2497/** @callback_method_impl{FNCPUMWRMSR} */
2498static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2499{
2500 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2501 /** @todo intel RAPL. */
2502 return VINF_SUCCESS;
2503}
2504
2505
2506/** @callback_method_impl{FNCPUMRDMSR} */
2507static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2508{
2509 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2510 /** @todo intel power management. */
2511 *puValue = 0;
2512 return VINF_SUCCESS;
2513}
2514
2515
2516/** @callback_method_impl{FNCPUMRDMSR} */
2517static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2518{
2519 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2520 /** @todo intel power management. */
2521 *puValue = 0;
2522 return VINF_SUCCESS;
2523}
2524
2525
2526/** @callback_method_impl{FNCPUMRDMSR} */
2527static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2528{
2529 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2530 /** @todo intel power management. */
2531 *puValue = 0;
2532 return VINF_SUCCESS;
2533}
2534
2535
2536/** @callback_method_impl{FNCPUMRDMSR} */
2537static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2538{
2539 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2540 /** @todo intel RAPL. */
2541 *puValue = 0;
2542 return VINF_SUCCESS;
2543}
2544
2545
2546/** @callback_method_impl{FNCPUMWRMSR} */
2547static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2548{
2549 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2550 /** @todo intel RAPL. */
2551 return VINF_SUCCESS;
2552}
2553
2554
2555/** @callback_method_impl{FNCPUMRDMSR} */
2556static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2557{
2558 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2559 /** @todo intel power management. */
2560 *puValue = 0;
2561 return VINF_SUCCESS;
2562}
2563
2564
2565/** @callback_method_impl{FNCPUMRDMSR} */
2566static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2567{
2568 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2569 /** @todo intel power management. */
2570 *puValue = 0;
2571 return VINF_SUCCESS;
2572}
2573
2574
2575/** @callback_method_impl{FNCPUMRDMSR} */
2576static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2577{
2578 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2579 /** @todo intel power management. */
2580 *puValue = 0;
2581 return VINF_SUCCESS;
2582}
2583
2584
2585/** @callback_method_impl{FNCPUMRDMSR} */
2586static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2587{
2588 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2589 /** @todo intel RAPL. */
2590 *puValue = 0;
2591 return VINF_SUCCESS;
2592}
2593
2594
2595/** @callback_method_impl{FNCPUMWRMSR} */
2596static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2597{
2598 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2599 /** @todo intel RAPL. */
2600 return VINF_SUCCESS;
2601}
2602
2603
2604/** @callback_method_impl{FNCPUMRDMSR} */
2605static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2606{
2607 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2608 /** @todo intel power management. */
2609 *puValue = 0;
2610 return VINF_SUCCESS;
2611}
2612
2613
2614/** @callback_method_impl{FNCPUMRDMSR} */
2615static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2616{
2617 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2618 /** @todo intel RAPL. */
2619 *puValue = 0;
2620 return VINF_SUCCESS;
2621}
2622
2623
2624/** @callback_method_impl{FNCPUMWRMSR} */
2625static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2626{
2627 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2628 /** @todo intel RAPL. */
2629 return VINF_SUCCESS;
2630}
2631
2632
2633/** @callback_method_impl{FNCPUMRDMSR} */
2634static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2635{
2636 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2637 /** @todo intel power management. */
2638 *puValue = 0;
2639 return VINF_SUCCESS;
2640}
2641
2642
2643/** @callback_method_impl{FNCPUMRDMSR} */
2644static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2645{
2646 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2647 /** @todo intel RAPL. */
2648 *puValue = 0;
2649 return VINF_SUCCESS;
2650}
2651
2652
2653/** @callback_method_impl{FNCPUMWRMSR} */
2654static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2655{
2656 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2657 /** @todo intel RAPL. */
2658 return VINF_SUCCESS;
2659}
2660
2661
2662/** @callback_method_impl{FNCPUMRDMSR} */
2663static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2664{
2665 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2666 /** @todo intel power management. */
2667 *puValue = 0;
2668 return VINF_SUCCESS;
2669}
2670
2671
2672/** @callback_method_impl{FNCPUMRDMSR} */
2673static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2674{
2675 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2676 /** @todo intel RAPL. */
2677 *puValue = 0;
2678 return VINF_SUCCESS;
2679}
2680
2681
2682/** @callback_method_impl{FNCPUMWRMSR} */
2683static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2684{
2685 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2686 /** @todo intel RAPL. */
2687 return VINF_SUCCESS;
2688}
2689
2690
2691/** @callback_method_impl{FNCPUMRDMSR} */
2692static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2693{
2694 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2695 /** @todo intel power management. */
2696 *puValue = pRange->uValue;
2697 return VINF_SUCCESS;
2698}
2699
2700
2701/** @callback_method_impl{FNCPUMRDMSR} */
2702static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2703{
2704 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2705 /** @todo intel power management. */
2706 *puValue = pRange->uValue;
2707 return VINF_SUCCESS;
2708}
2709
2710
2711/** @callback_method_impl{FNCPUMRDMSR} */
2712static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2713{
2714 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2715 /** @todo intel power management. */
2716 *puValue = pRange->uValue;
2717 return VINF_SUCCESS;
2718}
2719
2720
2721/** @callback_method_impl{FNCPUMRDMSR} */
2722static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2723{
2724 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2725 /** @todo intel power management. */
2726 *puValue = 0;
2727 return VINF_SUCCESS;
2728}
2729
2730
2731/** @callback_method_impl{FNCPUMWRMSR} */
2732static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2733{
2734 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2735 /** @todo intel power management. */
2736 return VINF_SUCCESS;
2737}
2738
2739
2740/** @callback_method_impl{FNCPUMRDMSR} */
2741static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2742{
2743 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2744 /** @todo intel power management. */
2745 *puValue = 0;
2746 return VINF_SUCCESS;
2747}
2748
2749
2750/** @callback_method_impl{FNCPUMWRMSR} */
2751static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2752{
2753 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2754 /** @todo intel power management. */
2755 return VINF_SUCCESS;
2756}
2757
2758
2759/** @callback_method_impl{FNCPUMRDMSR} */
2760static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2761{
2762 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2763 /** @todo uncore msrs. */
2764 *puValue = 0;
2765 return VINF_SUCCESS;
2766}
2767
2768
2769/** @callback_method_impl{FNCPUMWRMSR} */
2770static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2771{
2772 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2773 /** @todo uncore msrs. */
2774 return VINF_SUCCESS;
2775}
2776
2777
2778/** @callback_method_impl{FNCPUMRDMSR} */
2779static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2780{
2781 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2782 /** @todo uncore msrs. */
2783 *puValue = 0;
2784 return VINF_SUCCESS;
2785}
2786
2787
2788/** @callback_method_impl{FNCPUMWRMSR} */
2789static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2790{
2791 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2792 /** @todo uncore msrs. */
2793 return VINF_SUCCESS;
2794}
2795
2796
2797/** @callback_method_impl{FNCPUMRDMSR} */
2798static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2799{
2800 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2801 /** @todo uncore msrs. */
2802 *puValue = 0;
2803 return VINF_SUCCESS;
2804}
2805
2806
2807/** @callback_method_impl{FNCPUMWRMSR} */
2808static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2809{
2810 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2811 /** @todo uncore msrs. */
2812 return VINF_SUCCESS;
2813}
2814
2815
2816/** @callback_method_impl{FNCPUMRDMSR} */
2817static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2818{
2819 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2820 /** @todo uncore msrs. */
2821 *puValue = 0;
2822 return VINF_SUCCESS;
2823}
2824
2825
2826/** @callback_method_impl{FNCPUMWRMSR} */
2827static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2828{
2829 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2830 /** @todo uncore msrs. */
2831 return VINF_SUCCESS;
2832}
2833
2834
2835/** @callback_method_impl{FNCPUMRDMSR} */
2836static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2837{
2838 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2839 /** @todo uncore msrs. */
2840 *puValue = 0;
2841 return VINF_SUCCESS;
2842}
2843
2844
2845/** @callback_method_impl{FNCPUMWRMSR} */
2846static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2847{
2848 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2849 /** @todo uncore msrs. */
2850 return VINF_SUCCESS;
2851}
2852
2853
2854/** @callback_method_impl{FNCPUMRDMSR} */
2855static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2856{
2857 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2858 /** @todo uncore msrs. */
2859 *puValue = 0;
2860 return VINF_SUCCESS;
2861}
2862
2863
2864/** @callback_method_impl{FNCPUMRDMSR} */
2865static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2866{
2867 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2868 /** @todo uncore msrs. */
2869 *puValue = 0;
2870 return VINF_SUCCESS;
2871}
2872
2873
2874/** @callback_method_impl{FNCPUMWRMSR} */
2875static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2876{
2877 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2878 /** @todo uncore msrs. */
2879 return VINF_SUCCESS;
2880}
2881
2882
2883/** @callback_method_impl{FNCPUMRDMSR} */
2884static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2885{
2886 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2887 /** @todo uncore msrs. */
2888 *puValue = 0;
2889 return VINF_SUCCESS;
2890}
2891
2892
2893/** @callback_method_impl{FNCPUMWRMSR} */
2894static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2895{
2896 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2897 /** @todo uncore msrs. */
2898 return VINF_SUCCESS;
2899}
2900
2901
2902/** @callback_method_impl{FNCPUMRDMSR} */
2903static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2904{
2905 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2906
2907 /*
2908 * 31:0 is SMI count (read only), 63:32 reserved.
2909 * Since we don't do SMI, the count is always zero.
2910 */
2911 *puValue = 0;
2912 return VINF_SUCCESS;
2913}
2914
2915
2916/** @callback_method_impl{FNCPUMRDMSR} */
2917static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2918{
2919 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2920 /** @todo implement enhanced multi thread termal monitoring? */
2921 *puValue = pRange->uValue;
2922 return VINF_SUCCESS;
2923}
2924
2925
2926/** @callback_method_impl{FNCPUMWRMSR} */
2927static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2928{
2929 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2930 /** @todo implement enhanced multi thread termal monitoring? */
2931 return VINF_SUCCESS;
2932}
2933
2934
2935/** @callback_method_impl{FNCPUMRDMSR} */
2936static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2937{
2938 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2939 /** @todo SMM & C-states? */
2940 *puValue = 0;
2941 return VINF_SUCCESS;
2942}
2943
2944
2945/** @callback_method_impl{FNCPUMWRMSR} */
2946static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2947{
2948 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2949 /** @todo SMM & C-states? */
2950 return VINF_SUCCESS;
2951}
2952
2953
2954/** @callback_method_impl{FNCPUMRDMSR} */
2955static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2956{
2957 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2958 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2959 *puValue = 0;
2960 return VINF_SUCCESS;
2961}
2962
2963
2964/** @callback_method_impl{FNCPUMWRMSR} */
2965static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2966{
2967 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2968 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2969 return VINF_SUCCESS;
2970}
2971
2972
2973/** @callback_method_impl{FNCPUMRDMSR} */
2974static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2975{
2976 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2977 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2978 *puValue = 0;
2979 return VINF_SUCCESS;
2980}
2981
2982
2983/** @callback_method_impl{FNCPUMWRMSR} */
2984static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2985{
2986 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2987 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2988 return VINF_SUCCESS;
2989}
2990
2991
2992/** @callback_method_impl{FNCPUMRDMSR} */
2993static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2994{
2995 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2996 /** @todo Core2+ platform environment control interface control register? */
2997 *puValue = 0;
2998 return VINF_SUCCESS;
2999}
3000
3001
3002/** @callback_method_impl{FNCPUMWRMSR} */
3003static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3004{
3005 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3006 /** @todo Core2+ platform environment control interface control register? */
3007 return VINF_SUCCESS;
3008}
3009
3010
3011/** @callback_method_impl{FNCPUMRDMSR} */
3012static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3013{
3014 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3015 *puValue = 0;
3016 return VINF_SUCCESS;
3017}
3018
3019
3020/*
3021 * Multiple vendor P6 MSRs.
3022 * Multiple vendor P6 MSRs.
3023 * Multiple vendor P6 MSRs.
3024 *
3025 * These MSRs were introduced with the P6 but not elevated to architectural
3026 * MSRs, despite other vendors implementing them.
3027 */
3028
3029
3030/** @callback_method_impl{FNCPUMRDMSR} */
3031static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3032{
3033 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3034 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
3035 if I read the docs correctly, thus the need for separate functions. */
3036 /** @todo implement last branch records. */
3037 *puValue = 0;
3038 return VINF_SUCCESS;
3039}
3040
3041
3042/** @callback_method_impl{FNCPUMRDMSR} */
3043static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3044{
3045 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3046 /** @todo implement last branch records. */
3047 *puValue = 0;
3048 return VINF_SUCCESS;
3049}
3050
3051
3052/** @callback_method_impl{FNCPUMRDMSR} */
3053static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3054{
3055 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3056 /** @todo implement last exception records. */
3057 *puValue = 0;
3058 return VINF_SUCCESS;
3059}
3060
3061
3062/** @callback_method_impl{FNCPUMWRMSR} */
3063static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3064{
3065 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3066 /** @todo implement last exception records. */
3067 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
3068 a non-cannonical address. */
3069 return VINF_SUCCESS;
3070}
3071
3072
3073/** @callback_method_impl{FNCPUMRDMSR} */
3074static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3075{
3076 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3077 /** @todo implement last exception records. */
3078 *puValue = 0;
3079 return VINF_SUCCESS;
3080}
3081
3082
3083/** @callback_method_impl{FNCPUMWRMSR} */
3084static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3085{
3086 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3087 /** @todo implement last exception records. */
3088 return VINF_SUCCESS;
3089}
3090
3091
3092
3093/*
3094 * AMD specific
3095 * AMD specific
3096 * AMD specific
3097 */
3098
3099
3100/** @callback_method_impl{FNCPUMRDMSR} */
3101static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3102{
3103 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3104 /** @todo Implement TscRateMsr */
3105 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
3106 return VINF_SUCCESS;
3107}
3108
3109
3110/** @callback_method_impl{FNCPUMWRMSR} */
3111static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3112{
3113 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3114 /** @todo Implement TscRateMsr */
3115 return VINF_SUCCESS;
3116}
3117
3118
3119/** @callback_method_impl{FNCPUMRDMSR} */
3120static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3121{
3122 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3123 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3124 /* Note: Only listes in BKDG for Family 15H. */
3125 *puValue = 0;
3126 return VINF_SUCCESS;
3127}
3128
3129
3130/** @callback_method_impl{FNCPUMWRMSR} */
3131static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3132{
3133 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3134 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3135 return VINF_SUCCESS;
3136}
3137
3138
3139/** @callback_method_impl{FNCPUMRDMSR} */
3140static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3141{
3142 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3143 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3144 /* Note: Only listes in BKDG for Family 15H. */
3145 *puValue = 0;
3146 return VINF_SUCCESS;
3147}
3148
3149
3150/** @callback_method_impl{FNCPUMWRMSR} */
3151static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3152{
3153 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3154 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3155 return VINF_SUCCESS;
3156}
3157
3158
3159/** @callback_method_impl{FNCPUMRDMSR} */
3160static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3161{
3162 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3163 /** @todo machine check. */
3164 *puValue = 0;
3165 return VINF_SUCCESS;
3166}
3167
3168
3169/** @callback_method_impl{FNCPUMWRMSR} */
3170static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3171{
3172 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3173 /** @todo machine check. */
3174 return VINF_SUCCESS;
3175}
3176
3177
3178/** @callback_method_impl{FNCPUMRDMSR} */
3179static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3180{
3181 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3182 /** @todo AMD performance events. */
3183 *puValue = 0;
3184 return VINF_SUCCESS;
3185}
3186
3187
3188/** @callback_method_impl{FNCPUMWRMSR} */
3189static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3190{
3191 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3192 /** @todo AMD performance events. */
3193 return VINF_SUCCESS;
3194}
3195
3196
3197/** @callback_method_impl{FNCPUMRDMSR} */
3198static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3199{
3200 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3201 /** @todo AMD performance events. */
3202 *puValue = 0;
3203 return VINF_SUCCESS;
3204}
3205
3206
3207/** @callback_method_impl{FNCPUMWRMSR} */
3208static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3209{
3210 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3211 /** @todo AMD performance events. */
3212 return VINF_SUCCESS;
3213}
3214
3215
3216/** @callback_method_impl{FNCPUMRDMSR} */
3217static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3218{
3219 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3220 /** @todo AMD SYS_CFG */
3221 *puValue = pRange->uValue;
3222 return VINF_SUCCESS;
3223}
3224
3225
3226/** @callback_method_impl{FNCPUMWRMSR} */
3227static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3228{
3229 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3230 /** @todo AMD SYS_CFG */
3231 return VINF_SUCCESS;
3232}
3233
3234
3235/** @callback_method_impl{FNCPUMRDMSR} */
3236static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3237{
3238 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3239 /** @todo AMD HW_CFG */
3240 *puValue = 0;
3241 return VINF_SUCCESS;
3242}
3243
3244
3245/** @callback_method_impl{FNCPUMWRMSR} */
3246static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3247{
3248 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3249 /** @todo AMD HW_CFG */
3250 return VINF_SUCCESS;
3251}
3252
3253
3254/** @callback_method_impl{FNCPUMRDMSR} */
3255static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3256{
3257 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3258 /** @todo AMD IorrMask/IorrBase */
3259 *puValue = 0;
3260 return VINF_SUCCESS;
3261}
3262
3263
3264/** @callback_method_impl{FNCPUMWRMSR} */
3265static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3266{
3267 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3268 /** @todo AMD IorrMask/IorrBase */
3269 return VINF_SUCCESS;
3270}
3271
3272
3273/** @callback_method_impl{FNCPUMRDMSR} */
3274static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3275{
3276 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3277 /** @todo AMD IorrMask/IorrBase */
3278 *puValue = 0;
3279 return VINF_SUCCESS;
3280}
3281
3282
3283/** @callback_method_impl{FNCPUMWRMSR} */
3284static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3285{
3286 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3287 /** @todo AMD IorrMask/IorrBase */
3288 return VINF_SUCCESS;
3289}
3290
3291
3292/** @callback_method_impl{FNCPUMRDMSR} */
3293static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3294{
3295 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3296 *puValue = 0;
3297 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
3298 * for TOPMEM2. */
3299 //if (pRange->uValue == 0)
3300 // *puValue = _4G - RamHoleSize;
3301 return VINF_SUCCESS;
3302}
3303
3304
3305/** @callback_method_impl{FNCPUMWRMSR} */
3306static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3307{
3308 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3309 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
3310 return VINF_SUCCESS;
3311}
3312
3313
3314/** @callback_method_impl{FNCPUMRDMSR} */
3315static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3316{
3317 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3318 /** @todo AMD NB_CFG1 */
3319 *puValue = 0;
3320 return VINF_SUCCESS;
3321}
3322
3323
3324/** @callback_method_impl{FNCPUMWRMSR} */
3325static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3326{
3327 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3328 /** @todo AMD NB_CFG1 */
3329 return VINF_SUCCESS;
3330}
3331
3332
3333/** @callback_method_impl{FNCPUMRDMSR} */
3334static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3335{
3336 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3337 /** @todo machine check. */
3338 *puValue = 0;
3339 return VINF_SUCCESS;
3340}
3341
3342
3343/** @callback_method_impl{FNCPUMWRMSR} */
3344static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3345{
3346 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3347 /** @todo machine check. */
3348 return VINF_SUCCESS;
3349}
3350
3351
3352/** @callback_method_impl{FNCPUMRDMSR} */
3353static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3354{
3355 RT_NOREF_PV(idMsr);
3356 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
3357 if (pLeaf)
3358 {
3359 if (!(pRange->uValue & 1))
3360 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
3361 else
3362 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
3363 }
3364 else
3365 *puValue = 0;
3366 return VINF_SUCCESS;
3367}
3368
3369
3370/** @callback_method_impl{FNCPUMWRMSR} */
3371static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3372{
3373 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3374 /** @todo Remember guest programmed CPU name. */
3375 return VINF_SUCCESS;
3376}
3377
3378
3379/** @callback_method_impl{FNCPUMRDMSR} */
3380static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3381{
3382 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3383 /** @todo AMD HTC. */
3384 *puValue = pRange->uValue;
3385 return VINF_SUCCESS;
3386}
3387
3388
3389/** @callback_method_impl{FNCPUMWRMSR} */
3390static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3391{
3392 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3393 /** @todo AMD HTC. */
3394 return VINF_SUCCESS;
3395}
3396
3397
3398/** @callback_method_impl{FNCPUMRDMSR} */
3399static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3400{
3401 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3402 /** @todo AMD STC. */
3403 *puValue = 0;
3404 return VINF_SUCCESS;
3405}
3406
3407
3408/** @callback_method_impl{FNCPUMWRMSR} */
3409static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3410{
3411 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3412 /** @todo AMD STC. */
3413 return VINF_SUCCESS;
3414}
3415
3416
3417/** @callback_method_impl{FNCPUMRDMSR} */
3418static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3419{
3420 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3421 /** @todo AMD FIDVID_CTL. */
3422 *puValue = pRange->uValue;
3423 return VINF_SUCCESS;
3424}
3425
3426
3427/** @callback_method_impl{FNCPUMWRMSR} */
3428static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3429{
3430 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3431 /** @todo AMD FIDVID_CTL. */
3432 return VINF_SUCCESS;
3433}
3434
3435
3436/** @callback_method_impl{FNCPUMRDMSR} */
3437static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3438{
3439 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3440 /** @todo AMD FIDVID_STATUS. */
3441 *puValue = pRange->uValue;
3442 return VINF_SUCCESS;
3443}
3444
3445
3446/** @callback_method_impl{FNCPUMRDMSR} */
3447static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3448{
3449 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3450 /** @todo AMD MC. */
3451 *puValue = 0;
3452 return VINF_SUCCESS;
3453}
3454
3455
3456/** @callback_method_impl{FNCPUMWRMSR} */
3457static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3458{
3459 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3460 /** @todo AMD MC. */
3461 return VINF_SUCCESS;
3462}
3463
3464
3465/** @callback_method_impl{FNCPUMRDMSR} */
3466static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3467{
3468 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3469 /** @todo AMD SMM/SMI and I/O trap. */
3470 *puValue = 0;
3471 return VINF_SUCCESS;
3472}
3473
3474
3475/** @callback_method_impl{FNCPUMWRMSR} */
3476static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3477{
3478 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3479 /** @todo AMD SMM/SMI and I/O trap. */
3480 return VINF_SUCCESS;
3481}
3482
3483
3484/** @callback_method_impl{FNCPUMRDMSR} */
3485static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3486{
3487 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3488 /** @todo AMD SMM/SMI and I/O trap. */
3489 *puValue = 0;
3490 return VINF_SUCCESS;
3491}
3492
3493
3494/** @callback_method_impl{FNCPUMWRMSR} */
3495static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3496{
3497 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3498 /** @todo AMD SMM/SMI and I/O trap. */
3499 return VINF_SUCCESS;
3500}
3501
3502
3503/** @callback_method_impl{FNCPUMRDMSR} */
3504static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3505{
3506 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3507 /** @todo Interrupt pending message. */
3508 *puValue = 0;
3509 return VINF_SUCCESS;
3510}
3511
3512
3513/** @callback_method_impl{FNCPUMWRMSR} */
3514static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3515{
3516 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3517 /** @todo Interrupt pending message. */
3518 return VINF_SUCCESS;
3519}
3520
3521
3522/** @callback_method_impl{FNCPUMRDMSR} */
3523static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3524{
3525 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3526 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3527 *puValue = 0;
3528 return VINF_SUCCESS;
3529}
3530
3531
3532/** @callback_method_impl{FNCPUMWRMSR} */
3533static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3534{
3535 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3536 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3537 return VINF_SUCCESS;
3538}
3539
3540
3541/** @callback_method_impl{FNCPUMRDMSR} */
3542static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3543{
3544 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3545 /** @todo AMD MMIO Configuration base address. */
3546 *puValue = 0;
3547 return VINF_SUCCESS;
3548}
3549
3550
3551/** @callback_method_impl{FNCPUMWRMSR} */
3552static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3553{
3554 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3555 /** @todo AMD MMIO Configuration base address. */
3556 return VINF_SUCCESS;
3557}
3558
3559
3560/** @callback_method_impl{FNCPUMRDMSR} */
3561static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3562{
3563 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3564 /** @todo AMD 0xc0010059. */
3565 *puValue = 0;
3566 return VINF_SUCCESS;
3567}
3568
3569
3570/** @callback_method_impl{FNCPUMWRMSR} */
3571static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3572{
3573 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3574 /** @todo AMD 0xc0010059. */
3575 return VINF_SUCCESS;
3576}
3577
3578
3579/** @callback_method_impl{FNCPUMRDMSR} */
3580static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3581{
3582 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3583 /** @todo AMD P-states. */
3584 *puValue = pRange->uValue;
3585 return VINF_SUCCESS;
3586}
3587
3588
3589/** @callback_method_impl{FNCPUMRDMSR} */
3590static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3591{
3592 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3593 /** @todo AMD P-states. */
3594 *puValue = pRange->uValue;
3595 return VINF_SUCCESS;
3596}
3597
3598
3599/** @callback_method_impl{FNCPUMWRMSR} */
3600static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3601{
3602 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3603 /** @todo AMD P-states. */
3604 return VINF_SUCCESS;
3605}
3606
3607
3608/** @callback_method_impl{FNCPUMRDMSR} */
3609static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3610{
3611 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3612 /** @todo AMD P-states. */
3613 *puValue = pRange->uValue;
3614 return VINF_SUCCESS;
3615}
3616
3617
3618/** @callback_method_impl{FNCPUMWRMSR} */
3619static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3620{
3621 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3622 /** @todo AMD P-states. */
3623 return VINF_SUCCESS;
3624}
3625
3626
3627/** @callback_method_impl{FNCPUMRDMSR} */
3628static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3629{
3630 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3631 /** @todo AMD P-states. */
3632 *puValue = pRange->uValue;
3633 return VINF_SUCCESS;
3634}
3635
3636
3637/** @callback_method_impl{FNCPUMWRMSR} */
3638static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3639{
3640 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3641 /** @todo AMD P-states. */
3642 return VINF_SUCCESS;
3643}
3644
3645
3646/** @callback_method_impl{FNCPUMRDMSR} */
3647static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3648{
3649 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3650 /** @todo AMD P-states. */
3651 *puValue = pRange->uValue;
3652 return VINF_SUCCESS;
3653}
3654
3655
3656/** @callback_method_impl{FNCPUMWRMSR} */
3657static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3658{
3659 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3660 /** @todo AMD P-states. */
3661 return VINF_SUCCESS;
3662}
3663
3664
3665/** @callback_method_impl{FNCPUMRDMSR} */
3666static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3667{
3668 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3669 /** @todo AMD P-states. */
3670 *puValue = pRange->uValue;
3671 return VINF_SUCCESS;
3672}
3673
3674
3675/** @callback_method_impl{FNCPUMWRMSR} */
3676static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3677{
3678 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3679 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3680 /** @todo AMD P-states. */
3681 return VINF_SUCCESS;
3682}
3683
3684
3685/** @callback_method_impl{FNCPUMRDMSR} */
3686static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3687{
3688 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3689 /** @todo AMD C-states. */
3690 *puValue = 0;
3691 return VINF_SUCCESS;
3692}
3693
3694
3695/** @callback_method_impl{FNCPUMWRMSR} */
3696static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3697{
3698 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3699 /** @todo AMD C-states. */
3700 return VINF_SUCCESS;
3701}
3702
3703
3704/** @callback_method_impl{FNCPUMRDMSR} */
3705static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3706{
3707 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3708 /** @todo AMD machine checks. */
3709 *puValue = 0;
3710 return VINF_SUCCESS;
3711}
3712
3713
3714/** @callback_method_impl{FNCPUMWRMSR} */
3715static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3716{
3717 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3718 /** @todo AMD machine checks. */
3719 return VINF_SUCCESS;
3720}
3721
3722
3723/** @callback_method_impl{FNCPUMRDMSR} */
3724static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3725{
3726 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3727 /** @todo AMD SMM. */
3728 *puValue = 0;
3729 return VINF_SUCCESS;
3730}
3731
3732
3733/** @callback_method_impl{FNCPUMWRMSR} */
3734static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3735{
3736 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3737 /** @todo AMD SMM. */
3738 return VINF_SUCCESS;
3739}
3740
3741
3742/** @callback_method_impl{FNCPUMRDMSR} */
3743static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3744{
3745 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3746 /** @todo AMD SMM. */
3747 *puValue = 0;
3748 return VINF_SUCCESS;
3749}
3750
3751
3752/** @callback_method_impl{FNCPUMWRMSR} */
3753static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3754{
3755 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3756 /** @todo AMD SMM. */
3757 return VINF_SUCCESS;
3758}
3759
3760
3761
3762/** @callback_method_impl{FNCPUMRDMSR} */
3763static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3764{
3765 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3766 /** @todo AMD SMM. */
3767 *puValue = 0;
3768 return VINF_SUCCESS;
3769}
3770
3771
3772/** @callback_method_impl{FNCPUMWRMSR} */
3773static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3774{
3775 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3776 /** @todo AMD SMM. */
3777 return VINF_SUCCESS;
3778}
3779
3780
3781/** @callback_method_impl{FNCPUMRDMSR} */
3782static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3783{
3784 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3785 PVM pVM = pVCpu->CTX_SUFF(pVM);
3786 if (pVM->cpum.s.GuestFeatures.fSvm)
3787 *puValue = MSR_K8_VM_CR_LOCK;
3788 else
3789 *puValue = 0;
3790 return VINF_SUCCESS;
3791}
3792
3793
3794/** @callback_method_impl{FNCPUMWRMSR} */
3795static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3796{
3797 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3798 PVM pVM = pVCpu->CTX_SUFF(pVM);
3799 if (pVM->cpum.s.GuestFeatures.fSvm)
3800 {
3801 /* Silently ignore writes to LOCK and SVM_DISABLE bit when the LOCK bit is set (see cpumMsrRd_AmdK8VmCr). */
3802 if (uValue & (MSR_K8_VM_CR_DPD | MSR_K8_VM_CR_R_INIT | MSR_K8_VM_CR_DIS_A20M))
3803 return VERR_CPUM_RAISE_GP_0;
3804 return VINF_SUCCESS;
3805 }
3806 return VERR_CPUM_RAISE_GP_0;
3807}
3808
3809
3810/** @callback_method_impl{FNCPUMRDMSR} */
3811static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3812{
3813 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3814 /** @todo AMD IGNNE\# control. */
3815 *puValue = 0;
3816 return VINF_SUCCESS;
3817}
3818
3819
3820/** @callback_method_impl{FNCPUMWRMSR} */
3821static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3822{
3823 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3824 /** @todo AMD IGNNE\# control. */
3825 return VINF_SUCCESS;
3826}
3827
3828
3829/** @callback_method_impl{FNCPUMRDMSR} */
3830static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3831{
3832 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3833 /** @todo AMD SMM. */
3834 *puValue = 0;
3835 return VINF_SUCCESS;
3836}
3837
3838
3839/** @callback_method_impl{FNCPUMWRMSR} */
3840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3841{
3842 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3843 /** @todo AMD SMM. */
3844 return VINF_SUCCESS;
3845}
3846
3847
3848/** @callback_method_impl{FNCPUMRDMSR} */
3849static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3850{
3851 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3852 *puValue = pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa;
3853 return VINF_SUCCESS;
3854}
3855
3856
3857/** @callback_method_impl{FNCPUMWRMSR} */
3858static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3859{
3860 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3861 if (uValue & UINT64_C(0xfff))
3862 {
3863 Log(("CPUM: Invalid setting of low 12 bits set writing host-state save area MSR %#x: %#llx\n", idMsr, uValue));
3864 return VERR_CPUM_RAISE_GP_0;
3865 }
3866
3867 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3868 if (fInvPhysMask & uValue)
3869 {
3870 Log(("CPUM: Invalid physical address bits set writing host-state save area MSR %#x: %#llx (%#llx)\n",
3871 idMsr, uValue, uValue & fInvPhysMask));
3872 return VERR_CPUM_RAISE_GP_0;
3873 }
3874
3875 pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa = uValue;
3876 return VINF_SUCCESS;
3877}
3878
3879
3880/** @callback_method_impl{FNCPUMRDMSR} */
3881static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3882{
3883 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3884 /** @todo AMD SVM. */
3885 *puValue = 0; /* RAZ */
3886 return VINF_SUCCESS;
3887}
3888
3889
3890/** @callback_method_impl{FNCPUMWRMSR} */
3891static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3892{
3893 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3894 /** @todo AMD SVM. */
3895 return VINF_SUCCESS;
3896}
3897
3898
3899/** @callback_method_impl{FNCPUMRDMSR} */
3900static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3901{
3902 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3903 /** @todo AMD SMM. */
3904 *puValue = 0; /* RAZ */
3905 return VINF_SUCCESS;
3906}
3907
3908
3909/** @callback_method_impl{FNCPUMWRMSR} */
3910static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3911{
3912 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3913 /** @todo AMD SMM. */
3914 return VINF_SUCCESS;
3915}
3916
3917
3918/** @callback_method_impl{FNCPUMRDMSR} */
3919static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3920{
3921 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3922 /** @todo AMD SMM/SMI. */
3923 *puValue = 0;
3924 return VINF_SUCCESS;
3925}
3926
3927
3928/** @callback_method_impl{FNCPUMWRMSR} */
3929static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3930{
3931 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3932 /** @todo AMD SMM/SMI. */
3933 return VINF_SUCCESS;
3934}
3935
3936
3937/** @callback_method_impl{FNCPUMRDMSR} */
3938static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3939{
3940 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3941 /** @todo AMD OS visible workaround. */
3942 *puValue = pRange->uValue;
3943 return VINF_SUCCESS;
3944}
3945
3946
3947/** @callback_method_impl{FNCPUMWRMSR} */
3948static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3949{
3950 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3951 /** @todo AMD OS visible workaround. */
3952 return VINF_SUCCESS;
3953}
3954
3955
3956/** @callback_method_impl{FNCPUMRDMSR} */
3957static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3958{
3959 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3960 /** @todo AMD OS visible workaround. */
3961 *puValue = 0;
3962 return VINF_SUCCESS;
3963}
3964
3965
3966/** @callback_method_impl{FNCPUMWRMSR} */
3967static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3968{
3969 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3970 /** @todo AMD OS visible workaround. */
3971 return VINF_SUCCESS;
3972}
3973
3974
3975/** @callback_method_impl{FNCPUMRDMSR} */
3976static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3977{
3978 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3979 /** @todo AMD L2I performance counters. */
3980 *puValue = 0;
3981 return VINF_SUCCESS;
3982}
3983
3984
3985/** @callback_method_impl{FNCPUMWRMSR} */
3986static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3987{
3988 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3989 /** @todo AMD L2I performance counters. */
3990 return VINF_SUCCESS;
3991}
3992
3993
3994/** @callback_method_impl{FNCPUMRDMSR} */
3995static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3996{
3997 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3998 /** @todo AMD L2I performance counters. */
3999 *puValue = 0;
4000 return VINF_SUCCESS;
4001}
4002
4003
4004/** @callback_method_impl{FNCPUMWRMSR} */
4005static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4006{
4007 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4008 /** @todo AMD L2I performance counters. */
4009 return VINF_SUCCESS;
4010}
4011
4012
4013/** @callback_method_impl{FNCPUMRDMSR} */
4014static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4015{
4016 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4017 /** @todo AMD Northbridge performance counters. */
4018 *puValue = 0;
4019 return VINF_SUCCESS;
4020}
4021
4022
4023/** @callback_method_impl{FNCPUMWRMSR} */
4024static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4025{
4026 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4027 /** @todo AMD Northbridge performance counters. */
4028 return VINF_SUCCESS;
4029}
4030
4031
4032/** @callback_method_impl{FNCPUMRDMSR} */
4033static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4034{
4035 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4036 /** @todo AMD Northbridge performance counters. */
4037 *puValue = 0;
4038 return VINF_SUCCESS;
4039}
4040
4041
4042/** @callback_method_impl{FNCPUMWRMSR} */
4043static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4044{
4045 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4046 /** @todo AMD Northbridge performance counters. */
4047 return VINF_SUCCESS;
4048}
4049
4050
4051/** @callback_method_impl{FNCPUMRDMSR} */
4052static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4053{
4054 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4055 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4056 * cpus. Need to be explored and verify K7 presence. */
4057 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4058 *puValue = pRange->uValue;
4059 return VINF_SUCCESS;
4060}
4061
4062
4063/** @callback_method_impl{FNCPUMWRMSR} */
4064static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4065{
4066 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4067 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4068 * cpus. Need to be explored and verify K7 presence. */
4069 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4070 return VINF_SUCCESS;
4071}
4072
4073
4074/** @callback_method_impl{FNCPUMRDMSR} */
4075static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4076{
4077 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4078 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4079 * cpus. Need to be explored and verify K7 presence. */
4080 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4081 * describing EBL_CR_POWERON. */
4082 *puValue = pRange->uValue;
4083 return VINF_SUCCESS;
4084}
4085
4086
4087/** @callback_method_impl{FNCPUMWRMSR} */
4088static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4089{
4090 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4091 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4092 * cpus. Need to be explored and verify K7 presence. */
4093 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4094 * describing EBL_CR_POWERON. */
4095 return VINF_SUCCESS;
4096}
4097
4098
4099/** @callback_method_impl{FNCPUMRDMSR} */
4100static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4101{
4102 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4103 bool fIgnored;
4104 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
4105 if (pLeaf)
4106 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
4107 else
4108 *puValue = 0;
4109 return VINF_SUCCESS;
4110}
4111
4112
4113/** @callback_method_impl{FNCPUMWRMSR} */
4114static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4115{
4116 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4117 /** @todo Changing CPUID leaf 7/0. */
4118 return VINF_SUCCESS;
4119}
4120
4121
4122/** @callback_method_impl{FNCPUMRDMSR} */
4123static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4124{
4125 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4126 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
4127 if (pLeaf)
4128 *puValue = pLeaf->uEcx;
4129 else
4130 *puValue = 0;
4131 return VINF_SUCCESS;
4132}
4133
4134
4135/** @callback_method_impl{FNCPUMWRMSR} */
4136static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4137{
4138 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4139 /** @todo Changing CPUID leaf 6. */
4140 return VINF_SUCCESS;
4141}
4142
4143
4144/** @callback_method_impl{FNCPUMRDMSR} */
4145static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4146{
4147 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4148 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
4149 if (pLeaf)
4150 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4151 else
4152 *puValue = 0;
4153 return VINF_SUCCESS;
4154}
4155
4156
4157/** @callback_method_impl{FNCPUMWRMSR} */
4158static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4159{
4160 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4161 /** @todo Changing CPUID leaf 0x80000001. */
4162 return VINF_SUCCESS;
4163}
4164
4165
4166/** @callback_method_impl{FNCPUMRDMSR} */
4167static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4168{
4169 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4170 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
4171 if (pLeaf)
4172 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4173 else
4174 *puValue = 0;
4175 return VINF_SUCCESS;
4176}
4177
4178
4179/** @callback_method_impl{FNCPUMWRMSR} */
4180static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4181{
4182 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4183 /** @todo Changing CPUID leaf 0x80000001. */
4184 return VINF_SUCCESS;
4185}
4186
4187
4188/** @callback_method_impl{FNCPUMRDMSR} */
4189static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4190{
4191 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4192 /** @todo Fake AMD microcode patching. */
4193 *puValue = pRange->uValue;
4194 return VINF_SUCCESS;
4195}
4196
4197
4198/** @callback_method_impl{FNCPUMWRMSR} */
4199static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4200{
4201 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4202 /** @todo Fake AMD microcode patching. */
4203 return VINF_SUCCESS;
4204}
4205
4206
4207/** @callback_method_impl{FNCPUMRDMSR} */
4208static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4209{
4210 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4211 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4212 * cpus. Need to be explored and verify K7 presence. */
4213 /** @todo undocumented */
4214 *puValue = 0;
4215 return VINF_SUCCESS;
4216}
4217
4218
4219/** @callback_method_impl{FNCPUMWRMSR} */
4220static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4221{
4222 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4223 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4224 * cpus. Need to be explored and verify K7 presence. */
4225 /** @todo undocumented */
4226 return VINF_SUCCESS;
4227}
4228
4229
4230/** @callback_method_impl{FNCPUMRDMSR} */
4231static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4232{
4233 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4234 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4235 * cpus. Need to be explored and verify K7 presence. */
4236 /** @todo undocumented */
4237 *puValue = 0;
4238 return VINF_SUCCESS;
4239}
4240
4241
4242/** @callback_method_impl{FNCPUMWRMSR} */
4243static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4244{
4245 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4246 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4247 * cpus. Need to be explored and verify K7 presence. */
4248 /** @todo undocumented */
4249 return VINF_SUCCESS;
4250}
4251
4252
4253/** @callback_method_impl{FNCPUMRDMSR} */
4254static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4255{
4256 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4257 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4258 * cpus. Need to be explored and verify K7 presence. */
4259 /** @todo undocumented */
4260 *puValue = 0;
4261 return VINF_SUCCESS;
4262}
4263
4264
4265/** @callback_method_impl{FNCPUMWRMSR} */
4266static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4267{
4268 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4269 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4270 * cpus. Need to be explored and verify K7 presence. */
4271 /** @todo undocumented */
4272 return VINF_SUCCESS;
4273}
4274
4275
4276/** @callback_method_impl{FNCPUMRDMSR} */
4277static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4278{
4279 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4280 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4281 * cpus. Need to be explored and verify K7 presence. */
4282 /** @todo undocumented */
4283 *puValue = 0;
4284 return VINF_SUCCESS;
4285}
4286
4287
4288/** @callback_method_impl{FNCPUMWRMSR} */
4289static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4290{
4291 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4292 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4293 * cpus. Need to be explored and verify K7 presence. */
4294 /** @todo undocumented */
4295 return VINF_SUCCESS;
4296}
4297
4298
4299/** @callback_method_impl{FNCPUMRDMSR} */
4300static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4301{
4302 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4303 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4304 * cpus. Need to be explored and verify K7 presence. */
4305 /** @todo undocumented */
4306 *puValue = 0;
4307 return VINF_SUCCESS;
4308}
4309
4310
4311/** @callback_method_impl{FNCPUMWRMSR} */
4312static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4313{
4314 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4315 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4316 * cpus. Need to be explored and verify K7 presence. */
4317 /** @todo undocumented */
4318 return VINF_SUCCESS;
4319}
4320
4321
4322/** @callback_method_impl{FNCPUMRDMSR} */
4323static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4324{
4325 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4326 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4327 * cpus. Need to be explored and verify K7 presence. */
4328 /** @todo undocumented */
4329 *puValue = 0;
4330 return VINF_SUCCESS;
4331}
4332
4333
4334/** @callback_method_impl{FNCPUMWRMSR} */
4335static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4336{
4337 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4338 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4339 * cpus. Need to be explored and verify K7 presence. */
4340 /** @todo undocumented */
4341 return VINF_SUCCESS;
4342}
4343
4344
4345/** @callback_method_impl{FNCPUMRDMSR} */
4346static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4347{
4348 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4349 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4350 * cpus. Need to be explored and verify K7 presence. */
4351 /** @todo AMD node ID and bios scratch. */
4352 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
4353 return VINF_SUCCESS;
4354}
4355
4356
4357/** @callback_method_impl{FNCPUMWRMSR} */
4358static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4359{
4360 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4361 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4362 * cpus. Need to be explored and verify K7 presence. */
4363 /** @todo AMD node ID and bios scratch. */
4364 return VINF_SUCCESS;
4365}
4366
4367
4368/** @callback_method_impl{FNCPUMRDMSR} */
4369static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4370{
4371 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4372 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4373 * cpus. Need to be explored and verify K7 presence. */
4374 /** @todo AMD DRx address masking (range breakpoints). */
4375 *puValue = 0;
4376 return VINF_SUCCESS;
4377}
4378
4379
4380/** @callback_method_impl{FNCPUMWRMSR} */
4381static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4382{
4383 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4384 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4385 * cpus. Need to be explored and verify K7 presence. */
4386 /** @todo AMD DRx address masking (range breakpoints). */
4387 return VINF_SUCCESS;
4388}
4389
4390
4391/** @callback_method_impl{FNCPUMRDMSR} */
4392static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4393{
4394 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4395 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4396 * cpus. Need to be explored and verify K7 presence. */
4397 /** @todo AMD undocument debugging features. */
4398 *puValue = 0;
4399 return VINF_SUCCESS;
4400}
4401
4402
4403/** @callback_method_impl{FNCPUMWRMSR} */
4404static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4405{
4406 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4407 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4408 * cpus. Need to be explored and verify K7 presence. */
4409 /** @todo AMD undocument debugging features. */
4410 return VINF_SUCCESS;
4411}
4412
4413
4414/** @callback_method_impl{FNCPUMRDMSR} */
4415static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4416{
4417 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4418 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4419 * cpus. Need to be explored and verify K7 presence. */
4420 /** @todo AMD undocument debugging features. */
4421 *puValue = 0;
4422 return VINF_SUCCESS;
4423}
4424
4425
4426/** @callback_method_impl{FNCPUMWRMSR} */
4427static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4428{
4429 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4430 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4431 * cpus. Need to be explored and verify K7 presence. */
4432 /** @todo AMD undocument debugging features. */
4433 return VINF_SUCCESS;
4434}
4435
4436
4437/** @callback_method_impl{FNCPUMRDMSR} */
4438static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4439{
4440 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4441 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4442 * cpus. Need to be explored and verify K7 presence. */
4443 /** @todo AMD load-store config. */
4444 *puValue = 0;
4445 return VINF_SUCCESS;
4446}
4447
4448
4449/** @callback_method_impl{FNCPUMWRMSR} */
4450static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4451{
4452 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4453 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4454 * cpus. Need to be explored and verify K7 presence. */
4455 /** @todo AMD load-store config. */
4456 return VINF_SUCCESS;
4457}
4458
4459
4460/** @callback_method_impl{FNCPUMRDMSR} */
4461static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4462{
4463 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4464 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4465 * cpus. Need to be explored and verify K7 presence. */
4466 /** @todo AMD instruction cache config. */
4467 *puValue = 0;
4468 return VINF_SUCCESS;
4469}
4470
4471
4472/** @callback_method_impl{FNCPUMWRMSR} */
4473static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4474{
4475 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4476 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4477 * cpus. Need to be explored and verify K7 presence. */
4478 /** @todo AMD instruction cache config. */
4479 return VINF_SUCCESS;
4480}
4481
4482
4483/** @callback_method_impl{FNCPUMRDMSR} */
4484static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4485{
4486 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4487 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4488 * cpus. Need to be explored and verify K7 presence. */
4489 /** @todo AMD data cache config. */
4490 *puValue = 0;
4491 return VINF_SUCCESS;
4492}
4493
4494
4495/** @callback_method_impl{FNCPUMWRMSR} */
4496static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4497{
4498 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4499 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4500 * cpus. Need to be explored and verify K7 presence. */
4501 /** @todo AMD data cache config. */
4502 return VINF_SUCCESS;
4503}
4504
4505
4506/** @callback_method_impl{FNCPUMRDMSR} */
4507static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4508{
4509 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4510 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4511 * cpus. Need to be explored and verify K7 presence. */
4512 /** @todo AMD bus unit config. */
4513 *puValue = 0;
4514 return VINF_SUCCESS;
4515}
4516
4517
4518/** @callback_method_impl{FNCPUMWRMSR} */
4519static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4520{
4521 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4522 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4523 * cpus. Need to be explored and verify K7 presence. */
4524 /** @todo AMD bus unit config. */
4525 return VINF_SUCCESS;
4526}
4527
4528
4529/** @callback_method_impl{FNCPUMRDMSR} */
4530static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4531{
4532 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4533 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4534 * cpus. Need to be explored and verify K7 presence. */
4535 /** @todo Undocument AMD debug control register \#2. */
4536 *puValue = 0;
4537 return VINF_SUCCESS;
4538}
4539
4540
4541/** @callback_method_impl{FNCPUMWRMSR} */
4542static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4543{
4544 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4545 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4546 * cpus. Need to be explored and verify K7 presence. */
4547 /** @todo Undocument AMD debug control register \#2. */
4548 return VINF_SUCCESS;
4549}
4550
4551
4552/** @callback_method_impl{FNCPUMRDMSR} */
4553static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4554{
4555 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4556 /** @todo AMD FPU config. */
4557 *puValue = 0;
4558 return VINF_SUCCESS;
4559}
4560
4561
4562/** @callback_method_impl{FNCPUMWRMSR} */
4563static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4564{
4565 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4566 /** @todo AMD FPU config. */
4567 return VINF_SUCCESS;
4568}
4569
4570
4571/** @callback_method_impl{FNCPUMRDMSR} */
4572static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4573{
4574 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4575 /** @todo AMD decoder config. */
4576 *puValue = 0;
4577 return VINF_SUCCESS;
4578}
4579
4580
4581/** @callback_method_impl{FNCPUMWRMSR} */
4582static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4583{
4584 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4585 /** @todo AMD decoder config. */
4586 return VINF_SUCCESS;
4587}
4588
4589
4590/** @callback_method_impl{FNCPUMRDMSR} */
4591static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4592{
4593 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4594 /* Note! 10h and 16h */
4595 /** @todo AMD bus unit config. */
4596 *puValue = 0;
4597 return VINF_SUCCESS;
4598}
4599
4600
4601/** @callback_method_impl{FNCPUMWRMSR} */
4602static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4603{
4604 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4605 /* Note! 10h and 16h */
4606 /** @todo AMD bus unit config. */
4607 return VINF_SUCCESS;
4608}
4609
4610
4611/** @callback_method_impl{FNCPUMRDMSR} */
4612static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4613{
4614 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4615 /** @todo AMD unit config. */
4616 *puValue = 0;
4617 return VINF_SUCCESS;
4618}
4619
4620
4621/** @callback_method_impl{FNCPUMWRMSR} */
4622static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4623{
4624 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4625 /** @todo AMD unit config. */
4626 return VINF_SUCCESS;
4627}
4628
4629
4630/** @callback_method_impl{FNCPUMRDMSR} */
4631static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4632{
4633 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4634 /** @todo AMD unit config 2. */
4635 *puValue = 0;
4636 return VINF_SUCCESS;
4637}
4638
4639
4640/** @callback_method_impl{FNCPUMWRMSR} */
4641static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4642{
4643 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4644 /** @todo AMD unit config 2. */
4645 return VINF_SUCCESS;
4646}
4647
4648
4649/** @callback_method_impl{FNCPUMRDMSR} */
4650static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4651{
4652 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4653 /** @todo AMD combined unit config 3. */
4654 *puValue = 0;
4655 return VINF_SUCCESS;
4656}
4657
4658
4659/** @callback_method_impl{FNCPUMWRMSR} */
4660static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4661{
4662 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4663 /** @todo AMD combined unit config 3. */
4664 return VINF_SUCCESS;
4665}
4666
4667
4668/** @callback_method_impl{FNCPUMRDMSR} */
4669static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4670{
4671 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4672 /** @todo AMD execution unit config. */
4673 *puValue = 0;
4674 return VINF_SUCCESS;
4675}
4676
4677
4678/** @callback_method_impl{FNCPUMWRMSR} */
4679static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4680{
4681 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4682 /** @todo AMD execution unit config. */
4683 return VINF_SUCCESS;
4684}
4685
4686
4687/** @callback_method_impl{FNCPUMRDMSR} */
4688static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4689{
4690 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4691 /** @todo AMD load-store config 2. */
4692 *puValue = 0;
4693 return VINF_SUCCESS;
4694}
4695
4696
4697/** @callback_method_impl{FNCPUMWRMSR} */
4698static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4699{
4700 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4701 /** @todo AMD load-store config 2. */
4702 return VINF_SUCCESS;
4703}
4704
4705
4706/** @callback_method_impl{FNCPUMRDMSR} */
4707static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4708{
4709 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4710 /** @todo AMD IBS. */
4711 *puValue = 0;
4712 return VINF_SUCCESS;
4713}
4714
4715
4716/** @callback_method_impl{FNCPUMWRMSR} */
4717static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4718{
4719 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4720 /** @todo AMD IBS. */
4721 return VINF_SUCCESS;
4722}
4723
4724
4725/** @callback_method_impl{FNCPUMRDMSR} */
4726static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4727{
4728 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4729 /** @todo AMD IBS. */
4730 *puValue = 0;
4731 return VINF_SUCCESS;
4732}
4733
4734
4735/** @callback_method_impl{FNCPUMWRMSR} */
4736static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4737{
4738 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4739 /** @todo AMD IBS. */
4740 return VINF_SUCCESS;
4741}
4742
4743
4744/** @callback_method_impl{FNCPUMRDMSR} */
4745static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4746{
4747 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4748 /** @todo AMD IBS. */
4749 *puValue = 0;
4750 return VINF_SUCCESS;
4751}
4752
4753
4754/** @callback_method_impl{FNCPUMWRMSR} */
4755static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4756{
4757 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4758 /** @todo AMD IBS. */
4759 return VINF_SUCCESS;
4760}
4761
4762
4763/** @callback_method_impl{FNCPUMRDMSR} */
4764static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4765{
4766 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4767 /** @todo AMD IBS. */
4768 *puValue = 0;
4769 return VINF_SUCCESS;
4770}
4771
4772
4773/** @callback_method_impl{FNCPUMWRMSR} */
4774static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4775{
4776 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4777 /** @todo AMD IBS. */
4778 return VINF_SUCCESS;
4779}
4780
4781
4782/** @callback_method_impl{FNCPUMRDMSR} */
4783static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4784{
4785 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4786 /** @todo AMD IBS. */
4787 *puValue = 0;
4788 return VINF_SUCCESS;
4789}
4790
4791
4792/** @callback_method_impl{FNCPUMWRMSR} */
4793static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4794{
4795 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4796 /** @todo AMD IBS. */
4797 if (!X86_IS_CANONICAL(uValue))
4798 {
4799 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4800 return VERR_CPUM_RAISE_GP_0;
4801 }
4802 return VINF_SUCCESS;
4803}
4804
4805
4806/** @callback_method_impl{FNCPUMRDMSR} */
4807static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4808{
4809 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4810 /** @todo AMD IBS. */
4811 *puValue = 0;
4812 return VINF_SUCCESS;
4813}
4814
4815
4816/** @callback_method_impl{FNCPUMWRMSR} */
4817static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4818{
4819 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4820 /** @todo AMD IBS. */
4821 return VINF_SUCCESS;
4822}
4823
4824
4825/** @callback_method_impl{FNCPUMRDMSR} */
4826static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4827{
4828 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4829 /** @todo AMD IBS. */
4830 *puValue = 0;
4831 return VINF_SUCCESS;
4832}
4833
4834
4835/** @callback_method_impl{FNCPUMWRMSR} */
4836static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4837{
4838 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4839 /** @todo AMD IBS. */
4840 return VINF_SUCCESS;
4841}
4842
4843
4844/** @callback_method_impl{FNCPUMRDMSR} */
4845static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4846{
4847 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4848 /** @todo AMD IBS. */
4849 *puValue = 0;
4850 return VINF_SUCCESS;
4851}
4852
4853
4854/** @callback_method_impl{FNCPUMWRMSR} */
4855static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4856{
4857 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4858 /** @todo AMD IBS. */
4859 return VINF_SUCCESS;
4860}
4861
4862
4863/** @callback_method_impl{FNCPUMRDMSR} */
4864static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4865{
4866 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4867 /** @todo AMD IBS. */
4868 *puValue = 0;
4869 return VINF_SUCCESS;
4870}
4871
4872
4873/** @callback_method_impl{FNCPUMWRMSR} */
4874static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4875{
4876 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4877 /** @todo AMD IBS. */
4878 if (!X86_IS_CANONICAL(uValue))
4879 {
4880 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4881 return VERR_CPUM_RAISE_GP_0;
4882 }
4883 return VINF_SUCCESS;
4884}
4885
4886
4887/** @callback_method_impl{FNCPUMRDMSR} */
4888static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4889{
4890 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4891 /** @todo AMD IBS. */
4892 *puValue = 0;
4893 return VINF_SUCCESS;
4894}
4895
4896
4897/** @callback_method_impl{FNCPUMWRMSR} */
4898static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4899{
4900 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4901 /** @todo AMD IBS. */
4902 return VINF_SUCCESS;
4903}
4904
4905
4906/** @callback_method_impl{FNCPUMRDMSR} */
4907static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4908{
4909 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4910 /** @todo AMD IBS. */
4911 *puValue = 0;
4912 return VINF_SUCCESS;
4913}
4914
4915
4916/** @callback_method_impl{FNCPUMWRMSR} */
4917static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4918{
4919 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4920 /** @todo AMD IBS. */
4921 return VINF_SUCCESS;
4922}
4923
4924
4925/** @callback_method_impl{FNCPUMRDMSR} */
4926static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4927{
4928 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4929 /** @todo AMD IBS. */
4930 *puValue = 0;
4931 return VINF_SUCCESS;
4932}
4933
4934
4935/** @callback_method_impl{FNCPUMWRMSR} */
4936static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4937{
4938 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4939 /** @todo AMD IBS. */
4940 if (!X86_IS_CANONICAL(uValue))
4941 {
4942 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4943 return VERR_CPUM_RAISE_GP_0;
4944 }
4945 return VINF_SUCCESS;
4946}
4947
4948
4949
4950/*
4951 * GIM MSRs.
4952 * GIM MSRs.
4953 * GIM MSRs.
4954 */
4955
4956
4957/** @callback_method_impl{FNCPUMRDMSR} */
4958static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4959{
4960#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4961 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
4962 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4963 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
4964 return VERR_CPUM_RAISE_GP_0;
4965#endif
4966 return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
4967}
4968
4969
4970/** @callback_method_impl{FNCPUMWRMSR} */
4971static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4972{
4973#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4974 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
4975 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4976 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
4977 return VERR_CPUM_RAISE_GP_0;
4978#endif
4979 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
4980}
4981
4982
4983/**
4984 * MSR read function table.
4985 */
4986static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4987{
4988 NULL, /* Invalid */
4989 cpumMsrRd_FixedValue,
4990 NULL, /* Alias */
4991 cpumMsrRd_WriteOnly,
4992 cpumMsrRd_Ia32P5McAddr,
4993 cpumMsrRd_Ia32P5McType,
4994 cpumMsrRd_Ia32TimestampCounter,
4995 cpumMsrRd_Ia32PlatformId,
4996 cpumMsrRd_Ia32ApicBase,
4997 cpumMsrRd_Ia32FeatureControl,
4998 cpumMsrRd_Ia32BiosSignId,
4999 cpumMsrRd_Ia32SmmMonitorCtl,
5000 cpumMsrRd_Ia32PmcN,
5001 cpumMsrRd_Ia32MonitorFilterLineSize,
5002 cpumMsrRd_Ia32MPerf,
5003 cpumMsrRd_Ia32APerf,
5004 cpumMsrRd_Ia32MtrrCap,
5005 cpumMsrRd_Ia32MtrrPhysBaseN,
5006 cpumMsrRd_Ia32MtrrPhysMaskN,
5007 cpumMsrRd_Ia32MtrrFixed,
5008 cpumMsrRd_Ia32MtrrDefType,
5009 cpumMsrRd_Ia32Pat,
5010 cpumMsrRd_Ia32SysEnterCs,
5011 cpumMsrRd_Ia32SysEnterEsp,
5012 cpumMsrRd_Ia32SysEnterEip,
5013 cpumMsrRd_Ia32McgCap,
5014 cpumMsrRd_Ia32McgStatus,
5015 cpumMsrRd_Ia32McgCtl,
5016 cpumMsrRd_Ia32DebugCtl,
5017 cpumMsrRd_Ia32SmrrPhysBase,
5018 cpumMsrRd_Ia32SmrrPhysMask,
5019 cpumMsrRd_Ia32PlatformDcaCap,
5020 cpumMsrRd_Ia32CpuDcaCap,
5021 cpumMsrRd_Ia32Dca0Cap,
5022 cpumMsrRd_Ia32PerfEvtSelN,
5023 cpumMsrRd_Ia32PerfStatus,
5024 cpumMsrRd_Ia32PerfCtl,
5025 cpumMsrRd_Ia32FixedCtrN,
5026 cpumMsrRd_Ia32PerfCapabilities,
5027 cpumMsrRd_Ia32FixedCtrCtrl,
5028 cpumMsrRd_Ia32PerfGlobalStatus,
5029 cpumMsrRd_Ia32PerfGlobalCtrl,
5030 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
5031 cpumMsrRd_Ia32PebsEnable,
5032 cpumMsrRd_Ia32ClockModulation,
5033 cpumMsrRd_Ia32ThermInterrupt,
5034 cpumMsrRd_Ia32ThermStatus,
5035 cpumMsrRd_Ia32Therm2Ctl,
5036 cpumMsrRd_Ia32MiscEnable,
5037 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
5038 cpumMsrRd_Ia32McNCtl2,
5039 cpumMsrRd_Ia32DsArea,
5040 cpumMsrRd_Ia32TscDeadline,
5041 cpumMsrRd_Ia32X2ApicN,
5042 cpumMsrRd_Ia32DebugInterface,
5043 cpumMsrRd_Ia32VmxBase,
5044 cpumMsrRd_Ia32VmxPinbasedCtls,
5045 cpumMsrRd_Ia32VmxProcbasedCtls,
5046 cpumMsrRd_Ia32VmxExitCtls,
5047 cpumMsrRd_Ia32VmxEntryCtls,
5048 cpumMsrRd_Ia32VmxMisc,
5049 cpumMsrRd_Ia32VmxCr0Fixed0,
5050 cpumMsrRd_Ia32VmxCr0Fixed1,
5051 cpumMsrRd_Ia32VmxCr4Fixed0,
5052 cpumMsrRd_Ia32VmxCr4Fixed1,
5053 cpumMsrRd_Ia32VmxVmcsEnum,
5054 cpumMsrRd_Ia32VmxProcBasedCtls2,
5055 cpumMsrRd_Ia32VmxEptVpidCap,
5056 cpumMsrRd_Ia32VmxTruePinbasedCtls,
5057 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
5058 cpumMsrRd_Ia32VmxTrueExitCtls,
5059 cpumMsrRd_Ia32VmxTrueEntryCtls,
5060 cpumMsrRd_Ia32VmxVmFunc,
5061 cpumMsrRd_Ia32SpecCtrl,
5062 cpumMsrRd_Ia32ArchCapabilities,
5063
5064 cpumMsrRd_Amd64Efer,
5065 cpumMsrRd_Amd64SyscallTarget,
5066 cpumMsrRd_Amd64LongSyscallTarget,
5067 cpumMsrRd_Amd64CompSyscallTarget,
5068 cpumMsrRd_Amd64SyscallFlagMask,
5069 cpumMsrRd_Amd64FsBase,
5070 cpumMsrRd_Amd64GsBase,
5071 cpumMsrRd_Amd64KernelGsBase,
5072 cpumMsrRd_Amd64TscAux,
5073
5074 cpumMsrRd_IntelEblCrPowerOn,
5075 cpumMsrRd_IntelI7CoreThreadCount,
5076 cpumMsrRd_IntelP4EbcHardPowerOn,
5077 cpumMsrRd_IntelP4EbcSoftPowerOn,
5078 cpumMsrRd_IntelP4EbcFrequencyId,
5079 cpumMsrRd_IntelP6FsbFrequency,
5080 cpumMsrRd_IntelPlatformInfo,
5081 cpumMsrRd_IntelFlexRatio,
5082 cpumMsrRd_IntelPkgCStConfigControl,
5083 cpumMsrRd_IntelPmgIoCaptureBase,
5084 cpumMsrRd_IntelLastBranchFromToN,
5085 cpumMsrRd_IntelLastBranchFromN,
5086 cpumMsrRd_IntelLastBranchToN,
5087 cpumMsrRd_IntelLastBranchTos,
5088 cpumMsrRd_IntelBblCrCtl,
5089 cpumMsrRd_IntelBblCrCtl3,
5090 cpumMsrRd_IntelI7TemperatureTarget,
5091 cpumMsrRd_IntelI7MsrOffCoreResponseN,
5092 cpumMsrRd_IntelI7MiscPwrMgmt,
5093 cpumMsrRd_IntelP6CrN,
5094 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
5095 cpumMsrRd_IntelCpuId1FeatureMaskEax,
5096 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
5097 cpumMsrRd_IntelI7SandyAesNiCtl,
5098 cpumMsrRd_IntelI7TurboRatioLimit,
5099 cpumMsrRd_IntelI7LbrSelect,
5100 cpumMsrRd_IntelI7SandyErrorControl,
5101 cpumMsrRd_IntelI7VirtualLegacyWireCap,
5102 cpumMsrRd_IntelI7PowerCtl,
5103 cpumMsrRd_IntelI7SandyPebsNumAlt,
5104 cpumMsrRd_IntelI7PebsLdLat,
5105 cpumMsrRd_IntelI7PkgCnResidencyN,
5106 cpumMsrRd_IntelI7CoreCnResidencyN,
5107 cpumMsrRd_IntelI7SandyVrCurrentConfig,
5108 cpumMsrRd_IntelI7SandyVrMiscConfig,
5109 cpumMsrRd_IntelI7SandyRaplPowerUnit,
5110 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
5111 cpumMsrRd_IntelI7SandyPkgC2Residency,
5112 cpumMsrRd_IntelI7RaplPkgPowerLimit,
5113 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
5114 cpumMsrRd_IntelI7RaplPkgPerfStatus,
5115 cpumMsrRd_IntelI7RaplPkgPowerInfo,
5116 cpumMsrRd_IntelI7RaplDramPowerLimit,
5117 cpumMsrRd_IntelI7RaplDramEnergyStatus,
5118 cpumMsrRd_IntelI7RaplDramPerfStatus,
5119 cpumMsrRd_IntelI7RaplDramPowerInfo,
5120 cpumMsrRd_IntelI7RaplPp0PowerLimit,
5121 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
5122 cpumMsrRd_IntelI7RaplPp0Policy,
5123 cpumMsrRd_IntelI7RaplPp0PerfStatus,
5124 cpumMsrRd_IntelI7RaplPp1PowerLimit,
5125 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
5126 cpumMsrRd_IntelI7RaplPp1Policy,
5127 cpumMsrRd_IntelI7IvyConfigTdpNominal,
5128 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
5129 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
5130 cpumMsrRd_IntelI7IvyConfigTdpControl,
5131 cpumMsrRd_IntelI7IvyTurboActivationRatio,
5132 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
5133 cpumMsrRd_IntelI7UncPerfGlobalStatus,
5134 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
5135 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
5136 cpumMsrRd_IntelI7UncPerfFixedCtr,
5137 cpumMsrRd_IntelI7UncCBoxConfig,
5138 cpumMsrRd_IntelI7UncArbPerfCtrN,
5139 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
5140 cpumMsrRd_IntelI7SmiCount,
5141 cpumMsrRd_IntelCore2EmttmCrTablesN,
5142 cpumMsrRd_IntelCore2SmmCStMiscInfo,
5143 cpumMsrRd_IntelCore1ExtConfig,
5144 cpumMsrRd_IntelCore1DtsCalControl,
5145 cpumMsrRd_IntelCore2PeciControl,
5146 cpumMsrRd_IntelAtSilvCoreC1Recidency,
5147
5148 cpumMsrRd_P6LastBranchFromIp,
5149 cpumMsrRd_P6LastBranchToIp,
5150 cpumMsrRd_P6LastIntFromIp,
5151 cpumMsrRd_P6LastIntToIp,
5152
5153 cpumMsrRd_AmdFam15hTscRate,
5154 cpumMsrRd_AmdFam15hLwpCfg,
5155 cpumMsrRd_AmdFam15hLwpCbAddr,
5156 cpumMsrRd_AmdFam10hMc4MiscN,
5157 cpumMsrRd_AmdK8PerfCtlN,
5158 cpumMsrRd_AmdK8PerfCtrN,
5159 cpumMsrRd_AmdK8SysCfg,
5160 cpumMsrRd_AmdK8HwCr,
5161 cpumMsrRd_AmdK8IorrBaseN,
5162 cpumMsrRd_AmdK8IorrMaskN,
5163 cpumMsrRd_AmdK8TopOfMemN,
5164 cpumMsrRd_AmdK8NbCfg1,
5165 cpumMsrRd_AmdK8McXcptRedir,
5166 cpumMsrRd_AmdK8CpuNameN,
5167 cpumMsrRd_AmdK8HwThermalCtrl,
5168 cpumMsrRd_AmdK8SwThermalCtrl,
5169 cpumMsrRd_AmdK8FidVidControl,
5170 cpumMsrRd_AmdK8FidVidStatus,
5171 cpumMsrRd_AmdK8McCtlMaskN,
5172 cpumMsrRd_AmdK8SmiOnIoTrapN,
5173 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
5174 cpumMsrRd_AmdK8IntPendingMessage,
5175 cpumMsrRd_AmdK8SmiTriggerIoCycle,
5176 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
5177 cpumMsrRd_AmdFam10hTrapCtlMaybe,
5178 cpumMsrRd_AmdFam10hPStateCurLimit,
5179 cpumMsrRd_AmdFam10hPStateControl,
5180 cpumMsrRd_AmdFam10hPStateStatus,
5181 cpumMsrRd_AmdFam10hPStateN,
5182 cpumMsrRd_AmdFam10hCofVidControl,
5183 cpumMsrRd_AmdFam10hCofVidStatus,
5184 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
5185 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
5186 cpumMsrRd_AmdK8SmmBase,
5187 cpumMsrRd_AmdK8SmmAddr,
5188 cpumMsrRd_AmdK8SmmMask,
5189 cpumMsrRd_AmdK8VmCr,
5190 cpumMsrRd_AmdK8IgnNe,
5191 cpumMsrRd_AmdK8SmmCtl,
5192 cpumMsrRd_AmdK8VmHSavePa,
5193 cpumMsrRd_AmdFam10hVmLockKey,
5194 cpumMsrRd_AmdFam10hSmmLockKey,
5195 cpumMsrRd_AmdFam10hLocalSmiStatus,
5196 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
5197 cpumMsrRd_AmdFam10hOsVisWrkStatus,
5198 cpumMsrRd_AmdFam16hL2IPerfCtlN,
5199 cpumMsrRd_AmdFam16hL2IPerfCtrN,
5200 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
5201 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
5202 cpumMsrRd_AmdK7MicrocodeCtl,
5203 cpumMsrRd_AmdK7ClusterIdMaybe,
5204 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
5205 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
5206 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
5207 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
5208 cpumMsrRd_AmdK8PatchLevel,
5209 cpumMsrRd_AmdK7DebugStatusMaybe,
5210 cpumMsrRd_AmdK7BHTraceBaseMaybe,
5211 cpumMsrRd_AmdK7BHTracePtrMaybe,
5212 cpumMsrRd_AmdK7BHTraceLimitMaybe,
5213 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
5214 cpumMsrRd_AmdK7FastFlushCountMaybe,
5215 cpumMsrRd_AmdK7NodeId,
5216 cpumMsrRd_AmdK7DrXAddrMaskN,
5217 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
5218 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
5219 cpumMsrRd_AmdK7LoadStoreCfg,
5220 cpumMsrRd_AmdK7InstrCacheCfg,
5221 cpumMsrRd_AmdK7DataCacheCfg,
5222 cpumMsrRd_AmdK7BusUnitCfg,
5223 cpumMsrRd_AmdK7DebugCtl2Maybe,
5224 cpumMsrRd_AmdFam15hFpuCfg,
5225 cpumMsrRd_AmdFam15hDecoderCfg,
5226 cpumMsrRd_AmdFam10hBusUnitCfg2,
5227 cpumMsrRd_AmdFam15hCombUnitCfg,
5228 cpumMsrRd_AmdFam15hCombUnitCfg2,
5229 cpumMsrRd_AmdFam15hCombUnitCfg3,
5230 cpumMsrRd_AmdFam15hExecUnitCfg,
5231 cpumMsrRd_AmdFam15hLoadStoreCfg2,
5232 cpumMsrRd_AmdFam10hIbsFetchCtl,
5233 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
5234 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
5235 cpumMsrRd_AmdFam10hIbsOpExecCtl,
5236 cpumMsrRd_AmdFam10hIbsOpRip,
5237 cpumMsrRd_AmdFam10hIbsOpData,
5238 cpumMsrRd_AmdFam10hIbsOpData2,
5239 cpumMsrRd_AmdFam10hIbsOpData3,
5240 cpumMsrRd_AmdFam10hIbsDcLinAddr,
5241 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
5242 cpumMsrRd_AmdFam10hIbsCtl,
5243 cpumMsrRd_AmdFam14hIbsBrTarget,
5244
5245 cpumMsrRd_Gim
5246};
5247
5248
5249/**
5250 * MSR write function table.
5251 */
5252static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
5253{
5254 NULL, /* Invalid */
5255 cpumMsrWr_IgnoreWrite,
5256 cpumMsrWr_ReadOnly,
5257 NULL, /* Alias */
5258 cpumMsrWr_Ia32P5McAddr,
5259 cpumMsrWr_Ia32P5McType,
5260 cpumMsrWr_Ia32TimestampCounter,
5261 cpumMsrWr_Ia32ApicBase,
5262 cpumMsrWr_Ia32FeatureControl,
5263 cpumMsrWr_Ia32BiosSignId,
5264 cpumMsrWr_Ia32BiosUpdateTrigger,
5265 cpumMsrWr_Ia32SmmMonitorCtl,
5266 cpumMsrWr_Ia32PmcN,
5267 cpumMsrWr_Ia32MonitorFilterLineSize,
5268 cpumMsrWr_Ia32MPerf,
5269 cpumMsrWr_Ia32APerf,
5270 cpumMsrWr_Ia32MtrrPhysBaseN,
5271 cpumMsrWr_Ia32MtrrPhysMaskN,
5272 cpumMsrWr_Ia32MtrrFixed,
5273 cpumMsrWr_Ia32MtrrDefType,
5274 cpumMsrWr_Ia32Pat,
5275 cpumMsrWr_Ia32SysEnterCs,
5276 cpumMsrWr_Ia32SysEnterEsp,
5277 cpumMsrWr_Ia32SysEnterEip,
5278 cpumMsrWr_Ia32McgStatus,
5279 cpumMsrWr_Ia32McgCtl,
5280 cpumMsrWr_Ia32DebugCtl,
5281 cpumMsrWr_Ia32SmrrPhysBase,
5282 cpumMsrWr_Ia32SmrrPhysMask,
5283 cpumMsrWr_Ia32PlatformDcaCap,
5284 cpumMsrWr_Ia32Dca0Cap,
5285 cpumMsrWr_Ia32PerfEvtSelN,
5286 cpumMsrWr_Ia32PerfStatus,
5287 cpumMsrWr_Ia32PerfCtl,
5288 cpumMsrWr_Ia32FixedCtrN,
5289 cpumMsrWr_Ia32PerfCapabilities,
5290 cpumMsrWr_Ia32FixedCtrCtrl,
5291 cpumMsrWr_Ia32PerfGlobalStatus,
5292 cpumMsrWr_Ia32PerfGlobalCtrl,
5293 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
5294 cpumMsrWr_Ia32PebsEnable,
5295 cpumMsrWr_Ia32ClockModulation,
5296 cpumMsrWr_Ia32ThermInterrupt,
5297 cpumMsrWr_Ia32ThermStatus,
5298 cpumMsrWr_Ia32Therm2Ctl,
5299 cpumMsrWr_Ia32MiscEnable,
5300 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
5301 cpumMsrWr_Ia32McNCtl2,
5302 cpumMsrWr_Ia32DsArea,
5303 cpumMsrWr_Ia32TscDeadline,
5304 cpumMsrWr_Ia32X2ApicN,
5305 cpumMsrWr_Ia32DebugInterface,
5306 cpumMsrWr_Ia32SpecCtrl,
5307 cpumMsrWr_Ia32PredCmd,
5308
5309 cpumMsrWr_Amd64Efer,
5310 cpumMsrWr_Amd64SyscallTarget,
5311 cpumMsrWr_Amd64LongSyscallTarget,
5312 cpumMsrWr_Amd64CompSyscallTarget,
5313 cpumMsrWr_Amd64SyscallFlagMask,
5314 cpumMsrWr_Amd64FsBase,
5315 cpumMsrWr_Amd64GsBase,
5316 cpumMsrWr_Amd64KernelGsBase,
5317 cpumMsrWr_Amd64TscAux,
5318
5319 cpumMsrWr_IntelEblCrPowerOn,
5320 cpumMsrWr_IntelP4EbcHardPowerOn,
5321 cpumMsrWr_IntelP4EbcSoftPowerOn,
5322 cpumMsrWr_IntelP4EbcFrequencyId,
5323 cpumMsrWr_IntelFlexRatio,
5324 cpumMsrWr_IntelPkgCStConfigControl,
5325 cpumMsrWr_IntelPmgIoCaptureBase,
5326 cpumMsrWr_IntelLastBranchFromToN,
5327 cpumMsrWr_IntelLastBranchFromN,
5328 cpumMsrWr_IntelLastBranchToN,
5329 cpumMsrWr_IntelLastBranchTos,
5330 cpumMsrWr_IntelBblCrCtl,
5331 cpumMsrWr_IntelBblCrCtl3,
5332 cpumMsrWr_IntelI7TemperatureTarget,
5333 cpumMsrWr_IntelI7MsrOffCoreResponseN,
5334 cpumMsrWr_IntelI7MiscPwrMgmt,
5335 cpumMsrWr_IntelP6CrN,
5336 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
5337 cpumMsrWr_IntelCpuId1FeatureMaskEax,
5338 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
5339 cpumMsrWr_IntelI7SandyAesNiCtl,
5340 cpumMsrWr_IntelI7TurboRatioLimit,
5341 cpumMsrWr_IntelI7LbrSelect,
5342 cpumMsrWr_IntelI7SandyErrorControl,
5343 cpumMsrWr_IntelI7PowerCtl,
5344 cpumMsrWr_IntelI7SandyPebsNumAlt,
5345 cpumMsrWr_IntelI7PebsLdLat,
5346 cpumMsrWr_IntelI7SandyVrCurrentConfig,
5347 cpumMsrWr_IntelI7SandyVrMiscConfig,
5348 cpumMsrWr_IntelI7SandyRaplPowerUnit,
5349 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
5350 cpumMsrWr_IntelI7SandyPkgC2Residency,
5351 cpumMsrWr_IntelI7RaplPkgPowerLimit,
5352 cpumMsrWr_IntelI7RaplDramPowerLimit,
5353 cpumMsrWr_IntelI7RaplPp0PowerLimit,
5354 cpumMsrWr_IntelI7RaplPp0Policy,
5355 cpumMsrWr_IntelI7RaplPp1PowerLimit,
5356 cpumMsrWr_IntelI7RaplPp1Policy,
5357 cpumMsrWr_IntelI7IvyConfigTdpControl,
5358 cpumMsrWr_IntelI7IvyTurboActivationRatio,
5359 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
5360 cpumMsrWr_IntelI7UncPerfGlobalStatus,
5361 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
5362 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
5363 cpumMsrWr_IntelI7UncPerfFixedCtr,
5364 cpumMsrWr_IntelI7UncArbPerfCtrN,
5365 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
5366 cpumMsrWr_IntelCore2EmttmCrTablesN,
5367 cpumMsrWr_IntelCore2SmmCStMiscInfo,
5368 cpumMsrWr_IntelCore1ExtConfig,
5369 cpumMsrWr_IntelCore1DtsCalControl,
5370 cpumMsrWr_IntelCore2PeciControl,
5371
5372 cpumMsrWr_P6LastIntFromIp,
5373 cpumMsrWr_P6LastIntToIp,
5374
5375 cpumMsrWr_AmdFam15hTscRate,
5376 cpumMsrWr_AmdFam15hLwpCfg,
5377 cpumMsrWr_AmdFam15hLwpCbAddr,
5378 cpumMsrWr_AmdFam10hMc4MiscN,
5379 cpumMsrWr_AmdK8PerfCtlN,
5380 cpumMsrWr_AmdK8PerfCtrN,
5381 cpumMsrWr_AmdK8SysCfg,
5382 cpumMsrWr_AmdK8HwCr,
5383 cpumMsrWr_AmdK8IorrBaseN,
5384 cpumMsrWr_AmdK8IorrMaskN,
5385 cpumMsrWr_AmdK8TopOfMemN,
5386 cpumMsrWr_AmdK8NbCfg1,
5387 cpumMsrWr_AmdK8McXcptRedir,
5388 cpumMsrWr_AmdK8CpuNameN,
5389 cpumMsrWr_AmdK8HwThermalCtrl,
5390 cpumMsrWr_AmdK8SwThermalCtrl,
5391 cpumMsrWr_AmdK8FidVidControl,
5392 cpumMsrWr_AmdK8McCtlMaskN,
5393 cpumMsrWr_AmdK8SmiOnIoTrapN,
5394 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
5395 cpumMsrWr_AmdK8IntPendingMessage,
5396 cpumMsrWr_AmdK8SmiTriggerIoCycle,
5397 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
5398 cpumMsrWr_AmdFam10hTrapCtlMaybe,
5399 cpumMsrWr_AmdFam10hPStateControl,
5400 cpumMsrWr_AmdFam10hPStateStatus,
5401 cpumMsrWr_AmdFam10hPStateN,
5402 cpumMsrWr_AmdFam10hCofVidControl,
5403 cpumMsrWr_AmdFam10hCofVidStatus,
5404 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
5405 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
5406 cpumMsrWr_AmdK8SmmBase,
5407 cpumMsrWr_AmdK8SmmAddr,
5408 cpumMsrWr_AmdK8SmmMask,
5409 cpumMsrWr_AmdK8VmCr,
5410 cpumMsrWr_AmdK8IgnNe,
5411 cpumMsrWr_AmdK8SmmCtl,
5412 cpumMsrWr_AmdK8VmHSavePa,
5413 cpumMsrWr_AmdFam10hVmLockKey,
5414 cpumMsrWr_AmdFam10hSmmLockKey,
5415 cpumMsrWr_AmdFam10hLocalSmiStatus,
5416 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
5417 cpumMsrWr_AmdFam10hOsVisWrkStatus,
5418 cpumMsrWr_AmdFam16hL2IPerfCtlN,
5419 cpumMsrWr_AmdFam16hL2IPerfCtrN,
5420 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
5421 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
5422 cpumMsrWr_AmdK7MicrocodeCtl,
5423 cpumMsrWr_AmdK7ClusterIdMaybe,
5424 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
5425 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
5426 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
5427 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
5428 cpumMsrWr_AmdK8PatchLoader,
5429 cpumMsrWr_AmdK7DebugStatusMaybe,
5430 cpumMsrWr_AmdK7BHTraceBaseMaybe,
5431 cpumMsrWr_AmdK7BHTracePtrMaybe,
5432 cpumMsrWr_AmdK7BHTraceLimitMaybe,
5433 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
5434 cpumMsrWr_AmdK7FastFlushCountMaybe,
5435 cpumMsrWr_AmdK7NodeId,
5436 cpumMsrWr_AmdK7DrXAddrMaskN,
5437 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
5438 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
5439 cpumMsrWr_AmdK7LoadStoreCfg,
5440 cpumMsrWr_AmdK7InstrCacheCfg,
5441 cpumMsrWr_AmdK7DataCacheCfg,
5442 cpumMsrWr_AmdK7BusUnitCfg,
5443 cpumMsrWr_AmdK7DebugCtl2Maybe,
5444 cpumMsrWr_AmdFam15hFpuCfg,
5445 cpumMsrWr_AmdFam15hDecoderCfg,
5446 cpumMsrWr_AmdFam10hBusUnitCfg2,
5447 cpumMsrWr_AmdFam15hCombUnitCfg,
5448 cpumMsrWr_AmdFam15hCombUnitCfg2,
5449 cpumMsrWr_AmdFam15hCombUnitCfg3,
5450 cpumMsrWr_AmdFam15hExecUnitCfg,
5451 cpumMsrWr_AmdFam15hLoadStoreCfg2,
5452 cpumMsrWr_AmdFam10hIbsFetchCtl,
5453 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
5454 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
5455 cpumMsrWr_AmdFam10hIbsOpExecCtl,
5456 cpumMsrWr_AmdFam10hIbsOpRip,
5457 cpumMsrWr_AmdFam10hIbsOpData,
5458 cpumMsrWr_AmdFam10hIbsOpData2,
5459 cpumMsrWr_AmdFam10hIbsOpData3,
5460 cpumMsrWr_AmdFam10hIbsDcLinAddr,
5461 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
5462 cpumMsrWr_AmdFam10hIbsCtl,
5463 cpumMsrWr_AmdFam14hIbsBrTarget,
5464
5465 cpumMsrWr_Gim
5466};
5467
5468
5469/**
5470 * Looks up the range for the given MSR.
5471 *
5472 * @returns Pointer to the range if found, NULL if not.
5473 * @param pVM The cross context VM structure.
5474 * @param idMsr The MSR to look up.
5475 */
5476# ifndef IN_RING3
5477static
5478# endif
5479PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
5480{
5481 /*
5482 * Binary lookup.
5483 */
5484 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
5485 if (!cRanges)
5486 return NULL;
5487 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5488 for (;;)
5489 {
5490 uint32_t i = cRanges / 2;
5491 if (idMsr < paRanges[i].uFirst)
5492 {
5493 if (i == 0)
5494 break;
5495 cRanges = i;
5496 }
5497 else if (idMsr > paRanges[i].uLast)
5498 {
5499 i++;
5500 if (i >= cRanges)
5501 break;
5502 cRanges -= i;
5503 paRanges = &paRanges[i];
5504 }
5505 else
5506 {
5507 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
5508 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
5509 return &paRanges[i];
5510 }
5511 }
5512
5513# ifdef VBOX_STRICT
5514 /*
5515 * Linear lookup to verify the above binary search.
5516 */
5517 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
5518 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5519 while (cLeft-- > 0)
5520 {
5521 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
5522 {
5523 AssertFailed();
5524 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
5525 return cpumLookupMsrRange(pVM, pCur->uValue);
5526 return pCur;
5527 }
5528 pCur++;
5529 }
5530# endif
5531 return NULL;
5532}
5533
5534
5535/**
5536 * Query a guest MSR.
5537 *
5538 * The caller is responsible for checking privilege if the call is the result of
5539 * a RDMSR instruction. We'll do the rest.
5540 *
5541 * @retval VINF_SUCCESS on success.
5542 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
5543 * current context (raw-mode or ring-0).
5544 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
5545 * expected to take the appropriate actions. @a *puValue is set to 0.
5546 * @param pVCpu The cross context virtual CPU structure.
5547 * @param idMsr The MSR.
5548 * @param puValue Where to return the value.
5549 *
5550 * @remarks This will always return the right values, even when we're in the
5551 * recompiler.
5552 */
5553VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
5554{
5555 *puValue = 0;
5556
5557 VBOXSTRICTRC rcStrict;
5558 PVM pVM = pVCpu->CTX_SUFF(pVM);
5559 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5560 if (pRange)
5561 {
5562 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
5563 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5564
5565 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
5566 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5567
5568 STAM_COUNTER_INC(&pRange->cReads);
5569 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5570
5571 rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5572 if (rcStrict == VINF_SUCCESS)
5573 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5574 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5575 {
5576 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5577 STAM_COUNTER_INC(&pRange->cGps);
5578 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5579 }
5580#ifndef IN_RING3
5581 else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5582 Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5583#endif
5584 else
5585 {
5586 Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5587 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5588 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5589 Assert(rcStrict != VERR_EM_INTERPRETER);
5590 }
5591 }
5592 else
5593 {
5594 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5595 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5596 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5597 rcStrict = VERR_CPUM_RAISE_GP_0;
5598 }
5599 return rcStrict;
5600}
5601
5602
5603/**
5604 * Writes to a guest MSR.
5605 *
5606 * The caller is responsible for checking privilege if the call is the result of
5607 * a WRMSR instruction. We'll do the rest.
5608 *
5609 * @retval VINF_SUCCESS on success.
5610 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5611 * current context (raw-mode or ring-0).
5612 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5613 * appropriate actions.
5614 *
5615 * @param pVCpu The cross context virtual CPU structure.
5616 * @param idMsr The MSR id.
5617 * @param uValue The value to set.
5618 *
5619 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5620 * by calling this method. This makes sure we have current values and
5621 * that we trigger all the right actions when something changes.
5622 *
5623 * For performance reasons, this actually isn't entirely true for some
5624 * MSRs when in HM mode. The code here and in HM must be aware of
5625 * this.
5626 */
5627VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5628{
5629 VBOXSTRICTRC rcStrict;
5630 PVM pVM = pVCpu->CTX_SUFF(pVM);
5631 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5632 if (pRange)
5633 {
5634 STAM_COUNTER_INC(&pRange->cWrites);
5635 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5636
5637 if (!(uValue & pRange->fWrGpMask))
5638 {
5639 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5640 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5641
5642 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5643 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5644
5645 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5646 if (uValueAdjusted != uValue)
5647 {
5648 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5649 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5650 }
5651
5652 rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5653 if (rcStrict == VINF_SUCCESS)
5654 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5655 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5656 {
5657 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5658 STAM_COUNTER_INC(&pRange->cGps);
5659 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5660 }
5661#ifndef IN_RING3
5662 else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5663 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5664#endif
5665 else
5666 {
5667 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5668 idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5669 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5670 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5671 Assert(rcStrict != VERR_EM_INTERPRETER);
5672 }
5673 }
5674 else
5675 {
5676 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5677 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5678 STAM_COUNTER_INC(&pRange->cGps);
5679 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5680 rcStrict = VERR_CPUM_RAISE_GP_0;
5681 }
5682 }
5683 else
5684 {
5685 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5686 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5687 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5688 rcStrict = VERR_CPUM_RAISE_GP_0;
5689 }
5690 return rcStrict;
5691}
5692
5693
5694#if defined(VBOX_STRICT) && defined(IN_RING3)
5695/**
5696 * Performs some checks on the static data related to MSRs.
5697 *
5698 * @returns VINF_SUCCESS on success, error on failure.
5699 */
5700int cpumR3MsrStrictInitChecks(void)
5701{
5702#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5703 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5704#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5705 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5706
5707 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5708 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5709 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5710 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5711 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5712 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5713 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5714 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5715 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5716 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5717 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5718 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5719 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5720 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5721 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5722 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5723 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5724 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5725 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5726 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5727 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5728 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5729 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5730 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5731 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5732 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5733 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5734 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5735 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5736 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5737 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5738 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5739 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5740 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5741 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5742 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5743 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5744 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5745 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5746 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5747 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5748 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5749 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5750 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5751 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5752 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5753 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5754 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5755 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5756 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5757 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5758 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5759 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5760 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5761 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5762 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5763 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5764 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5765 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5766 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5767 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5768 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5769 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5770 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5771 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5772 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5773 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5774 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5775 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5776 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5777 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc);
5778 CPUM_ASSERT_RD_MSR_FN(Ia32SpecCtrl);
5779 CPUM_ASSERT_RD_MSR_FN(Ia32ArchCapabilities);
5780
5781 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5782 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5783 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5784 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5785 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5786 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5787 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5788 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5789 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5790
5791 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5792 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5793 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5794 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5795 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5796 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5797 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5798 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5799 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5800 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5801 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5802 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5803 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5804 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5805 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5806 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5807 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5808 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5809 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5810 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5811 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5812 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5813 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5814 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5815 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5816 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5817 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5818 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5819 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5820 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5821 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5822 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5823 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5824 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5825 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5826 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5827 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5828 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5829 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5830 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5831 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5832 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5833 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5834 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5835 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5836 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5837 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5838 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5839 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5840 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5841 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5842 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5843 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5844 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5845 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5846 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5847 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5848 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5849 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5850 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5851 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5852 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5853 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5854 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5855 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5856 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5857 CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount);
5858 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5859 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5860 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5861 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5862 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5863 CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency);
5864
5865 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5866 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5867 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5868 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5869
5870 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5871 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5872 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5873 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5874 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5875 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5876 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5877 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5878 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5879 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5880 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5881 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5882 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5883 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5884 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5885 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5886 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5887 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5888 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5889 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5890 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5891 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5892 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5893 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5894 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5895 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5896 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5897 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5898 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5899 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5900 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5901 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5902 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5903 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5904 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5905 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5906 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5907 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5908 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5909 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5910 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5911 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5912 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5913 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5914 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5915 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5916 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5917 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5918 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5919 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5920 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5921 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5922 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5923 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5924 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5925 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5926 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5927 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5928 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5929 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5930 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5931 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5932 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5933 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5934 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5935 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5936 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5937 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5938 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5939 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5940 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5941 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5942 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5943 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5944 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5945 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5946 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5947 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5948 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5949 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5950 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5951 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5952 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5953 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5954 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5955 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5956 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5957 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5958 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5959 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5960 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5961
5962 CPUM_ASSERT_RD_MSR_FN(Gim)
5963
5964 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5965 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5966 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5967 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5968 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5969 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5970 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5971 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5972 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5973 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5974 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5975 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5976 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5977 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5978 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5979 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5980 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5981 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5982 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5983 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5984 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5985 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5986 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5987 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5988 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5989 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5990 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5991 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5992 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5993 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5994 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5995 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5996 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5997 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5998 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5999 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
6000 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
6001 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
6002 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
6003 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
6004 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
6005 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
6006 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
6007 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
6008 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
6009 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
6010 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
6011 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
6012 CPUM_ASSERT_WR_MSR_FN(Ia32SpecCtrl);
6013 CPUM_ASSERT_WR_MSR_FN(Ia32PredCmd);
6014
6015 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
6016 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
6017 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
6018 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
6019 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
6020 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
6021 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
6022 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
6023 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
6024
6025 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
6026 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
6027 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
6028 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
6029 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
6030 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
6031 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
6032 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
6033 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
6034 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
6035 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
6036 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
6037 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
6038 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
6039 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
6040 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
6041 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
6042 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6043 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
6044 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6045 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
6046 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
6047 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
6048 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
6049 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
6050 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
6051 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
6052 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
6053 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
6054 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
6055 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency);
6056 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
6057 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
6058 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
6059 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
6060 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
6061 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
6062 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
6063 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
6064 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
6065 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
6066 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6067 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6068 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
6069 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
6070 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
6071 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
6072 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
6073 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
6074 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
6075 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
6076
6077 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
6078 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
6079
6080 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
6081 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
6082 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
6083 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
6084 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
6085 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
6086 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
6087 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
6088 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
6089 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
6090 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
6091 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
6092 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
6093 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
6094 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
6095 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
6096 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
6097 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
6098 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
6099 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6100 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
6101 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
6102 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6103 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
6104 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
6105 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
6106 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
6107 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
6108 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
6109 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
6110 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
6111 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
6112 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
6113 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
6114 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
6115 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
6116 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
6117 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
6118 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
6119 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
6120 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
6121 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
6122 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
6123 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
6124 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
6125 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6126 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6127 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
6128 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
6129 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6130 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6131 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6132 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6133 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
6134 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
6135 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
6136 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
6137 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
6138 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6139 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
6140 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
6141 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
6142 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
6143 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
6144 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
6145 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
6146 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
6147 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
6148 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
6149 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
6150 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
6151 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
6152 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
6153 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
6154 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
6155 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
6156 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
6157 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
6158 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
6159 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6160 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
6161 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
6162 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
6163 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
6164 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
6165 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
6166 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
6167 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
6168 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
6169
6170 CPUM_ASSERT_WR_MSR_FN(Gim);
6171
6172 return VINF_SUCCESS;
6173}
6174#endif /* VBOX_STRICT && IN_RING3 */
6175
6176
6177/**
6178 * Gets the scalable bus frequency.
6179 *
6180 * The bus frequency is used as a base in several MSRs that gives the CPU and
6181 * other frequency ratios.
6182 *
6183 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
6184 * @param pVM The cross context VM structure.
6185 */
6186VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
6187{
6188 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
6189 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
6190 uFreq = CPUM_SBUSFREQ_100MHZ;
6191 return uFreq;
6192}
6193
6194
6195/**
6196 * Sets the guest EFER MSR without performing any additional checks.
6197 *
6198 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6199 * @param uOldEfer The previous EFER MSR value.
6200 * @param uValidEfer The new, validated EFER MSR value.
6201 *
6202 * @remarks One would normally call CPUMQueryValidatedGuestEfer before calling this
6203 * function to change the EFER in order to perform an EFER transition.
6204 */
6205VMMDECL(void) CPUMSetGuestMsrEferNoCheck(PVMCPU pVCpu, uint64_t uOldEfer, uint64_t uValidEfer)
6206{
6207 pVCpu->cpum.s.Guest.msrEFER = uValidEfer;
6208
6209 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
6210 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
6211 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
6212 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
6213 {
6214 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
6215 HMFlushTLB(pVCpu);
6216
6217 /* Notify PGM about NXE changes. */
6218 if ( (uOldEfer & MSR_K6_EFER_NXE)
6219 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
6220 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
6221 }
6222}
6223
6224
6225/**
6226 * Checks if a guest PAT MSR write is valid.
6227 *
6228 * @returns @c true if the PAT bit combination is valid, @c false otherwise.
6229 * @param uValue The PAT MSR value.
6230 */
6231VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue)
6232{
6233 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
6234 {
6235 /* Check all eight bits because the top 5 bits of each byte are reserved. */
6236 uint8_t uType = (uint8_t)(uValue >> cShift);
6237 if ((uType >= 8) || (uType == 2) || (uType == 3))
6238 {
6239 Log(("CPUM: Invalid PAT type at %u:%u in IA32_PAT: %#llx (%#llx)\n", cShift + 7, cShift, uValue, uType));
6240 return false;
6241 }
6242 }
6243 return true;
6244}
6245
6246
6247/**
6248 * Validates an EFER MSR write.
6249 *
6250 * @returns VBox status code.
6251 * @param pVM The cross context VM structure.
6252 * @param uCr0 The CR0 of the CPU corresponding to the EFER MSR.
6253 * @param uOldEfer Value of the previous EFER MSR on the CPU if any.
6254 * @param uNewEfer The new EFER MSR value being written.
6255 * @param puValidEfer Where to store the validated EFER (only updated if
6256 * this function returns VINF_SUCCESS).
6257 */
6258VMMDECL(int) CPUMQueryValidatedGuestEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer, uint64_t *puValidEfer)
6259{
6260 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
6261 ? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
6262 : 0;
6263 uint64_t fMask = 0;
6264 uint64_t const fIgnoreMask = MSR_K6_EFER_LMA;
6265
6266 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
6267 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
6268 fMask |= MSR_K6_EFER_NXE;
6269 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
6270 fMask |= MSR_K6_EFER_LME;
6271 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
6272 fMask |= MSR_K6_EFER_SCE;
6273 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
6274 fMask |= MSR_K6_EFER_FFXSR;
6275 if (pVM->cpum.s.GuestFeatures.fSvm)
6276 fMask |= MSR_K6_EFER_SVME;
6277
6278 /* #GP(0) If anything outside the allowed bits is set. */
6279 if (uNewEfer & ~(fIgnoreMask | fMask))
6280 {
6281 Log(("CPUM: Settings disallowed EFER bit. uNewEfer=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uNewEfer, fMask));
6282 return VERR_CPUM_RAISE_GP_0;
6283 }
6284
6285 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
6286 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6287 if ( (uOldEfer & MSR_K6_EFER_LME) != (uNewEfer & fMask & MSR_K6_EFER_LME)
6288 && (uCr0 & X86_CR0_PG))
6289 {
6290 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
6291 return VERR_CPUM_RAISE_GP_0;
6292 }
6293
6294 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
6295 AssertMsg(!(uNewEfer & ~( MSR_K6_EFER_NXE
6296 | MSR_K6_EFER_LME
6297 | MSR_K6_EFER_LMA /* ignored anyway */
6298 | MSR_K6_EFER_SCE
6299 | MSR_K6_EFER_FFXSR
6300 | MSR_K6_EFER_SVME)),
6301 ("Unexpected value %#RX64\n", uNewEfer));
6302
6303 *puValidEfer = (uOldEfer & ~fMask) | (uNewEfer & fMask);
6304 return VINF_SUCCESS;
6305}
6306
6307
6308/**
6309 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6310 *
6311 * @returns The register value.
6312 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6313 * @thread EMT(pVCpu)
6314 */
6315VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPU pVCpu)
6316{
6317 Assert(!(pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_TSC_AUX));
6318 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
6319}
6320
6321
6322/**
6323 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6324 *
6325 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6326 * @param uValue The new value.
6327 * @thread EMT(pVCpu)
6328 */
6329VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
6330{
6331 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_TSC_AUX;
6332 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
6333}
6334
6335
6336/**
6337 * Fast way for HM to access the IA32_SPEC_CTRL register.
6338 *
6339 * @returns The register value.
6340 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6341 * @thread EMT(pVCpu)
6342 */
6343VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPU pVCpu)
6344{
6345 return pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
6346}
6347
6348
6349/**
6350 * Fast way for HM to access the IA32_SPEC_CTRL register.
6351 *
6352 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6353 * @param uValue The new value.
6354 * @thread EMT(pVCpu)
6355 */
6356VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPU pVCpu, uint64_t uValue)
6357{
6358 pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
6359}
6360
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